Angus Gratton 17adb40ca8 bootloader: Calculate SHA256 hash of image on every boot ... Makes app image booting more reliable (256-bit rather than 8-bit verification.) Some measurements, time to boot a 655KB app.bin file and run to app_main() execution. (All for rev 1 silicon, ie no 340ms spurious WDT delay.) 80MHz QIO mode: before = 300ms after = 140ms 40MHz DIO mode: before = 712ms after = 577ms 40MHz DIO mode, secure boot enabled before = 1380ms after = 934ms (Secure boot involves two ECC signature verifications (partition table, app) that take approx 300ms each with 80MHz CPU.)		2017-07-19 18:31:59 +10:00
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include/soc	bootloader: Calculate SHA256 hash of image on every boot	2017-07-19 18:31:59 +10:00
test	soc: implement XTAL frequency detection	2017-04-24 15:29:30 +08:00
cpu_util.c	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
i2c_apll.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
i2c_bbpll.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
i2c_rtc_clk.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
rtc_clk.c	component/soc : move dport access header files to soc	2017-05-09 18:06:00 +08:00
rtc_init.c	soc: fix typo in register name	2017-07-06 12:36:06 +08:00
rtc_pm.c	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
rtc_sleep.c	component/soc : move dport access header files to soc	2017-05-09 18:06:00 +08:00
rtc_time.c	Add support for 32k XTAL as RTC_SLOW_CLK source	2017-04-26 12:43:22 +08:00
soc_log.h	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
soc_memory_layout.c	heap: Rename memory "tags" to "types" to avoid confusion w/ old tag allocator API	2017-07-10 17:46:03 +08:00