571864e8ae
There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
43 lines
1.3 KiB
CMake
43 lines
1.3 KiB
CMake
set(priv_requires bootloader_support soc)
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if(BOOTLOADER_BUILD)
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# Bootloader needs SPIUnlock from this file, but doesn't
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# need other parts of this component
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set(srcs "spi_flash_rom_patch.c")
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set(cache_srcs "")
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else()
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set(cache_srcs
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"cache_utils.c"
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"flash_mmap.c"
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"flash_ops.c"
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)
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set(srcs
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"partition.c"
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"spi_flash_rom_patch.c"
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)
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# New implementation
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list(APPEND cache_srcs
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"esp_flash_api.c"
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"esp_flash_spi_init.c"
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"spi_flash_os_func_app.c"
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"spi_flash_os_func_noos.c"
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)
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list(APPEND srcs
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"spi_flash_chip_drivers.c"
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"spi_flash_chip_generic.c"
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"spi_flash_chip_issi.c"
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"memspi_host_driver.c"
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)
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list(APPEND srcs ${cache_srcs})
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set(priv_requires bootloader_support app_update soc)
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endif()
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idf_component_register(SRCS "${srcs}"
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PRIV_REQUIRES "${priv_requires}"
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INCLUDE_DIRS include
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PRIV_INCLUDE_DIRS private_include
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LDFRAGMENTS linker.lf)
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# Avoid cache miss by unexpected inlineing when built by -Os
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set_source_files_properties(${cache_srcs} PROPERTIES COMPILE_FLAGS
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"-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once")
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