Ivan Grokhotkov 1618dbc9a5 soc/rtc: wait for frequency switch to complete ... The fast path of CPU frequency switch function, used in DFS, was not waiting for the frequency switch to complete when switching from XTAL to PLL. This resulted in incorrect reads from peripherals on APB, where two consecutive reads could return the same value. For example, in esp_timer, read of FRC_COUNT_REG would return same value as the preceding read of FRC_ALARM_REG, causing time to jump by the value of FRC_ALARM_REG / apb_freq_mhz.		2018-03-20 18:27:32 +08:00
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esp32	soc/rtc: wait for frequency switch to complete	2018-03-20 18:27:32 +08:00
include/soc	Especially when internal memory fills up, some FreeRTOS structures (queues etc) get allocated in psram. These structures also contain a spinlock, which needs an atomic-compare-swap operation to work. The psram hardware, however, does not support this operation. As a workaround, this patch detects these spinlocks and will, instead of S32C1I, use equivalent C-code to simulate the behaviour, with an (internal) mux for atomicity.	2018-02-02 17:11:06 +08:00
test	soc: add source code of rtc_clk, rtc_pm	2017-04-11 15:45:54 +08:00
component.mk	Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet.	2017-09-04 12:05:49 +08:00