659 lines
29 KiB
C
659 lines
29 KiB
C
/*
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Driver bits for PSRAM chips (at the moment only the ESP-PSRAM32 chip).
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*/
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// Copyright 2013-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "spiram_psram.h"
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#include "rom/ets_sys.h"
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#include "rom/spi_flash.h"
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#include "rom/gpio.h"
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#include "rom/cache.h"
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/efuse_reg.h"
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#include "driver/gpio.h"
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#include "driver/spi_common.h"
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#if CONFIG_SPIRAM_SUPPORT
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//Commands for PSRAM chip
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#define PSRAM_READ 0x03
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#define PSRAM_FAST_READ 0x0B
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#define PSRAM_FAST_READ_DUMMY 0x3
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#define PSRAM_FAST_READ_QUAD 0xEB
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#define PSRAM_WRITE 0x02
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#define PSRAM_QUAD_WRITE 0x38
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#define PSRAM_ENTER_QMODE 0x35
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#define PSRAM_EXIT_QMODE 0xF5
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#define PSRAM_RESET_EN 0x66
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#define PSRAM_RESET 0x99
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#define PSRAM_SET_BURST_LEN 0xC0
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#define PSRAM_DEVICE_ID 0x9F
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#if CONFIG_SPIRAM_TYPE_ESPPSRAM32
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#define PSRAM_MFG_ID_M 0xff
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#define PSRAM_MFG_ID_S 8
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#define PSRAM_MFG_ID_V 0x5d
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#endif
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// IO-pins for PSRAM. These need to be in the VDD_SIO power domain because all chips we
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// currently support are 1.8V parts.
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// WARNING: PSRAM shares all but the CS and CLK pins with the flash, so these defines
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// hardcode the flash pins as well, making this code incompatible with either a setup
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// that has the flash on non-standard pins or ESP32s with built-in flash.
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#define FLASH_CLK_IO 6 //Psram clock is a delayed version of this in 40MHz mode
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#define FLASH_CS_IO 11
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#define PSRAM_CLK_IO 17
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#define PSRAM_CS_IO 16
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#define PSRAM_SPIQ_IO 7
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#define PSRAM_SPID_IO 8
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#define PSRAM_SPIWP_IO 10
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#define PSRAM_SPIHD_IO 9
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#define PSRAM_INTERNAL_IO_28 28
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#define PSRAM_INTERNAL_IO_29 29
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#define PSRAM_IO_MATRIX_DUMMY_40M 1
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#define PSRAM_IO_MATRIX_DUMMY_80M 2
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#if CONFIG_FLASHMODE_QIO
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#define SPI_CACHE_DUMMY SPI0_R_QIO_DUMMY_CYCLELEN //qio 3
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#elif CONFIG_FLASHMODE_QOUT
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#define SPI_CACHE_DUMMY SPI0_R_FAST_DUMMY_CYCLELEN //qout 7
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#elif CONFIG_FLASHMODE_DIO
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#define SPI_CACHE_DUMMY SPI0_R_DIO_DUMMY_CYCLELEN //dio 3
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#elif CONFIG_FLASHMODE_DOUT
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#define SPI_CACHE_DUMMY SPI0_R_FAST_DUMMY_CYCLELEN //dout 7
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#endif
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static const char* TAG = "psram";
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typedef enum {
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PSRAM_SPI_1 = 0x1,
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PSRAM_SPI_2,
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PSRAM_SPI_3,
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PSRAM_SPI_MAX ,
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} psram_spi_num_t;
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static psram_cache_mode_t s_psram_mode = PSRAM_CACHE_MAX;
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/* dummy_len_plus values defined in ROM for SPI flash configuration */
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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static int extra_dummy = 0;
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typedef enum {
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PSRAM_CMD_QPI,
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PSRAM_CMD_SPI,
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} psram_cmd_mode_t;
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typedef struct {
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uint16_t cmd; /*!< Command value */
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uint16_t cmdBitLen; /*!< Command byte length*/
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uint32_t *addr; /*!< Point to address value*/
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uint16_t addrBitLen; /*!< Address byte length*/
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uint32_t *txData; /*!< Point to send data buffer*/
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uint16_t txDataBitLen; /*!< Send data byte length.*/
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uint32_t *rxData; /*!< Point to recevie data buffer*/
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uint16_t rxDataBitLen; /*!< Recevie Data byte length.*/
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uint32_t dummyBitLen;
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} psram_cmd_t;
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode);
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static void psram_clear_spi_fifo(psram_spi_num_t spi_num)
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{
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int i;
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for (i = 0; i < 16; i++) {
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WRITE_PERI_REG(SPI_W0_REG(spi_num)+i*4, 0);
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}
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}
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//set basic SPI write mode
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static void psram_set_basic_write_mode(psram_spi_num_t spi_num)
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{
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
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}
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//set QPI write mode
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static void psram_set_qio_write_mode(psram_spi_num_t spi_num)
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{
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DIO);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_QUAD);
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_FWRITE_DUAL);
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}
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//set QPI read mode
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static void psram_set_qio_read_mode(psram_spi_num_t spi_num)
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{
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SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
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}
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//set SPI read mode
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static void psram_set_basic_read_mode(psram_spi_num_t spi_num)
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{
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QIO);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_QUAD);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DUAL);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_FREAD_DIO);
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}
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//start sending cmd/addr and optionally, receiving data
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static void IRAM_ATTR psram_cmd_recv_start(psram_spi_num_t spi_num, uint32_t* pRxData, uint16_t rxByteLen,
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psram_cmd_mode_t cmd_mode)
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{
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//get cs1
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
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uint32_t mode_backup = (READ_PERI_REG(SPI_USER_REG(spi_num)) >> SPI_FWRITE_DUAL_S) & 0xf;
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uint32_t rd_mode_backup = READ_PERI_REG(SPI_CTRL_REG(spi_num)) & (SPI_FREAD_DIO_M | SPI_FREAD_DUAL_M | SPI_FREAD_QUAD_M | SPI_FREAD_QIO_M);
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if (cmd_mode == PSRAM_CMD_SPI) {
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psram_set_basic_write_mode(spi_num);
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psram_set_basic_read_mode(spi_num);
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} else if (cmd_mode == PSRAM_CMD_QPI) {
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psram_set_qio_write_mode(spi_num);
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psram_set_qio_read_mode(spi_num);
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}
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//Wait for SPI0 to idle
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while ( READ_PERI_REG(SPI_EXT2_REG(0)) != 0);
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DPORT_SET_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
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// Start send data
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SET_PERI_REG_MASK(SPI_CMD_REG(spi_num), SPI_USR);
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while ((READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR));
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DPORT_CLEAR_PERI_REG_MASK(DPORT_HOST_INF_SEL_REG, 1 << 14);
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//recover spi mode
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SET_PERI_REG_BITS(SPI_USER_REG(spi_num), (pRxData?SPI_FWRITE_DUAL_M:0xf), mode_backup, SPI_FWRITE_DUAL_S);
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CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), (SPI_FREAD_DIO_M|SPI_FREAD_DUAL_M|SPI_FREAD_QUAD_M|SPI_FREAD_QIO_M));
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SET_PERI_REG_MASK(SPI_CTRL_REG(spi_num), rd_mode_backup);
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//return cs to cs0
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SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS1_DIS_M);
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1), SPI_CS0_DIS_M);
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if (pRxData) {
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int idx = 0;
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// Read data out
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do {
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*pRxData++ = READ_PERI_REG(SPI_W0_REG(spi_num) + (idx << 2));
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} while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0)));
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}
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}
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static uint32_t backup_usr[3];
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static uint32_t backup_usr1[3];
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static uint32_t backup_usr2[3];
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//setup spi command/addr/data/dummy in user mode
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static int psram_cmd_config(psram_spi_num_t spi_num, psram_cmd_t* pInData)
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{
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while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
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backup_usr[spi_num]=READ_PERI_REG(SPI_USER_REG(spi_num));
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backup_usr1[spi_num]=READ_PERI_REG(SPI_USER1_REG(spi_num));
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backup_usr2[spi_num]=READ_PERI_REG(SPI_USER2_REG(spi_num));
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// Set command by user.
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if (pInData->cmdBitLen != 0) {
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// Max command length 16 bits.
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SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, pInData->cmdBitLen - 1,
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SPI_USR_COMMAND_BITLEN_S);
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// Enable command
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
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// Load command,bit15-0 is cmd value.
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SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_VALUE, pInData->cmd, SPI_USR_COMMAND_VALUE_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_COMMAND);
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SET_PERI_REG_BITS(SPI_USER2_REG(spi_num), SPI_USR_COMMAND_BITLEN, 0, SPI_USR_COMMAND_BITLEN_S);
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}
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// Set Address by user.
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if (pInData->addrBitLen != 0) {
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SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, (pInData->addrBitLen - 1), SPI_USR_ADDR_BITLEN_S);
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// Enable address
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
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// Set address
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WRITE_PERI_REG(SPI_ADDR_REG(spi_num), *pInData->addr);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_ADDR);
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SET_PERI_REG_BITS(SPI_USER1_REG(spi_num), SPI_USR_ADDR_BITLEN, 0, SPI_USR_ADDR_BITLEN_S);
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}
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// Set data by user.
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uint32_t* p_tx_val = pInData->txData;
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if (pInData->txDataBitLen != 0) {
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// Enable MOSI
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
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// Load send buffer
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int len = (pInData->txDataBitLen + 31) / 32;
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if (p_tx_val != NULL) {
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memcpy((void*)SPI_W0_REG(spi_num), p_tx_val, len * 4);
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}
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// Set data send buffer length.Max data length 64 bytes.
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SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1),
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SPI_USR_MOSI_DBITLEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);
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SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spi_num), SPI_USR_MOSI_DBITLEN, 0, SPI_USR_MOSI_DBITLEN_S);
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}
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// Set rx data by user.
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if (pInData->rxDataBitLen != 0) {
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// Enable MOSI
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
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// Set data send buffer length.Max data length 64 bytes.
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SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen - 1),
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SPI_USR_MISO_DBITLEN_S);
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);
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SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spi_num), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S);
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}
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if (pInData->dummyBitLen != 0) {
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SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
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SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, pInData->dummyBitLen - 1,
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SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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} else {
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CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_DUMMY); // dummy en
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SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1), SPI_USR_DUMMY_CYCLELEN_V, 0, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
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}
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return 0;
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}
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void psram_cmd_end(int spi_num) {
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while (READ_PERI_REG(SPI_CMD_REG(spi_num)) & SPI_USR);
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WRITE_PERI_REG(SPI_USER_REG(spi_num), backup_usr[spi_num]);
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WRITE_PERI_REG(SPI_USER1_REG(spi_num), backup_usr1[spi_num]);
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WRITE_PERI_REG(SPI_USER2_REG(spi_num), backup_usr2[spi_num]);
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}
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//exit QPI mode(set back to SPI mode)
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static void psram_disable_qio_mode(psram_spi_num_t spi_num)
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{
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psram_cmd_t ps_cmd;
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uint32_t cmd_exit_qpi;
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switch (s_psram_mode) {
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case PSRAM_CACHE_F80M_S80M:
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cmd_exit_qpi = PSRAM_EXIT_QMODE;
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ps_cmd.txDataBitLen = 8;
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break;
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case PSRAM_CACHE_F80M_S40M:
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case PSRAM_CACHE_F40M_S40M:
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default:
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cmd_exit_qpi = PSRAM_EXIT_QMODE << 8;
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ps_cmd.txDataBitLen = 16;
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break;
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}
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ps_cmd.txData = &cmd_exit_qpi;
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ps_cmd.cmd = 0;
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ps_cmd.cmdBitLen = 0;
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ps_cmd.addr = 0;
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ps_cmd.addrBitLen = 0;
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ps_cmd.rxData = NULL;
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ps_cmd.rxDataBitLen = 0;
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ps_cmd.dummyBitLen = 0;
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psram_cmd_config(spi_num, &ps_cmd);
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psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_QPI);
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psram_cmd_end(spi_num);
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}
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//read psram id
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static void psram_read_id(uint32_t* dev_id)
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{
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psram_spi_num_t spi_num = PSRAM_SPI_1;
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psram_disable_qio_mode(spi_num);
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uint32_t addr = (PSRAM_DEVICE_ID << 24) | 0;
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uint32_t dummy_bits = 0;
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psram_cmd_t ps_cmd;
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switch (s_psram_mode) {
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case PSRAM_CACHE_F80M_S80M:
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dummy_bits = 0 + extra_dummy;
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ps_cmd.cmdBitLen = 0;
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break;
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case PSRAM_CACHE_F80M_S40M:
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case PSRAM_CACHE_F40M_S40M:
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default:
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dummy_bits = 0 + extra_dummy;
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ps_cmd.cmdBitLen = 2; //this two bits is used to delay 2 clock cycle
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break;
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}
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ps_cmd.cmd = 0;
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ps_cmd.addr = &addr;
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ps_cmd.addrBitLen = 4 * 8;
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ps_cmd.txDataBitLen = 0;
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ps_cmd.txData = NULL;
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ps_cmd.rxDataBitLen = 4 * 8;
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ps_cmd.rxData = dev_id;
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ps_cmd.dummyBitLen = dummy_bits;
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psram_cmd_config(spi_num, &ps_cmd);
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psram_clear_spi_fifo(spi_num);
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psram_cmd_recv_start(spi_num, ps_cmd.rxData, ps_cmd.rxDataBitLen / 8, PSRAM_CMD_SPI);
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psram_cmd_end(spi_num);
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}
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//enter QPI mode
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static esp_err_t IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spi_num)
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{
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psram_cmd_t ps_cmd;
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uint32_t addr = (PSRAM_ENTER_QMODE << 24) | 0;
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switch (s_psram_mode) {
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case PSRAM_CACHE_F80M_S80M:
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ps_cmd.cmdBitLen = 0;
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break;
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case PSRAM_CACHE_F80M_S40M:
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case PSRAM_CACHE_F40M_S40M:
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default:
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ps_cmd.cmdBitLen = 2;
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break;
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}
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ps_cmd.cmd = 0;
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ps_cmd.addr = &addr;
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ps_cmd.addrBitLen = 8;
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ps_cmd.txData = NULL;
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ps_cmd.txDataBitLen = 0;
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ps_cmd.rxData = NULL;
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ps_cmd.rxDataBitLen = 0;
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ps_cmd.dummyBitLen = 0;
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psram_cmd_config(spi_num, &ps_cmd);
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psram_cmd_recv_start(spi_num, NULL, 0, PSRAM_CMD_SPI);
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psram_cmd_end(spi_num);
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return ESP_OK;
|
|
}
|
|
|
|
//spi param init for psram
|
|
void IRAM_ATTR psram_spi_init(psram_spi_num_t spi_num, psram_cache_mode_t mode)
|
|
{
|
|
uint8_t i, k;
|
|
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_TRANS_DONE << 5);
|
|
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_SETUP);
|
|
// SPI_CPOL & SPI_CPHA
|
|
CLEAR_PERI_REG_MASK(SPI_PIN_REG(spi_num), SPI_CK_IDLE_EDGE);
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CK_OUT_EDGE);
|
|
// SPI bit order
|
|
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_WR_BIT_ORDER);
|
|
CLEAR_PERI_REG_MASK(SPI_CTRL_REG(spi_num), SPI_RD_BIT_ORDER);
|
|
// SPI bit order
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_DOUTDIN);
|
|
// May be not must to do.
|
|
WRITE_PERI_REG(SPI_USER1_REG(spi_num), 0);
|
|
// SPI mode type
|
|
CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_SLAVE_MODE);
|
|
// Set SPI speed for non-80M mode. (80M mode uses APB clock directly.)
|
|
if (mode!=PSRAM_CACHE_F80M_S80M) {
|
|
i = 1; //Pre-divider
|
|
k = 2; //Main divider. Divide by 2 so we get 40MHz
|
|
//clear bit 31, set SPI clock div
|
|
CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(spi_num), SPI_CLK_EQU_SYSCLK);
|
|
WRITE_PERI_REG(SPI_CLOCK_REG(spi_num),
|
|
(((i - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) |
|
|
(((k - 1) & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) |
|
|
((((k + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) | //50% duty cycle
|
|
(((k - 1) & SPI_CLKCNT_L) << SPI_CLKCNT_L_S));
|
|
}
|
|
// Enable MOSI
|
|
SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI);
|
|
memset((void*)SPI_W0_REG(spi_num), 0, 16 * 4);
|
|
}
|
|
|
|
static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode)
|
|
{
|
|
gpio_matrix_out(FLASH_CS_IO, SPICS0_OUT_IDX, 0, 0);
|
|
gpio_matrix_out(PSRAM_SPIQ_IO, SPIQ_OUT_IDX, 0, 0);
|
|
gpio_matrix_in(PSRAM_SPIQ_IO, SPIQ_IN_IDX, 0);
|
|
gpio_matrix_out(PSRAM_SPID_IO, SPID_OUT_IDX, 0, 0);
|
|
gpio_matrix_in(PSRAM_SPID_IO, SPID_IN_IDX, 0);
|
|
gpio_matrix_out(PSRAM_SPIWP_IO, SPIWP_OUT_IDX, 0, 0);
|
|
gpio_matrix_in(PSRAM_SPIWP_IO, SPIWP_IN_IDX, 0);
|
|
gpio_matrix_out(PSRAM_SPIHD_IO, SPIHD_OUT_IDX, 0, 0);
|
|
gpio_matrix_in(PSRAM_SPIHD_IO, SPIHD_IN_IDX, 0);
|
|
|
|
switch (mode) {
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
//set drive ability for clock
|
|
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], FUN_DRV, 2, FUN_DRV_S);
|
|
break;
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_80M;
|
|
g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_80M;
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_80M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
//set drive ability for clock
|
|
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3, FUN_DRV_S);
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], FUN_DRV, 3, FUN_DRV_S);
|
|
break;
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
extra_dummy = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
g_rom_spiflash_dummy_len_plus[1] = PSRAM_IO_MATRIX_DUMMY_40M;
|
|
SET_PERI_REG_BITS(SPI_USER1_REG(0), SPI_USR_DUMMY_CYCLELEN_V, SPI_CACHE_DUMMY + PSRAM_IO_MATRIX_DUMMY_40M, SPI_USR_DUMMY_CYCLELEN_S); //DUMMY
|
|
//set drive ability for clock
|
|
SET_PERI_REG_BITS(PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 2, FUN_DRV_S);
|
|
SET_PERI_REG_BITS(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], FUN_DRV, 2, FUN_DRV_S);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
SET_PERI_REG_MASK(SPI_USER_REG(0), SPI_USR_DUMMY); // dummy en
|
|
|
|
//select pin function gpio
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U, PIN_FUNC_GPIO);
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U, PIN_FUNC_GPIO);
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U, PIN_FUNC_GPIO);
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U, PIN_FUNC_GPIO);
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CMD_U, PIN_FUNC_GPIO);
|
|
//flash clock signal should come from IO MUX.
|
|
PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U, FUNC_SD_CLK_SPICLK);
|
|
}
|
|
|
|
//psram gpio init , different working frequency we have different solutions
|
|
esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode, psram_vaddr_mode_t vaddrmode) //psram init
|
|
{
|
|
uint32_t chip_ver = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
|
|
uint32_t pkg_ver = chip_ver & 0x7;
|
|
if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32D2WDQ5) {
|
|
ESP_EARLY_LOGE(TAG, "ESP32D2WD do not support psram yet");
|
|
return ESP_FAIL;
|
|
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD2) {
|
|
ESP_EARLY_LOGE(TAG, "ESP32PICOD2 do not support psram yet");
|
|
return ESP_FAIL;
|
|
} else if (pkg_ver == EFUSE_RD_CHIP_VER_PKG_ESP32PICOD4) {
|
|
ESP_EARLY_LOGE(TAG, "ESP32PICOD4 do not support psram yet");
|
|
return ESP_FAIL;
|
|
}
|
|
|
|
/* note: If the third mode(80Mhz+80Mhz) is enabled, VSPI port will be occupied by the system,
|
|
Application code should never touch VSPI hardware in this case. We try to stop applications
|
|
from doing this using the drivers by claiming the port for ourselves*/
|
|
if (mode == PSRAM_CACHE_F80M_S80M) {
|
|
bool r=spicommon_periph_claim(VSPI_HOST);
|
|
if (!r) {
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
}
|
|
|
|
WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG, BIT(PSRAM_CLK_IO) | BIT(PSRAM_CS_IO)); //DISABLE OUPUT FOR IO16/17
|
|
assert(mode < PSRAM_CACHE_MAX && "we don't support any other mode for now.");
|
|
s_psram_mode = mode;
|
|
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN);
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST);
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_1);
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_1);
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, DPORT_SPI_CLK_EN_2);
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_RST_2);
|
|
|
|
WRITE_PERI_REG(SPI_EXT3_REG(0), 0x1);
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M);
|
|
|
|
switch (mode) {
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
psram_spi_init(PSRAM_SPI_1, mode);
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD);
|
|
gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
|
|
gpio_matrix_out(PSRAM_CLK_IO, VSPICLK_OUT_IDX, 0, 0);
|
|
//use spi3 clock,but use spi1 data/cs wires
|
|
WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_3), 32 << 24);
|
|
WRITE_PERI_REG(SPI_CLOCK_REG(PSRAM_SPI_3), SPI_CLK_EQU_SYSCLK_M); //SET 80M AND CLEAR OTHERS
|
|
SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_3), SPI_FLASH_READ_M);
|
|
uint32_t spi_status;
|
|
while (1) {
|
|
spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_3));
|
|
if (spi_status != 0 && spi_status != 1) {
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG, BIT(PSRAM_CS_IO)); //DPORT_SPI_CLK_EN
|
|
break;
|
|
}
|
|
}
|
|
break;
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
default:
|
|
psram_spi_init(PSRAM_SPI_1, mode);
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD);
|
|
gpio_matrix_out(PSRAM_CS_IO, SPICS1_OUT_IDX, 0, 0);
|
|
/* We need to delay CLK to the PSRAM with respect to the clock signal as output by the SPI peripheral.
|
|
We do this by routing it signal to signal 224/225, which are used as a loopback; the extra run through
|
|
the GPIO matrix causes the delay. We use GPIO20 (which is not in any package but has pad logic in
|
|
silicon) as a temporary pad for this. So the signal path is:
|
|
SPI CLK --> GPIO28 --> signal224(in then out) --> internal GPIO29 --> signal225(in then out) --> GPIO17(PSRAM CLK)
|
|
*/
|
|
gpio_matrix_out(PSRAM_INTERNAL_IO_28, SPICLK_OUT_IDX, 0, 0);
|
|
gpio_matrix_in(PSRAM_INTERNAL_IO_28, SIG_IN_FUNC224_IDX, 0);
|
|
gpio_matrix_out(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC224_IDX, 0, 0);
|
|
gpio_matrix_in(PSRAM_INTERNAL_IO_29, SIG_IN_FUNC225_IDX, 0);
|
|
gpio_matrix_out(PSRAM_CLK_IO, SIG_IN_FUNC225_IDX, 0, 0);
|
|
break;
|
|
}
|
|
CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_SETUP_M);
|
|
psram_gpio_config(mode);
|
|
WRITE_PERI_REG(GPIO_ENABLE_W1TS_REG, BIT(PSRAM_CS_IO)| BIT(PSRAM_CLK_IO));
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CS_IO], PIN_FUNC_GPIO);
|
|
PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[PSRAM_CLK_IO], PIN_FUNC_GPIO);
|
|
uint32_t id;
|
|
psram_read_id(&id);
|
|
if (((id >> PSRAM_MFG_ID_S) & PSRAM_MFG_ID_M) != PSRAM_MFG_ID_V) {
|
|
return ESP_FAIL;
|
|
}
|
|
psram_enable_qio_mode(PSRAM_SPI_1);
|
|
|
|
psram_cache_init(mode, vaddrmode);
|
|
return ESP_OK;
|
|
}
|
|
|
|
//register initialization for sram cache params and r/w commands
|
|
static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode, psram_vaddr_mode_t vaddrmode)
|
|
{
|
|
CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M);
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKDIV_PRE_V, 0, SPI_CLKDIV_PRE_S);
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_N, 1, SPI_CLKCNT_N_S);
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_H, 0, SPI_CLKCNT_H_S);
|
|
SET_PERI_REG_BITS(SPI_CLOCK_REG(0), SPI_CLKCNT_L, 1, SPI_CLKCNT_L_S);
|
|
|
|
switch (psram_cache_mode) {
|
|
case PSRAM_CACHE_F80M_S80M:
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk,80+40;
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4
|
|
WRITE_PERI_REG(SPI_CLOCK_REG(0), SPI_CLK_EQU_SYSCLK_M); //SET 1DIV CLOCK AND RESET OTHER PARAMS
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
|
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_DUMMY + extra_dummy,
|
|
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
|
|
break;
|
|
case PSRAM_CACHE_F80M_S40M:
|
|
SET_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0.
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
|
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_DUMMY + extra_dummy,
|
|
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
|
|
break;
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
default:
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(31)); //flash 1 div clk
|
|
CLEAR_PERI_REG_MASK(SPI_DATE_REG(0), BIT(30)); //pre clk div
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_RD_SRAM_DUMMY_M); //enable cache read dummy
|
|
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_DUMMY_CYCLELEN_V, PSRAM_FAST_READ_DUMMY + extra_dummy,
|
|
SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_RCMD_M); //enable user mode for cache read command
|
|
break;
|
|
}
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_CACHE_SRAM_USR_WCMD_M); // cache write command enable
|
|
SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0), SPI_SRAM_ADDR_BITLEN_V, 23, SPI_SRAM_ADDR_BITLEN_S); //write address for cache command.
|
|
SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_QIO_M); //enable qio mode for cache command
|
|
CLEAR_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0), SPI_USR_SRAM_DIO_M); //disable dio mode for cache command
|
|
|
|
|
|
//config sram cache r/w command
|
|
switch (psram_cache_mode) {
|
|
case PSRAM_CACHE_F80M_S80M: //in this mode , no delay is needed
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 7,
|
|
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S);
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, PSRAM_QUAD_WRITE,
|
|
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 7,
|
|
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S);
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, PSRAM_FAST_READ,
|
|
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b
|
|
break;
|
|
case PSRAM_CACHE_F80M_S40M: //is sram is @40M, need 2 cycles of delay
|
|
case PSRAM_CACHE_F40M_S40M:
|
|
default:
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_V, 15,
|
|
SPI_CACHE_SRAM_USR_RD_CMD_BITLEN_S); //read command length, 2 bytes(1byte for delay),sending in qio mode in cache
|
|
SET_PERI_REG_BITS(SPI_SRAM_DRD_CMD_REG(0), SPI_CACHE_SRAM_USR_RD_CMD_VALUE_V, ((PSRAM_FAST_READ) << 8),
|
|
SPI_CACHE_SRAM_USR_RD_CMD_VALUE_S); //0x0b, read command value,(0x00 for delay,0x0b for cmd)
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_BITLEN, 15,
|
|
SPI_CACHE_SRAM_USR_WR_CMD_BITLEN_S); //write command length,2 bytes(1byte for delay,send in qio mode in cache)
|
|
SET_PERI_REG_BITS(SPI_SRAM_DWR_CMD_REG(0), SPI_CACHE_SRAM_USR_WR_CMD_VALUE, ((PSRAM_QUAD_WRITE) << 8),
|
|
SPI_CACHE_SRAM_USR_WR_CMD_VALUE_S); //0x38, write command value,(0x00 for delay)
|
|
break;
|
|
}
|
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL|DPORT_PRO_DRAM_SPLIT);
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL|DPORT_APP_DRAM_SPLIT);
|
|
if (vaddrmode == PSRAM_VADDR_MODE_LOWHIGH) {
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_HL);
|
|
DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_HL);
|
|
} else if (vaddrmode == PSRAM_VADDR_MODE_EVENODD) {
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL_REG, DPORT_PRO_DRAM_SPLIT);
|
|
DPORT_SET_PERI_REG_MASK(DPORT_APP_CACHE_CTRL_REG, DPORT_APP_DRAM_SPLIT);
|
|
}
|
|
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CACHE_MASK_DRAM1|DPORT_PRO_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
|
|
//cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
|
DPORT_SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, DPORT_PRO_CMMU_SRAM_PAGE_MODE, 0, DPORT_PRO_CMMU_SRAM_PAGE_MODE_S);
|
|
DPORT_CLEAR_PERI_REG_MASK(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CACHE_MASK_DRAM1|DPORT_APP_CACHE_MASK_OPSDRAM); //use Dram1 to visit ext sram.
|
|
//cache page mode : 1 -->16k 4 -->2k 0-->32k,(accord with the settings in cache_sram_mmu_set)
|
|
DPORT_SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, DPORT_APP_CMMU_SRAM_PAGE_MODE, 0, DPORT_APP_CMMU_SRAM_PAGE_MODE_S);
|
|
|
|
CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
|
|
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}
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#endif // CONFIG_SPIRAM_SUPPORT
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