Commit graph

20 commits

Author SHA1 Message Date
Angus Gratton
aceb6517c0 Refactor existing bootloader common functionality into bootloader_support component 2016-11-02 17:58:41 +11:00
Ivan Grokhotkov
42827ff869 bootloader, menuconfig: add flash size setting support 2016-10-21 15:27:25 +11:00
Angus Gratton
feca308f1f rom/spi_flash.h: Remove first parameter of SPI_read_status_high()
Corrects the prototype to match the one compiled into ROM.
2016-10-21 10:44:05 +11:00
jack
4e092be6d6 Add Comments
We reserve 4KB Slow RTC memory to save RF calibation result and BT NVS data.
If not all these Slow RTC momory Blocks are used, we will open the other parts.
2016-09-29 16:29:13 +08:00
xiaxiaotian
ec03c31ec4 1. Change the deep sleep stub code to fix wake bug. 2016-09-28 11:52:39 +08:00
Angus Gratton
7c494055e3 esp32: Bootloader wake deep sleep stub
App can contain a stub program resident in RTC fast memory. Bootloader
will load the stub on initial boot. If the device wakes from deep sleep,
the stub is run immediately (before any other data is loaded, etc.)

To implement a custom wake stub, implement a function in your program:

```
void RTC_IRAM_ATTR esp_wake_deep_sleep(void)
{
  esp_default_wake_deep_sleep();
  // other wake logic
}
```

... and it will replace the default implementation.
2016-09-28 11:14:58 +08:00
Angus Gratton
6cffb5d8b4 rom/gpio.h: Use new GPIO_PIN0_REG register name
Closes github #12
2016-09-16 09:43:52 +10:00
Wu Jian Gang
2efaf42253 Merge remote-tracking branch 'origin/feature/mbedtls' 2016-09-14 18:05:56 +08:00
Wangjialin
41d397cf3f Only modify headers in soc/ .
Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-14 13:47:28 +08:00
Wu Jian Gang
b56098a612 Merge remote-tracking branch 'origin/master' into feature/mbedtls 2016-09-13 16:31:48 +08:00
Jack
bd8febe58c add MACRO to get flash pad number from efuse value 2016-09-12 17:47:50 +08:00
Wu Jian Gang
04b53643ef header files: clean up
1. format;
2. Slow RTC memory reverse 2KB;
2016-09-12 17:47:50 +08:00
jack
24011ddd05 header files: modify rom code and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
2016-09-12 17:47:49 +08:00
Angus Gratton
2580c07ae6 esp32 hwcrypto: Make SHA-224 an obvious no-op for now
This is not the long term solution...
2016-09-08 16:47:28 +08:00
Angus Gratton
2bee84062a esp32: Add comment to ROM crypto functions recommending they not be used directly 2016-09-08 16:47:24 +08:00
Angus Gratton
2f54d0e425 Merge wifi branch commit '588d384393536a040f899b382890316c56061b6a' into feature/wifi-stage-one 2016-09-02 11:14:27 +10:00
Angus Gratton
a825fe8703 md5_hash.h: Replace outdated use of c_types.h with stdint 2016-09-01 08:58:29 +10:00
rudi ;-)
fa310016dd Update aes.h
found small mistake in it

we have:

PROVIDE ( ets_aes_crypt = 0x4005c9b8 );
PROVIDE ( ets_aes_disable = 0x4005c8f8 );
PROVIDE ( ets_aes_enable = 0x4005c8cc );
PROVIDE ( ets_aes_set_endian = 0x4005c928 );
PROVIDE ( ets_aes_setkey_dec = 0x4005c994 );
PROVIDE ( ets_aes_setkey_enc = 0x4005c97c );

Signed-off-by: Ivan Grokhotkov <ivan@espressif.com>
2016-08-27 22:17:23 +08:00
liuzhifu
ebfb8547d2 Implement ETS_INTR_ENABLE/ETS_INTR_DISABLE with xt_ints_on/xt_ints_off 2016-08-26 19:03:51 +08:00
Ivan Grokhotkov
bd6ea4393c Initial public version 2016-08-17 23:08:22 +08:00