Commit graph

17 commits

Author SHA1 Message Date
chenjianqiang
a6f990ffb9 bugfix(flash): improve flash dio read timing
When flash work in DIO Mode, in order to ensure the fast read mode of flash
is a fixed value, we merged the mode bits into address part, and the fast
read mode value is 0 (the default value).
2019-07-02 14:25:27 +08:00
Wangjialin
b1dcb52fec feature(psram): configure flash and psram speed during runtime
1. Bootloader reads SPI configuration from bin header, so that the burning configuration can be different with compiling configuration.
2. Psram mode init will overwrite original flash speed mode, so that users can change psram and flash speed after OTA.
3. Flash read mode(QIO/DIO…) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
4. Add read flash ID function, and save flash ID in g_rom_flashchip
5. Set drive ability for all related GPIOs
6. Check raise VDDSDIO voltage in 80Mhz mode
7. Add check flash ID and update settings in bootloader
8. Read flash ID once and keep in global variable
9. Read flash image header once and reuse the result

Tested cases:
1. Test new and old version of bootloader
boot Flash 20M —> app Flash 80M + Psram 80M
boot Flash 40M —> app Flash 80M + Psram 80M
boot Flash 80M —> app Flash 80M + Psram 80M
boot Flash 20M —> app Flash 80M + Psram 40M
boot Flash 40M —> app Flash 80M + Psram 40M
boot Flash 80M —> app Flash 80M + Psram 40M
boot Flash 20M —> app Flash 40M + Psram 40M
boot Flash 40M —> app Flash 40M + Psram 40M
boot Flash 80M —> app Flash 40M + Psram 40M
2. Working after esp_restart reboot.
2018-04-20 20:51:44 +08:00
Angus Gratton
f7793840e1 bootloader: Add QIO support for ESP32-D2WD SPI flash 2017-04-13 17:55:47 +10:00
Angus Gratton
85e76a7cfc spiflash ROM functions: Remove Quad I/O mode enable/disable code from flash ROM functions
Confusion here is that original ROM has two functions:

* SPIReadModeCnfig() - sets mode, calls enable_qio_mode/disable_qio_mode
* SPIMasterReadModeCnfig() - As above, but doesn't set QIO mode in status register

However we never want to use the ROM method to set/clear QIO mode flag, as not all flash chips work this way. Instead we
do it in flash_qio_mode.c in bootloader.

So in both cases (ROM or "patched ROM") we now call SPIMasterReadModeCnfig(), which is now named
esp_rom_spiflash_config_readmode().
2017-04-13 17:54:42 +10:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Angus Gratton
68cba2a1fb Bootloader: Support switching to Quad I/O mode during boot process 2017-02-09 08:44:05 +11:00
Deomid Ryabkov
d288a3d053 Remove alignment reqs from spi_flash_{read,write} 2016-12-15 10:07:31 +11:00
Angus Gratton
bab1d49f1f Merge branch 'feature/esptool_flash_encryption' into 'master'
Flash encryption support

Flash encryption support in build system, tooling

To come in future MR:
* On-device key generation on first boot (for production devices), need to finalise testing of bootloader entropy seeding.
* spi_flash_encrypted_write to support non-32-byte block writes (at least optionally.)
* I think a lot of the bootloader_support component can possibly be rolled into "spiflash" and other components, to use a common API.

See merge request !240
2016-12-12 06:50:46 +08:00
Angus Gratton
8ba75a1e9f SPI flash: Block erase size 64KB not 32KB
Reverts changes made in 9f9d92b2df
2016-12-09 14:18:58 +11:00
Angus Gratton
9eb135fd73 Flash encryption: Support enabling flash encryption in bootloader, app support
* App access functions are all flash encryption-aware
* Documentation for flash encryption
* Partition read/write is flash aware
* New encrypted write function
2016-12-01 23:49:12 -08:00
Angus Gratton
be53a6950c spi_flash_erase_range: Allow for 32KB blocks not 64KB blocks
SPI flash hardware sends 52h command, which is a 32KB erase.

There is a matching bug in the ROM SPIEraseArea code, unless
flashchip->block_size is modified first.
2016-11-24 18:05:06 +11:00
Ivan Grokhotkov
42827ff869 bootloader, menuconfig: add flash size setting support 2016-10-21 15:27:25 +11:00
Angus Gratton
feca308f1f rom/spi_flash.h: Remove first parameter of SPI_read_status_high()
Corrects the prototype to match the one compiled into ROM.
2016-10-21 10:44:05 +11:00
Wangjialin
41d397cf3f Only modify headers in soc/ .
Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-14 13:47:28 +08:00
Wu Jian Gang
04b53643ef header files: clean up
1. format;
2. Slow RTC memory reverse 2KB;
2016-09-12 17:47:50 +08:00
jack
24011ddd05 header files: modify rom code and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
2016-09-12 17:47:49 +08:00
Ivan Grokhotkov
bd6ea4393c Initial public version 2016-08-17 23:08:22 +08:00