Commit graph

216 commits

Author SHA1 Message Date
Xia Xiaotian
2a7d2a7795 soc: clear PHY status when cpu start 2020-02-13 14:28:33 +08:00
Darian Leung
09ae962c33 can: Add support for lower bit rates
This commit adds support for lower bit rates in the CAN Driver for
ESP32 Rev 2 or later chips.
2019-12-16 07:45:59 +00:00
KonstantinKondrashov
3a402fa7b2 soc/esp32: Add test_env for 32kHz XTAL unit tests 2019-11-20 16:07:17 +08:00
suda-morris
eb4c8d9991 support esp32 eco revision 2 and 3 2019-09-19 17:05:08 +08:00
Angus Gratton
5bb5670d69 efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field
8th bit is not used by hardware.

As reported https://esp32.com/viewtopic.php?f=2&t=7800&p=40895#p40894
2019-04-12 07:28:57 +00:00
Angus Gratton
e5e226a121 Merge branch 'bugfix/external_rtc_start_fail_v3.2' into 'release/v3.2'
Bugfix/external rtc start fail (v3.2)

See merge request idf/esp-idf!4662
2019-04-10 14:17:41 +08:00
maojianxin
f85294b058 Fix external start fail 2019-04-02 12:52:58 +11:00
Zhang Jun Yi
413b6487fb soc/rtc: Bypass touchpad current to external 32k crystal oscillator 2019-04-02 12:50:50 +11:00
Angus Gratton
1fac58deb7 heap: Add integer overflow checks on MALLOC_CAP_32BIT & MALLOC_CAP_EXEC 2019-03-20 18:30:17 +11:00
Ivan Grokhotkov
22dc4898d9 soc: define named constants for DPORT_CPUPERIOD_SEL values 2019-02-28 20:38:31 +08:00
Ivan Grokhotkov
b4727a8765 soc/rtc_clk: don’t clear DPORT_CPUPERIOD_SEL when switching to XTAL
This is not necessary since RTC_CNTL_SOC_CLK_SEL is set before this.
2019-02-28 20:38:31 +08:00
Angus Gratton
a7f826750b Merge branch 'revert-00d10688' into 'release/v3.2'
Revert "Merge branch 'bugfix/external_rtc_start_fail_3.2' into 'release/v3.2'"

See merge request idf/esp-idf!4293
2019-02-20 15:09:59 +08:00
Ivan Grokhotkov
509884c5ac Revert "Merge branch 'bugfix/external_rtc_start_fail_3.2' into 'release/v3.2'"
This reverts merge request !4272
2019-02-19 12:47:44 +08:00
Konstantin Kondrashov
8a656f006e esp32: Fix wdt settings in esp_restart_noos
Fixed compatibility the new apps with the old bootloaders.

Closes: https://github.com/espressif/esp-idf/issues/2927
2019-02-19 12:43:35 +08:00
maojianxin
9a229f4077 soc/rtc: fix RTC_TOUCH_TRIG_EN or RTC_ULP_TRIG_EN should keep RTC_PERIPH power on 2019-02-15 10:58:14 +08:00
Zhang Jun Yi
016c8d8b05 soc/rtc: Bypass touchpad current to external 32k crystal oscillator 2019-02-15 10:55:08 +08:00
Jiang Jiang Jian
fcf1dba9cd Merge branch 'bugfix/init_memctl_v3.2' into 'release/v3.2'
bootloader, esp32: add workaround for Tensilica erratum 572 (backport v3.2)

See merge request idf/esp-idf!4134
2019-01-23 21:43:58 +08:00
Ivan Grokhotkov
42b6c4953d bootloader, esp32: add workaround for Tensilica erratum 572
If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
2019-01-23 16:23:56 +08:00
Jiang Jiang Jian
d59d9eef4f Merge branch 'bugfix/bbpll_wakeup_reset_v3.2' into 'release/v3.2'
BBPLL reset fixes (backport v3.2)

See merge request idf/esp-idf!4011
2018-12-24 18:16:47 +08:00
Ivan Grokhotkov
c7a297195f soc/rtc: reset another BBPLL related register
Follow-up to b21ffc8a: an additional register needs to be reset.

Ref. https://github.com/espressif/esp-idf/issues/2711
2018-12-21 12:40:08 +08:00
Ivan Grokhotkov
19e96add8a soc/rtc: reset BBPLL configuration after enabling it
A workaround to reset BBPLL configuration after light sleep. Fixes the
issue that Wi-Fi can not receive packets after waking up from light
sleep.

Ref. https://github.com/espressif/esp-idf/issues/2711
2018-12-21 12:39:49 +08:00
Ivan Grokhotkov
ade85cc850 panic: dump some instruction memory on IllegalInstruction exception 2018-12-12 11:58:55 +08:00
Konstantin Kondrashov
8bba348528 aes/sha/mpi: Bugfix a use of shared registers.
This commit resolves a blocking in esp_aes_block function.

Introduce:
The problem was in the fact that AES is switched off at the moment when he should give out the processed data. But because of the disabled, the operation can not be completed successfully, there is an infinite hang. The reason for this behavior is that the registers for controlling the inclusion of AES, SHA, MPI have shared registers and they were not protected from sharing.

Fix some related issue with shared using of AES SHA RSA accelerators.

Closes: https://github.com/espressif/esp-idf/issues/2295#issuecomment-432898137
2018-11-05 04:22:47 +00:00
Michael (XIAO Xufeng)
4132834faa test: fix the unit test fail issue under single_core config
Introduced in 97e3542947.

The previous commit frees the IRAM part when single core, but doesn't
change the memory layout functions. The unit test mallocs IRAM memory
from the heap, accidently into the new-released region, which doesn't
match the memory layout function.

This commit update the memory layout function to fix this.
2018-10-31 17:04:32 +08:00
Jiang Jiang Jian
97e3542947 Merge branch 'bugfix/release_some_memory_on_single_core_mode' into 'master'
release memory not used in single core mode

See merge request idf/esp-idf!2733
2018-10-30 15:53:31 +08:00
Michael (XIAO Xufeng)
d0361a32d7 test: fix the IRAM type conflict issue using heap_caps_malloc 2018-10-25 12:31:44 +08:00
Renz Bagaporo
cc774111bf cmake: Add support for test build 2018-10-20 12:07:24 +08:00
Ivan Grokhotkov
bd11965f6c Merge branch 'bugfix/ndebug_build' into 'master'
soc,sdmmc: fix build failures when NDEBUG is used

See merge request idf/esp-idf!3352
2018-10-19 11:55:37 +08:00
Angus Gratton
f53fef9936 Secure Boot & Flash encryption: Support 3/4 Coding Scheme
Includes esptool update to v2.6-beta1
2018-10-16 16:24:10 +11:00
Ivan Grokhotkov
a20d9287fe soc: use _EARLY versions of ESP_LOG
Some logging done in soc component may happen before logging via
stdout is possible. Use _EARLY version of log calls to make sure that
output is visible. The downside is that application does not have a
way to silence these logs. However since the soc component doesn’t
use any LOGV/LOGD/LOGI and only logs warnings and errors, this should
not impact the application.
2018-10-15 14:59:46 +08:00
Ivan Grokhotkov
ab68b9d90d soc,sdmmc: fix build failures when NDEBUG is used
Use explicit error checking instead of asserts, use SOC_LOG to print
error/warning messages where needed.
2018-10-15 14:57:12 +08:00
Ivan Grokhotkov
22b840f3df bootloader: don’t reload RTC_FAST DRAM after deep sleep
When CONFIG_ESP32_RTCDATA_IN_FAST_MEM is enabled, RTC data is placed
into RTC_FAST memory region, viewed from the data bus. However the
bootloader was missing a check that this region should not be
overwritten after deep sleep, which caused .rtc.bss segment to loose
its contents after wakeup.
2018-09-29 14:02:16 +08:00
Jack
2efd6859ed release memory not used in single core mode
1. do not start ipc task in single core mode
2. do not use APP cpu cache memory in single core mode
3. relase data used in rom by APP cpu
2018-09-25 15:13:47 +08:00
negativekelvin
8e2856b83d soc: fix CPU frequency not updated in rtc_clk_init
Add missing call to rtc_clk_cpu_freq_set_config

Merges https://github.com/espressif/esp-idf/pull/2398
2018-09-12 21:13:42 +08:00
Renz Christian Bagaporo
d9939cedd9 cmake: make main a component again 2018-09-11 09:44:12 +08:00
Konstantin Kondrashov
38098b713f esp32/sleep: Add a function to disable logging from ROM code 2018-09-04 16:03:18 +08:00
Konstantin Kondrashov
9c715d7946 bootloader_support: Fix enable rtc_wdt for resolve issue with varying supply
Eliminates the issue with the lock up in the bootloader due to a power drawdown during its operation.

Closes https://github.com/espressif/esp-idf/issues/1814
2018-09-03 05:43:01 +00:00
Ivan Grokhotkov
78fab8a0f9 sdmmc: implement partial DDR support
Works for 3.3V eMMC in 4 line mode.
Not implemented:
- DDR mode for SD cards (UHS-I) also need voltage to be switched to 1.8V.
- 8-line DDR mode for eMMC to be implemented later.
2018-08-30 13:11:54 +08:00
Mahavir Jain
f0fa66a50e rtc_wdt: fix overflow issue with setting wdt interval
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-24 18:06:39 +05:30
Ivan Grokhotkov
88d40e01b4 Merge branch 'feature/rtc_slowclk_extra_options' into 'master'
Add more RTC_SLOW_CLK options

See merge request idf/esp-idf!2984
2018-08-23 11:27:14 +08:00
Ivan Grokhotkov
902344c516 Merge branch 'bugfix/trace_mem_layout_pro_cpu' into 'master'
soc: fix trace memory region for single core mode

See merge request idf/esp-idf!3029
2018-08-22 16:51:43 +08:00
Ivan Grokhotkov
5bf3654637 soc/rtc: Force power on 8M clock if it is used to derive RTC slow clock 2018-08-22 11:33:20 +08:00
Ivan Grokhotkov
8365f0f5d2 soc/rtc: add support for external 32k oscillator
Compared to external 32k XTAL, when active oscillator is used as input,
some parameters need to be set differently.
2018-08-22 11:33:20 +08:00
Ivan Grokhotkov
e59571eece soc/rtc_clk: reduce data size by disabling CSWTCH generation
Saves about 200 bytes of DRAM at the expense of 4 bytes in IRAM.
2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
db2f0f45be soc/rtc_clk: split rtc_clk_init into separate object file
rtc_clk_init and related functions don’t need to be in IRAM/DRAM.
2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
bcf79e5cf2 tests: use new CPU frequency setting API 2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
bec70ce298 esp32: use new CPU frequency setting API 2018-08-21 13:02:46 +08:00
Ivan Grokhotkov
2e31cce390 soc/rtc: CPU frequency settings refactoring
Previous APIs used to set CPU frequency used CPU frequencies listed in
rtc_cpu_freq_t enumeration. This was problematic for two reasons.
First, supporting many possible frequency values obtained by dividing
XTAL frequency was hard, as every value would have to be listed in
the enumeration. Since different base XTAL frequencies are supported,
this further complicated things, since not all of these divided
frequencies would be valid for any given XTAL frequency. Second,
having to deal with enumeration values often involved switch
statements to convert between enumeration and MHz values, handle
PLL/XTAL frequencies separately, etc.

This change introduces rtc_cpu_freq_config_t structure, which contains
CPU frequency (in MHz) and information on how this frequency has to
be generated: clock source (XTAL/PLL), source frequency, clock
divider value. More fields can be added to this structure in the
future. This structure simplifies many parts of the code, since both
frequency value and frequency generation settings can be accessed in
any place in code without the need for conversions.

Additionally, this change adds setting of REF_TICK dividers to support
frequencies lower then XTAL with DFS.
2018-08-21 13:02:03 +08:00
Mahavir Jain
0075e2f316 soc: fix trace memory region for single core mode
Signed-off-by: Mahavir Jain <mahavir@espressif.com>
2018-08-15 20:52:39 +05:30
Konstantin Kondrashov
a8e46775c6 soc/rtc_wdt: Add API functions for rtc_wdt
Added functions:
rtc_wdt_protect_off/on
rtc_wdt_set_length_of_reset_signal
rtc_wdt_set_stage
rtc_wdt_set_time
rtc_wdt_feed
rtc_wdt_disable/enable
2018-08-14 17:48:02 +05:00