- In SPI mode, the card will respond to the initial SDIO reset (done
using CMD52) with “invalid command” error. Handle this correctly.
- sdmmc_card_init had a hack where GO_IDLE_STATE (CMD0) command was
sent twice. Add explanation why this is done, and don’t expect
correct response from the card on first CMD0.
- improve logs printed at debug level by adding CMD index
- Add SDIO support at protocol layer (probing, data transfer, interrupts)
- Add SDIO interrupts support in SDMMC host
- Add test (communicate with ESP32 in SDIO download mode)
SET_BUS_WIDTH is not a data transfer command. Extensive search in the
host datasheet and SD card spec did not reveal the origin of this hack
or 'feature'. Further testing showed that removing this does not lead to
regressions.
Previously the timeout was set to the same value (1000ms) for all kinds
of commands. In some cases, such as with slow cards, write commands
failed to complete in time.
This change makes command timeouts configurable via sdmmc_host_t
structure, and also makes default timeouts different for ordinary
commands and write commands.
Closes https://github.com/espressif/esp-idf/issues/1093
Ref TW15774.
By default SD cards are initialized in default speed (DS) mode. Enabling
HS mode requires SWITCH_FUNC command to be sent twice: first time to
query if the card supports switching to HS mode, second time to perform
the switch.
This change implements SWITCH_FUNC command and adds the procedure to
switch to HS mode.
In some cases the card needs to be returned to standby mode from data
transfer mode. This is done using CMD7 command, which does not receive
any response in this case.
MMC_RSP_BITS helper function had a hack that it flipped word order in
the response, assuming that response size is 4 words. This hack does not
work for responses which are not 4 words long (such as the SWITCH_FUNC
response, which is 64 words long).
This change removes the hack and the matching word order reversal code
in sdmmc driver.
SDMMC hardware treats all buffers as aligned, and ignores 2 LSBs of
addresses written into DMA descriptors. Previously SDMMC host driver
assumed that data buffers passed from SDDMC command layer would be
aligned. However alignment checks were never implemented in the command
layer, as were the checks that the buffer coming from the application
would be in DMA capable memory. Most of the time this was indeed true.
However in some cases FATFS library can pass buffers offset by 2 bytes
from word boundary. “DMA capable” restriction may be broken if pSRAM
support is used.
This change adds buffer checks to the SDMMC host driver (alignment and
DMA capability), so that the host layer will error out for incompatible
buffers. In SDMMC command layer, a check is added to read and write
functions. If an incompatible buffer is passed from the application, new
buffer (512 bytes size) is allocated, and the transfer is performed
using {READ,WRITE}_SINGLE_BLOCK commands.
