check master read write functions with array of registers)
fix master serial processing code and modbus controller to work with register array
modbus_master: add reading and writing of test value array (58 registers) to check failure is gone
remove parameter temporary buffer from modbus controller to allow more than 24 byte writes
driver: fix issue with TOUT feature
driver: fix uart_rx_timeout issue
driver: fix issue with rxfifo_tout_int_raw not triggered when received fifo_len = 120 byte and all bytes read out of fifo as result of rxfifo_full_int_raw
driver: add function uart_internal_set_always_rx_timeout() to always handle tout interrupt
examples: call uart_internal_set_always_rx_timeout() to handle tout interrupt correctly
examples: update examples to use tout feature
driver: reflect changes of uart_set_always_rx_timeout() function, change uart.c
driver: change conditions to trigger workaround for tout feature in uart.c
driver: change uart_set_always_rx_timeout()
freemodbus: fix tabs, remove commented code
driver: remove uart_ll_is_rx_idle()
tout_thr - move calculation and masking into hal layer update driver and uart_ll (add uart_ll_set_rx_tout)
move tout calculation into uart_ll
move calculation of time out in bit time for esp32s2 into low level uart_ll.h file
move uart_hal_get_symb_len() into hal
update set_rx_timeout() to warn user about incorrect value
update HAL, LL 1
fix uart_xx_set_rx_tout() to convert symbol time into bit time
update param description
update tout calculation in LL
update uart_hal_get_max_rx_timeout_thrd() and uart_ll_get_max_rx_timeout_thrd()
This commit updates the watchdog timers (MWDT and RWDT)
in the following ways:
- Add seprate LL for MWDT and RWDT.
- Add a combined WDT HAL for all Watchdog Timers
- Update int_wdt.c and task_wdt.c to use WDT HAL
- Remove most dependencies on LL or direct register access
in other components. They will now use the WDT HAL
- Update use of watchdogs (including RTC WDT) in bootloader and
startup code to use the HAL layer.
Prefer assertions, making available functions only when caps support it
for cpu-related abstractions.
Changes cpu hal functions to stall, unstall, reset to not accept -1;
instead prefering macros that provide the same functionality.
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
