Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.
With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.
In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
Small changes to clock calibration value will cause increasing errors
the longer the device runs. Consider the case of deep sleep, assuming
that RTC counter is used for timekeeping:
- before sleep:
time_before = rtc_counter * calibration_val
- after sleep:
time_after = (rtc_counter + sleep_count) * (calibration_val + epsilon)
where 'epsilon' is a small estimation error of 'calibration_val'.
The apparent sleep duration thus will be:
time_after - time_before = sleep_count * (calibration_val + epsilon)
+ rtc_counter * epsilon
Second term on the right hand side is the error in time difference
estimation, it is proportional to the total system runtime (rtc_counter).
To avoid this issue, this change makes RTC_SLOW_CLK calibration value
persistent across restarts. This allows the calibration value update to
be preformed, while keeping time after update same as before the update.
DPORT access protection can not work when the other CPU is stalled.
Writes to DPORT registers in esp_restart caused the program to hang due
to access protection, and the reset happened due to RTC_WDT, not SW_RST.
This change adds esp_dport_access_int_deinit function and calls it from
esp_restart once the other core is stalled.
add API to get chip info
This change adds an API to get chip info, such as chip model, enabled capabilities, size of embedded flash, silicon revision.
Hello_world example is modified to print out the information about the chip. The example is also simplified by moving all code into the main task.
Ref TW12031.
See merge request !549
Optimize configuration of base MAC address
Application developer can call APIs to configure base MAC address
instead of using menuconfig.
See merge request !744
component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
See merge request !742
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
optimize scan before station connecting to AP
1. Store the information of AP(ssid, password, bssid, channel, etc)
into nvs when station connects to AP successfully. If station
connects to the same AP next time, it will scan the stored channel of the AP
first.
2. Add a parameter of channel for scanning before connecting to AP.
If the channel is set to 0, station will scan full channels. If it
is set to 1~13, station will only scan the channel.
See merge request !704
1. Store the information of AP(ssid, password, bssid, channel, etc)
into nvs when station connects to AP successfully. If station
connects to the same AP next time, it will scan the stored channel of the AP
first.
2. Add a parameter of channel for scanning before connecting to AP.
If it is set to 1~13, station will scan starting from the channel.
If the channel of AP is unknown, set it to 0.
esp32: Core dump sanity checks
Adds sanity checks when doing core dump to flash
- CRC for core dump flash partition config
- Tasks with corrupted TCBs are skipped
- Assertions to check that nothing is written beyond core dump flash partition
Ref TW11879
See merge request !686
- CRC for core dump flash partition config
- Tasks with corrupted TCBs are skipped
- Assertions to check that nothing is written beyond core dump flash partition
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
function can be used instead to get an approximate RTC_SLOW_CLK
frequency
- Clock calibration is performed at startup. The value is saved and used
for timekeeping and when entering deep sleep.
- When using the 32k XTAL, startup code will wait for the oscillator to
start up. This can be possibly optimized by starting a separate task
to wait for oscillator startup, and performing clock switch in that
task.
- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.
- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
error.
- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
slow_clk_cycles argument would exceed certain value
- Improve 32k XTAL oscillator startup time by introducing bootstrapping
code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
pins to set better initial conditions for the oscillator.
Base MAC address can be stored in default manufacture-defined or customer
pre-defined place in EFUSE and other place e.g. flash or EEPROM.
If choose to use base MAC address which is stored in other place, please
call esp_base_mac_addr_set_external() before initializing WiFi/BT/Ehternet.
- Implements application tracing module which allows to send arbitrary
data to host over JTAG. This feature is useful for analyzing
program modules behavior, dumping run-time application data etc.
- Implements printf-like logging functions on top of apptrace module.
This feature is a kind of semihosted printf functionality with lower
overhead and impact on system behaviour as compared to standard printf.
Detect invalid cache access
This MR adds always-on feature which detects cache invalid access and triggers panic handler when invalid access interrupt is raised.
See merge request !660
Confusion here is that original ROM has two functions:
* SPIReadModeCnfig() - sets mode, calls enable_qio_mode/disable_qio_mode
* SPIMasterReadModeCnfig() - As above, but doesn't set QIO mode in status register
However we never want to use the ROM method to set/clear QIO mode flag, as not all flash chips work this way. Instead we
do it in flash_qio_mode.c in bootloader.
So in both cases (ROM or "patched ROM") we now call SPIMasterReadModeCnfig(), which is now named
esp_rom_spiflash_config_readmode().
Introduce soc component, add source of rtc_clk and rtc_pm libraries
This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.
Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.
Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.
See merge request !633
