Commit graph

165 commits

Author SHA1 Message Date
Sachin Parekh
46d914ff45 gdb: Modify PC in case of invalid PC
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-05-08 18:34:52 +05:30
Mahavir Jain
44939a6b1e Merge branch 'feature/iram_data_bss' into 'master'
esp32: IRAM_DATA_ATTR and IRAM_BSS_ATTR introduced

See merge request espressif/esp-idf!8377
2020-04-22 21:44:44 +08:00
Sachin Parekh
1e6c25992e esp32: IRAM_DATA_ATTR and IRAM_BSS_ATTR introduced
Using these attributes, .data and .bss can be placed in IRAM

Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-04-17 19:35:23 +05:30
Jakob Hasse
4943b1cbf0 CXX: make __attribute__((init_priority(n))) work
* Added corresponding test case
* Moved all C++ init tests to separate file

Closes https://github.com/espressif/esp-idf/issues/5038
2020-04-08 09:11:54 +08:00
Ivan Grokhotkov
cbb84e8f5e esp32s2: fix THREADPTR calculation, re-enable FreeRTOS TLS tests
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.

2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.

Full explanation of the calculation below.

Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).

At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:

THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)

The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to

THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).

The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.

Closes IDF-1239
2020-01-23 11:29:22 +01:00
Renz Christian Bagaporo
df26ab13e2 test_utils: implement performance timer 2019-11-18 10:29:01 +08:00
xiehang
5e7f43f3d1 esp_wifi: Put some rx code to iram 2019-11-13 11:44:23 +00:00
Anton Maklakov
d86ec0f367 Revert "C++: add provisions for optional RTTI support"
This reverts commit 499d087c91.
2019-10-31 10:12:16 +07:00
Angus Gratton
8675a818f9 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-22 13:51:49 +11:00
Ivan Grokhotkov
499d087c91 C++: add provisions for optional RTTI support
Ref. https://github.com/espressif/esp-idf/issues/1684

This change allows RTTI to be enabled in menuconfig. For full RTTI
support, libstdc++.a in the toolchain should be built without
-fno-rtti, as it is done now.

Generally if libstdc++.a is built with RTTI, applications which do not
use RTTI (and build with -fno-rtti) could still include typeinfo
structures referenced from STL classes’ vtables. This change works
around this, by moving all typeinfo structures from libstdc++.a into
a non-loadable section, placed into a non-existent memory region
starting at address 0. This can be done because when the application
is compiled with -fno-rtti, typeinfo structures are not used at run
time. This way, typeinfo structures do not contribute to the
application binary size.

If the application is build with RTTI support, typeinfo structures are
linked into the application .rodata section as usual.

Note that this commit does not actually enable RTTI support.
The respective Kconfig option is hidden, and will be made visible when
the toolchain is updated.
2019-10-13 14:46:44 +02:00
Ivan Grokhotkov
5830f529d8 Merge branch 'master' into feature/esp32s2beta_merge 2019-10-02 19:01:39 +02:00
Roland Dobai
5a916ce126 Support ELF files loadable with gdb 2019-09-24 07:19:50 +00:00
Angus Gratton
438d513a95 Merge branch 'master' into feature/esp32s2beta_merge 2019-09-16 16:18:48 +10:00
Michael (XIAO Xufeng)
df27a50866 app_update: re-enable elf-sha256 2019-09-11 18:29:11 +08:00
KonstantinKondrashov
c543aac91e bootloader: API for the fast wakeup and custom using RTC mem
Added "Reserve RTC FAST memory for custom purposes" option.
Added a boot counter.
2019-08-21 11:44:37 +00:00
Tim Nordell
43393cf4d1 bootloader: Support for skipping validation upon wake from deep sleep
This saves time when waking up from deep sleep, but potentially decreases
the security of the system.  If the application able to modify itself
(especially areas that are loaded into RAM) in flash while running
without crashing or is modifies the cached bits of information about
what was last booted from the bootloader, this could cause security
issues if the user does a "deep sleep reset" since the full validation
is skipped.

Signed-off-by: Tim Nordell <tim.nordell@nimbelink.com>
2019-08-21 11:44:37 +00:00
suda-morris
90c4827bd2 add esp_eth component 2019-06-26 10:19:23 +08:00
Hrishikesh Dhayagude
342f6a7829 Port NimBLE Host Stack on ESP-IDF 2019-06-25 09:03:58 +08:00
Gautier Seidel
542e544faa esp32: Allow fixed static RAM size and DRAM heap size
Merges https://github.com/espressif/esp-idf/pull/3222
2019-06-06 18:23:04 +10:00
Angus Gratton
22514c1dd9 cmake: For gcc8 use linker to find paths to libc, libm, libstdc++, etc
Removes the need to know/guess the paths to these libraries. Once we are gcc 8 only, we
can remove -nostdlib and no additional arguments are needed for system libraries.

The catch is: any time IDF overrides a symbol in the toolchain sysroot, we need
an undefined linker marker to make sure this symbol is seen by linker.
2019-05-28 12:54:37 +08:00
Roland Dobai
0ae53691ba Rename Kconfig options (components/esp32) 2019-05-21 09:09:01 +02:00
morris
f5b03c9ea3 misc adjustment of esp32 component 2019-04-03 19:57:46 +08:00
morris
c159984264 separate rom from esp32 component to esp_rom
1. separate rom include files and linkscript to esp_rom
2. modefiy "include rom/xxx.h" to "include esp32/rom/xxx.h"
3. Forward compatible
4. update mqtt
2019-03-21 18:51:45 +08:00
Angus Gratton
a79c5b8271 esp32: Rename esp32.common.ld to esp32.project.ld to avoid build errors when downgrading
Linker script generator produces build/esp32/esp32.common.ld from
components/esp32/ld/esp32.common.ld.in

This works fine until IDF is downgraded to V3.1 which uses components/esp32/ld/esp32.common.ld and
doesn't track build/esp32/esp32.common.ld at all.

At this point, the linker runs in the build/esp32 directory and "-T esp32.common.ld" picks up the
linker script generated .ld file, which causes mis-builds.

As reported on forums: https://esp32.com/viewtopic.php?f=13&t=9684&p=40105
2019-03-14 09:59:31 +11:00
Liu Zhi Fu
711173b3d6 esp32: make WiFi IRAM optimization configurable
With this feature, the WiFi IRAM optimization can be disabled/enabled via menuconfig.
2019-02-26 19:55:57 +08:00
Angus Gratton
5b182eefc1 Merge branch 'bugfix/spiram_linker_wildcards' into 'master'
newlib: Provide library name for ROM libc object files linked as PSRAM workarounds

See merge request idf/esp-idf!4152
2019-02-19 13:28:10 +08:00
baohongde
27235e023f components/bt: Fix crash when inquiry stop 2019-01-31 11:47:41 +08:00
Angus Gratton
7f307423c1 newlib: Provide library name for ROM libc object files linked as PSRAM workarounds
Works around bug reported on forums where any source file ending in *lock.c or *creat.c
was being linked to IRAM.

https://esp32.com/viewtopic.php?f=13&t=8909&p=37362#p37362

Also moves all related functionality to newlib component.
2019-01-24 11:30:05 +08:00
Angus Gratton
db243d092c linker external bss: Align end of ext bss to word boundary
TW27954
2018-12-20 01:40:05 +00:00
Angus Gratton
769bd4a4af linker: When using section type attributes, create unique sections
* Prevents section type conflict errors if (say) const & non-const data
  is put into the same section (ie with DRAM_ATTR)

* Allows linker --gc-sections to remove unused custom sections
2018-12-19 04:42:04 +00:00
Konstantin Kondrashov
3b9cb25fe1 esp32: Add firmware version to app
Added a new structure esp_app_desc_t. It has info about firmware:
version, secure_version, project_name, time/date build and IDF version.
Added the ability to add a custom structure with a description of the firmware.

The esp_app_desc_t is located in fixed place in start of ROM secotor. It is located after structures esp_image_header_t and esp_image_segment_header_t.

app_version is filed from PROJECT_VER variable (if set in custom make file) or PROJECT_PATH/version.txt or git repo (git describe).

Add API to get app_desc from partition.
2018-12-03 16:52:04 +08:00
Renz Bagaporo
63411fc556 tools: implement linker script generation 2018-11-16 12:42:02 +08:00
zwj
baf57b9702 component/bt: add vendor hci cmd 2018-11-09 14:39:04 +08:00
baohongde
f2309f1013 components/bt: Point ACL RX buffer ptr to ACL RX buffer if ACL RX buffer ptr is null
1. When WIFI task or other high priority task blocks the Bluetooth task, ACL RX buffer will use up, ACL RX buffer ptr will point to null and will never point to a valid adress. Causing errors in Bluetooth.
2. hcimsgs.h used whether flow control is on or off
2018-11-01 17:33:44 +08:00
wangmengyang
159d4ac742 component/bt: bugfix for the error in calculation sniff anchor point which can result in supervision timeout after connection is brought into sniff mode 2018-10-31 16:16:49 +00:00
Mahavir Jain
49130c6b34 esp_ringbuf: fix default placement from flash to IRAM
In earlier change this component was decoupled from freertos and hence
regression was introduced which changed default placement to flash. Some
device drivers make use of ringbuffer while flash cache is being disabled
and hence default placement should instead be internal memory.

Closes: https://github.com/espressif/esp-idf/issues/2517
2018-10-17 23:34:07 -05:00
Angus Gratton
31cf117404 Merge branch 'feature/bss_seg_in_external_memory' into 'master'
memory:   support .bss segment can be in psram

See merge request idf/esp-idf!2236
2018-10-10 14:40:21 +08:00
Ivan Grokhotkov
9240bbb708 esp32: remove ROM functions redefined in IDF from LD script
In some cases, linker could choose to use ROM functions instead of the
ones defined in IDF.
For functions used in ROM stub table, this would lead to infinite
recursion when the corresponding function was called from ROM.
For crypto functions, some of these were modified in IDF, and
incompatible with ROM counterparts.
2018-10-02 01:20:04 +00:00
Ivan Grokhotkov
70412928de esp32: fix placement of .rtc_noinit
When CONFIG_ESP32_RTCDATA_IN_FAST_MEM is enabled, .rtc_noinit should
be in RTC_FAST memory, same as .rtc.data
2018-09-29 14:02:16 +08:00
TianZhongXing
01308df8a6 doc: update document of external memory 2018-09-26 10:39:57 +08:00
TianZhongXing
19a67271ef lwip:move lwip bss segment to psram 2018-09-21 16:20:31 +08:00
TianZhongXing
974112378b feature: allow .bss segment in external memory 2018-09-21 16:20:26 +08:00
Alex Lisitsyn
ec5eb1e5c2 esp32: Add option to place.rtc_data and .rtc_rodata into the RTC_FAST segment
Changes:
KConfig: The option CONFIG_ESP32_RTCDATA_IN_FAST_MEM is added in Kconfig file for esp32 component.
esp32.common.ld: added support of RTC_DATA_ATTR, RTC_RODATA_ATTR data placement into appropriate segment according to Kconfig option.
esp32.ld: linker script is modified to set alias for memory segment selected by Kconfig option to place data. The segments for force placement are added for RTC_FAST_ATTR, RTC_SLOW_ATTR attributes.
esp_attr.h: added new attributes RTC_FAST_ATTR, RTC_SLOW_ATTR for force placement into fest/slow memory.
test_rtc_fast.c: Added unit test cases to check data placement into appropriate memory segment.
Updated documentation for RTC_DATA_ATTR, RTC_FAST_ATTR, RTC_SLOW_ATTR in deep_sleep_stub.rst file.

TW#18001
Closes https://github.com/espressif/esp-idf/issues/1553
2018-09-12 09:25:13 +02:00
Angus Gratton
b355854d4d Merge branch 'master' into feature/cmake 2018-09-05 10:35:04 +08:00
Angus Gratton
a9c4ed7139 Merge branch 'master' into feature/cmake 2018-08-30 18:51:01 +08:00
Tian Hao
5a8917c337 fix bluetooth security vulnerability of ECDH publick key checking 2018-08-30 11:39:19 +08:00
zwj
430d3da089 component/bt: fix crash when BLE do SMP connect and disconnect stress test 2018-08-27 11:09:29 +08:00
Ivan Grokhotkov
4dd7233b20 Merge branch 'feature/reset_reason' into 'master'
Add API to get reset reason

See merge request idf/esp-idf!2871
2018-08-21 11:34:12 +08:00
Ivan Grokhotkov
3ef650cd46 esp32/test: add tests for reset reasons 2018-08-20 16:49:20 +08:00
Angus Gratton
ff2404a272 Merge branch 'master' into feature/cmake 2018-08-16 17:14:17 +10:00