Commit graph

21 commits

Author SHA1 Message Date
Ivan Grokhotkov
5376a06d7b Merge branch 'bugfix/range_CONFIG_ESP32_RTC_CLK_CAL_CYCLES' into 'master'
soc/clk: Fix range CONFIG_ESP32_RTC_CLK_CAL_CYCLES

See merge request idf/esp-idf!2719
2018-07-17 19:43:11 +08:00
Konstantin Kondrashov
ac3508615a soc/clk: Fix range CONFIG_ESP32_RTC_CLK_CAL_CYCLES
Fixed the error division on zero.
Also fixed range CONFIG_ESP32_RTC_CLK_CAL_CYCLES in Kconfig.
Fixed a overflow error by TIMG in the function rtc_clk_cal_internal. This error was due to a limit in values TIMG_RTC_CALI_MAX=0x7FFF (to write the slowclk_cycles) and TIMG_RTC_CALI_VALUE=0x1FFFFFF (to read xtal_cycles). Added assert finctions.

Closes https://github.com/espressif/esp-idf/issues/2147
2018-07-10 11:56:12 +05:00
Alexey Gerenkov
c2dc09304c gcc8_newlib3: Compilation warnings and errors not specific to newlib v3 2018-07-09 13:22:24 +03:00
kooho
ef39c09bc1 driver: reset communication peripherals when the cpu starts. 2018-05-18 14:41:58 +08:00
Angus Gratton
662fe55996 Merge branch 'bugfix/select_rtc_slow_clk' into 'master'
esp32/clk: Fix starting rtc oscillator if it bad

See merge request idf/esp-idf!2215
2018-05-15 12:57:22 +08:00
Konstantin Kondrashov
9ad0760b9d esp32/clk:Fix starting rtc oscillator if it is bad
If the RTC crystal is bad or has no matched capacitance, then you do not need to start such the crystal. It is necessary to determine this case, output an error (about impossibility to start from the oscillator) and start from the internal RC of the chain.

Reduced the default value of the number of bootstrap cycles. Because we can oscillating the oscillator which then stops. (in Kconfig). Changed from 100 to 5.

The number of calibration cycles has been increased. It is the main criterion for estimating the launch of an oscillator. A large increase leads to an increase in the load time, as well as the stability of recognition of this case. (in Kconfig).
Changed from 1024 to 3000.
2018-05-15 08:59:15 +05:00
jack
c384fa2492 rename clock enable and reset bits for SPI modules
1.The names of clock enable and reset bits do not match with TRM, just rename them.
2018-05-14 16:45:03 +08:00
Angus Gratton
2f318d16fa log: Make ESP_LOGx macros into single statements
Requires a semicolon after any use (previously this was optional due to trailing } after expansion)

Closes https://github.com/espressif/esp-idf/issues/1757
2018-04-26 09:08:07 +10:00
Konstantin Kondrashov
f7df532ec0 bugfix/rtc_clk_32k_bootstrap: Fix starting 32k RTC
1. External 32kHz crystal is started for too long or it may not start at all. It is often observed at the first start.
2. At the first start, it is possible that the crystal did not start. And the recorded period was recorded as 0. Which led to a division error by zero during the transition to the deep sleep mode (Maybe somewhere else).
3. Added a unit test to test a new method of oscillation an external crystal.
4. Added a new method of oscillating of an external crystal. The legs of the crystal are fed with a 32 kHz frequency.

The new method eliminates these errors.

Added unit test: `\esp-idf\components\soc\esp32\test\test_rtc_clk.c`: `make TEST_COMPONENTS=soc`
- 8 Test starting external RTC crystal. Will pass.

`Bootstrap cycles for external 32kHz crystal` - is specified in the file Kconfig by default 100.

QA tested a new method of oscillation the crystal on 25 boards. The supply of square waves on the crystal showed a 100% result in contrast to the previous method of launching the crystal. After the tests, the old method was deleted.

Closes TW19143
2018-03-21 13:27:56 +05:00
Jeroen Domburg
569bfad2e3 Fix the clock subsystem so it doesn't undo the weird condition spiram_psram.c jams the enable/reset bits of SPI3 in when 80MHz mode is selected anymore 2017-12-19 19:12:58 +08:00
Angus Gratton
c69af42b96 esp32: Fix backwards compatibility for pre-v2.1 bootloaders
Older bootloaders don't set RTC_XTAL_FREQ_REG or call rtc_clk_init(),
app needs to pick this up.

Reported at
https://esp32.com/viewtopic.php?f=2&t=3939&p=17836
2017-12-18 13:45:57 +11:00
Ivan Grokhotkov
a705221492 esp32: fix incorrect clock enable bit name for UART0
Closes https://github.com/espressif/esp-idf/issues/1301
2017-12-08 13:14:36 +08:00
Frederik Merz
20ccec1061 Disable all UART CLKs that are not console 2017-11-03 19:03:00 +08:00
XiaXiaotian
42cefc173f refractor WiFi clock setting
Do not set WiFi clock in PHY initializing function, move it to WiFi
   start/stop function.
2017-11-02 15:24:21 +08:00
Ivan Grokhotkov
37e9bc715c esp_clk.h: make public, add getters for RTC time, CPU/APB freq 2017-10-18 14:19:14 +08:00
michael
9d9e771933 fix(global, log): fix esp_log(_early)_timestamp readings after startup by correct the CCOUNT register when switching CPU clock.
TW#13332, Closes #700
2017-09-26 15:18:17 +08:00
Jeroen Domburg
6d95934a3c Make 80MHz PSRAM work as well, add testcase for weirdness reported on esp32 forums, clean up unused define in psram code 2017-09-14 10:47:44 +08:00
XiaXiaotian
4776f73ca4 Disable some peripheral clocks when cpu starts
All peripheral clocks are default enabled after chip is powered on.
    When CPU starts, if reset reason is CPU reset, disable those clocks
    that are not enabled before reset. Otherwise, disable all those
    useless clocks.
    These peripheral clocks must be enabled when the peripherals are
    initialized and disabled when they are deinitialized.
2017-08-29 11:18:42 +08:00
Ivan Grokhotkov
8ccb2a4990 esp32: make time monotonic across resets
Small changes to clock calibration value will cause increasing errors
the longer the device runs. Consider the case of deep sleep, assuming
that RTC counter is used for timekeeping:
- before sleep:
   time_before = rtc_counter * calibration_val
- after sleep:
   time_after = (rtc_counter + sleep_count) * (calibration_val + epsilon)
where 'epsilon' is a small estimation error of 'calibration_val'.
The apparent sleep duration thus will be:
time_after - time_before = sleep_count * (calibration_val + epsilon)
                           + rtc_counter * epsilon

Second term on the right hand side is the error in time difference
estimation, it is proportional to the total system runtime (rtc_counter).

To avoid this issue, this change makes RTC_SLOW_CLK calibration value
persistent across restarts. This allows the calibration value update to
be preformed, while keeping time after update same as before the update.
2017-06-16 12:06:04 +08:00
Ivan Grokhotkov
1c3b40adeb esp32: select 8M clock as RTC_FAST_CLK on startup
Even though RTC_CLK_CONFIG_DEFAULT correctly had RTC_FAST_FREQ_8M as the
fast clock, the bootloader modified fast_freq field to the currently
selected RTC_FAST_CLK (so that the clock choice is not affected by the
bootloader). The application startup code never switched to 8M clock,
which caused the default (XTAL/4) to be used as RTC_FAST_CLK. This had
caused a number of issues, such as touch pads not working in deep sleep.

Fixes https://github.com/espressif/esp-idf/issues/542.
Ref TW12053.
2017-04-27 12:44:54 +08:00
Ivan Grokhotkov
6353bc40d7 Add support for 32k XTAL as RTC_SLOW_CLK source
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.
2017-04-26 12:43:22 +08:00