Commit graph

11 commits

Author SHA1 Message Date
Deomid Ryabkov
d288a3d053 Remove alignment reqs from spi_flash_{read,write} 2016-12-15 10:07:31 +11:00
Angus Gratton
bab1d49f1f Merge branch 'feature/esptool_flash_encryption' into 'master'
Flash encryption support

Flash encryption support in build system, tooling

To come in future MR:
* On-device key generation on first boot (for production devices), need to finalise testing of bootloader entropy seeding.
* spi_flash_encrypted_write to support non-32-byte block writes (at least optionally.)
* I think a lot of the bootloader_support component can possibly be rolled into "spiflash" and other components, to use a common API.

See merge request !240
2016-12-12 06:50:46 +08:00
Angus Gratton
8ba75a1e9f SPI flash: Block erase size 64KB not 32KB
Reverts changes made in 9f9d92b2df
2016-12-09 14:18:58 +11:00
Angus Gratton
9eb135fd73 Flash encryption: Support enabling flash encryption in bootloader, app support
* App access functions are all flash encryption-aware
* Documentation for flash encryption
* Partition read/write is flash aware
* New encrypted write function
2016-12-01 23:49:12 -08:00
Angus Gratton
be53a6950c spi_flash_erase_range: Allow for 32KB blocks not 64KB blocks
SPI flash hardware sends 52h command, which is a 32KB erase.

There is a matching bug in the ROM SPIEraseArea code, unless
flashchip->block_size is modified first.
2016-11-24 18:05:06 +11:00
Ivan Grokhotkov
42827ff869 bootloader, menuconfig: add flash size setting support 2016-10-21 15:27:25 +11:00
Angus Gratton
feca308f1f rom/spi_flash.h: Remove first parameter of SPI_read_status_high()
Corrects the prototype to match the one compiled into ROM.
2016-10-21 10:44:05 +11:00
Wangjialin
41d397cf3f Only modify headers in soc/ .
Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-14 13:47:28 +08:00
Wu Jian Gang
04b53643ef header files: clean up
1. format;
2. Slow RTC memory reverse 2KB;
2016-09-12 17:47:50 +08:00
jack
24011ddd05 header files: modify rom code and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
2016-09-12 17:47:49 +08:00
Ivan Grokhotkov
bd6ea4393c Initial public version 2016-08-17 23:08:22 +08:00