Commit graph

44 commits

Author SHA1 Message Date
Wangjialin
10340d718f bugfix(typo): fix typo in rom/gpio.h 2017-07-17 15:41:02 +08:00
Ivan Grokhotkov
8ccb2a4990 esp32: make time monotonic across resets
Small changes to clock calibration value will cause increasing errors
the longer the device runs. Consider the case of deep sleep, assuming
that RTC counter is used for timekeeping:
- before sleep:
   time_before = rtc_counter * calibration_val
- after sleep:
   time_after = (rtc_counter + sleep_count) * (calibration_val + epsilon)
where 'epsilon' is a small estimation error of 'calibration_val'.
The apparent sleep duration thus will be:
time_after - time_before = sleep_count * (calibration_val + epsilon)
                           + rtc_counter * epsilon

Second term on the right hand side is the error in time difference
estimation, it is proportional to the total system runtime (rtc_counter).

To avoid this issue, this change makes RTC_SLOW_CLK calibration value
persistent across restarts. This allows the calibration value update to
be preformed, while keeping time after update same as before the update.
2017-06-16 12:06:04 +08:00
Tian Hao
377a1f5ea1 component/esp32 : do more fix of dualcore bug
1. the cache API in romcode will access DPORT register, so protect it.
2. fix STALL spelling.
3. check dport access by non-dport access function
2017-05-12 15:41:51 +08:00
Ivan Grokhotkov
15ec487fde Merge branch 'feature/esp32_d2wd_support' into 'master'
ESP32-D2WD support

Support ESP32-D2WD with integrated flash in ESP-IDF.

Includes fix for https://github.com/espressif/esp-idf/issues /521


See merge request !639
2017-04-14 20:57:39 +08:00
Angus Gratton
f7793840e1 bootloader: Add QIO support for ESP32-D2WD SPI flash 2017-04-13 17:55:47 +10:00
Angus Gratton
85e76a7cfc spiflash ROM functions: Remove Quad I/O mode enable/disable code from flash ROM functions
Confusion here is that original ROM has two functions:

* SPIReadModeCnfig() - sets mode, calls enable_qio_mode/disable_qio_mode
* SPIMasterReadModeCnfig() - As above, but doesn't set QIO mode in status register

However we never want to use the ROM method to set/clear QIO mode flag, as not all flash chips work this way. Instead we
do it in flash_qio_mode.c in bootloader.

So in both cases (ROM or "patched ROM") we now call SPIMasterReadModeCnfig(), which is now named
esp_rom_spiflash_config_readmode().
2017-04-13 17:54:42 +10:00
Ivan Grokhotkov
9edab21385 Merge branch 'feature/rtc_clk_impl' into 'master'
Introduce soc component, add source of rtc_clk and rtc_pm libraries

This MR adds parts of the RTC library source code (initialization, clock selection functions, sleep functions). WiFi-related power management functions are kept inside the precompiled library. Most of RTC library APIs have been renamed.

Default CPU frequency option in Kconfig is set to 160MHz, pending qualification of 240MHz mode at high temperatures.

Register header files are moved into the new soc component, which will contain chip-specific header files and low-level non-RTOS-aware APIs (such as rtc_ APIs). Some of the files from ESP32 component were also moved: cpu_util.c, brownout.c, and the corresponding header files. Further refactoring of ESP32 component into more meaningful layers (chip-specific low level functions; chip-specific RTOS aware functions; framework-specific RTOS-related functions) will be done in future MRs.

See merge request !633
2017-04-12 10:38:23 +08:00
Ivan Grokhotkov
7ee8ee8b7e soc: add source code of rtc_clk, rtc_pm 2017-04-11 15:45:54 +08:00
Alexey Gerenkov
0860f46220 spi_flash: Fixed bug in SPI flash ROM driver to work with embedded flash chip
1) fixed SPI_read_status: added check for flash busy flag in matrix mode
2) fixed SPI_page_program: enable write before writing data to SPI FIFO
3) SPI flash ROM funcs replacement is controlled via menuconfig option
2017-04-11 10:51:19 +08:00
Angus Gratton
68cba2a1fb Bootloader: Support switching to Quad I/O mode during boot process 2017-02-09 08:44:05 +11:00
Angus Gratton
e53d307814 Panic handler: Use same reset path as esp_restart(), disabling hardware
Closes #223 https://github.com/espressif/esp-idf/issues/223
2017-01-13 14:37:36 +11:00
Ivan Grokhotkov
b24ac487cb newlib: use RTC_STORE registers to keep boot time instead of RTC_SLOW_MEM
This allows RTC_SLOW_MEM to be powered down in deep sleep if no other variables are placed into RTC_SLOW_MEM.
2017-01-12 14:43:34 +08:00
Ivan Grokhotkov
e4811216ff deep sleep: fix regression due to moving ets_update_cpu_frequency into IRAM
Deep sleep stub may call ets_update_cpu_frequency, which has been moved from ROM to IRAM.
Restore the ROM version in the linker script, call it ets_update_cpu_frequency_rom, use it in the deep sleep stub.
2017-01-12 14:15:25 +08:00
Deomid Ryabkov
d288a3d053 Remove alignment reqs from spi_flash_{read,write} 2016-12-15 10:07:31 +11:00
Angus Gratton
bab1d49f1f Merge branch 'feature/esptool_flash_encryption' into 'master'
Flash encryption support

Flash encryption support in build system, tooling

To come in future MR:
* On-device key generation on first boot (for production devices), need to finalise testing of bootloader entropy seeding.
* spi_flash_encrypted_write to support non-32-byte block writes (at least optionally.)
* I think a lot of the bootloader_support component can possibly be rolled into "spiflash" and other components, to use a common API.

See merge request !240
2016-12-12 06:50:46 +08:00
Angus Gratton
8ba75a1e9f SPI flash: Block erase size 64KB not 32KB
Reverts changes made in 9f9d92b2df
2016-12-09 14:18:58 +11:00
Ivan Grokhotkov
b57aecdfe9 uart_tx_wait_idle: fix issue with last character not transmitted
- ROM function uart_tx_wait_idle may have a bug which causes the function to return before the final character is fully transmitted.
  This replaces uart_tx_wait_idle declaration with a static inline definition which fixes the issue.
- Also replaces the use of uart_tx_flush with uart_tx_wait_idle in esp_restart, to remove garbage in console output on restart.
- rtc_printf is temporary replaced with a no-op, pending a new release of librtc.a. Current release assumes that UART0 is used for output,
  and switches UART0 baud rate while doing frequency changes and printing some log output. This doesn’t work if a different UART is used for output.
2016-12-08 01:42:37 +08:00
Angus Gratton
9eb135fd73 Flash encryption: Support enabling flash encryption in bootloader, app support
* App access functions are all flash encryption-aware
* Documentation for flash encryption
* Partition read/write is flash aware
* New encrypted write function
2016-12-01 23:49:12 -08:00
Angus Gratton
d0801fdbab Merge branch 'feature/sha_tls_integration' into 'master'
SHA acceleration integrated to mbedTLS incl. TLS sessions

Uses hardware SHA acceleration where available, fails over to software where not available.

Ref TW7112

See merge request !232
2016-11-25 10:12:29 +08:00
Angus Gratton
9f9d92b2df Merge branch 'bugfix/spi_flash_region' into 'master'
spi_flash_erase_range: Allow for 32KB blocks not 64KB blocks

SPI flash hardware sends 52h command, which is a 32KB erase.

There is a matching bug in the ROM SPIEraseArea code, unless
flashchip->block_size is modified first.

See merge request !249
2016-11-25 10:11:51 +08:00
Angus Gratton
be53a6950c spi_flash_erase_range: Allow for 32KB blocks not 64KB blocks
SPI flash hardware sends 52h command, which is a 32KB erase.

There is a matching bug in the ROM SPIEraseArea code, unless
flashchip->block_size is modified first.
2016-11-24 18:05:06 +11:00
Ivan Grokhotkov
df6edb50e9 implement esp_deep_sleep, fix build issues 2016-11-22 21:54:49 +08:00
Ivan Grokhotkov
2393d829de remove legacy definitions from esp_types.h 2016-11-22 21:14:36 +08:00
Angus Gratton
c48612e516 mbedTLS SHA acceleration: Allow concurrent digest calculation, works with TLS
SHA hardware allows each of SHA1, SHA256, SHA384&SHA512 to calculate digests
concurrently.

Currently incompatible with AES acceleration due to a hardware reset problem.

Ref TW7111.
2016-11-22 20:42:38 +11:00
Angus Gratton
aceb6517c0 Refactor existing bootloader common functionality into bootloader_support component 2016-11-02 17:58:41 +11:00
Ivan Grokhotkov
42827ff869 bootloader, menuconfig: add flash size setting support 2016-10-21 15:27:25 +11:00
Angus Gratton
feca308f1f rom/spi_flash.h: Remove first parameter of SPI_read_status_high()
Corrects the prototype to match the one compiled into ROM.
2016-10-21 10:44:05 +11:00
jack
4e092be6d6 Add Comments
We reserve 4KB Slow RTC memory to save RF calibation result and BT NVS data.
If not all these Slow RTC momory Blocks are used, we will open the other parts.
2016-09-29 16:29:13 +08:00
xiaxiaotian
ec03c31ec4 1. Change the deep sleep stub code to fix wake bug. 2016-09-28 11:52:39 +08:00
Angus Gratton
7c494055e3 esp32: Bootloader wake deep sleep stub
App can contain a stub program resident in RTC fast memory. Bootloader
will load the stub on initial boot. If the device wakes from deep sleep,
the stub is run immediately (before any other data is loaded, etc.)

To implement a custom wake stub, implement a function in your program:

```
void RTC_IRAM_ATTR esp_wake_deep_sleep(void)
{
  esp_default_wake_deep_sleep();
  // other wake logic
}
```

... and it will replace the default implementation.
2016-09-28 11:14:58 +08:00
Angus Gratton
6cffb5d8b4 rom/gpio.h: Use new GPIO_PIN0_REG register name
Closes github #12
2016-09-16 09:43:52 +10:00
Wu Jian Gang
2efaf42253 Merge remote-tracking branch 'origin/feature/mbedtls' 2016-09-14 18:05:56 +08:00
Wangjialin
41d397cf3f Only modify headers in soc/ .
Pass compiling under esp-idf-tests/merge_soc_tmp/merge_for_soc_headers branch.(only change some names of register and INUM).
2016-09-14 13:47:28 +08:00
Wu Jian Gang
b56098a612 Merge remote-tracking branch 'origin/master' into feature/mbedtls 2016-09-13 16:31:48 +08:00
Jack
bd8febe58c add MACRO to get flash pad number from efuse value 2016-09-12 17:47:50 +08:00
Wu Jian Gang
04b53643ef header files: clean up
1. format;
2. Slow RTC memory reverse 2KB;
2016-09-12 17:47:50 +08:00
jack
24011ddd05 header files: modify rom code and soc header files
1. timer reg file for both time group 0 and time group 1, not only timer group 0
2. fix bug that io mux header file mismatch with chip
3. fix bug that some BASE address not correct
4. add some static function to eagle.fpga32.rom.addr.v7.ld
5. add interrupts usage table
6. add some comments for rom code functions
2016-09-12 17:47:49 +08:00
Angus Gratton
2580c07ae6 esp32 hwcrypto: Make SHA-224 an obvious no-op for now
This is not the long term solution...
2016-09-08 16:47:28 +08:00
Angus Gratton
2bee84062a esp32: Add comment to ROM crypto functions recommending they not be used directly 2016-09-08 16:47:24 +08:00
Angus Gratton
2f54d0e425 Merge wifi branch commit '588d384393536a040f899b382890316c56061b6a' into feature/wifi-stage-one 2016-09-02 11:14:27 +10:00
Angus Gratton
a825fe8703 md5_hash.h: Replace outdated use of c_types.h with stdint 2016-09-01 08:58:29 +10:00
rudi ;-)
fa310016dd Update aes.h
found small mistake in it

we have:

PROVIDE ( ets_aes_crypt = 0x4005c9b8 );
PROVIDE ( ets_aes_disable = 0x4005c8f8 );
PROVIDE ( ets_aes_enable = 0x4005c8cc );
PROVIDE ( ets_aes_set_endian = 0x4005c928 );
PROVIDE ( ets_aes_setkey_dec = 0x4005c994 );
PROVIDE ( ets_aes_setkey_enc = 0x4005c97c );

Signed-off-by: Ivan Grokhotkov <ivan@espressif.com>
2016-08-27 22:17:23 +08:00
liuzhifu
ebfb8547d2 Implement ETS_INTR_ENABLE/ETS_INTR_DISABLE with xt_ints_on/xt_ints_off 2016-08-26 19:03:51 +08:00
Ivan Grokhotkov
bd6ea4393c Initial public version 2016-08-17 23:08:22 +08:00