Commit graph

107 commits

Author SHA1 Message Date
kooho
492db0591d Fix uart fifo overflow bug 2018-01-12 14:42:54 +08:00
Ivan Grokhotkov
914ab07567 Merge branch 'feature/ulp_i2c_reg' into 'master'
soc,ulp: add register definitions of RTC_I2C peripheral

See merge request !1762
2018-01-11 12:08:25 +08:00
Deng Xin
337f790fd3 bug fix of assert happen in PSRAM 2018-01-09 20:01:06 +08:00
Ivan Grokhotkov
dba291416f soc,ulp: add register definitions of RTC_I2C peripheral 2018-01-08 21:28:14 +08:00
Angus Gratton
c69af42b96 esp32: Fix backwards compatibility for pre-v2.1 bootloaders
Older bootloaders don't set RTC_XTAL_FREQ_REG or call rtc_clk_init(),
app needs to pick this up.

Reported at
https://esp32.com/viewtopic.php?f=2&t=3939&p=17836
2017-12-18 13:45:57 +11:00
Ivan Grokhotkov
a99483a727 docs: add information about execution time of ULP instructions 2017-12-11 14:05:41 +08:00
Ivan Grokhotkov
ca751648fa ulp: document the need to wait for RTC to be ready for wakeup 2017-12-11 12:11:46 +08:00
krzychb
421592a8eb LEDC Driver: Added back original definitions of 'duty_resolution' and 'clock_divider'. This update is to provide backward compatibility with ESP-IDF 2.1. 2017-12-04 21:12:56 +01:00
Jiang Jiang Jian
c672fc54fd Merge branch 'feature/ledc_more_meaningful_parameter_names' into 'master'
Provided more meaningful parameter names by renaming 'bit_num' to 'duty_resoluti…

See merge request !1440
2017-12-01 19:33:53 +08:00
Vitor Massaru Iha
cf768380b1 soc: Remove redefinition of MCU_SEL_M
Signed-off-by: Vitor Massaru Iha <vitor@massaru.org>

Merges #1290
2017-11-22 11:01:42 +08:00
Ivan Grokhotkov
3369f15fa3 soc/rtc: don't power down BIAS_I2C along with APLL if other PLL is used
If enable == false, and SOC_CLK_SEL == PLL, the code would would
erroneously set RTC_CNTL_BIAS_I2C_FORCE_PD. This change fixes the logic.
2017-11-20 15:27:16 +08:00
krzychb
d488bb7bac Provided more meaningful parameter names by renaming 'bit_num' to 'duty_resolution' and 'div_num' to 'clock_divider' 2017-11-15 08:08:12 +01:00
Ivan Grokhotkov
f22c681c1c soc/rtc: raise core voltage when 80MHz flash frequency is used
To achieve reliable operation with GD flash at 80MHz, need to raise
core voltage.
This causes the following current consumption increase:

At 80MHz: from 29mA to 33mA
At 160MHz: from 41mA to 47mA

Test conditions: 2 cores running code from IRAM, remaining peripherals
clock gated.
2017-11-08 21:13:02 +08:00
Jiang Jiang Jian
abacf8d2a0 Merge branch 'bugfix/rtc_and_restart_fixes' into 'master'
rtc_clk and esp_restart fixes

See merge request !1458
2017-11-04 01:34:38 +08:00
Ivan Grokhotkov
a02b30ccda efuse: add package definitions for PICOD2/D4 2017-11-03 15:49:10 +08:00
Ivan Grokhotkov
fb9c106bcb soc/rtc: add function to get/set VDDSDIO configuration
Also consider case of VDDSDIO force powered on in rtc_sleep.
2017-11-03 15:49:09 +08:00
Ivan Grokhotkov
5a294c9acd soc/gpio: fix description of GPIO_STRAP_REG 2017-11-03 15:49:09 +08:00
Ivan Grokhotkov
80eb3b6ddb Merge branch 'bugfix/light_sleep_current' into 'master'
soc/rtc: fix increased current consumption in light sleep

See merge request !1483
2017-11-02 18:26:23 +08:00
XiaXiaotian
42cefc173f refractor WiFi clock setting
Do not set WiFi clock in PHY initializing function, move it to WiFi
   start/stop function.
2017-11-02 15:24:21 +08:00
wangmengyang
bd6394db92 component/bt: clean up WIFI_CLK_EN_REG settings for Bluetooth
1. move settings of WIFI_CLK_EN_REG for bluetooth into controller init/deinit APIs
2. modify the bit mask used in phy_rf init/deinit to use WIFI-BT shared bits
2017-11-02 15:24:21 +08:00
Ivan Grokhotkov
9bfb45aa1d soc/rtc: fix increased current consumption in light sleep
This fixes a configuration issue of RTC, which caused light sleep current
to be 1.35mA instead of 0.85mA.
2017-11-02 13:57:26 +08:00
Ivan Grokhotkov
eb5752c635 esp_restart: fix possible race while stalling other CPU, enable WDT early
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.

With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.

In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
f11ad0c904 soc/rtc: fix spurious warnings about XTAL frequency on startup
1. Make sure that 8MD256 clock used to estimate XTAL frequency is enabled
   before trying to use rtc_clk_cal_ratio.
   This fixes "Bogus XTAL frequency: 0 MHz" warnings after software reset.

2. Don't call rtc_clk_xtal_freq_estimate if XTAL frequency is already
   known. This reduces startup time after deep sleep or software reset.

3. Compare known XTAL frequency and estimated one before printing a
   warning. This fixes "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting
   (40MHz). Detected 40 MHz." warnings.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
9317cb3434 soc/rtc: add tests for CPU frequency switching
These tests switch between PLL and XTAL frequencies for 10 seconds.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
6d4ed4ff6c soc/rtc: wait for SLOW_CLK cycle when switching CPU clock
Previous implementation waited for 20us after setting
RTC_CNTL_SOC_CLK_SEL_XTL register, using ets_delay_us, assuming that
the CPU was running at XTAL frequency. In reality, clock switch happened
on the next RTC_SLOW_CLK cycle, and CPU could be running at the previous
frequency (for example, 240 MHz) until then.
ets_delay_us would wait for 20 us * 40 cycles per us = 800 CPU cycles
(assuming 40 MHz XTAL; even less with a 26 MHz XTAL).
But if CPU was running at 240 MHz, 800 cycles would pass in just 3.3us,
while SLOW_CLK cycle could happen as much as 1/150kHz = 6.7us after
RTC_CNTL_SOC_CLK_SEL_XTL was set. So the software would not actually wait
long enough for the clock switch to happen, and would disable the PLL
while CPU was still clocked from PLL, leading to a halt.

This implementation uses rtc_clk_wait_for_slow_cycle() function to wait
until the clock switch, removing the need to wait for a fixed number of
CPU cycles.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
05a0fbd49b soc/rtc: add a function to wait for slow clock cycle
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
2017-10-26 19:53:53 +08:00
esp32de
7c0020bfd0 feat(adc2): append adc2 support and api and the lock with WIFI module
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
2017-10-26 14:35:29 +08:00
Ivan Grokhotkov
59b7d98fec Merge branch 'feature/dfs' into 'master'
Dynamic frequency scaling

See merge request !1189
2017-10-22 12:34:11 +08:00
Ivan Grokhotkov
b6f37bda97 Merge branch 'feature/i2s_built_in_adc' into 'master'
feature(I2S-ADC): add ADC mode for I2S.

See merge request !1077
2017-10-20 15:52:56 +08:00
Ivan Grokhotkov
099565635b soc: correct values of SOC_BYTE_ACCESSIBLE_LOW, SOC_MEM_INTERNAL_LOW
Internal byte accessible memory starts with Internal ROM 1 at 0x3FF90000.
Region of RTC fast memory starting at 0x3FF80000 is not used in IDF as
it is mapped to PRO CPU only.
2017-10-19 21:35:21 +08:00
Ivan Grokhotkov
fba9678c56 uart: add support for REF_TICK 2017-10-18 14:19:20 +08:00
Ivan Grokhotkov
b03e08dc4e soc/rtc: add function to convert CPU frequency in MHz to rtc_cpu_freq_t 2017-10-18 14:19:15 +08:00
Ivan Grokhotkov
a242ae6d0b soc/rtc: add fast paths for switching between PLL and XTAL 2017-10-18 14:19:14 +08:00
Jeroen Domburg
740f8a79f0 Add logic to make external RAM usable with malloc() 2017-09-28 17:17:50 +08:00
michael
9d9e771933 fix(global, log): fix esp_log(_early)_timestamp readings after startup by correct the CCOUNT register when switching CPU clock.
TW#13332, Closes #700
2017-09-26 15:18:17 +08:00
Tian Hao
3e2ee24e4f component/bt : support bluetooth controller DRAM release dynamically
1. remove CONFIG_BT_DRAM_RELEASE from Kconfig
2. add API to release bluetooth controller DRAM to heap
2017-09-21 14:31:20 +08:00
michael
8244fa95fe feat(log): add new function to log buffer with level and hex dump. 2017-09-18 11:44:54 +08:00
Wangjialin
2fceec4d85 feature(I2S-ADC): add ADC mode for I2S.
1. Support built-in ADC for I2S.
2. Modify code of ADC, made no change to the original APIs.
3. Add APIs in I2S:
esp_err_t i2s_set_adc_mode(adc_unit_t adc_unit, adc1_channel_t adc_channel);
4. Add I2S ADC/DAC example code.
5. add old-fashion definition to make it more compatible
6. replase spi_flash_ APIs with esp_partition_ APIs
7. add example of generating audio table from wav
8. change example sound
2017-09-14 13:24:08 +08:00
Jeroen Domburg
875ae6a134 Add option to allocate external RAM using heap_alloc_caps 2017-09-14 10:47:44 +08:00
Ivan Grokhotkov
1e7c3854d3 Merge branch 'bugfix/warn_on_invalid_xtal_freq' into 'master'
soc/rtc: warn if detected XTAL frequency does not match configured one

See merge request !1242
2017-09-11 18:15:11 +08:00
Ivan Grokhotkov
5a88f90a33 soc/rtc: warn if detected XTAL frequency does not match configured one
Since 9a8c0392, XTAL frequency is set to 40MHz by default, and users
of 26MHz boards need to select 26MHz manually. Most users are not aware
of this change, and existing getting started guides do not mention that
XTAL frequency needs to be set for some boards. So users are left with
garbage output from UART without any clue what to check.

This change adds a warning in case specific XTAL frequency was set, and
it does not match automatically detected one. This should help users
fix the issue.
2017-09-11 11:42:26 +08:00
michael
08b9fbc242 feat(global): add macros for GPIO->channel lookup
including: macros for dac, adc, touch, rtc_gpio, uart and clk_out.

TW#13970
2017-09-07 10:40:25 +08:00
Jeroen Domburg
34372a091c Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00
Ivan Grokhotkov
5666fc0a56 Merge branch 'feature/esp_timer_improvements' into 'master'
esp_timer improvements

See merge request !1172
2017-09-01 16:14:01 +08:00
Ivan Grokhotkov
d2acf1ce77 sleep: add light sleep, factor out APIs common for deep/light sleep 2017-09-01 10:36:14 +08:00
Ivan Grokhotkov
f8b719d911 soc/rtc: add sleep flag to control powerdown of VDD_SDIO 2017-09-01 10:36:14 +08:00
Ivan Grokhotkov
c743bdac88 soc/rtc: round APB clock frequency to nearest MHz 2017-09-01 10:34:36 +08:00
Ivan Grokhotkov
a25eb825e1 Merge branch 'bugfix/dport_protect_crypto' into 'master'
add protection for crypto registers in DPORT

See merge request !928
2017-08-30 11:45:35 +08:00
Ivan Grokhotkov
547ef83020 Merge branch 'feature/disable_some_perip_clk_when_cpu_start' into 'master'
Disable some peripheral clocks when cpu starts

See merge request !1089
2017-08-30 11:43:38 +08:00
XiaXiaotian
4776f73ca4 Disable some peripheral clocks when cpu starts
All peripheral clocks are default enabled after chip is powered on.
    When CPU starts, if reset reason is CPU reset, disable those clocks
    that are not enabled before reset. Otherwise, disable all those
    useless clocks.
    These peripheral clocks must be enabled when the peripherals are
    initialized and disabled when they are deinitialized.
2017-08-29 11:18:42 +08:00