Commit graph

7 commits

Author SHA1 Message Date
chenjianqiang
80c013ee5a bugfix(psram): fix the error that two macro definitions are undeclared
1. add definition of FLASH_ID_GD25LQ32C
2. modify DPORT_SPI3_CLK_EN as DPORT_SPI_CLK_EN_2
2018-10-10 20:21:01 +08:00
chenjianqiang
8cfb0b207a bugfix(psram): fix psram driver
1. remove use EID to distinguish psram voltage
2. 1V8 64Mbit psram and 3V3 64Mbit psram use the same psram driver(standard spi interface)
3. set cs hold time register as 1
2018-10-10 15:51:18 +08:00
Wangjialin
6d253b4394 feature(psram): add support for 64MBit psram of 1.8v and 3.3v.
1. Add reading psram EID.
2. Configure different clock mode for different EID.
3. add API to get psram size and voltage.
4. Remove unnecessary VSPI claim.

For 32MBit@1.8V and 64MBit@3.3V psram, there should be 2 extra clock cycles after CS get high level.
For 64MBit@1.8 psram, we can just use standard SPI protocol to drive the psram. We also need to increase the HOLD time for CS in this case.

EID for psram:
32MBit 1.8v: 0x20
64MBit 1.8v: 0x26
64MBit 3.3v: 0x46
2018-10-10 15:43:30 +08:00
Jeroen Domburg
41baf59287 Fix the clock subsystem so it doesn't undo the weird condition spiram_psram.c jams the enable/reset bits of SPI3 in when 80MHz mode is selected anymore 2017-12-27 16:54:26 +08:00
Wangjialin
cea7dfbe90 psram: improve clock signal generation, increase drive strength
Also check the chip type when initializing.
2017-11-03 16:30:10 +08:00
Jeroen Domburg
6d95934a3c Make 80MHz PSRAM work as well, add testcase for weirdness reported on esp32 forums, clean up unused define in psram code 2017-09-14 10:47:44 +08:00
Jeroen Domburg
34372a091c Add initial SPI RAM support. This adds support for an ESP-PSRAM32 chip connected to the default flash pins and GPIO 16 and 17. The RAM is mapped to address 0x3F800000, but otherwise ignored by esp-idf as of yet. 2017-09-04 12:05:49 +08:00