fixes for issues observed when using spi_flash
This MR fixes three unrelated issues:
- Race condition in spi_flash_enable_interrupts_caches_and_other_cpu
when operations on unpinned tasks are performed.
The issue is reported in https://github.com/espressif/esp-idf/pull/258
- esp_intr_noniram_disable doesn’t disable interrupts when compiled in
release mode. This issue manifested itself with an illegal instruction
exception when task WDT ISR was called at the time when flash was
disabled.
Fixes https://github.com/espressif/esp-idf/issues/263.
- Tick hooks on CPU1 were not called if CPU0 scheduler was disabled for
significant amount of time (which could happen when doing flash erase).
The issue manifested itself as “INT WDT timeout on core 1” error.
Fixes https://github.com/espressif/esp-idf/issues/219.
See merge request !441
The block which dispatches ticks on CPU1 was a copy of the code block
for the normal path (CPU0). It used to check uxPendedTicks, with the
logic that uxPendedTicks can be 0 iff the scheduler is not suspended.
On CPU1 however, uxPendedTicks is not related to the state of the
scheduler (as uxPendedTicks is updated on CPU0). Due to this, if CPU0
scheduler was suspended, and uxPendedTicks happened to be nonzero,
tick hooks on CPU1 didn’t run, even though CPU1 scheduler was working.
This change removes the check for uxPendedTicks in CPU1 code path,
so that the tick hooks on CPU1 always get called (as for the CPU0 code
path).
The following issues mentioned during MR!341 review were fixed:
1) Core dump test application description
2) Usage of CONFIG_ESP32_ENABLE_COREDUMP_TO_FLASH and CONFIG_ESP32_ENABLE_COREDUMP_TO_UART
3) FLASH_GUARD_START macro usage is fixed in flash API
4) Core dump module logging facility
5) cache util functions doc updated
6) interactive delay before print core dump to uart
7) core dump partion support in build system
1) PS is fixed up to allow GDB backtrace to work properly
2) MR!341 discussion: in core dump module: esp_panicPutXXX was replaced by ets_printf.
3) MR!341 discussion: core dump flash magic number was changed.
4) MR!341 discussion: SPI flash access API was redesigned to allow flexible critical section management.
5) test app for core dump feature was added
6) fixed base64 file reading issues on Windows platform
7) now raw bin core file is deleted upon core loader failure by epscoredump.py
Complimentary changes:
1) Partition table definitions files with core dump partition
2) Special sub-type for core dump partition
3) Special version of spi_flash_xxx
4) espcoredump.py is script to get core dump from flash and print useful info
5) FreeRTOS API was extended to get tasks snapshots
1. Update wifi lib which contains ampdu and other optimizations
2. Add throughput code debug code
3. Other misc modification about throughput optimization
This commit fixes:
1. xTaskGetCurrentTaskHandle may return wrong TCB when current task switch to a different core
2. Idle task may have problem when it terminate the task in both core
Minor fixes from various sources
- Fix memory debugging code. Noticed by Tuan.
- intr_enable/disable should be in IRAM. Noticed by rojer
- Still old timer code in examples in doxygen comments. Noticed on the forum by jumjum123
- Timer example was broken. Noticed on the forum by jumjum123
See merge request !325
“Full” printf uses more stack space than “nano” printf, and more space than available in the idle task.
This caused stack overflow in TLS delete test. Replacing printf with ets_printf.
Refs:
http://esp32.com/viewtopic.php?f=13&t=550http://esp32.com/viewtopic.php?f=13&t=551
rmt.c should include stdlib.h for malloc, esp_bignum,c &
https_request_main.c for abort().
FreeRTOSConfig.h is only including stdlib if
CONFIG_FREERTOS_ASSERT_ON_UNTESTED_FUNCTION is set. However, it is
included for abort() so needs to be included whenever
CONFIG_FREERTOS_ASSERT_FAIL_ABORT is set.
This change includes unconditionally in FreeRTOSConfig.h. This is to
avoid this kind of bug where compiler errors are dependent on config. I
suggest we don't change this to be more selective until we have 'make
randomconfig' style tests in CI.
Integrate unit tests into build system
This MR moves unit tests from esp-idf-tests repository into 'test' subdirectories of respective components.
Tests are run using a runner app in tools/unit-test-app.
This needs a bit of cleanup:
1. remove extra newlines added to makefiles,
2. re-format unit tests code which has tabs
3. write a document on using this test app
4. maybe some refactoring in project.mk
I think 1&2&4 need to be done in this MR, while 3 may be done in a follow-up one.
See merge request !221
Includes a tweak to make Static_task_t equal size to TCB_t when using
MPU_WRAPPERS . Matches tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE macro
in tasks.c. This isn't actually a bug (if static task allocation is off,
there is no use for Static_task_t), but it allows us to make consistent
compile-time checks that Static_task_t == TCB_t.
Without this change, building FreeRTOS with static allocation enabled succeeds, but trying to create a queue from a static buffer causes an assert because the size of static and dynamic queues differ.
rename nvs host test folder, modify .gitlab-ci.yml
remove unit-test-app build
re-format unit test files
remove extra newlines in project.mk
some refactoring for unit test part in project.mk
add build files of unit-test-app in gitignore
add README.md for unit test app
correct headings in README.md
remove files and make minor tweaks in unit test app
update .gitlab-ci.yml to use unit test app
delete unused lines in component_wrapper.mk
delete periph_i2s.h and lcd test
add text floating point in components/esp32/test/Kconfig
correct idf test build paths in .gitlab-ci.yml
Default esp-idf builds now show -Wextra warnings (except for a few:
signed/unsigned comparison, unused parameters, old-style C declarations.)
CI building of examples runs with that level raised to -Werror, to catch
those changes going into the main repo.
Per-CPU interrupt handlers and args
Up to now, the interrupt handlers and args were shared between CPUs, that is, if you set an interrupt handler on CPU0, CPU1 would invoke the same interrupt handler on that interrupt. This code gives every CPU its own space for interrupt handlers.
See merge request !192
