Commit graph

1904 commits

Author SHA1 Message Date
Ivan Grokhotkov
7304651320 esp32: use semaphore in FP switch test, raise worker task priority 2020-02-10 13:36:43 +01:00
Angus Gratton
11fac8637a docs: Resolve doxygen & Sphinx warnings 2020-02-07 16:37:45 +11:00
Konstantin Kondrashov
739eb05bb9 esp32: add implementation of esp_timer based on TG0 LAC timer
Closes: IDF-979
2020-02-06 14:00:18 +08:00
Ivan Grokhotkov
41631587f8 Merge branch 'feature/esp32s2_brownout' into 'master'
esp32s2: add brownout detector support

Closes IDF-751

See merge request espressif/esp-idf!7428
2020-02-04 17:00:46 +08:00
Felipe Neves
429712c6eb freertos: moved all xtensa specific files into a separated folder 2020-01-27 16:05:30 -03:00
Ivan Grokhotkov
caef7ad9f2 esp32, esp32s2beta: move brownout.c to esp_common 2020-01-23 13:44:19 +01:00
Ivan Grokhotkov
70752baba4 esp32s2: add brownout detector support
1. add brownout detector HAL for esp32 and esp32s2
2. enable brownout reset for esp32 rev. 1 and above
3. add approximate brownout detector levels for esp32s2
2020-01-23 13:44:19 +01:00
Ivan Grokhotkov
cbb84e8f5e esp32s2: fix THREADPTR calculation, re-enable FreeRTOS TLS tests
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.

2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.

Full explanation of the calculation below.

Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).

At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:

THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)

The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to

THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).

The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.

Closes IDF-1239
2020-01-23 11:29:22 +01:00
Angus Gratton
d672809080 Merge branch 'refactor/rename_esp32s2beta_to_esp32s2' into 'master'
global: rename esp32s2beta to esp32s2

See merge request espressif/esp-idf!7369
2020-01-23 09:16:30 +08:00
KonstantinKondrashov
6061d5d65a esp_timer/esp32: Fix case when alarm_reg > counter_reg but FRC_TIMER_INT_STATUS is not set
Closes: WIFI-1576
Closes: https://github.com/espressif/esp-idf/issues/2954
2020-01-22 14:30:34 +08:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
morris
e1f9b283bc esp32s2: mac addr allocation 2020-01-14 15:19:38 +08:00
Ivan Grokhotkov
a559014ff0 Merge branch 'bugfix/coredump_bin_fmt_ver_update' into 'master'
Fixes coredump compatibility with legacy binary core dumps

See merge request espressif/esp-idf!6794
2020-01-10 10:04:17 +08:00
Angus Gratton
459b3195ac esp_wifi: Move esp32 DPORT access wrappers into esp_wifi component 2020-01-08 18:23:29 +11:00
Angus Gratton
65dad0d46f build system: Remove some dependencies from esp32 & esp32s2beta
Possible now that wifi related source files are all in esp_wifi
2020-01-08 18:13:12 +11:00
Angus Gratton
f616d2f2de esp_wifi: Move wifi OS adapter structures into esp_wifi component 2020-01-08 18:13:12 +11:00
Ivan Grokhotkov
43de2cc84c test: add a (non-automated) case for backtraces with ROM functions 2020-01-02 18:50:32 +01:00
Ivan Grokhotkov
f52952cb45 esp32: panic: do digital reset if cache error interrupt is set
Even if frame->exccause != PANIC_RSN_CACHEERR, it is possible that
the cache error interrupt status is set. For example, this may happen
due to an invalid cache access in the panic handler itself.
Check cache error interrupt status instead of frame->exccause to
decide whether to do CPU reset or digital reset.

Also remove unnecessary esp_dport_access_int_pause from
esp_cache_err_get_cpuid, since the panic handler already calls
esp_dport_access_int_abort on entry.
2019-12-30 09:49:07 +01:00
liu zhifu
e1eeef2276 esp_wifi: fix a WiFi receiving bug
Support WiFi/BT MAC register writting when the WiFi/BT common clock is disabled.
2019-12-24 21:32:03 +08:00
Ivan Grokhotkov
f687cedebe Merge branch 'bugfix/wa_dport_and_intr' into 'master'
esp32: Fix for DPORT

See merge request espressif/esp-idf!7070
2019-12-24 01:30:56 +08:00
michael
3d1ec3f451 intr_alloc: fix the issue intr_enable/disable cannot be used in ISR in
esp32s2beta.

This issue is reported in config freertos_compliance_s2.
2019-12-23 10:23:00 +08:00
KonstantinKondrashov
9432ebddf9 esp32: Add UT for DPORT 2019-12-21 14:10:38 +00:00
KonstantinKondrashov
c4dcf6f917 esp32: Fix esp_dport_access_reg_read 2019-12-21 14:10:38 +00:00
Ivan Grokhotkov
2b6c85e182 intr_alloc: don't call ESP_LOG from a critical section
Calling ESP_LOG from a critical section leads to abort() in 4.1, and
may also randomly abort() in earlier versions.

Closes FCS-268
2019-12-18 10:11:24 +01:00
Angus Gratton
f7b51c164d Merge branch 'bufgix/esp_timer_set_alarm' into 'master'
esp_timer: Fix set_alarm. Case when timestamp < now_time

Closes WIFI-1511

See merge request espressif/esp-idf!6960
2019-12-16 13:39:44 +08:00
KonstantinKondrashov
ada09f8fad esp_timer: Add Test case when set_alarm needs set timer < now_time 2019-12-13 13:51:47 +08:00
KonstantinKondrashov
e6223440b3 esp_timer: Fix set_alarm. Case when timestamp < now_time
arg1 = MAX(int64_t arg1, uint64_t arg2) gave the wrong result, if arg1 < 0, it was presented as a larger value.
And ALARM_REG = (uin32_t)arg1. This leads to an infinite loop.
Fixed: both args are int64_t.

Closes: WIFI-1511
2019-12-12 14:02:26 +08:00
Marius Vikhammer
c63684cf6c hw crypto: activated hardware acceleration for esp32s2beta
Activated AES, RSA and SHA hardware acceleration for esp32s2 and enabled related unit tests.

Updated with changes made for ESP32 from 0a04034, 961f59f and caea288.

Added performance targets for esp32s2beta

Closes IDF-757
2019-12-12 12:37:29 +08:00
Jack
134a627ad8 esp_wifi: fix WiFi scan and connect bugs when coexist with Bluetooth
1. Fix WiFi scan leads to poor performance of Bluetooth.
2. Improve WiFi connect success ratio when coexist with Bluetooth.
3. Check if WiFi is still connected when CSA or beacon timeout happen.
4. add coex pre init
2019-12-02 18:20:40 +08:00
Alexey Gerenkov
e092d6f858 coredump: Makes compatible with legacy binary core dumps
Also:
 - improves coredump versioning scheme
 - Moves some API funtions to respective flash/UART dependent code
2019-11-25 22:44:51 +03:00
Angus Gratton
b7b4cd3418 Merge branch 'bugfix/timer_group_reset_ut' into 'master'
timer: remove check for POWERON_RESET in the test case, add esp_reset_reason API for s2beta

See merge request espressif/esp-idf!6747
2019-11-23 14:04:41 +08:00
Angus Gratton
ea29c101cd Merge branch 'bugfix/fix_iram_intr_alloc_test' into 'master'
ccomp_timer: fix broken unit test

See merge request espressif/esp-idf!6779
2019-11-22 08:41:50 +08:00
Ivan Grokhotkov
477e66103c Merge branch 'feature/esp32s2beta_apptrace_port' into 'master'
esp32s2: Adds apptrace support

Closes IDF-510 and IDF-1032

See merge request espressif/esp-idf!5610
2019-11-22 05:33:35 +08:00
Ivan Grokhotkov
ad986849a6 timer: remove check for POWERON_RESET in the test case
The test case may run after an RTC_WDT_RESET (if we are on rev. 0
ESP32), or software reset (when running test cases locally).

Also moving the test case next to the other timer group driver tests.
2019-11-21 20:03:26 +01:00
Mahavir Jain
43411da465 Merge branch 'bugfix/freertos_critical_section_compliance' into 'master'
Changes in uart and esp_timer for critical section compliance with vanilla FreeRTOS

See merge request espressif/esp-idf!6733
2019-11-21 19:25:14 +08:00
chenjianqiang
9f9da9ec96 feat(timer): refator timer group driver
1. add hal and low-level layer for timer group
2. add callback functions to handle interrupt
3. add timer deinit function
4. add timer spinlock take function
2019-11-21 14:14:19 +08:00
fuzhibo
0c2bf7c8bc rtcio: add hal for driver 2019-11-21 10:40:49 +08:00
suda-morris
e673817530 ccomp_timer: fix broken unit test 2019-11-21 08:45:11 +08:00
Angus Gratton
bc9267aa24 Merge branch 'feature/use_cpu_time_for_tests' into 'master'
Cache compensated timer

See merge request espressif/esp-idf!6087
2019-11-20 08:33:27 +08:00
Ivan Grokhotkov
a74988ae3b Merge branch 'bugfix/cpp_extern' into 'master'
Add extern C header guards to some files

Closes IDFGH-2025 and IDFGH-2093

See merge request espressif/esp-idf!6611
2019-11-19 19:01:29 +08:00
Renz Christian Bagaporo
df26ab13e2 test_utils: implement performance timer 2019-11-18 10:29:01 +08:00
Mahavir Jain
d0a37704a3 esp_timer: use freertos critical section compliant APIs
Some modules use esp_timer from interrupt context and hence
with vanilla FreeRTOS it should use correct critical section
API
2019-11-15 15:57:55 +05:30
Shubham Kulkarni
c741dd0535 Fixed warnings for components driver, esp32 and mbedtls 2019-11-15 08:51:16 +00:00
Alexey Gerenkov
30ff7198b8 apptrace: Renames Kconfig options 2019-11-13 15:24:01 +03:00
xiehang
5e7f43f3d1 esp_wifi: Put some rx code to iram 2019-11-13 11:44:23 +00:00
Ivan Grokhotkov
2026340752 clk.h: add extern C guards
Closes https://github.com/espressif/esp-idf/issues/4215
2019-11-05 14:56:16 +01:00
Angus Gratton
13ff57f133 Merge branch 'feature/ipc_runs_with_caller_priority' into 'master'
esp_common: IPC works with the priority of the caller's task

Closes IDF-78

See merge request espressif/esp-idf!6191
2019-11-04 18:29:14 +08:00
Angus Gratton
9ac55b5e55 Merge branch 'fix/ci_ut_psram_wroverb' into 'master'
ci: fix one ut issue when using Wrover-B module with newer ver of PSRAM

See merge request espressif/esp-idf!6553
2019-11-04 18:12:44 +08:00
Angus Gratton
b7c2c93ecc Merge branch 'bugfix/wifi_internal_memory' into 'master'
wifi: Include DMA reserved pool when allocating internal-only memory

Closes WIFI-883

See merge request espressif/esp-idf!6545
2019-11-04 13:55:49 +08:00
Michael (XIAO Xufeng)
748b79e94a ci: fix one ut issue when using Wrover-B module with newer ver of PSRAM
The workaround for PSRAM that will occupy an SPI bus is enabled only when:

1. used on 32MBit ver 0 PSRAM.
2. work at 80MHz.

The test used to only check 32MBit by the config option, but for PSRAM
on Wrover-B module seems to use a newer version of 32MBit PSRAM.  So it
expects the workaround to be enabled, but actually not.

This commit split the unit test into two parts:

1. check all SPI buses are available, for all configs except psram_hspi
and psram_vspi, run on regular runners (including Wrover and Wrover-B).
a hidden option is enabled so that the compiler knows it's not building
psram_hspi or psram_vspi.

2. check the specified bus are acquired, for config psram_hspi and
psram_vspi. This only run on special runner (legacy Wrover module).
2019-11-03 03:07:37 +00:00