By default SD cards are initialized in default speed (DS) mode. Enabling
HS mode requires SWITCH_FUNC command to be sent twice: first time to
query if the card supports switching to HS mode, second time to perform
the switch.
This change implements SWITCH_FUNC command and adds the procedure to
switch to HS mode.
‘make_hw_cmd’ function checks opcodes in a few cases. Comparing opcode
does not tell the whole story, because for some SD commands there is are
APP commands with the same opcodes. This change introduces a flag which
indicates whether the next command is going to be an APP command.
The check for APP_SET_BUS_WIDTH command is updated to use this flag.
This fixes a bug with an unexpected STOP_TRANSMISSION command sent after
SWITCH_FUNC command, which has opcode 6, same as APP_SET_BUS_WIDTH.
MMC_RSP_BITS helper function had a hack that it flipped word order in
the response, assuming that response size is 4 words. This hack does not
work for responses which are not 4 words long (such as the SWITCH_FUNC
response, which is 64 words long).
This change removes the hack and the matching word order reversal code
in sdmmc driver.
The address field should be placed at the highest bits of address and slv_wr_status registers. Instead of breaking the address into two parts and fill in each register, move the address to the highest bits and write to the registers respectively.
Breaking change: if you fill-in the SPI address filed in a previous version in some way and it works correctly, you still have to rewrite the address, in a more intuitive way.
force rxlength=length and mosi=1 and inlink.start=1 on in full-duplex mode.
set rxlength > length is forbidden in full-duplex mode.
TW#12609, TW#14240, https://www.esp32.com/viewtopic.php?f=13&t=2519
SDMMC hardware treats all buffers as aligned, and ignores 2 LSBs of
addresses written into DMA descriptors. Previously SDMMC host driver
assumed that data buffers passed from SDDMC command layer would be
aligned. However alignment checks were never implemented in the command
layer, as were the checks that the buffer coming from the application
would be in DMA capable memory. Most of the time this was indeed true.
However in some cases FATFS library can pass buffers offset by 2 bytes
from word boundary. “DMA capable” restriction may be broken if pSRAM
support is used.
This change adds buffer checks to the SDMMC host driver (alignment and
DMA capability), so that the host layer will error out for incompatible
buffers. In SDMMC command layer, a check is added to read and write
functions. If an incompatible buffer is passed from the application, new
buffer (512 bytes size) is allocated, and the transfer is performed
using {READ,WRITE}_SINGLE_BLOCK commands.
SD SPI mode driver
This MR adds functionality to support SD cards connected via SPI interface.
Additionally, two bugs are fixed:
- Definition of `SPI_TRANS_MODE_DIOQIO_ADDR` in spi_master driver
- SD card probing frequency was 4000kHz instead of 400kHz as required by the standard
See merge request !727
gpio_matrix_out function will set output enable for GPIO, seems in gpio_matrix_out there will be a short moment that the chip will output GPIO level.
So we can set GPIO as high before gpio_matrix_out function.
Previously the first call to rmt_driver_uninstall() would remove the interrupt handler,
even if other channels still had the driver installed.
Adds an OS-level lock to control concurrent registration/deregistration of channels.
1. Name change from chopper to carrier, block diagram update, minor changes to example codes
2. mcpwm_reg.h changed, brought uniformity in comments, worked on suggestions, duty to accept float. Some name changes!
3. Minor readme changes and Indetation
4. Minor change: move mcpwm_reg.h and mcpwm_struct.h to new path
5. Minor change: addition of BLDC example code and Readme
6. Name changed from epwm to mcpwm
7. Improve the reg name in mcpwm_struct.h
8. Name change chopper>carrier, deadband>deadtime
component/esp32 : fix dualcore bug
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
See merge request !742
1. When dual core cpu run access DPORT register, must do protection.
2. If access DPORT register, must use DPORT_REG_READ/DPORT_REG_WRITE and DPORT_XXX register operation macro.
