Commit graph

12 commits

Author SHA1 Message Date
Ivan Grokhotkov
253930acd1 spi_master, ulp: fix aliasing errors in unit tests 2018-07-24 09:54:55 +03:00
Ivan Grokhotkov
d2acf1ce77 sleep: add light sleep, factor out APIs common for deep/light sleep 2017-09-01 10:36:14 +08:00
Ivan Grokhotkov
6353bc40d7 Add support for 32k XTAL as RTC_SLOW_CLK source
- RTC_CNTL_SLOWCLK_FREQ define is removed; rtc_clk_slow_freq_get_hz
  function can be used instead to get an approximate RTC_SLOW_CLK
  frequency

- Clock calibration is performed at startup. The value is saved and used
  for timekeeping and when entering deep sleep.

- When using the 32k XTAL, startup code will wait for the oscillator to
  start up. This can be possibly optimized by starting a separate task
  to wait for oscillator startup, and performing clock switch in that
  task.

- Fix a bug that 32k XTAL would be disabled in rtc_clk_init.

- Fix a rounding error in rtc_clk_cal, which caused systematic frequency
  error.

- Fix an overflow bug which caused rtc_clk_cal to timeout early if the
  slow_clk_cycles argument would exceed certain value

- Improve 32k XTAL oscillator startup time by introducing bootstrapping
  code, which uses internal pullup/pulldown resistors on 32K_N/32K_P
  pins to set better initial conditions for the oscillator.
2017-04-26 12:43:22 +08:00
Ivan Grokhotkov
cde4072f25 ulp: ignore tests which use deep sleep 2017-03-08 16:19:58 +08:00
Ivan Grokhotkov
5cab04075e ulp: rename I_SLEEP, redefine I_WAKE, add I_ADC, add tests
This fixes incorrect descriptions of I_END/I_SLEEP instructions and
changes the definition of I_END. New instruction, I_WAKE, is added,
which wakes up the SoC. Macro for ADC instruction is defined, and new
tests are added.
2017-02-22 15:00:36 +08:00
Ivan Grokhotkov
cdf122baa0 ulp: add I_WR_REG instruction test 2017-02-22 14:40:36 +08:00
Ivan Grokhotkov
d0d2c4cb49 esp32,ulp: add tests for TSENS 2017-02-22 14:40:36 +08:00
Ivan Grokhotkov
0483548a39 ulp: fix I_{RD,WR}_REG definitions
- I_RD_REG used the wrong union member (.rd_reg) due to a copy-paste
  mistake

- Peripheral register address in bits[7:0] should be given in words,
  not in bytes

Fixes https://github.com/espressif/esp-idf/issues/297
2017-02-22 14:40:36 +08:00
antti
f8b5c29346 esp32: add [ignore] tag to some unit test cases for CI
Add ignore tag on unit test cases that are not supported in CI yet
2017-01-18 17:08:20 +08:00
Ivan Grokhotkov
7a527896dc ulp: use timer to start ULP, fix I_ANDI bug, add tests
Starting the ULP using SENS_SAR_START_FORCE_REG doesn’t disable clock gating of RTC fast clock.
When SoC goes into deep sleep mode, RTC fast clock gets gated, so ULP can no longer run.
Instead, it has to be started using the timer (RTC_CNTL_ULP_CP_SLP_TIMER_EN bit).
When ULP is enabled by the timer, clock also gets enabled.
2016-12-16 20:25:38 +08:00
Ivan Grokhotkov
616d1d32f1 ulp: add missing component.mk for tests 2016-12-16 14:30:27 +08:00
Ivan Grokhotkov
ab3677d64c initial support for generation of ULP coprocessor code 2016-12-01 20:26:47 -08:00