ulp: rename I_SLEEP, redefine I_WAKE, add I_ADC, add tests
This fixes incorrect descriptions of I_END/I_SLEEP instructions and changes the definition of I_END. New instruction, I_WAKE, is added, which wakes up the SoC. Macro for ADC instruction is defined, and new tests are added.
This commit is contained in:
Ivan Grokhotkov
parent
0465528431
commit
5cab04075e
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@ -81,7 +81,7 @@ extern "C" {
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#define B_CMP_L 0 /*!< Branch if R0 is less than an immediate */
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#define B_CMP_GE 1 /*!< Branch if R0 is greater than or equal to an immediate */
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#define OPCODE_END 9 /*!< Stop executing the program (not implemented yet) */
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#define OPCODE_END 9 /*!< Stop executing the program */
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#define SUB_OPCODE_END 0 /*!< Stop executing the program and optionally wake up the chip */
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#define SUB_OPCODE_SLEEP 1 /*!< Stop executing the program and run it again after selected interval */
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@ -342,27 +342,56 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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#define I_WR_REG_BIT(reg, shift, val) I_WR_REG(reg, shift, shift, val)
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/**
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* End program.
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* Wake the SoC from deep sleep.
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*
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* This instruction halts the coprocessor, and disables the ULP timer.
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* If wake == 1, the main CPU is woken up from deep sleep.
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* To stop the program but allow it to be restarted by timer, use I_HALT()
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* or I_SLEEP() instructions.
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* This instruction initiates wake up from deep sleep.
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* Use esp_deep_sleep_enable_ulp_wakeup to enable deep sleep wakeup
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* triggered by the ULP before going into deep sleep.
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* Note that ULP program will still keep running until the I_HALT
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* instruction, and it will still be restarted by timer at regular
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* intervals, even when the SoC is woken up.
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*
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* To stop the ULP program, use I_HALT instruction.
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*
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* To disable the timer which start ULP program, use I_END()
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* instruction. I_END instruction clears the
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* RTC_CNTL_ULP_CP_SLP_TIMER_EN_S bit of RTC_CNTL_STATE0_REG
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* register, which controls the ULP timer.
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*/
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#define I_END(wake) { .end = { \
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.wakeup = wake, \
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#define I_WAKE() { .end = { \
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.wakeup = 1, \
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.unused = 0, \
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.sub_opcode = SUB_OPCODE_END, \
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.opcode = OPCODE_END } }
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/**
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* End program and restart it after given amount of time.
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* Stop ULP program timer.
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*
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* Time to restart the program is determined by the value of
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* SENS_SLEEP_CYCLES_Sx register, where x == timer_idx.
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* There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5.
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* This is a convenience macro which disables the ULP program timer.
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* Once this instruction is used, ULP program will not be restarted
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* anymore until ulp_run function is called.
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*
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* ULP program will continue running after this instruction. To stop
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* the currently running program, use I_HALT().
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*/
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#define I_SLEEP(timer_idx) { .sleep = { \
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#define I_END() \
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I_WR_REG_BIT(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN_S, 0)
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/**
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* Select the time interval used to run ULP program.
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*
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* This instructions selects which of the SENS_SLEEP_CYCLES_Sx
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* registers' value is used by the ULP program timer.
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* When the ULP program stops at I_HALT instruction, ULP program
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* timer start counting. When the counter reaches the value of
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* the selected SENS_SLEEP_CYCLES_Sx register, ULP program
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* start running again from the start address (passed to the ulp_run
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* function).
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* There are 5 SENS_SLEEP_CYCLES_Sx registers, so 0 <= timer_idx < 5.
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*
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* By default, SENS_SLEEP_CYCLES_S0 register is used by the ULP
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* program timer.
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*/
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#define I_SLEEP_CYCLE_SEL(timer_idx) { .sleep = { \
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.cycle_sel = timer_idx, \
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.unused = 0, \
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.sub_opcode = SUB_OPCODE_SLEEP, \
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@ -380,6 +409,21 @@ static inline uint32_t SOC_REG_TO_ULP_PERIPH_SEL(uint32_t reg) {
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.reserved = 0, \
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.opcode = OPCODE_TSENS } }
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/**
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* Perform ADC measurement and store result in reg_dest.
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*
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* adc_idx selects ADC (0 or 1).
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* pad_idx selects ADC pad (0 - 7).
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*/
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#define I_ADC(reg_dest, adc_idx, pad_idx) { .adc = {\
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.dreg = reg_dest, \
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.mux = pad_idx + 1, \
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.sar_sel = adc_idx, \
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.unused1 = 0, \
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.cycles = 0, \
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.unused2 = 0, \
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.opcode = OPCODE_ADC } }
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/**
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* Store value from register reg_val into RTC memory.
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*
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@ -112,7 +112,9 @@ TEST_CASE("ulp wakeup test", "[ulp][ignore]")
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I_MOVI(R2, 42),
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I_MOVI(R3, 15),
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I_ST(R2, R3, 0),
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I_END(1)
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I_WAKE(),
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I_END(),
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I_HALT()
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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ulp_process_macros_and_load(0, program, &size);
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@ -145,7 +147,8 @@ TEST_CASE("ulp can write and read peripheral registers", "[ulp]")
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I_LD(R0, R1, 4),
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I_ADDI(R0, R0, 1),
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I_ST(R0, R1, 4),
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I_END(0)
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I_END(),
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I_HALT()
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
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@ -198,7 +201,7 @@ TEST_CASE("ULP I_WR_REG instruction test", "[ulp]")
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test_items[i].low,
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test_items[i].low + test_items[i].width - 1,
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0xff & ((1 << test_items[i].width) - 1)),
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I_END(0),
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I_END(),
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I_HALT()
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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@ -242,7 +245,9 @@ TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
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M_LABEL(5),
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M_BX(4),
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M_LABEL(6),
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I_END(1) // wake up the SoC
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I_WAKE(), // wake up the SoC
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I_END(), // stop ULP program timer
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I_HALT()
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};
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const gpio_num_t led_gpios[] = {
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GPIO_NUM_2,
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@ -261,6 +266,72 @@ TEST_CASE("ulp controls RTC_IO", "[ulp][ignore]")
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esp_deep_sleep_start();
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}
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TEST_CASE("ulp power consumption in deep sleep", "[ulp]")
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 4 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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ulp_insn_t insn = I_HALT();
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RTC_SLOW_MEM[0] = *(uint32_t*) &insn;
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REG_WRITE(SENS_ULP_CP_SLEEP_CYC0_REG, 0x8000);
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ulp_run(0);
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esp_deep_sleep_enable_ulp_wakeup();
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esp_deep_sleep_enable_timer_wakeup(10 * 1000000);
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esp_deep_sleep_start();
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}
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TEST_CASE("ulp timer setting", "[ulp]")
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{
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/*
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* Run a simple ULP program which increments the counter, for one second.
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* Program calls I_HALT each time and gets restarted by the timer.
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* Compare the expected number of times the program runs with the actual.
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*/
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 32 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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const int offset = 6;
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const ulp_insn_t program[] = {
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I_MOVI(R1, offset), // r1 <- offset
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I_LD(R2, R1, 0), // load counter
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I_ADDI(R2, R2, 1), // counter += 1
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I_ST(R2, R1, 0), // save counter
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I_HALT(),
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
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assert(offset >= size && "data offset needs to be greater or equal to program size");
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TEST_ESP_OK(ulp_run(0));
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// disable the ULP program timer — we will enable it later
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CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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const uint32_t cycles_to_test[] = {0x80, 0x100, 0x200, 0x400, 0x800, 0x1000, 0x2000, 0x4000};
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const size_t tests_count = sizeof(cycles_to_test) / sizeof(cycles_to_test[0]);
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for (size_t i = 0; i < tests_count; ++i) {
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// zero out the counter
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RTC_SLOW_MEM[offset] = 0;
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// set the number of slow clock cycles
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REG_WRITE(SENS_ULP_CP_SLEEP_CYC0_REG, cycles_to_test[i]);
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// enable the timer and wait for a second
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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vTaskDelay(1000 / portTICK_PERIOD_MS);
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// get the counter value and stop the timer
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uint32_t counter = RTC_SLOW_MEM[offset] & 0xffff;
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CLEAR_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_ULP_CP_SLP_TIMER_EN);
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// compare the actual and expected numbers of iterations of ULP program
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float expected_period = (cycles_to_test[i] + 16) / (float) RTC_CNTL_SLOWCLK_FREQ + 5 / 8e6f;
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float error = 1.0f - counter * expected_period;
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printf("%u\t%u\t%.01f\t%.04f\n", cycles_to_test[i], counter, 1.0f / expected_period, error);
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// Should be within 15%
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TEST_ASSERT_INT_WITHIN(15, 0, (int) error * 100);
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// Note: currently RTC_CNTL_SLOWCLK_FREQ is ballpark value — we need to determine it
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// Precisely by running calibration similar to the one done in deep sleep.
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// This may cause the test to fail on some chips which have the slow clock frequency
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// way off.
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}
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}
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TEST_CASE("ulp can use TSENS in deep sleep", "[ulp][ignore]")
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{
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@ -297,10 +368,87 @@ TEST_CASE("ulp can use TSENS in deep sleep", "[ulp][ignore]")
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I_ST(R0, R2, offset + 4),
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I_ADDI(R2, R2, 1), // counter += 1
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I_ST(R2, R1, 1), // save counter
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I_SLEEP(0), // enter sleep
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I_HALT(), // enter sleep
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M_LABEL(1), // done with measurements
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I_END(), // stop ULP timer
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I_WAKE(), // initiate wakeup
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I_HALT()
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
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assert(offset >= size);
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TEST_ESP_OK(ulp_run(0));
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esp_deep_sleep_enable_timer_wakeup(4000000);
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esp_deep_sleep_enable_ulp_wakeup();
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esp_deep_sleep_start();
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}
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TEST_CASE("can use ADC in deep sleep", "[ulp][ignore]")
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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hexdump(RTC_SLOW_MEM, CONFIG_ULP_COPROC_RESERVE_MEM / 4);
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printf("\n\n");
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memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR1_BIT_WIDTH, 3, SENS_SAR1_BIT_WIDTH_S);
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SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR2_BIT_WIDTH, 3, SENS_SAR2_BIT_WIDTH_S);
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SET_PERI_REG_BITS(SENS_SAR_READ_CTRL_REG, SENS_SAR1_SAMPLE_BIT, 0x3, SENS_SAR1_SAMPLE_BIT_S);
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SET_PERI_REG_BITS(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_SAMPLE_BIT, 0x3, SENS_SAR2_SAMPLE_BIT_S);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_MEAS2_START_FORCE);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_MEAS1_START_FORCE);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_AMP, 2, SENS_FORCE_XPD_AMP_S);
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// SAR1 invert result
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DATA_INV);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR2_DATA_INV);
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// const int adc = 1;
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// const int channel = 1;
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// const int atten = 3;
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// const int gpio_num = 0;
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const int adc = 0;
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const int channel = 0;
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const int atten = 0;
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const int gpio_num = 36;
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rtc_gpio_init(gpio_num);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_SAR1_EN_PAD_FORCE_M);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_SAR2_EN_PAD_FORCE_M);
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SET_PERI_REG_BITS(SENS_SAR_ATTEN1_REG, 3, atten, 2 * channel); //set SAR1 attenuation
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SET_PERI_REG_BITS(SENS_SAR_ATTEN2_REG, 3, atten, 2 * channel); //set SAR2 attenuation
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// data start offset
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size_t offset = 20;
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// number of samples to collect
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RTC_SLOW_MEM[offset] = (CONFIG_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
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// sample counter
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RTC_SLOW_MEM[offset + 1] = 0;
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const ulp_insn_t program[] = {
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I_MOVI(R1, offset), // r1 <- offset
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I_LD(R2, R1, 1), // r2 <- counter
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I_LD(R3, R1, 0), // r3 <- length
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I_SUBI(R3, R3, 1), // end = length - 1
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I_SUBR(R3, R3, R2), // r3 = length - counter
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M_BXF(1), // if overflow goto 1:
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I_ADC(R0, adc, channel), // r0 <- ADC
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I_ST(R0, R2, offset + 4),
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I_ADDI(R2, R2, 1), // counter += 1
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I_ST(R2, R1, 1), // save counter
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I_HALT(),
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M_LABEL(1), // done with measurements
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I_END(0), // stop ULP timer
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I_END(), // stop ULP program timer
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I_HALT()
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};
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