5 commits

Author	SHA1	Message	Date
Jeroen Domburg	81e35a142a	Spiram: Add option to reserve MMU banks; add himem API to make use of those banks	2018-10-15 14:32:58 +08:00
Tian Hao	377a1f5ea1	component/esp32 : do more fix of dualcore bug ... 1. the cache API in romcode will access DPORT register, so protect it. 2. fix STALL spelling. 3. check dport access by non-dport access function	2017-05-12 15:41:51 +08:00
Wu Jian Gang	04b53643ef	header files: clean up ... 1. format; 2. Slow RTC memory reverse 2KB;	2016-09-12 17:47:50 +08:00
jack	24011ddd05	header files: modify rom code and soc header files ... 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions	2016-09-12 17:47:49 +08:00
Ivan Grokhotkov	bd6ea4393c	Initial public version	2016-08-17 23:08:22 +08:00