24011ddd05
1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions
147 lines
4.3 KiB
C
147 lines
4.3 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _ROM_CACHE_H_
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#define _ROM_CACHE_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** \defgroup uart_apis, uart configuration and communication related apis
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* @brief uart apis
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*/
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/** @addtogroup uart_apis
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* @{
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*/
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/**
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* @brief Initialise cache mmu, mark all entries as invalid.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
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*
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* @return None
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*/
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void mmu_init(int cpu_no);
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/**
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* @brief Set Flash-Cache mmu mapping.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
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*
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* @param int pod : process identifier. Range 0~7.
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*
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* @param unsigned int vaddr : virtual address in CPU address space.
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* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
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* Should be aligned by psize.
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*
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* @param unsigned int paddr : physical address in Flash.
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* Should be aligned by psize.
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*
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* @param int psize : page size of flash, in kilobytes. Should be 64 here.
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*
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* @param int num : pages to be set.
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*
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* @return unsigned int: error status
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* 0 : mmu set success
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* 1 : vaddr or paddr is not aligned
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* 2 : pid error
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* 3 : psize error
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* 4 : mmu table to be written is out of range
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* 5 : vaddr is out of range
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*/
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unsigned int cache_flash_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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/**
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* @brief Set Ext-SRAM-Cache mmu mapping.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : CPU number, 0 for PRO cpu, 1 for APP cpu.
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*
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* @param int pod : process identifier. Range 0~7.
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*
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* @param unsigned int vaddr : virtual address in CPU address space.
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* Can be IRam0, IRam1, IRom0 and DRom0 memory address.
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* Should be aligned by psize.
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*
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* @param unsigned int paddr : physical address in Ext-SRAM.
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* Should be aligned by psize.
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*
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* @param int psize : page size of flash, in kilobytes. Should be 32 here.
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*
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* @param int num : pages to be set.
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*
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* @return unsigned int: error status
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* 0 : mmu set success
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* 1 : vaddr or paddr is not aligned
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* 2 : pid error
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* 3 : psize error
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* 4 : mmu table to be written is out of range
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* 5 : vaddr is out of range
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*/
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unsigned int cache_sram_mmu_set(int cpu_no, int pid, unsigned int vaddr, unsigned int paddr, int psize, int num);
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/**
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* @brief Initialise cache access for the cpu.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
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*
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* @return None
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*/
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void Cache_Read_Init(int cpu_no);
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/**
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* @brief Flush the cache value for the cpu.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
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*
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* @return None
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*/
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void Cache_Flush(int cpu_no);
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/**
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* @brief Disable Cache access for the cpu.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
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*
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* @return None
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*/
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void Cache_Read_Disable(int cpu_no);
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/**
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* @brief Enable Cache access for the cpu.
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* Please do not call this function in your SDK application.
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*
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* @param int cpu_no : 0 for PRO cpu, 1 for APP cpu.
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*
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* @return None
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*/
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void Cache_Read_Enable(int cpu_no);
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ROM_CACHE_H_ */
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