Commit graph

1935 commits

Author SHA1 Message Date
Sachin Parekh
46d914ff45 gdb: Modify PC in case of invalid PC
Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-05-08 18:34:52 +05:30
Angus Gratton
d013105256 Merge branch 'feature/twdt_prints_backtrace' into 'master'
Add Task Watchdog backtrace printing

Closes IDF-1072

See merge request espressif/esp-idf!8136
2020-05-04 14:58:53 +08:00
Angus Gratton
fdd6bfe3c4 Merge branch 'bugfix/sleep_comments' into 'master'
doc: Specify that sleep wakeup source restrictions apply to all current ESP32 revisions

See merge request espressif/esp-idf!8351
2020-04-30 13:36:58 +08:00
Darian Leung
b097dd0a79 Add Task Watchdog backtrace printing
This commit makes the Task Watchdog print the backtrace of both
cores when it times out.
2020-04-27 18:11:29 +00:00
Ivan Grokhotkov
275ed32a11 Merge branch 'feature/esp32s2_iram_dram_protection' into 'master'
esp32s2: IRAM/DRAM memory protection

See merge request espressif/esp-idf!8156
2020-04-23 21:52:54 +08:00
Mahavir Jain
44939a6b1e Merge branch 'feature/iram_data_bss' into 'master'
esp32: IRAM_DATA_ATTR and IRAM_BSS_ATTR introduced

See merge request espressif/esp-idf!8377
2020-04-22 21:44:44 +08:00
Martin Vychodil
7491ea677a esp32s2: IRAM/DRAM memory protection
* new mem_prot API
* mem_prot on & locked by default (see Kconfig)
* feature activated in start_cpu0_default()

JIRA IDF-1355
2020-04-21 15:10:58 +02:00
Sachin Parekh
1e6c25992e esp32: IRAM_DATA_ATTR and IRAM_BSS_ATTR introduced
Using these attributes, .data and .bss can be placed in IRAM

Signed-off-by: Sachin Parekh <sachin.parekh@espressif.com>
2020-04-17 19:35:23 +05:30
Ivan Grokhotkov
9003c01b4b Merge branch 'init_priority_fix' into 'master'
CXX: make __attribute__((init_priority(n))) work

See merge request espressif/esp-idf!8276
2020-04-17 17:56:10 +08:00
Angus Gratton
552bf7be4a doc: Specify that sleep wakeup source restrictions apply to all current ESP32 revisions
Closes https://github.com/espressif/esp-idf/issues/4681

Discussion https://esp32.com/viewtopic.php?f=13&t=15145
2020-04-15 09:39:10 +10:00
Jiang Jiang Jian
3feffdfe03 Merge branch 'bugfix/psram_single_bit_error' into 'master'
bugfix(psram): support psram 2T mode to fix single bit error

See merge request espressif/esp-idf!6936
2020-04-10 15:04:15 +08:00
Jakob Hasse
4943b1cbf0 CXX: make __attribute__((init_priority(n))) work
* Added corresponding test case
* Moved all C++ init tests to separate file

Closes https://github.com/espressif/esp-idf/issues/5038
2020-04-08 09:11:54 +08:00
Ivan Grokhotkov
168660aebf Merge branch 'feature/toolchain_2020r1-RC1' into 'master'
Toolchain 2020r1 support bringing (esp32, esp32s2)

See merge request espressif/esp-idf!7509
2020-04-01 18:17:28 +08:00
Ivan Grokhotkov
455dbf28f4 esp32: use ccomp_timer in SHA test 2020-03-27 20:07:02 +07:00
Jeroen Domburg
419848549e Add fixes for gcc8 psram fix improvement 2020-03-27 20:04:47 +07:00
KonstantinKondrashov
a259746016 esp32: Add a Kconfig option- Number of attempts to repeat 32k XTAL calibration
Closes: IDF-1479
2020-03-27 04:56:44 +00:00
Darian Leung
91841a53ff WDT: Add LL and HAL for watchdog timers
This commit updates the watchdog timers (MWDT and RWDT)
in the following ways:

- Add seprate LL for MWDT and RWDT.
- Add a combined WDT HAL for all Watchdog Timers
- Update int_wdt.c and task_wdt.c to use WDT HAL
- Remove most dependencies on LL or direct register access
  in other components. They will now use the WDT HAL
- Update use of watchdogs (including RTC WDT) in bootloader and
  startup code to use the HAL layer.
2020-03-26 02:14:02 +08:00
chenjianqiang
04781fb009 psram: improve 2T mode enable
1. recover psram bankswitch config
2. set 2T mode enable default config as n
3. remove PSRAM ID check
2020-03-25 18:39:50 +08:00
chenjianqiang
55a20033e7 bugfix(psram): support psram 2T mode to fix single bit error
1. add enable PSRAM 2T mode function
2. enable PSRAM 2T mode base on PSRAM ID
3. abort when himem and 2T mode are enabled meanwhile
4. set SPIRAM_2T_MODE as "y" by default and modify SPIRAM_BANKSWITCH_ENABLE as "n" by default
2020-03-25 18:29:32 +08:00
Angus Gratton
62426a6c90 Merge branch 'refactor/use_new_component_registration_functions' into 'master'
CMake: Use new component registration function

See merge request espressif/esp-idf!8068
2020-03-25 08:02:42 +08:00
Renz Bagaporo
3d0967a58a test: declare requirements and include dirs private 2020-03-23 10:58:50 +08:00
Ivan Grokhotkov
18bc25b3a6 cpu_start: handle CONFIG_VFS_SUPPORT_IO 2020-03-20 14:03:45 +01:00
Angus Gratton
207914a13a Merge branch 'refactor/common_code_panic_handler' into 'master'
Panic handling common code refactor

See merge request espressif/esp-idf!7489
2020-03-19 11:23:57 +08:00
Angus Gratton
59381b60c0 Merge branch 'refactor/hal_function_set_exception_vector_table' into 'master'
soc: add hal api to set exception vector table base address

See merge request espressif/esp-idf!7905
2020-03-11 14:44:42 +08:00
Renz Bagaporo
890510aecd esp32, esp32s2: move reset reason source to esp_system 2020-03-10 19:56:24 +08:00
Renz Christian Bagaporo
2b100789b7 esp32, esp32s2: move panic handling code to new component 2020-03-10 19:56:24 +08:00
Roland Dobai
15884eccf2 Add multi-target support for performance tests 2020-03-09 13:41:56 +01:00
morris
8b6c0947c7 soc: add hal api to set exception vector table base address 2020-03-06 20:23:30 +08:00
Renz Christian Bagaporo
cefc71cdcd bootloader_support: mem-related initializations using cpu abstractions 2020-02-27 07:14:21 +05:00
Renz Christian Bagaporo
c9a51bfbb2 soc: create abstraction for cpu related operations 2020-02-27 07:14:19 +05:00
Sachin Parekh
301dacfb33 Exception handlers for LoadStoreError and LoadStoreAlignmentError
Configurable option to use IRAM as byte accessible memory (in single core mode) using
load-store (non-word aligned and non-word size IRAM access specific) exception handlers.
This allows to use IRAM for use-cases where certain performance penalty
(upto 170 cpu cycles per load or store operation) is acceptable. Additional configuration
option has been provided to redirect mbedTLS specific in-out content length buffers to
IRAM (in single core mode), allows to save 20KB per TLS connection.
2020-02-26 20:21:59 +08:00
Ivan Grokhotkov
7304651320 esp32: use semaphore in FP switch test, raise worker task priority 2020-02-10 13:36:43 +01:00
Angus Gratton
11fac8637a docs: Resolve doxygen & Sphinx warnings 2020-02-07 16:37:45 +11:00
Konstantin Kondrashov
739eb05bb9 esp32: add implementation of esp_timer based on TG0 LAC timer
Closes: IDF-979
2020-02-06 14:00:18 +08:00
Ivan Grokhotkov
41631587f8 Merge branch 'feature/esp32s2_brownout' into 'master'
esp32s2: add brownout detector support

Closes IDF-751

See merge request espressif/esp-idf!7428
2020-02-04 17:00:46 +08:00
Felipe Neves
429712c6eb freertos: moved all xtensa specific files into a separated folder 2020-01-27 16:05:30 -03:00
Ivan Grokhotkov
caef7ad9f2 esp32, esp32s2beta: move brownout.c to esp_common 2020-01-23 13:44:19 +01:00
Ivan Grokhotkov
70752baba4 esp32s2: add brownout detector support
1. add brownout detector HAL for esp32 and esp32s2
2. enable brownout reset for esp32 rev. 1 and above
3. add approximate brownout detector levels for esp32s2
2020-01-23 13:44:19 +01:00
Ivan Grokhotkov
cbb84e8f5e esp32s2: fix THREADPTR calculation, re-enable FreeRTOS TLS tests
1. Clarify THREADPTR calculation in FreeRTOS code, explaining where
the constant 0x10 offset comes from.

2. On the ESP32-S2, .flash.rodata section had different default
alignment (8 bytes instead of 16), which resulted in different offset
of the TLS sections. Unfortunately I haven’t found a way to query
section alignment from C code, or to use a constant value to define
section alignment in the linker script. The linker scripts are
modified to force a fixed 16 byte alignment for .flash.rodata on the
ESP32 and ESP32-S2beta. Note that the base address of .flash.rodata
was already 16 byte aligned, so this has not changed the actual
memory layout of the application.

Full explanation of the calculation below.

Assume we have the TLS template section base address
(tls_section_vma), the address of a TLS variable in the template
(address), and the final relocation value (offset). The linker
calculates:
offset = address - tls_section_vma + align_up(TCB_SIZE, alignment).

At run time, the TLS section gets copied from _thread_local_start
(in .rodata) to task_thread_local_start. Let’s assume that an address
of a variable in the runtime TLS section is runtime_address.
Access to this address will happen by calculating THREADPTR + offset.
So, by a series of substitutions:

THREADPTR + offset = runtime_address THREADPTR = runtime_address - offset
THREADPTR = runtime_address - (address - tls_section_vma + align_up(TCB_SIZE, alignment)) THREADPTR = (runtime_address - address) + tls_section_vma - align_up(TCB_SIZE, alignment)

The difference between runtime_address and address is same as the
difference between task_thread_local_start and _thread_local_start.
And tls_section_vma is the address of .rodata section, i.e.
_rodata_start. So we arrive to

THREADPTR = task_thread_local_start - _thread_local_start + _rodata_start - align_up(TCB_SIZE, alignment).

The idea with TCB_SIZE being added to the THREADPTR when computing
the relocation was to let the OS save TCB pointer in the TREADPTR
register. The location of the run-time TLS section was assumed to be
immediately after the TCB, aligned to whatever the section alignment
was. However in our case the problem is that the run-time TLS section
is stored not next to the TCB, but at the top of the stack. Plus,
even if it was stored next to the TCB, the size of a FreeRTOS TCB is
not equal to 8 bytes (TCB_SIZE hardcoded in the linker). So we have
to calculate THREADPTR in a slightly obscure way, to compensate for
these differences.

Closes IDF-1239
2020-01-23 11:29:22 +01:00
Angus Gratton
d672809080 Merge branch 'refactor/rename_esp32s2beta_to_esp32s2' into 'master'
global: rename esp32s2beta to esp32s2

See merge request espressif/esp-idf!7369
2020-01-23 09:16:30 +08:00
KonstantinKondrashov
6061d5d65a esp_timer/esp32: Fix case when alarm_reg > counter_reg but FRC_TIMER_INT_STATUS is not set
Closes: WIFI-1576
Closes: https://github.com/espressif/esp-idf/issues/2954
2020-01-22 14:30:34 +08:00
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
morris
e1f9b283bc esp32s2: mac addr allocation 2020-01-14 15:19:38 +08:00
Ivan Grokhotkov
a559014ff0 Merge branch 'bugfix/coredump_bin_fmt_ver_update' into 'master'
Fixes coredump compatibility with legacy binary core dumps

See merge request espressif/esp-idf!6794
2020-01-10 10:04:17 +08:00
Angus Gratton
459b3195ac esp_wifi: Move esp32 DPORT access wrappers into esp_wifi component 2020-01-08 18:23:29 +11:00
Angus Gratton
65dad0d46f build system: Remove some dependencies from esp32 & esp32s2beta
Possible now that wifi related source files are all in esp_wifi
2020-01-08 18:13:12 +11:00
Angus Gratton
f616d2f2de esp_wifi: Move wifi OS adapter structures into esp_wifi component 2020-01-08 18:13:12 +11:00
Ivan Grokhotkov
43de2cc84c test: add a (non-automated) case for backtraces with ROM functions 2020-01-02 18:50:32 +01:00
Ivan Grokhotkov
f52952cb45 esp32: panic: do digital reset if cache error interrupt is set
Even if frame->exccause != PANIC_RSN_CACHEERR, it is possible that
the cache error interrupt status is set. For example, this may happen
due to an invalid cache access in the panic handler itself.
Check cache error interrupt status instead of frame->exccause to
decide whether to do CPU reset or digital reset.

Also remove unnecessary esp_dport_access_int_pause from
esp_cache_err_get_cpuid, since the panic handler already calls
esp_dport_access_int_abort on entry.
2019-12-30 09:49:07 +01:00
liu zhifu
e1eeef2276 esp_wifi: fix a WiFi receiving bug
Support WiFi/BT MAC register writting when the WiFi/BT common clock is disabled.
2019-12-24 21:32:03 +08:00