Commit graph

13 commits

Author SHA1 Message Date
morris
e30cd361a8 global: rename esp32s2beta to esp32s2 2020-01-22 12:14:38 +08:00
morris
2422c52851 global: hello world on real esp32-s2 2020-01-16 17:43:59 +08:00
morris
1c2cc5430e global: bring up esp32s2(not beta) 2020-01-16 17:41:31 +08:00
michael
4220752aed ut: Move tests back from "esp32" subfolder
DISABLED_FOR_TARGETS macros are used

Partly revert "ci: disable unavailable tests for esp32s2beta"

This partly reverts commit 76a3a5fb48.

Partly revert "ci: disable UTs for esp32s2beta without runners"

This partly reverts commit eb158e9a22.

Partly revert "fix unit test and examples for s2beta"

This partly reverts commit 9baa7826be.

Partly revert "efuse: Add support for esp32s2beta"

This partly reverts commit db84ba868c.
2020-01-06 17:13:53 +08:00
michael
11fa11000f spi: re-enable the unit tests for esp32s2beta 2019-12-23 10:22:59 +08:00
Michael (XIAO Xufeng)
76a3a5fb48 ci: disable unavailable tests for esp32s2beta 2019-09-04 10:53:25 +10:00
Michael (XIAO Xufeng)
eb158e9a22 ci: disable UTs for esp32s2beta without runners 2019-09-04 10:53:25 +10:00
Michael (XIAO Xufeng)
9baa7826be fix unit test and examples for s2beta 2019-09-04 10:53:25 +10:00
Ivan Grokhotkov
e77540b695 Merge branch 'test/spi_sio_test' into 'master'
spi: add test for sio mode

See merge request idf/esp-idf!3416
2019-03-13 15:15:43 +08:00
He Yin Ling
8f3fe52b5a test: temp disable spi master slave mode test 2019-03-10 06:21:37 +00:00
michael
12a6664afa spi test: describe the wiring of param test in the comments 2019-02-28 19:43:58 +08:00
michael
305354d0a2 test: change spi test host to macros 2019-01-30 20:57:25 +08:00
michael
41e58bc419 spi: add new test for timing and mode
New unit tests added
------------------------

**Local:** Local test uses the GPIO matrix to connect the master and the
slave on the same board. When the master needs the iomux, the master
uses the GPIOs of its own, the slave connect to the pins by GPIO matrix;
When the slave needs the iomux, the slave uses the GPIOs of its own, the
master connects to the pins by GPIO matrix.

- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.

**M & S**: Master & slave tests performs the test with two boards. The
master and slave use iomux or gpio matrix according to the config.

- Provide a new unit test which performs freq scanning in mode 0. It
scans frequency of 1M, 8M, 9M and all frequency steps up to the maximum
frequency allowed.

- Provide a new unit test which performs mode test with significant
frequencies. It tests mode 0,1,2,3 with low frequency, and the maximum
frequency allowed.
2019-01-26 00:10:41 +08:00