Commit graph

4621 commits

Author SHA1 Message Date
He Yin Ling
4cb52e0a3d test: add test for https_request 2017-10-31 17:42:20 +08:00
He Yin Ling
47a9a4a614 test: add test fw for example test 2017-10-31 17:42:19 +08:00
YAMAMOTO Masaya
de61c096a1 Fix COMPONENT_DEPENDS 2017-10-31 17:29:20 +09:00
XiaXiaotian
50b6912bf8 Increase maximum number of WiFi dynamic transmitting buffer 2017-10-31 15:18:20 +08:00
XiaXiaotian
87d3986b87 Fix the return value of esp_now_send() 2017-10-31 15:18:20 +08:00
Jiang Jiang Jian
19aa3c72e9 Merge branch 'bugfix/wrong_ap_info_in_all_channel_scan' into 'master'
Wifi: bugfix of get wrong ap information in all channel scan

See merge request !1470
2017-10-31 15:15:07 +08:00
Jiang Jiang Jian
939b46596f Merge branch 'bugfix/btdm_unable_use_esp_ble_gatts_get_attr_value_after_long_write' into 'master'
component/bt: Fix the bug cann't use esp_ble_gatts_get_attr_value to get the att…

See merge request !1381
2017-10-31 14:45:17 +08:00
krzychb
d637952555 Small updates of documentation 2017-10-31 07:36:55 +01:00
Jiang Jiang Jian
07f92f0bd1 Merge branch 'bugfix/btdm_smp_decide_association_model' into 'master'
component/bt: Fix bug of function smp_decide_association_model

See merge request !1377
2017-10-31 14:34:41 +08:00
Jiang Jiang Jian
c4bb378e4c Merge branch 'bugfix/btdm_set_MAX_L2CAP_CHANNELS_error' into 'master'
component/bt: Fix bug of set MAX_L2CAP_CHANNELS error

See merge request !1448
2017-10-31 14:32:53 +08:00
Deng Xin
ccfbecd25f Wifi: bugfix of get wrong ap information in all channel scan
fix the issue get wrong ap information in all channel scan
2017-10-31 11:35:11 +08:00
Jiang Jiang Jian
4d5c3de1e0 Merge branch 'bugfix/btdm_app_malloc_invalid_bug' into 'master'
bt/examples: The application layer does not allocate memory correctly causing the btc layer pointer to cross the border.

See merge request !1438
2017-10-31 11:34:37 +08:00
Jiang Jiang Jian
97dffbfc47 Merge branch 'bugfix/btdm_disable_role_switch' into 'master'
component/bt: disable the use of ROLE_SWITCH feature for classic BT as workaround

See merge request !1446
2017-10-31 11:31:15 +08:00
Jiang Jiang Jian
182cd1ce4d Merge branch 'bugfix/btdm_fix_crash_when_set_device_name_null' into 'master'
component/bt: fix crash when set device name NULL

See merge request !1462
2017-10-31 11:17:49 +08:00
Jiang Jiang Jian
5b19cf23fc Merge branch 'feature/reduce_default_wifi_static_buffer_number' into 'master'
esp32: reduce default wifi static tx buffer

See merge request !1465
2017-10-31 11:16:22 +08:00
Angus Gratton
696dfbcfee Merge branch 'bugfix/fix_tcp_crash' into 'master'
fix tcp crash

See merge request !1444
2017-10-31 06:18:49 +08:00
Ivan Grokhotkov
4048db35b6 Merge branch 'bugfix/unit_test_refactored_timer_api_usage' into 'master'
unit_tests/Update unit test timer divider

See merge request !1468
2017-10-30 21:35:04 +08:00
Darian Leung
b908b3cd58 unit_tests/Update unit test timer divider
This commit updates various test cases throughout esp-idf such that
the values used for timer divider pass the assertions in the timer component.
Timer divider values must be between 2 to 65536
2017-10-30 19:42:16 +08:00
michael
0330ec270a feat(spi_master): add new feature allow use variable command and address field length for the same device.
Closes #654
2017-10-30 19:33:41 +08:00
Liu Zhi Fu
1195ced75c esp32: reduce default wifi static tx buffer
Modify the the default WiFi static tx buffer from 32 to 16
2017-10-28 12:15:40 +08:00
Alexey Skalozub
5405255928 Fix losing sign when multiplying by -1 2017-10-28 03:47:00 +03:00
Angus Gratton
7c9b24b407 Merge branch 'bugfix/fix_uart_vfs_test_error' into 'master'
bugfix(uart): Don't disable console uart peripheral

See merge request !1456
2017-10-27 19:20:13 +08:00
Jiang Jiang Jian
a9b63b796e Merge branch 'bugfix/btdm_cpu_core' into 'master'
component/bt : fix bug of sw interrupt cause to run btdm to different cpu core.

See merge request !1434
2017-10-27 18:36:59 +08:00
Wangjialin
102eb96c8b bugfix(uart): Don't disable console UART peripheral 2017-10-27 16:46:10 +08:00
xiewenxiang
04a8d32cba component/bt: modify spp client demo for discussion
- check the characteristic properties before write
 - check the db count is equal to SPP_IDX_NB or not
 - modify some other code for discussion
2017-10-27 15:35:31 +08:00
zhiweijian
15c75974de component/bt: fix crash when set device name NULL 2017-10-27 15:21:00 +08:00
xiewenxiang
d57901cd54 component/bt: refactor spp client demo
- because the GATTC API was modified, the spp client demo was
   refactored
2017-10-27 13:56:48 +08:00
Angus Gratton
ffeecde9e2 Merge branch 'feature/docs_update_timer_api' into 'master'
Timer API docs update, refactored example

See merge request !1316
2017-10-27 13:31:18 +08:00
krzychb
9b7d5d76a7 Timer API docs update, refactored example 2017-10-27 07:13:59 +02:00
Angus Gratton
62e24370f1 Merge branch 'feature/uart_example_separate_tx_rx_tasks' into 'master'
Added an asynchronous UART example, using separate RX and TX tasks.

See merge request !1403
2017-10-27 13:13:24 +08:00
Ivan Grokhotkov
00bf160f94 Merge branch 'bugfix/pthread_once' into 'master'
[pthread] Perform init_routine execution outside of the mutex

See merge request !1453
2017-10-27 09:21:55 +08:00
Angus Gratton
3338f1074f Merge branch 'bugfix/set_cppflags' into 'master'
Ensure that C++ and C compilers get the same preprocessor setup (from github)

See merge request !1459
2017-10-26 20:21:49 +08:00
Ivan Grokhotkov
eb5752c635 esp_restart: fix possible race while stalling other CPU, enable WDT early
Previously esp_restart would stall the other CPU before enabling RTC_WDT.
If the other CPU was executing an s32c1i instruction, the lock signal
from CPU to the arbiter would still be held after CPU was stalled. If
the CPU running esp_restart would then try to access the same locked
memory pool, it would be stuck, because lock signal would never be
released.

With this change, esp_restart resets the other CPU before stalling it.
Ideally, we would want to reset the CPU and keep it in reset, but the
hardware doesn't have such feature for PRO_CPU (it is possible to hold
APP_CPU in reset using DPORT register). Given that ROM code will not use
s32c1i in the first few hundred cycles, doing reset and then stall seems
to be safe.

In addition to than, RTC_WDT initialization is moved to the beginning of
the function, to prevent possible lock-up if CPU stalling still has any
issue.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
f11ad0c904 soc/rtc: fix spurious warnings about XTAL frequency on startup
1. Make sure that 8MD256 clock used to estimate XTAL frequency is enabled
   before trying to use rtc_clk_cal_ratio.
   This fixes "Bogus XTAL frequency: 0 MHz" warnings after software reset.

2. Don't call rtc_clk_xtal_freq_estimate if XTAL frequency is already
   known. This reduces startup time after deep sleep or software reset.

3. Compare known XTAL frequency and estimated one before printing a
   warning. This fixes "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting
   (40MHz). Detected 40 MHz." warnings.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
9317cb3434 soc/rtc: add tests for CPU frequency switching
These tests switch between PLL and XTAL frequencies for 10 seconds.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
6d4ed4ff6c soc/rtc: wait for SLOW_CLK cycle when switching CPU clock
Previous implementation waited for 20us after setting
RTC_CNTL_SOC_CLK_SEL_XTL register, using ets_delay_us, assuming that
the CPU was running at XTAL frequency. In reality, clock switch happened
on the next RTC_SLOW_CLK cycle, and CPU could be running at the previous
frequency (for example, 240 MHz) until then.
ets_delay_us would wait for 20 us * 40 cycles per us = 800 CPU cycles
(assuming 40 MHz XTAL; even less with a 26 MHz XTAL).
But if CPU was running at 240 MHz, 800 cycles would pass in just 3.3us,
while SLOW_CLK cycle could happen as much as 1/150kHz = 6.7us after
RTC_CNTL_SOC_CLK_SEL_XTL was set. So the software would not actually wait
long enough for the clock switch to happen, and would disable the PLL
while CPU was still clocked from PLL, leading to a halt.

This implementation uses rtc_clk_wait_for_slow_cycle() function to wait
until the clock switch, removing the need to wait for a fixed number of
CPU cycles.
2017-10-26 19:53:53 +08:00
Ivan Grokhotkov
05a0fbd49b soc/rtc: add a function to wait for slow clock cycle
Some RTC features are synchronized to RTC_SLOW_CLK, so sometimes
software needs to wait for the next slow clock cycle.
This function implements waiting using Timer Group clock calibration
feature.
2017-10-26 19:53:53 +08:00
Andreas Pokorny
2a1906cf50 Ensure that C++ and C compilers get the same preprocessor setup
CPPFLAGS is applied for both languages while CFLAGS only for C

Signed-off-by: Andreas Pokorny <andreas.pokorny@siemens.com>
2017-10-26 13:04:41 +02:00
Angus Gratton
9159e2b807 Merge branch 'bugfix/panic_handler_debugexception' into 'master'
panic handler: Print correct PC & backtrace for debug exceptions

See merge request !1441
2017-10-26 15:49:30 +08:00
Angus Gratton
f5b3a370cd Merge branch 'feature/adc2_driver' into 'master'
feature(adc2): add support to use ADC2 when WIFI is disabled

See merge request !1237
2017-10-26 15:48:48 +08:00
Angus Gratton
baf1641c29 Merge branch 'bugfix/uart_set_default_idle_time_to_zero' into 'master'
bugfix(uart): set default tx idle num

See merge request !1419
2017-10-26 15:17:45 +08:00
Angus Gratton
5c5d5f0acb Merge branch 'bugfix/tcpip_stack_overflow_logging_printf' into 'master'
lwip: Increase minimum TCP/IP task stack size if log level is Debug or Verbose

See merge request !1396
2017-10-26 15:09:22 +08:00
michael
87f2b27dc4 refactor(rtc): re-organize code in rtc_module.c 2017-10-26 14:35:30 +08:00
michael
d30f3e7aa8 example(adc2): add example and test case for adc2.
closes #461
2017-10-26 14:35:30 +08:00
esp32de
7c0020bfd0 feat(adc2): append adc2 support and api and the lock with WIFI module
append adc support and api
- esp_err_t adc2_config_width(adc_bits_width_t width_bit);
- esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten);
- int adc2_get_voltage(adc2_channel_t channel);
2017-10-26 14:35:29 +08:00
Kedar Sovani
07992b08e8 [pthread] Perform init_routine execution outside of the mutex
The mutex is common across all the threads. It needn't be held across
the init_routine() call as long as the 'once' behaviour is guaranteed

Saw a deadlock case, where init_routine of one thread was waiting for
the completion of init_routine in another thread.

t2: wait for command
t1: pthread_once:
         lock once_mux
         init_routine:
               inform thread t2
               wait for signal from t2
t2: received command
         pthread_once
             lock once_mux (already held by t1)
---- Deadlock ----
2017-10-25 13:57:39 +05:30
Jiang Jiang Jian
2765514314 Merge branch 'bugfix/btdm_fix_bonded_public_scan_issue' into 'master'
component/bt: Fix scan problem of bonded device using public address

See merge request !1305
2017-10-25 14:11:56 +08:00
Wangjialin
303b9f60db bugfix(uart): set default tx idle num
Reported from:
https://github.com/espressif/esp-idf/issues/703
https://github.com/espressif/esp-idf/issues/917
In uart driver we didn't change the default value of tx idle num, so there would be a delay after tx FIFO is empty.

1. Add API to set tx idle interval before next data transmission. (The UART hardware can add an interval after tx FIFO is empty).
2. Set default tx idle interval to zero.
3. Add hardware disable in uart driver delete function.
2017-10-25 13:29:02 +08:00
baohongde
3dab0fd340 component/bt: Fix bug of set MAX_L2CAP_CHANNELS error 2017-10-25 12:02:41 +08:00
island
4e7de126dc component/bt: Fix scan problem of bonded device using public address 2017-10-25 11:52:03 +08:00