Commit Graph

17 Commits

Author SHA1 Message Date
suda-morris 0af56e2815 Add chip revision into image header
Check chip id and chip revision before boot app image

Closes https://github.com/espressif/esp-idf/issues/4000
2019-09-27 10:24:39 +08:00
chenjianqiang cf2062f1d7 bugfix(flash): add flash config in app startup
We fixed some flash bugs in bootloader, but for the users used the old
vrsion bootloader, they can not fix these bugs via OTA, the solution is
add these updates in app startup.

These updates include:
1. SPI flash gpio matrix and drive strength configuration
2. SPI flash clock configuration
3. SPI flash read dummy configuration
4. SPI flash cs timing configuration
5. Update flash id of g_rom_flashchip
2019-08-27 21:04:36 +08:00
Jiang Jiang Jian 148a269808 Merge branch 'bugfix/improve_spi_timing_for_flash_v3.3' into 'release/v3.3'
bugfix(flash): improve spi cs timing settings for flash (backport v3.3)

See merge request espressif/esp-idf!5514
2019-08-20 16:33:57 +08:00
chenjianqiang 232408981d bugfix(flash): improve spi cs timing settings for flash
cs setup time is recomemded to be 1.5T, and cs hold time is recommended to be 2.5T.
(cs_setup = 1, cs_setup_time = 0; cs_hold = 1, cs_hold_time = 1)
2019-07-15 14:45:35 +08:00
chenjianqiang 9821e533db bugfix(flash): fix flash read error in DIO/26MHz mode 2019-07-15 14:26:53 +08:00
Jiang Jiang Jian 47ca5d53df Merge branch 'feature/config_spi_pins_based_on_efuse_value_v3.3' into 'release/v3.3'
feat(psram): config SPI psram pins based on efuse value (backport v3.3)

See merge request espressif/esp-idf!5240
2019-07-08 11:52:24 +08:00
chenjianqiang a6f990ffb9 bugfix(flash): improve flash dio read timing
When flash work in DIO Mode, in order to ensure the fast read mode of flash
is a fixed value, we merged the mode bits into address part, and the fast
read mode value is 0 (the default value).
2019-07-02 14:25:27 +08:00
chenjianqiang 55f5c2e08d feat(psram): config SPI psram pins based on efuse value 2019-07-02 14:15:55 +08:00
Konstantin Kondrashov 1db04ae574 esp32: Add reset uart
Fixed the case when the first part of log was missed
this was happened when:
 * CONFIG_CONSOLE_UART_CUSTOM option is selected (UART1)
 * The selected CONSOLE_UART port is used also for the console component
 * in code esp_restart() or abort() functions were called.
2019-06-04 20:15:35 +08:00
Konstantin Kondrashov 38509b2b95 bootloader_support: Fix UART RXD pin for console output (CUSTOM option)
The RXD pin is assigned as input (fix for custom uart option).

Closes: https://github.com/espressif/esp-idf/issues/2843

Closes: IDFGH-505
2019-05-28 12:44:41 +00:00
Ivan Grokhotkov 964f5a91f7 bootloader, esp32: add workaround for Tensilica erratum 572
If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
2018-11-19 04:39:35 +00:00
Ivan Grokhotkov a1f809fcc5 bootloader: provide implementation of `abort`
ROM definition of `abort` was removed in 9240bbb. The old definition
resulted in a panic due to a jump to a null pointer (abort member in
ROM stub table was zero). The new definition triggers a debug
exception if JTAG is connected, or goes into an infinite loop to be
reset by the WDT.
2018-10-15 15:02:56 +08:00
Konstantin Kondrashov 9c715d7946 bootloader_support: Fix enable rtc_wdt for resolve issue with varying supply
Eliminates the issue with the lock up in the bootloader due to a power drawdown during its operation.

Closes https://github.com/espressif/esp-idf/issues/1814
2018-09-03 05:43:01 +00:00
Konstantin Kondrashov a8e46775c6 soc/rtc_wdt: Add API functions for rtc_wdt
Added functions:
rtc_wdt_protect_off/on
rtc_wdt_set_length_of_reset_signal
rtc_wdt_set_stage
rtc_wdt_set_time
rtc_wdt_feed
rtc_wdt_disable/enable
2018-08-14 17:48:02 +05:00
Angus Gratton d775cc4c4c soc: Fix description of rtc_config_t.tieh, add macros
Usage of TIEH was correct but description had 1.8V & 3.3V backwards.

Add macro definitions for TIEH values to improve readability.
2018-05-25 14:58:37 +10:00
Wangjialin b1dcb52fec feature(psram): configure flash and psram speed during runtime
1. Bootloader reads SPI configuration from bin header, so that the burning configuration can be different with compiling configuration.
2. Psram mode init will overwrite original flash speed mode, so that users can change psram and flash speed after OTA.
3. Flash read mode(QIO/DIO…) will not be changed in app bin. It is decided by bootloader, OTA can not change this mode.
4. Add read flash ID function, and save flash ID in g_rom_flashchip
5. Set drive ability for all related GPIOs
6. Check raise VDDSDIO voltage in 80Mhz mode
7. Add check flash ID and update settings in bootloader
8. Read flash ID once and keep in global variable
9. Read flash image header once and reuse the result

Tested cases:
1. Test new and old version of bootloader
boot Flash 20M —> app Flash 80M + Psram 80M
boot Flash 40M —> app Flash 80M + Psram 80M
boot Flash 80M —> app Flash 80M + Psram 80M
boot Flash 20M —> app Flash 80M + Psram 40M
boot Flash 40M —> app Flash 80M + Psram 40M
boot Flash 80M —> app Flash 80M + Psram 40M
boot Flash 20M —> app Flash 40M + Psram 40M
boot Flash 40M —> app Flash 40M + Psram 40M
boot Flash 80M —> app Flash 40M + Psram 40M
2. Working after esp_restart reboot.
2018-04-20 20:51:44 +08:00
Konstantin Kondrashov 86256b3541 bootloader: Refactoring
Need to make the bootloader modular so that users can redefine its functional part.

- refactoring and moving functions to the bootloader_support component
- Changed function to `void` bootloader_utility_load_image(...);

TW19596
2018-04-17 16:36:49 +05:00