7 commits

Author	SHA1	Message	Date
Ivan Grokhotkov	0290a34b55	components/esp32: clean up cpu_start ... Move CPU region protection setup into soc/cpu.h change tabs to spaces remove unused extern declarations use RTC_WDTCONFIG0 instead of numeric address (still need to fix BB reg)	2016-09-15 02:03:55 +08:00
Jack	d0442602c7	add comments to register read/write operations	2016-09-12 17:47:50 +08:00
Wu Jian Gang	04b53643ef	header files: clean up ... 1. format; 2. Slow RTC memory reverse 2KB;	2016-09-12 17:47:50 +08:00
jack	24011ddd05	header files: modify rom code and soc header files ... 1. timer reg file for both time group 0 and time group 1, not only timer group 0 2. fix bug that io mux header file mismatch with chip 3. fix bug that some BASE address not correct 4. add some static function to eagle.fpga32.rom.addr.v7.ld 5. add interrupts usage table 6. add some comments for rom code functions	2016-09-12 17:47:49 +08:00
liuzhifu	2ca1b738d3	modify APB_CLK_FREQ from 40M to 80M	2016-08-26 19:03:51 +08:00
Angus Gratton	bd2f9e03f0	Add newlib libc locking using FreeRTOS primitives	2016-08-24 13:49:17 +08:00
Ivan Grokhotkov	bd6ea4393c	Initial public version	2016-08-17 23:08:22 +08:00