components/esp32: clean up cpu_start
Move CPU region protection setup into soc/cpu.h change tabs to spaces remove unused extern declarations use RTC_WDTCONFIG0 instead of numeric address (still need to fix BB reg)
This commit is contained in:
Ivan Grokhotkov
parent
716cec5ded
commit
0290a34b55
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@ -24,6 +24,7 @@
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#include "rom/crc.h"
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#include "soc/soc.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/efuse_reg.h"
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@ -60,36 +61,7 @@ void IRAM_ATTR set_cache_and_start_app(uint32_t drom_addr,
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void IRAM_ATTR call_start_cpu0()
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{
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//Make page 0 access raise an exception
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//Also some other unused pages so we can catch weirdness
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//ToDo: this but nicer.
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asm volatile (\
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"movi a4,0x00000000\n" \
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"movi a5,0xf\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x80000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xa0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xc0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xe0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x20000000\n" \
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"movi a5,0x0\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x40000000\n" \
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"movi a5,0x2\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"isync\n" \
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:::"a4","a5");
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cpu_configure_region_protection();
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//Clear bss
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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@ -20,8 +20,10 @@
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#include "rom/ets_sys.h"
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#include "rom/uart.h"
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#include "soc/cpu.h"
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#include "soc/dport_reg.h"
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#include "soc/io_mux_reg.h"
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#include "soc/rtc_cntl_reg.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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@ -45,169 +47,104 @@ static void IRAM_ATTR user_start_cpu0(void);
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static void IRAM_ATTR call_user_start_cpu1();
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static void IRAM_ATTR user_start_cpu1(void);
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extern void ets_setup_syscalls(void);
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extern esp_err_t app_main(void *ctx);
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extern int __cpu1_entry_point;
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extern int _bss_start;
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extern int _bss_end;
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extern int _init_start;
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extern int _init_end;
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extern int _iram_romjumptable_start;
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extern int _iram_romjumptable_end;
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extern int _iram_text_start;
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extern int _iram_text_end;
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static const char* TAG = "cpu_start";
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/*
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We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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flash cache is down and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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static bool app_cpu_started = false;
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void IRAM_ATTR call_user_start_cpu0() {
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//Kill wdt
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REG_CLR_BIT(0x3ff4808c, BIT(10)); //RTCCNTL+8C RTC_WDTCONFIG0 RTC_
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REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
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//Move exception vectors to IRAM
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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uartAttach();
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ets_install_uart_printf();
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//Make page 0 access raise an exception
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//Also some other unused pages so we can catch weirdness
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//ToDo: this but nicer.
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asm volatile (\
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"movi a4,0x00000000\n" \
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"movi a5,0xf\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x80000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xa0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xc0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xe0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x20000000\n" \
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"movi a5,0x0\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x40000000\n" \
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"movi a5,0x2\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"isync\n" \
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:::"a4","a5");
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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// Initialize heap allocator
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heap_alloc_caps_init();
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ESP_EARLY_LOGI(TAG, "Pro cpu up.");
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#ifndef CONFIG_FREERTOS_UNICORE
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ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_user_start_cpu1);
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SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
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CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
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SET_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
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CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
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ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
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while (!app_cpu_started) {
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ets_delay_us(100);
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}
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#else
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ESP_EARLY_LOGI(TAG, "Single core mode");
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CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
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#endif
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ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
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user_start_cpu0();
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}
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extern int _init_start;
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void IRAM_ATTR call_user_start_cpu1() {
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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//Make page 0 access raise an exception
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//Also some other unused pages so we can catch weirdness
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//ToDo: this but nicer.
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asm volatile (\
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"movi a4,0x00000000\n" \
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"movi a5,0xf\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x80000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xa0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xc0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0xe0000000\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x20000000\n" \
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"movi a5,0x0\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"movi a4,0x40000000\n" \
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"movi a5,0x2\n" \
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"wdtlb a5,a4\n" \
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"witlb a5,a4\n" \
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"isync\n" \
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:::"a4","a5");
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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app_cpu_started = 1;
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user_start_cpu1();
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}
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extern volatile int port_xSchedulerRunning[2];
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void IRAM_ATTR user_start_cpu1(void) {
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// Wait for FreeRTOS initialization to finish on PRO CPU
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while (port_xSchedulerRunning[0] == 0) {
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;
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}
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ESP_LOGI(TAG, "Starting scheduler on APP CPU.");
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xPortStartScheduler();
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}
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extern void (*__init_array_start)(void);
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extern void (*__init_array_end)(void);
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extern volatile int port_xSchedulerRunning[2];
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static void do_global_ctors(void) {
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void (**p)(void);
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for(p = &__init_array_start; p != &__init_array_end; ++p)
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(*p)();
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static const char* TAG = "cpu_start";
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static bool app_cpu_started = false;
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/*
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* We arrive here after the bootloader finished loading the program from flash. The hardware is mostly uninitialized,
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* and the app CPU is in reset. We do have a stack, so we can do the initialization in C.
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*/
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void IRAM_ATTR call_user_start_cpu0()
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{
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//Kill wdt
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REG_CLR_BIT(RTC_WDTCONFIG0, RTC_CNTL_WDT_FLASHBOOT_MOD_EN);
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REG_CLR_BIT(0x6001f048, BIT(14)); //DR_REG_BB_BASE+48
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cpu_configure_region_protection();
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//Move exception vectors to IRAM
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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uartAttach();
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ets_install_uart_printf();
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memset(&_bss_start, 0, (&_bss_end - &_bss_start) * sizeof(_bss_start));
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// Initialize heap allocator
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heap_alloc_caps_init();
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ESP_EARLY_LOGI(TAG, "Pro cpu up.");
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#ifndef CONFIG_FREERTOS_UNICORE
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ESP_EARLY_LOGI(TAG, "Starting app cpu, entry point is %p", call_user_start_cpu1);
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SET_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
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CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
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SET_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
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CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_A, DPORT_APPCPU_RESETTING);
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ets_set_appcpu_boot_addr((uint32_t)call_user_start_cpu1);
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while (!app_cpu_started) {
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ets_delay_us(100);
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}
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#else
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ESP_EARLY_LOGI(TAG, "Single core mode");
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CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_B, DPORT_APPCPU_CLKGATE_EN);
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#endif
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ESP_EARLY_LOGI(TAG, "Pro cpu start user code");
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user_start_cpu0();
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}
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extern esp_err_t app_main(void *ctx);
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void user_start_cpu0(void) {
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void IRAM_ATTR call_user_start_cpu1()
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{
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asm volatile (\
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"wsr %0, vecbase\n" \
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::"r"(&_init_start));
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cpu_configure_region_protection();
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ESP_EARLY_LOGI(TAG, "App cpu up.");
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app_cpu_started = 1;
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user_start_cpu1();
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}
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void IRAM_ATTR user_start_cpu1(void)
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{
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// Wait for FreeRTOS initialization to finish on PRO CPU
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while (port_xSchedulerRunning[0] == 0) {
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;
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}
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ESP_LOGI(TAG, "Starting scheduler on APP CPU.");
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xPortStartScheduler();
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}
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static void do_global_ctors(void)
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{
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void (**p)(void);
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for (p = &__init_array_start; p != &__init_array_end; ++p) {
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(*p)();
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}
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}
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void user_start_cpu0(void)
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{
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ets_setup_syscalls();
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do_global_ctors();
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esp_ipc_init();
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spi_flash_init();
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do_global_ctors();
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esp_ipc_init();
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spi_flash_init();
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#if CONFIG_WIFI_ENABLED
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esp_err_t ret = nvs_flash_init(5, 3);
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@ -216,20 +153,18 @@ void user_start_cpu0(void) {
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}
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system_init();
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esp_event_init(NULL, NULL);
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tcpip_adapter_init();
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#endif
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#if CONFIG_WIFI_ENABLED && CONFIG_WIFI_AUTO_STARTUP
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#include "esp_wifi.h"
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esp_wifi_startup(app_main, NULL);
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esp_wifi_startup(app_main, NULL);
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#else
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app_main(NULL);
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app_main(NULL);
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#endif
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ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
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vTaskStartScheduler();
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ESP_LOGI(TAG, "Starting scheduler on PRO CPU.");
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vTaskStartScheduler();
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}
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@ -33,4 +33,39 @@ static inline bool cpu_in_interrupt_context(void)
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return (ps & PS_UM) == 0;
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}
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/* Functions to set page attributes for Region Protection option in the CPU.
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* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
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*/
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static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
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{
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asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
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}
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static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
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{
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asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
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}
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/* Make page 0 access raise an exception.
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* Also protect some other unused pages so we can catch weirdness.
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* Useful attribute values:
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* 0 — cached, RW
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* 2 — bypass cache, RWX (default value after CPU reset)
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* 15 — no access, raise exception
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*/
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static inline void cpu_configure_region_protection()
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{
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const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
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for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
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cpu_write_dtlb(pages_to_protect[i], 0xf);
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cpu_write_itlb(pages_to_protect[i], 0xf);
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}
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cpu_write_dtlb(0x20000000, 0);
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cpu_write_itlb(0x20000000, 0);
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}
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#endif
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