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Merge branch 'bugfix/i2s_adc_output_invert' into 'master'

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bugfix(i2s): fix adc output invert issue

See merge request espressif/esp-idf!7180
This commit is contained in:
Wang Jia Lin 2020-02-18 18:29:23 +08:00
commit f02399948d
4 changed files with 41 additions and 7 deletions
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2
components/soc/include/hal/adc_hal.h
View file

@ -59,7 +59,7 @@ void adc_hal_init(void);
*
* @prarm adc_n ADC unit.
*/
#define adc_hal_output_invert(adc_n, inv_en) adc_ll_output_invert(adc_n, inv_en)
void adc_hal_output_invert(adc_ll_num_t adc_n, bool inv_en);
/**
* Set ADC module controller.

18
components/soc/src/esp32/include/hal/adc_ll.h
View file

@ -435,11 +435,11 @@ static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, a
}
/**
* ADC module output data invert or not.
* ADC module RTC output data invert or not.
*
* @prarm adc_n ADC unit.
*/
static inline void adc_ll_output_invert(adc_ll_num_t adc_n, bool inv_en)
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
SENS.sar_read_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
@ -448,6 +448,20 @@ static inline void adc_ll_output_invert(adc_ll_num_t adc_n, bool inv_en)
}
}
/**
* ADC module Digital output data invert or not.
*
* @prarm adc_n ADC unit.
*/
static inline void adc_ll_dig_output_invert(adc_ll_num_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
SYSCON.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2
SYSCON.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
}
}
/**
* Set ADC module controller.
* There are five SAR ADC controllers:

18
components/soc/src/esp32s2/include/hal/adc_ll.h
View file

@ -436,11 +436,11 @@ static inline void adc_ll_set_atten(adc_ll_num_t adc_n, adc_channel_t channel, a
}
/**
* ADC module output data invert or not.
* ADC module RTC output data invert or not.
*
* @prarm adc_n ADC unit.
*/
static inline void adc_ll_output_invert(adc_ll_num_t adc_n, bool inv_en)
static inline void adc_ll_rtc_output_invert(adc_ll_num_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
SENS.sar_reader1_ctrl.sar1_data_inv = inv_en; // Enable / Disable ADC data invert
@ -449,6 +449,20 @@ static inline void adc_ll_output_invert(adc_ll_num_t adc_n, bool inv_en)
}
}
/**
* ADC module Digital output data invert or not.
*
* @prarm adc_n ADC unit.
*/
static inline void adc_ll_dig_output_invert(adc_ll_num_t adc_n, bool inv_en)
{
if (adc_n == ADC_NUM_1) {
APB_CTRL.saradc_ctrl2.sar1_inv = inv_en; // Enable / Disable ADC data invert
} else { // adc_n == ADC_NUM_2
APB_CTRL.saradc_ctrl2.sar2_inv = inv_en; // Enable / Disable ADC data invert
}
}
/**
* Set ADC module controller.
* There are five SAR ADC controllers:

10
components/soc/src/hal/adc_hal.c
View file

@ -21,8 +21,8 @@ void adc_hal_init(void)
adc_ll_dig_set_fsm_time(SOC_ADC_FSM_RSTB_WAIT_DEFAULT, SOC_ADC_FSM_START_WAIT_DEFAULT,
SOC_ADC_FSM_STANDBY_WAIT_DEFAULT);
adc_ll_dig_set_sample_cycle(ADC_FSM_SAMPLE_CYCLE_DEFAULT);
adc_ll_output_invert(ADC_NUM_1, SOC_ADC1_DATA_INVERT_DEFAULT);
adc_ll_output_invert(ADC_NUM_2, SOC_ADC2_DATA_INVERT_DEFAULT);
adc_hal_output_invert(ADC_NUM_1, SOC_ADC1_DATA_INVERT_DEFAULT);
adc_hal_output_invert(ADC_NUM_2, SOC_ADC2_DATA_INVERT_DEFAULT);
}
void adc_hal_dig_controller_config(const adc_hal_dig_config_t *cfg)
@ -81,3 +81,9 @@ int adc_hal_hall_convert(void)
hall_value = (Sens_Vp1 - Sens_Vp0) - (Sens_Vn1 - Sens_Vn0);
return hall_value;
}
void adc_hal_output_invert(adc_ll_num_t adc_n, bool inv_en)
{
adc_ll_rtc_output_invert(adc_n, inv_en);
adc_ll_dig_output_invert(adc_n, inv_en);
}