From d3290479b2a30e404520ab3db2a688556bed8ba8 Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Fri, 26 May 2017 17:41:18 +0800 Subject: [PATCH] Merge panic and dport high level interrupt code to both use int level 4 --- components/esp32/component.mk | 1 - components/esp32/dport_highint_hdl.S | 93 ------------------- ...ighint_hdl.S => dport_panic_highint_hdl.S} | 90 ++++++++++++++++-- components/soc/esp32/include/soc/soc.h | 8 +- 4 files changed, 85 insertions(+), 107 deletions(-) delete mode 100644 components/esp32/dport_highint_hdl.S rename components/esp32/{panic_highint_hdl.S => dport_panic_highint_hdl.S} (63%) diff --git a/components/esp32/component.mk b/components/esp32/component.mk index 1c5201932..666384e73 100644 --- a/components/esp32/component.mk +++ b/components/esp32/component.mk @@ -35,7 +35,6 @@ COMPONENT_ADD_LDFLAGS := -lesp32 \ -L $(COMPONENT_PATH)/ld \ -T esp32_out.ld \ -u ld_include_panic_highint_hdl \ - -u ld_include_dport_highint_hdl \ $(addprefix -T ,$(LINKER_SCRIPTS)) ALL_LIB_FILES := $(patsubst %,$(COMPONENT_PATH)/lib/lib%.a,$(LIBS)) diff --git a/components/esp32/dport_highint_hdl.S b/components/esp32/dport_highint_hdl.S deleted file mode 100644 index f07d29808..000000000 --- a/components/esp32/dport_highint_hdl.S +++ /dev/null @@ -1,93 +0,0 @@ -#include -#include -#include -#include -#include "freertos/xtensa_context.h" -#include "esp_panic.h" -#include "sdkconfig.h" -#include "soc/soc.h" -#include "soc/dport_reg.h" - - -#define L5_INTR_STACK_SIZE 8 -#define L5_INTR_A2_OFFSET 0 -#define L5_INTR_A3_OFFSET 4 - .data -_l5_intr_stack: - .space L5_INTR_STACK_SIZE - - .section .iram1,"ax" - .global xt_highint5 - .type xt_highint5,@function - .align 4 -xt_highint5: - - - /* This section is for access dport register protection */ - /* Allocate exception frame and save minimal context. */ - /* Because the interrupt cause code have protection that only - allow one cpu enter in L5 interrupt at one time, so - there needn't have two _l5_intr_stack for each cpu */ - - movi a0, _l5_intr_stack - s32i a2, a0, L5_INTR_A2_OFFSET - s32i a3, a0, L5_INTR_A3_OFFSET - - /* Check interrupt */ - rsr a0, INTERRUPT - extui a0, a0, ETS_DPORT_INUM, 1 /* get dport int bit */ - beqz a0, 1f - - /* handle dport interrupt */ - /* get CORE_ID */ - getcoreid a0 - beqz a0, 2f - - /* current cpu is 1 */ - movi a0, DPORT_CPU_INTR_FROM_CPU_3_REG - movi a2, 0 - s32i a2, a0, 0 /* clear intr */ - movi a0, 0 /* other cpu id */ - j 3f -2: - /* current cpu is 0 */ - movi a0, DPORT_CPU_INTR_FROM_CPU_2_REG - movi a2, 0 - s32i a2, a0, 0 /* clear intr */ - movi a0, 1 /* other cpu id */ -3: - /* set and wait flag */ - movi a2, dport_access_start - addx4 a2, a0, a2 - movi a3, 1 - s32i a3, a2, 0 - memw - movi a2, dport_access_end - addx4 a2, a0, a2 -.check_dport_access_end: - l32i a3, a2, 0 - beqz a3, .check_dport_access_end - -1: - movi a0, _l5_intr_stack - l32i a2, a0, L5_INTR_A2_OFFSET - l32i a3, a0, L5_INTR_A3_OFFSET - rsync /* ensure register restored */ - - rsr a0, EXCSAVE_5 /* restore a0 */ - rfi 5 - - - .align 4 -.L_xt_highint5_exit: - rsr a0, EXCSAVE_5 /* restore a0 */ - rfi 5 - - -/* The linker has no reason to link in this file; all symbols it exports are already defined - (weakly!) in the default int handler. Define a symbol here so we can use it to have the - linker inspect this anyway. */ - - .global ld_include_dport_highint_hdl -ld_include_dport_highint_hdl: - diff --git a/components/esp32/panic_highint_hdl.S b/components/esp32/dport_panic_highint_hdl.S similarity index 63% rename from components/esp32/panic_highint_hdl.S rename to components/esp32/dport_panic_highint_hdl.S index 67fd110a9..e921e258f 100644 --- a/components/esp32/panic_highint_hdl.S +++ b/components/esp32/dport_panic_highint_hdl.S @@ -21,25 +21,34 @@ #include "esp_panic.h" #include "sdkconfig.h" #include "soc/soc.h" - - +#include "soc/dport_reg.h" /* -In some situations, the panic handler needs to be invoked even when (low/medium priority) interrupts -are disabled. In that case, we use a high interrupt to panic anyway. This is the high-level interrupt -handler for such a situation. We use interrupt level 4 for this. + +Interrupt , a high-priority interrupt, is used for several things: +- Dport access mediation +- Cache error panic handler +- Interrupt watchdog panic handler + */ +#define L4_INTR_STACK_SIZE 8 +#define L4_INTR_A2_OFFSET 0 +#define L4_INTR_A3_OFFSET 4 + .data +_l4_intr_stack: + .space L4_INTR_STACK_SIZE + .section .iram1,"ax" .global xt_highint4 .type xt_highint4,@function .align 4 xt_highint4: - - /* On the ESP32, this level is used for panic events that are detected by hardware and should - also panic when interrupts are disabled. At the moment, these are the interrupt watchdog - as well as the cache invalid access interrupt. (24 and 25) */ + /* See if we're here for the dport access interrupt */ + rsr a0, INTERRUPT + extui a0, a0, ETS_DPORT_INUM, 1 + bnez a0, .handle_dport_access_int /* Allocate exception frame and save minimal context. */ mov a0, sp @@ -119,6 +128,66 @@ xt_highint4: + + + .align 4 +.handle_dport_access_int: + /* This section is for dport access register protection */ + /* Allocate exception frame and save minimal context. */ + /* Because the interrupt cause code has protection that only + allows one cpu to enter in the dport section of the L4 + interrupt at one time, there's no need to have two + _l4_intr_stack for each cpu */ + + /* This int is edge-triggered and needs clearing. */ + movi a0, (1<