Merge branch 'feature/interrupt_overhead_improvement' into 'master'
feature/interrupt overhead improvement Closes IDF-248 See merge request espressif/esp-idf!6328
This commit is contained in:
Angus Gratton
commit
a7aea56977
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@ -5,7 +5,7 @@ if(IDF_TARGET STREQUAL "esp32")
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endif()
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idf_component_register(SRC_DIRS ${src_dirs}
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idf_component_register(SRC_DIRS ${srcdirs}
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INCLUDE_DIRS .
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REQUIRES unity test_utils
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)
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73
components/freertos/test/test_isr_latency.c
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73
components/freertos/test/test_isr_latency.c
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@ -0,0 +1,73 @@
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#include <esp_types.h>
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#include <stdio.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/semphr.h"
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#include "freertos/queue.h"
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#include "freertos/xtensa_api.h"
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#include "esp_intr_alloc.h"
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#include "xtensa/hal.h"
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#include "unity.h"
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#include "soc/cpu.h"
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#include "test_utils.h"
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#define SW_ISR_LEVEL_1 7
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static SemaphoreHandle_t sync;
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static SemaphoreHandle_t end_sema;
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static uint32_t cycle_before_trigger;
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static uint32_t cycle_before_exit;
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static uint32_t delta_enter_cycles = 0;
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static uint32_t delta_exit_cycles = 0;
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static void software_isr(void *arg) {
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(void)arg;
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BaseType_t yield;
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delta_enter_cycles += portGET_RUN_TIME_COUNTER_VALUE() - cycle_before_trigger;
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xt_set_intclear(1 << SW_ISR_LEVEL_1);
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xSemaphoreGiveFromISR(sync, &yield);
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if(yield) {
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portYIELD_FROM_ISR();
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}
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cycle_before_exit = portGET_RUN_TIME_COUNTER_VALUE();
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}
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static void test_task(void *arg) {
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(void)arg;
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intr_handle_t handle;
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esp_err_t err = esp_intr_alloc(ETS_INTERNAL_SW0_INTR_SOURCE, ESP_INTR_FLAG_LEVEL1, &software_isr, NULL, &handle);
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TEST_ASSERT_EQUAL_HEX32(ESP_OK, err);
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for(int i = 0;i < 10000; i++) {
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cycle_before_trigger = portGET_RUN_TIME_COUNTER_VALUE();
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xt_set_intset(1 << SW_ISR_LEVEL_1);
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xSemaphoreTake(sync, portMAX_DELAY);
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delta_exit_cycles += portGET_RUN_TIME_COUNTER_VALUE() - cycle_before_exit;
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}
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delta_enter_cycles /= 10000;
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delta_exit_cycles /= 10000;
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esp_intr_free(handle);
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xSemaphoreGive(end_sema);
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vTaskDelete(NULL);
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}
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TEST_CASE("isr latency test", "[freertos] [ignore]")
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{
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sync = xSemaphoreCreateBinary();
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TEST_ASSERT(sync != NULL);
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end_sema = xSemaphoreCreateBinary();
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TEST_ASSERT(end_sema != NULL);
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xTaskCreatePinnedToCore(test_task, "tst" , 4096, NULL, configMAX_PRIORITIES - 1, NULL, 0);
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BaseType_t result = xSemaphoreTake(end_sema, portMAX_DELAY);
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TEST_ASSERT_EQUAL_HEX32(pdTRUE, result);
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TEST_PERFORMANCE_LESS_THAN(ISR_ENTER_CYCLES, "%d cycles" ,delta_enter_cycles);
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TEST_PERFORMANCE_LESS_THAN(ISR_EXIT_CYCLES, "%d cycles" ,delta_exit_cycles);
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}
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88
components/freertos/xt_asm_utils.h
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88
components/freertos/xt_asm_utils.h
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@ -0,0 +1,88 @@
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/*
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* Copyright (c) 2017, Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/* File adapted to use on IDF FreeRTOS component, extracted
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* originally from zephyr RTOS code base:
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* https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
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*/
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#ifndef __XT_ASM_UTILS_H
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#define __XT_ASM_UTILS_H
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/*
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* SPILL_ALL_WINDOWS
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*
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* Spills all windowed registers (i.e. registers not visible as
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* A0-A15) to their ABI-defined spill regions on the stack.
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*
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* Unlike the Xtensa HAL implementation, this code requires that the
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* EXCM and WOE bit be enabled in PS, and relies on repeated hardware
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* exception handling to do the register spills. The trick is to do a
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* noop write to the high registers, which the hardware will trap
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* (into an overflow exception) in the case where those registers are
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* already used by an existing call frame. Then it rotates the window
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* and repeats until all but the A0-A3 registers of the original frame
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* are guaranteed to be spilled, eventually rotating back around into
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* the original frame. Advantages:
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*
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* - Vastly smaller code size
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*
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* - More easily maintained if changes are needed to window over/underflow
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* exception handling.
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*
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* - Requires no scratch registers to do its work, so can be used safely in any
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* context.
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*
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* - If the WOE bit is not enabled (for example, in code written for
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* the CALL0 ABI), this becomes a silent noop and operates compatbily.
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*
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* - Hilariously it's ACTUALLY FASTER than the HAL routine. And not
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* just a little bit, it's MUCH faster. With a mostly full register
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* file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
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* registers with this vs. 279 (!) to do it with
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* xthal_spill_windows().
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*/
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.macro SPILL_ALL_WINDOWS
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#if XCHAL_NUM_AREGS == 64
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 4
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#elif XCHAL_NUM_AREGS == 32
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and a12, a12, a12
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rotw 3
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and a12, a12, a12
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rotw 3
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and a4, a4, a4
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rotw 2
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#else
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#error Unrecognized XCHAL_NUM_AREGS
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#endif
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.endm
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#endif
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@ -51,6 +51,7 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
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#include "xtensa_rtos.h"
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#include "xtensa_context.h"
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#include "xt_asm_utils.h"
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#ifdef XT_USE_OVLY
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#include <xtensa/overlay_os_asm.h>
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@ -58,8 +59,6 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
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.text
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/*******************************************************************************
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_xt_context_save
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@ -97,8 +96,8 @@ Exit conditions:
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.align 4
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.literal_position
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.align 4
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_xt_context_save:
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_xt_context_save:
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s32i a2, sp, XT_STK_A2
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s32i a3, sp, XT_STK_A3
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s32i a4, sp, XT_STK_A4
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@ -143,49 +142,15 @@ _xt_context_save:
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mov a9, a0 /* preserve ret addr */
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#endif
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#ifndef __XTENSA_CALL0_ABI__
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/*
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To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
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Need to save a9,12,13 temporarily (in frame temps) and recover originals.
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Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
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and underflow exceptions disabled (assured by PS.EXCM == 1).
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*/
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s32i a12, sp, XT_STK_TMP0 /* temp. save stuff in stack frame */
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s32i a13, sp, XT_STK_TMP1
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s32i a9, sp, XT_STK_TMP2
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/*
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Save the overlay state if we are supporting overlays. Since we just saved
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three registers, we can conveniently use them here. Note that as of now,
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overlays only work for windowed calling ABI.
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*/
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#ifdef XT_USE_OVLY
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l32i a9, sp, XT_STK_PC /* recover saved PC */
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_xt_overlay_get_state a9, a12, a13
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s32i a9, sp, XT_STK_OVLY /* save overlay state */
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#endif
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l32i a12, sp, XT_STK_A12 /* recover original a9,12,13 */
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l32i a13, sp, XT_STK_A13
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l32i a9, sp, XT_STK_A9
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addi sp, sp, XT_STK_FRMSZ /* restore the interruptee's SP */
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call0 xthal_window_spill_nw /* preserves only a4,5,8,9,12,13 */
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addi sp, sp, -XT_STK_FRMSZ
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l32i a12, sp, XT_STK_TMP0 /* recover stuff from stack frame */
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l32i a13, sp, XT_STK_TMP1
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l32i a9, sp, XT_STK_TMP2
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#endif
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#if XCHAL_EXTRA_SA_SIZE > 0
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/*
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NOTE: Normally the xthal_save_extra_nw macro only affects address
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registers a2-a5. It is theoretically possible for Xtensa processor
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designers to write TIE that causes more address registers to be
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affected, but it is generally unlikely. If that ever happens,
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more registers need to be saved/restored around this macro invocation.
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Here we assume a9,12,13 are preserved.
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Future Xtensa tools releases might limit the regs that can be affected.
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*/
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addi a2, sp, XT_STK_EXTRA /* where to save it */
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# if XCHAL_EXTRA_SA_ALIGN > 16
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movi a3, -XCHAL_EXTRA_SA_ALIGN
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@ -194,6 +159,38 @@ _xt_context_save:
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call0 xthal_save_extra_nw /* destroys a0,2,3,4,5 */
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#endif
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#ifndef __XTENSA_CALL0_ABI__
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#ifdef XT_USE_OVLY
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l32i a9, sp, XT_STK_PC /* recover saved PC */
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_xt_overlay_get_state a9, a12, a13
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s32i a9, sp, XT_STK_OVLY /* save overlay state */
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#endif
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rsr a2, PS /* We need to enable window exceptions to */
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movi a3, PS_INTLEVEL_MASK /* perform spill registers*/
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and a2, a2, a3
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bnez a2, _not_l1
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rsr a2, PS
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movi a3, PS_INTLEVEL(1) /* For some curious reason the level 1 interrupts */
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or a2, a2, a3 /* dont set the intlevel correctly on PS, we need to */
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wsr a2, PS /* do this manually */
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_not_l1:
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rsr a2, PS /* finally umask the window exceptions */
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movi a3, ~(PS_EXCM_MASK)
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and a2, a2, a3
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wsr a2, PS
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rsync
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addi sp, sp, XT_STK_FRMSZ /* go back to spill register region */
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SPILL_ALL_WINDOWS /* place the live register windows there */
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addi sp, sp, -XT_STK_FRMSZ /* return the current stack pointer and proceed with context save*/
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#endif
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l32i a12, sp, XT_STK_TMP0 /* restore the temp saved registers */
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l32i a13, sp, XT_STK_TMP1 /* our return address is there */
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l32i a9, sp, XT_STK_TMP2
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#if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
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mov a0, a9 /* retrieve ret addr */
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#endif
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@ -32,6 +32,10 @@
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#define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
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// SHA256 hardware throughput at 240MHz, threshold set lower than worst case
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#define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC 9.0
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#define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES 150
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#define IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES 290
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#define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES 565
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP 19000
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#define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 180000
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@ -27,6 +27,14 @@
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#define UNITY_EXCLUDE_TIME_H
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/**
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* @note For some reason setjmp does not work with
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* unity, since it is only used on test entry and
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* exit it should not impact the rest of test
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* framework. So we disable it here.
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*/
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#define UNITY_EXCLUDE_SETJMP_H
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void unity_flush(void);
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void unity_putc(int c);
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void unity_gets(char* dst, size_t len);
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@ -307,7 +307,7 @@ example_test_012:
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UT_001:
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extends: .unit_test_template
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parallel: 28
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parallel: 30
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tags:
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- ESP32_IDF
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- UT_T1_1
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@ -316,7 +316,7 @@ UT_001:
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UT_002:
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extends: .unit_test_template
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parallel: 9
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parallel: 11
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tags:
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- ESP32_IDF
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- UT_T1_1
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@ -466,7 +466,7 @@ UT_034:
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UT_035:
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extends: .unit_test_template
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parallel: 17
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parallel: 20
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tags:
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- ESP32S2BETA_IDF
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- UT_T1_1
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