From d18562516268fee7e61715cb4ccdd9dd153e91ea Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Mon, 7 Oct 2019 17:59:26 -0300
Subject: [PATCH 01/21] freertos/xtensa_context: added infrastructure to
 receive the spill register optimized code

---
 .../include/freertos/xtensa_context.h         |  7 +++
 components/freertos/xt_asm_utils.h            | 63 +++++++++++++++++++
 components/freertos/xtensa_context.S          |  5 ++
 3 files changed, 75 insertions(+)
 create mode 100644 components/freertos/xt_asm_utils.h

diff --git a/components/freertos/include/freertos/xtensa_context.h b/components/freertos/include/freertos/xtensa_context.h
index 120676dad..980d79494 100644
--- a/components/freertos/include/freertos/xtensa_context.h
+++ b/components/freertos/include/freertos/xtensa_context.h
@@ -129,11 +129,18 @@ STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
 STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
 #endif
 #ifndef __XTENSA_CALL0_ABI__
+#ifdef  CONFIG_FREERTOS_PORT_OPTIMIZE_INTERRUPT_HANDLING
+/* Todo prepare the stack frame to receive all windows regisster */
+STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
+STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
+STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
+#else
 /* Temporary space for saving stuff during window spill */
 STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
 STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
 STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
 #endif
+#endif
 #ifdef XT_USE_SWPRI
 /* Storage for virtual priority mask */
 STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)
diff --git a/components/freertos/xt_asm_utils.h b/components/freertos/xt_asm_utils.h
new file mode 100644
index 000000000..b3caad1cb
--- /dev/null
+++ b/components/freertos/xt_asm_utils.h
@@ -0,0 +1,63 @@
+#ifndef __XT_ASM_UTILS_H
+#define __XT_ASM_UTILS_H
+
+/*
+ * SPILL_ALL_WINDOWS
+ *
+ * Spills all windowed registers (i.e. registers not visible as
+ * A0-A15) to their ABI-defined spill regions on the stack.
+ *
+ * Unlike the Xtensa HAL implementation, this code requires that the
+ * EXCM and WOE bit be enabled in PS, and relies on repeated hardware
+ * exception handling to do the register spills.  The trick is to do a
+ * noop write to the high registers, which the hardware will trap
+ * (into an overflow exception) in the case where those registers are
+ * already used by an existing call frame.  Then it rotates the window
+ * and repeats until all but the A0-A3 registers of the original frame
+ * are guaranteed to be spilled, eventually rotating back around into
+ * the original frame.  Advantages:
+ *
+ * - Vastly smaller code size
+ *
+ * - More easily maintained if changes are needed to window over/underflow
+ *   exception handling.
+ *
+ * - Requires no scratch registers to do its work, so can be used safely in any
+ *   context.
+ *
+ * - If the WOE bit is not enabled (for example, in code written for
+ *   the CALL0 ABI), this becomes a silent noop and operates compatbily.
+ *
+ * - Hilariously it's ACTUALLY FASTER than the HAL routine.  And not
+ *   just a little bit, it's MUCH faster.  With a mostly full register
+ *   file on an LX6 core (ESP-32) I'm measuring 145 cycles to spill
+ *   registers with this vs. 279 (!) to do it with
+ *   xthal_spill_windows().  
+ */
+
+.macro SPILL_ALL_WINDOWS
+#if XCHAL_NUM_AREGS == 64
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 4
+#elif XCHAL_NUM_AREGS == 32
+	and a12, a12, a12
+	rotw 3
+	and a12, a12, a12
+	rotw 3
+	and a4, a4, a4
+	rotw 2
+#else
+#error Unrecognized XCHAL_NUM_AREGS
+#endif
+.endm
+
+
+#endif
\ No newline at end of file
diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index a8a19be7e..f5192e25a 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -51,6 +51,7 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
 
 #include "xtensa_rtos.h"
 #include "xtensa_context.h"
+#include "xt_asm_utils.h"
 
 #ifdef XT_USE_OVLY
 #include <xtensa/overlay_os_asm.h>
@@ -143,6 +144,9 @@ _xt_context_save:
     mov     a9,  a0                     /* preserve ret addr */
     #endif
 
+    #ifdef CONFIG_FREERTOS_PORT_OPTIMIZE_INTERRUPT_HANDLING
+    SPILL_ALL_WINDOWS /* add the optimized spill reg */   
+    #else
     #ifndef __XTENSA_CALL0_ABI__
     /*
     To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
@@ -175,6 +179,7 @@ _xt_context_save:
     l32i    a13, sp, XT_STK_TMP1    
     l32i    a9,  sp, XT_STK_TMP2    
     #endif
+    #endif
 
     #if XCHAL_EXTRA_SA_SIZE > 0
     /*  

From eb740ca8e40e53720b0911603471a5883278109a Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Fri, 11 Oct 2019 11:08:32 -0300
Subject: [PATCH 02/21] freertos/xtensa_context: modification of interrupt
 handler is workin, needs stabilization

---
 components/freertos/xtensa_context.S | 71 +++++++++++++---------------
 1 file changed, 33 insertions(+), 38 deletions(-)

diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index f5192e25a..4ef7365e5 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -144,53 +144,15 @@ _xt_context_save:
     mov     a9,  a0                     /* preserve ret addr */
     #endif
 
-    #ifdef CONFIG_FREERTOS_PORT_OPTIMIZE_INTERRUPT_HANDLING
-    SPILL_ALL_WINDOWS /* add the optimized spill reg */   
-    #else
-    #ifndef __XTENSA_CALL0_ABI__
-    /*
-    To spill the reg windows, temp. need pre-interrupt stack ptr and a4-15.
-    Need to save a9,12,13 temporarily (in frame temps) and recover originals.
-    Interrupts need to be disabled below XCHAL_EXCM_LEVEL and window overflow
-    and underflow exceptions disabled (assured by PS.EXCM == 1).
-    */
     s32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
     s32i    a13, sp, XT_STK_TMP1    
     s32i    a9,  sp, XT_STK_TMP2    
 
-    /*
-    Save the overlay state if we are supporting overlays. Since we just saved
-    three registers, we can conveniently use them here. Note that as of now,
-    overlays only work for windowed calling ABI.
-    */
-    #ifdef XT_USE_OVLY
-    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
-    _xt_overlay_get_state    a9, a12, a13
-    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
-    #endif
-
     l32i    a12, sp, XT_STK_A12         /* recover original a9,12,13 */
     l32i    a13, sp, XT_STK_A13
     l32i    a9,  sp, XT_STK_A9
-    addi    sp,  sp, XT_STK_FRMSZ       /* restore the interruptee's SP */
-    call0   xthal_window_spill_nw       /* preserves only a4,5,8,9,12,13 */
-    addi    sp,  sp, -XT_STK_FRMSZ
-    l32i    a12, sp, XT_STK_TMP0        /* recover stuff from stack frame */
-    l32i    a13, sp, XT_STK_TMP1    
-    l32i    a9,  sp, XT_STK_TMP2    
-    #endif
-    #endif
 
     #if XCHAL_EXTRA_SA_SIZE > 0
-    /*  
-    NOTE: Normally the xthal_save_extra_nw macro only affects address
-    registers a2-a5. It is theoretically possible for Xtensa processor
-    designers to write TIE that causes more address registers to be
-    affected, but it is generally unlikely. If that ever happens,
-    more registers need to be saved/restored around this macro invocation.
-    Here we assume a9,12,13 are preserved.
-    Future Xtensa tools releases might limit the regs that can be affected.
-    */
     addi    a2,  sp, XT_STK_EXTRA       /* where to save it */
     # if XCHAL_EXTRA_SA_ALIGN > 16
     movi    a3, -XCHAL_EXTRA_SA_ALIGN
@@ -199,6 +161,39 @@ _xt_context_save:
     call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
     #endif
 
+
+    #ifndef __XTENSA_CALL0_ABI__
+    #ifdef XT_USE_OVLY
+    l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
+    _xt_overlay_get_state    a9, a12, a13
+    s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
+    #endif
+
+	rsr     a2, PS
+	movi    a3, PS_INTLEVEL_MASK
+	and     a2, a2, a3
+	bnez    a2, _not_l1
+	rsr     a2, PS
+	movi    a3, PS_INTLEVEL(1)
+	or      a2, a2, a3
+	wsr     a2, PS
+_not_l1:
+
+	rsr     a2, PS
+	movi    a3, ~(PS_EXCM_MASK)
+	and     a2, a2, a3
+	wsr     a2, PS
+    rsync
+
+    addi    sp,  sp, XT_STK_FRMSZ      /* restore the interruptee's SP */
+    SPILL_ALL_WINDOWS
+    addi    sp,  sp, -XT_STK_FRMSZ
+    #endif
+
+    l32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
+    l32i    a13, sp, XT_STK_TMP1    
+    l32i    a9,  sp, XT_STK_TMP2  
+
     #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)
     mov     a0, a9                      /* retrieve ret addr */
     #endif

From 768d115e85c253a6550946c13d645b95026f09aa Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Fri, 11 Oct 2019 12:18:25 -0300
Subject: [PATCH 03/21] freertos/Kconfig: removed isr optimization option from
 menuconfig

---
 components/freertos/xtensa_context.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index 4ef7365e5..db6dee3c5 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -177,8 +177,8 @@ _xt_context_save:
 	movi    a3, PS_INTLEVEL(1)
 	or      a2, a2, a3
 	wsr     a2, PS
-_not_l1:
 
+_not_l1:
 	rsr     a2, PS
 	movi    a3, ~(PS_EXCM_MASK)
 	and     a2, a2, a3

From cd11787153849b35c43b36e604fcec97327aeefc Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Mon, 14 Oct 2019 11:57:36 -0300
Subject: [PATCH 04/21] freertos/xt_asm_utils: added documentation of current
 windows spill solution

---
 components/freertos/xt_asm_utils.h   | 26 +++++++++++++++++++++++++-
 components/freertos/xtensa_context.S | 18 +++++++++---------
 2 files changed, 34 insertions(+), 10 deletions(-)

diff --git a/components/freertos/xt_asm_utils.h b/components/freertos/xt_asm_utils.h
index b3caad1cb..eccf7aa87 100644
--- a/components/freertos/xt_asm_utils.h
+++ b/components/freertos/xt_asm_utils.h
@@ -1,3 +1,28 @@
+/* Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* File adapted to use on IDF FreeRTOS component, extracted 
+ * originally from zephyr RTOS code base
+ */
+
+/*
+ * Copyright (c) 2017, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 #ifndef __XT_ASM_UTILS_H
 #define __XT_ASM_UTILS_H
 
@@ -59,5 +84,4 @@
 #endif
 .endm
 
-
 #endif
\ No newline at end of file
diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index db6dee3c5..b0490c5e6 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -169,25 +169,25 @@ _xt_context_save:
     s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
     #endif
 
-	rsr     a2, PS
-	movi    a3, PS_INTLEVEL_MASK
+	rsr     a2, PS                      /* We need to enable window execptions to */ 
+	movi    a3, PS_INTLEVEL_MASK        /* perform spill registers*/
 	and     a2, a2, a3
 	bnez    a2, _not_l1
 	rsr     a2, PS
-	movi    a3, PS_INTLEVEL(1)
-	or      a2, a2, a3
-	wsr     a2, PS
+	movi    a3, PS_INTLEVEL(1)          /* For some curious reason the level 1 interrupts */
+	or      a2, a2, a3                  /* dont set the intlevel correctly on PS, we need to */     
+	wsr     a2, PS                      /* do this manually */
 
 _not_l1:
-	rsr     a2, PS
+	rsr     a2, PS                      /* finally umask the window exceptions */
 	movi    a3, ~(PS_EXCM_MASK)
 	and     a2, a2, a3
 	wsr     a2, PS
     rsync
 
-    addi    sp,  sp, XT_STK_FRMSZ      /* restore the interruptee's SP */
-    SPILL_ALL_WINDOWS
-    addi    sp,  sp, -XT_STK_FRMSZ
+    addi    sp,  sp, XT_STK_FRMSZ      /* go back to spill register region */
+    SPILL_ALL_WINDOWS                  /* place the live register windows there */ 
+    addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with conext save*/
     #endif
 
     l32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */

From d7d8b47b898d1623534e43a9baae0d633ec21f02 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Mon, 14 Oct 2019 13:58:14 -0300
Subject: [PATCH 05/21] unity/unity_config.h: changed configuration for setjmp
 usage

For some reason after use modified context save routine, the local unit test
app were crashed, the reason behind this resides on setjmp usage of test_runner,
since this feature seems to not be used for nothing special (just was a default config),
I changed the unity_config to replace the setjmp macros, this sounds less hacky.
---
 components/unity/include/unity_config.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/components/unity/include/unity_config.h b/components/unity/include/unity_config.h
index b23a5fe12..67f882a9a 100644
--- a/components/unity/include/unity_config.h
+++ b/components/unity/include/unity_config.h
@@ -26,6 +26,7 @@
 #endif
 
 #define UNITY_EXCLUDE_TIME_H
+#define UNITY_EXCLUDE_SETJMP_H
 
 void unity_flush(void);
 void unity_putc(int c);

From 5ce7a33c87aa2e8b20a85f7cd30f389a2fd2032a Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Mon, 14 Oct 2019 14:02:35 -0300
Subject: [PATCH 06/21] freertos/xtensa_context.S: fix some dread tabs

---
 components/freertos/xtensa_context.S | 28 +++++++++++++---------------
 1 file changed, 13 insertions(+), 15 deletions(-)

diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index b0490c5e6..4f33e7cc8 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -161,7 +161,6 @@ _xt_context_save:
     call0   xthal_save_extra_nw         /* destroys a0,2,3,4,5 */
     #endif
 
-
     #ifndef __XTENSA_CALL0_ABI__
     #ifdef XT_USE_OVLY
     l32i    a9,  sp, XT_STK_PC          /* recover saved PC */
@@ -169,22 +168,21 @@ _xt_context_save:
     s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
     #endif
 
-	rsr     a2, PS                      /* We need to enable window execptions to */ 
-	movi    a3, PS_INTLEVEL_MASK        /* perform spill registers*/
-	and     a2, a2, a3
-	bnez    a2, _not_l1
-	rsr     a2, PS
-	movi    a3, PS_INTLEVEL(1)          /* For some curious reason the level 1 interrupts */
-	or      a2, a2, a3                  /* dont set the intlevel correctly on PS, we need to */     
-	wsr     a2, PS                      /* do this manually */
-
+    rsr     a2, PS                      /* We need to enable window execptions to */ 
+    movi    a3, PS_INTLEVEL_MASK        /* perform spill registers*/
+    and     a2, a2, a3
+    bnez    a2, _not_l1
+    rsr     a2, PS
+    movi    a3, PS_INTLEVEL(1)          /* For some curious reason the level 1 interrupts */
+    or      a2, a2, a3                  /* dont set the intlevel correctly on PS, we need to */     
+    wsr     a2, PS                      /* do this manually */
 _not_l1:
-	rsr     a2, PS                      /* finally umask the window exceptions */
-	movi    a3, ~(PS_EXCM_MASK)
-	and     a2, a2, a3
-	wsr     a2, PS
+    rsr     a2, PS                      /* finally umask the window exceptions */
+    movi    a3, ~(PS_EXCM_MASK)
+    and     a2, a2, a3
+    wsr     a2, PS
     rsync
-
+    
     addi    sp,  sp, XT_STK_FRMSZ      /* go back to spill register region */
     SPILL_ALL_WINDOWS                  /* place the live register windows there */ 
     addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with conext save*/

From 346b12e29ab69efeb35b120621ed9c9075436c94 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Mon, 14 Oct 2019 23:32:31 -0300
Subject: [PATCH 07/21] freertos/test: added spill register timer measurement
 test

---
 .../freertos/test/test_improved_isr_time.c    | 61 +++++++++++++++++++
 components/freertos/xtensa_context.S          | 24 ++++++--
 components/idf_test/include/idf_performance.h |  1 +
 3 files changed, 81 insertions(+), 5 deletions(-)
 create mode 100644 components/freertos/test/test_improved_isr_time.c

diff --git a/components/freertos/test/test_improved_isr_time.c b/components/freertos/test/test_improved_isr_time.c
new file mode 100644
index 000000000..0448f0a0b
--- /dev/null
+++ b/components/freertos/test/test_improved_isr_time.c
@@ -0,0 +1,61 @@
+#include <esp_types.h>
+#include <stdio.h>
+#include "esp32/rom/ets_sys.h"
+
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "freertos/queue.h"
+#include "freertos/xtensa_api.h"
+#include "esp_intr_alloc.h"
+#include "xtensa/hal.h"
+#include "unity.h"
+#include "soc/cpu.h"
+#include "test_utils.h"
+
+static SemaphoreHandle_t end_sema;
+extern uint32_t isr_enter_spent_time_cycles;
+volatile static uint32_t isr_enter_spent_time_cycles_copy;
+
+static void testint(void *arg) {
+    xthal_set_ccompare(1, xthal_get_ccount()+8000000);
+}
+
+static void nested3(void) {
+    intr_handle_t handle;
+
+    esp_err_t err = esp_intr_alloc(ETS_INTERNAL_TIMER1_INTR_SOURCE, 0, &testint, NULL, &handle);
+    TEST_ASSERT_EQUAL_HEX32(ESP_OK, err);
+    xthal_set_ccompare(1, xthal_get_ccount()+8000000);
+    vTaskDelay(10);
+
+    isr_enter_spent_time_cycles_copy = isr_enter_spent_time_cycles;
+
+    ets_printf("Average time spent on context save is: %d cycles\n\n", isr_enter_spent_time_cycles_copy);
+    xSemaphoreGive(end_sema);
+    vTaskDelete(NULL);
+}
+
+static void nested2(void) {
+    nested3();
+}
+
+static void nested1(void) {
+    nested2();
+}
+
+static void test_task(void *arg) {
+    (void)arg;
+    nested1();
+ }
+
+TEST_CASE("isr handling time test", "[freertos]")
+{
+    end_sema = xSemaphoreCreateBinary();
+    TEST_ASSERT(end_sema != NULL);
+    xTaskCreatePinnedToCore(test_task, "tst" , 4096, NULL, 3, NULL, 0);
+    BaseType_t result = xSemaphoreTake(end_sema, portMAX_DELAY);    
+    TEST_ASSERT_EQUAL_HEX32(pdTRUE, result);
+    TEST_PERFORMANCE_LESS_THAN(SPILL_REG_CYCLES, "%d cycles" ,isr_enter_spent_time_cycles_copy); 
+}
+
diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index 4f33e7cc8..6d0399d99 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -57,10 +57,19 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
 #include <xtensa/overlay_os_asm.h>
 #endif
 
+/*
+--------------------------------------------------------------------------------
+    ISR overhead statistics data:
+--------------------------------------------------------------------------------
+*/
+    .data
+    .align      16
+    .global     isr_enter_spent_time_cycles
+isr_enter_spent_time_cycles:
+    .word		0
+
     .text
 
-
-
 /*******************************************************************************
 
 _xt_context_save
@@ -99,7 +108,6 @@ Exit conditions:
 	.literal_position
     .align  4
 _xt_context_save:
-
     s32i    a2,  sp, XT_STK_A2
     s32i    a3,  sp, XT_STK_A3
     s32i    a4,  sp, XT_STK_A4
@@ -182,10 +190,17 @@ _not_l1:
     and     a2, a2, a3
     wsr     a2, PS
     rsync
-    
+
+    rsr a2, CCOUNT
+
     addi    sp,  sp, XT_STK_FRMSZ      /* go back to spill register region */
     SPILL_ALL_WINDOWS                  /* place the live register windows there */ 
     addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with conext save*/
+
+    rsr a3, CCOUNT
+    sub  a3, a3, a2
+    movi a2, isr_enter_spent_time_cycles
+    s32i a3,a2,0
     #endif
 
     l32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
@@ -197,7 +212,6 @@ _not_l1:
     #endif
 
     ret
-
 /*******************************************************************************
 
 _xt_context_restore
diff --git a/components/idf_test/include/idf_performance.h b/components/idf_test/include/idf_performance.h
index ff8654c0b..a5b88eb24 100644
--- a/components/idf_test/include/idf_performance.h
+++ b/components/idf_test/include/idf_performance.h
@@ -32,6 +32,7 @@
 #define IDF_PERFORMANCE_MAX_ESP32_CYCLES_PER_SQRT 140
 // SHA256 hardware throughput at 240MHz, threshold set lower than worst case
 #define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC                             9.0
+#define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES                                    150
 
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP  19000
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 180000

From 64f918bd7028b10ab8781490dad70f8c17bfc1e2 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Wed, 16 Oct 2019 11:21:52 -0300
Subject: [PATCH 08/21] freertos/xtensa_context: added conditional compiling
 option around isr cycle measurement

It is possible to enable and disable the isr time measurement on context save and
it related test via menuconfig by the new option: FREERTOS_ISR_STATS
---
 components/freertos/Kconfig                       | 9 +++++++++
 components/freertos/test/test_improved_isr_time.c | 5 ++++-
 components/freertos/xtensa_context.S              | 8 ++++++++
 3 files changed, 21 insertions(+), 1 deletion(-)

diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig
index 198722331..0a589980f 100644
--- a/components/freertos/Kconfig
+++ b/components/freertos/Kconfig
@@ -435,9 +435,18 @@ menu "FreeRTOS"
             would be checked to be in compliance with Vanilla FreeRTOS.
             e.g Calling port*_CRITICAL from ISR context would cause assert failure
 
+<<<<<<< HEAD
     config FREERTOS_DEBUG_OCDAWARE
         bool
         help
             Hidden option, gets selected by CONFIG_ESPxx_DEBUG_OCDAWARE
 
+=======
+    config FREERTOS_ISR_STATS
+        bool "Enable cycle measurement inside ISR"
+        default n
+        help
+            If enabled, every context save operation will have its time
+            spent in cycles, measured.
+>>>>>>> 0f141ba8a... freertos/xtensa_context: added conditional compiling option around isr cycle measurement
 endmenu
diff --git a/components/freertos/test/test_improved_isr_time.c b/components/freertos/test/test_improved_isr_time.c
index 0448f0a0b..257592165 100644
--- a/components/freertos/test/test_improved_isr_time.c
+++ b/components/freertos/test/test_improved_isr_time.c
@@ -13,6 +13,8 @@
 #include "soc/cpu.h"
 #include "test_utils.h"
 
+#ifdef CONFIG_FREERTOS_ISR_STATS
+
 static SemaphoreHandle_t end_sema;
 extern uint32_t isr_enter_spent_time_cycles;
 volatile static uint32_t isr_enter_spent_time_cycles_copy;
@@ -49,7 +51,7 @@ static void test_task(void *arg) {
     nested1();
  }
 
-TEST_CASE("isr handling time test", "[freertos]")
+TEST_CASE("isr handling time test", "[freertos] [ignore]")
 {
     end_sema = xSemaphoreCreateBinary();
     TEST_ASSERT(end_sema != NULL);
@@ -59,3 +61,4 @@ TEST_CASE("isr handling time test", "[freertos]")
     TEST_PERFORMANCE_LESS_THAN(SPILL_REG_CYCLES, "%d cycles" ,isr_enter_spent_time_cycles_copy); 
 }
 
+#endif
\ No newline at end of file
diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index 6d0399d99..afa49f1ec 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -62,11 +62,14 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
     ISR overhead statistics data:
 --------------------------------------------------------------------------------
 */
+
+    #ifdef CONFIG_FREERTOS_ISR_STATS
     .data
     .align      16
     .global     isr_enter_spent_time_cycles
 isr_enter_spent_time_cycles:
     .word		0
+    #endif
 
     .text
 
@@ -191,16 +194,21 @@ _not_l1:
     wsr     a2, PS
     rsync
 
+    #ifdef CONFIG_FREERTOS_ISR_STATS
     rsr a2, CCOUNT
+    #endif
 
     addi    sp,  sp, XT_STK_FRMSZ      /* go back to spill register region */
     SPILL_ALL_WINDOWS                  /* place the live register windows there */ 
     addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with conext save*/
 
+    #ifdef CONFIG_FREERTOS_ISR_STATS
     rsr a3, CCOUNT
     sub  a3, a3, a2
     movi a2, isr_enter_spent_time_cycles
     s32i a3,a2,0
+    #endif //CONFIG_ISR_TIMING_STATS
+    
     #endif
 
     l32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */

From c14fc39b0ad4ea0f00a1c13875aca3b6c5eae789 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Thu, 17 Oct 2019 10:32:14 -0300
Subject: [PATCH 09/21] components/freertos: fixed typos and licence placement
 on external code

---
 ...est_improved_isr_time.c => test_isr_latency.c} |  2 +-
 components/freertos/xt_asm_utils.h                | 15 ++++++++-------
 components/freertos/xtensa_context.S              |  6 +++---
 3 files changed, 12 insertions(+), 11 deletions(-)
 rename components/freertos/test/{test_improved_isr_time.c => test_isr_latency.c} (96%)

diff --git a/components/freertos/test/test_improved_isr_time.c b/components/freertos/test/test_isr_latency.c
similarity index 96%
rename from components/freertos/test/test_improved_isr_time.c
rename to components/freertos/test/test_isr_latency.c
index 257592165..5af68be4f 100644
--- a/components/freertos/test/test_improved_isr_time.c
+++ b/components/freertos/test/test_isr_latency.c
@@ -51,7 +51,7 @@ static void test_task(void *arg) {
     nested1();
  }
 
-TEST_CASE("isr handling time test", "[freertos] [ignore]")
+TEST_CASE("isr latency test", "[freertos] [ignore]")
 {
     end_sema = xSemaphoreCreateBinary();
     TEST_ASSERT(end_sema != NULL);
diff --git a/components/freertos/xt_asm_utils.h b/components/freertos/xt_asm_utils.h
index eccf7aa87..e16d4b32c 100644
--- a/components/freertos/xt_asm_utils.h
+++ b/components/freertos/xt_asm_utils.h
@@ -1,3 +1,9 @@
+/*
+ * Copyright (c) 2017, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
 /* Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
  *
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -14,13 +20,8 @@
  */
 
 /* File adapted to use on IDF FreeRTOS component, extracted 
- * originally from zephyr RTOS code base
- */
-
-/*
- * Copyright (c) 2017, Intel Corporation
- *
- * SPDX-License-Identifier: Apache-2.0
+ * originally from zephyr RTOS code base:
+ * https://github.com/zephyrproject-rtos/zephyr/blob/dafd348/arch/xtensa/include/xtensa-asm2-s.h
  */
 
 #ifndef __XT_ASM_UTILS_H
diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index afa49f1ec..bacf78e92 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -200,7 +200,7 @@ _not_l1:
 
     addi    sp,  sp, XT_STK_FRMSZ      /* go back to spill register region */
     SPILL_ALL_WINDOWS                  /* place the live register windows there */ 
-    addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with conext save*/
+    addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with context save*/
 
     #ifdef CONFIG_FREERTOS_ISR_STATS
     rsr a3, CCOUNT
@@ -211,8 +211,8 @@ _not_l1:
     
     #endif
 
-    l32i    a12, sp, XT_STK_TMP0        /* temp. save stuff in stack frame */
-    l32i    a13, sp, XT_STK_TMP1    
+    l32i    a12, sp, XT_STK_TMP0       /* restore the temp saved registers */
+    l32i    a13, sp, XT_STK_TMP1       /* our return address is there */
     l32i    a9,  sp, XT_STK_TMP2  
 
     #if XCHAL_EXTRA_SA_SIZE > 0 || !defined(__XTENSA_CALL0_ABI__)

From e4804358795de9c2327f9f548270ea9b93a1d724 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Thu, 17 Oct 2019 10:43:22 -0300
Subject: [PATCH 10/21] components/freertos: removed some dead ifdefs

---
 components/freertos/include/freertos/xtensa_context.h | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/components/freertos/include/freertos/xtensa_context.h b/components/freertos/include/freertos/xtensa_context.h
index 980d79494..120676dad 100644
--- a/components/freertos/include/freertos/xtensa_context.h
+++ b/components/freertos/include/freertos/xtensa_context.h
@@ -129,18 +129,11 @@ STRUCT_FIELD (long, 4, XT_STK_LEND,   lend)
 STRUCT_FIELD (long, 4, XT_STK_LCOUNT, lcount)
 #endif
 #ifndef __XTENSA_CALL0_ABI__
-#ifdef  CONFIG_FREERTOS_PORT_OPTIMIZE_INTERRUPT_HANDLING
-/* Todo prepare the stack frame to receive all windows regisster */
-STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
-STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
-STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
-#else
 /* Temporary space for saving stuff during window spill */
 STRUCT_FIELD (long, 4, XT_STK_TMP0,   tmp0)
 STRUCT_FIELD (long, 4, XT_STK_TMP1,   tmp1)
 STRUCT_FIELD (long, 4, XT_STK_TMP2,   tmp2)
 #endif
-#endif
 #ifdef XT_USE_SWPRI
 /* Storage for virtual priority mask */
 STRUCT_FIELD (long, 4, XT_STK_VPRI,   vpri)

From 8b6b97ec578a8e3eb9565bce55b3fe65271f1737 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Fri, 18 Oct 2019 10:17:52 -0300
Subject: [PATCH 11/21] freertos/xtensa_context: fixed small typo

---
 components/freertos/xtensa_context.S | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index bacf78e92..8009de902 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -179,7 +179,7 @@ _xt_context_save:
     s32i    a9,  sp, XT_STK_OVLY        /* save overlay state */
     #endif
 
-    rsr     a2, PS                      /* We need to enable window execptions to */ 
+    rsr     a2, PS                      /* We need to enable window exceptions to */ 
     movi    a3, PS_INTLEVEL_MASK        /* perform spill registers*/
     and     a2, a2, a3
     bnez    a2, _not_l1

From bcdc35be59236fc3153a417cce9e061daf68a9a8 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Thu, 24 Oct 2019 16:49:59 -0300
Subject: [PATCH 12/21] components/freertos: refactor of isr_latency tests to
 perform full measurement

---
 components/freertos/test/test_isr_latency.c   | 74 +++++++++++--------
 components/freertos/xtensa_context.S          | 25 -------
 components/idf_test/include/idf_performance.h |  3 +
 3 files changed, 45 insertions(+), 57 deletions(-)

diff --git a/components/freertos/test/test_isr_latency.c b/components/freertos/test/test_isr_latency.c
index 5af68be4f..3c8d78685 100644
--- a/components/freertos/test/test_isr_latency.c
+++ b/components/freertos/test/test_isr_latency.c
@@ -13,52 +13,62 @@
 #include "soc/cpu.h"
 #include "test_utils.h"
 
-#ifdef CONFIG_FREERTOS_ISR_STATS
+#define SW_ISR_LEVEL_1  7
 
+static SemaphoreHandle_t sync;
 static SemaphoreHandle_t end_sema;
-extern uint32_t isr_enter_spent_time_cycles;
-volatile static uint32_t isr_enter_spent_time_cycles_copy;
+uint32_t cycle_before_trigger;
+uint32_t cycle_before_exit;
+uint32_t delta_enter_cycles;
+uint32_t delta_enter_cycles;
+uint32_t delta_exit_cycles;
 
-static void testint(void *arg) {
-    xthal_set_ccompare(1, xthal_get_ccount()+8000000);
-}
+static void software_isr(void *arg) {
+    (void)arg;
+    BaseType_t yield;
+    delta_enter_cycles += portGET_RUN_TIME_COUNTER_VALUE() - cycle_before_trigger;
+    
+    xt_set_intclear(1 << SW_ISR_LEVEL_1);
 
-static void nested3(void) {
-    intr_handle_t handle;
+    xSemaphoreGiveFromISR(sync, &yield);
+    if(yield) {
+        portYIELD_FROM_ISR();
+    }
 
-    esp_err_t err = esp_intr_alloc(ETS_INTERNAL_TIMER1_INTR_SOURCE, 0, &testint, NULL, &handle);
-    TEST_ASSERT_EQUAL_HEX32(ESP_OK, err);
-    xthal_set_ccompare(1, xthal_get_ccount()+8000000);
-    vTaskDelay(10);
-
-    isr_enter_spent_time_cycles_copy = isr_enter_spent_time_cycles;
-
-    ets_printf("Average time spent on context save is: %d cycles\n\n", isr_enter_spent_time_cycles_copy);
-    xSemaphoreGive(end_sema);
-    vTaskDelete(NULL);
-}
-
-static void nested2(void) {
-    nested3();
-}
-
-static void nested1(void) {
-    nested2();
+    cycle_before_exit = portGET_RUN_TIME_COUNTER_VALUE();
 }
 
 static void test_task(void *arg) {
     (void)arg;
-    nested1();
- }
+    
+    intr_handle_t handle;
+ 
+    esp_err_t err = esp_intr_alloc(ETS_INTERNAL_SW0_INTR_SOURCE, ESP_INTR_FLAG_LEVEL1, &software_isr, NULL, &handle);
+    TEST_ASSERT_EQUAL_HEX32(ESP_OK, err);
+
+    for(int i = 0;i < 10000; i++) {
+        cycle_before_trigger = portGET_RUN_TIME_COUNTER_VALUE();
+        xt_set_intset(1 << SW_ISR_LEVEL_1);
+        xSemaphoreTake(sync, portMAX_DELAY);
+        delta_exit_cycles += portGET_RUN_TIME_COUNTER_VALUE() - cycle_before_exit;
+    }
+
+    delta_enter_cycles /= 10000;
+    delta_exit_cycles /= 10000;
+
+    xSemaphoreGive(end_sema);
+    vTaskDelete(NULL);
+}
 
 TEST_CASE("isr latency test", "[freertos] [ignore]")
 {
+    sync = xSemaphoreCreateBinary();
+    TEST_ASSERT(sync != NULL);
     end_sema = xSemaphoreCreateBinary();
     TEST_ASSERT(end_sema != NULL);
     xTaskCreatePinnedToCore(test_task, "tst" , 4096, NULL, 3, NULL, 0);
     BaseType_t result = xSemaphoreTake(end_sema, portMAX_DELAY);    
     TEST_ASSERT_EQUAL_HEX32(pdTRUE, result);
-    TEST_PERFORMANCE_LESS_THAN(SPILL_REG_CYCLES, "%d cycles" ,isr_enter_spent_time_cycles_copy); 
-}
-
-#endif
\ No newline at end of file
+    TEST_PERFORMANCE_LESS_THAN(ISR_ENTER_CYCLES, "%d cycles" ,delta_enter_cycles);
+    TEST_PERFORMANCE_LESS_THAN(ISR_EXIT_CYCLES, "%d cycles" ,delta_exit_cycles);
+}
\ No newline at end of file
diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index 8009de902..3d1d979d6 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -57,20 +57,6 @@ NOERROR: .error "C preprocessor needed for this file: make sure its filename\
 #include <xtensa/overlay_os_asm.h>
 #endif
 
-/*
---------------------------------------------------------------------------------
-    ISR overhead statistics data:
---------------------------------------------------------------------------------
-*/
-
-    #ifdef CONFIG_FREERTOS_ISR_STATS
-    .data
-    .align      16
-    .global     isr_enter_spent_time_cycles
-isr_enter_spent_time_cycles:
-    .word		0
-    #endif
-
     .text
 
 /*******************************************************************************
@@ -194,20 +180,9 @@ _not_l1:
     wsr     a2, PS
     rsync
 
-    #ifdef CONFIG_FREERTOS_ISR_STATS
-    rsr a2, CCOUNT
-    #endif
-
     addi    sp,  sp, XT_STK_FRMSZ      /* go back to spill register region */
     SPILL_ALL_WINDOWS                  /* place the live register windows there */ 
     addi    sp,  sp, -XT_STK_FRMSZ     /* return the current stack pointer and proceed with context save*/
-
-    #ifdef CONFIG_FREERTOS_ISR_STATS
-    rsr a3, CCOUNT
-    sub  a3, a3, a2
-    movi a2, isr_enter_spent_time_cycles
-    s32i a3,a2,0
-    #endif //CONFIG_ISR_TIMING_STATS
     
     #endif
 
diff --git a/components/idf_test/include/idf_performance.h b/components/idf_test/include/idf_performance.h
index a5b88eb24..8e0eb5a34 100644
--- a/components/idf_test/include/idf_performance.h
+++ b/components/idf_test/include/idf_performance.h
@@ -33,6 +33,9 @@
 // SHA256 hardware throughput at 240MHz, threshold set lower than worst case
 #define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC                             9.0
 #define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES                                    150
+#define IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES    290
+#define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES     550
+
 
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP  19000
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PRIVATE_OP 180000

From c64e108a1d8ffab7c44d677b4f28cfae154b6ead Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Thu, 24 Oct 2019 17:07:11 -0300
Subject: [PATCH 13/21] components/freertos: removed CONFIG_FREERTOS_ISR_STATS
 the ISR test is now self contained

---
 components/freertos/Kconfig | 10 ----------
 1 file changed, 10 deletions(-)

diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig
index 0a589980f..22b190447 100644
--- a/components/freertos/Kconfig
+++ b/components/freertos/Kconfig
@@ -435,18 +435,8 @@ menu "FreeRTOS"
             would be checked to be in compliance with Vanilla FreeRTOS.
             e.g Calling port*_CRITICAL from ISR context would cause assert failure
 
-<<<<<<< HEAD
     config FREERTOS_DEBUG_OCDAWARE
         bool
         help
             Hidden option, gets selected by CONFIG_ESPxx_DEBUG_OCDAWARE
-
-=======
-    config FREERTOS_ISR_STATS
-        bool "Enable cycle measurement inside ISR"
-        default n
-        help
-            If enabled, every context save operation will have its time
-            spent in cycles, measured.
->>>>>>> 0f141ba8a... freertos/xtensa_context: added conditional compiling option around isr cycle measurement
 endmenu

From f119cc58cfb12f258e7e3e0d644d9a2c94296378 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Thu, 24 Oct 2019 17:08:21 -0300
Subject: [PATCH 14/21] components/freertos: tuned performance value for ISR
 exit cycles to pass in test in -Og

---
 components/idf_test/include/idf_performance.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/idf_test/include/idf_performance.h b/components/idf_test/include/idf_performance.h
index 8e0eb5a34..6a67e4b5e 100644
--- a/components/idf_test/include/idf_performance.h
+++ b/components/idf_test/include/idf_performance.h
@@ -34,7 +34,7 @@
 #define IDF_PERFORMANCE_MIN_SHA256_THROUGHPUT_MBSEC                             9.0
 #define IDF_PERFORMANCE_MAX_SPILL_REG_CYCLES                                    150
 #define IDF_PERFORMANCE_MAX_ISR_ENTER_CYCLES    290
-#define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES     550
+#define IDF_PERFORMANCE_MAX_ISR_EXIT_CYCLES     565
 
 
 #define IDF_PERFORMANCE_MAX_RSA_2048KEY_PUBLIC_OP  19000

From 64a50f0423ff7f382e0977959bcaad5ed51362a9 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Thu, 24 Oct 2019 17:31:19 -0300
Subject: [PATCH 15/21] components/freertos: fixed isr test failling when run
 multiple times

---
 components/freertos/test/test_isr_latency.c | 6 +++---
 components/freertos/xtensa_context.S        | 2 ++
 2 files changed, 5 insertions(+), 3 deletions(-)

diff --git a/components/freertos/test/test_isr_latency.c b/components/freertos/test/test_isr_latency.c
index 3c8d78685..5999b72f3 100644
--- a/components/freertos/test/test_isr_latency.c
+++ b/components/freertos/test/test_isr_latency.c
@@ -19,9 +19,8 @@ static SemaphoreHandle_t sync;
 static SemaphoreHandle_t end_sema;
 uint32_t cycle_before_trigger;
 uint32_t cycle_before_exit;
-uint32_t delta_enter_cycles;
-uint32_t delta_enter_cycles;
-uint32_t delta_exit_cycles;
+uint32_t delta_enter_cycles = 0;
+uint32_t delta_exit_cycles = 0;
 
 static void software_isr(void *arg) {
     (void)arg;
@@ -56,6 +55,7 @@ static void test_task(void *arg) {
     delta_enter_cycles /= 10000;
     delta_exit_cycles /= 10000;
 
+    esp_intr_free(handle);
     xSemaphoreGive(end_sema);
     vTaskDelete(NULL);
 }
diff --git a/components/freertos/xtensa_context.S b/components/freertos/xtensa_context.S
index 3d1d979d6..4db99114b 100644
--- a/components/freertos/xtensa_context.S
+++ b/components/freertos/xtensa_context.S
@@ -96,6 +96,7 @@ Exit conditions:
     .align  4
 	.literal_position
     .align  4
+
 _xt_context_save:
     s32i    a2,  sp, XT_STK_A2
     s32i    a3,  sp, XT_STK_A3
@@ -195,6 +196,7 @@ _not_l1:
     #endif
 
     ret
+
 /*******************************************************************************
 
 _xt_context_restore

From 55cbc213f37bd63931bdaf485a3558a0f093cc67 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Thu, 24 Oct 2019 17:36:37 -0300
Subject: [PATCH 16/21] components/freertos: create the test task with highest
 priority to ensure peer-to-peer ISR to task sync

---
 components/freertos/test/test_isr_latency.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/freertos/test/test_isr_latency.c b/components/freertos/test/test_isr_latency.c
index 5999b72f3..a4b344f11 100644
--- a/components/freertos/test/test_isr_latency.c
+++ b/components/freertos/test/test_isr_latency.c
@@ -66,7 +66,7 @@ TEST_CASE("isr latency test", "[freertos] [ignore]")
     TEST_ASSERT(sync != NULL);
     end_sema = xSemaphoreCreateBinary();
     TEST_ASSERT(end_sema != NULL);
-    xTaskCreatePinnedToCore(test_task, "tst" , 4096, NULL, 3, NULL, 0);
+    xTaskCreatePinnedToCore(test_task, "tst" , 4096, NULL, configMAX_PRIORITIES - 1, NULL, 0);
     BaseType_t result = xSemaphoreTake(end_sema, portMAX_DELAY);    
     TEST_ASSERT_EQUAL_HEX32(pdTRUE, result);
     TEST_PERFORMANCE_LESS_THAN(ISR_ENTER_CYCLES, "%d cycles" ,delta_enter_cycles);

From 8cd2831ec1416d41156e44a6d7bf0d20f751c333 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Tue, 29 Oct 2019 19:09:14 -0300
Subject: [PATCH 17/21] components/unity: re-enabled setjmp longjmp block on
 unity

---
 components/unity/include/unity_config.h | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/components/unity/include/unity_config.h b/components/unity/include/unity_config.h
index 67f882a9a..85a8d9c54 100644
--- a/components/unity/include/unity_config.h
+++ b/components/unity/include/unity_config.h
@@ -26,7 +26,16 @@
 #endif
 
 #define UNITY_EXCLUDE_TIME_H
-#define UNITY_EXCLUDE_SETJMP_H
+
+/**
+ * @note For some reason setjmp does not work with 
+ * unity in local tests for, at least now, unknown 
+ * reasons since the interrupt handling was modified
+ * so if you want to perform tests locally, 
+ * uncomment this line. Remote tests on CI
+ * still working as expected 
+ */ 
+//#define UNITY_EXCLUDE_SETJMP_H
 
 void unity_flush(void);
 void unity_putc(int c);

From 3882d986bdec3876beefe262dd8c83a4f8896d70 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Tue, 5 Nov 2019 14:27:27 +0800
Subject: [PATCH 18/21] components/unity: reverted the inclusion of test
 protect based on setjmp

---
 components/unity/include/unity_config.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/components/unity/include/unity_config.h b/components/unity/include/unity_config.h
index 85a8d9c54..a0786f6ea 100644
--- a/components/unity/include/unity_config.h
+++ b/components/unity/include/unity_config.h
@@ -35,7 +35,7 @@
  * uncomment this line. Remote tests on CI
  * still working as expected 
  */ 
-//#define UNITY_EXCLUDE_SETJMP_H
+#define UNITY_EXCLUDE_SETJMP_H
 
 void unity_flush(void);
 void unity_putc(int c);

From 0ea6453b1caa83b21ddfd25243133923ba70f289 Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Tue, 26 Nov 2019 14:49:08 -0300
Subject: [PATCH 19/21] freertos: changed isr time test case variables to
 static

---
 components/freertos/Kconfig                 | 1 +
 components/freertos/test/CMakeLists.txt     | 2 +-
 components/freertos/test/test_isr_latency.c | 8 ++++----
 components/unity/include/unity_config.h     | 8 +++-----
 4 files changed, 9 insertions(+), 10 deletions(-)

diff --git a/components/freertos/Kconfig b/components/freertos/Kconfig
index 22b190447..198722331 100644
--- a/components/freertos/Kconfig
+++ b/components/freertos/Kconfig
@@ -439,4 +439,5 @@ menu "FreeRTOS"
         bool
         help
             Hidden option, gets selected by CONFIG_ESPxx_DEBUG_OCDAWARE
+
 endmenu
diff --git a/components/freertos/test/CMakeLists.txt b/components/freertos/test/CMakeLists.txt
index 8f40b2df0..896bb5795 100644
--- a/components/freertos/test/CMakeLists.txt
+++ b/components/freertos/test/CMakeLists.txt
@@ -5,7 +5,7 @@ if(IDF_TARGET STREQUAL "esp32")
 endif()
 
 
-idf_component_register(SRC_DIRS ${src_dirs}
+idf_component_register(SRC_DIRS ${srcdirs}
                        INCLUDE_DIRS .
                        REQUIRES unity test_utils
                       )
\ No newline at end of file
diff --git a/components/freertos/test/test_isr_latency.c b/components/freertos/test/test_isr_latency.c
index a4b344f11..46749173d 100644
--- a/components/freertos/test/test_isr_latency.c
+++ b/components/freertos/test/test_isr_latency.c
@@ -17,10 +17,10 @@
 
 static SemaphoreHandle_t sync;
 static SemaphoreHandle_t end_sema;
-uint32_t cycle_before_trigger;
-uint32_t cycle_before_exit;
-uint32_t delta_enter_cycles = 0;
-uint32_t delta_exit_cycles = 0;
+static uint32_t cycle_before_trigger;
+static uint32_t cycle_before_exit;
+static uint32_t delta_enter_cycles = 0;
+static uint32_t delta_exit_cycles = 0;
 
 static void software_isr(void *arg) {
     (void)arg;
diff --git a/components/unity/include/unity_config.h b/components/unity/include/unity_config.h
index a0786f6ea..686fb2507 100644
--- a/components/unity/include/unity_config.h
+++ b/components/unity/include/unity_config.h
@@ -29,11 +29,9 @@
 
 /**
  * @note For some reason setjmp does not work with 
- * unity in local tests for, at least now, unknown 
- * reasons since the interrupt handling was modified
- * so if you want to perform tests locally, 
- * uncomment this line. Remote tests on CI
- * still working as expected 
+ * unity, since it is only used on test entry and
+ * exit it should not impact the rest of test
+ * framework. So we disable it here.  
  */ 
 #define UNITY_EXCLUDE_SETJMP_H
 

From 57522059aa786be06e428fcfd9796b2a49fc519b Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Mon, 2 Dec 2019 12:31:17 -0300
Subject: [PATCH 20/21] freertos/tests: fixed wrong header file on isr latency
 test

---
 components/freertos/test/test_isr_latency.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/components/freertos/test/test_isr_latency.c b/components/freertos/test/test_isr_latency.c
index 46749173d..10c5d3069 100644
--- a/components/freertos/test/test_isr_latency.c
+++ b/components/freertos/test/test_isr_latency.c
@@ -1,6 +1,5 @@
 #include <esp_types.h>
 #include <stdio.h>
-#include "esp32/rom/ets_sys.h"
 
 #include "freertos/FreeRTOS.h"
 #include "freertos/task.h"

From b0491307fc5617587e85e088c55104a751faeeff Mon Sep 17 00:00:00 2001
From: Felipe Neves <felipe.neves@espressif.com>
Date: Tue, 3 Dec 2019 11:42:40 -0300
Subject: [PATCH 21/21] target-test: bumping test cases parallel count

---
 tools/ci/config/target-test.yml | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/tools/ci/config/target-test.yml b/tools/ci/config/target-test.yml
index 565872872..47044a1c5 100644
--- a/tools/ci/config/target-test.yml
+++ b/tools/ci/config/target-test.yml
@@ -307,7 +307,7 @@ example_test_012:
 
 UT_001:
   extends: .unit_test_template
-  parallel: 28
+  parallel: 30
   tags:
     - ESP32_IDF
     - UT_T1_1
@@ -316,7 +316,7 @@ UT_001:
 
 UT_002:
   extends: .unit_test_template
-  parallel: 9
+  parallel: 11
   tags:
     - ESP32_IDF
     - UT_T1_1
@@ -466,7 +466,7 @@ UT_034:
 
 UT_035:
   extends: .unit_test_template
-  parallel: 17
+  parallel: 20
   tags:
     - ESP32S2BETA_IDF
     - UT_T1_1