From 91508ca27ffcd5de6c53ebd66ad6206d980f484e Mon Sep 17 00:00:00 2001
From: suda-morris <362953310@qq.com>
Date: Wed, 3 Apr 2019 17:08:02 +0800
Subject: [PATCH] add esp32s2beta in soc component

---
 components/driver/cas.h                       |   23 +
 components/lwip/CMakeLists.txt                |    4 -
 components/soc/component.mk                   |    1 +
 components/soc/esp32/include/soc/dport_reg.h  |   12 +-
 .../soc/esp32/include/soc/hwcrypto_reg.h      |   14 +-
 components/soc/esp32/include/soc/io_mux_reg.h |   15 +-
 components/soc/esp32/include/soc/soc.h        |   54 +-
 components/soc/esp32/include/soc/spi_pins.h   |    7 +-
 components/soc/esp32/soc_memory_layout.c      |    4 +-
 components/soc/esp32/spi_periph.c             |   11 +-
 components/soc/esp32s2beta/component.mk       |    1 +
 components/soc/esp32s2beta/cpu_util.c         |   63 +
 components/soc/esp32s2beta/i2c_apll.h         |  136 +
 components/soc/esp32s2beta/i2c_bbpll.h        |  184 +
 components/soc/esp32s2beta/i2c_rtc_clk.h      |   48 +
 .../soc/esp32s2beta/include/soc/adc_channel.h |   78 +
 .../esp32s2beta/include/soc/apb_ctrl_reg.h    |  841 ++
 .../esp32s2beta/include/soc/apb_ctrl_struct.h |  524 +
 .../include/soc/assist_debug_reg.h            |  115 +
 .../soc/esp32s2beta/include/soc/bb_reg.h      |   42 +
 .../soc/esp32s2beta/include/soc/boot_mode.h   |   92 +
 .../esp32s2beta/include/soc/clkout_channel.h  |   26 +
 components/soc/esp32s2beta/include/soc/cpu.h  |  104 +
 .../soc/esp32s2beta/include/soc/dac_channel.h |   24 +
 .../esp32s2beta/include/soc/dport_access.h    |  111 +
 .../soc/esp32s2beta/include/soc/dport_reg.h   |  193 +
 .../soc/esp32s2beta/include/soc/efuse_reg.h   | 2122 ++++
 .../esp32s2beta/include/soc/efuse_struct.h    |  407 +
 .../soc/esp32s2beta/include/soc/extmem_reg.h  | 1459 +++
 .../soc/esp32s2beta/include/soc/fe_reg.h      |   41 +
 .../esp32s2beta/include/soc/frc_timer_reg.h   |   52 +
 .../soc/esp32s2beta/include/soc/gpio_reg.h    | 9222 +++++++++++++++++
 .../soc/esp32s2beta/include/soc/gpio_sd_reg.h |  172 +
 .../esp32s2beta/include/soc/gpio_sd_struct.h  |   57 +
 .../esp32s2beta/include/soc/gpio_sig_map.h    |  288 +
 .../soc/esp32s2beta/include/soc/gpio_struct.h |  196 +
 .../soc/esp32s2beta/include/soc/hinf_reg.h    |  248 +
 .../soc/esp32s2beta/include/soc/hinf_struct.h |  134 +
 .../soc/esp32s2beta/include/soc/host_reg.h    | 1806 ++++
 .../soc/esp32s2beta/include/soc/host_struct.h |  602 ++
 .../esp32s2beta/include/soc/hwcrypto_reg.h    |  107 +
 .../soc/esp32s2beta/include/soc/i2c_reg.h     | 1122 ++
 .../soc/esp32s2beta/include/soc/i2c_struct.h  |  339 +
 .../soc/esp32s2beta/include/soc/i2s_reg.h     | 1728 +++
 .../soc/esp32s2beta/include/soc/i2s_struct.h  |  505 +
 .../esp32s2beta/include/soc/interrupt_reg.h   |  772 ++
 .../soc/esp32s2beta/include/soc/io_mux_reg.h  |  391 +
 .../soc/esp32s2beta/include/soc/ledc_reg.h    | 3002 ++++++
 .../soc/esp32s2beta/include/soc/ledc_struct.h |  356 +
 .../soc/esp32s2beta/include/soc/mcpwm_reg.h   | 3028 ++++++
 .../esp32s2beta/include/soc/mcpwm_struct.h    |  462 +
 .../soc/esp32s2beta/include/soc/nrx_reg.h     |   55 +
 .../soc/esp32s2beta/include/soc/pcnt_reg.h    | 1742 ++++
 .../soc/esp32s2beta/include/soc/pcnt_struct.h |  180 +
 .../soc/esp32s2beta/include/soc/periph_defs.h |  165 +
 .../soc/esp32s2beta/include/soc/rmt_reg.h     | 2964 ++++++
 .../soc/esp32s2beta/include/soc/rmt_struct.h  |  376 +
 components/soc/esp32s2beta/include/soc/rtc.h  |  662 ++
 .../esp32s2beta/include/soc/rtc_cntl_reg.h    | 3182 ++++++
 .../esp32s2beta/include/soc/rtc_cntl_struct.h |  645 ++
 .../include/soc/rtc_gpio_channel.h            |   73 +
 .../soc/esp32s2beta/include/soc/rtc_i2c_reg.h |  690 ++
 .../esp32s2beta/include/soc/rtc_i2c_struct.h  |  230 +
 .../soc/esp32s2beta/include/soc/rtc_io_reg.h  | 2284 ++++
 .../esp32s2beta/include/soc/rtc_io_struct.h   |  356 +
 .../soc/esp32s2beta/include/soc/sdmmc_reg.h   |   96 +
 .../esp32s2beta/include/soc/sdmmc_struct.h    |  377 +
 .../soc/esp32s2beta/include/soc/sens_reg.h    | 1267 +++
 .../soc/esp32s2beta/include/soc/sens_struct.h |  373 +
 .../esp32s2beta/include/soc/sensitive_reg.h   | 1220 +++
 .../soc/esp32s2beta/include/soc/slc_reg.h     | 1914 ++++
 .../soc/esp32s2beta/include/soc/slc_struct.h  |  588 ++
 components/soc/esp32s2beta/include/soc/soc.h  |  373 +
 .../soc/esp32s2beta/include/soc/soc_ulp.h     |   46 +
 .../soc/esp32s2beta/include/soc/spi_mem_reg.h | 1893 ++++
 .../esp32s2beta/include/soc/spi_mem_struct.h  |  741 ++
 .../soc/esp32s2beta/include/soc/spi_pins.h    |   40 +
 .../soc/esp32s2beta/include/soc/spi_reg.h     | 1646 +++
 .../soc/esp32s2beta/include/soc/spi_struct.h  |  677 ++
 .../soc/esp32s2beta/include/soc/syscon_reg.h  |  896 ++
 .../esp32s2beta/include/soc/syscon_struct.h   |  123 +
 .../soc/esp32s2beta/include/soc/system_reg.h  |  891 ++
 .../esp32s2beta/include/soc/timer_group_reg.h |  724 ++
 .../include/soc/timer_group_struct.h          |  221 +
 .../esp32s2beta/include/soc/touch_channel.h   |   49 +
 .../esp32s2beta/include/soc/uart_channel.h    |   61 +
 .../soc/esp32s2beta/include/soc/uart_reg.h    | 1100 ++
 .../soc/esp32s2beta/include/soc/uart_struct.h |  375 +
 .../soc/esp32s2beta/include/soc/uhci_reg.h    | 1270 +++
 .../soc/esp32s2beta/include/soc/uhci_struct.h |  365 +
 .../soc/esp32s2beta/include/soc/wdev_reg.h    |   21 +
 components/soc/esp32s2beta/rtc_clk.c          |  840 ++
 components/soc/esp32s2beta/rtc_init.c         |  237 +
 components/soc/esp32s2beta/rtc_pm.c           |   67 +
 components/soc/esp32s2beta/rtc_sleep.c        |  189 +
 components/soc/esp32s2beta/rtc_time.c         |  166 +
 components/soc/esp32s2beta/soc_log.h          |   29 +
 .../soc/esp32s2beta/soc_memory_layout.c       |  148 +
 components/soc/esp32s2beta/sources.cmake      |   12 +
 components/soc/esp32s2beta/spi_periph.c       |  123 +
 .../soc/esp32s2beta/test/test_rtc_clk.c       |  284 +
 .../soc/include/soc/soc_memory_layout.h       |    8 +-
 components/soc/include/soc/spi_periph.h       |   17 +-
 103 files changed, 64354 insertions(+), 62 deletions(-)
 create mode 100644 components/driver/cas.h
 create mode 100644 components/soc/esp32s2beta/component.mk
 create mode 100644 components/soc/esp32s2beta/cpu_util.c
 create mode 100644 components/soc/esp32s2beta/i2c_apll.h
 create mode 100644 components/soc/esp32s2beta/i2c_bbpll.h
 create mode 100644 components/soc/esp32s2beta/i2c_rtc_clk.h
 create mode 100644 components/soc/esp32s2beta/include/soc/adc_channel.h
 create mode 100644 components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/assist_debug_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/bb_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/boot_mode.h
 create mode 100644 components/soc/esp32s2beta/include/soc/clkout_channel.h
 create mode 100644 components/soc/esp32s2beta/include/soc/cpu.h
 create mode 100644 components/soc/esp32s2beta/include/soc/dac_channel.h
 create mode 100644 components/soc/esp32s2beta/include/soc/dport_access.h
 create mode 100644 components/soc/esp32s2beta/include/soc/dport_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/efuse_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/efuse_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/extmem_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/fe_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/frc_timer_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/gpio_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/gpio_sd_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/gpio_sd_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/gpio_sig_map.h
 create mode 100644 components/soc/esp32s2beta/include/soc/gpio_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/hinf_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/hinf_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/host_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/host_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/hwcrypto_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/i2c_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/i2c_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/i2s_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/i2s_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/interrupt_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/io_mux_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/ledc_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/ledc_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/mcpwm_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/mcpwm_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/nrx_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/pcnt_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/pcnt_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/periph_defs.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rmt_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rmt_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc_io_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/rtc_io_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/sdmmc_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/sdmmc_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/sens_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/sens_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/sensitive_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/slc_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/slc_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/soc.h
 create mode 100644 components/soc/esp32s2beta/include/soc/soc_ulp.h
 create mode 100644 components/soc/esp32s2beta/include/soc/spi_mem_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/spi_mem_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/spi_pins.h
 create mode 100644 components/soc/esp32s2beta/include/soc/spi_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/spi_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/syscon_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/syscon_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/system_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/timer_group_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/timer_group_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/touch_channel.h
 create mode 100644 components/soc/esp32s2beta/include/soc/uart_channel.h
 create mode 100644 components/soc/esp32s2beta/include/soc/uart_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/uart_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/uhci_reg.h
 create mode 100644 components/soc/esp32s2beta/include/soc/uhci_struct.h
 create mode 100644 components/soc/esp32s2beta/include/soc/wdev_reg.h
 create mode 100644 components/soc/esp32s2beta/rtc_clk.c
 create mode 100644 components/soc/esp32s2beta/rtc_init.c
 create mode 100644 components/soc/esp32s2beta/rtc_pm.c
 create mode 100644 components/soc/esp32s2beta/rtc_sleep.c
 create mode 100644 components/soc/esp32s2beta/rtc_time.c
 create mode 100644 components/soc/esp32s2beta/soc_log.h
 create mode 100644 components/soc/esp32s2beta/soc_memory_layout.c
 create mode 100644 components/soc/esp32s2beta/sources.cmake
 create mode 100644 components/soc/esp32s2beta/spi_periph.c
 create mode 100644 components/soc/esp32s2beta/test/test_rtc_clk.c

diff --git a/components/driver/cas.h b/components/driver/cas.h
new file mode 100644
index 000000000..31a32f1d0
--- /dev/null
+++ b/components/driver/cas.h
@@ -0,0 +1,23 @@
+
+#ifndef __CAS_H__
+#define __CAS_H__
+
+#include "sdkconfig.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/portmacro.h"
+
+#define __cas_temp_sync_compare_and_swap_test(ptr, expected, desired) ({\
+    bool ret = false;\
+    unsigned state = portENTER_CRITICAL_NESTED(); \
+    if (*ptr == expected) { \
+        *ptr = desired; \
+        ret = true;\
+    }\
+    portEXIT_CRITICAL_NESTED(state); \
+    ret; \
+})
+
+#define __sync_bool_compare_and_swap(ptr, expected, desired) __cas_temp_sync_compare_and_swap_test(ptr, expected, desired)
+
+
+#endif
\ No newline at end of file
diff --git a/components/lwip/CMakeLists.txt b/components/lwip/CMakeLists.txt
index 0467902dc..ca028b99f 100644
--- a/components/lwip/CMakeLists.txt
+++ b/components/lwip/CMakeLists.txt
@@ -86,11 +86,7 @@ set(COMPONENT_SRCS "apps/dhcpserver/dhcpserver.c"
                    "port/esp32/debug/lwip_debug.c"
                    "port/esp32/freertos/sys_arch.c"
                    "port/esp32/netif/dhcp_state.c"
-<<<<<<< bce8b14e7324423a5caad1c6a240e97fdc45afe2
-                   "port/esp32/netif/ethernetif.c"
                    "port/esp32/netif/nettestif.c"
-=======
->>>>>>> Ethernet peripheral will depend on IDF_TARGET
                    "port/esp32/netif/wlanif.c")
 
 if(CONFIG_IDF_TARGET_ESP32)
diff --git a/components/soc/component.mk b/components/soc/component.mk
index 22d239cbe..9aed53c28 100644
--- a/components/soc/component.mk
+++ b/components/soc/component.mk
@@ -5,4 +5,5 @@ COMPONENT_SRCDIRS := $(SOC_NAME) src src/hal
 COMPONENT_ADD_INCLUDEDIRS := $(SOC_NAME)/include include
 
 -include $(COMPONENT_PATH)/$(SOC_NAME)/component.mk
+
 COMPONENT_ADD_LDFRAGMENTS += linker.lf
diff --git a/components/soc/esp32/include/soc/dport_reg.h b/components/soc/esp32/include/soc/dport_reg.h
index 9cc3320b3..b9f2c31e2 100644
--- a/components/soc/esp32/include/soc/dport_reg.h
+++ b/components/soc/esp32/include/soc/dport_reg.h
@@ -19,7 +19,7 @@
 #ifndef __ASSEMBLER__
 #include "dport_access.h"
 #endif
-   
+
 /* Registers defined in this header file must be accessed using special macros,
  * prefixed with DPORT_. See soc/dport_access.h file for details.
  */
@@ -961,7 +961,6 @@
 #define DPORT_CAN_CLK_EN   (BIT(19))
 #define DPORT_I2C_EXT1_CLK_EN   (BIT(18))
 #define DPORT_PWM0_CLK_EN   (BIT(17))
-#define DPORT_SPI_CLK_EN_2   (BIT(16)) /** Deprecated, please use DPORT_SPI3_CLK_EN **/
 #define DPORT_SPI3_CLK_EN   (BIT(16))
 #define DPORT_TIMERGROUP1_CLK_EN   (BIT(15))
 #define DPORT_EFUSE_CLK_EN   (BIT(14))
@@ -972,13 +971,11 @@
 #define DPORT_RMT_CLK_EN   (BIT(9))
 #define DPORT_UHCI0_CLK_EN   (BIT(8))
 #define DPORT_I2C_EXT0_CLK_EN   (BIT(7))
-#define DPORT_SPI_CLK_EN   (BIT(6)) /** Deprecated, please use DPORT_SPI2_CLK_EN **/
 #define DPORT_SPI2_CLK_EN   (BIT(6))
 #define DPORT_UART1_CLK_EN   (BIT(5))
 #define DPORT_I2S0_CLK_EN   (BIT(4))
 #define DPORT_WDG_CLK_EN   (BIT(3))
 #define DPORT_UART_CLK_EN   (BIT(2))
-#define DPORT_SPI_CLK_EN_1   (BIT(1)) /** Deprecated, please use DPORT_SPI01_CLK_EN **/
 #define DPORT_SPI01_CLK_EN   (BIT(1))
 #define DPORT_TIMERS_CLK_EN   (BIT(0))
 #define DPORT_PERIP_RST_EN_REG          (DR_REG_DPORT_BASE + 0x0C4)
@@ -998,7 +995,6 @@
 #define DPORT_CAN_RST   (BIT(19))
 #define DPORT_I2C_EXT1_RST   (BIT(18))
 #define DPORT_PWM0_RST   (BIT(17))
-#define DPORT_SPI_RST_2   (BIT(16)) /** Deprecated, please use DPORT_SPI3_RST **/
 #define DPORT_SPI3_RST   (BIT(16))
 #define DPORT_TIMERGROUP1_RST   (BIT(15))
 #define DPORT_EFUSE_RST   (BIT(14))
@@ -1009,13 +1005,11 @@
 #define DPORT_RMT_RST   (BIT(9))
 #define DPORT_UHCI0_RST   (BIT(8))
 #define DPORT_I2C_EXT0_RST   (BIT(7))
-#define DPORT_SPI_RST   (BIT(6)) /** Deprecated, please use DPORT_SPI2_RST **/
 #define DPORT_SPI2_RST   (BIT(6))
 #define DPORT_UART1_RST   (BIT(5))
 #define DPORT_I2S0_RST   (BIT(4))
 #define DPORT_WDG_RST   (BIT(3))
 #define DPORT_UART_RST   (BIT(2))
-#define DPORT_SPI_RST_1   (BIT(1)) /** Deprecated, please use DPORT_SPI01_RST **/
 #define DPORT_SPI01_RST   (BIT(1))
 #define DPORT_TIMERS_RST   (BIT(0))
 #define DPORT_SLAVE_SPI_CONFIG_REG          (DR_REG_DPORT_BASE + 0x0C8)
@@ -1090,7 +1084,7 @@
 #define DPORT_BT_RST (BIT(3))
 #define DPORT_MAC_RST (BIT(2))
 #define DPORT_FE_RST (BIT(1))
-#define DPORT_BB_RST (BIT(0))  
+#define DPORT_BB_RST (BIT(0))
 
 #define DPORT_BT_LPCK_DIV_INT_REG          (DR_REG_DPORT_BASE + 0x0D4)
 /* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */
@@ -4283,6 +4277,8 @@
 
 #define DPORT_FLASH_MMU_TABLE_INVALID_VAL 0x100
 
+#define DPORT_MMU_ADDRESS_MASK 0xff
+
 #endif /*_SOC_DPORT_REG_H_ */
 
 
diff --git a/components/soc/esp32/include/soc/hwcrypto_reg.h b/components/soc/esp32/include/soc/hwcrypto_reg.h
index d0dfa7485..1db081f2b 100644
--- a/components/soc/esp32/include/soc/hwcrypto_reg.h
+++ b/components/soc/esp32/include/soc/hwcrypto_reg.h
@@ -26,16 +26,22 @@
 
 #define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
 #define RSA_MODEXP_MODE_REG           (DR_REG_RSA_BASE + 0x804)
-#define RSA_START_MODEXP_REG          (DR_REG_RSA_BASE + 0x808)
+#define RSA_MODEXP_START_REG          (DR_REG_RSA_BASE + 0x808)
 #define RSA_MULT_MODE_REG             (DR_REG_RSA_BASE + 0x80c)
 #define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x810)
 
-#define RSA_INTERRUPT_REG             (DR_REG_RSA_BASE + 0x814)
+#define RSA_CLEAR_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x814)
+#define RSA_QUERY_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x814) /* same */
 
-#define RSA_CLEAN_REG                 (DR_REG_RSA_BASE + 0x818)
+#define RSA_QUERY_CLEAN_REG           (DR_REG_RSA_BASE + 0x818)
+
+/* Backwards compatibility register names used pre-ESP32S2 */
+#define RSA_CLEAN_REG                 (RSA_QUERY_CLEAN_REG)
+#define RSA_INTERRUPT_REG             (RSA_CLEAR_INTERRUPT_REG)
+#define RSA_START_MODEXP_REG          (RSA_MODEXP_START_REG)
 
 /* SHA acceleration registers */
-#define SHA_TEXT_BASE          ((DR_REG_SHA_BASE) + 0x00)
+#define SHA_TEXT_BASE           ((DR_REG_SHA_BASE) + 0x00)
 
 #define SHA_1_START_REG         ((DR_REG_SHA_BASE) + 0x80)
 #define SHA_1_CONTINUE_REG      ((DR_REG_SHA_BASE) + 0x84)
diff --git a/components/soc/esp32/include/soc/io_mux_reg.h b/components/soc/esp32/include/soc/io_mux_reg.h
index 25978b326..bf7d59e52 100644
--- a/components/soc/esp32/include/soc/io_mux_reg.h
+++ b/components/soc/esp32/include/soc/io_mux_reg.h
@@ -79,9 +79,9 @@
 
 /*
  * @attention
- *     The PIN_PULL[UP|DWN]_[EN|DIS]() functions used to exist as macros in previous SDK versions. 
- *     Unfortunately, however, they do not work for some GPIOs on the ESP32 chip, which needs pullups 
- *     and -downs turned on and off through RTC registers. The functions still exist for compatibility 
+ *     The PIN_PULL[UP|DWN]_[EN|DIS]() functions used to exist as macros in previous SDK versions.
+ *     Unfortunately, however, they do not work for some GPIOs on the ESP32 chip, which needs pullups
+ *     and -downs turned on and off through RTC registers. The functions still exist for compatibility
  *     with older code, but are marked as deprecated in order to generate a warning.
  *     Please replace them in this fashion: (make sure to include driver/gpio.h as well)
  *     PIN_PULLUP_EN(GPIO_PIN_MUX_REG[x])   ->  gpio_pullup_en(x)
@@ -90,7 +90,7 @@
  *     PIN_PULLDWN_DIS(GPIO_PIN_MUX_REG[x]) ->  gpio_pulldown_dis(x)
  *
 */
-static inline void __attribute__ ((deprecated)) PIN_PULLUP_DIS(uint32_t PIN_NAME) 
+static inline void __attribute__ ((deprecated)) PIN_PULLUP_DIS(uint32_t PIN_NAME)
 {
     REG_CLR_BIT(PIN_NAME, FUN_PU);
 }
@@ -115,6 +115,13 @@ static inline void __attribute__ ((deprecated)) PIN_PULLDWN_EN(uint32_t PIN_NAME
 
 #define PIN_FUNC_GPIO                               2
 
+#define SPI_CLK_GPIO_NUM                            6
+#define SPI_CS0_GPIO_NUM                            11
+#define SPI_Q_GPIO_NUM                              7
+#define SPI_D_GPIO_NUM                              8
+#define SPI_WP_GPIO_NUM                             10
+#define SPI_HD_GPIO_NUM                             9
+
 #define PIN_CTRL                          (DR_REG_IO_MUX_BASE +0x00)
 #define CLK_OUT3                                    0xf
 #define CLK_OUT3_V                                  CLK_OUT3
diff --git a/components/soc/esp32/include/soc/soc.h b/components/soc/esp32/include/soc/soc.h
index 5901abca2..afe45c921 100644
--- a/components/soc/esp32/include/soc/soc.h
+++ b/components/soc/esp32/include/soc/soc.h
@@ -25,19 +25,6 @@
 #define PRO_CPU_NUM (0)
 #define APP_CPU_NUM (1)
 
-/* Overall memory map */
-#define SOC_IROM_LOW            0x400D0000
-#define SOC_IROM_HIGH           0x40400000
-#define SOC_DROM_LOW            0x3F400000
-#define SOC_DROM_HIGH           0x3F800000
-#define SOC_DRAM_LOW            0x3FFAE000
-#define SOC_DRAM_HIGH           0x40000000
-#define SOC_RTC_IRAM_LOW        0x400C0000
-#define SOC_RTC_IRAM_HIGH       0x400C2000
-#define SOC_RTC_DATA_LOW        0x50000000
-#define SOC_RTC_DATA_HIGH       0x50002000
-#define SOC_EXTRAM_DATA_LOW     0x3F800000
-#define SOC_EXTRAM_DATA_HIGH    0x3FC00000
 
 #define SOC_MAX_CONTIGUOUS_RAM_SIZE 0x400000 ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
 
@@ -246,24 +233,28 @@
 //}}
 
 /* Overall memory map */
-#define SOC_DROM_LOW    0x3F400000
-#define SOC_DROM_HIGH   0x3F800000
-#define SOC_IROM_LOW    0x400D0000
-#define SOC_IROM_HIGH   0x40400000
-#define SOC_IROM_MASK_LOW   0x40000000
-#define SOC_IROM_MASK_HIGH  0x40070000
-#define SOC_CACHE_PRO_LOW   0x40070000
-#define SOC_CACHE_PRO_HIGH  0x40078000
-#define SOC_CACHE_APP_LOW   0x40078000
-#define SOC_CACHE_APP_HIGH  0x40080000
-#define SOC_IRAM_LOW    0x40080000
-#define SOC_IRAM_HIGH   0x400A0000
-#define SOC_RTC_IRAM_LOW  0x400C0000
-#define SOC_RTC_IRAM_HIGH 0x400C2000
-#define SOC_RTC_DRAM_LOW  0x3FF80000
-#define SOC_RTC_DRAM_HIGH 0x3FF82000
-#define SOC_RTC_DATA_LOW  0x50000000
-#define SOC_RTC_DATA_HIGH 0x50002000
+#define SOC_DROM_LOW            0x3F400000
+#define SOC_DROM_HIGH           0x3F800000
+#define SOC_DRAM_LOW            0x3FFAE000
+#define SOC_DRAM_HIGH           0x40000000
+#define SOC_IROM_LOW            0x400D0000
+#define SOC_IROM_HIGH           0x40400000
+#define SOC_IROM_MASK_LOW       0x40000000
+#define SOC_IROM_MASK_HIGH      0x40070000
+#define SOC_CACHE_PRO_LOW       0x40070000
+#define SOC_CACHE_PRO_HIGH      0x40078000
+#define SOC_CACHE_APP_LOW       0x40078000
+#define SOC_CACHE_APP_HIGH      0x40080000
+#define SOC_IRAM_LOW            0x40080000
+#define SOC_IRAM_HIGH           0x400A0000
+#define SOC_RTC_IRAM_LOW        0x400C0000
+#define SOC_RTC_IRAM_HIGH       0x400C2000
+#define SOC_RTC_DRAM_LOW        0x3FF80000
+#define SOC_RTC_DRAM_HIGH       0x3FF82000
+#define SOC_RTC_DATA_LOW        0x50000000
+#define SOC_RTC_DATA_HIGH       0x50002000
+#define SOC_EXTRAM_DATA_LOW     0x3F800000
+#define SOC_EXTRAM_DATA_HIGH    0x3FC00000
 
 //First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
 #define SOC_DIRAM_IRAM_LOW    0x400A0000
@@ -355,6 +346,7 @@
 #define ETS_MMU_IA_INTR_SOURCE                  66/**< interrupt of MMU Invalid Access, LEVEL*/
 #define ETS_MPU_IA_INTR_SOURCE                  67/**< interrupt of MPU Invalid Access, LEVEL*/
 #define ETS_CACHE_IA_INTR_SOURCE                68/**< interrupt of Cache Invalied Access, LEVEL*/
+#define ETS_MAX_INTR_SOURCE                     69/**< total number of interrupt sources*/
 
 //interrupt cpu using table, Please see the core-isa.h
 /*************************************************************************************************************
diff --git a/components/soc/esp32/include/soc/spi_pins.h b/components/soc/esp32/include/soc/spi_pins.h
index eb7af8582..a7887b19e 100644
--- a/components/soc/esp32/include/soc/spi_pins.h
+++ b/components/soc/esp32/include/soc/spi_pins.h
@@ -15,6 +15,9 @@
 #ifndef _SOC_SPI_PINS_H_
 #define _SOC_SPI_PINS_H_
 
+#define SPI_PERIPH_NUM          3
+
+#define SPI_FUNC_NUM            1
 #define SPI_IOMUX_PIN_NUM_MISO  7
 #define SPI_IOMUX_PIN_NUM_MOSI  8
 #define SPI_IOMUX_PIN_NUM_CLK   6
@@ -22,6 +25,7 @@
 #define SPI_IOMUX_PIN_NUM_WP    10
 #define SPI_IOMUX_PIN_NUM_HD    9
 
+#define HSPI_FUNC_NUM           1
 #define HSPI_IOMUX_PIN_NUM_MISO 12
 #define HSPI_IOMUX_PIN_NUM_MOSI 13
 #define HSPI_IOMUX_PIN_NUM_CLK  14
@@ -29,6 +33,7 @@
 #define HSPI_IOMUX_PIN_NUM_WP   2
 #define HSPI_IOMUX_PIN_NUM_HD   4
 
+#define VSPI_FUNC_NUM           1
 #define VSPI_IOMUX_PIN_NUM_MISO 19
 #define VSPI_IOMUX_PIN_NUM_MOSI 23
 #define VSPI_IOMUX_PIN_NUM_CLK  18
@@ -36,4 +41,4 @@
 #define VSPI_IOMUX_PIN_NUM_WP   22
 #define VSPI_IOMUX_PIN_NUM_HD   21
 
-#endif /* _SOC_SPI_PINS_H_ */
\ No newline at end of file
+#endif /* _SOC_SPI_PINS_H_ */
diff --git a/components/soc/esp32/soc_memory_layout.c b/components/soc/esp32/soc_memory_layout.c
index dcae0c472..b3c7cae3f 100644
--- a/components/soc/esp32/soc_memory_layout.c
+++ b/components/soc/esp32/soc_memory_layout.c
@@ -76,7 +76,7 @@ from low to high start address.
 */
 const soc_memory_region_t soc_memory_regions[] = {
 #ifdef CONFIG_ESP32_SPIRAM_SUPPORT
-    { 0x3F800000, 0x400000, 15, 0}, //SPI SRAM, if available
+    { SOC_EXTRAM_DATA_LOW, CONFIG_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available
 #endif
     { 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
     { 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
@@ -167,7 +167,7 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me
 #endif
 
 #ifdef CONFIG_ESP32_SPIRAM_SUPPORT
-SOC_RESERVE_MEMORY_REGION(0x3f800000, 0x3fC00000, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
+SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
 #endif
 
 #endif /* BOOTLOADER_BUILD */
diff --git a/components/soc/esp32/spi_periph.c b/components/soc/esp32/spi_periph.c
index 084777708..8742eaba4 100644
--- a/components/soc/esp32/spi_periph.c
+++ b/components/soc/esp32/spi_periph.c
@@ -40,7 +40,8 @@ const spi_signal_conn_t spi_periph_signal[3] = {
         .irq = ETS_SPI1_INTR_SOURCE,
         .irq_dma = ETS_SPI1_DMA_INTR_SOURCE,
         .module = PERIPH_SPI_MODULE,
-        .hw = &SPI1
+        .hw = &SPI1,
+        .func = SPI_FUNC_NUM
     }, {
         .spiclk_out = HSPICLK_OUT_IDX,
         .spiclk_in = HSPICLK_IN_IDX,
@@ -63,7 +64,8 @@ const spi_signal_conn_t spi_periph_signal[3] = {
         .irq = ETS_SPI2_INTR_SOURCE,
         .irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
         .module = PERIPH_HSPI_MODULE,
-        .hw = &SPI2
+        .hw = &SPI2,
+        .func = HSPI_FUNC_NUM
     }, {
         .spiclk_out = VSPICLK_OUT_IDX,
         .spiclk_in = VSPICLK_IN_IDX,
@@ -86,6 +88,7 @@ const spi_signal_conn_t spi_periph_signal[3] = {
         .irq = ETS_SPI3_INTR_SOURCE,
         .irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
         .module = PERIPH_VSPI_MODULE,
-        .hw = &SPI3
+        .hw = &SPI3,
+        .func = VSPI_FUNC_NUM
     }
-};
\ No newline at end of file
+};
diff --git a/components/soc/esp32s2beta/component.mk b/components/soc/esp32s2beta/component.mk
new file mode 100644
index 000000000..385d55c75
--- /dev/null
+++ b/components/soc/esp32s2beta/component.mk
@@ -0,0 +1 @@
+esp32s2beta/rtc_clk.o: CFLAGS += -fno-jump-tables -fno-tree-switch-conversion
diff --git a/components/soc/esp32s2beta/cpu_util.c b/components/soc/esp32s2beta/cpu_util.c
new file mode 100644
index 000000000..bc052af98
--- /dev/null
+++ b/components/soc/esp32s2beta/cpu_util.c
@@ -0,0 +1,63 @@
+// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "esp_attr.h"
+#include "soc/cpu.h"
+#include "soc/soc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "sdkconfig.h"
+
+void IRAM_ATTR esp_cpu_stall(int cpu_id)
+{
+    if (cpu_id == 1) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
+        SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_APPCPU_C1_S);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
+        SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_APPCPU_C0_S);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
+        SET_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, 0x21<<RTC_CNTL_SW_STALL_PROCPU_C1_S);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
+        SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, 2<<RTC_CNTL_SW_STALL_PROCPU_C0_S);
+    }
+}
+
+void IRAM_ATTR esp_cpu_unstall(int cpu_id)
+{
+    if (cpu_id == 1) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_APPCPU_C1_M);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_APPCPU_C0_M);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_SW_CPU_STALL_REG, RTC_CNTL_SW_STALL_PROCPU_C1_M);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_SW_STALL_PROCPU_C0_M);
+    }
+}
+
+void IRAM_ATTR esp_cpu_reset(int cpu_id)
+{
+    SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
+            cpu_id == 0 ? RTC_CNTL_SW_PROCPU_RST_M : RTC_CNTL_SW_APPCPU_RST_M);
+}
+
+bool IRAM_ATTR esp_cpu_in_ocd_debug_mode()
+{
+#if CONFIG_ESP32_DEBUG_OCDAWARE
+    int dcr;
+    int reg=0x10200C; //DSRSET register
+    asm("rer %0,%1":"=r"(dcr):"r"(reg));
+    return (dcr&0x1);
+#else
+    return false; // Always return false if "OCD aware" is disabled
+#endif
+}
diff --git a/components/soc/esp32s2beta/i2c_apll.h b/components/soc/esp32s2beta/i2c_apll.h
new file mode 100644
index 000000000..935810afa
--- /dev/null
+++ b/components/soc/esp32s2beta/i2c_apll.h
@@ -0,0 +1,136 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file i2c_apll.h
+ * @brief Register definitions for audio PLL (APLL)
+ *
+ * This file lists register fields of APLL, located on an internal configuration
+ * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * rtc_clk_apll_enable function in rtc_clk.c.
+ */
+
+#define I2C_APLL            0X6D
+#define I2C_APLL_HOSTID     3
+
+#define I2C_APLL_IR_CAL_DELAY        0
+#define I2C_APLL_IR_CAL_DELAY_MSB    3
+#define I2C_APLL_IR_CAL_DELAY_LSB    0
+
+#define I2C_APLL_IR_CAL_RSTB        0
+#define I2C_APLL_IR_CAL_RSTB_MSB    4
+#define I2C_APLL_IR_CAL_RSTB_LSB    4
+
+#define I2C_APLL_IR_CAL_START        0
+#define I2C_APLL_IR_CAL_START_MSB    5
+#define I2C_APLL_IR_CAL_START_LSB    5
+
+#define I2C_APLL_IR_CAL_UNSTOP        0
+#define I2C_APLL_IR_CAL_UNSTOP_MSB    6
+#define I2C_APLL_IR_CAL_UNSTOP_LSB    6
+
+#define I2C_APLL_OC_ENB_FCAL        0
+#define I2C_APLL_OC_ENB_FCAL_MSB    7
+#define I2C_APLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_APLL_IR_CAL_EXT_CAP        1
+#define I2C_APLL_IR_CAL_EXT_CAP_MSB    4
+#define I2C_APLL_IR_CAL_EXT_CAP_LSB    0
+
+#define I2C_APLL_IR_CAL_ENX_CAP        1
+#define I2C_APLL_IR_CAL_ENX_CAP_MSB    5
+#define I2C_APLL_IR_CAL_ENX_CAP_LSB    5
+
+#define I2C_APLL_OC_LBW        1
+#define I2C_APLL_OC_LBW_MSB    6
+#define I2C_APLL_OC_LBW_LSB    6
+
+#define I2C_APLL_IR_CAL_CK_DIV        2
+#define I2C_APLL_IR_CAL_CK_DIV_MSB    3
+#define I2C_APLL_IR_CAL_CK_DIV_LSB    0
+
+#define I2C_APLL_OC_DCHGP        2
+#define I2C_APLL_OC_DCHGP_MSB    6
+#define I2C_APLL_OC_DCHGP_LSB    4
+
+#define I2C_APLL_OC_ENB_VCON        2
+#define I2C_APLL_OC_ENB_VCON_MSB    7
+#define I2C_APLL_OC_ENB_VCON_LSB    7
+
+#define I2C_APLL_OR_CAL_CAP        3
+#define I2C_APLL_OR_CAL_CAP_MSB    4
+#define I2C_APLL_OR_CAL_CAP_LSB    0
+
+#define I2C_APLL_OR_CAL_UDF        3
+#define I2C_APLL_OR_CAL_UDF_MSB    5
+#define I2C_APLL_OR_CAL_UDF_LSB    5
+
+#define I2C_APLL_OR_CAL_OVF        3
+#define I2C_APLL_OR_CAL_OVF_MSB    6
+#define I2C_APLL_OR_CAL_OVF_LSB    6
+
+#define I2C_APLL_OR_CAL_END        3
+#define I2C_APLL_OR_CAL_END_MSB    7
+#define I2C_APLL_OR_CAL_END_LSB    7
+
+#define I2C_APLL_OR_OUTPUT_DIV        4
+#define I2C_APLL_OR_OUTPUT_DIV_MSB    4
+#define I2C_APLL_OR_OUTPUT_DIV_LSB    0
+
+#define I2C_APLL_OC_TSCHGP        4
+#define I2C_APLL_OC_TSCHGP_MSB    6
+#define I2C_APLL_OC_TSCHGP_LSB    6
+
+#define I2C_APLL_EN_FAST_CAL        4
+#define I2C_APLL_EN_FAST_CAL_MSB    7
+#define I2C_APLL_EN_FAST_CAL_LSB    7
+
+#define I2C_APLL_OC_DHREF_SEL        5
+#define I2C_APLL_OC_DHREF_SEL_MSB    1
+#define I2C_APLL_OC_DHREF_SEL_LSB    0
+
+#define I2C_APLL_OC_DLREF_SEL        5
+#define I2C_APLL_OC_DLREF_SEL_MSB    3
+#define I2C_APLL_OC_DLREF_SEL_LSB    2
+
+#define I2C_APLL_SDM_DITHER        5
+#define I2C_APLL_SDM_DITHER_MSB    4
+#define I2C_APLL_SDM_DITHER_LSB    4
+
+#define I2C_APLL_SDM_STOP        5
+#define I2C_APLL_SDM_STOP_MSB    5
+#define I2C_APLL_SDM_STOP_LSB    5
+
+#define I2C_APLL_SDM_RSTB        5
+#define I2C_APLL_SDM_RSTB_MSB    6
+#define I2C_APLL_SDM_RSTB_LSB    6
+
+#define I2C_APLL_OC_DVDD        6
+#define I2C_APLL_OC_DVDD_MSB    4
+#define I2C_APLL_OC_DVDD_LSB    0
+
+#define I2C_APLL_DSDM2        7
+#define I2C_APLL_DSDM2_MSB    5
+#define I2C_APLL_DSDM2_LSB    0
+
+#define I2C_APLL_DSDM1        8
+#define I2C_APLL_DSDM1_MSB    7
+#define I2C_APLL_DSDM1_LSB    0
+
+#define I2C_APLL_DSDM0        9
+#define I2C_APLL_DSDM0_MSB    7
+#define I2C_APLL_DSDM0_LSB    0
+
diff --git a/components/soc/esp32s2beta/i2c_bbpll.h b/components/soc/esp32s2beta/i2c_bbpll.h
new file mode 100644
index 000000000..1f56a5f40
--- /dev/null
+++ b/components/soc/esp32s2beta/i2c_bbpll.h
@@ -0,0 +1,184 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file i2c_apll.h
+ * @brief Register definitions for digital PLL (BBPLL)
+ *
+ * This file lists register fields of BBPLL, located on an internal configuration
+ * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
+ * rtc_clk_cpu_freq_set function in rtc_clk.c.
+ */
+
+#define I2C_BBPLL           0x66
+#define I2C_BBPLL_HOSTID    1
+
+#define I2C_BBPLL_IR_CAL_DELAY        0
+#define I2C_BBPLL_IR_CAL_DELAY_MSB    3
+#define I2C_BBPLL_IR_CAL_DELAY_LSB    0
+
+#define I2C_BBPLL_IR_CAL_CK_DIV        0
+#define I2C_BBPLL_IR_CAL_CK_DIV_MSB    7
+#define I2C_BBPLL_IR_CAL_CK_DIV_LSB    4
+
+#define I2C_BBPLL_IR_CAL_EXT_CAP        1
+#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB    3
+#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB    0
+
+#define I2C_BBPLL_IR_CAL_ENX_CAP        1
+#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB    4
+#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB    4
+
+#define I2C_BBPLL_IR_CAL_RSTB        1
+#define I2C_BBPLL_IR_CAL_RSTB_MSB    5
+#define I2C_BBPLL_IR_CAL_RSTB_LSB    5
+
+#define I2C_BBPLL_IR_CAL_START        1
+#define I2C_BBPLL_IR_CAL_START_MSB    6
+#define I2C_BBPLL_IR_CAL_START_LSB    6
+
+#define I2C_BBPLL_IR_CAL_UNSTOP        1
+#define I2C_BBPLL_IR_CAL_UNSTOP_MSB    7
+#define I2C_BBPLL_IR_CAL_UNSTOP_LSB    7
+
+#define I2C_BBPLL_OC_REF_DIV        2
+#define I2C_BBPLL_OC_REF_DIV_MSB    3
+#define I2C_BBPLL_OC_REF_DIV_LSB    0
+
+#define I2C_BBPLL_OC_DCHGP        2
+#define I2C_BBPLL_OC_DCHGP_MSB    6
+#define I2C_BBPLL_OC_DCHGP_LSB    4
+
+#define I2C_BBPLL_OC_ENB_FCAL        2
+#define I2C_BBPLL_OC_ENB_FCAL_MSB    7
+#define I2C_BBPLL_OC_ENB_FCAL_LSB    7
+
+#define I2C_BBPLL_OC_DIV_7_0        3
+#define I2C_BBPLL_OC_DIV_7_0_MSB    7
+#define I2C_BBPLL_OC_DIV_7_0_LSB    0
+
+#define I2C_BBPLL_RSTB_DIV_ADC        4
+#define I2C_BBPLL_RSTB_DIV_ADC_MSB    0
+#define I2C_BBPLL_RSTB_DIV_ADC_LSB    0
+
+#define I2C_BBPLL_MODE_HF        4
+#define I2C_BBPLL_MODE_HF_MSB    1
+#define I2C_BBPLL_MODE_HF_LSB    1
+
+#define I2C_BBPLL_DIV_ADC        4
+#define I2C_BBPLL_DIV_ADC_MSB    3
+#define I2C_BBPLL_DIV_ADC_LSB    2
+
+#define I2C_BBPLL_DIV_DAC        4
+#define I2C_BBPLL_DIV_DAC_MSB    4
+#define I2C_BBPLL_DIV_DAC_LSB    4
+
+#define I2C_BBPLL_DIV_CPU        4
+#define I2C_BBPLL_DIV_CPU_MSB    5
+#define I2C_BBPLL_DIV_CPU_LSB    5
+
+#define I2C_BBPLL_OC_ENB_VCON        4
+#define I2C_BBPLL_OC_ENB_VCON_MSB    6
+#define I2C_BBPLL_OC_ENB_VCON_LSB    6
+
+#define I2C_BBPLL_OC_TSCHGP        4
+#define I2C_BBPLL_OC_TSCHGP_MSB    7
+#define I2C_BBPLL_OC_TSCHGP_LSB    7
+
+#define I2C_BBPLL_OC_DR1        5
+#define I2C_BBPLL_OC_DR1_MSB    2
+#define I2C_BBPLL_OC_DR1_LSB    0
+
+#define I2C_BBPLL_OC_DR3        5
+#define I2C_BBPLL_OC_DR3_MSB    6
+#define I2C_BBPLL_OC_DR3_LSB    4
+
+#define I2C_BBPLL_EN_USB        5
+#define I2C_BBPLL_EN_USB_MSB    7
+#define I2C_BBPLL_EN_USB_LSB    7
+
+#define I2C_BBPLL_OC_DCUR        6
+#define I2C_BBPLL_OC_DCUR_MSB    2
+#define I2C_BBPLL_OC_DCUR_LSB    0
+
+#define I2C_BBPLL_INC_CUR        6
+#define I2C_BBPLL_INC_CUR_MSB    3
+#define I2C_BBPLL_INC_CUR_LSB    3
+
+#define I2C_BBPLL_OC_DHREF_SEL        6
+#define I2C_BBPLL_OC_DHREF_SEL_MSB    5
+#define I2C_BBPLL_OC_DHREF_SEL_LSB    4
+
+#define I2C_BBPLL_OC_DLREF_SEL        6
+#define I2C_BBPLL_OC_DLREF_SEL_MSB    7
+#define I2C_BBPLL_OC_DLREF_SEL_LSB    6
+
+#define I2C_BBPLL_OR_CAL_CAP        8
+#define I2C_BBPLL_OR_CAL_CAP_MSB    3
+#define I2C_BBPLL_OR_CAL_CAP_LSB    0
+
+#define I2C_BBPLL_OR_CAL_UDF        8
+#define I2C_BBPLL_OR_CAL_UDF_MSB    4
+#define I2C_BBPLL_OR_CAL_UDF_LSB    4
+
+#define I2C_BBPLL_OR_CAL_OVF        8
+#define I2C_BBPLL_OR_CAL_OVF_MSB    5
+#define I2C_BBPLL_OR_CAL_OVF_LSB    5
+
+#define I2C_BBPLL_OR_CAL_END        8
+#define I2C_BBPLL_OR_CAL_END_MSB    6
+#define I2C_BBPLL_OR_CAL_END_LSB    6
+
+#define I2C_BBPLL_OR_LOCK        8
+#define I2C_BBPLL_OR_LOCK_MSB    7
+#define I2C_BBPLL_OR_LOCK_LSB    7
+
+#define I2C_BBPLL_BBADC_DELAY1        9
+#define I2C_BBPLL_BBADC_DELAY1_MSB    1
+#define I2C_BBPLL_BBADC_DELAY1_LSB    0
+
+#define I2C_BBPLL_BBADC_DELAY2        9
+#define I2C_BBPLL_BBADC_DELAY2_MSB    3
+#define I2C_BBPLL_BBADC_DELAY2_LSB    2
+
+#define I2C_BBPLL_BBADC_DVDD        9
+#define I2C_BBPLL_BBADC_DVDD_MSB    5
+#define I2C_BBPLL_BBADC_DVDD_LSB    4
+
+#define I2C_BBPLL_BBADC_DREF        9
+#define I2C_BBPLL_BBADC_DREF_MSB    7
+#define I2C_BBPLL_BBADC_DREF_LSB    6
+
+#define I2C_BBPLL_BBADC_DCUR        10
+#define I2C_BBPLL_BBADC_DCUR_MSB    1
+#define I2C_BBPLL_BBADC_DCUR_LSB    0
+
+#define I2C_BBPLL_BBADC_INPUT_SHORT        10
+#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB    2
+#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB    2
+
+#define I2C_BBPLL_ENT_PLL        10
+#define I2C_BBPLL_ENT_PLL_MSB    3
+#define I2C_BBPLL_ENT_PLL_LSB    3
+
+#define I2C_BBPLL_DTEST        10
+#define I2C_BBPLL_DTEST_MSB    5
+#define I2C_BBPLL_DTEST_LSB    4
+
+#define I2C_BBPLL_ENT_ADC        10
+#define I2C_BBPLL_ENT_ADC_MSB    7
+#define I2C_BBPLL_ENT_ADC_LSB    6
+
diff --git a/components/soc/esp32s2beta/i2c_rtc_clk.h b/components/soc/esp32s2beta/i2c_rtc_clk.h
new file mode 100644
index 000000000..a26b52100
--- /dev/null
+++ b/components/soc/esp32s2beta/i2c_rtc_clk.h
@@ -0,0 +1,48 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "i2c_apll.h"
+#include "i2c_bbpll.h"
+
+/* Analog function control register */
+#define ANA_CONFIG_REG  0x6000E044
+#define ANA_CONFIG_S    (8)
+#define ANA_CONFIG_M    (0x3FF)
+/* Clear to enable APLL */
+#define I2C_APLL_M      (BIT(14))
+/* Clear to enable BBPLL */
+#define I2C_BBPLL_M     (BIT(17))
+
+/* ROM functions which read/write internal control bus */
+uint8_t rom_i2c_readReg(uint8_t block, uint8_t host_id, uint8_t reg_add);
+uint8_t rom_i2c_readReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb);
+void rom_i2c_writeReg(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t data);
+void rom_i2c_writeReg_Mask(uint8_t block, uint8_t host_id, uint8_t reg_add, uint8_t msb, uint8_t lsb, uint8_t data);
+
+/* Convenience macros for the above functions, these use register definitions
+ * from i2c_apll.h/i2c_bbpll.h header files.
+ */
+#define I2C_WRITEREG_MASK_RTC(block, reg_add, indata) \
+      rom_i2c_writeReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB,  indata)
+
+#define I2C_READREG_MASK_RTC(block, reg_add) \
+      rom_i2c_readReg_Mask(block, block##_HOSTID,  reg_add,  reg_add##_MSB,  reg_add##_LSB)
+
+#define I2C_WRITEREG_RTC(block, reg_add, indata) \
+      rom_i2c_writeReg(block, block##_HOSTID,  reg_add, indata)
+
+#define I2C_READREG_RTC(block, reg_add) \
+      rom_i2c_readReg(block, block##_HOSTID,  reg_add)
diff --git a/components/soc/esp32s2beta/include/soc/adc_channel.h b/components/soc/esp32s2beta/include/soc/adc_channel.h
new file mode 100644
index 000000000..a03303f0f
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/adc_channel.h
@@ -0,0 +1,78 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_ADC_CHANNEL_H
+#define _SOC_ADC_CHANNEL_H
+
+#define ADC1_GPIO1_CHANNEL     ADC1_CHANNEL_0
+#define ADC1_CHANNEL_0_GPIO_NUM 1
+
+#define ADC1_GPIO2_CHANNEL     ADC1_CHANNEL_1
+#define ADC1_CHANNEL_1_GPIO_NUM 2
+
+#define ADC1_GPIO3_CHANNEL     ADC1_CHANNEL_2
+#define ADC1_CHANNEL_2_GPIO_NUM 3
+
+#define ADC1_GPIO4_CHANNEL     ADC1_CHANNEL_3
+#define ADC1_CHANNEL_3_GPIO_NUM 4
+
+#define ADC1_GPIO5_CHANNEL     ADC1_CHANNEL_4
+#define ADC1_CHANNEL_4_GPIO_NUM 5
+
+#define ADC1_GPIO6_CHANNEL     ADC1_CHANNEL_5
+#define ADC1_CHANNEL_5_GPIO_NUM 6
+
+#define ADC1_GPIO7_CHANNEL     ADC1_CHANNEL_6
+#define ADC1_CHANNEL_6_GPIO_NUM 7
+
+#define ADC1_GPIO8_CHANNEL     ADC1_CHANNEL_7
+#define ADC1_CHANNEL_7_GPIO_NUM 8
+
+#define ADC1_GPIO9_CHANNEL     ADC1_CHANNEL_8
+#define ADC1_CHANNEL_8_GPIO_NUM 9
+
+#define ADC1_GPIO10_CHANNEL     ADC1_CHANNEL_9
+#define ADC1_CHANNEL_9_GPIO_NUM 10
+
+#define ADC2_GPIO11_CHANNEL      ADC2_CHANNEL_0
+#define ADC2_CHANNEL_0_GPIO_NUM 11
+
+#define ADC2_GPIO12_CHANNEL      ADC2_CHANNEL_1
+#define ADC2_CHANNEL_1_GPIO_NUM 12
+
+#define ADC2_GPIO13_CHANNEL      ADC2_CHANNEL_2
+#define ADC2_CHANNEL_2_GPIO_NUM 13
+
+#define ADC2_GPIO14_CHANNEL     ADC2_CHANNEL_3
+#define ADC2_CHANNEL_3_GPIO_NUM 14
+
+#define ADC2_GPIO15_CHANNEL     ADC2_CHANNEL_4
+#define ADC2_CHANNEL_4_GPIO_NUM 15
+
+#define ADC2_GPIO16_CHANNEL     ADC2_CHANNEL_5
+#define ADC2_CHANNEL_5_GPIO_NUM 16
+
+#define ADC2_GPIO17_CHANNEL     ADC2_CHANNEL_6
+#define ADC2_CHANNEL_6_GPIO_NUM 17
+
+#define ADC2_GPIO18_CHANNEL     ADC2_CHANNEL_7
+#define ADC2_CHANNEL_7_GPIO_NUM 18
+
+#define ADC2_GPIO19_CHANNEL     ADC2_CHANNEL_8
+#define ADC2_CHANNEL_8_GPIO_NUM 19
+
+#define ADC2_GPIO20_CHANNEL     ADC2_CHANNEL_9
+#define ADC2_CHANNEL_9_GPIO_NUM 20
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h b/components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h
new file mode 100644
index 000000000..eefcf3b02
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/apb_ctrl_reg.h
@@ -0,0 +1,841 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_CTRL_REG_H_
+#define _SOC_APB_CTRL_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define APB_CTRL_SYSCLK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x000)
+/* APB_CTRL_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: */
+#define APB_CTRL_SOC_CLK_SEL  0x00000003
+#define APB_CTRL_SOC_CLK_SEL_M  ((APB_CTRL_SOC_CLK_SEL_V)<<(APB_CTRL_SOC_CLK_SEL_S))
+#define APB_CTRL_SOC_CLK_SEL_V  0x3
+#define APB_CTRL_SOC_CLK_SEL_S  14
+#define APB_CTRL_SOC_CLK_SEL_XTL    0
+#define APB_CTRL_SOC_CLK_SEL_PLL    1
+#define APB_CTRL_SOC_CLK_SEL_8M     2
+#define APB_CTRL_SOC_CLK_SEL_APLL   3
+
+/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_RST_TICK_CNT  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_M  (BIT(12))
+#define APB_CTRL_RST_TICK_CNT_V  0x1
+#define APB_CTRL_RST_TICK_CNT_S  12
+/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_EN  (BIT(11))
+#define APB_CTRL_CLK_EN_M  (BIT(11))
+#define APB_CTRL_CLK_EN_V  0x1
+#define APB_CTRL_CLK_EN_S  11
+/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_CLK_320M_EN  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_M  (BIT(10))
+#define APB_CTRL_CLK_320M_EN_V  0x1
+#define APB_CTRL_CLK_320M_EN_S  10
+/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define APB_CTRL_PRE_DIV_CNT  0x000003FF
+#define APB_CTRL_PRE_DIV_CNT_M  ((APB_CTRL_PRE_DIV_CNT_V)<<(APB_CTRL_PRE_DIV_CNT_S))
+#define APB_CTRL_PRE_DIV_CNT_V  0x3FF
+#define APB_CTRL_PRE_DIV_CNT_S  0
+
+#define APB_CTRL_TICK_CONF_REG          (DR_REG_APB_CTRL_BASE + 0x004)
+/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: */
+#define APB_CTRL_TICK_ENABLE  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_M  (BIT(16))
+#define APB_CTRL_TICK_ENABLE_V  0x1
+#define APB_CTRL_TICK_ENABLE_S  16
+/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: */
+#define APB_CTRL_CK8M_TICK_NUM  0x000000FF
+#define APB_CTRL_CK8M_TICK_NUM_M  ((APB_CTRL_CK8M_TICK_NUM_V)<<(APB_CTRL_CK8M_TICK_NUM_S))
+#define APB_CTRL_CK8M_TICK_NUM_V  0xFF
+#define APB_CTRL_CK8M_TICK_NUM_S  8
+/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: */
+#define APB_CTRL_XTAL_TICK_NUM  0x000000FF
+#define APB_CTRL_XTAL_TICK_NUM_M  ((APB_CTRL_XTAL_TICK_NUM_V)<<(APB_CTRL_XTAL_TICK_NUM_S))
+#define APB_CTRL_XTAL_TICK_NUM_V  0xFF
+#define APB_CTRL_XTAL_TICK_NUM_S  0
+
+#define APB_CTRL_SARADC_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x008)
+/* APB_CTRL_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: force option to xpd sar blocks*/
+#define APB_CTRL_SARADC_XPD_SAR_FORCE  0x00000003
+#define APB_CTRL_SARADC_XPD_SAR_FORCE_M  ((APB_CTRL_SARADC_XPD_SAR_FORCE_V)<<(APB_CTRL_SARADC_XPD_SAR_FORCE_S))
+#define APB_CTRL_SARADC_XPD_SAR_FORCE_V  0x3
+#define APB_CTRL_SARADC_XPD_SAR_FORCE_S  27
+/* APB_CTRL_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: I2S input data is from SAR ADC (for DMA)  0: I2S input data
+ is from GPIO matrix*/
+#define APB_CTRL_SARADC_DATA_TO_I2S  (BIT(26))
+#define APB_CTRL_SARADC_DATA_TO_I2S_M  (BIT(26))
+#define APB_CTRL_SARADC_DATA_TO_I2S_V  0x1
+#define APB_CTRL_SARADC_DATA_TO_I2S_S  26
+/* APB_CTRL_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
+  in this case the resolution should not be larger than 11 bits.*/
+#define APB_CTRL_SARADC_DATA_SAR_SEL  (BIT(25))
+#define APB_CTRL_SARADC_DATA_SAR_SEL_M  (BIT(25))
+#define APB_CTRL_SARADC_DATA_SAR_SEL_V  0x1
+#define APB_CTRL_SARADC_DATA_SAR_SEL_S  25
+/* APB_CTRL_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR  (BIT(24))
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_V  0x1
+#define APB_CTRL_SARADC_SAR2_PATT_P_CLEAR_S  24
+/* APB_CTRL_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR  (BIT(23))
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_V  0x1
+#define APB_CTRL_SARADC_SAR1_PATT_P_CLEAR_S  23
+/* APB_CTRL_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define APB_CTRL_SARADC_SAR2_PATT_LEN  0x0000000F
+#define APB_CTRL_SARADC_SAR2_PATT_LEN_M  ((APB_CTRL_SARADC_SAR2_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR2_PATT_LEN_S))
+#define APB_CTRL_SARADC_SAR2_PATT_LEN_V  0xF
+#define APB_CTRL_SARADC_SAR2_PATT_LEN_S  19
+/* APB_CTRL_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define APB_CTRL_SARADC_SAR1_PATT_LEN  0x0000000F
+#define APB_CTRL_SARADC_SAR1_PATT_LEN_M  ((APB_CTRL_SARADC_SAR1_PATT_LEN_V)<<(APB_CTRL_SARADC_SAR1_PATT_LEN_S))
+#define APB_CTRL_SARADC_SAR1_PATT_LEN_V  0xF
+#define APB_CTRL_SARADC_SAR1_PATT_LEN_S  15
+/* APB_CTRL_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
+/*description: SAR clock divider*/
+#define APB_CTRL_SARADC_SAR_CLK_DIV  0x000000FF
+#define APB_CTRL_SARADC_SAR_CLK_DIV_M  ((APB_CTRL_SARADC_SAR_CLK_DIV_V)<<(APB_CTRL_SARADC_SAR_CLK_DIV_S))
+#define APB_CTRL_SARADC_SAR_CLK_DIV_V  0xFF
+#define APB_CTRL_SARADC_SAR_CLK_DIV_S  7
+/* APB_CTRL_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_SARADC_SAR_CLK_GATED  (BIT(6))
+#define APB_CTRL_SARADC_SAR_CLK_GATED_M  (BIT(6))
+#define APB_CTRL_SARADC_SAR_CLK_GATED_V  0x1
+#define APB_CTRL_SARADC_SAR_CLK_GATED_S  6
+/* APB_CTRL_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: 0: SAR1  1: SAR2  only work for single SAR mode*/
+#define APB_CTRL_SARADC_SAR_SEL  (BIT(5))
+#define APB_CTRL_SARADC_SAR_SEL_M  (BIT(5))
+#define APB_CTRL_SARADC_SAR_SEL_V  0x1
+#define APB_CTRL_SARADC_SAR_SEL_S  5
+/* APB_CTRL_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
+/*description: 0: single mode  1: double mode  2: alternate mode*/
+#define APB_CTRL_SARADC_WORK_MODE  0x00000003
+#define APB_CTRL_SARADC_WORK_MODE_M  ((APB_CTRL_SARADC_WORK_MODE_V)<<(APB_CTRL_SARADC_WORK_MODE_S))
+#define APB_CTRL_SARADC_WORK_MODE_V  0x3
+#define APB_CTRL_SARADC_WORK_MODE_S  3
+/* APB_CTRL_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_START  (BIT(1))
+#define APB_CTRL_SARADC_START_M  (BIT(1))
+#define APB_CTRL_SARADC_START_V  0x1
+#define APB_CTRL_SARADC_START_S  1
+/* APB_CTRL_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_START_FORCE  (BIT(0))
+#define APB_CTRL_SARADC_START_FORCE_M  (BIT(0))
+#define APB_CTRL_SARADC_START_FORCE_V  0x1
+#define APB_CTRL_SARADC_START_FORCE_S  0
+
+#define APB_CTRL_SARADC_CTRL2_REG          (DR_REG_APB_CTRL_BASE + 0x00C)
+/* APB_CTRL_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: to enable saradc timer trigger*/
+#define APB_CTRL_SARADC_TIMER_EN  (BIT(20))
+#define APB_CTRL_SARADC_TIMER_EN_M  (BIT(20))
+#define APB_CTRL_SARADC_TIMER_EN_V  0x1
+#define APB_CTRL_SARADC_TIMER_EN_S  20
+/* APB_CTRL_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */
+/*description: to set saradc timer target*/
+#define APB_CTRL_SARADC_TIMER_TARGET  0x000000FF
+#define APB_CTRL_SARADC_TIMER_TARGET_M  ((APB_CTRL_SARADC_TIMER_TARGET_V)<<(APB_CTRL_SARADC_TIMER_TARGET_S))
+#define APB_CTRL_SARADC_TIMER_TARGET_V  0xFF
+#define APB_CTRL_SARADC_TIMER_TARGET_S  12
+/* APB_CTRL_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: 1: select saradc timer 0: i2s_ws trigger*/
+#define APB_CTRL_SARADC_TIMER_SEL  (BIT(11))
+#define APB_CTRL_SARADC_TIMER_SEL_M  (BIT(11))
+#define APB_CTRL_SARADC_TIMER_SEL_V  0x1
+#define APB_CTRL_SARADC_TIMER_SEL_S  11
+/* APB_CTRL_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+#define APB_CTRL_SARADC_SAR2_INV  (BIT(10))
+#define APB_CTRL_SARADC_SAR2_INV_M  (BIT(10))
+#define APB_CTRL_SARADC_SAR2_INV_V  0x1
+#define APB_CTRL_SARADC_SAR2_INV_S  10
+/* APB_CTRL_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+#define APB_CTRL_SARADC_SAR1_INV  (BIT(9))
+#define APB_CTRL_SARADC_SAR1_INV_M  (BIT(9))
+#define APB_CTRL_SARADC_SAR1_INV_V  0x1
+#define APB_CTRL_SARADC_SAR1_INV_S  9
+/* APB_CTRL_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
+/*description: max conversion number*/
+#define APB_CTRL_SARADC_MAX_MEAS_NUM  0x000000FF
+#define APB_CTRL_SARADC_MAX_MEAS_NUM_M  ((APB_CTRL_SARADC_MAX_MEAS_NUM_V)<<(APB_CTRL_SARADC_MAX_MEAS_NUM_S))
+#define APB_CTRL_SARADC_MAX_MEAS_NUM_V  0xFF
+#define APB_CTRL_SARADC_MAX_MEAS_NUM_S  1
+/* APB_CTRL_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT  (BIT(0))
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_V  0x1
+#define APB_CTRL_SARADC_MEAS_NUM_LIMIT_S  0
+
+#define APB_CTRL_SARADC_FSM_REG          (DR_REG_APB_CTRL_BASE + 0x010)
+/* APB_CTRL_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
+/*description: sample cycles*/
+#define APB_CTRL_SARADC_SAMPLE_CYCLE  0x000000FF
+#define APB_CTRL_SARADC_SAMPLE_CYCLE_M  ((APB_CTRL_SARADC_SAMPLE_CYCLE_V)<<(APB_CTRL_SARADC_SAMPLE_CYCLE_S))
+#define APB_CTRL_SARADC_SAMPLE_CYCLE_V  0xFF
+#define APB_CTRL_SARADC_SAMPLE_CYCLE_S  24
+/* APB_CTRL_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
+/*description: sample number*/
+#define APB_CTRL_SARADC_SAMPLE_NUM  0x000000FF
+#define APB_CTRL_SARADC_SAMPLE_NUM_M  ((APB_CTRL_SARADC_SAMPLE_NUM_V)<<(APB_CTRL_SARADC_SAMPLE_NUM_S))
+#define APB_CTRL_SARADC_SAMPLE_NUM_V  0xFF
+#define APB_CTRL_SARADC_SAMPLE_NUM_S  16
+
+#define APB_CTRL_SARADC_FSM_WAIT_REG          (DR_REG_APB_CTRL_BASE + 0x014)
+/* APB_CTRL_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: */
+#define APB_CTRL_SARADC_STANDBY_WAIT  0x000000FF
+#define APB_CTRL_SARADC_STANDBY_WAIT_M  ((APB_CTRL_SARADC_STANDBY_WAIT_V)<<(APB_CTRL_SARADC_STANDBY_WAIT_S))
+#define APB_CTRL_SARADC_STANDBY_WAIT_V  0xFF
+#define APB_CTRL_SARADC_STANDBY_WAIT_S  16
+/* APB_CTRL_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: */
+#define APB_CTRL_SARADC_RSTB_WAIT  0x000000FF
+#define APB_CTRL_SARADC_RSTB_WAIT_M  ((APB_CTRL_SARADC_RSTB_WAIT_V)<<(APB_CTRL_SARADC_RSTB_WAIT_S))
+#define APB_CTRL_SARADC_RSTB_WAIT_V  0xFF
+#define APB_CTRL_SARADC_RSTB_WAIT_S  8
+/* APB_CTRL_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: */
+#define APB_CTRL_SARADC_XPD_WAIT  0x000000FF
+#define APB_CTRL_SARADC_XPD_WAIT_M  ((APB_CTRL_SARADC_XPD_WAIT_V)<<(APB_CTRL_SARADC_XPD_WAIT_S))
+#define APB_CTRL_SARADC_XPD_WAIT_V  0xFF
+#define APB_CTRL_SARADC_XPD_WAIT_S  0
+
+#define APB_CTRL_SARADC_SAR1_STATUS_REG          (DR_REG_APB_CTRL_BASE + 0x018)
+/* APB_CTRL_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_SAR1_STATUS  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_STATUS_M  ((APB_CTRL_SARADC_SAR1_STATUS_V)<<(APB_CTRL_SARADC_SAR1_STATUS_S))
+#define APB_CTRL_SARADC_SAR1_STATUS_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_STATUS_S  0
+
+#define APB_CTRL_SARADC_SAR2_STATUS_REG          (DR_REG_APB_CTRL_BASE + 0x01C)
+/* APB_CTRL_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define APB_CTRL_SARADC_SAR2_STATUS  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_STATUS_M  ((APB_CTRL_SARADC_SAR2_STATUS_V)<<(APB_CTRL_SARADC_SAR2_STATUS_S))
+#define APB_CTRL_SARADC_SAR2_STATUS_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_STATUS_S  0
+
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_APB_CTRL_BASE + 0x020)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB1_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB1_S  0
+
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_APB_CTRL_BASE + 0x024)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB2_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB2_S  0
+
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_APB_CTRL_BASE + 0x028)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB3_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB3_S  0
+
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_APB_CTRL_BASE + 0x02C)
+/* APB_CTRL_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4_M  ((APB_CTRL_SARADC_SAR1_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR1_PATT_TAB4_S))
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR1_PATT_TAB4_S  0
+
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_APB_CTRL_BASE + 0x030)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB1_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB1_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB1_S  0
+
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_APB_CTRL_BASE + 0x034)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB2_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB2_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB2_S  0
+
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_APB_CTRL_BASE + 0x038)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB3_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB3_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB3_S  0
+
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_APB_CTRL_BASE + 0x03C)
+/* APB_CTRL_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4_M  ((APB_CTRL_SARADC_SAR2_PATT_TAB4_V)<<(APB_CTRL_SARADC_SAR2_PATT_TAB4_S))
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4_V  0xFFFFFFFF
+#define APB_CTRL_SARADC_SAR2_PATT_TAB4_S  0
+
+#define APB_CTRL_ADC_ARB_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x040)
+/* APB_CTRL_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: adc2 arbiter uses fixed priority*/
+#define APB_CTRL_ADC_ARB_FIX_PRIORITY  (BIT(12))
+#define APB_CTRL_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
+#define APB_CTRL_ADC_ARB_FIX_PRIORITY_V  0x1
+#define APB_CTRL_ADC_ARB_FIX_PRIORITY_S  12
+/* APB_CTRL_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
+/*description: Set adc2 arbiter wifi priority*/
+#define APB_CTRL_ADC_ARB_WIFI_PRIORITY  0x00000003
+#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_M  ((APB_CTRL_ADC_ARB_WIFI_PRIORITY_V)<<(APB_CTRL_ADC_ARB_WIFI_PRIORITY_S))
+#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_V  0x3
+#define APB_CTRL_ADC_ARB_WIFI_PRIORITY_S  10
+/* APB_CTRL_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
+/*description: Set adc2 arbiter rtc priority*/
+#define APB_CTRL_ADC_ARB_RTC_PRIORITY  0x00000003
+#define APB_CTRL_ADC_ARB_RTC_PRIORITY_M  ((APB_CTRL_ADC_ARB_RTC_PRIORITY_V)<<(APB_CTRL_ADC_ARB_RTC_PRIORITY_S))
+#define APB_CTRL_ADC_ARB_RTC_PRIORITY_V  0x3
+#define APB_CTRL_ADC_ARB_RTC_PRIORITY_S  8
+/* APB_CTRL_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Set adc2 arbiter apb priority*/
+#define APB_CTRL_ADC_ARB_APB_PRIORITY  0x00000003
+#define APB_CTRL_ADC_ARB_APB_PRIORITY_M  ((APB_CTRL_ADC_ARB_APB_PRIORITY_V)<<(APB_CTRL_ADC_ARB_APB_PRIORITY_S))
+#define APB_CTRL_ADC_ARB_APB_PRIORITY_V  0x3
+#define APB_CTRL_ADC_ARB_APB_PRIORITY_S  6
+/* APB_CTRL_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: adc2 arbiter force grant*/
+#define APB_CTRL_ADC_ARB_GRANT_FORCE  (BIT(5))
+#define APB_CTRL_ADC_ARB_GRANT_FORCE_M  (BIT(5))
+#define APB_CTRL_ADC_ARB_GRANT_FORCE_V  0x1
+#define APB_CTRL_ADC_ARB_GRANT_FORCE_S  5
+/* APB_CTRL_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable wifi controller*/
+#define APB_CTRL_ADC_ARB_WIFI_FORCE  (BIT(4))
+#define APB_CTRL_ADC_ARB_WIFI_FORCE_M  (BIT(4))
+#define APB_CTRL_ADC_ARB_WIFI_FORCE_V  0x1
+#define APB_CTRL_ADC_ARB_WIFI_FORCE_S  4
+/* APB_CTRL_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable rtc controller*/
+#define APB_CTRL_ADC_ARB_RTC_FORCE  (BIT(3))
+#define APB_CTRL_ADC_ARB_RTC_FORCE_M  (BIT(3))
+#define APB_CTRL_ADC_ARB_RTC_FORCE_V  0x1
+#define APB_CTRL_ADC_ARB_RTC_FORCE_S  3
+/* APB_CTRL_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable apb controller*/
+#define APB_CTRL_ADC_ARB_APB_FORCE  (BIT(2))
+#define APB_CTRL_ADC_ARB_APB_FORCE_M  (BIT(2))
+#define APB_CTRL_ADC_ARB_APB_FORCE_V  0x1
+#define APB_CTRL_ADC_ARB_APB_FORCE_S  2
+
+#define APB_CTRL_CLK_OUT_EN_REG          (DR_REG_APB_CTRL_BASE + 0x044)
+/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_XTAL_OEN  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_M  (BIT(10))
+#define APB_CTRL_CLK_XTAL_OEN_V  0x1
+#define APB_CTRL_CLK_XTAL_OEN_S  10
+/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK40X_BB_OEN  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_M  (BIT(9))
+#define APB_CTRL_CLK40X_BB_OEN_V  0x1
+#define APB_CTRL_CLK40X_BB_OEN_S  9
+/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_DAC_CPU_OEN  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define APB_CTRL_CLK_DAC_CPU_OEN_V  0x1
+#define APB_CTRL_CLK_DAC_CPU_OEN_S  8
+/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_ADC_INF_OEN  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_M  (BIT(7))
+#define APB_CTRL_CLK_ADC_INF_OEN_V  0x1
+#define APB_CTRL_CLK_ADC_INF_OEN_S  7
+/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_320M_OEN  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_M  (BIT(6))
+#define APB_CTRL_CLK_320M_OEN_V  0x1
+#define APB_CTRL_CLK_320M_OEN_S  6
+/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK160_OEN  (BIT(5))
+#define APB_CTRL_CLK160_OEN_M  (BIT(5))
+#define APB_CTRL_CLK160_OEN_V  0x1
+#define APB_CTRL_CLK160_OEN_S  5
+/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK80_OEN  (BIT(4))
+#define APB_CTRL_CLK80_OEN_M  (BIT(4))
+#define APB_CTRL_CLK80_OEN_V  0x1
+#define APB_CTRL_CLK80_OEN_S  4
+/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK_BB_OEN  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_M  (BIT(3))
+#define APB_CTRL_CLK_BB_OEN_V  0x1
+#define APB_CTRL_CLK_BB_OEN_S  3
+/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK44_OEN  (BIT(2))
+#define APB_CTRL_CLK44_OEN_M  (BIT(2))
+#define APB_CTRL_CLK44_OEN_V  0x1
+#define APB_CTRL_CLK44_OEN_S  2
+/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK22_OEN  (BIT(1))
+#define APB_CTRL_CLK22_OEN_M  (BIT(1))
+#define APB_CTRL_CLK22_OEN_V  0x1
+#define APB_CTRL_CLK22_OEN_S  1
+/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_CLK20_OEN  (BIT(0))
+#define APB_CTRL_CLK20_OEN_M  (BIT(0))
+#define APB_CTRL_CLK20_OEN_V  0x1
+#define APB_CTRL_CLK20_OEN_S  0
+
+#define APB_CTRL_HOST_INF_SEL_REG          (DR_REG_APB_CTRL_BASE + 0x048)
+/* APB_CTRL_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI_PRIOR  (BIT(13))
+#define APB_CTRL_SPI_PRIOR_M  (BIT(13))
+#define APB_CTRL_SPI_PRIOR_V  0x1
+#define APB_CTRL_SPI_PRIOR_S  13
+/* APB_CTRL_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI1_HOLD  (BIT(9))
+#define APB_CTRL_SPI1_HOLD_M  (BIT(9))
+#define APB_CTRL_SPI1_HOLD_V  0x1
+#define APB_CTRL_SPI1_HOLD_S  9
+/* APB_CTRL_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI0_HOLD  (BIT(8))
+#define APB_CTRL_SPI0_HOLD_M  (BIT(8))
+#define APB_CTRL_SPI0_HOLD_V  0x1
+#define APB_CTRL_SPI0_HOLD_S  8
+/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define APB_CTRL_PERI_IO_SWAP  0x000000FF
+#define APB_CTRL_PERI_IO_SWAP_M  ((APB_CTRL_PERI_IO_SWAP_V)<<(APB_CTRL_PERI_IO_SWAP_S))
+#define APB_CTRL_PERI_IO_SWAP_V  0xFF
+#define APB_CTRL_PERI_IO_SWAP_S  0
+
+#define APB_CTRL_EXT_MEM_PMS_LOCK_REG          (DR_REG_APB_CTRL_BASE + 0x04C)
+/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_EXT_MEM_PMS_LOCK  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define APB_CTRL_EXT_MEM_PMS_LOCK_V  0x1
+#define APB_CTRL_EXT_MEM_PMS_LOCK_S  0
+
+#define APB_CTRL_FLASH_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x050)
+/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_ATTR  0x00000007
+#define APB_CTRL_FLASH_ACE0_ATTR_M  ((APB_CTRL_FLASH_ACE0_ATTR_V)<<(APB_CTRL_FLASH_ACE0_ATTR_S))
+#define APB_CTRL_FLASH_ACE0_ATTR_V  0x7
+#define APB_CTRL_FLASH_ACE0_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x054)
+/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_ATTR  0x00000007
+#define APB_CTRL_FLASH_ACE1_ATTR_M  ((APB_CTRL_FLASH_ACE1_ATTR_V)<<(APB_CTRL_FLASH_ACE1_ATTR_S))
+#define APB_CTRL_FLASH_ACE1_ATTR_V  0x7
+#define APB_CTRL_FLASH_ACE1_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x058)
+/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_ATTR  0x00000007
+#define APB_CTRL_FLASH_ACE2_ATTR_M  ((APB_CTRL_FLASH_ACE2_ATTR_V)<<(APB_CTRL_FLASH_ACE2_ATTR_S))
+#define APB_CTRL_FLASH_ACE2_ATTR_V  0x7
+#define APB_CTRL_FLASH_ACE2_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x05C)
+/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_ATTR  0x00000007
+#define APB_CTRL_FLASH_ACE3_ATTR_M  ((APB_CTRL_FLASH_ACE3_ATTR_V)<<(APB_CTRL_FLASH_ACE3_ATTR_S))
+#define APB_CTRL_FLASH_ACE3_ATTR_V  0x7
+#define APB_CTRL_FLASH_ACE3_ATTR_S  0
+
+#define APB_CTRL_FLASH_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x060)
+/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_M  ((APB_CTRL_FLASH_ACE0_ADDR_S_V)<<(APB_CTRL_FLASH_ACE0_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE0_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x064)
+/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_M  ((APB_CTRL_FLASH_ACE1_ADDR_S_V)<<(APB_CTRL_FLASH_ACE1_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE1_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x068)
+/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_M  ((APB_CTRL_FLASH_ACE2_ADDR_S_V)<<(APB_CTRL_FLASH_ACE2_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE2_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x06C)
+/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_M  ((APB_CTRL_FLASH_ACE3_ADDR_S_V)<<(APB_CTRL_FLASH_ACE3_ADDR_S_S))
+#define APB_CTRL_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_FLASH_ACE3_ADDR_S_S  0
+
+#define APB_CTRL_FLASH_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x070)
+/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE0_SIZE  0x0000FFFF
+#define APB_CTRL_FLASH_ACE0_SIZE_M  ((APB_CTRL_FLASH_ACE0_SIZE_V)<<(APB_CTRL_FLASH_ACE0_SIZE_S))
+#define APB_CTRL_FLASH_ACE0_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE0_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x074)
+/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE1_SIZE  0x0000FFFF
+#define APB_CTRL_FLASH_ACE1_SIZE_M  ((APB_CTRL_FLASH_ACE1_SIZE_V)<<(APB_CTRL_FLASH_ACE1_SIZE_S))
+#define APB_CTRL_FLASH_ACE1_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE1_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x078)
+/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE2_SIZE  0x0000FFFF
+#define APB_CTRL_FLASH_ACE2_SIZE_M  ((APB_CTRL_FLASH_ACE2_SIZE_V)<<(APB_CTRL_FLASH_ACE2_SIZE_S))
+#define APB_CTRL_FLASH_ACE2_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE2_SIZE_S  0
+
+#define APB_CTRL_FLASH_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x07C)
+/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_FLASH_ACE3_SIZE  0x0000FFFF
+#define APB_CTRL_FLASH_ACE3_SIZE_M  ((APB_CTRL_FLASH_ACE3_SIZE_V)<<(APB_CTRL_FLASH_ACE3_SIZE_S))
+#define APB_CTRL_FLASH_ACE3_SIZE_V  0xFFFF
+#define APB_CTRL_FLASH_ACE3_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE0_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x080)
+/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE0_ATTR  0x00000007
+#define APB_CTRL_SRAM_ACE0_ATTR_M  ((APB_CTRL_SRAM_ACE0_ATTR_V)<<(APB_CTRL_SRAM_ACE0_ATTR_S))
+#define APB_CTRL_SRAM_ACE0_ATTR_V  0x7
+#define APB_CTRL_SRAM_ACE0_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE1_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x084)
+/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE1_ATTR  0x00000007
+#define APB_CTRL_SRAM_ACE1_ATTR_M  ((APB_CTRL_SRAM_ACE1_ATTR_V)<<(APB_CTRL_SRAM_ACE1_ATTR_S))
+#define APB_CTRL_SRAM_ACE1_ATTR_V  0x7
+#define APB_CTRL_SRAM_ACE1_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE2_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x088)
+/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE2_ATTR  0x00000007
+#define APB_CTRL_SRAM_ACE2_ATTR_M  ((APB_CTRL_SRAM_ACE2_ATTR_V)<<(APB_CTRL_SRAM_ACE2_ATTR_S))
+#define APB_CTRL_SRAM_ACE2_ATTR_V  0x7
+#define APB_CTRL_SRAM_ACE2_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE3_ATTR_REG          (DR_REG_APB_CTRL_BASE + 0x08C)
+/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE3_ATTR  0x00000007
+#define APB_CTRL_SRAM_ACE3_ATTR_M  ((APB_CTRL_SRAM_ACE3_ATTR_V)<<(APB_CTRL_SRAM_ACE3_ATTR_S))
+#define APB_CTRL_SRAM_ACE3_ATTR_V  0x7
+#define APB_CTRL_SRAM_ACE3_ATTR_S  0
+
+#define APB_CTRL_SRAM_ACE0_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x090)
+/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE0_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE0_ADDR_S_M  ((APB_CTRL_SRAM_ACE0_ADDR_S_V)<<(APB_CTRL_SRAM_ACE0_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE0_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE0_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE1_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x094)
+/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE1_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE1_ADDR_S_M  ((APB_CTRL_SRAM_ACE1_ADDR_S_V)<<(APB_CTRL_SRAM_ACE1_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE1_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE1_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE2_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x098)
+/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE2_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE2_ADDR_S_M  ((APB_CTRL_SRAM_ACE2_ADDR_S_V)<<(APB_CTRL_SRAM_ACE2_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE2_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE2_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE3_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x09C)
+/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE3_ADDR_S  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE3_ADDR_S_M  ((APB_CTRL_SRAM_ACE3_ADDR_S_V)<<(APB_CTRL_SRAM_ACE3_ADDR_S_S))
+#define APB_CTRL_SRAM_ACE3_ADDR_S_V  0xFFFFFFFF
+#define APB_CTRL_SRAM_ACE3_ADDR_S_S  0
+
+#define APB_CTRL_SRAM_ACE0_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x0A0)
+/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE0_SIZE  0x0000FFFF
+#define APB_CTRL_SRAM_ACE0_SIZE_M  ((APB_CTRL_SRAM_ACE0_SIZE_V)<<(APB_CTRL_SRAM_ACE0_SIZE_S))
+#define APB_CTRL_SRAM_ACE0_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE0_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE1_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x0A4)
+/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE1_SIZE  0x0000FFFF
+#define APB_CTRL_SRAM_ACE1_SIZE_M  ((APB_CTRL_SRAM_ACE1_SIZE_V)<<(APB_CTRL_SRAM_ACE1_SIZE_S))
+#define APB_CTRL_SRAM_ACE1_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE1_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE2_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x0A8)
+/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE2_SIZE  0x0000FFFF
+#define APB_CTRL_SRAM_ACE2_SIZE_M  ((APB_CTRL_SRAM_ACE2_SIZE_V)<<(APB_CTRL_SRAM_ACE2_SIZE_S))
+#define APB_CTRL_SRAM_ACE2_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE2_SIZE_S  0
+
+#define APB_CTRL_SRAM_ACE3_SIZE_REG          (DR_REG_APB_CTRL_BASE + 0x0AC)
+/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define APB_CTRL_SRAM_ACE3_SIZE  0x0000FFFF
+#define APB_CTRL_SRAM_ACE3_SIZE_M  ((APB_CTRL_SRAM_ACE3_SIZE_V)<<(APB_CTRL_SRAM_ACE3_SIZE_S))
+#define APB_CTRL_SRAM_ACE3_SIZE_V  0xFFFF
+#define APB_CTRL_SRAM_ACE3_SIZE_S  0
+
+#define APB_CTRL_SPI0_PMS_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x0B0)
+/* APB_CTRL_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define APB_CTRL_SPI0_REJECT_CDE  0x0000001F
+#define APB_CTRL_SPI0_REJECT_CDE_M  ((APB_CTRL_SPI0_REJECT_CDE_V)<<(APB_CTRL_SPI0_REJECT_CDE_S))
+#define APB_CTRL_SPI0_REJECT_CDE_V  0x1F
+#define APB_CTRL_SPI0_REJECT_CDE_S  2
+/* APB_CTRL_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI0_REJECT_CLR  (BIT(1))
+#define APB_CTRL_SPI0_REJECT_CLR_M  (BIT(1))
+#define APB_CTRL_SPI0_REJECT_CLR_V  0x1
+#define APB_CTRL_SPI0_REJECT_CLR_S  1
+/* APB_CTRL_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI0_REJECT_INT  (BIT(0))
+#define APB_CTRL_SPI0_REJECT_INT_M  (BIT(0))
+#define APB_CTRL_SPI0_REJECT_INT_V  0x1
+#define APB_CTRL_SPI0_REJECT_INT_S  0
+
+#define APB_CTRL_SPI0_REJECT_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0B4)
+/* APB_CTRL_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_SPI0_REJECT_ADDR  0xFFFFFFFF
+#define APB_CTRL_SPI0_REJECT_ADDR_M  ((APB_CTRL_SPI0_REJECT_ADDR_V)<<(APB_CTRL_SPI0_REJECT_ADDR_S))
+#define APB_CTRL_SPI0_REJECT_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_SPI0_REJECT_ADDR_S  0
+
+#define APB_CTRL_SPI1_PMS_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x0B8)
+/* APB_CTRL_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define APB_CTRL_SPI1_REJECT_CDE  0x0000001F
+#define APB_CTRL_SPI1_REJECT_CDE_M  ((APB_CTRL_SPI1_REJECT_CDE_V)<<(APB_CTRL_SPI1_REJECT_CDE_S))
+#define APB_CTRL_SPI1_REJECT_CDE_V  0x1F
+#define APB_CTRL_SPI1_REJECT_CDE_S  2
+/* APB_CTRL_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI1_REJECT_CLR  (BIT(1))
+#define APB_CTRL_SPI1_REJECT_CLR_M  (BIT(1))
+#define APB_CTRL_SPI1_REJECT_CLR_V  0x1
+#define APB_CTRL_SPI1_REJECT_CLR_S  1
+/* APB_CTRL_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_SPI1_REJECT_INT  (BIT(0))
+#define APB_CTRL_SPI1_REJECT_INT_M  (BIT(0))
+#define APB_CTRL_SPI1_REJECT_INT_V  0x1
+#define APB_CTRL_SPI1_REJECT_INT_S  0
+
+#define APB_CTRL_SPI1_REJECT_ADDR_REG          (DR_REG_APB_CTRL_BASE + 0x0BC)
+/* APB_CTRL_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_SPI1_REJECT_ADDR  0xFFFFFFFF
+#define APB_CTRL_SPI1_REJECT_ADDR_M  ((APB_CTRL_SPI1_REJECT_ADDR_V)<<(APB_CTRL_SPI1_REJECT_ADDR_S))
+#define APB_CTRL_SPI1_REJECT_ADDR_V  0xFFFFFFFF
+#define APB_CTRL_SPI1_REJECT_ADDR_S  0
+
+#define APB_CTRL_SDIO_CTRL_REG          (DR_REG_APB_CTRL_BASE + 0x0C0)
+/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_SDIO_WIN_ACCESS_EN  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_V  0x1
+#define APB_CTRL_SDIO_WIN_ACCESS_EN_S  0
+
+#define APB_CTRL_REDCY_SIG0_REG          (DR_REG_APB_CTRL_BASE + 0x0C4)
+/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_ANDOR  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_ANDOR_V  0x1
+#define APB_CTRL_REDCY_ANDOR_S  31
+/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_SIG0  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_M  ((APB_CTRL_REDCY_SIG0_V)<<(APB_CTRL_REDCY_SIG0_S))
+#define APB_CTRL_REDCY_SIG0_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG0_S  0
+
+#define APB_CTRL_REDCY_SIG1_REG          (DR_REG_APB_CTRL_BASE + 0x0C8)
+/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_NANDOR  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_M  (BIT(31))
+#define APB_CTRL_REDCY_NANDOR_V  0x1
+#define APB_CTRL_REDCY_NANDOR_S  31
+/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define APB_CTRL_REDCY_SIG1  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_M  ((APB_CTRL_REDCY_SIG1_V)<<(APB_CTRL_REDCY_SIG1_S))
+#define APB_CTRL_REDCY_SIG1_V  0x7FFFFFFF
+#define APB_CTRL_REDCY_SIG1_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_REG          (DR_REG_APB_CTRL_BASE + 0x0CC)
+/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_BB_CFG  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_M  ((APB_CTRL_WIFI_BB_CFG_V)<<(APB_CTRL_WIFI_BB_CFG_S))
+#define APB_CTRL_WIFI_BB_CFG_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_S  0
+
+#define APB_CTRL_WIFI_BB_CFG_2_REG          (DR_REG_APB_CTRL_BASE + 0x0D0)
+/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_BB_CFG_2  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_M  ((APB_CTRL_WIFI_BB_CFG_2_V)<<(APB_CTRL_WIFI_BB_CFG_2_S))
+#define APB_CTRL_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_BB_CFG_2_S  0
+
+#define APB_CTRL_WIFI_CLK_EN_REG          (DR_REG_APB_CTRL_BASE + 0x0D4)
+/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define APB_CTRL_WIFI_CLK_EN  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_M  ((APB_CTRL_WIFI_CLK_EN_V)<<(APB_CTRL_WIFI_CLK_EN_S))
+#define APB_CTRL_WIFI_CLK_EN_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_CLK_EN_S  0
+
+#define APB_CTRL_WIFI_RST_EN_REG          (DR_REG_APB_CTRL_BASE + 0x0D8)
+/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define APB_CTRL_WIFI_RST  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_M  ((APB_CTRL_WIFI_RST_V)<<(APB_CTRL_WIFI_RST_S))
+#define APB_CTRL_WIFI_RST_V  0xFFFFFFFF
+#define APB_CTRL_WIFI_RST_S  0
+
+#define APB_CTRL_FRONT_END_MEM_PD_REG          (DR_REG_APB_CTRL_BASE + 0x0DC)
+/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_DC_MEM_FORCE_PD  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_M  (BIT(5))
+#define APB_CTRL_DC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PD_S  5
+/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_DC_MEM_FORCE_PU  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_M  (BIT(4))
+#define APB_CTRL_DC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_DC_MEM_FORCE_PU_S  4
+/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_PBUS_MEM_FORCE_PD  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define APB_CTRL_PBUS_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PD_S  3
+/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_PBUS_MEM_FORCE_PU  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define APB_CTRL_PBUS_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_PBUS_MEM_FORCE_PU_S  2
+/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define APB_CTRL_AGC_MEM_FORCE_PD  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define APB_CTRL_AGC_MEM_FORCE_PD_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PD_S  1
+/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define APB_CTRL_AGC_MEM_FORCE_PU  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define APB_CTRL_AGC_MEM_FORCE_PU_V  0x1
+#define APB_CTRL_AGC_MEM_FORCE_PU_S  0
+
+#define APB_CTRL_DATE_REG          (DR_REG_APB_CTRL_BASE + 0x3FC)
+/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */
+/*description: */
+#define APB_CTRL_DATE  0xFFFFFFFF
+#define APB_CTRL_DATE_M  ((APB_CTRL_DATE_V)<<(APB_CTRL_DATE_S))
+#define APB_CTRL_DATE_V  0xFFFFFFFF
+#define APB_CTRL_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_APB_CTRL_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h b/components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h
new file mode 100644
index 000000000..0e002330f
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/apb_ctrl_struct.h
@@ -0,0 +1,524 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_APB_CTRL_STRUCT_H_
+#define _SOC_APB_CTRL_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t pre_div:     10;
+            uint32_t clk_320m_en:  1;
+            uint32_t clk_en:       1;
+            uint32_t rst_tick:     1;
+            uint32_t reserved13:   1;
+            uint32_t soc_clk_sel:  2;
+            uint32_t reserved16:  16;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t xtal_tick:     8;
+            uint32_t ck8m_tick:     8;
+            uint32_t tick_enable:   1;
+            uint32_t reserved17:   15;
+        };
+        uint32_t val;
+    } tick_conf;
+    union {
+        struct {
+            uint32_t start_force:              1;
+            uint32_t start:                    1;
+            uint32_t reserved2:                1;
+            uint32_t work_mode:                2;       /*0: single mode  1: double mode  2: alternate mode*/
+            uint32_t sar_sel:                  1;       /*0: SAR1  1: SAR2  only work for single SAR mode*/
+            uint32_t sar_clk_gated:            1;
+            uint32_t sar_clk_div:              8;       /*SAR clock divider*/
+            uint32_t sar1_patt_len:            4;       /*0 ~ 15 means length 1 ~ 16*/
+            uint32_t sar2_patt_len:            4;       /*0 ~ 15 means length 1 ~ 16*/
+            uint32_t sar1_patt_p_clear:        1;       /*clear the pointer of pattern table for DIG ADC1 CTRL*/
+            uint32_t sar2_patt_p_clear:        1;       /*clear the pointer of pattern table for DIG ADC2 CTRL*/
+            uint32_t data_sar_sel:             1;       /*1: sar_sel will be coded by the MSB of the 16-bit output data  in this case the resolution should not be larger than 11 bits.*/
+            uint32_t data_to_i2s:              1;       /*1: I2S input data is from SAR ADC (for DMA)  0: I2S input data is from GPIO matrix*/
+            uint32_t xpd_sar_force:            2;       /*force option to xpd sar blocks*/
+            uint32_t reserved29:               3;
+        };
+        uint32_t val;
+    } saradc_ctrl;
+    union {
+        struct {
+            uint32_t meas_num_limit:        1;
+            uint32_t max_meas_num:          8;          /*max conversion number*/
+            uint32_t sar1_inv:              1;          /*1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+            uint32_t sar2_inv:              1;          /*1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+            uint32_t timer_sel:             1;          /*1: select saradc timer 0: i2s_ws trigger*/
+            uint32_t timer_target:          8;          /*to set saradc timer target*/
+            uint32_t timer_en:              1;          /*to enable saradc timer trigger*/
+            uint32_t reserved21:           11;
+        };
+        uint32_t val;
+    } saradc_ctrl2;
+    union {
+        struct {
+            uint32_t reserved0:          16;
+            uint32_t sample_num:          8;            /*sample number*/
+            uint32_t sample_cycle:        8;            /*sample cycles*/
+        };
+        uint32_t val;
+    } saradc_fsm;
+    union {
+        struct {
+            uint32_t xpd_wait:            8;
+            uint32_t rstb_wait:           8;
+            uint32_t standby_wait:        8;
+            uint32_t reserved24:          8;
+        };
+        uint32_t val;
+    } saradc_fsm_wait;
+    uint32_t saradc_sar1_status;                    /**/
+    uint32_t saradc_sar2_status;                    /**/
+    uint32_t saradc_sar1_patt_tab1;                 /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
+    uint32_t saradc_sar1_patt_tab2;                 /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
+    uint32_t saradc_sar1_patt_tab3;                 /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
+    uint32_t saradc_sar1_patt_tab4;                 /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
+    uint32_t saradc_sar2_patt_tab1;                 /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
+    uint32_t saradc_sar2_patt_tab2;                 /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
+    uint32_t saradc_sar2_patt_tab3;                 /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
+    uint32_t saradc_sar2_patt_tab4;                 /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
+    union {
+        struct {
+            uint32_t reserved0:             2;
+            uint32_t adc_arb_apb_force:     1;          /*adc2 arbiter force to enableapb controller*/
+            uint32_t adc_arb_rtc_force:     1;          /*adc2 arbiter force to enable rtc controller*/
+            uint32_t adc_arb_wifi_force:    1;          /*adc2 arbiter force to enable wifi controller*/
+            uint32_t adc_arb_grant_force:   1;          /*adc2 arbiter force grant*/
+            uint32_t adc_arb_apb_priority:  2;          /*Set adc2 arbiterapb priority*/
+            uint32_t adc_arb_rtc_priority:  2;          /*Set adc2 arbiter rtc priority*/
+            uint32_t adc_arb_wifi_priority: 2;          /*Set adc2 arbiter wifi priority*/
+            uint32_t adc_arb_fix_priority:  1;          /*adc2 arbiter uses fixed priority*/
+            uint32_t reserved13:           19;
+        };
+        uint32_t val;
+    } adc_arb_ctrl;
+    union {
+        struct {
+            uint32_t clk20_oen:       1;
+            uint32_t clk22_oen:       1;
+            uint32_t clk44_oen:       1;
+            uint32_t clk_bb_oen:      1;
+            uint32_t clk80_oen:       1;
+            uint32_t clk160_oen:      1;
+            uint32_t clk_320m_oen:    1;
+            uint32_t clk_adc_inf_oen: 1;
+            uint32_t clk_dac_cpu_oen: 1;
+            uint32_t clk40x_bb_oen:   1;
+            uint32_t clk_xtal_oen:    1;
+            uint32_t reserved11:     21;
+        };
+        uint32_t val;
+    } clk_out_en;
+    union {
+        struct {
+            uint32_t peri_io_swap: 8;
+            uint32_t spi0_hold:    1;
+            uint32_t spi1_hold:    1;
+            uint32_t reserved10:   3;
+            uint32_t spi_prior:    1;
+            uint32_t reserved14:  18;
+        };
+        uint32_t val;
+    } host_inf_sel;
+    union {
+        struct {
+            uint32_t ext_mem_pms_lock: 1;
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } ext_mem_pms_lock;
+    union {
+        struct {
+            uint32_t flash_ace0_attr: 3;
+            uint32_t reserved3:      29;
+        };
+        uint32_t val;
+    } flash_ace0_attr;
+    union {
+        struct {
+            uint32_t flash_ace1_attr: 3;
+            uint32_t reserved3:      29;
+        };
+        uint32_t val;
+    } flash_ace1_attr;
+    union {
+        struct {
+            uint32_t flash_ace2_attr: 3;
+            uint32_t reserved3:      29;
+        };
+        uint32_t val;
+    } flash_ace2_attr;
+    union {
+        struct {
+            uint32_t flash_ace3_attr: 3;
+            uint32_t reserved3:      29;
+        };
+        uint32_t val;
+    } flash_ace3_attr;
+    uint32_t flash_ace0_addr;                           /**/
+    uint32_t flash_ace1_addr;                           /**/
+    uint32_t flash_ace2_addr;                           /**/
+    uint32_t flash_ace3_addr;                           /**/
+    union {
+        struct {
+            uint32_t flash_ace0_size:16;
+            uint32_t reserved16:     16;
+        };
+        uint32_t val;
+    } flash_ace0_size;
+    union {
+        struct {
+            uint32_t flash_ace1_size:16;
+            uint32_t reserved16:     16;
+        };
+        uint32_t val;
+    } flash_ace1_size;
+    union {
+        struct {
+            uint32_t flash_ace2_size:16;
+            uint32_t reserved16:     16;
+        };
+        uint32_t val;
+    } flash_ace2_size;
+    union {
+        struct {
+            uint32_t flash_ace3_size:16;
+            uint32_t reserved16:     16;
+        };
+        uint32_t val;
+    } flash_ace3_size;
+    union {
+        struct {
+            uint32_t sram_ace0_attr: 3;
+            uint32_t reserved3:     29;
+        };
+        uint32_t val;
+    } sram_ace0_attr;
+    union {
+        struct {
+            uint32_t sram_ace1_attr: 3;
+            uint32_t reserved3:     29;
+        };
+        uint32_t val;
+    } sram_ace1_attr;
+    union {
+        struct {
+            uint32_t sram_ace2_attr: 3;
+            uint32_t reserved3:     29;
+        };
+        uint32_t val;
+    } sram_ace2_attr;
+    union {
+        struct {
+            uint32_t sram_ace3_attr: 3;
+            uint32_t reserved3:     29;
+        };
+        uint32_t val;
+    } sram_ace3_attr;
+    uint32_t sram_ace0_addr;                            /**/
+    uint32_t sram_ace1_addr;                            /**/
+    uint32_t sram_ace2_addr;                            /**/
+    uint32_t sram_ace3_addr;                            /**/
+    union {
+        struct {
+            uint32_t sram_ace0_size:16;
+            uint32_t reserved16:    16;
+        };
+        uint32_t val;
+    } sram_ace0_size;
+    union {
+        struct {
+            uint32_t sram_ace1_size:16;
+            uint32_t reserved16:    16;
+        };
+        uint32_t val;
+    } sram_ace1_size;
+    union {
+        struct {
+            uint32_t sram_ace2_size:16;
+            uint32_t reserved16:    16;
+        };
+        uint32_t val;
+    } sram_ace2_size;
+    union {
+        struct {
+            uint32_t sram_ace3_size:16;
+            uint32_t reserved16:    16;
+        };
+        uint32_t val;
+    } sram_ace3_size;
+    union {
+        struct {
+            uint32_t spi0_reject_int: 1;
+            uint32_t spi0_reject_clr: 1;
+            uint32_t spi0_reject_cde: 5;
+            uint32_t reserved7:      25;
+        };
+        uint32_t val;
+    } spi0_pms_ctrl;
+    uint32_t spi0_reject_addr;                          /**/
+    union {
+        struct {
+            uint32_t spi1_reject_int: 1;
+            uint32_t spi1_reject_clr: 1;
+            uint32_t spi1_reject_cde: 5;
+            uint32_t reserved7:      25;
+        };
+        uint32_t val;
+    } spi1_pms_ctrl;
+    uint32_t spi1_reject_addr;                          /**/
+    union {
+        struct {
+            uint32_t sdio_win_access_en: 1;
+            uint32_t reserved1:         31;
+        };
+        uint32_t val;
+    } sdio_ctrl;
+    union {
+        struct {
+            uint32_t redcy_sig0: 31;
+            uint32_t redcy_andor: 1;
+        };
+        uint32_t val;
+    } redcy_sig0;
+    union {
+        struct {
+            uint32_t redcy_sig1:  31;
+            uint32_t redcy_nandor: 1;
+        };
+        uint32_t val;
+    } redcy_sig1;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    uint32_t date;                                      /**/
+} apb_ctrl_dev_t;
+extern apb_ctrl_dev_t APB_CTRL;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_APB_CTRL_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/assist_debug_reg.h b/components/soc/esp32s2beta/include/soc/assist_debug_reg.h
new file mode 100644
index 000000000..bb34e315d
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/assist_debug_reg.h
@@ -0,0 +1,115 @@
+#define ASSIST_DEBUG_BASE DR_REG_ASSIST_DEBUG_BASE
+
+#define ASSIST_DEBUG_INTERRUPT_ENA              ((ASSIST_DEBUG_BASE) +0x00)
+#define ASSIST_DEBUG_INTERRUPT_RAW              ((ASSIST_DEBUG_BASE) +0x04)
+#define ASSIST_DEBUG_INTERRUPT_RLS              ((ASSIST_DEBUG_BASE) +0x08)
+#define ASSIST_DEBUG_INTERRUPT_CLR              ((ASSIST_DEBUG_BASE) +0x0C)
+#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_RD                   BIT(0)
+#define ASSIST_DEBUG_INTERRUPT_AREA_0_TOUCH_PRO_WR                   BIT(1)
+#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_RD                   BIT(2)
+#define ASSIST_DEBUG_INTERRUPT_AREA_1_TOUCH_PRO_WR                   BIT(3)
+#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MIN                      BIT(4)
+#define ASSIST_DEBUG_INTERRUPT_PRO_SP_SPILL_MAX                      BIT(5)
+
+
+#define ASSIST_DEBUG_AREA_0_MIN                 ((ASSIST_DEBUG_BASE) +0x10)
+#define ASSIST_DEBUG_AREA_0_MAX                 ((ASSIST_DEBUG_BASE) +0x14)
+#define ASSIST_DEBUG_AREA_0_PC                  ((ASSIST_DEBUG_BASE) +0x18)
+#define ASSIST_DEBUG_AREA_0_SP                  ((ASSIST_DEBUG_BASE) +0x1C)
+
+#define ASSIST_DEBUG_AREA_1_MIN                 ((ASSIST_DEBUG_BASE) +0x20)
+#define ASSIST_DEBUG_AREA_1_MAX                 ((ASSIST_DEBUG_BASE) +0x24)
+#define ASSIST_DEBUG_AREA_1_PC                  ((ASSIST_DEBUG_BASE) +0x28)
+#define ASSIST_DEBUG_AREA_1_SP                  ((ASSIST_DEBUG_BASE) +0x2C)
+
+#define ASSIST_DEBUG_PRO_SP_UNSTABLE            ((ASSIST_DEBUG_BASE) +0x30)
+#define ASSIST_DEBUG_PRO_SP_MIN                 ((ASSIST_DEBUG_BASE) +0x34)
+#define ASSIST_DEBUG_PRO_SP_MAX                 ((ASSIST_DEBUG_BASE) +0x38)
+#define ASSIST_DEBUG_PRO_SP_PC                  ((ASSIST_DEBUG_BASE) +0x3C)
+
+#define ASSIST_DEBUG_PRO_PDEBUGENABLE		((ASSIST_DEBUG_BASE) +0x40)
+#define ASSIST_DEBUG_PRO_RCD_RECORDING		((ASSIST_DEBUG_BASE) +0x44)
+#define ASSIST_DEBUG_PRO_RCD_PDEBUGINST		((ASSIST_DEBUG_BASE) +0x48)
+/* register layout:
+ * SIZE [7..0]           : Instructions normally complete in the W stage. The size of the instruction in the W is given
+ *                         by this field in number of bytes. If it is 8’b0 in a given cycle the W stage has no completing
+ *                         instruction. This is also known as a bubble cycle. Also see DPORT_PRO_CPU_RECORD_PDEBUGSTATUS_REG.
+ * ISRC [14..12]         : Instruction source.
+** LOOP [23..20]         : Loopback status.
+** CINTLEVEL [27..24]: CINTLEVEL.
+*/
+#define DPORT_RECORD_PDEBUGINST_SZ_M            ((DPORT_RECORD_PDEBUGINST_SZ_V)<<(DPORT_RECORD_PDEBUGINST_SZ_S))
+#define DPORT_RECORD_PDEBUGINST_SZ_V            0xFF
+#define DPORT_RECORD_PDEBUGINST_SZ_S            0
+#define DPORT_RECORD_PDEBUGINST_SZ(_r_)         (((_r_)>>DPORT_RECORD_PDEBUGINST_SZ_S) & DPORT_RECORD_PDEBUGINST_SZ_V)
+#define DPORT_RECORD_PDEBUGINST_ISRC_M          ((DPORT_RECORD_PDEBUGINST_ISRC_V)<<(DPORT_RECORD_PDEBUGINST_ISRC_S))
+#define DPORT_RECORD_PDEBUGINST_ISRC_V          0x07
+#define DPORT_RECORD_PDEBUGINST_ISRC_S          12
+#define DPORT_RECORD_PDEBUGINST_ISRC(_r_)       (((_r_)>>DPORT_RECORD_PDEBUGINST_ISRC_S) & DPORT_RECORD_PDEBUGINST_ISRC_V)
+// #define DPORT_RECORD_PDEBUGINST_LOOP_M       ((DPORT_RECORD_PDEBUGINST_LOOP_V)<<(DPORT_RECORD_PDEBUGINST_LOOP_S))
+// #define DPORT_RECORD_PDEBUGINST_LOOP_V       0x0F
+// #define DPORT_RECORD_PDEBUGINST_LOOP_S       20
+// #define DPORT_RECORD_PDEBUGINST_LOOP(_r_)    (((_r_)>>DPORT_RECORD_PDEBUGINST_LOOP_S) & DPORT_RECORD_PDEBUGINST_LOOP_V)
+#define DPORT_RECORD_PDEBUGINST_LOOP_REP        (BIT(20)) /* loopback will occur */
+#define DPORT_RECORD_PDEBUGINST_LOOP            (BIT(21)) /* last inst of loop */
+#define DPORT_RECORD_PDEBUGINST_CINTL_M         ((DPORT_RECORD_PDEBUGINST_CINTL_V)<<(DPORT_RECORD_PDEBUGINST_CINTL_S))
+#define DPORT_RECORD_PDEBUGINST_CINTL_V         0x0F
+#define DPORT_RECORD_PDEBUGINST_CINTL_S         24
+#define DPORT_RECORD_PDEBUGINST_CINTL(_r_)      (((_r_)>>DPORT_RECORD_PDEBUGINST_CINTL_S) & DPORT_RECORD_PDEBUGINST_CINTL_V)
+
+#define ASSIST_DEBUG_PRO_RCD_PDEBUGSTATUS	((ASSIST_DEBUG_BASE) +0x4C)
+/* register layout:
+ * BBCAUSE [5..0]: Indicates cause for bubble cycle. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ == 0
+ * INSNTYPE[5..0]: Indicates type of instruction retiring in the W stage. See below for posible values. When DPORT_RECORD_PDEBUGINST_SZ > 0
+*/
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_M             ((DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)<<(DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S))
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V             0x3F
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S             0
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE(_r_)          (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_S) & DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_V)
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_PSO           0x00 /* Power shut off */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DEP           0x02 /* Register dependency or resource conflict. See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_CTL           0x04 /* Control transfer bubble */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ICM           0x08 /* I-cache miss (incl uncached miss) */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DCM           0x0C /* D-cache miss (excl uncached miss) */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC0          0x10 /* Exception or interrupt (W stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info.
+                                                                                                                        The virtual address of the instruction that was killed appears on DPORT_PRO_CPU_RECORD_PDEBUGPC_REG[31:0] */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_EXC1          0x11 /* Exception or interrupt (W+1 stage). See DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG for extra info. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_RPL           0x14 /* Instruction replay (other). DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG has the PC of the replaying instruction. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLB          0x18 /* HW ITLB refill. The refill address and data are available on
+                                                                                                                        DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_ITLBM         0x1A /* ITLB miss */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLB          0x1C /* HW DTLB refill. The refill address and data are available on
+                                                                                                                        DPORT_PRO_CPU_RECORD_PDEBUGLS0ADDR_REG and DPORT_PRO_CPU_RECORD_PDEBUGLS0DATA_REG. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_DTLBM         0x1E /* DTLB miss */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_STALL         0x20 /* Stall . The cause of the global stall is further classified in the DPORT_XXX_CPU_RECORD_PDEBUGDATA_REG. */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_HWMEC         0x24 /* HW-corrected memory error */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_WAITI         0x28 /* WAITI mode */
+#define DPORT_RECORD_PDEBUGSTATUS_BBCAUSE_OTHER         0x3C /* all other bubbles */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_M            ((DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)<<(DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S))
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V            0x3F
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S            0
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE(_r_)         (((_r_)>>DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S) & DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_V)
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_JX           0x00 /* JX */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALLX        0x04 /* CALLX */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CRET         0x08 /* All call returns */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_ERET         0x0C /* All exception returns */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_B            0x10 /* Branch taken or loop not taken */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_J            0x14 /* J */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_CALL         0x18 /* CALL */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_BN           0x1C /* Branch not taken */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_LOOP         0x20 /* Loop instruction (taken) */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_S32C1I       0x24 /* S32C1I. The address and load data (before the conditional store) are available on the LS signals*/
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WXSR2LB      0x28 /* WSR/XSR to LBEGIN */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_WSR2MMID     0x2C /* WSR to MMID */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWXSR        0x30 /* RSR or WSR (except MMID and LBEGIN) or XSR (except LBEGIN) */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_RWER         0x34 /* RER or WER */
+#define DPORT_RECORD_PDEBUGSTATUS_INSNTYPE_DEF          0x3C /* Default */
+
+
+#define ASSIST_DEBUG_PRO_RCD_PDEBUGDATA		((ASSIST_DEBUG_BASE) +0x50)
+#define ASSIST_DEBUG_PRO_RCD_PDEBUGPC		((ASSIST_DEBUG_BASE) +0x54)
+#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0STAT	((ASSIST_DEBUG_BASE) +0x58)
+#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0ADDR	((ASSIST_DEBUG_BASE) +0x5C)
+#define ASSIST_DEBUG_PRO_RCD_PDEBUGLS0DATA	((ASSIST_DEBUG_BASE) +0x60)
+#define ASSIST_DEBUG_PRO_RCD_SP			((ASSIST_DEBUG_BASE) +0x64)
+
diff --git a/components/soc/esp32s2beta/include/soc/bb_reg.h b/components/soc/esp32s2beta/include/soc/bb_reg.h
new file mode 100644
index 000000000..69d2f43d2
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/bb_reg.h
@@ -0,0 +1,42 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_BB_REG_H_
+#define _SOC_BB_REG_H_
+
+/* Some of the baseband control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
+#define BB_FFT_FORCE_PU (BIT(3))
+#define BB_FFT_FORCE_PU_M (BIT(3))
+#define BB_FFT_FORCE_PU_V 1
+#define BB_FFT_FORCE_PU_S 3
+#define BB_FFT_FORCE_PD (BIT(2))
+#define BB_FFT_FORCE_PD_M (BIT(2))
+#define BB_FFT_FORCE_PD_V 1
+#define BB_FFT_FORCE_PD_S 2
+#define BB_DC_EST_FORCE_PU (BIT(1))
+#define BB_DC_EST_FORCE_PU_M (BIT(1))
+#define BB_DC_EST_FORCE_PU_V 1
+#define BB_DC_EST_FORCE_PU_S 1
+#define BB_DC_EST_FORCE_PD (BIT(0))
+#define BB_DC_EST_FORCE_PD_M (BIT(0))
+#define BB_DC_EST_FORCE_PD_V 1
+#define BB_DC_EST_FORCE_PD_S 0
+
+
+#endif /* _SOC_BB_REG_H_ */
+
diff --git a/components/soc/esp32s2beta/include/soc/boot_mode.h b/components/soc/esp32s2beta/include/soc/boot_mode.h
new file mode 100644
index 000000000..46d7205d4
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/boot_mode.h
@@ -0,0 +1,92 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_BOOT_MODE_H_
+#define _SOC_BOOT_MODE_H_
+
+#include "soc.h"
+
+/*SPI Boot*/
+#define IS_1XXX(v)				(((v)&0x08)==0x08)
+
+/*Download Boot, USB/SDIO/UART0/UART1*/
+#define IS_00XX(v)				(((v)&0x0c)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
+#define IS_0000(v)				(((v)&0x0f)==0x00)
+
+/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
+#define IS_0001(v)				(((v)&0x0f)==0x01)
+
+/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
+#define IS_0010(v)				(((v)&0x0f)==0x02)
+
+/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
+#define IS_0011(v)				(((v)&0x0f)==0x03)
+
+/*ATE/ANALOG Mode*/
+#define IS_0101(v)				(((v)&0x0f)==0x05)
+
+/*Diagnostic Mode+UART0 download Mode*/
+#define IS_0111(v)				(((v)&0x0f)==0x07)
+
+/*legacy SPI Boot*/
+#define IS_0100(v)				(((v)&0x0f)==0x04)
+
+/*SDIO_Slave download Mode V1.1*/
+#define IS_0110(v)				(((v)&0x0f)==0x06)
+
+
+
+#define BOOT_MODE_GET()                                 (GPIO_REG_READ(GPIO_STRAP_REG))
+
+/*do not include download mode*/
+#define ETS_IS_UART_BOOT()				IS_0111(BOOT_MODE_GET())
+
+/*all spi boot including spi/legacy*/
+#define ETS_IS_FLASH_BOOT()				(IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
+
+/*all faster spi boot including spi*/
+#define ETS_IS_FAST_FLASH_BOOT()				IS_1XXX(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, failing edge output*/
+#define ETS_IS_SDIO_FEI_FEO_V2_BOOT()				IS_0000(BOOT_MODE_GET())
+
+/*all sdio V2 of failing edge input, raising edge output*/
+#define ETS_IS_SDIO_FEI_REO_V2_BOOT()				IS_0001(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V2_BOOT()				IS_0010(BOOT_MODE_GET())
+
+/*all sdio V2 of raising edge input, raising edge output*/
+#define ETS_IS_SDIO_REI_REO_V2_BOOT()				IS_0011(BOOT_MODE_GET())
+
+/*all sdio V1 of raising edge input, failing edge output*/
+#define ETS_IS_SDIO_REI_FEO_V1_BOOT()				IS_0110(BOOT_MODE_GET())
+
+/*do not include download mode*/
+#define ETS_IS_SDIO_BOOT()				IS_0110(BOOT_MODE_GET())
+
+/*joint download boot*/
+#define ETS_IS_USB_SDIO_UART_BOOT()				IS_00XX(BOOT_MODE_GET())
+
+/*ATE mode*/
+#define ETS_IS_ATE_BOOT()				IS_0101(BOOT_MODE_GET())
+
+/*used by  ETS_IS_SDIO_UART_BOOT*/
+#define SEL_NO_BOOT                                    0
+#define SEL_SDIO_BOOT                                 BIT0
+#define SEL_UART_BOOT                                BIT1
+
+#endif /* _SOC_BOOT_MODE_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/clkout_channel.h b/components/soc/esp32s2beta/include/soc/clkout_channel.h
new file mode 100644
index 000000000..c9e9a0c24
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/clkout_channel.h
@@ -0,0 +1,26 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_CLKOUT_CHANNEL_H
+#define _SOC_CLKOUT_CHANNEL_H
+
+//CLKOUT channels
+#define CLKOUT_GPIO20_DIRECT_CHANNEL         CLKOUT_CHANNEL_1
+#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM     20
+#define CLKOUT_GPIO19_DIRECT_CHANNEL         CLKOUT_CHANNEL_2
+#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM     19
+#define CLKOUT_GPIO18_DIRECT_CHANNEL         CLKOUT_CHANNEL_3
+#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM     18
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/cpu.h b/components/soc/esp32s2beta/include/soc/cpu.h
new file mode 100644
index 000000000..05ec91776
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/cpu.h
@@ -0,0 +1,104 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_CPU_H
+#define _SOC_CPU_H
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "xtensa/corebits.h"
+
+/* C macros for xtensa special register read/write/exchange */
+
+#define RSR(reg, curval)  asm volatile ("rsr %0, " #reg : "=r" (curval));
+#define WSR(reg, newval)  asm volatile ("wsr %0, " #reg : : "r" (newval));
+#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
+
+/** @brief Read current stack pointer address
+ *
+ */
+static inline void *get_sp()
+{
+    void *sp;
+    asm volatile ("mov %0, sp;" : "=r" (sp));
+    return sp;
+}
+
+/* Functions to set page attributes for Region Protection option in the CPU.
+ * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
+ */
+
+static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
+{
+    asm volatile ("wdtlb  %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
+}
+
+
+static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
+{
+    asm volatile ("witlb  %1, %0; isync\n" :: "r" (vpn), "r" (attr));
+}
+
+/**
+ * @brief Configure memory region protection
+ *
+ * Make page 0 access raise an exception.
+ * Also protect some other unused pages so we can catch weirdness.
+ * Useful attribute values:
+ * 0 — cached, RW
+ * 2 — bypass cache, RWX (default value after CPU reset)
+ * 15 — no access, raise exception
+ */
+
+static inline void cpu_configure_region_protection()
+{
+    const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
+    for (int i = 0; i < sizeof(pages_to_protect)/sizeof(pages_to_protect[0]); ++i) {
+        cpu_write_dtlb(pages_to_protect[i], 0xf);
+        cpu_write_itlb(pages_to_protect[i], 0xf);
+    }
+    cpu_write_dtlb(0x20000000, 0);
+    cpu_write_itlb(0x20000000, 0);
+}
+
+/**
+ * @brief Stall CPU using RTC controller
+ * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
+ */
+void esp_cpu_stall(int cpu_id);
+
+/**
+ * @brief Un-stall CPU using RTC controller
+ * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
+ */
+void esp_cpu_unstall(int cpu_id);
+
+/**
+ * @brief Reset CPU using RTC controller
+ * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
+ */
+void esp_cpu_reset(int cpu_id);
+
+
+/**
+ * @brief Returns true if a JTAG debugger is attached to CPU
+ * OCD (on chip debug) port.
+ *
+ * @note If "Make exception and panic handlers JTAG/OCD aware"
+ * is disabled, this function always returns false.
+ */
+bool esp_cpu_in_ocd_debug_mode();
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/dac_channel.h b/components/soc/esp32s2beta/include/soc/dac_channel.h
new file mode 100644
index 000000000..175158f78
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/dac_channel.h
@@ -0,0 +1,24 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_DAC_CHANNEL_H
+#define _SOC_DAC_CHANNEL_H
+
+#define DAC_GPIO17_CHANNEL      DAC_CHANNEL_1
+#define DAC_CHANNEL_1_GPIO_NUM  17
+
+#define DAC_GPIO18_CHANNEL      DAC_CHANNEL_2
+#define DAC_CHANNEL_2_GPIO_NUM  18
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/dport_access.h b/components/soc/esp32s2beta/include/soc/dport_access.h
new file mode 100644
index 000000000..bee3da39e
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/dport_access.h
@@ -0,0 +1,111 @@
+// Copyright 2010-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _DPORT_ACCESS_H_
+#define _DPORT_ACCESS_H_
+
+#include <stdint.h>
+#include "esp_attr.h"
+#include "esp_dport_access.h"
+#include "soc.h"
+#include "uart_reg.h"
+#include "xtensa/xtruntime.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+// ESP32C is single core and does not have DPORT bug, so these macros are all same as the non-DPORT versions
+
+// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
+#define _DPORT_REG_READ(_r)        (*(volatile uint32_t *)(_r))
+#define _DPORT_REG_WRITE(_r, _v)   (*(volatile uint32_t *)(_r)) = (_v)
+
+// Write value to DPORT register (does not require protecting)
+#define DPORT_REG_WRITE(_r, _v)   _DPORT_REG_WRITE((_r), (_v))
+
+#define DPORT_REG_READ(_r)    _DPORT_REG_READ(_r)
+#define DPORT_SEQUENCE_REG_READ(_r)    _DPORT_REG_READ(_r)
+
+//get bit or get bits from register
+#define DPORT_REG_GET_BIT(_r, _b)  (DPORT_REG_READ(_r) & (_b))
+
+//set bit or set bits to register
+#define DPORT_REG_SET_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
+
+//clear bit or clear bits of register
+#define DPORT_REG_CLR_BIT(_r, _b)  DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
+
+//set bits of register controlled by mask
+#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
+
+//get field from register, uses field _S & _V to determine mask
+#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
+
+//set field to register, used when _f is not left shifted by _f##_S
+#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
+#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
+#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
+#define _DPORT_REG_SET_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
+#define _DPORT_REG_CLR_BIT(_r, _b)  _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
+
+#define DPORT_READ_PERI_REG(addr)       _DPORT_READ_PERI_REG(addr)
+
+//write value to register
+#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
+
+//clear bits of register controlled by mask
+#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
+
+//set bits of register controlled by mask
+#define DPORT_SET_PERI_REG_MASK(reg, mask)   DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
+
+//get bits of register controlled by mask
+#define DPORT_GET_PERI_REG_MASK(reg, mask)   (DPORT_READ_PERI_REG(reg) & (mask))
+
+//get bits of register controlled by highest bit and lowest bit
+#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos)     ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
+
+//set bits of register controlled by mask and shift
+#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
+
+//get field of register
+#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift)      ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
+//}}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _DPORT_ACCESS_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/dport_reg.h b/components/soc/esp32s2beta/include/soc/dport_reg.h
new file mode 100644
index 000000000..17270ac98
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/dport_reg.h
@@ -0,0 +1,193 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_DPORT_REG_H_
+#define _SOC_DPORT_REG_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include"extmem_reg.h"
+#include"interrupt_reg.h"
+#include"system_reg.h"
+#include "sensitive_reg.h"
+#include "soc.h"
+
+/*IRAM0 connected with Cache IBUS0*/
+#define IRAM0_ADDRESS_LOW		0x40000000
+#define IRAM0_ADDRESS_HIGH		0x40400000
+#define IRAM0_CACHE_ADDRESS_LOW		0x40080000
+#define IRAM0_CACHE_ADDRESS_HIGH	0x40400000
+
+/*IRAM1 and AHB_IBUS1 connected with Cache IBUS1, alternative*/
+#define IRAM1_ADDRESS_LOW		0x40400000
+#define IRAM1_ADDRESS_HIGH		0x40800000
+#define AHB_IBUS1_ADDRESS_LOW		0x60400000
+#define AHB_IBUS1_ADDRESS_HIGH		0x60800000
+
+/*IROM0 and AHB_IBUS2 connected with Cache IBUS2, alternative*/
+#define IROM0_ADDRESS_LOW		0x40800000
+#define IROM0_ADDRESS_HIGH		0x40c00000
+#define AHB_IBUS2_ADDRESS_LOW		0x60800000
+#define AHB_IBUS2_ADDRESS_HIGH		0x60c00000
+
+/*DROM0 and AHB_IBUS2 connected with Cache IBUS3, alternative*/
+/*DROM0 and AHB_DBUS2 connected with Cache DBUS3, alternative*/
+#define DROM0_ADDRESS_LOW		0x3f000000
+#define DROM0_ADDRESS_HIGH		0x3f400000
+#define AHB_IBUS3_ADDRESS_LOW		0x60c00000
+#define AHB_IBUS3_ADDRESS_HIGH		0x61000000
+#define AHB_DBUS3_ADDRESS_LOW		0x61800000
+#define AHB_DBUS3_ADDRESS_HIGH		0x61c00000
+
+/*DRAM0 and AHB_DBUS2 connected with Cache DBUS0, alternative*/
+#define DRAM0_ADDRESS_LOW       	0x3fc00000
+#define DRAM0_ADDRESS_HIGH      	0x40000000
+#define DRAM0_CACHE_ADDRESS_LOW       	0x3fc00000
+#define DRAM0_CACHE_ADDRESS_HIGH      	0x3ff90000
+#define AHB_DBUS0_ADDRESS_LOW		0x61000000
+#define AHB_DBUS0_ADDRESS_HIGH		0x61400000
+
+/*DRAM1 connected with Cache DBUS1*/
+#define DRAM1_ADDRESS_LOW       	0x3f800000
+#define DRAM1_ADDRESS_HIGH      	0x3fc00000
+
+/*DPORT and AHB_DBUS2 connected with Cache DBUS2, alternative*/
+#define DPORT_ADDRESS_LOW       	0x3f400000
+#define DPORT_ADDRESS_HIGH      	0x3f800000
+#define DPORT_CACHE_ADDRESS_LOW       	0x3f500000
+#define DPORT_CACHE_ADDRESS_HIGH      	0x3f800000
+#define AHB_DBUS2_ADDRESS_LOW		0x61400000
+#define AHB_DBUS2_ADDRESS_HIGH		0x61800000
+
+#define BUS_SIZE(bus_name)                 (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
+#define ADDRESS_IN_BUS(bus_name, vaddr)    ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
+
+#define ADDRESS_IN_IRAM0(vaddr)            ADDRESS_IN_BUS(IRAM0, vaddr)
+#define ADDRESS_IN_IRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
+#define ADDRESS_IN_IRAM1(vaddr)            ADDRESS_IN_BUS(IRAM1, vaddr)
+#define ADDRESS_IN_AHB_IBUS1(vaddr)        ADDRESS_IN_BUS(AHB_IBUS1, vaddr)
+#define ADDRESS_IN_IROM0(vaddr)            ADDRESS_IN_BUS(IROM0, vaddr)
+#define ADDRESS_IN_AHB_IBUS2(vaddr)        ADDRESS_IN_BUS(AHB_IBUS2, vaddr)
+#define ADDRESS_IN_DROM0(vaddr)            ADDRESS_IN_BUS(DROM0, vaddr)
+#define ADDRESS_IN_AHB_IBUS3(vaddr)        ADDRESS_IN_BUS(AHB_IBUS3, vaddr)
+#define ADDRESS_IN_AHB_DBUS3(vaddr)        ADDRESS_IN_BUS(AHB_DBUS3, vaddr)
+#define ADDRESS_IN_DRAM0(vaddr)            ADDRESS_IN_BUS(DRAM0, vaddr)
+#define ADDRESS_IN_DRAM0_CACHE(vaddr)      ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
+#define ADDRESS_IN_AHB_DBUS0(vaddr)        ADDRESS_IN_BUS(AHB_DBUS0, vaddr)
+#define ADDRESS_IN_DRAM1(vaddr)            ADDRESS_IN_BUS(DRAM1, vaddr)
+#define ADDRESS_IN_DPORT(vaddr)            ADDRESS_IN_BUS(DPORT, vaddr)
+#define ADDRESS_IN_DPORT_CACHE(vaddr)      ADDRESS_IN_BUS(DPORT_CACHE, vaddr)
+#define ADDRESS_IN_AHB_DBUS2(vaddr)        ADDRESS_IN_BUS(AHB_DBUS2, vaddr)
+
+#define BUS_IRAM0_CACHE_SIZE              BUS_SIZE(IRAM0_CACHE)
+#define BUS_IRAM1_CACHE_SIZE              BUS_SIZE(IRAM1)
+#define BUS_IROM0_CACHE_SIZE              BUS_SIZE(IROM0)
+#define BUS_DROM0_CACHE_SIZE              BUS_SIZE(DROM0)
+#define BUS_DRAM0_CACHE_SIZE              BUS_SIZE(DRAM0_CACHE)
+#define BUS_DRAM1_CACHE_SIZE              BUS_SIZE(DRAM1)
+#define BUS_DPORT_CACHE_SIZE              BUS_SIZE(DPORT)
+
+#define BUS_AHB_IBUS1_CACHE_SIZE          BUS_SIZE(AHB_IBUS1)
+#define BUS_AHB_IBUS2_CACHE_SIZE          BUS_SIZE(AHB_IBUS2)
+#define BUS_AHB_IBUS3_CACHE_SIZE          BUS_SIZE(AHB_IBUS3)
+#define BUS_AHB_DBUS0_CACHE_SIZE          BUS_SIZE(AHB_DBUS0)
+#define BUS_AHB_DBUS2_CACHE_SIZE          BUS_SIZE(AHB_DBUS2)
+#define BUS_AHB_DBUS3_CACHE_SIZE          BUS_SIZE(AHB_DBUS3)
+
+
+
+#define PRO_CACHE_IBUS0			0
+#define PRO_CACHE_IBUS0_MMU_START 	0
+#define PRO_CACHE_IBUS0_MMU_END 	0x100
+
+#define PRO_CACHE_IBUS1			1
+#define PRO_CACHE_IBUS1_MMU_START	0x100
+#define PRO_CACHE_IBUS1_MMU_END		0x200
+
+#define PRO_CACHE_IBUS2			2
+#define PRO_CACHE_IBUS2_MMU_START	0x200
+#define PRO_CACHE_IBUS2_MMU_END		0x300
+
+#define PRO_CACHE_IBUS3			3
+#define PRO_CACHE_IBUS3_MMU_START	0x300
+#define PRO_CACHE_IBUS3_MMU_END		0x400
+
+#define PRO_CACHE_DBUS0			4
+#define PRO_CACHE_DBUS0_MMU_START	0x400
+#define PRO_CACHE_DBUS0_MMU_END		0x500
+
+#define PRO_CACHE_DBUS1			5
+#define PRO_CACHE_DBUS1_MMU_START	0x500
+#define PRO_CACHE_DBUS1_MMU_END		0x600
+
+#define PRO_CACHE_DBUS2			6
+#define PRO_CACHE_DBUS2_MMU_START	0x600
+#define PRO_CACHE_DBUS2_MMU_END		0x700
+
+#define PRO_CACHE_DBUS3			7
+#define PRO_CACHE_DBUS3_MMU_START	0x700
+#define PRO_CACHE_DBUS3_MMU_END		0x800
+
+#define DPORT_MMU_SIZE			0x800
+#define DPORT_ICACHE_MMU_SIZE		0x400
+#define DPORT_DCACHE_MMU_SIZE		0x400
+
+#define DPORT_MMU_BUS_START(i)		((i) * 0x100)
+#define DPORT_MMU_BUS_SIZE		0x100
+
+#define DPORT_MMU_INVALID		BIT(14)
+#define DPORT_MMU_ACCESS_FLASH		BIT(15)
+#define DPORT_MMU_ACCESS_SPIRAM		BIT(16)
+
+/* Flash MMU table for PRO CPU */
+#define DPORT_PRO_FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
+
+#define DPORT_FLASH_MMU_TABLE_SIZE (DPORT_ICACHE_MMU_SIZE/sizeof(uint32_t))
+
+#define DPORT_MMU_TABLE_INVALID_VAL 0x4000
+#define DPORT_FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
+#define DPORT_MMU_ADDRESS_MASK 0x3fff
+
+#define BUS_ADDR_SIZE 0x400000
+#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
+#define BUS_NUM_MASK  0x3
+
+#define CACHE_MEMORY_BLOCK_SIZE         8192
+#define CACHE_MEMORY_BLOCK_NUM          4
+#define CACHE_MEMORY_BLOCK_NUM_MASK     0x3
+#define CACHE_MEMORY_LAYOUT_SHIFT       4
+#define CACHE_MEMORY_LAYOUT_SHIFT0      0
+#define CACHE_MEMORY_LAYOUT_SHIFT1      4
+#define CACHE_MEMORY_LAYOUT_SHIFT2      8
+#define CACHE_MEMORY_LAYOUT_SHIFT3      12
+#define CACHE_MEMORY_LAYOUT_MASK        0xf
+#define CACHE_MEMORY_BLOCK0_ADDR        0x40020000
+#define CACHE_MEMORY_BLOCK1_ADDR        0x40022000
+#define CACHE_MEMORY_BLOCK2_ADDR        0x40024000
+#define CACHE_MEMORY_BLOCK3_ADDR        0x40026000
+
+#define DPORT_DATE_REG SYSTEM_DATE_REG
+
+#ifndef __ASSEMBLER__
+#include "dport_access.h"
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_SOC_DPORT_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/efuse_reg.h b/components/soc/esp32s2beta/include/soc/efuse_reg.h
new file mode 100644
index 000000000..b208fa965
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/efuse_reg.h
@@ -0,0 +1,2122 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_EFUSE_REG_H_
+#define _SOC_EFUSE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define EFUSE_PGM_DATA0_REG          (DR_REG_EFUSE_BASE + 0x000)
+/* EFUSE_WR_DIS : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define EFUSE_WR_DIS  0xFFFFFFFF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_PGM_DATA1_REG          (DR_REG_EFUSE_BASE + 0x004)
+/* EFUSE_SDIO_DREFH : R/W ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFH  0x00000003
+#define EFUSE_SDIO_DREFH_M  ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S))
+#define EFUSE_SDIO_DREFH_V  0x3
+#define EFUSE_SDIO_DREFH_S  30
+/* EFUSE_SDIO_MODECURLIM : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_MODECURLIM  (BIT(29))
+#define EFUSE_SDIO_MODECURLIM_M  (BIT(29))
+#define EFUSE_SDIO_MODECURLIM_V  0x1
+#define EFUSE_SDIO_MODECURLIM_S  29
+/* EFUSE_USB_DRES : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_USB_DRES  0x00000003
+#define EFUSE_USB_DRES_M  ((EFUSE_USB_DRES_V)<<(EFUSE_USB_DRES_S))
+#define EFUSE_USB_DRES_V  0x3
+#define EFUSE_USB_DRES_S  27
+/* EFUSE_USB_FORCE_B : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_USB_FORCE_B  (BIT(26))
+#define EFUSE_USB_FORCE_B_M  (BIT(26))
+#define EFUSE_USB_FORCE_B_V  0x1
+#define EFUSE_USB_FORCE_B_S  26
+/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_USB_EXT_PHY_ENABLE  (BIT(25))
+#define EFUSE_USB_EXT_PHY_ENABLE_M  (BIT(25))
+#define EFUSE_USB_EXT_PHY_ENABLE_V  0x1
+#define EFUSE_USB_EXT_PHY_ENABLE_S  25
+/* EFUSE_USB_EXCHG_PINS : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_USB_EXCHG_PINS  (BIT(24))
+#define EFUSE_USB_EXCHG_PINS_M  (BIT(24))
+#define EFUSE_USB_EXCHG_PINS_V  0x1
+#define EFUSE_USB_EXCHG_PINS_S  24
+/* EFUSE_USB_DREFL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_USB_DREFL  0x00000003
+#define EFUSE_USB_DREFL_M  ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S))
+#define EFUSE_USB_DREFL_V  0x3
+#define EFUSE_USB_DREFL_S  22
+/* EFUSE_USB_DREFH : R/W ;bitpos:[21:20] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_USB_DREFH  0x00000003
+#define EFUSE_USB_DREFH_M  ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S))
+#define EFUSE_USB_DREFH_V  0x3
+#define EFUSE_USB_DREFH_S  20
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT  (BIT(19))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(19))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  19
+/* EFUSE_HARD_DIS_JTAG : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_HARD_DIS_JTAG  (BIT(18))
+#define EFUSE_HARD_DIS_JTAG_M  (BIT(18))
+#define EFUSE_HARD_DIS_JTAG_V  0x1
+#define EFUSE_HARD_DIS_JTAG_S  18
+/* EFUSE_SOFT_DIS_JTAG : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SOFT_DIS_JTAG  (BIT(17))
+#define EFUSE_SOFT_DIS_JTAG_M  (BIT(17))
+#define EFUSE_SOFT_DIS_JTAG_V  0x1
+#define EFUSE_SOFT_DIS_JTAG_S  17
+/* EFUSE_DIS_EFUSE_ATE_WR : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_EFUSE_ATE_WR  (BIT(16))
+#define EFUSE_DIS_EFUSE_ATE_WR_M  (BIT(16))
+#define EFUSE_DIS_EFUSE_ATE_WR_V  0x1
+#define EFUSE_DIS_EFUSE_ATE_WR_S  16
+/* EFUSE_DIS_SDIO_ACCESS : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_SDIO_ACCESS  (BIT(15))
+#define EFUSE_DIS_SDIO_ACCESS_M  (BIT(15))
+#define EFUSE_DIS_SDIO_ACCESS_V  0x1
+#define EFUSE_DIS_SDIO_ACCESS_S  15
+/* EFUSE_DIS_CAN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_CAN  (BIT(14))
+#define EFUSE_DIS_CAN_M  (BIT(14))
+#define EFUSE_DIS_CAN_V  0x1
+#define EFUSE_DIS_CAN_S  14
+/* EFUSE_DIS_USB : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_USB  (BIT(13))
+#define EFUSE_DIS_USB_M  (BIT(13))
+#define EFUSE_DIS_USB_V  0x1
+#define EFUSE_DIS_USB_S  13
+/* EFUSE_DIS_BT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_BT  (BIT(12))
+#define EFUSE_DIS_BT_M  (BIT(12))
+#define EFUSE_DIS_BT_V  0x1
+#define EFUSE_DIS_BT_S  12
+/* EFUSE_DIS_DOWNLOAD_DCACHE : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_DCACHE  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_M  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_DCACHE_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_ICACHE  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/* EFUSE_DIS_DCACHE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DCACHE  (BIT(9))
+#define EFUSE_DIS_DCACHE_M  (BIT(9))
+#define EFUSE_DIS_DCACHE_V  0x1
+#define EFUSE_DIS_DCACHE_S  9
+/* EFUSE_DIS_ICACHE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_ICACHE  (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_V  0x1
+#define EFUSE_DIS_ICACHE_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_RTC_RAM_BOOT  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/* EFUSE_RD_DIS : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: */
+#define EFUSE_RD_DIS  0x0000007F
+#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V  0x7F
+#define EFUSE_RD_DIS_S  0
+
+#define EFUSE_PGM_DATA2_REG          (DR_REG_EFUSE_BASE + 0x008)
+/* EFUSE_KEY_PURPOSE_1 : R/W ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_1  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
+#define EFUSE_KEY_PURPOSE_1_V  0xF
+#define EFUSE_KEY_PURPOSE_1_S  28
+/* EFUSE_KEY_PURPOSE_0 : R/W ;bitpos:[27:24] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_0  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
+#define EFUSE_KEY_PURPOSE_0_V  0xF
+#define EFUSE_KEY_PURPOSE_0_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT : R/W ;bitpos:[20:18] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_SPI_BOOT_CRYPT_CNT  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/* EFUSE_WDT_DELAY_SEL : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_WDT_DELAY_SEL  0x00000003
+#define EFUSE_WDT_DELAY_SEL_M  ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
+#define EFUSE_WDT_DELAY_SEL_V  0x3
+#define EFUSE_WDT_DELAY_SEL_S  16
+/* EFUSE_SDIO_DCAP : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DCAP  0x00000003
+#define EFUSE_SDIO_DCAP_M  ((EFUSE_SDIO_DCAP_V)<<(EFUSE_SDIO_DCAP_S))
+#define EFUSE_SDIO_DCAP_V  0x3
+#define EFUSE_SDIO_DCAP_S  14
+/* EFUSE_SDIO_INIT : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_INIT  0x00000003
+#define EFUSE_SDIO_INIT_M  ((EFUSE_SDIO_INIT_V)<<(EFUSE_SDIO_INIT_S))
+#define EFUSE_SDIO_INIT_V  0x3
+#define EFUSE_SDIO_INIT_S  12
+/* EFUSE_SDIO_DCURLIM : R/W ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DCURLIM  0x00000007
+#define EFUSE_SDIO_DCURLIM_M  ((EFUSE_SDIO_DCURLIM_V)<<(EFUSE_SDIO_DCURLIM_S))
+#define EFUSE_SDIO_DCURLIM_V  0x7
+#define EFUSE_SDIO_DCURLIM_S  9
+/* EFUSE_SDIO_ENCURLIM : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_ENCURLIM  (BIT(8))
+#define EFUSE_SDIO_ENCURLIM_M  (BIT(8))
+#define EFUSE_SDIO_ENCURLIM_V  0x1
+#define EFUSE_SDIO_ENCURLIM_S  8
+/* EFUSE_SDIO_EN_INIT : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_EN_INIT  (BIT(7))
+#define EFUSE_SDIO_EN_INIT_M  (BIT(7))
+#define EFUSE_SDIO_EN_INIT_V  0x1
+#define EFUSE_SDIO_EN_INIT_S  7
+/* EFUSE_SDIO_FORCE : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_FORCE  (BIT(6))
+#define EFUSE_SDIO_FORCE_M  (BIT(6))
+#define EFUSE_SDIO_FORCE_V  0x1
+#define EFUSE_SDIO_FORCE_S  6
+/* EFUSE_SDIO_TIEH : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_TIEH  (BIT(5))
+#define EFUSE_SDIO_TIEH_M  (BIT(5))
+#define EFUSE_SDIO_TIEH_V  0x1
+#define EFUSE_SDIO_TIEH_S  5
+/* EFUSE_SDIO_XPD : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_XPD  (BIT(4))
+#define EFUSE_SDIO_XPD_M  (BIT(4))
+#define EFUSE_SDIO_XPD_V  0x1
+#define EFUSE_SDIO_XPD_S  4
+/* EFUSE_SDIO_DREFL : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFL  0x00000003
+#define EFUSE_SDIO_DREFL_M  ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S))
+#define EFUSE_SDIO_DREFL_V  0x3
+#define EFUSE_SDIO_DREFL_S  2
+/* EFUSE_SDIO_DREFM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFM  0x00000003
+#define EFUSE_SDIO_DREFM_M  ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S))
+#define EFUSE_SDIO_DREFM_V  0x3
+#define EFUSE_SDIO_DREFM_S  0
+
+#define EFUSE_PGM_DATA3_REG          (DR_REG_EFUSE_BASE + 0x00c)
+/* EFUSE_FLASH_TPUW : R/W ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_FLASH_TPUW  0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  28
+/* EFUSE_XTAL_FREQ : R/W ;bitpos:[27:22] ;default: 6'b0 ; */
+/*description: */
+#define EFUSE_XTAL_FREQ  0x0000003F
+#define EFUSE_XTAL_FREQ_M  ((EFUSE_XTAL_FREQ_V)<<(EFUSE_XTAL_FREQ_S))
+#define EFUSE_XTAL_FREQ_V  0x3F
+#define EFUSE_XTAL_FREQ_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/* EFUSE_SECURE_BOOT_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_EN  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  20
+/* EFUSE_KEY_PURPOSE_6 : R/W ;bitpos:[19:16] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_6  0x0000000F
+#define EFUSE_KEY_PURPOSE_6_M  ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S))
+#define EFUSE_KEY_PURPOSE_6_V  0xF
+#define EFUSE_KEY_PURPOSE_6_S  16
+/* EFUSE_KEY_PURPOSE_5 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_5  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
+#define EFUSE_KEY_PURPOSE_5_V  0xF
+#define EFUSE_KEY_PURPOSE_5_S  12
+/* EFUSE_KEY_PURPOSE_4 : R/W ;bitpos:[11:8] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_4  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
+#define EFUSE_KEY_PURPOSE_4_V  0xF
+#define EFUSE_KEY_PURPOSE_4_S  8
+/* EFUSE_KEY_PURPOSE_3 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_3  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
+#define EFUSE_KEY_PURPOSE_3_V  0xF
+#define EFUSE_KEY_PURPOSE_3_S  4
+/* EFUSE_KEY_PURPOSE_2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_2  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
+#define EFUSE_KEY_PURPOSE_2_V  0xF
+#define EFUSE_KEY_PURPOSE_2_S  0
+
+#define EFUSE_PGM_DATA4_REG          (DR_REG_EFUSE_BASE + 0x010)
+/* EFUSE_RESERVE : R/W ;bitpos:[31:8] ;default: 24'h0 ; */
+/*description: */
+#define EFUSE_RESERVE  0x00FFFFFF
+#define EFUSE_RESERVE_M  ((EFUSE_RESERVE_V)<<(EFUSE_RESERVE_S))
+#define EFUSE_RESERVE_V  0xFFFFFF
+#define EFUSE_RESERVE_S  8
+/* EFUSE_UART_PRINT_CONTROL : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_UART_PRINT_CONTROL  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_USB_DOWNLOAD_MODE  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S  4
+/* EFUSE_DIS_TINY_BASIC : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_TINY_BASIC  (BIT(3))
+#define EFUSE_DIS_TINY_BASIC_M  (BIT(3))
+#define EFUSE_DIS_TINY_BASIC_V  0x1
+#define EFUSE_DIS_TINY_BASIC_S  3
+/* EFUSE_UART_PRINT_CHANNEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_UART_PRINT_CHANNEL  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_LEGACY_SPI_BOOT  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_MODE  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+
+#define EFUSE_PGM_DATA5_REG          (DR_REG_EFUSE_BASE + 0x014)
+/* EFUSE_RS_DATA_23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define EFUSE_RS_DATA_23  0x000000FF
+#define EFUSE_RS_DATA_23_M  ((EFUSE_RS_DATA_23_V)<<(EFUSE_RS_DATA_23_S))
+#define EFUSE_RS_DATA_23_V  0xFF
+#define EFUSE_RS_DATA_23_S  24
+/* EFUSE_CHIP_VERSION : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VERSION  0x00FFFFFF
+#define EFUSE_CHIP_VERSION_M  ((EFUSE_CHIP_VERSION_V)<<(EFUSE_CHIP_VERSION_S))
+#define EFUSE_CHIP_VERSION_V  0xFFFFFF
+#define EFUSE_CHIP_VERSION_S  0
+
+#define EFUSE_PGM_DATA6_REG          (DR_REG_EFUSE_BASE + 0x018)
+/* EFUSE_RS_DATA_24_27 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_RS_DATA_24_27  0xFFFFFFFF
+#define EFUSE_RS_DATA_24_27_M  ((EFUSE_RS_DATA_24_27_V)<<(EFUSE_RS_DATA_24_27_S))
+#define EFUSE_RS_DATA_24_27_V  0xFFFFFFFF
+#define EFUSE_RS_DATA_24_27_S  0
+
+#define EFUSE_PGM_DATA7_REG          (DR_REG_EFUSE_BASE + 0x01c)
+/* EFUSE_RS_DATA_28_31 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_RS_DATA_28_31  0xFFFFFFFF
+#define EFUSE_RS_DATA_28_31_M  ((EFUSE_RS_DATA_28_31_V)<<(EFUSE_RS_DATA_28_31_S))
+#define EFUSE_RS_DATA_28_31_V  0xFFFFFFFF
+#define EFUSE_RS_DATA_28_31_S  0
+
+#define EFUSE_PGM_CHECK_VALUE0_REG          (DR_REG_EFUSE_BASE + 0x020)
+/* EFUSE_RS_DATA_32_35 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_RS_DATA_32_35  0xFFFFFFFF
+#define EFUSE_RS_DATA_32_35_M  ((EFUSE_RS_DATA_32_35_V)<<(EFUSE_RS_DATA_32_35_S))
+#define EFUSE_RS_DATA_32_35_V  0xFFFFFFFF
+#define EFUSE_RS_DATA_32_35_S  0
+
+#define EFUSE_PGM_CHECK_VALUE1_REG          (DR_REG_EFUSE_BASE + 0x024)
+/* EFUSE_RS_DATA_36_39 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_RS_DATA_36_39  0xFFFFFFFF
+#define EFUSE_RS_DATA_36_39_M  ((EFUSE_RS_DATA_36_39_V)<<(EFUSE_RS_DATA_36_39_S))
+#define EFUSE_RS_DATA_36_39_V  0xFFFFFFFF
+#define EFUSE_RS_DATA_36_39_S  0
+
+#define EFUSE_PGM_CHECK_VALUE2_REG          (DR_REG_EFUSE_BASE + 0x028)
+/* EFUSE_RS_DATA_40_43 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_RS_DATA_40_43  0xFFFFFFFF
+#define EFUSE_RS_DATA_40_43_M  ((EFUSE_RS_DATA_40_43_V)<<(EFUSE_RS_DATA_40_43_S))
+#define EFUSE_RS_DATA_40_43_V  0xFFFFFFFF
+#define EFUSE_RS_DATA_40_43_S  0
+
+#define EFUSE_RD_WR_DIS_REG          (DR_REG_EFUSE_BASE + 0x02c)
+/* EFUSE_WR_DIS : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define EFUSE_WR_DIS  0xFFFFFFFF
+#define EFUSE_WR_DIS_M  ((EFUSE_WR_DIS_V)<<(EFUSE_WR_DIS_S))
+#define EFUSE_WR_DIS_V  0xFFFFFFFF
+#define EFUSE_WR_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA0_REG          (DR_REG_EFUSE_BASE + 0x030)
+/* EFUSE_SDIO_DREFH : RO ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFH  0x00000003
+#define EFUSE_SDIO_DREFH_M  ((EFUSE_SDIO_DREFH_V)<<(EFUSE_SDIO_DREFH_S))
+#define EFUSE_SDIO_DREFH_V  0x3
+#define EFUSE_SDIO_DREFH_S  30
+/* EFUSE_SDIO_MODECURLIM : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_MODECURLIM  (BIT(29))
+#define EFUSE_SDIO_MODECURLIM_M  (BIT(29))
+#define EFUSE_SDIO_MODECURLIM_V  0x1
+#define EFUSE_SDIO_MODECURLIM_S  29
+/* EFUSE_USB_DRES : RO ;bitpos:[28:27] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_USB_DRES  0x00000003
+#define EFUSE_USB_DRES_M  ((EFUSE_USB_DRES_V)<<(EFUSE_USB_DRES_S))
+#define EFUSE_USB_DRES_V  0x3
+#define EFUSE_USB_DRES_S  27
+/* EFUSE_USB_FORCE_B : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_USB_FORCE_B  (BIT(26))
+#define EFUSE_USB_FORCE_B_M  (BIT(26))
+#define EFUSE_USB_FORCE_B_V  0x1
+#define EFUSE_USB_FORCE_B_S  26
+/* EFUSE_USB_EXT_PHY_ENABLE : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_USB_EXT_PHY_ENABLE  (BIT(25))
+#define EFUSE_USB_EXT_PHY_ENABLE_M  (BIT(25))
+#define EFUSE_USB_EXT_PHY_ENABLE_V  0x1
+#define EFUSE_USB_EXT_PHY_ENABLE_S  25
+/* EFUSE_USB_EXCHG_PINS : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_USB_EXCHG_PINS  (BIT(24))
+#define EFUSE_USB_EXCHG_PINS_M  (BIT(24))
+#define EFUSE_USB_EXCHG_PINS_V  0x1
+#define EFUSE_USB_EXCHG_PINS_S  24
+/* EFUSE_USB_DREFL : RO ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_USB_DREFL  0x00000003
+#define EFUSE_USB_DREFL_M  ((EFUSE_USB_DREFL_V)<<(EFUSE_USB_DREFL_S))
+#define EFUSE_USB_DREFL_V  0x3
+#define EFUSE_USB_DREFL_S  22
+/* EFUSE_USB_DREFH : RO ;bitpos:[21:20] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_USB_DREFH  0x00000003
+#define EFUSE_USB_DREFH_M  ((EFUSE_USB_DREFH_V)<<(EFUSE_USB_DREFH_S))
+#define EFUSE_USB_DREFH_V  0x3
+#define EFUSE_USB_DREFH_S  20
+/* EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT  (BIT(19))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(19))
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MANUAL_ENCRYPT_S  19
+/* EFUSE_HARD_DIS_JTAG : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_HARD_DIS_JTAG  (BIT(18))
+#define EFUSE_HARD_DIS_JTAG_M  (BIT(18))
+#define EFUSE_HARD_DIS_JTAG_V  0x1
+#define EFUSE_HARD_DIS_JTAG_S  18
+/* EFUSE_SOFT_DIS_JTAG : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SOFT_DIS_JTAG  (BIT(17))
+#define EFUSE_SOFT_DIS_JTAG_M  (BIT(17))
+#define EFUSE_SOFT_DIS_JTAG_V  0x1
+#define EFUSE_SOFT_DIS_JTAG_S  17
+/* EFUSE_DIS_EFUSE_ATE_WR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_EFUSE_ATE_WR  (BIT(16))
+#define EFUSE_DIS_EFUSE_ATE_WR_M  (BIT(16))
+#define EFUSE_DIS_EFUSE_ATE_WR_V  0x1
+#define EFUSE_DIS_EFUSE_ATE_WR_S  16
+/* EFUSE_DIS_SDIO_ACCESS : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_SDIO_ACCESS  (BIT(15))
+#define EFUSE_DIS_SDIO_ACCESS_M  (BIT(15))
+#define EFUSE_DIS_SDIO_ACCESS_V  0x1
+#define EFUSE_DIS_SDIO_ACCESS_S  15
+/* EFUSE_DIS_CAN : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_CAN  (BIT(14))
+#define EFUSE_DIS_CAN_M  (BIT(14))
+#define EFUSE_DIS_CAN_V  0x1
+#define EFUSE_DIS_CAN_S  14
+/* EFUSE_DIS_USB : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_USB  (BIT(13))
+#define EFUSE_DIS_USB_M  (BIT(13))
+#define EFUSE_DIS_USB_V  0x1
+#define EFUSE_DIS_USB_S  13
+/* EFUSE_DIS_BT : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_BT  (BIT(12))
+#define EFUSE_DIS_BT_M  (BIT(12))
+#define EFUSE_DIS_BT_V  0x1
+#define EFUSE_DIS_BT_S  12
+/* EFUSE_DIS_DOWNLOAD_DCACHE : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_DCACHE  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_M  (BIT(11))
+#define EFUSE_DIS_DOWNLOAD_DCACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_DCACHE_S  11
+/* EFUSE_DIS_DOWNLOAD_ICACHE : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_ICACHE  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_M  (BIT(10))
+#define EFUSE_DIS_DOWNLOAD_ICACHE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_ICACHE_S  10
+/* EFUSE_DIS_DCACHE : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DCACHE  (BIT(9))
+#define EFUSE_DIS_DCACHE_M  (BIT(9))
+#define EFUSE_DIS_DCACHE_V  0x1
+#define EFUSE_DIS_DCACHE_S  9
+/* EFUSE_DIS_ICACHE : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_ICACHE  (BIT(8))
+#define EFUSE_DIS_ICACHE_M  (BIT(8))
+#define EFUSE_DIS_ICACHE_V  0x1
+#define EFUSE_DIS_ICACHE_S  8
+/* EFUSE_DIS_RTC_RAM_BOOT : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_RTC_RAM_BOOT  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_M  (BIT(7))
+#define EFUSE_DIS_RTC_RAM_BOOT_V  0x1
+#define EFUSE_DIS_RTC_RAM_BOOT_S  7
+/* EFUSE_RD_DIS : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: */
+#define EFUSE_RD_DIS  0x0000007F
+#define EFUSE_RD_DIS_M  ((EFUSE_RD_DIS_V)<<(EFUSE_RD_DIS_S))
+#define EFUSE_RD_DIS_V  0x7F
+#define EFUSE_RD_DIS_S  0
+
+#define EFUSE_RD_REPEAT_DATA1_REG          (DR_REG_EFUSE_BASE + 0x034)
+/* EFUSE_KEY_PURPOSE_1 : RO ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_1  0x0000000F
+#define EFUSE_KEY_PURPOSE_1_M  ((EFUSE_KEY_PURPOSE_1_V)<<(EFUSE_KEY_PURPOSE_1_S))
+#define EFUSE_KEY_PURPOSE_1_V  0xF
+#define EFUSE_KEY_PURPOSE_1_S  28
+/* EFUSE_KEY_PURPOSE_0 : RO ;bitpos:[27:24] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_0  0x0000000F
+#define EFUSE_KEY_PURPOSE_0_M  ((EFUSE_KEY_PURPOSE_0_V)<<(EFUSE_KEY_PURPOSE_0_S))
+#define EFUSE_KEY_PURPOSE_0_V  0xF
+#define EFUSE_KEY_PURPOSE_0_S  24
+/* EFUSE_SECURE_BOOT_KEY_REVOKE2 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_M  (BIT(23))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE2_S  23
+/* EFUSE_SECURE_BOOT_KEY_REVOKE1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_M  (BIT(22))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE1_S  22
+/* EFUSE_SECURE_BOOT_KEY_REVOKE0 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_V  0x1
+#define EFUSE_SECURE_BOOT_KEY_REVOKE0_S  21
+/* EFUSE_SPI_BOOT_CRYPT_CNT : RO ;bitpos:[20:18] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_SPI_BOOT_CRYPT_CNT  0x00000007
+#define EFUSE_SPI_BOOT_CRYPT_CNT_M  ((EFUSE_SPI_BOOT_CRYPT_CNT_V)<<(EFUSE_SPI_BOOT_CRYPT_CNT_S))
+#define EFUSE_SPI_BOOT_CRYPT_CNT_V  0x7
+#define EFUSE_SPI_BOOT_CRYPT_CNT_S  18
+/* EFUSE_WDT_DELAY_SEL : RO ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_WDT_DELAY_SEL  0x00000003
+#define EFUSE_WDT_DELAY_SEL_M  ((EFUSE_WDT_DELAY_SEL_V)<<(EFUSE_WDT_DELAY_SEL_S))
+#define EFUSE_WDT_DELAY_SEL_V  0x3
+#define EFUSE_WDT_DELAY_SEL_S  16
+/* EFUSE_EUFSE_SDIO_DCAP : RO ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_EUFSE_SDIO_DCAP  0x00000003
+#define EFUSE_EUFSE_SDIO_DCAP_M  ((EFUSE_EUFSE_SDIO_DCAP_V)<<(EFUSE_EUFSE_SDIO_DCAP_S))
+#define EFUSE_EUFSE_SDIO_DCAP_V  0x3
+#define EFUSE_EUFSE_SDIO_DCAP_S  14
+/* EFUSE_SDIO_INIT : RO ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_INIT  0x00000003
+#define EFUSE_SDIO_INIT_M  ((EFUSE_SDIO_INIT_V)<<(EFUSE_SDIO_INIT_S))
+#define EFUSE_SDIO_INIT_V  0x3
+#define EFUSE_SDIO_INIT_S  12
+/* EFUSE_SDIO_DCURLIM : RO ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DCURLIM  0x00000007
+#define EFUSE_SDIO_DCURLIM_M  ((EFUSE_SDIO_DCURLIM_V)<<(EFUSE_SDIO_DCURLIM_S))
+#define EFUSE_SDIO_DCURLIM_V  0x7
+#define EFUSE_SDIO_DCURLIM_S  9
+/* EFUSE_SDIO_ENCURLIM : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_ENCURLIM  (BIT(8))
+#define EFUSE_SDIO_ENCURLIM_M  (BIT(8))
+#define EFUSE_SDIO_ENCURLIM_V  0x1
+#define EFUSE_SDIO_ENCURLIM_S  8
+/* EFUSE_SDIO_EN_INIT : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_EN_INIT  (BIT(7))
+#define EFUSE_SDIO_EN_INIT_M  (BIT(7))
+#define EFUSE_SDIO_EN_INIT_V  0x1
+#define EFUSE_SDIO_EN_INIT_S  7
+/* EFUSE_SDIO_FORCE : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_FORCE  (BIT(6))
+#define EFUSE_SDIO_FORCE_M  (BIT(6))
+#define EFUSE_SDIO_FORCE_V  0x1
+#define EFUSE_SDIO_FORCE_S  6
+/* EFUSE_SDIO_TIEH : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_TIEH  (BIT(5))
+#define EFUSE_SDIO_TIEH_M  (BIT(5))
+#define EFUSE_SDIO_TIEH_V  0x1
+#define EFUSE_SDIO_TIEH_S  5
+/* EFUSE_SDIO_XPD : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SDIO_XPD  (BIT(4))
+#define EFUSE_SDIO_XPD_M  (BIT(4))
+#define EFUSE_SDIO_XPD_V  0x1
+#define EFUSE_SDIO_XPD_S  4
+/* EFUSE_SDIO_DREFL : RO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFL  0x00000003
+#define EFUSE_SDIO_DREFL_M  ((EFUSE_SDIO_DREFL_V)<<(EFUSE_SDIO_DREFL_S))
+#define EFUSE_SDIO_DREFL_V  0x3
+#define EFUSE_SDIO_DREFL_S  2
+/* EFUSE_SDIO_DREFM : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_SDIO_DREFM  0x00000003
+#define EFUSE_SDIO_DREFM_M  ((EFUSE_SDIO_DREFM_V)<<(EFUSE_SDIO_DREFM_S))
+#define EFUSE_SDIO_DREFM_V  0x3
+#define EFUSE_SDIO_DREFM_S  0
+
+#define EFUSE_RD_REPEAT_DATA2_REG          (DR_REG_EFUSE_BASE + 0x038)
+/* EFUSE_FLASH_TPUW : RO ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_FLASH_TPUW  0x0000000F
+#define EFUSE_FLASH_TPUW_M  ((EFUSE_FLASH_TPUW_V)<<(EFUSE_FLASH_TPUW_S))
+#define EFUSE_FLASH_TPUW_V  0xF
+#define EFUSE_FLASH_TPUW_S  28
+/* EFUSE_XTAL_FREQ : RO ;bitpos:[27:22] ;default: 6'b0 ; */
+/*description: */
+#define EFUSE_XTAL_FREQ  0x0000003F
+#define EFUSE_XTAL_FREQ_M  ((EFUSE_XTAL_FREQ_V)<<(EFUSE_XTAL_FREQ_S))
+#define EFUSE_XTAL_FREQ_V  0x3F
+#define EFUSE_XTAL_FREQ_S  22
+/* EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_M  (BIT(21))
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_V  0x1
+#define EFUSE_SECURE_BOOT_AGGRESSIVE_REVOKE_S  21
+/* EFUSE_SECURE_BOOT_EN : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_SECURE_BOOT_EN  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_M  (BIT(20))
+#define EFUSE_SECURE_BOOT_EN_V  0x1
+#define EFUSE_SECURE_BOOT_EN_S  20
+/* EFUSE_KEY_PURPOSE_6 : RO ;bitpos:[19:16] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_6  0x0000000F
+#define EFUSE_KEY_PURPOSE_6_M  ((EFUSE_KEY_PURPOSE_6_V)<<(EFUSE_KEY_PURPOSE_6_S))
+#define EFUSE_KEY_PURPOSE_6_V  0xF
+#define EFUSE_KEY_PURPOSE_6_S  16
+/* EFUSE_KEY_PURPOSE_5 : RO ;bitpos:[15:12] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_5  0x0000000F
+#define EFUSE_KEY_PURPOSE_5_M  ((EFUSE_KEY_PURPOSE_5_V)<<(EFUSE_KEY_PURPOSE_5_S))
+#define EFUSE_KEY_PURPOSE_5_V  0xF
+#define EFUSE_KEY_PURPOSE_5_S  12
+/* EFUSE_KEY_PURPOSE_4 : RO ;bitpos:[11:8] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_4  0x0000000F
+#define EFUSE_KEY_PURPOSE_4_M  ((EFUSE_KEY_PURPOSE_4_V)<<(EFUSE_KEY_PURPOSE_4_S))
+#define EFUSE_KEY_PURPOSE_4_V  0xF
+#define EFUSE_KEY_PURPOSE_4_S  8
+/* EFUSE_KEY_PURPOSE_3 : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_3  0x0000000F
+#define EFUSE_KEY_PURPOSE_3_M  ((EFUSE_KEY_PURPOSE_3_V)<<(EFUSE_KEY_PURPOSE_3_S))
+#define EFUSE_KEY_PURPOSE_3_V  0xF
+#define EFUSE_KEY_PURPOSE_3_S  4
+/* EFUSE_KEY_PURPOSE_2 : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_KEY_PURPOSE_2  0x0000000F
+#define EFUSE_KEY_PURPOSE_2_M  ((EFUSE_KEY_PURPOSE_2_V)<<(EFUSE_KEY_PURPOSE_2_S))
+#define EFUSE_KEY_PURPOSE_2_V  0xF
+#define EFUSE_KEY_PURPOSE_2_S  0
+
+#define EFUSE_RD_REPEAT_DATA3_REG          (DR_REG_EFUSE_BASE + 0x03c)
+/* EFUSE_RESERVE : RO ;bitpos:[31:8] ;default: 24'h0 ; */
+/*description: */
+#define EFUSE_RESERVE  0x00FFFFFF
+#define EFUSE_RESERVE_M  ((EFUSE_RESERVE_V)<<(EFUSE_RESERVE_S))
+#define EFUSE_RESERVE_V  0xFFFFFF
+#define EFUSE_RESERVE_S  8
+/* EFUSE_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_UART_PRINT_CONTROL  0x00000003
+#define EFUSE_UART_PRINT_CONTROL_M  ((EFUSE_UART_PRINT_CONTROL_V)<<(EFUSE_UART_PRINT_CONTROL_S))
+#define EFUSE_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_UART_PRINT_CONTROL_S  6
+/* EFUSE_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_USB_DOWNLOAD_MODE  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_USB_DOWNLOAD_MODE_S  4
+/* EFUSE_DIS_TINY_BASIC : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_TINY_BASIC  (BIT(3))
+#define EFUSE_DIS_TINY_BASIC_M  (BIT(3))
+#define EFUSE_DIS_TINY_BASIC_V  0x1
+#define EFUSE_DIS_TINY_BASIC_S  3
+/* EFUSE_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_UART_PRINT_CHANNEL  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_M  (BIT(2))
+#define EFUSE_UART_PRINT_CHANNEL_V  0x1
+#define EFUSE_UART_PRINT_CHANNEL_S  2
+/* EFUSE_DIS_LEGACY_SPI_BOOT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_LEGACY_SPI_BOOT  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_M  (BIT(1))
+#define EFUSE_DIS_LEGACY_SPI_BOOT_V  0x1
+#define EFUSE_DIS_LEGACY_SPI_BOOT_S  1
+/* EFUSE_DIS_DOWNLOAD_MODE : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DIS_DOWNLOAD_MODE  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_M  (BIT(0))
+#define EFUSE_DIS_DOWNLOAD_MODE_V  0x1
+#define EFUSE_DIS_DOWNLOAD_MODE_S  0
+
+#define EFUSE_RD_REPEAT_DATA4_REG          (DR_REG_EFUSE_BASE + 0x040)
+/* EFUSE_CHIP_VERSION : RO ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define EFUSE_CHIP_VERSION  0x00FFFFFF
+#define EFUSE_CHIP_VERSION_M  ((EFUSE_CHIP_VERSION_V)<<(EFUSE_CHIP_VERSION_S))
+#define EFUSE_CHIP_VERSION_V  0xFFFFFF
+#define EFUSE_CHIP_VERSION_S  0
+
+#define EFUSE_RD_MAC_SPI_8M_0_REG          (DR_REG_EFUSE_BASE + 0x044)
+/* EFUSE_MAC_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_MAC_0  0xFFFFFFFF
+#define EFUSE_MAC_0_M  ((EFUSE_MAC_0_V)<<(EFUSE_MAC_0_S))
+#define EFUSE_MAC_0_V  0xFFFFFFFF
+#define EFUSE_MAC_0_S  0
+
+#define EFUSE_RD_MAC_SPI_8M_1_REG          (DR_REG_EFUSE_BASE + 0x048)
+/* EFUSE_SPI_PAD_CONF_0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: */
+#define EFUSE_SPI_PAD_CONF_0  0x0000FFFF
+#define EFUSE_SPI_PAD_CONF_0_M  ((EFUSE_SPI_PAD_CONF_0_V)<<(EFUSE_SPI_PAD_CONF_0_S))
+#define EFUSE_SPI_PAD_CONF_0_V  0xFFFF
+#define EFUSE_SPI_PAD_CONF_0_S  16
+/* EFUSE_MAC_1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define EFUSE_MAC_1  0x0000FFFF
+#define EFUSE_MAC_1_M  ((EFUSE_MAC_1_V)<<(EFUSE_MAC_1_S))
+#define EFUSE_MAC_1_V  0xFFFF
+#define EFUSE_MAC_1_S  0
+
+#define EFUSE_RD_MAC_SPI_8M_2_REG          (DR_REG_EFUSE_BASE + 0x04c)
+/* EFUSE_CLK8M_FREQ : RO ;bitpos:[31:20] ;default: 12'h0 ; */
+/*description: */
+#define EFUSE_CLK8M_FREQ  0x00000FFF
+#define EFUSE_CLK8M_FREQ_M  ((EFUSE_CLK8M_FREQ_V)<<(EFUSE_CLK8M_FREQ_S))
+#define EFUSE_CLK8M_FREQ_V  0xFFF
+#define EFUSE_CLK8M_FREQ_S  20
+/* EFUSE_SPI_PAD_CONF_1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define EFUSE_SPI_PAD_CONF_1  0x000FFFFF
+#define EFUSE_SPI_PAD_CONF_1_M  ((EFUSE_SPI_PAD_CONF_1_V)<<(EFUSE_SPI_PAD_CONF_1_S))
+#define EFUSE_SPI_PAD_CONF_1_V  0xFFFFF
+#define EFUSE_SPI_PAD_CONF_1_S  0
+
+#define EFUSE_RD_MAC_SPI_8M_3_REG          (DR_REG_EFUSE_BASE + 0x050)
+/* EFUSE_SYS_DATA_PART0_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA_PART0_0  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_0_M  ((EFUSE_SYS_DATA_PART0_0_V)<<(EFUSE_SYS_DATA_PART0_0_S))
+#define EFUSE_SYS_DATA_PART0_0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_0_S  0
+
+#define EFUSE_RD_MAC_SPI_8M_4_REG          (DR_REG_EFUSE_BASE + 0x054)
+/* EFUSE_SYS_DATA_PART0_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA_PART0_1  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_M  ((EFUSE_SYS_DATA_PART0_1_V)<<(EFUSE_SYS_DATA_PART0_1_S))
+#define EFUSE_SYS_DATA_PART0_1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_1_S  0
+
+#define EFUSE_RD_MAC_SPI_8M_5_REG          (DR_REG_EFUSE_BASE + 0x058)
+/* EFUSE_SYS_DATA_PART0_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA_PART0_2  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_M  ((EFUSE_SYS_DATA_PART0_2_V)<<(EFUSE_SYS_DATA_PART0_2_S))
+#define EFUSE_SYS_DATA_PART0_2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA_PART0_2_S  0
+
+#define EFUSE_RD_SYS_DATA0_REG          (DR_REG_EFUSE_BASE + 0x05c)
+/* EFUSE_SYS_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA0  0xFFFFFFFF
+#define EFUSE_SYS_DATA0_M  ((EFUSE_SYS_DATA0_V)<<(EFUSE_SYS_DATA0_S))
+#define EFUSE_SYS_DATA0_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA0_S  0
+
+#define EFUSE_RD_SYS_DATA1_REG          (DR_REG_EFUSE_BASE + 0x060)
+/* EFUSE_SYS_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA1  0xFFFFFFFF
+#define EFUSE_SYS_DATA1_M  ((EFUSE_SYS_DATA1_V)<<(EFUSE_SYS_DATA1_S))
+#define EFUSE_SYS_DATA1_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA1_S  0
+
+#define EFUSE_RD_SYS_DATA2_REG          (DR_REG_EFUSE_BASE + 0x064)
+/* EFUSE_SYS_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA2  0xFFFFFFFF
+#define EFUSE_SYS_DATA2_M  ((EFUSE_SYS_DATA2_V)<<(EFUSE_SYS_DATA2_S))
+#define EFUSE_SYS_DATA2_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA2_S  0
+
+#define EFUSE_RD_SYS_DATA3_REG          (DR_REG_EFUSE_BASE + 0x068)
+/* EFUSE_SYS_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA3  0xFFFFFFFF
+#define EFUSE_SYS_DATA3_M  ((EFUSE_SYS_DATA3_V)<<(EFUSE_SYS_DATA3_S))
+#define EFUSE_SYS_DATA3_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA3_S  0
+
+#define EFUSE_RD_SYS_DATA4_REG          (DR_REG_EFUSE_BASE + 0x06c)
+/* EFUSE_SYS_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA4  0xFFFFFFFF
+#define EFUSE_SYS_DATA4_M  ((EFUSE_SYS_DATA4_V)<<(EFUSE_SYS_DATA4_S))
+#define EFUSE_SYS_DATA4_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA4_S  0
+
+#define EFUSE_RD_SYS_DATA5_REG          (DR_REG_EFUSE_BASE + 0x070)
+/* EFUSE_SYS_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA5  0xFFFFFFFF
+#define EFUSE_SYS_DATA5_M  ((EFUSE_SYS_DATA5_V)<<(EFUSE_SYS_DATA5_S))
+#define EFUSE_SYS_DATA5_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA5_S  0
+
+#define EFUSE_RD_SYS_DATA6_REG          (DR_REG_EFUSE_BASE + 0x074)
+/* EFUSE_SYS_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA6  0xFFFFFFFF
+#define EFUSE_SYS_DATA6_M  ((EFUSE_SYS_DATA6_V)<<(EFUSE_SYS_DATA6_S))
+#define EFUSE_SYS_DATA6_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA6_S  0
+
+#define EFUSE_RD_SYS_DATA7_REG          (DR_REG_EFUSE_BASE + 0x078)
+/* EFUSE_SYS_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_SYS_DATA7  0xFFFFFFFF
+#define EFUSE_SYS_DATA7_M  ((EFUSE_SYS_DATA7_V)<<(EFUSE_SYS_DATA7_S))
+#define EFUSE_SYS_DATA7_V  0xFFFFFFFF
+#define EFUSE_SYS_DATA7_S  0
+
+#define EFUSE_RD_USR_DATA0_REG          (DR_REG_EFUSE_BASE + 0x07c)
+/* EFUSE_USR_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA0  0xFFFFFFFF
+#define EFUSE_USR_DATA0_M  ((EFUSE_USR_DATA0_V)<<(EFUSE_USR_DATA0_S))
+#define EFUSE_USR_DATA0_V  0xFFFFFFFF
+#define EFUSE_USR_DATA0_S  0
+
+#define EFUSE_RD_USR_DATA1_REG          (DR_REG_EFUSE_BASE + 0x080)
+/* EFUSE_USR_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA1  0xFFFFFFFF
+#define EFUSE_USR_DATA1_M  ((EFUSE_USR_DATA1_V)<<(EFUSE_USR_DATA1_S))
+#define EFUSE_USR_DATA1_V  0xFFFFFFFF
+#define EFUSE_USR_DATA1_S  0
+
+#define EFUSE_RD_USR_DATA2_REG          (DR_REG_EFUSE_BASE + 0x084)
+/* EFUSE_USR_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA2  0xFFFFFFFF
+#define EFUSE_USR_DATA2_M  ((EFUSE_USR_DATA2_V)<<(EFUSE_USR_DATA2_S))
+#define EFUSE_USR_DATA2_V  0xFFFFFFFF
+#define EFUSE_USR_DATA2_S  0
+
+#define EFUSE_RD_USR_DATA3_REG          (DR_REG_EFUSE_BASE + 0x088)
+/* EFUSE_USR_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA3  0xFFFFFFFF
+#define EFUSE_USR_DATA3_M  ((EFUSE_USR_DATA3_V)<<(EFUSE_USR_DATA3_S))
+#define EFUSE_USR_DATA3_V  0xFFFFFFFF
+#define EFUSE_USR_DATA3_S  0
+
+#define EFUSE_RD_USR_DATA4_REG          (DR_REG_EFUSE_BASE + 0x08c)
+/* EFUSE_USR_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA4  0xFFFFFFFF
+#define EFUSE_USR_DATA4_M  ((EFUSE_USR_DATA4_V)<<(EFUSE_USR_DATA4_S))
+#define EFUSE_USR_DATA4_V  0xFFFFFFFF
+#define EFUSE_USR_DATA4_S  0
+
+#define EFUSE_RD_USR_DATA5_REG          (DR_REG_EFUSE_BASE + 0x090)
+/* EFUSE_USR_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA5  0xFFFFFFFF
+#define EFUSE_USR_DATA5_M  ((EFUSE_USR_DATA5_V)<<(EFUSE_USR_DATA5_S))
+#define EFUSE_USR_DATA5_V  0xFFFFFFFF
+#define EFUSE_USR_DATA5_S  0
+
+#define EFUSE_RD_USR_DATA6_REG          (DR_REG_EFUSE_BASE + 0x094)
+/* EFUSE_USR_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA6  0xFFFFFFFF
+#define EFUSE_USR_DATA6_M  ((EFUSE_USR_DATA6_V)<<(EFUSE_USR_DATA6_S))
+#define EFUSE_USR_DATA6_V  0xFFFFFFFF
+#define EFUSE_USR_DATA6_S  0
+
+#define EFUSE_RD_USR_DATA7_REG          (DR_REG_EFUSE_BASE + 0x098)
+/* EFUSE_USR_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_USR_DATA7  0xFFFFFFFF
+#define EFUSE_USR_DATA7_M  ((EFUSE_USR_DATA7_V)<<(EFUSE_USR_DATA7_S))
+#define EFUSE_USR_DATA7_V  0xFFFFFFFF
+#define EFUSE_USR_DATA7_S  0
+
+#define EFUSE_RD_KEY0_DATA0_REG          (DR_REG_EFUSE_BASE + 0x09c)
+/* EFUSE_KEY0_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA0  0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_M  ((EFUSE_KEY0_DATA0_V)<<(EFUSE_KEY0_DATA0_S))
+#define EFUSE_KEY0_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA0_S  0
+
+#define EFUSE_RD_KEY0_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0a0)
+/* EFUSE_KEY0_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA1  0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_M  ((EFUSE_KEY0_DATA1_V)<<(EFUSE_KEY0_DATA1_S))
+#define EFUSE_KEY0_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA1_S  0
+
+#define EFUSE_RD_KEY0_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0a4)
+/* EFUSE_KEY0_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA2  0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_M  ((EFUSE_KEY0_DATA2_V)<<(EFUSE_KEY0_DATA2_S))
+#define EFUSE_KEY0_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA2_S  0
+
+#define EFUSE_RD_KEY0_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0a8)
+/* EFUSE_KEY0_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA3  0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_M  ((EFUSE_KEY0_DATA3_V)<<(EFUSE_KEY0_DATA3_S))
+#define EFUSE_KEY0_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA3_S  0
+
+#define EFUSE_RD_KEY0_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0ac)
+/* EFUSE_KEY0_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA4  0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_M  ((EFUSE_KEY0_DATA4_V)<<(EFUSE_KEY0_DATA4_S))
+#define EFUSE_KEY0_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA4_S  0
+
+#define EFUSE_RD_KEY0_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0b0)
+/* EFUSE_KEY0_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA5  0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_M  ((EFUSE_KEY0_DATA5_V)<<(EFUSE_KEY0_DATA5_S))
+#define EFUSE_KEY0_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA5_S  0
+
+#define EFUSE_RD_KEY0_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0b4)
+/* EFUSE_KEY0_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA6  0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_M  ((EFUSE_KEY0_DATA6_V)<<(EFUSE_KEY0_DATA6_S))
+#define EFUSE_KEY0_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA6_S  0
+
+#define EFUSE_RD_KEY0_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0b8)
+/* EFUSE_KEY0_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY0_DATA7  0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_M  ((EFUSE_KEY0_DATA7_V)<<(EFUSE_KEY0_DATA7_S))
+#define EFUSE_KEY0_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY0_DATA7_S  0
+
+#define EFUSE_RD_KEY1_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0bc)
+/* EFUSE_KEY1_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA0  0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_M  ((EFUSE_KEY1_DATA0_V)<<(EFUSE_KEY1_DATA0_S))
+#define EFUSE_KEY1_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA0_S  0
+
+#define EFUSE_RD_KEY1_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0c0)
+/* EFUSE_KEY1_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA1  0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_M  ((EFUSE_KEY1_DATA1_V)<<(EFUSE_KEY1_DATA1_S))
+#define EFUSE_KEY1_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA1_S  0
+
+#define EFUSE_RD_KEY1_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0c4)
+/* EFUSE_KEY1_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA2  0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_M  ((EFUSE_KEY1_DATA2_V)<<(EFUSE_KEY1_DATA2_S))
+#define EFUSE_KEY1_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA2_S  0
+
+#define EFUSE_RD_KEY1_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0c8)
+/* EFUSE_KEY1_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA3  0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_M  ((EFUSE_KEY1_DATA3_V)<<(EFUSE_KEY1_DATA3_S))
+#define EFUSE_KEY1_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA3_S  0
+
+#define EFUSE_RD_KEY1_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0cc)
+/* EFUSE_KEY1_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA4  0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_M  ((EFUSE_KEY1_DATA4_V)<<(EFUSE_KEY1_DATA4_S))
+#define EFUSE_KEY1_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA4_S  0
+
+#define EFUSE_RD_KEY1_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0d0)
+/* EFUSE_KEY1_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA5  0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_M  ((EFUSE_KEY1_DATA5_V)<<(EFUSE_KEY1_DATA5_S))
+#define EFUSE_KEY1_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA5_S  0
+
+#define EFUSE_RD_KEY1_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0d4)
+/* EFUSE_KEY1_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA6  0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_M  ((EFUSE_KEY1_DATA6_V)<<(EFUSE_KEY1_DATA6_S))
+#define EFUSE_KEY1_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA6_S  0
+
+#define EFUSE_RD_KEY1_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0d8)
+/* EFUSE_KEY1_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY1_DATA7  0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_M  ((EFUSE_KEY1_DATA7_V)<<(EFUSE_KEY1_DATA7_S))
+#define EFUSE_KEY1_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY1_DATA7_S  0
+
+#define EFUSE_RD_KEY2_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0dc)
+/* EFUSE_KEY2_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA0  0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_M  ((EFUSE_KEY2_DATA0_V)<<(EFUSE_KEY2_DATA0_S))
+#define EFUSE_KEY2_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA0_S  0
+
+#define EFUSE_RD_KEY2_DATA1_REG          (DR_REG_EFUSE_BASE + 0x0e0)
+/* EFUSE_KEY2_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA1  0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_M  ((EFUSE_KEY2_DATA1_V)<<(EFUSE_KEY2_DATA1_S))
+#define EFUSE_KEY2_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA1_S  0
+
+#define EFUSE_RD_KEY2_DATA2_REG          (DR_REG_EFUSE_BASE + 0x0e4)
+/* EFUSE_KEY2_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA2  0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_M  ((EFUSE_KEY2_DATA2_V)<<(EFUSE_KEY2_DATA2_S))
+#define EFUSE_KEY2_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA2_S  0
+
+#define EFUSE_RD_KEY2_DATA3_REG          (DR_REG_EFUSE_BASE + 0x0e8)
+/* EFUSE_KEY2_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA3  0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_M  ((EFUSE_KEY2_DATA3_V)<<(EFUSE_KEY2_DATA3_S))
+#define EFUSE_KEY2_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA3_S  0
+
+#define EFUSE_RD_KEY2_DATA4_REG          (DR_REG_EFUSE_BASE + 0x0ec)
+/* EFUSE_KEY2_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA4  0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_M  ((EFUSE_KEY2_DATA4_V)<<(EFUSE_KEY2_DATA4_S))
+#define EFUSE_KEY2_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA4_S  0
+
+#define EFUSE_RD_KEY2_DATA5_REG          (DR_REG_EFUSE_BASE + 0x0f0)
+/* EFUSE_KEY2_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA5  0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_M  ((EFUSE_KEY2_DATA5_V)<<(EFUSE_KEY2_DATA5_S))
+#define EFUSE_KEY2_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA5_S  0
+
+#define EFUSE_RD_KEY2_DATA6_REG          (DR_REG_EFUSE_BASE + 0x0f4)
+/* EFUSE_KEY2_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA6  0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_M  ((EFUSE_KEY2_DATA6_V)<<(EFUSE_KEY2_DATA6_S))
+#define EFUSE_KEY2_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA6_S  0
+
+#define EFUSE_RD_KEY2_DATA7_REG          (DR_REG_EFUSE_BASE + 0x0f8)
+/* EFUSE_KEY2_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY2_DATA7  0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_M  ((EFUSE_KEY2_DATA7_V)<<(EFUSE_KEY2_DATA7_S))
+#define EFUSE_KEY2_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY2_DATA7_S  0
+
+#define EFUSE_RD_KEY3_DATA0_REG          (DR_REG_EFUSE_BASE + 0x0fc)
+/* EFUSE_KEY3_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA0  0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_M  ((EFUSE_KEY3_DATA0_V)<<(EFUSE_KEY3_DATA0_S))
+#define EFUSE_KEY3_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA0_S  0
+
+#define EFUSE_RD_KEY3_DATA1_REG          (DR_REG_EFUSE_BASE + 0x100)
+/* EFUSE_KEY3_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA1  0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_M  ((EFUSE_KEY3_DATA1_V)<<(EFUSE_KEY3_DATA1_S))
+#define EFUSE_KEY3_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA1_S  0
+
+#define EFUSE_RD_KEY3_DATA2_REG          (DR_REG_EFUSE_BASE + 0x104)
+/* EFUSE_KEY3_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA2  0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_M  ((EFUSE_KEY3_DATA2_V)<<(EFUSE_KEY3_DATA2_S))
+#define EFUSE_KEY3_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA2_S  0
+
+#define EFUSE_RD_KEY3_DATA3_REG          (DR_REG_EFUSE_BASE + 0x108)
+/* EFUSE_KEY3_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA3  0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_M  ((EFUSE_KEY3_DATA3_V)<<(EFUSE_KEY3_DATA3_S))
+#define EFUSE_KEY3_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA3_S  0
+
+#define EFUSE_RD_KEY3_DATA4_REG          (DR_REG_EFUSE_BASE + 0x10c)
+/* EFUSE_KEY3_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA4  0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_M  ((EFUSE_KEY3_DATA4_V)<<(EFUSE_KEY3_DATA4_S))
+#define EFUSE_KEY3_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA4_S  0
+
+#define EFUSE_RD_KEY3_DATA5_REG          (DR_REG_EFUSE_BASE + 0x110)
+/* EFUSE_KEY3_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA5  0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_M  ((EFUSE_KEY3_DATA5_V)<<(EFUSE_KEY3_DATA5_S))
+#define EFUSE_KEY3_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA5_S  0
+
+#define EFUSE_RD_KEY3_DATA6_REG          (DR_REG_EFUSE_BASE + 0x114)
+/* EFUSE_KEY3_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA6  0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_M  ((EFUSE_KEY3_DATA6_V)<<(EFUSE_KEY3_DATA6_S))
+#define EFUSE_KEY3_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA6_S  0
+
+#define EFUSE_RD_KEY3_DATA7_REG          (DR_REG_EFUSE_BASE + 0x118)
+/* EFUSE_KEY3_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY3_DATA7  0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_M  ((EFUSE_KEY3_DATA7_V)<<(EFUSE_KEY3_DATA7_S))
+#define EFUSE_KEY3_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY3_DATA7_S  0
+
+#define EFUSE_RD_KEY4_DATA0_REG          (DR_REG_EFUSE_BASE + 0x11c)
+/* EFUSE_KEY4_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA0  0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_M  ((EFUSE_KEY4_DATA0_V)<<(EFUSE_KEY4_DATA0_S))
+#define EFUSE_KEY4_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA0_S  0
+
+#define EFUSE_RD_KEY4_DATA1_REG          (DR_REG_EFUSE_BASE + 0x120)
+/* EFUSE_KEY4_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA1  0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_M  ((EFUSE_KEY4_DATA1_V)<<(EFUSE_KEY4_DATA1_S))
+#define EFUSE_KEY4_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA1_S  0
+
+#define EFUSE_RD_KEY4_DATA2_REG          (DR_REG_EFUSE_BASE + 0x124)
+/* EFUSE_KEY4_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA2  0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_M  ((EFUSE_KEY4_DATA2_V)<<(EFUSE_KEY4_DATA2_S))
+#define EFUSE_KEY4_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA2_S  0
+
+#define EFUSE_RD_KEY4_DATA3_REG          (DR_REG_EFUSE_BASE + 0x128)
+/* EFUSE_KEY4_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA3  0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_M  ((EFUSE_KEY4_DATA3_V)<<(EFUSE_KEY4_DATA3_S))
+#define EFUSE_KEY4_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA3_S  0
+
+#define EFUSE_RD_KEY4_DATA4_REG          (DR_REG_EFUSE_BASE + 0x12c)
+/* EFUSE_KEY4_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA4  0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_M  ((EFUSE_KEY4_DATA4_V)<<(EFUSE_KEY4_DATA4_S))
+#define EFUSE_KEY4_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA4_S  0
+
+#define EFUSE_RD_KEY4_DATA5_REG          (DR_REG_EFUSE_BASE + 0x130)
+/* EFUSE_KEY4_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA5  0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_M  ((EFUSE_KEY4_DATA5_V)<<(EFUSE_KEY4_DATA5_S))
+#define EFUSE_KEY4_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA5_S  0
+
+#define EFUSE_RD_KEY4_DATA6_REG          (DR_REG_EFUSE_BASE + 0x134)
+/* EFUSE_KEY4_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA6  0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_M  ((EFUSE_KEY4_DATA6_V)<<(EFUSE_KEY4_DATA6_S))
+#define EFUSE_KEY4_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA6_S  0
+
+#define EFUSE_RD_KEY4_DATA7_REG          (DR_REG_EFUSE_BASE + 0x138)
+/* EFUSE_KEY4_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY4_DATA7  0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_M  ((EFUSE_KEY4_DATA7_V)<<(EFUSE_KEY4_DATA7_S))
+#define EFUSE_KEY4_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY4_DATA7_S  0
+
+#define EFUSE_RD_KEY5_DATA0_REG          (DR_REG_EFUSE_BASE + 0x13c)
+/* EFUSE_KEY5_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA0  0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_M  ((EFUSE_KEY5_DATA0_V)<<(EFUSE_KEY5_DATA0_S))
+#define EFUSE_KEY5_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA0_S  0
+
+#define EFUSE_RD_KEY5_DATA1_REG          (DR_REG_EFUSE_BASE + 0x140)
+/* EFUSE_KEY5_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA1  0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_M  ((EFUSE_KEY5_DATA1_V)<<(EFUSE_KEY5_DATA1_S))
+#define EFUSE_KEY5_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA1_S  0
+
+#define EFUSE_RD_KEY5_DATA2_REG          (DR_REG_EFUSE_BASE + 0x144)
+/* EFUSE_KEY5_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA2  0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_M  ((EFUSE_KEY5_DATA2_V)<<(EFUSE_KEY5_DATA2_S))
+#define EFUSE_KEY5_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA2_S  0
+
+#define EFUSE_RD_KEY5_DATA3_REG          (DR_REG_EFUSE_BASE + 0x148)
+/* EFUSE_KEY5_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA3  0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_M  ((EFUSE_KEY5_DATA3_V)<<(EFUSE_KEY5_DATA3_S))
+#define EFUSE_KEY5_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA3_S  0
+
+#define EFUSE_RD_KEY5_DATA4_REG          (DR_REG_EFUSE_BASE + 0x14c)
+/* EFUSE_KEY5_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA4  0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_M  ((EFUSE_KEY5_DATA4_V)<<(EFUSE_KEY5_DATA4_S))
+#define EFUSE_KEY5_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA4_S  0
+
+#define EFUSE_RD_KEY5_DATA5_REG          (DR_REG_EFUSE_BASE + 0x150)
+/* EFUSE_KEY5_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA5  0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_M  ((EFUSE_KEY5_DATA5_V)<<(EFUSE_KEY5_DATA5_S))
+#define EFUSE_KEY5_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA5_S  0
+
+#define EFUSE_RD_KEY5_DATA6_REG          (DR_REG_EFUSE_BASE + 0x154)
+/* EFUSE_KEY5_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA6  0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_M  ((EFUSE_KEY5_DATA6_V)<<(EFUSE_KEY5_DATA6_S))
+#define EFUSE_KEY5_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA6_S  0
+
+#define EFUSE_RD_KEY5_DATA7_REG          (DR_REG_EFUSE_BASE + 0x158)
+/* EFUSE_KEY5_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY5_DATA7  0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_M  ((EFUSE_KEY5_DATA7_V)<<(EFUSE_KEY5_DATA7_S))
+#define EFUSE_KEY5_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY5_DATA7_S  0
+
+#define EFUSE_RD_KEY6_DATA0_REG          (DR_REG_EFUSE_BASE + 0x15c)
+/* EFUSE_KEY6_DATA0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA0  0xFFFFFFFF
+#define EFUSE_KEY6_DATA0_M  ((EFUSE_KEY6_DATA0_V)<<(EFUSE_KEY6_DATA0_S))
+#define EFUSE_KEY6_DATA0_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA0_S  0
+
+#define EFUSE_RD_KEY6_DATA1_REG          (DR_REG_EFUSE_BASE + 0x160)
+/* EFUSE_KEY6_DATA1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA1  0xFFFFFFFF
+#define EFUSE_KEY6_DATA1_M  ((EFUSE_KEY6_DATA1_V)<<(EFUSE_KEY6_DATA1_S))
+#define EFUSE_KEY6_DATA1_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA1_S  0
+
+#define EFUSE_RD_KEY6_DATA2_REG          (DR_REG_EFUSE_BASE + 0x164)
+/* EFUSE_KEY6_DATA2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA2  0xFFFFFFFF
+#define EFUSE_KEY6_DATA2_M  ((EFUSE_KEY6_DATA2_V)<<(EFUSE_KEY6_DATA2_S))
+#define EFUSE_KEY6_DATA2_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA2_S  0
+
+#define EFUSE_RD_KEY6_DATA3_REG          (DR_REG_EFUSE_BASE + 0x168)
+/* EFUSE_KEY6_DATA3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA3  0xFFFFFFFF
+#define EFUSE_KEY6_DATA3_M  ((EFUSE_KEY6_DATA3_V)<<(EFUSE_KEY6_DATA3_S))
+#define EFUSE_KEY6_DATA3_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA3_S  0
+
+#define EFUSE_RD_KEY6_DATA4_REG          (DR_REG_EFUSE_BASE + 0x16c)
+/* EFUSE_KEY6_DATA4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA4  0xFFFFFFFF
+#define EFUSE_KEY6_DATA4_M  ((EFUSE_KEY6_DATA4_V)<<(EFUSE_KEY6_DATA4_S))
+#define EFUSE_KEY6_DATA4_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA4_S  0
+
+#define EFUSE_RD_KEY6_DATA5_REG          (DR_REG_EFUSE_BASE + 0x170)
+/* EFUSE_KEY6_DATA5 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA5  0xFFFFFFFF
+#define EFUSE_KEY6_DATA5_M  ((EFUSE_KEY6_DATA5_V)<<(EFUSE_KEY6_DATA5_S))
+#define EFUSE_KEY6_DATA5_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA5_S  0
+
+#define EFUSE_RD_KEY6_DATA6_REG          (DR_REG_EFUSE_BASE + 0x174)
+/* EFUSE_KEY6_DATA6 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA6  0xFFFFFFFF
+#define EFUSE_KEY6_DATA6_M  ((EFUSE_KEY6_DATA6_V)<<(EFUSE_KEY6_DATA6_S))
+#define EFUSE_KEY6_DATA6_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA6_S  0
+
+#define EFUSE_RD_KEY6_DATA7_REG          (DR_REG_EFUSE_BASE + 0x178)
+/* EFUSE_KEY6_DATA7 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define EFUSE_KEY6_DATA7  0xFFFFFFFF
+#define EFUSE_KEY6_DATA7_M  ((EFUSE_KEY6_DATA7_V)<<(EFUSE_KEY6_DATA7_S))
+#define EFUSE_KEY6_DATA7_V  0xFFFFFFFF
+#define EFUSE_KEY6_DATA7_S  0
+
+#define EFUSE_RD_REPEAT_ERR0_REG          (DR_REG_EFUSE_BASE + 0x17c)
+/* EFUSE_RD_SDIO_DREFH_ERR : RO ;bitpos:[31:30] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DREFH_ERR  0x00000003
+#define EFUSE_RD_SDIO_DREFH_ERR_M  ((EFUSE_RD_SDIO_DREFH_ERR_V)<<(EFUSE_RD_SDIO_DREFH_ERR_S))
+#define EFUSE_RD_SDIO_DREFH_ERR_V  0x3
+#define EFUSE_RD_SDIO_DREFH_ERR_S  30
+/* EFUSE_RD_SDIO_MODECURLIM_ERR : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_MODECURLIM_ERR  (BIT(29))
+#define EFUSE_RD_SDIO_MODECURLIM_ERR_M  (BIT(29))
+#define EFUSE_RD_SDIO_MODECURLIM_ERR_V  0x1
+#define EFUSE_RD_SDIO_MODECURLIM_ERR_S  29
+/* EFUSE_RD_USB_DRES_ERR : RO ;bitpos:[28:25] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_USB_DRES_ERR  0x0000000F
+#define EFUSE_RD_USB_DRES_ERR_M  ((EFUSE_RD_USB_DRES_ERR_V)<<(EFUSE_RD_USB_DRES_ERR_S))
+#define EFUSE_RD_USB_DRES_ERR_V  0xF
+#define EFUSE_RD_USB_DRES_ERR_S  25
+/* EFUSE_RD_USB_EXCHG_PINS_ERR : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_USB_EXCHG_PINS_ERR  (BIT(24))
+#define EFUSE_RD_USB_EXCHG_PINS_ERR_M  (BIT(24))
+#define EFUSE_RD_USB_EXCHG_PINS_ERR_V  0x1
+#define EFUSE_RD_USB_EXCHG_PINS_ERR_S  24
+/* EFUSE_RD_USB_DREFL_ERR : RO ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_USB_DREFL_ERR  0x00000003
+#define EFUSE_RD_USB_DREFL_ERR_M  ((EFUSE_RD_USB_DREFL_ERR_V)<<(EFUSE_RD_USB_DREFL_ERR_S))
+#define EFUSE_RD_USB_DREFL_ERR_V  0x3
+#define EFUSE_RD_USB_DREFL_ERR_S  22
+/* EFUSE_RD_USB_DREFH_ERR : RO ;bitpos:[21:20] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_USB_DREFH_ERR  0x00000003
+#define EFUSE_RD_USB_DREFH_ERR_M  ((EFUSE_RD_USB_DREFH_ERR_V)<<(EFUSE_RD_USB_DREFH_ERR_S))
+#define EFUSE_RD_USB_DREFH_ERR_V  0x3
+#define EFUSE_RD_USB_DREFH_ERR_S  20
+/* EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR  (BIT(19))
+#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_M  (BIT(19))
+#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_V  0x1
+#define EFUSE_RD_DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR_S  19
+/* EFUSE_RD_HARD_DIS_JTAG_ERR : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_HARD_DIS_JTAG_ERR  (BIT(18))
+#define EFUSE_RD_HARD_DIS_JTAG_ERR_M  (BIT(18))
+#define EFUSE_RD_HARD_DIS_JTAG_ERR_V  0x1
+#define EFUSE_RD_HARD_DIS_JTAG_ERR_S  18
+/* EFUSE_RD_SOFT_DIS_JTAG_ERR : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SOFT_DIS_JTAG_ERR  (BIT(17))
+#define EFUSE_RD_SOFT_DIS_JTAG_ERR_M  (BIT(17))
+#define EFUSE_RD_SOFT_DIS_JTAG_ERR_V  0x1
+#define EFUSE_RD_SOFT_DIS_JTAG_ERR_S  17
+/* EFUSE_RD_DIS_EFUSE_ATE_WR_ERR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR  (BIT(16))
+#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR_M  (BIT(16))
+#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR_V  0x1
+#define EFUSE_RD_DIS_EFUSE_ATE_WR_ERR_S  16
+/* EFUSE_RD_DIS_SDIO_ACCESS_ERR : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_SDIO_ACCESS_ERR  (BIT(15))
+#define EFUSE_RD_DIS_SDIO_ACCESS_ERR_M  (BIT(15))
+#define EFUSE_RD_DIS_SDIO_ACCESS_ERR_V  0x1
+#define EFUSE_RD_DIS_SDIO_ACCESS_ERR_S  15
+/* EFUSE_RD_DIS_CAN_ERR : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_CAN_ERR  (BIT(14))
+#define EFUSE_RD_DIS_CAN_ERR_M  (BIT(14))
+#define EFUSE_RD_DIS_CAN_ERR_V  0x1
+#define EFUSE_RD_DIS_CAN_ERR_S  14
+/* EFUSE_RD_DIS_USB_ERR : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_USB_ERR  (BIT(13))
+#define EFUSE_RD_DIS_USB_ERR_M  (BIT(13))
+#define EFUSE_RD_DIS_USB_ERR_V  0x1
+#define EFUSE_RD_DIS_USB_ERR_S  13
+/* EFUSE_RD_DIS_BT_ERR : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_BT_ERR  (BIT(12))
+#define EFUSE_RD_DIS_BT_ERR_M  (BIT(12))
+#define EFUSE_RD_DIS_BT_ERR_V  0x1
+#define EFUSE_RD_DIS_BT_ERR_S  12
+/* EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR  (BIT(11))
+#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR_M  (BIT(11))
+#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR_V  0x1
+#define EFUSE_RD_DIS_DOWNLOAD_DCACHE_ERR_S  11
+/* EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR  (BIT(10))
+#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR_M  (BIT(10))
+#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR_V  0x1
+#define EFUSE_RD_DIS_DOWNLOAD_ICACHE_ERR_S  10
+/* EFUSE_RD_DIS_DCACHE_ERR : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_DCACHE_ERR  (BIT(9))
+#define EFUSE_RD_DIS_DCACHE_ERR_M  (BIT(9))
+#define EFUSE_RD_DIS_DCACHE_ERR_V  0x1
+#define EFUSE_RD_DIS_DCACHE_ERR_S  9
+/* EFUSE_RD_DIS_ICACHE_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_ICACHE_ERR  (BIT(8))
+#define EFUSE_RD_DIS_ICACHE_ERR_M  (BIT(8))
+#define EFUSE_RD_DIS_ICACHE_ERR_V  0x1
+#define EFUSE_RD_DIS_ICACHE_ERR_S  8
+/* EFUSE_RD_DIS_RTC_RAM_BOOT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR  (BIT(7))
+#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR_M  (BIT(7))
+#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR_V  0x1
+#define EFUSE_RD_DIS_RTC_RAM_BOOT_ERR_S  7
+/* EFUSE_RD_RD_DIS_ERR : RO ;bitpos:[6:0] ;default: 7'h0 ; */
+/*description: */
+#define EFUSE_RD_RD_DIS_ERR  0x0000007F
+#define EFUSE_RD_RD_DIS_ERR_M  ((EFUSE_RD_RD_DIS_ERR_V)<<(EFUSE_RD_RD_DIS_ERR_S))
+#define EFUSE_RD_RD_DIS_ERR_V  0x7F
+#define EFUSE_RD_RD_DIS_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR1_REG          (DR_REG_EFUSE_BASE + 0x180)
+/* EFUSE_RD_KEY_PURPOSE_1_ERR : RO ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY_PURPOSE_1_ERR  0x0000000F
+#define EFUSE_RD_KEY_PURPOSE_1_ERR_M  ((EFUSE_RD_KEY_PURPOSE_1_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_1_ERR_S))
+#define EFUSE_RD_KEY_PURPOSE_1_ERR_V  0xF
+#define EFUSE_RD_KEY_PURPOSE_1_ERR_S  28
+/* EFUSE_RD_KEY_PURPOSE_0_ERR : RO ;bitpos:[27:24] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY_PURPOSE_0_ERR  0x0000000F
+#define EFUSE_RD_KEY_PURPOSE_0_ERR_M  ((EFUSE_RD_KEY_PURPOSE_0_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_0_ERR_S))
+#define EFUSE_RD_KEY_PURPOSE_0_ERR_V  0xF
+#define EFUSE_RD_KEY_PURPOSE_0_ERR_S  24
+/* EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR  (BIT(23))
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR_M  (BIT(23))
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR_V  0x1
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE2_ERR_S  23
+/* EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR  (BIT(22))
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR_M  (BIT(22))
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR_V  0x1
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE1_ERR_S  22
+/* EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR  (BIT(21))
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR_M  (BIT(21))
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR_V  0x1
+#define EFUSE_RD_SECURE_BOOT_KEY_REVOKE0_ERR_S  21
+/* EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR : RO ;bitpos:[20:18] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR  0x00000007
+#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_M  ((EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_V)<<(EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_S))
+#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_V  0x7
+#define EFUSE_RD_SPI_BOOT_CRYPT_CNT_ERR_S  18
+/* EFUSE_RD_WDT_DELAY_SEL_ERR : RO ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_WDT_DELAY_SEL_ERR  0x00000003
+#define EFUSE_RD_WDT_DELAY_SEL_ERR_M  ((EFUSE_RD_WDT_DELAY_SEL_ERR_V)<<(EFUSE_RD_WDT_DELAY_SEL_ERR_S))
+#define EFUSE_RD_WDT_DELAY_SEL_ERR_V  0x3
+#define EFUSE_RD_WDT_DELAY_SEL_ERR_S  16
+/* EFUSE_RD_SDIO_DCAP_ERR : RO ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DCAP_ERR  0x00000003
+#define EFUSE_RD_SDIO_DCAP_ERR_M  ((EFUSE_RD_SDIO_DCAP_ERR_V)<<(EFUSE_RD_SDIO_DCAP_ERR_S))
+#define EFUSE_RD_SDIO_DCAP_ERR_V  0x3
+#define EFUSE_RD_SDIO_DCAP_ERR_S  14
+/* EFUSE_RD_SDIO_INIT_ERR : RO ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_INIT_ERR  0x00000003
+#define EFUSE_RD_SDIO_INIT_ERR_M  ((EFUSE_RD_SDIO_INIT_ERR_V)<<(EFUSE_RD_SDIO_INIT_ERR_S))
+#define EFUSE_RD_SDIO_INIT_ERR_V  0x3
+#define EFUSE_RD_SDIO_INIT_ERR_S  12
+/* EFUSE_RD_SDIO_DCURLIM_ERR : RO ;bitpos:[11:9] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DCURLIM_ERR  0x00000007
+#define EFUSE_RD_SDIO_DCURLIM_ERR_M  ((EFUSE_RD_SDIO_DCURLIM_ERR_V)<<(EFUSE_RD_SDIO_DCURLIM_ERR_S))
+#define EFUSE_RD_SDIO_DCURLIM_ERR_V  0x7
+#define EFUSE_RD_SDIO_DCURLIM_ERR_S  9
+/* EFUSE_RD_SDIO_ENCURLIM_ERR : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_ENCURLIM_ERR  (BIT(8))
+#define EFUSE_RD_SDIO_ENCURLIM_ERR_M  (BIT(8))
+#define EFUSE_RD_SDIO_ENCURLIM_ERR_V  0x1
+#define EFUSE_RD_SDIO_ENCURLIM_ERR_S  8
+/* EFUSE_RD_SDIO_EN_INIT_ERR : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_EN_INIT_ERR  (BIT(7))
+#define EFUSE_RD_SDIO_EN_INIT_ERR_M  (BIT(7))
+#define EFUSE_RD_SDIO_EN_INIT_ERR_V  0x1
+#define EFUSE_RD_SDIO_EN_INIT_ERR_S  7
+/* EFUSE_RD_SDIO_FORCE_ERR : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_FORCE_ERR  (BIT(6))
+#define EFUSE_RD_SDIO_FORCE_ERR_M  (BIT(6))
+#define EFUSE_RD_SDIO_FORCE_ERR_V  0x1
+#define EFUSE_RD_SDIO_FORCE_ERR_S  6
+/* EFUSE_RD_SDIO_TIEH_ERR : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_TIEH_ERR  (BIT(5))
+#define EFUSE_RD_SDIO_TIEH_ERR_M  (BIT(5))
+#define EFUSE_RD_SDIO_TIEH_ERR_V  0x1
+#define EFUSE_RD_SDIO_TIEH_ERR_S  5
+/* EFUSE_RD_SDIO_XPD_ERR : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_XPD_ERR  (BIT(4))
+#define EFUSE_RD_SDIO_XPD_ERR_M  (BIT(4))
+#define EFUSE_RD_SDIO_XPD_ERR_V  0x1
+#define EFUSE_RD_SDIO_XPD_ERR_S  4
+/* EFUSE_RD_SDIO_DREFL_ERR : RO ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DREFL_ERR  0x00000003
+#define EFUSE_RD_SDIO_DREFL_ERR_M  ((EFUSE_RD_SDIO_DREFL_ERR_V)<<(EFUSE_RD_SDIO_DREFL_ERR_S))
+#define EFUSE_RD_SDIO_DREFL_ERR_V  0x3
+#define EFUSE_RD_SDIO_DREFL_ERR_S  2
+/* EFUSE_RD_SDIO_DREFM_ERR : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_SDIO_DREFM_ERR  0x00000003
+#define EFUSE_RD_SDIO_DREFM_ERR_M  ((EFUSE_RD_SDIO_DREFM_ERR_V)<<(EFUSE_RD_SDIO_DREFM_ERR_S))
+#define EFUSE_RD_SDIO_DREFM_ERR_V  0x3
+#define EFUSE_RD_SDIO_DREFM_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR2_REG          (DR_REG_EFUSE_BASE + 0x184)
+/* EFUSE_RD_FLASH_TPUW_ERR : RO ;bitpos:[31:28] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_FLASH_TPUW_ERR  0x0000000F
+#define EFUSE_RD_FLASH_TPUW_ERR_M  ((EFUSE_RD_FLASH_TPUW_ERR_V)<<(EFUSE_RD_FLASH_TPUW_ERR_S))
+#define EFUSE_RD_FLASH_TPUW_ERR_V  0xF
+#define EFUSE_RD_FLASH_TPUW_ERR_S  28
+/* EFUSE_RD_XTAL_FREQ_ERR : RO ;bitpos:[27:22] ;default: 6'b0 ; */
+/*description: */
+#define EFUSE_RD_XTAL_FREQ_ERR  0x0000003F
+#define EFUSE_RD_XTAL_FREQ_ERR_M  ((EFUSE_RD_XTAL_FREQ_ERR_V)<<(EFUSE_RD_XTAL_FREQ_ERR_S))
+#define EFUSE_RD_XTAL_FREQ_ERR_V  0x3F
+#define EFUSE_RD_XTAL_FREQ_ERR_S  22
+/* EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR  (BIT(21))
+#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_M  (BIT(21))
+#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_V  0x1
+#define EFUSE_RD_SECURE_BOOT_AGGRESSIVE_REVOKE_ERR_S  21
+/* EFUSE_RD_SECURE_BOOT_EN_ERR : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SECURE_BOOT_EN_ERR  (BIT(20))
+#define EFUSE_RD_SECURE_BOOT_EN_ERR_M  (BIT(20))
+#define EFUSE_RD_SECURE_BOOT_EN_ERR_V  0x1
+#define EFUSE_RD_SECURE_BOOT_EN_ERR_S  20
+/* EFUSE_RD_KEY_PURPOSE_6_ERR : RO ;bitpos:[19:16] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY_PURPOSE_6_ERR  0x0000000F
+#define EFUSE_RD_KEY_PURPOSE_6_ERR_M  ((EFUSE_RD_KEY_PURPOSE_6_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_6_ERR_S))
+#define EFUSE_RD_KEY_PURPOSE_6_ERR_V  0xF
+#define EFUSE_RD_KEY_PURPOSE_6_ERR_S  16
+/* EFUSE_RD_KEY_PURPOSE_5_ERR : RO ;bitpos:[15:12] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY_PURPOSE_5_ERR  0x0000000F
+#define EFUSE_RD_KEY_PURPOSE_5_ERR_M  ((EFUSE_RD_KEY_PURPOSE_5_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_5_ERR_S))
+#define EFUSE_RD_KEY_PURPOSE_5_ERR_V  0xF
+#define EFUSE_RD_KEY_PURPOSE_5_ERR_S  12
+/* EFUSE_RD_KEY_PURPOSE_4_ERR : RO ;bitpos:[11:8] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY_PURPOSE_4_ERR  0x0000000F
+#define EFUSE_RD_KEY_PURPOSE_4_ERR_M  ((EFUSE_RD_KEY_PURPOSE_4_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_4_ERR_S))
+#define EFUSE_RD_KEY_PURPOSE_4_ERR_V  0xF
+#define EFUSE_RD_KEY_PURPOSE_4_ERR_S  8
+/* EFUSE_RD_KEY_PURPOSE_3_ERR : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY_PURPOSE_3_ERR  0x0000000F
+#define EFUSE_RD_KEY_PURPOSE_3_ERR_M  ((EFUSE_RD_KEY_PURPOSE_3_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_3_ERR_S))
+#define EFUSE_RD_KEY_PURPOSE_3_ERR_V  0xF
+#define EFUSE_RD_KEY_PURPOSE_3_ERR_S  4
+/* EFUSE_RD_KEY_PURPOSE_2_ERR : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY_PURPOSE_2_ERR  0x0000000F
+#define EFUSE_RD_KEY_PURPOSE_2_ERR_M  ((EFUSE_RD_KEY_PURPOSE_2_ERR_V)<<(EFUSE_RD_KEY_PURPOSE_2_ERR_S))
+#define EFUSE_RD_KEY_PURPOSE_2_ERR_V  0xF
+#define EFUSE_RD_KEY_PURPOSE_2_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR3_REG          (DR_REG_EFUSE_BASE + 0x188)
+/* EFUSE_RD_RESERVE_ERR : RO ;bitpos:[31:8] ;default: 24'h0 ; */
+/*description: */
+#define EFUSE_RD_RESERVE_ERR  0x00FFFFFF
+#define EFUSE_RD_RESERVE_ERR_M  ((EFUSE_RD_RESERVE_ERR_V)<<(EFUSE_RD_RESERVE_ERR_S))
+#define EFUSE_RD_RESERVE_ERR_V  0xFFFFFF
+#define EFUSE_RD_RESERVE_ERR_S  8
+/* EFUSE_RD_UART_PRINT_CONTROL : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: */
+#define EFUSE_RD_UART_PRINT_CONTROL  0x00000003
+#define EFUSE_RD_UART_PRINT_CONTROL_M  ((EFUSE_RD_UART_PRINT_CONTROL_V)<<(EFUSE_RD_UART_PRINT_CONTROL_S))
+#define EFUSE_RD_UART_PRINT_CONTROL_V  0x3
+#define EFUSE_RD_UART_PRINT_CONTROL_S  6
+/* EFUSE_RD_ENABLE_SECURITY_DOWNLOAD : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD  (BIT(5))
+#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD_M  (BIT(5))
+#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD_V  0x1
+#define EFUSE_RD_ENABLE_SECURITY_DOWNLOAD_S  5
+/* EFUSE_RD_DIS_USB_DOWNLOAD_MODE : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE  (BIT(4))
+#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE_M  (BIT(4))
+#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE_V  0x1
+#define EFUSE_RD_DIS_USB_DOWNLOAD_MODE_S  4
+/* EFUSE_RD_DIS_TINY_BASIC : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_TINY_BASIC  (BIT(3))
+#define EFUSE_RD_DIS_TINY_BASIC_M  (BIT(3))
+#define EFUSE_RD_DIS_TINY_BASIC_V  0x1
+#define EFUSE_RD_DIS_TINY_BASIC_S  3
+/* EFUSE_RD_UART_PRINT_CHANNEL : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_UART_PRINT_CHANNEL  (BIT(2))
+#define EFUSE_RD_UART_PRINT_CHANNEL_M  (BIT(2))
+#define EFUSE_RD_UART_PRINT_CHANNEL_V  0x1
+#define EFUSE_RD_UART_PRINT_CHANNEL_S  2
+/* EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR  (BIT(1))
+#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR_M  (BIT(1))
+#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR_V  0x1
+#define EFUSE_RD_DIS_LEGACY_SPI_BOOT_ERR_S  1
+/* EFUSE_RD_DIS_DOWNLOAD_MODE_ERR : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR  (BIT(0))
+#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR_M  (BIT(0))
+#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR_V  0x1
+#define EFUSE_RD_DIS_DOWNLOAD_MODE_ERR_S  0
+
+#define EFUSE_RD_REPEAT_ERR4_REG          (DR_REG_EFUSE_BASE + 0x190)
+/* EFUSE_RD_CHIP_VERSION_ERR : RO ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: */
+#define EFUSE_RD_CHIP_VERSION_ERR  0x00FFFFFF
+#define EFUSE_RD_CHIP_VERSION_ERR_M  ((EFUSE_RD_CHIP_VERSION_ERR_V)<<(EFUSE_RD_CHIP_VERSION_ERR_S))
+#define EFUSE_RD_CHIP_VERSION_ERR_V  0xFFFFFF
+#define EFUSE_RD_CHIP_VERSION_ERR_S  0
+
+#define EFUSE_RD_RS_ERR0_REG          (DR_REG_EFUSE_BASE + 0x194)
+/* EFUSE_RD_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY4_FAIL  (BIT(31))
+#define EFUSE_RD_KEY4_FAIL_M  (BIT(31))
+#define EFUSE_RD_KEY4_FAIL_V  0x1
+#define EFUSE_RD_KEY4_FAIL_S  31
+/* EFUSE_RD_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY4_ERR_NUM  0x00000007
+#define EFUSE_RD_KEY4_ERR_NUM_M  ((EFUSE_RD_KEY4_ERR_NUM_V)<<(EFUSE_RD_KEY4_ERR_NUM_S))
+#define EFUSE_RD_KEY4_ERR_NUM_V  0x7
+#define EFUSE_RD_KEY4_ERR_NUM_S  28
+/* EFUSE_RD_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY3_FAIL  (BIT(27))
+#define EFUSE_RD_KEY3_FAIL_M  (BIT(27))
+#define EFUSE_RD_KEY3_FAIL_V  0x1
+#define EFUSE_RD_KEY3_FAIL_S  27
+/* EFUSE_RD_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY3_ERR_NUM  0x00000007
+#define EFUSE_RD_KEY3_ERR_NUM_M  ((EFUSE_RD_KEY3_ERR_NUM_V)<<(EFUSE_RD_KEY3_ERR_NUM_S))
+#define EFUSE_RD_KEY3_ERR_NUM_V  0x7
+#define EFUSE_RD_KEY3_ERR_NUM_S  24
+/* EFUSE_RD_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY2_FAIL  (BIT(23))
+#define EFUSE_RD_KEY2_FAIL_M  (BIT(23))
+#define EFUSE_RD_KEY2_FAIL_V  0x1
+#define EFUSE_RD_KEY2_FAIL_S  23
+/* EFUSE_RD_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY2_ERR_NUM  0x00000007
+#define EFUSE_RD_KEY2_ERR_NUM_M  ((EFUSE_RD_KEY2_ERR_NUM_V)<<(EFUSE_RD_KEY2_ERR_NUM_S))
+#define EFUSE_RD_KEY2_ERR_NUM_V  0x7
+#define EFUSE_RD_KEY2_ERR_NUM_S  20
+/* EFUSE_RD_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY1_FAIL  (BIT(19))
+#define EFUSE_RD_KEY1_FAIL_M  (BIT(19))
+#define EFUSE_RD_KEY1_FAIL_V  0x1
+#define EFUSE_RD_KEY1_FAIL_S  19
+/* EFUSE_RD_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY1_ERR_NUM  0x00000007
+#define EFUSE_RD_KEY1_ERR_NUM_M  ((EFUSE_RD_KEY1_ERR_NUM_V)<<(EFUSE_RD_KEY1_ERR_NUM_S))
+#define EFUSE_RD_KEY1_ERR_NUM_V  0x7
+#define EFUSE_RD_KEY1_ERR_NUM_S  16
+/* EFUSE_RD_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY0_FAIL  (BIT(15))
+#define EFUSE_RD_KEY0_FAIL_M  (BIT(15))
+#define EFUSE_RD_KEY0_FAIL_V  0x1
+#define EFUSE_RD_KEY0_FAIL_S  15
+/* EFUSE_RD_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY0_ERR_NUM  0x00000007
+#define EFUSE_RD_KEY0_ERR_NUM_M  ((EFUSE_RD_KEY0_ERR_NUM_V)<<(EFUSE_RD_KEY0_ERR_NUM_S))
+#define EFUSE_RD_KEY0_ERR_NUM_V  0x7
+#define EFUSE_RD_KEY0_ERR_NUM_S  12
+/* EFUSE_RD_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_USR_DATA_FAIL  (BIT(11))
+#define EFUSE_RD_USR_DATA_FAIL_M  (BIT(11))
+#define EFUSE_RD_USR_DATA_FAIL_V  0x1
+#define EFUSE_RD_USR_DATA_FAIL_S  11
+/* EFUSE_RD_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_USR_DATA_ERR_NUM  0x00000007
+#define EFUSE_RD_USR_DATA_ERR_NUM_M  ((EFUSE_RD_USR_DATA_ERR_NUM_V)<<(EFUSE_RD_USR_DATA_ERR_NUM_S))
+#define EFUSE_RD_USR_DATA_ERR_NUM_V  0x7
+#define EFUSE_RD_USR_DATA_ERR_NUM_S  8
+/* EFUSE_RD_SYS_ERR_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_SYS_ERR_FAIL  (BIT(7))
+#define EFUSE_RD_SYS_ERR_FAIL_M  (BIT(7))
+#define EFUSE_RD_SYS_ERR_FAIL_V  0x1
+#define EFUSE_RD_SYS_ERR_FAIL_S  7
+/* EFUSE_RD_SYS_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_SYS_ERR_NUM  0x00000007
+#define EFUSE_RD_SYS_ERR_NUM_M  ((EFUSE_RD_SYS_ERR_NUM_V)<<(EFUSE_RD_SYS_ERR_NUM_S))
+#define EFUSE_RD_SYS_ERR_NUM_V  0x7
+#define EFUSE_RD_SYS_ERR_NUM_S  4
+/* EFUSE_RD_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_MAC_SPI_8M_FAIL  (BIT(3))
+#define EFUSE_RD_MAC_SPI_8M_FAIL_M  (BIT(3))
+#define EFUSE_RD_MAC_SPI_8M_FAIL_V  0x1
+#define EFUSE_RD_MAC_SPI_8M_FAIL_S  3
+/* EFUSE_RD_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_MAC_SPI_8M_ERR_NUM  0x00000007
+#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_M  ((EFUSE_RD_MAC_SPI_8M_ERR_NUM_V)<<(EFUSE_RD_MAC_SPI_8M_ERR_NUM_S))
+#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_V  0x7
+#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_S  0
+
+#define EFUSE_RD_RS_ERR1_REG          (DR_REG_EFUSE_BASE + 0x198)
+/* EFUSE_RD_KEY6_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY6_FAIL  (BIT(7))
+#define EFUSE_RD_KEY6_FAIL_M  (BIT(7))
+#define EFUSE_RD_KEY6_FAIL_V  0x1
+#define EFUSE_RD_KEY6_FAIL_S  7
+/* EFUSE_RD_KEY6_ERR_NUM : RO ;bitpos:[6:4] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY6_ERR_NUM  0x00000007
+#define EFUSE_RD_KEY6_ERR_NUM_M  ((EFUSE_RD_KEY6_ERR_NUM_V)<<(EFUSE_RD_KEY6_ERR_NUM_S))
+#define EFUSE_RD_KEY6_ERR_NUM_V  0x7
+#define EFUSE_RD_KEY6_ERR_NUM_S  4
+/* EFUSE_RD_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY5_FAIL  (BIT(3))
+#define EFUSE_RD_KEY5_FAIL_M  (BIT(3))
+#define EFUSE_RD_KEY5_FAIL_V  0x1
+#define EFUSE_RD_KEY5_FAIL_S  3
+/* EFUSE_RD_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_RD_KEY5_ERR_NUM  0x00000007
+#define EFUSE_RD_KEY5_ERR_NUM_M  ((EFUSE_RD_KEY5_ERR_NUM_V)<<(EFUSE_RD_KEY5_ERR_NUM_S))
+#define EFUSE_RD_KEY5_ERR_NUM_V  0x7
+#define EFUSE_RD_KEY5_ERR_NUM_S  0
+
+#define EFUSE_CLK_REG          (DR_REG_EFUSE_BASE + 0x19c)
+/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_CLK_EN  (BIT(16))
+#define EFUSE_CLK_EN_M  (BIT(16))
+#define EFUSE_CLK_EN_V  0x1
+#define EFUSE_CLK_EN_S  16
+/* EFUSE_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_MEM_PD  (BIT(0))
+#define EFUSE_MEM_PD_M  (BIT(0))
+#define EFUSE_MEM_PD_V  0x1
+#define EFUSE_MEM_PD_S  0
+
+#define EFUSE_CONF_REG          (DR_REG_EFUSE_BASE + 0x1a0)
+/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define EFUSE_OP_CODE  0x0000FFFF
+#define EFUSE_OP_CODE_M  ((EFUSE_OP_CODE_V)<<(EFUSE_OP_CODE_S))
+#define EFUSE_OP_CODE_V  0xFFFF
+#define EFUSE_OP_CODE_S  0
+
+#define EFUSE_STATUS_REG          (DR_REG_EFUSE_BASE + 0x1a4)
+/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[16:9] ;default: 8'h0 ; */
+/*description: */
+#define EFUSE_REPEAT_ERR_CNT  0x000000FF
+#define EFUSE_REPEAT_ERR_CNT_M  ((EFUSE_REPEAT_ERR_CNT_V)<<(EFUSE_REPEAT_ERR_CNT_S))
+#define EFUSE_REPEAT_ERR_CNT_V  0xFF
+#define EFUSE_REPEAT_ERR_CNT_S  9
+/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_OTP_VDDQ_IS_SW  (BIT(8))
+#define EFUSE_OTP_VDDQ_IS_SW_M  (BIT(8))
+#define EFUSE_OTP_VDDQ_IS_SW_V  0x1
+#define EFUSE_OTP_VDDQ_IS_SW_S  8
+/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_OTP_PGENB_SW  (BIT(7))
+#define EFUSE_OTP_PGENB_SW_M  (BIT(7))
+#define EFUSE_OTP_PGENB_SW_V  0x1
+#define EFUSE_OTP_PGENB_SW_S  7
+/* EFUSE_OTP_CSB_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_OTP_CSB_SW  (BIT(6))
+#define EFUSE_OTP_CSB_SW_M  (BIT(6))
+#define EFUSE_OTP_CSB_SW_V  0x1
+#define EFUSE_OTP_CSB_SW_S  6
+/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_OTP_STROBE_SW  (BIT(5))
+#define EFUSE_OTP_STROBE_SW_M  (BIT(5))
+#define EFUSE_OTP_STROBE_SW_V  0x1
+#define EFUSE_OTP_STROBE_SW_S  5
+/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_OTP_VDDQ_C_SYNC2  (BIT(4))
+#define EFUSE_OTP_VDDQ_C_SYNC2_M  (BIT(4))
+#define EFUSE_OTP_VDDQ_C_SYNC2_V  0x1
+#define EFUSE_OTP_VDDQ_C_SYNC2_S  4
+/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_OTP_LOAD_SW  (BIT(3))
+#define EFUSE_OTP_LOAD_SW_M  (BIT(3))
+#define EFUSE_OTP_LOAD_SW_V  0x1
+#define EFUSE_OTP_LOAD_SW_S  3
+/* EFUSE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define EFUSE_STATE  0x00000007
+#define EFUSE_STATE_M  ((EFUSE_STATE_V)<<(EFUSE_STATE_S))
+#define EFUSE_STATE_V  0x7
+#define EFUSE_STATE_S  0
+
+#define EFUSE_CMD_REG          (DR_REG_EFUSE_BASE + 0x1a8)
+/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'b0 ; */
+/*description: */
+#define EFUSE_BLK_NUM  0x0000000F
+#define EFUSE_BLK_NUM_M  ((EFUSE_BLK_NUM_V)<<(EFUSE_BLK_NUM_S))
+#define EFUSE_BLK_NUM_V  0xF
+#define EFUSE_BLK_NUM_S  2
+/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_PGM_CMD  (BIT(1))
+#define EFUSE_PGM_CMD_M  (BIT(1))
+#define EFUSE_PGM_CMD_V  0x1
+#define EFUSE_PGM_CMD_S  1
+/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_READ_CMD  (BIT(0))
+#define EFUSE_READ_CMD_M  (BIT(0))
+#define EFUSE_READ_CMD_V  0x1
+#define EFUSE_READ_CMD_S  0
+
+#define EFUSE_INT_RAW_REG          (DR_REG_EFUSE_BASE + 0x1ac)
+/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_PGM_DONE_INT_RAW  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_RAW_V  0x1
+#define EFUSE_PGM_DONE_INT_RAW_S  1
+/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_READ_DONE_INT_RAW  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_RAW_V  0x1
+#define EFUSE_READ_DONE_INT_RAW_S  0
+
+#define EFUSE_INT_ST_REG          (DR_REG_EFUSE_BASE + 0x1b0)
+/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_PGM_DONE_INT_ST  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ST_V  0x1
+#define EFUSE_PGM_DONE_INT_ST_S  1
+/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_READ_DONE_INT_ST  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ST_V  0x1
+#define EFUSE_READ_DONE_INT_ST_S  0
+
+#define EFUSE_INT_ENA_REG          (DR_REG_EFUSE_BASE + 0x1b4)
+/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_PGM_DONE_INT_ENA  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_ENA_V  0x1
+#define EFUSE_PGM_DONE_INT_ENA_S  1
+/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_READ_DONE_INT_ENA  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_ENA_V  0x1
+#define EFUSE_READ_DONE_INT_ENA_S  0
+
+#define EFUSE_INT_CLR_REG          (DR_REG_EFUSE_BASE + 0x1b8)
+/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_PGM_DONE_INT_CLR  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_M  (BIT(1))
+#define EFUSE_PGM_DONE_INT_CLR_V  0x1
+#define EFUSE_PGM_DONE_INT_CLR_S  1
+/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_READ_DONE_INT_CLR  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_M  (BIT(0))
+#define EFUSE_READ_DONE_INT_CLR_V  0x1
+#define EFUSE_READ_DONE_INT_CLR_S  0
+
+#define EFUSE_DAC_CONF_REG          (DR_REG_EFUSE_BASE + 0x1bc)
+/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define EFUSE_DAC_CLK_PAD_SEL  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_M  (BIT(8))
+#define EFUSE_DAC_CLK_PAD_SEL_V  0x1
+#define EFUSE_DAC_CLK_PAD_SEL_S  8
+/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd40 ; */
+/*description: */
+#define EFUSE_DAC_CLK_DIV  0x000000FF
+#define EFUSE_DAC_CLK_DIV_M  ((EFUSE_DAC_CLK_DIV_V)<<(EFUSE_DAC_CLK_DIV_S))
+#define EFUSE_DAC_CLK_DIV_V  0xFF
+#define EFUSE_DAC_CLK_DIV_S  0
+
+#define EFUSE_RD_TIM_CONF_REG          (DR_REG_EFUSE_BASE + 0x1c0)
+/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */
+/*description: */
+#define EFUSE_READ_INIT_NUM  0x000000FF
+#define EFUSE_READ_INIT_NUM_M  ((EFUSE_READ_INIT_NUM_V)<<(EFUSE_READ_INIT_NUM_S))
+#define EFUSE_READ_INIT_NUM_V  0xFF
+#define EFUSE_READ_INIT_NUM_S  24
+/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define EFUSE_TSUR_A  0x000000FF
+#define EFUSE_TSUR_A_M  ((EFUSE_TSUR_A_V)<<(EFUSE_TSUR_A_S))
+#define EFUSE_TSUR_A_V  0xFF
+#define EFUSE_TSUR_A_S  16
+/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
+/*description: */
+#define EFUSE_TRD  0x000000FF
+#define EFUSE_TRD_M  ((EFUSE_TRD_V)<<(EFUSE_TRD_S))
+#define EFUSE_TRD_V  0xFF
+#define EFUSE_TRD_S  8
+/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: */
+#define EFUSE_THR_A  0x000000FF
+#define EFUSE_THR_A_M  ((EFUSE_THR_A_V)<<(EFUSE_THR_A_S))
+#define EFUSE_THR_A_V  0xFF
+#define EFUSE_THR_A_S  0
+
+#define EFUSE_WR_TIM_CONF0_REG          (DR_REG_EFUSE_BASE + 0x1c4)
+/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'h190 ; */
+/*description: */
+#define EFUSE_TPGM  0x0000FFFF
+#define EFUSE_TPGM_M  ((EFUSE_TPGM_V)<<(EFUSE_TPGM_S))
+#define EFUSE_TPGM_V  0xFFFF
+#define EFUSE_TPGM_S  16
+/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h2 ; */
+/*description: */
+#define EFUSE_TPGM_INACTIVE  0x000000FF
+#define EFUSE_TPGM_INACTIVE_M  ((EFUSE_TPGM_INACTIVE_V)<<(EFUSE_TPGM_INACTIVE_S))
+#define EFUSE_TPGM_INACTIVE_V  0xFF
+#define EFUSE_TPGM_INACTIVE_S  8
+/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: */
+#define EFUSE_THP_A  0x000000FF
+#define EFUSE_THP_A_M  ((EFUSE_THP_A_V)<<(EFUSE_THP_A_S))
+#define EFUSE_THP_A_V  0xFF
+#define EFUSE_THP_A_S  0
+
+#define EFUSE_WR_TIM_CONF1_REG          (DR_REG_EFUSE_BASE + 0x1c8)
+/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h7000 ; */
+/*description: */
+#define EFUSE_PWR_ON_NUM  0x0000FFFF
+#define EFUSE_PWR_ON_NUM_M  ((EFUSE_PWR_ON_NUM_V)<<(EFUSE_PWR_ON_NUM_S))
+#define EFUSE_PWR_ON_NUM_V  0xFFFF
+#define EFUSE_PWR_ON_NUM_S  8
+/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
+/*description: */
+#define EFUSE_TSUP_A  0x000000FF
+#define EFUSE_TSUP_A_M  ((EFUSE_TSUP_A_V)<<(EFUSE_TSUP_A_S))
+#define EFUSE_TSUP_A_V  0xFF
+#define EFUSE_TSUP_A_S  0
+
+#define EFUSE_DATE_REG          (DR_REG_EFUSE_BASE + 0x1FC)
+/* EFUSE_DATE : R/W ;bitpos:[31:0] ;default: 32'h18101600 ; */
+/*description: */
+#define EFUSE_DATE  0xFFFFFFFF
+#define EFUSE_DATE_M  ((EFUSE_DATE_V)<<(EFUSE_DATE_S))
+#define EFUSE_DATE_V  0xFFFFFFFF
+#define EFUSE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*_SOC_EFUSE_REG_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/efuse_struct.h b/components/soc/esp32s2beta/include/soc/efuse_struct.h
new file mode 100644
index 000000000..bde2b54f9
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/efuse_struct.h
@@ -0,0 +1,407 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_EFUSE_STRUCT_H_
+#define _SOC_EFUSE_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t rd_efuse_wr_dis:   16;
+            uint32_t rd_efuse_rd_dis:    4;
+            uint32_t rd_flash_crypt_cnt: 8;
+            uint32_t reserved28:         4;
+        };
+        uint32_t val;
+    } blk0_rdata0;
+    uint32_t blk0_rdata1;                           /**/
+    union {
+        struct {
+            uint32_t rd_wifi_mac_crc_high:24;
+            uint32_t reserved24:           8;
+        };
+        uint32_t val;
+    } blk0_rdata2;
+    union {
+        struct {
+            uint32_t rd_soft_disable_jtag:  1;
+            uint32_t rd_chip_ver_dis_bt:    1;
+            uint32_t rd_chip_ver_32pad:     1;
+            uint32_t rd_chip_ver_dis_cache: 1;
+            uint32_t rd_chip_ver_reserve:  13;
+            uint32_t reserved17:           15;
+        };
+        uint32_t val;
+    } blk0_rdata3;
+    union {
+        struct {
+            uint32_t rd_ck8m_freq:  8;
+            uint32_t rd_sdio_drefh: 2;
+            uint32_t rd_sdio_drefm: 2;
+            uint32_t rd_sdio_drefl: 2;
+            uint32_t rd_xpd_sdio:   1;
+            uint32_t rd_sdio_tieh:  1;
+            uint32_t rd_sdio_force: 1;
+            uint32_t reserved17:   15;
+        };
+        uint32_t val;
+    } blk0_rdata4;
+    union {
+        struct {
+            uint32_t rd_spi_pad_config:    20;
+            uint32_t rd_tsens_dos:          4;
+            uint32_t rd_reserve_use1:       4;
+            uint32_t rd_flash_crypt_config: 4;
+        };
+        uint32_t val;
+    } blk0_rdata5;
+    union {
+        struct {
+            uint32_t rd_coding_scheme:      2;
+            uint32_t rd_dig_reserve:        1;
+            uint32_t rd_disable_sdio_host:  1;
+            uint32_t rd_abs_done_0:         1;
+            uint32_t rd_abs_done_1:         1;
+            uint32_t rd_hard_disable_jtag:  1;
+            uint32_t rd_disable_dl_encrypt: 1;
+            uint32_t rd_disable_dl_decrypt: 1;
+            uint32_t rd_disable_dl_cache:   1;
+            uint32_t rd_key_status:         1;
+            uint32_t reserved11:           21;
+        };
+        uint32_t val;
+    } blk0_rdata6;
+    union {
+        struct {
+            uint32_t wr_dis:         16;
+            uint32_t rd_dis:          4;
+            uint32_t flash_crypt_cnt: 8;
+            uint32_t reserved28:      4;
+        };
+        uint32_t val;
+    } blk0_wdata0;
+    uint32_t blk0_wdata1;                           /**/
+    union {
+        struct {
+            uint32_t wifi_mac_crc_high:24;
+            uint32_t reserved24:        8;
+        };
+        uint32_t val;
+    } blk0_wdata2;
+    union {
+        struct {
+            uint32_t soft_disable_jtag:  1;
+            uint32_t chip_ver_dis_bt:    1;
+            uint32_t chip_ver_32pad:     1;
+            uint32_t chip_ver_dis_cache: 1;
+            uint32_t chip_ver_reserve:  13;
+            uint32_t reserved17:        15;
+        };
+        uint32_t val;
+    } blk0_wdata3;
+    union {
+        struct {
+            uint32_t ck8m_freq:  8;
+            uint32_t sdio_drefh: 2;
+            uint32_t sdio_drefm: 2;
+            uint32_t sdio_drefl: 2;
+            uint32_t xpd_sdio:   1;
+            uint32_t sdio_tieh:  1;
+            uint32_t sdio_force: 1;
+            uint32_t reserved17:15;
+        };
+        uint32_t val;
+    } blk0_wdata4;
+    union {
+        struct {
+            uint32_t spi_pad_config:    20;
+            uint32_t tsens_dos:          4;
+            uint32_t reserve_use1:       4;
+            uint32_t flash_crypt_config: 4;
+        };
+        uint32_t val;
+    } blk0_wdata5;
+    union {
+        struct {
+            uint32_t coding_scheme:      2;
+            uint32_t dig_reserve:        1;
+            uint32_t disable_sdio_host:  1;
+            uint32_t abs_done_0:         1;
+            uint32_t abs_done_1:         1;
+            uint32_t hard_disable_jtag:  1;
+            uint32_t disable_dl_encrypt: 1;
+            uint32_t disable_dl_decrypt: 1;
+            uint32_t disable_dl_cache:   1;
+            uint32_t key_status:         1;
+            uint32_t reserved11:        21;
+        };
+        uint32_t val;
+    } blk0_wdata6;
+    uint32_t blk1_rdata0;                           /**/
+    uint32_t blk1_rdata1;                           /**/
+    uint32_t blk1_rdata2;                           /**/
+    uint32_t blk1_rdata3;                           /**/
+    uint32_t blk1_rdata4;                           /**/
+    uint32_t blk1_rdata5;                           /**/
+    uint32_t blk1_rdata6;                           /**/
+    uint32_t blk1_rdata7;                           /**/
+    uint32_t blk2_rdata0;                           /**/
+    uint32_t blk2_rdata1;                           /**/
+    uint32_t blk2_rdata2;                           /**/
+    uint32_t blk2_rdata3;                           /**/
+    uint32_t blk2_rdata4;                           /**/
+    uint32_t blk2_rdata5;                           /**/
+    uint32_t blk2_rdata6;                           /**/
+    uint32_t blk2_rdata7;                           /**/
+    uint32_t blk3_rdata0;                           /**/
+    uint32_t blk3_rdata1;                           /**/
+    uint32_t blk3_rdata2;                           /**/
+    uint32_t blk3_rdata3;                           /**/
+    uint32_t blk3_rdata4;                           /**/
+    uint32_t blk3_rdata5;                           /**/
+    uint32_t blk3_rdata6;                           /**/
+    uint32_t blk3_rdata7;                           /**/
+    uint32_t blk1_wdata0;                           /**/
+    uint32_t blk1_wdata1;                           /**/
+    uint32_t blk1_wdata2;                           /**/
+    uint32_t blk1_wdata3;                           /**/
+    uint32_t blk1_wdata4;                           /**/
+    uint32_t blk1_wdata5;                           /**/
+    uint32_t blk1_wdata6;                           /**/
+    uint32_t blk1_wdata7;                           /**/
+    uint32_t blk2_wdata0;                           /**/
+    uint32_t blk2_wdata1;                           /**/
+    uint32_t blk2_wdata2;                           /**/
+    uint32_t blk2_wdata3;                           /**/
+    uint32_t blk2_wdata4;                           /**/
+    uint32_t blk2_wdata5;                           /**/
+    uint32_t blk2_wdata6;                           /**/
+    uint32_t blk2_wdata7;                           /**/
+    uint32_t blk3_wdata0;                           /**/
+    uint32_t blk3_wdata1;                           /**/
+    uint32_t blk3_wdata2;                           /**/
+    uint32_t blk3_wdata3;                           /**/
+    uint32_t blk3_wdata4;                           /**/
+    uint32_t blk3_wdata5;                           /**/
+    uint32_t blk3_wdata6;                           /**/
+    uint32_t blk3_wdata7;                           /**/
+    union {
+        struct {
+            uint32_t reserved0: 16;
+            uint32_t clk_en:     1;
+            uint32_t reserved17:15;
+        };
+        uint32_t val;
+    } clk;
+    union {
+        struct {
+            uint32_t op_code:           16;
+            uint32_t force_no_wr_rd_dis: 1;
+            uint32_t reserved17:        15;
+        };
+        uint32_t val;
+    } conf;
+    uint32_t status;                                /**/
+    union {
+        struct {
+            uint32_t read_cmd:   1;
+            uint32_t pgm_cmd:    1;
+            uint32_t reserved2: 30;
+        };
+        uint32_t val;
+    } cmd;
+    union {
+        struct {
+            uint32_t read_done:         1;
+            uint32_t pgm_done:          1;
+            uint32_t reserved2:        30;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t read_done:        1;
+            uint32_t pgm_done:         1;
+            uint32_t reserved2:       30;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t read_done:         1;
+            uint32_t pgm_done:          1;
+            uint32_t reserved2:        30;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t read_done:         1;
+            uint32_t pgm_done:          1;
+            uint32_t reserved2:        30;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t dac_clk_div:     8;
+            uint32_t dac_clk_pad_sel: 1;
+            uint32_t reserved9:      23;
+        };
+        uint32_t val;
+    } dac_conf;
+    union {
+        struct {
+            uint32_t dec_warnings:12;
+            uint32_t reserved12:  20;
+        };
+        uint32_t val;
+    } dec_status;
+    union {
+        struct {
+            uint32_t thr_a:         8;
+            uint32_t trd:           8;
+            uint32_t tsur_a:        8;
+            uint32_t read_init_num: 8;
+        };
+        uint32_t val;
+    } rd_tim_conf;
+    union {
+        struct {
+            uint32_t thp_a:         8;
+            uint32_t tpgm_inactive: 8;
+            uint32_t tpgm:         16;
+        };
+        uint32_t val;
+    } wr_tim_conf0;
+    union {
+        struct {
+            uint32_t tsup_a:     8;
+            uint32_t pwr_on_num:16;
+            uint32_t reserved24: 8;
+        };
+        uint32_t val;
+    } wr_tim_conf1;
+    union {
+        struct {
+            uint32_t rd_dis_err:           4;
+            uint32_t chip_ver_reserve_err:13;
+            uint32_t ck8m_freq_err:        8;
+            uint32_t sdio_drefh_err:       2;
+            uint32_t sdio_drefm_err:       2;
+            uint32_t sdio_drefl_err:       2;
+            uint32_t key_status_err:       1;
+        };
+        uint32_t val;
+    } repeat_err0;
+    union {
+        struct {
+            uint32_t spi_pad_config_err:    20;
+            uint32_t flash_crypt_config_err: 4;
+            uint32_t tsens_dos_err:          4;
+            uint32_t reserve_use1_err:       4;
+        };
+        uint32_t val;
+    } repeat_err1;
+    union {
+        struct {
+            uint32_t abs_done_0_err:         1;
+            uint32_t abs_done_1_err:         1;
+            uint32_t hard_disable_jtag_err:  1;
+            uint32_t disable_dl_encrypt_err: 1;
+            uint32_t disable_dl_decrypt_err: 1;
+            uint32_t disable_dl_cache_err:   1;
+            uint32_t disable_sdio_host_err:  1;
+            uint32_t dig_reserve_err:        1;
+            uint32_t soft_disable_jtag_err:  1;
+            uint32_t chip_ver_dis_bt_err:    1;
+            uint32_t chip_ver_32pad_err:     1;
+            uint32_t chip_ver_dis_cache_err: 1;
+            uint32_t xpd_sdio_err:           1;
+            uint32_t sdio_tieh_err:          1;
+            uint32_t sdio_force_err:         1;
+            uint32_t reserved15:            17;
+        };
+        uint32_t val;
+    } repeat_err2;
+    uint32_t repeat_blk1_err0;                      /**/
+    uint32_t repeat_blk1_err1;                      /**/
+    uint32_t repeat_blk1_err2;                      /**/
+    uint32_t repeat_blk1_err3;                      /**/
+    uint32_t repeat_blk2_err0;                      /**/
+    uint32_t repeat_blk2_err1;                      /**/
+    uint32_t repeat_blk2_err2;                      /**/
+    uint32_t repeat_blk2_err3;                      /**/
+    uint32_t repeat_blk3_err0;                      /**/
+    uint32_t repeat_blk3_err1;                      /**/
+    uint32_t repeat_blk3_err2;                      /**/
+    uint32_t repeat_blk3_err3;                      /**/
+    union {
+        struct {
+            uint32_t rs_errornum_blk1: 4;
+            uint32_t rs_fail_blk1:     1;
+            uint32_t rs_errornum_blk2: 4;
+            uint32_t rs_fail_blk2:     1;
+            uint32_t rs_errornum_blk3: 4;
+            uint32_t rs_fail_blk3:     1;
+            uint32_t reserved15:      17;
+        };
+        uint32_t val;
+    } rs_state;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t date;                                  /**/
+} efuse_dev_t;
+extern efuse_dev_t EFUSE;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_EFUSE_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/extmem_reg.h b/components/soc/esp32s2beta/include/soc/extmem_reg.h
new file mode 100644
index 000000000..815cde7cc
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/extmem_reg.h
@@ -0,0 +1,1459 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_EXTMEM_REG_H_
+#define _SOC_EXTMEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define DPORT_PRO_DCACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x000)
+/* DPORT_PRO_DCACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_UNLOCK_DONE  (BIT(23))
+#define DPORT_PRO_DCACHE_UNLOCK_DONE_M  (BIT(23))
+#define DPORT_PRO_DCACHE_UNLOCK_DONE_V  0x1
+#define DPORT_PRO_DCACHE_UNLOCK_DONE_S  23
+/* DPORT_PRO_DCACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_UNLOCK_ENA  (BIT(22))
+#define DPORT_PRO_DCACHE_UNLOCK_ENA_M  (BIT(22))
+#define DPORT_PRO_DCACHE_UNLOCK_ENA_V  0x1
+#define DPORT_PRO_DCACHE_UNLOCK_ENA_S  22
+/* DPORT_PRO_DCACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_DONE  (BIT(21))
+#define DPORT_PRO_DCACHE_PRELOAD_DONE_M  (BIT(21))
+#define DPORT_PRO_DCACHE_PRELOAD_DONE_V  0x1
+#define DPORT_PRO_DCACHE_PRELOAD_DONE_S  21
+/* DPORT_PRO_DCACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_ENA  (BIT(20))
+#define DPORT_PRO_DCACHE_PRELOAD_ENA_M  (BIT(20))
+#define DPORT_PRO_DCACHE_PRELOAD_ENA_V  0x1
+#define DPORT_PRO_DCACHE_PRELOAD_ENA_S  20
+/* DPORT_PRO_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_DONE  (BIT(19))
+#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_M  (BIT(19))
+#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_V  0x1
+#define DPORT_PRO_DCACHE_AUTOLOAD_DONE_S  19
+/* DPORT_PRO_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_ENA  (BIT(18))
+#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_M  (BIT(18))
+#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_V  0x1
+#define DPORT_PRO_DCACHE_AUTOLOAD_ENA_S  18
+/* DPORT_PRO_DCACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_LOCK1_EN  (BIT(15))
+#define DPORT_PRO_DCACHE_LOCK1_EN_M  (BIT(15))
+#define DPORT_PRO_DCACHE_LOCK1_EN_V  0x1
+#define DPORT_PRO_DCACHE_LOCK1_EN_S  15
+/* DPORT_PRO_DCACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_LOCK0_EN  (BIT(14))
+#define DPORT_PRO_DCACHE_LOCK0_EN_M  (BIT(14))
+#define DPORT_PRO_DCACHE_LOCK0_EN_V  0x1
+#define DPORT_PRO_DCACHE_LOCK0_EN_S  14
+/* DPORT_PRO_DCACHE_CLEAN_DONE : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_CLEAN_DONE  (BIT(13))
+#define DPORT_PRO_DCACHE_CLEAN_DONE_M  (BIT(13))
+#define DPORT_PRO_DCACHE_CLEAN_DONE_V  0x1
+#define DPORT_PRO_DCACHE_CLEAN_DONE_S  13
+/* DPORT_PRO_DCACHE_CLEAN_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_CLEAN_ENA  (BIT(12))
+#define DPORT_PRO_DCACHE_CLEAN_ENA_M  (BIT(12))
+#define DPORT_PRO_DCACHE_CLEAN_ENA_V  0x1
+#define DPORT_PRO_DCACHE_CLEAN_ENA_S  12
+/* DPORT_PRO_DCACHE_FLUSH_DONE : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_FLUSH_DONE  (BIT(11))
+#define DPORT_PRO_DCACHE_FLUSH_DONE_M  (BIT(11))
+#define DPORT_PRO_DCACHE_FLUSH_DONE_V  0x1
+#define DPORT_PRO_DCACHE_FLUSH_DONE_S  11
+/* DPORT_PRO_DCACHE_FLUSH_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_FLUSH_ENA  (BIT(10))
+#define DPORT_PRO_DCACHE_FLUSH_ENA_M  (BIT(10))
+#define DPORT_PRO_DCACHE_FLUSH_ENA_V  0x1
+#define DPORT_PRO_DCACHE_FLUSH_ENA_S  10
+/* DPORT_PRO_DCACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_INVALIDATE_DONE  (BIT(9))
+#define DPORT_PRO_DCACHE_INVALIDATE_DONE_M  (BIT(9))
+#define DPORT_PRO_DCACHE_INVALIDATE_DONE_V  0x1
+#define DPORT_PRO_DCACHE_INVALIDATE_DONE_S  9
+/* DPORT_PRO_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_INVALIDATE_ENA  (BIT(8))
+#define DPORT_PRO_DCACHE_INVALIDATE_ENA_M  (BIT(8))
+#define DPORT_PRO_DCACHE_INVALIDATE_ENA_V  0x1
+#define DPORT_PRO_DCACHE_INVALIDATE_ENA_S  8
+/* DPORT_PRO_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE  0x00000003
+#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_M  ((DPORT_PRO_DCACHE_BLOCKSIZE_MODE_V)<<(DPORT_PRO_DCACHE_BLOCKSIZE_MODE_S))
+#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_V  0x3
+#define DPORT_PRO_DCACHE_BLOCKSIZE_MODE_S  3
+/* DPORT_PRO_DCACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_SETSIZE_MODE  (BIT(2))
+#define DPORT_PRO_DCACHE_SETSIZE_MODE_M  (BIT(2))
+#define DPORT_PRO_DCACHE_SETSIZE_MODE_V  0x1
+#define DPORT_PRO_DCACHE_SETSIZE_MODE_S  2
+/* DPORT_PRO_DCACHE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_MODE  (BIT(1))
+#define DPORT_PRO_DCACHE_MODE_M  (BIT(1))
+#define DPORT_PRO_DCACHE_MODE_V  0x1
+#define DPORT_PRO_DCACHE_MODE_S  1
+/* DPORT_PRO_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_ENABLE  (BIT(0))
+#define DPORT_PRO_DCACHE_ENABLE_M  (BIT(0))
+#define DPORT_PRO_DCACHE_ENABLE_V  0x1
+#define DPORT_PRO_DCACHE_ENABLE_S  0
+
+#define DPORT_PRO_DCACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x004)
+/* DPORT_PRO_DCACHE_MASK_BUS3 : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_MASK_BUS3  (BIT(3))
+#define DPORT_PRO_DCACHE_MASK_BUS3_M  (BIT(3))
+#define DPORT_PRO_DCACHE_MASK_BUS3_V  0x1
+#define DPORT_PRO_DCACHE_MASK_BUS3_S  3
+/* DPORT_PRO_DCACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_MASK_BUS2  (BIT(2))
+#define DPORT_PRO_DCACHE_MASK_BUS2_M  (BIT(2))
+#define DPORT_PRO_DCACHE_MASK_BUS2_V  0x1
+#define DPORT_PRO_DCACHE_MASK_BUS2_S  2
+/* DPORT_PRO_DCACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_MASK_BUS1  (BIT(1))
+#define DPORT_PRO_DCACHE_MASK_BUS1_M  (BIT(1))
+#define DPORT_PRO_DCACHE_MASK_BUS1_V  0x1
+#define DPORT_PRO_DCACHE_MASK_BUS1_S  1
+/* DPORT_PRO_DCACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_MASK_BUS0  (BIT(0))
+#define DPORT_PRO_DCACHE_MASK_BUS0_M  (BIT(0))
+#define DPORT_PRO_DCACHE_MASK_BUS0_V  0x1
+#define DPORT_PRO_DCACHE_MASK_BUS0_S  0
+#define DPORT_PRO_DCACHE_MASK_DRAM0 DPORT_PRO_DCACHE_MASK_BUS0
+#define DPORT_PRO_DCACHE_MASK_DRAM1 DPORT_PRO_DCACHE_MASK_BUS1
+#define DPORT_PRO_DCACHE_MASK_DPORT DPORT_PRO_DCACHE_MASK_BUS2
+#define DPORT_PRO_DCACHE_MASK_DROM0 DPORT_PRO_DCACHE_MASK_BUS3
+
+#define DPORT_PRO_DCACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x008)
+/* DPORT_PRO_DCACHE_TAG_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_TAG_MEM_PD  (BIT(1))
+#define DPORT_PRO_DCACHE_TAG_MEM_PD_M  (BIT(1))
+#define DPORT_PRO_DCACHE_TAG_MEM_PD_V  0x1
+#define DPORT_PRO_DCACHE_TAG_MEM_PD_S  1
+/* DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON  (BIT(0))
+#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
+#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_V  0x1
+#define DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON_S  0
+
+#define DPORT_PRO_DCACHE_LOCK0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x00C)
+/* DPORT_PRO_DCACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_LOCK0_ADDR  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_LOCK0_ADDR_M  ((DPORT_PRO_DCACHE_LOCK0_ADDR_V)<<(DPORT_PRO_DCACHE_LOCK0_ADDR_S))
+#define DPORT_PRO_DCACHE_LOCK0_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_LOCK0_ADDR_S  0
+
+#define DPORT_PRO_DCACHE_LOCK0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x010)
+/* DPORT_PRO_DCACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_LOCK0_SIZE  0x0000FFFF
+#define DPORT_PRO_DCACHE_LOCK0_SIZE_M  ((DPORT_PRO_DCACHE_LOCK0_SIZE_V)<<(DPORT_PRO_DCACHE_LOCK0_SIZE_S))
+#define DPORT_PRO_DCACHE_LOCK0_SIZE_V  0xFFFF
+#define DPORT_PRO_DCACHE_LOCK0_SIZE_S  0
+
+#define DPORT_PRO_DCACHE_LOCK1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x014)
+/* DPORT_PRO_DCACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_LOCK1_ADDR  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_LOCK1_ADDR_M  ((DPORT_PRO_DCACHE_LOCK1_ADDR_V)<<(DPORT_PRO_DCACHE_LOCK1_ADDR_S))
+#define DPORT_PRO_DCACHE_LOCK1_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_LOCK1_ADDR_S  0
+
+#define DPORT_PRO_DCACHE_LOCK1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x018)
+/* DPORT_PRO_DCACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_LOCK1_SIZE  0x0000FFFF
+#define DPORT_PRO_DCACHE_LOCK1_SIZE_M  ((DPORT_PRO_DCACHE_LOCK1_SIZE_V)<<(DPORT_PRO_DCACHE_LOCK1_SIZE_S))
+#define DPORT_PRO_DCACHE_LOCK1_SIZE_V  0xFFFF
+#define DPORT_PRO_DCACHE_LOCK1_SIZE_S  0
+
+#define DPORT_PRO_DCACHE_MEM_SYNC0_REG          (DR_REG_EXTMEM_BASE + 0x01C)
+/* DPORT_PRO_DCACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_MEMSYNC_ADDR  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_M  ((DPORT_PRO_DCACHE_MEMSYNC_ADDR_V)<<(DPORT_PRO_DCACHE_MEMSYNC_ADDR_S))
+#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_MEMSYNC_ADDR_S  0
+
+#define DPORT_PRO_DCACHE_MEM_SYNC1_REG          (DR_REG_EXTMEM_BASE + 0x020)
+/* DPORT_PRO_DCACHE_MEMSYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h400000 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_MEMSYNC_SIZE  0x007FFFFF
+#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_M  ((DPORT_PRO_DCACHE_MEMSYNC_SIZE_V)<<(DPORT_PRO_DCACHE_MEMSYNC_SIZE_S))
+#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_V  0x7FFFFF
+#define DPORT_PRO_DCACHE_MEMSYNC_SIZE_S  0
+
+#define DPORT_PRO_DCACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x024)
+/* DPORT_PRO_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_ADDR  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_PRELOAD_ADDR_M  ((DPORT_PRO_DCACHE_PRELOAD_ADDR_V)<<(DPORT_PRO_DCACHE_PRELOAD_ADDR_S))
+#define DPORT_PRO_DCACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_PRELOAD_ADDR_S  0
+
+#define DPORT_PRO_DCACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x028)
+/* DPORT_PRO_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_ORDER  (BIT(16))
+#define DPORT_PRO_DCACHE_PRELOAD_ORDER_M  (BIT(16))
+#define DPORT_PRO_DCACHE_PRELOAD_ORDER_V  0x1
+#define DPORT_PRO_DCACHE_PRELOAD_ORDER_S  16
+/* DPORT_PRO_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h8000 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_SIZE  0x0000FFFF
+#define DPORT_PRO_DCACHE_PRELOAD_SIZE_M  ((DPORT_PRO_DCACHE_PRELOAD_SIZE_V)<<(DPORT_PRO_DCACHE_PRELOAD_SIZE_S))
+#define DPORT_PRO_DCACHE_PRELOAD_SIZE_V  0xFFFF
+#define DPORT_PRO_DCACHE_PRELOAD_SIZE_S  0
+
+#define DPORT_PRO_DCACHE_AUTOLOAD_CFG_REG          (DR_REG_EXTMEM_BASE + 0x02C)
+/* DPORT_PRO_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[21:6] ;default: 16'h1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE  0x0000FFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SIZE_S))
+#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_V  0xFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SIZE_S  6
+/* DPORT_PRO_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_RQST  0x00000003
+#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_M  ((DPORT_PRO_DCACHE_AUTOLOAD_RQST_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_RQST_S))
+#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_V  0x3
+#define DPORT_PRO_DCACHE_AUTOLOAD_RQST_S  4
+/* DPORT_PRO_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER  (BIT(3))
+#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_M  (BIT(3))
+#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_V  0x1
+#define DPORT_PRO_DCACHE_AUTOLOAD_ORDER_S  3
+/* DPORT_PRO_DCACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_STEP  0x00000003
+#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_M  ((DPORT_PRO_DCACHE_AUTOLOAD_STEP_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_STEP_S))
+#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_V  0x3
+#define DPORT_PRO_DCACHE_AUTOLOAD_STEP_S  1
+/* DPORT_PRO_DCACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_MODE  (BIT(0))
+#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_M  (BIT(0))
+#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_V  0x1
+#define DPORT_PRO_DCACHE_AUTOLOAD_MODE_S  0
+
+#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x030)
+/* DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S))
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x034)
+/* DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE  0x00FFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S))
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x038)
+/* DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S))
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define DPORT_PRO_DCACHE_AUTOLOAD_SECTION1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x03C)
+/* DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE  0x00FFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_M  ((DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S))
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
+#define DPORT_PRO_DCACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define DPORT_PRO_ICACHE_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x040)
+/* DPORT_PRO_ICACHE_UNLOCK_DONE : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_UNLOCK_DONE  (BIT(23))
+#define DPORT_PRO_ICACHE_UNLOCK_DONE_M  (BIT(23))
+#define DPORT_PRO_ICACHE_UNLOCK_DONE_V  0x1
+#define DPORT_PRO_ICACHE_UNLOCK_DONE_S  23
+/* DPORT_PRO_ICACHE_UNLOCK_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_UNLOCK_ENA  (BIT(22))
+#define DPORT_PRO_ICACHE_UNLOCK_ENA_M  (BIT(22))
+#define DPORT_PRO_ICACHE_UNLOCK_ENA_V  0x1
+#define DPORT_PRO_ICACHE_UNLOCK_ENA_S  22
+/* DPORT_PRO_ICACHE_PRELOAD_DONE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_DONE  (BIT(21))
+#define DPORT_PRO_ICACHE_PRELOAD_DONE_M  (BIT(21))
+#define DPORT_PRO_ICACHE_PRELOAD_DONE_V  0x1
+#define DPORT_PRO_ICACHE_PRELOAD_DONE_S  21
+/* DPORT_PRO_ICACHE_PRELOAD_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_ENA  (BIT(20))
+#define DPORT_PRO_ICACHE_PRELOAD_ENA_M  (BIT(20))
+#define DPORT_PRO_ICACHE_PRELOAD_ENA_V  0x1
+#define DPORT_PRO_ICACHE_PRELOAD_ENA_S  20
+/* DPORT_PRO_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_DONE  (BIT(19))
+#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_M  (BIT(19))
+#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_V  0x1
+#define DPORT_PRO_ICACHE_AUTOLOAD_DONE_S  19
+/* DPORT_PRO_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_ENA  (BIT(18))
+#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_M  (BIT(18))
+#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_V  0x1
+#define DPORT_PRO_ICACHE_AUTOLOAD_ENA_S  18
+/* DPORT_PRO_ICACHE_LOCK1_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_LOCK1_EN  (BIT(15))
+#define DPORT_PRO_ICACHE_LOCK1_EN_M  (BIT(15))
+#define DPORT_PRO_ICACHE_LOCK1_EN_V  0x1
+#define DPORT_PRO_ICACHE_LOCK1_EN_S  15
+/* DPORT_PRO_ICACHE_LOCK0_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_LOCK0_EN  (BIT(14))
+#define DPORT_PRO_ICACHE_LOCK0_EN_M  (BIT(14))
+#define DPORT_PRO_ICACHE_LOCK0_EN_V  0x1
+#define DPORT_PRO_ICACHE_LOCK0_EN_S  14
+/* DPORT_PRO_ICACHE_INVALIDATE_DONE : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_INVALIDATE_DONE  (BIT(9))
+#define DPORT_PRO_ICACHE_INVALIDATE_DONE_M  (BIT(9))
+#define DPORT_PRO_ICACHE_INVALIDATE_DONE_V  0x1
+#define DPORT_PRO_ICACHE_INVALIDATE_DONE_S  9
+/* DPORT_PRO_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_INVALIDATE_ENA  (BIT(8))
+#define DPORT_PRO_ICACHE_INVALIDATE_ENA_M  (BIT(8))
+#define DPORT_PRO_ICACHE_INVALIDATE_ENA_V  0x1
+#define DPORT_PRO_ICACHE_INVALIDATE_ENA_S  8
+/* DPORT_PRO_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE  0x00000003
+#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_M  ((DPORT_PRO_ICACHE_BLOCKSIZE_MODE_V)<<(DPORT_PRO_ICACHE_BLOCKSIZE_MODE_S))
+#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_V  0x3
+#define DPORT_PRO_ICACHE_BLOCKSIZE_MODE_S  3
+/* DPORT_PRO_ICACHE_SETSIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_SETSIZE_MODE  (BIT(2))
+#define DPORT_PRO_ICACHE_SETSIZE_MODE_M  (BIT(2))
+#define DPORT_PRO_ICACHE_SETSIZE_MODE_V  0x1
+#define DPORT_PRO_ICACHE_SETSIZE_MODE_S  2
+/* DPORT_PRO_ICACHE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_MODE  (BIT(1))
+#define DPORT_PRO_ICACHE_MODE_M  (BIT(1))
+#define DPORT_PRO_ICACHE_MODE_V  0x1
+#define DPORT_PRO_ICACHE_MODE_S  1
+/* DPORT_PRO_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_ENABLE  (BIT(0))
+#define DPORT_PRO_ICACHE_ENABLE_M  (BIT(0))
+#define DPORT_PRO_ICACHE_ENABLE_V  0x1
+#define DPORT_PRO_ICACHE_ENABLE_S  0
+
+#define DPORT_PRO_ICACHE_CTRL1_REG          (DR_REG_EXTMEM_BASE + 0x044)
+/* DPORT_PRO_ICACHE_MASK_BUS3 : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_MASK_BUS3  (BIT(3))
+#define DPORT_PRO_ICACHE_MASK_BUS3_M  (BIT(3))
+#define DPORT_PRO_ICACHE_MASK_BUS3_V  0x1
+#define DPORT_PRO_ICACHE_MASK_BUS3_S  3
+/* DPORT_PRO_ICACHE_MASK_BUS2 : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_MASK_BUS2  (BIT(2))
+#define DPORT_PRO_ICACHE_MASK_BUS2_M  (BIT(2))
+#define DPORT_PRO_ICACHE_MASK_BUS2_V  0x1
+#define DPORT_PRO_ICACHE_MASK_BUS2_S  2
+/* DPORT_PRO_ICACHE_MASK_BUS1 : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_MASK_BUS1  (BIT(1))
+#define DPORT_PRO_ICACHE_MASK_BUS1_M  (BIT(1))
+#define DPORT_PRO_ICACHE_MASK_BUS1_V  0x1
+#define DPORT_PRO_ICACHE_MASK_BUS1_S  1
+/* DPORT_PRO_ICACHE_MASK_BUS0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_MASK_BUS0  (BIT(0))
+#define DPORT_PRO_ICACHE_MASK_BUS0_M  (BIT(0))
+#define DPORT_PRO_ICACHE_MASK_BUS0_V  0x1
+#define DPORT_PRO_ICACHE_MASK_BUS0_S  0
+#define DPORT_PRO_ICACHE_MASK_IRAM0 DPORT_PRO_ICACHE_MASK_BUS0
+#define DPORT_PRO_ICACHE_MASK_IRAM1 DPORT_PRO_ICACHE_MASK_BUS1
+#define DPORT_PRO_ICACHE_MASK_IROM0 DPORT_PRO_ICACHE_MASK_BUS2
+#define DPORT_PRO_ICACHE_MASK_DROM0 DPORT_PRO_ICACHE_MASK_BUS3
+
+#define DPORT_PRO_ICACHE_TAG_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x048)
+/* DPORT_PRO_ICACHE_TAG_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_TAG_MEM_PD  (BIT(1))
+#define DPORT_PRO_ICACHE_TAG_MEM_PD_M  (BIT(1))
+#define DPORT_PRO_ICACHE_TAG_MEM_PD_V  0x1
+#define DPORT_PRO_ICACHE_TAG_MEM_PD_S  1
+/* DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON  (BIT(0))
+#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_M  (BIT(0))
+#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_V  0x1
+#define DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON_S  0
+
+#define DPORT_PRO_ICACHE_LOCK0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x04C)
+/* DPORT_PRO_ICACHE_LOCK0_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_LOCK0_ADDR  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_LOCK0_ADDR_M  ((DPORT_PRO_ICACHE_LOCK0_ADDR_V)<<(DPORT_PRO_ICACHE_LOCK0_ADDR_S))
+#define DPORT_PRO_ICACHE_LOCK0_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_LOCK0_ADDR_S  0
+
+#define DPORT_PRO_ICACHE_LOCK0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x050)
+/* DPORT_PRO_ICACHE_LOCK0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_LOCK0_SIZE  0x0000FFFF
+#define DPORT_PRO_ICACHE_LOCK0_SIZE_M  ((DPORT_PRO_ICACHE_LOCK0_SIZE_V)<<(DPORT_PRO_ICACHE_LOCK0_SIZE_S))
+#define DPORT_PRO_ICACHE_LOCK0_SIZE_V  0xFFFF
+#define DPORT_PRO_ICACHE_LOCK0_SIZE_S  0
+
+#define DPORT_PRO_ICACHE_LOCK1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x054)
+/* DPORT_PRO_ICACHE_LOCK1_ADDR : R/W ;bitpos:[31:0] ;default: 10'h0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_LOCK1_ADDR  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_LOCK1_ADDR_M  ((DPORT_PRO_ICACHE_LOCK1_ADDR_V)<<(DPORT_PRO_ICACHE_LOCK1_ADDR_S))
+#define DPORT_PRO_ICACHE_LOCK1_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_LOCK1_ADDR_S  0
+
+#define DPORT_PRO_ICACHE_LOCK1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x058)
+/* DPORT_PRO_ICACHE_LOCK1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_LOCK1_SIZE  0x0000FFFF
+#define DPORT_PRO_ICACHE_LOCK1_SIZE_M  ((DPORT_PRO_ICACHE_LOCK1_SIZE_V)<<(DPORT_PRO_ICACHE_LOCK1_SIZE_S))
+#define DPORT_PRO_ICACHE_LOCK1_SIZE_V  0xFFFF
+#define DPORT_PRO_ICACHE_LOCK1_SIZE_S  0
+
+#define DPORT_PRO_ICACHE_MEM_SYNC0_REG          (DR_REG_EXTMEM_BASE + 0x05C)
+/* DPORT_PRO_ICACHE_MEMSYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_MEMSYNC_ADDR  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_M  ((DPORT_PRO_ICACHE_MEMSYNC_ADDR_V)<<(DPORT_PRO_ICACHE_MEMSYNC_ADDR_S))
+#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_MEMSYNC_ADDR_S  0
+
+#define DPORT_PRO_ICACHE_MEM_SYNC1_REG          (DR_REG_EXTMEM_BASE + 0x060)
+/* DPORT_PRO_ICACHE_MEMSYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h400000 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_MEMSYNC_SIZE  0x007FFFFF
+#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_M  ((DPORT_PRO_ICACHE_MEMSYNC_SIZE_V)<<(DPORT_PRO_ICACHE_MEMSYNC_SIZE_S))
+#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_V  0x7FFFFF
+#define DPORT_PRO_ICACHE_MEMSYNC_SIZE_S  0
+
+#define DPORT_PRO_ICACHE_PRELOAD_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x064)
+/* DPORT_PRO_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_ADDR  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_PRELOAD_ADDR_M  ((DPORT_PRO_ICACHE_PRELOAD_ADDR_V)<<(DPORT_PRO_ICACHE_PRELOAD_ADDR_S))
+#define DPORT_PRO_ICACHE_PRELOAD_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_PRELOAD_ADDR_S  0
+
+#define DPORT_PRO_ICACHE_PRELOAD_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x068)
+/* DPORT_PRO_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_ORDER  (BIT(16))
+#define DPORT_PRO_ICACHE_PRELOAD_ORDER_M  (BIT(16))
+#define DPORT_PRO_ICACHE_PRELOAD_ORDER_V  0x1
+#define DPORT_PRO_ICACHE_PRELOAD_ORDER_S  16
+/* DPORT_PRO_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h8000 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_SIZE  0x0000FFFF
+#define DPORT_PRO_ICACHE_PRELOAD_SIZE_M  ((DPORT_PRO_ICACHE_PRELOAD_SIZE_V)<<(DPORT_PRO_ICACHE_PRELOAD_SIZE_S))
+#define DPORT_PRO_ICACHE_PRELOAD_SIZE_V  0xFFFF
+#define DPORT_PRO_ICACHE_PRELOAD_SIZE_S  0
+
+#define DPORT_PRO_ICACHE_AUTOLOAD_CFG_REG          (DR_REG_EXTMEM_BASE + 0x06C)
+/* DPORT_PRO_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[21:6] ;default: 16'h1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE  0x0000FFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SIZE_S))
+#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_V  0xFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SIZE_S  6
+/* DPORT_PRO_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[5:4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_RQST  0x00000003
+#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_M  ((DPORT_PRO_ICACHE_AUTOLOAD_RQST_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_RQST_S))
+#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_V  0x3
+#define DPORT_PRO_ICACHE_AUTOLOAD_RQST_S  4
+/* DPORT_PRO_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER  (BIT(3))
+#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_M  (BIT(3))
+#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_V  0x1
+#define DPORT_PRO_ICACHE_AUTOLOAD_ORDER_S  3
+/* DPORT_PRO_ICACHE_AUTOLOAD_STEP : R/W ;bitpos:[2:1] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_STEP  0x00000003
+#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_M  ((DPORT_PRO_ICACHE_AUTOLOAD_STEP_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_STEP_S))
+#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_V  0x3
+#define DPORT_PRO_ICACHE_AUTOLOAD_STEP_S  1
+/* DPORT_PRO_ICACHE_AUTOLOAD_MODE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_MODE  (BIT(0))
+#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_M  (BIT(0))
+#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_V  0x1
+#define DPORT_PRO_ICACHE_AUTOLOAD_MODE_S  0
+
+#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION0_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x070)
+/* DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S))
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_ADDR_S  0
+
+#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION0_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x074)
+/* DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE  0x00FFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S))
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_V  0xFFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT0_SIZE_S  0
+
+#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION1_ADDR_REG          (DR_REG_EXTMEM_BASE + 0x078)
+/* DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S))
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_V  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_ADDR_S  0
+
+#define DPORT_PRO_ICACHE_AUTOLOAD_SECTION1_SIZE_REG          (DR_REG_EXTMEM_BASE + 0x07C)
+/* DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[23:0] ;default: 24'h8000 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE  0x00FFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_M  ((DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S))
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_V  0xFFFFFF
+#define DPORT_PRO_ICACHE_AUTOLOAD_SCT1_SIZE_S  0
+
+#define DPORT_IC_PRELOAD_CNT_REG          (DR_REG_EXTMEM_BASE + 0x080)
+/* DPORT_IC_PRELOAD_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_CNT  0xFFFFFFFF
+#define DPORT_IC_PRELOAD_CNT_M  ((DPORT_IC_PRELOAD_CNT_V)<<(DPORT_IC_PRELOAD_CNT_S))
+#define DPORT_IC_PRELOAD_CNT_V  0xFFFFFFFF
+#define DPORT_IC_PRELOAD_CNT_S  0
+
+#define DPORT_IC_PRELOAD_EVICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x084)
+/* DPORT_IC_PRELOAD_EVICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_EVICT_CNT  0xFFFFFFFF
+#define DPORT_IC_PRELOAD_EVICT_CNT_M  ((DPORT_IC_PRELOAD_EVICT_CNT_V)<<(DPORT_IC_PRELOAD_EVICT_CNT_S))
+#define DPORT_IC_PRELOAD_EVICT_CNT_V  0xFFFFFFFF
+#define DPORT_IC_PRELOAD_EVICT_CNT_S  0
+
+#define DPORT_IC_PRELOAD_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x088)
+/* DPORT_IC_PRELOAD_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_MISS_CNT  0xFFFFFFFF
+#define DPORT_IC_PRELOAD_MISS_CNT_M  ((DPORT_IC_PRELOAD_MISS_CNT_V)<<(DPORT_IC_PRELOAD_MISS_CNT_S))
+#define DPORT_IC_PRELOAD_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_IC_PRELOAD_MISS_CNT_S  0
+
+#define DPORT_IBUS3_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x08C)
+/* DPORT_IBUS3_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS3_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_IBUS3_ABANDON_CNT_M  ((DPORT_IBUS3_ABANDON_CNT_V)<<(DPORT_IBUS3_ABANDON_CNT_S))
+#define DPORT_IBUS3_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS3_ABANDON_CNT_S  0
+
+#define DPORT_IBUS2_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x090)
+/* DPORT_IBUS2_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS2_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_IBUS2_ABANDON_CNT_M  ((DPORT_IBUS2_ABANDON_CNT_V)<<(DPORT_IBUS2_ABANDON_CNT_S))
+#define DPORT_IBUS2_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS2_ABANDON_CNT_S  0
+
+#define DPORT_IBUS1_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x094)
+/* DPORT_IBUS1_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS1_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_IBUS1_ABANDON_CNT_M  ((DPORT_IBUS1_ABANDON_CNT_V)<<(DPORT_IBUS1_ABANDON_CNT_S))
+#define DPORT_IBUS1_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS1_ABANDON_CNT_S  0
+
+#define DPORT_IBUS0_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x098)
+/* DPORT_IBUS0_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS0_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_IBUS0_ABANDON_CNT_M  ((DPORT_IBUS0_ABANDON_CNT_V)<<(DPORT_IBUS0_ABANDON_CNT_S))
+#define DPORT_IBUS0_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS0_ABANDON_CNT_S  0
+
+#define DPORT_IBUS3_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x09C)
+/* DPORT_IBUS3_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS3_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_IBUS3_ACS_MISS_CNT_M  ((DPORT_IBUS3_ACS_MISS_CNT_V)<<(DPORT_IBUS3_ACS_MISS_CNT_S))
+#define DPORT_IBUS3_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS3_ACS_MISS_CNT_S  0
+
+#define DPORT_IBUS2_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A0)
+/* DPORT_IBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS2_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_IBUS2_ACS_MISS_CNT_M  ((DPORT_IBUS2_ACS_MISS_CNT_V)<<(DPORT_IBUS2_ACS_MISS_CNT_S))
+#define DPORT_IBUS2_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS2_ACS_MISS_CNT_S  0
+
+#define DPORT_IBUS1_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A4)
+/* DPORT_IBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS1_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_IBUS1_ACS_MISS_CNT_M  ((DPORT_IBUS1_ACS_MISS_CNT_V)<<(DPORT_IBUS1_ACS_MISS_CNT_S))
+#define DPORT_IBUS1_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS1_ACS_MISS_CNT_S  0
+
+#define DPORT_IBUS0_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0A8)
+/* DPORT_IBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS0_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_IBUS0_ACS_MISS_CNT_M  ((DPORT_IBUS0_ACS_MISS_CNT_V)<<(DPORT_IBUS0_ACS_MISS_CNT_S))
+#define DPORT_IBUS0_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS0_ACS_MISS_CNT_S  0
+
+#define DPORT_IBUS3_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0AC)
+/* DPORT_IBUS3_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS3_ACS_CNT  0xFFFFFFFF
+#define DPORT_IBUS3_ACS_CNT_M  ((DPORT_IBUS3_ACS_CNT_V)<<(DPORT_IBUS3_ACS_CNT_S))
+#define DPORT_IBUS3_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS3_ACS_CNT_S  0
+
+#define DPORT_IBUS2_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B0)
+/* DPORT_IBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS2_ACS_CNT  0xFFFFFFFF
+#define DPORT_IBUS2_ACS_CNT_M  ((DPORT_IBUS2_ACS_CNT_V)<<(DPORT_IBUS2_ACS_CNT_S))
+#define DPORT_IBUS2_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS2_ACS_CNT_S  0
+
+#define DPORT_IBUS1_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B4)
+/* DPORT_IBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS1_ACS_CNT  0xFFFFFFFF
+#define DPORT_IBUS1_ACS_CNT_M  ((DPORT_IBUS1_ACS_CNT_V)<<(DPORT_IBUS1_ACS_CNT_S))
+#define DPORT_IBUS1_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS1_ACS_CNT_S  0
+
+#define DPORT_IBUS0_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0B8)
+/* DPORT_IBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_IBUS0_ACS_CNT  0xFFFFFFFF
+#define DPORT_IBUS0_ACS_CNT_M  ((DPORT_IBUS0_ACS_CNT_V)<<(DPORT_IBUS0_ACS_CNT_S))
+#define DPORT_IBUS0_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_IBUS0_ACS_CNT_S  0
+
+#define DPORT_DC_PRELOAD_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0BC)
+/* DPORT_DC_PRELOAD_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_CNT  0xFFFFFFFF
+#define DPORT_DC_PRELOAD_CNT_M  ((DPORT_DC_PRELOAD_CNT_V)<<(DPORT_DC_PRELOAD_CNT_S))
+#define DPORT_DC_PRELOAD_CNT_V  0xFFFFFFFF
+#define DPORT_DC_PRELOAD_CNT_S  0
+
+#define DPORT_DC_PRELOAD_EVICT_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C0)
+/* DPORT_DC_PRELOAD_EVICT_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_EVICT_CNT  0xFFFFFFFF
+#define DPORT_DC_PRELOAD_EVICT_CNT_M  ((DPORT_DC_PRELOAD_EVICT_CNT_V)<<(DPORT_DC_PRELOAD_EVICT_CNT_S))
+#define DPORT_DC_PRELOAD_EVICT_CNT_V  0xFFFFFFFF
+#define DPORT_DC_PRELOAD_EVICT_CNT_S  0
+
+#define DPORT_DC_PRELOAD_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C4)
+/* DPORT_DC_PRELOAD_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_MISS_CNT  0xFFFFFFFF
+#define DPORT_DC_PRELOAD_MISS_CNT_M  ((DPORT_DC_PRELOAD_MISS_CNT_V)<<(DPORT_DC_PRELOAD_MISS_CNT_S))
+#define DPORT_DC_PRELOAD_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_DC_PRELOAD_MISS_CNT_S  0
+
+#define DPORT_DBUS3_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0C8)
+/* DPORT_DBUS3_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS3_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_DBUS3_ABANDON_CNT_M  ((DPORT_DBUS3_ABANDON_CNT_V)<<(DPORT_DBUS3_ABANDON_CNT_S))
+#define DPORT_DBUS3_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS3_ABANDON_CNT_S  0
+
+#define DPORT_DBUS2_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0CC)
+/* DPORT_DBUS2_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS2_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_DBUS2_ABANDON_CNT_M  ((DPORT_DBUS2_ABANDON_CNT_V)<<(DPORT_DBUS2_ABANDON_CNT_S))
+#define DPORT_DBUS2_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS2_ABANDON_CNT_S  0
+
+#define DPORT_DBUS1_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D0)
+/* DPORT_DBUS1_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS1_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_DBUS1_ABANDON_CNT_M  ((DPORT_DBUS1_ABANDON_CNT_V)<<(DPORT_DBUS1_ABANDON_CNT_S))
+#define DPORT_DBUS1_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS1_ABANDON_CNT_S  0
+
+#define DPORT_DBUS0_ABANDON_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D4)
+/* DPORT_DBUS0_ABANDON_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS0_ABANDON_CNT  0xFFFFFFFF
+#define DPORT_DBUS0_ABANDON_CNT_M  ((DPORT_DBUS0_ABANDON_CNT_V)<<(DPORT_DBUS0_ABANDON_CNT_S))
+#define DPORT_DBUS0_ABANDON_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS0_ABANDON_CNT_S  0
+
+#define DPORT_DBUS3_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0D8)
+/* DPORT_DBUS3_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS3_ACS_WB_CNT  0xFFFFFFFF
+#define DPORT_DBUS3_ACS_WB_CNT_M  ((DPORT_DBUS3_ACS_WB_CNT_V)<<(DPORT_DBUS3_ACS_WB_CNT_S))
+#define DPORT_DBUS3_ACS_WB_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS3_ACS_WB_CNT_S  0
+
+#define DPORT_DBUS2_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0DC)
+/* DPORT_DBUS2_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS2_ACS_WB_CNT  0xFFFFFFFF
+#define DPORT_DBUS2_ACS_WB_CNT_M  ((DPORT_DBUS2_ACS_WB_CNT_V)<<(DPORT_DBUS2_ACS_WB_CNT_S))
+#define DPORT_DBUS2_ACS_WB_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS2_ACS_WB_CNT_S  0
+
+#define DPORT_DBUS1_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E0)
+/* DPORT_DBUS1_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS1_ACS_WB_CNT  0xFFFFFFFF
+#define DPORT_DBUS1_ACS_WB_CNT_M  ((DPORT_DBUS1_ACS_WB_CNT_V)<<(DPORT_DBUS1_ACS_WB_CNT_S))
+#define DPORT_DBUS1_ACS_WB_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS1_ACS_WB_CNT_S  0
+
+#define DPORT_DBUS0_ACS_WB_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E4)
+/* DPORT_DBUS0_ACS_WB_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS0_ACS_WB_CNT  0xFFFFFFFF
+#define DPORT_DBUS0_ACS_WB_CNT_M  ((DPORT_DBUS0_ACS_WB_CNT_V)<<(DPORT_DBUS0_ACS_WB_CNT_S))
+#define DPORT_DBUS0_ACS_WB_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS0_ACS_WB_CNT_S  0
+
+#define DPORT_DBUS3_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0E8)
+/* DPORT_DBUS3_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS3_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_DBUS3_ACS_MISS_CNT_M  ((DPORT_DBUS3_ACS_MISS_CNT_V)<<(DPORT_DBUS3_ACS_MISS_CNT_S))
+#define DPORT_DBUS3_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS3_ACS_MISS_CNT_S  0
+
+#define DPORT_DBUS2_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0EC)
+/* DPORT_DBUS2_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS2_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_DBUS2_ACS_MISS_CNT_M  ((DPORT_DBUS2_ACS_MISS_CNT_V)<<(DPORT_DBUS2_ACS_MISS_CNT_S))
+#define DPORT_DBUS2_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS2_ACS_MISS_CNT_S  0
+
+#define DPORT_DBUS1_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0F0)
+/* DPORT_DBUS1_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS1_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_DBUS1_ACS_MISS_CNT_M  ((DPORT_DBUS1_ACS_MISS_CNT_V)<<(DPORT_DBUS1_ACS_MISS_CNT_S))
+#define DPORT_DBUS1_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS1_ACS_MISS_CNT_S  0
+
+#define DPORT_DBUS0_ACS_MISS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0F4)
+/* DPORT_DBUS0_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS0_ACS_MISS_CNT  0xFFFFFFFF
+#define DPORT_DBUS0_ACS_MISS_CNT_M  ((DPORT_DBUS0_ACS_MISS_CNT_V)<<(DPORT_DBUS0_ACS_MISS_CNT_S))
+#define DPORT_DBUS0_ACS_MISS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS0_ACS_MISS_CNT_S  0
+
+#define DPORT_DBUS3_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0F8)
+/* DPORT_DBUS3_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS3_ACS_CNT  0xFFFFFFFF
+#define DPORT_DBUS3_ACS_CNT_M  ((DPORT_DBUS3_ACS_CNT_V)<<(DPORT_DBUS3_ACS_CNT_S))
+#define DPORT_DBUS3_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS3_ACS_CNT_S  0
+
+#define DPORT_DBUS2_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x0FC)
+/* DPORT_DBUS2_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS2_ACS_CNT  0xFFFFFFFF
+#define DPORT_DBUS2_ACS_CNT_M  ((DPORT_DBUS2_ACS_CNT_V)<<(DPORT_DBUS2_ACS_CNT_S))
+#define DPORT_DBUS2_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS2_ACS_CNT_S  0
+
+#define DPORT_DBUS1_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x100)
+/* DPORT_DBUS1_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS1_ACS_CNT  0xFFFFFFFF
+#define DPORT_DBUS1_ACS_CNT_M  ((DPORT_DBUS1_ACS_CNT_V)<<(DPORT_DBUS1_ACS_CNT_S))
+#define DPORT_DBUS1_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS1_ACS_CNT_S  0
+
+#define DPORT_DBUS0_ACS_CNT_REG          (DR_REG_EXTMEM_BASE + 0x104)
+/* DPORT_DBUS0_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_DBUS0_ACS_CNT  0xFFFFFFFF
+#define DPORT_DBUS0_ACS_CNT_M  ((DPORT_DBUS0_ACS_CNT_V)<<(DPORT_DBUS0_ACS_CNT_S))
+#define DPORT_DBUS0_ACS_CNT_V  0xFFFFFFFF
+#define DPORT_DBUS0_ACS_CNT_S  0
+
+#define DPORT_PRO_CACHE_IA_INT_EN_REG DPORT_CACHE_DBG_INT_ENA_REG
+#define DPORT_PRO_CACHE_INT_CLR DPORT_CACHE_DBG_INT_CLR
+#define DPORT_PRO_CACHE_DBG_EN DPORT_CACHE_DBG_EN
+#define DPORT_CACHE_DBG_INT_ENA_REG          (DR_REG_EXTMEM_BASE + 0x108)
+/* DPORT_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_MMU_ENTRY_FAULT_INT_ENA  (BIT(13))
+#define DPORT_MMU_ENTRY_FAULT_INT_ENA_M  (BIT(13))
+#define DPORT_MMU_ENTRY_FAULT_INT_ENA_V  0x1
+#define DPORT_MMU_ENTRY_FAULT_INT_ENA_S  13
+/* DPORT_DCACHE_REJECT_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DCACHE_REJECT_INT_ENA  (BIT(12))
+#define DPORT_DCACHE_REJECT_INT_ENA_M  (BIT(12))
+#define DPORT_DCACHE_REJECT_INT_ENA_V  0x1
+#define DPORT_DCACHE_REJECT_INT_ENA_S  12
+/* DPORT_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DCACHE_WRITE_FLASH_INT_ENA  (BIT(11))
+#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_M  (BIT(11))
+#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_V  0x1
+#define DPORT_DCACHE_WRITE_FLASH_INT_ENA_S  11
+/* DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA  (BIT(10))
+#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_M  (BIT(10))
+#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_V  0x1
+#define DPORT_DC_PRELOAD_SIZE_FAULT_INT_ENA_S  10
+/* DPORT_DC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA  (BIT(9))
+#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_M  (BIT(9))
+#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_V  0x1
+#define DPORT_DC_SYNC_SIZE_FAULT_INT_ENA_S  9
+/* DPORT_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS_CNT_OVF_INT_ENA  (BIT(8))
+#define DPORT_DBUS_CNT_OVF_INT_ENA_M  (BIT(8))
+#define DPORT_DBUS_CNT_OVF_INT_ENA_V  0x1
+#define DPORT_DBUS_CNT_OVF_INT_ENA_S  8
+/* DPORT_DBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS_ACS_MSK_IC_INT_ENA  (BIT(7))
+#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_M  (BIT(7))
+#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define DPORT_DBUS_ACS_MSK_IC_INT_ENA_S  7
+/* DPORT_ICACHE_REJECT_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ICACHE_REJECT_INT_ENA  (BIT(6))
+#define DPORT_ICACHE_REJECT_INT_ENA_M  (BIT(6))
+#define DPORT_ICACHE_REJECT_INT_ENA_V  0x1
+#define DPORT_ICACHE_REJECT_INT_ENA_S  6
+/* DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA  (BIT(5))
+#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_M  (BIT(5))
+#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_V  0x1
+#define DPORT_IC_PRELOAD_SIZE_FAULT_INT_ENA_S  5
+/* DPORT_IC_SYNC_SIZE_FAULT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA  (BIT(4))
+#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_M  (BIT(4))
+#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_V  0x1
+#define DPORT_IC_SYNC_SIZE_FAULT_INT_ENA_S  4
+/* DPORT_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS_CNT_OVF_INT_ENA  (BIT(3))
+#define DPORT_IBUS_CNT_OVF_INT_ENA_M  (BIT(3))
+#define DPORT_IBUS_CNT_OVF_INT_ENA_V  0x1
+#define DPORT_IBUS_CNT_OVF_INT_ENA_S  3
+/* DPORT_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS_ACS_MSK_IC_INT_ENA  (BIT(2))
+#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_M  (BIT(2))
+#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_V  0x1
+#define DPORT_IBUS_ACS_MSK_IC_INT_ENA_S  2
+/* DPORT_CACHE_DBG_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CACHE_DBG_INT_CLR  (BIT(1))
+#define DPORT_CACHE_DBG_INT_CLR_M  (BIT(1))
+#define DPORT_CACHE_DBG_INT_CLR_V  0x1
+#define DPORT_CACHE_DBG_INT_CLR_S  1
+/* DPORT_CACHE_DBG_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_CACHE_DBG_EN  (BIT(0))
+#define DPORT_CACHE_DBG_EN_M  (BIT(0))
+#define DPORT_CACHE_DBG_EN_V  0x1
+#define DPORT_CACHE_DBG_EN_S  0
+
+#define DPORT_CACHE_DBG_STATUS0_REG          (DR_REG_EXTMEM_BASE + 0x10C)
+/* DPORT_ICACHE_REJECT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ICACHE_REJECT_ST  (BIT(21))
+#define DPORT_ICACHE_REJECT_ST_M  (BIT(21))
+#define DPORT_ICACHE_REJECT_ST_V  0x1
+#define DPORT_ICACHE_REJECT_ST_S  21
+/* DPORT_IC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_SIZE_FAULT_ST  (BIT(20))
+#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_M  (BIT(20))
+#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_V  0x1
+#define DPORT_IC_PRELOAD_SIZE_FAULT_ST_S  20
+/* DPORT_IC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IC_SYNC_SIZE_FAULT_ST  (BIT(19))
+#define DPORT_IC_SYNC_SIZE_FAULT_ST_M  (BIT(19))
+#define DPORT_IC_SYNC_SIZE_FAULT_ST_V  0x1
+#define DPORT_IC_SYNC_SIZE_FAULT_ST_S  19
+/* DPORT_IC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_CNT_OVF_ST  (BIT(18))
+#define DPORT_IC_PRELOAD_CNT_OVF_ST_M  (BIT(18))
+#define DPORT_IC_PRELOAD_CNT_OVF_ST_V  0x1
+#define DPORT_IC_PRELOAD_CNT_OVF_ST_S  18
+/* DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST  (BIT(17))
+#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_M  (BIT(17))
+#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_V  0x1
+#define DPORT_IC_PRELOAD_EVICT_CNT_OVF_ST_S  17
+/* DPORT_IC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST  (BIT(16))
+#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_M  (BIT(16))
+#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_IC_PRELOAD_MISS_CNT_OVF_ST_S  16
+/* DPORT_IBUS3_ABANDON_CNT_OVF_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS3_ABANDON_CNT_OVF_ST  (BIT(15))
+#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_M  (BIT(15))
+#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS3_ABANDON_CNT_OVF_ST_S  15
+/* DPORT_IBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS2_ABANDON_CNT_OVF_ST  (BIT(14))
+#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_M  (BIT(14))
+#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS2_ABANDON_CNT_OVF_ST_S  14
+/* DPORT_IBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS1_ABANDON_CNT_OVF_ST  (BIT(13))
+#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_M  (BIT(13))
+#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS1_ABANDON_CNT_OVF_ST_S  13
+/* DPORT_IBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS0_ABANDON_CNT_OVF_ST  (BIT(12))
+#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_M  (BIT(12))
+#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS0_ABANDON_CNT_OVF_ST_S  12
+/* DPORT_IBUS3_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST  (BIT(11))
+#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_M  (BIT(11))
+#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS3_ACS_MISS_CNT_OVF_ST_S  11
+/* DPORT_IBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST  (BIT(10))
+#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_M  (BIT(10))
+#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS2_ACS_MISS_CNT_OVF_ST_S  10
+/* DPORT_IBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST  (BIT(9))
+#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_M  (BIT(9))
+#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS1_ACS_MISS_CNT_OVF_ST_S  9
+/* DPORT_IBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST  (BIT(8))
+#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
+#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS0_ACS_MISS_CNT_OVF_ST_S  8
+/* DPORT_IBUS3_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS3_ACS_CNT_OVF_ST  (BIT(7))
+#define DPORT_IBUS3_ACS_CNT_OVF_ST_M  (BIT(7))
+#define DPORT_IBUS3_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS3_ACS_CNT_OVF_ST_S  7
+/* DPORT_IBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS2_ACS_CNT_OVF_ST  (BIT(6))
+#define DPORT_IBUS2_ACS_CNT_OVF_ST_M  (BIT(6))
+#define DPORT_IBUS2_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS2_ACS_CNT_OVF_ST_S  6
+/* DPORT_IBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS1_ACS_CNT_OVF_ST  (BIT(5))
+#define DPORT_IBUS1_ACS_CNT_OVF_ST_M  (BIT(5))
+#define DPORT_IBUS1_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS1_ACS_CNT_OVF_ST_S  5
+/* DPORT_IBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS0_ACS_CNT_OVF_ST  (BIT(4))
+#define DPORT_IBUS0_ACS_CNT_OVF_ST_M  (BIT(4))
+#define DPORT_IBUS0_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_IBUS0_ACS_CNT_OVF_ST_S  4
+/* DPORT_IBUS3_ACS_MSK_ICACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS3_ACS_MSK_ICACHE_ST  (BIT(3))
+#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_M  (BIT(3))
+#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_V  0x1
+#define DPORT_IBUS3_ACS_MSK_ICACHE_ST_S  3
+/* DPORT_IBUS2_ACS_MSK_ICACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS2_ACS_MSK_ICACHE_ST  (BIT(2))
+#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_M  (BIT(2))
+#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_V  0x1
+#define DPORT_IBUS2_ACS_MSK_ICACHE_ST_S  2
+/* DPORT_IBUS1_ACS_MSK_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS1_ACS_MSK_ICACHE_ST  (BIT(1))
+#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_M  (BIT(1))
+#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_V  0x1
+#define DPORT_IBUS1_ACS_MSK_ICACHE_ST_S  1
+/* DPORT_IBUS0_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_IBUS0_ACS_MSK_ICACHE_ST  (BIT(0))
+#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_M  (BIT(0))
+#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_V  0x1
+#define DPORT_IBUS0_ACS_MSK_ICACHE_ST_S  0
+
+#define DPORT_CACHE_DBG_STATUS1_REG          (DR_REG_EXTMEM_BASE + 0x110)
+/* DPORT_MMU_ENTRY_FAULT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_MMU_ENTRY_FAULT_ST  (BIT(27))
+#define DPORT_MMU_ENTRY_FAULT_ST_M  (BIT(27))
+#define DPORT_MMU_ENTRY_FAULT_ST_V  0x1
+#define DPORT_MMU_ENTRY_FAULT_ST_S  27
+/* DPORT_DCACHE_REJECT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DCACHE_REJECT_ST  (BIT(26))
+#define DPORT_DCACHE_REJECT_ST_M  (BIT(26))
+#define DPORT_DCACHE_REJECT_ST_V  0x1
+#define DPORT_DCACHE_REJECT_ST_S  26
+/* DPORT_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DCACHE_WRITE_FLASH_ST  (BIT(25))
+#define DPORT_DCACHE_WRITE_FLASH_ST_M  (BIT(25))
+#define DPORT_DCACHE_WRITE_FLASH_ST_V  0x1
+#define DPORT_DCACHE_WRITE_FLASH_ST_S  25
+/* DPORT_DC_PRELOAD_SIZE_FAULT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_SIZE_FAULT_ST  (BIT(24))
+#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_M  (BIT(24))
+#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_V  0x1
+#define DPORT_DC_PRELOAD_SIZE_FAULT_ST_S  24
+/* DPORT_DC_SYNC_SIZE_FAULT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DC_SYNC_SIZE_FAULT_ST  (BIT(23))
+#define DPORT_DC_SYNC_SIZE_FAULT_ST_M  (BIT(23))
+#define DPORT_DC_SYNC_SIZE_FAULT_ST_V  0x1
+#define DPORT_DC_SYNC_SIZE_FAULT_ST_S  23
+/* DPORT_DC_PRELOAD_CNT_OVF_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_CNT_OVF_ST  (BIT(22))
+#define DPORT_DC_PRELOAD_CNT_OVF_ST_M  (BIT(22))
+#define DPORT_DC_PRELOAD_CNT_OVF_ST_V  0x1
+#define DPORT_DC_PRELOAD_CNT_OVF_ST_S  22
+/* DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST  (BIT(21))
+#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_M  (BIT(21))
+#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_V  0x1
+#define DPORT_DC_PRELOAD_EVICT_CNT_OVF_ST_S  21
+/* DPORT_DC_PRELOAD_MISS_CNT_OVF_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST  (BIT(20))
+#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_M  (BIT(20))
+#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_DC_PRELOAD_MISS_CNT_OVF_ST_S  20
+/* DPORT_DBUS3_ABANDON_CNT_OVF_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS3_ABANDON_CNT_OVF_ST  (BIT(19))
+#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_M  (BIT(19))
+#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS3_ABANDON_CNT_OVF_ST_S  19
+/* DPORT_DBUS2_ABANDON_CNT_OVF_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS2_ABANDON_CNT_OVF_ST  (BIT(18))
+#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_M  (BIT(18))
+#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS2_ABANDON_CNT_OVF_ST_S  18
+/* DPORT_DBUS1_ABANDON_CNT_OVF_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS1_ABANDON_CNT_OVF_ST  (BIT(17))
+#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_M  (BIT(17))
+#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS1_ABANDON_CNT_OVF_ST_S  17
+/* DPORT_DBUS0_ABANDON_CNT_OVF_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS0_ABANDON_CNT_OVF_ST  (BIT(16))
+#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_M  (BIT(16))
+#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS0_ABANDON_CNT_OVF_ST_S  16
+/* DPORT_DBUS3_ACS_WB_CNT_OVF_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST  (BIT(15))
+#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_M  (BIT(15))
+#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS3_ACS_WB_CNT_OVF_ST_S  15
+/* DPORT_DBUS2_ACS_WB_CNT_OVF_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST  (BIT(14))
+#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_M  (BIT(14))
+#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS2_ACS_WB_CNT_OVF_ST_S  14
+/* DPORT_DBUS1_ACS_WB_CNT_OVF_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST  (BIT(13))
+#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_M  (BIT(13))
+#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS1_ACS_WB_CNT_OVF_ST_S  13
+/* DPORT_DBUS0_ACS_WB_CNT_OVF_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST  (BIT(12))
+#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_M  (BIT(12))
+#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS0_ACS_WB_CNT_OVF_ST_S  12
+/* DPORT_DBUS3_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST  (BIT(11))
+#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_M  (BIT(11))
+#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS3_ACS_MISS_CNT_OVF_ST_S  11
+/* DPORT_DBUS2_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST  (BIT(10))
+#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_M  (BIT(10))
+#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS2_ACS_MISS_CNT_OVF_ST_S  10
+/* DPORT_DBUS1_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST  (BIT(9))
+#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_M  (BIT(9))
+#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS1_ACS_MISS_CNT_OVF_ST_S  9
+/* DPORT_DBUS0_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST  (BIT(8))
+#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_M  (BIT(8))
+#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS0_ACS_MISS_CNT_OVF_ST_S  8
+/* DPORT_DBUS3_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS3_ACS_CNT_OVF_ST  (BIT(7))
+#define DPORT_DBUS3_ACS_CNT_OVF_ST_M  (BIT(7))
+#define DPORT_DBUS3_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS3_ACS_CNT_OVF_ST_S  7
+/* DPORT_DBUS2_ACS_CNT_OVF_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS2_ACS_CNT_OVF_ST  (BIT(6))
+#define DPORT_DBUS2_ACS_CNT_OVF_ST_M  (BIT(6))
+#define DPORT_DBUS2_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS2_ACS_CNT_OVF_ST_S  6
+/* DPORT_DBUS1_ACS_CNT_OVF_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS1_ACS_CNT_OVF_ST  (BIT(5))
+#define DPORT_DBUS1_ACS_CNT_OVF_ST_M  (BIT(5))
+#define DPORT_DBUS1_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS1_ACS_CNT_OVF_ST_S  5
+/* DPORT_DBUS0_ACS_CNT_OVF_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS0_ACS_CNT_OVF_ST  (BIT(4))
+#define DPORT_DBUS0_ACS_CNT_OVF_ST_M  (BIT(4))
+#define DPORT_DBUS0_ACS_CNT_OVF_ST_V  0x1
+#define DPORT_DBUS0_ACS_CNT_OVF_ST_S  4
+/* DPORT_DBUS3_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS3_ACS_MSK_DCACHE_ST  (BIT(3))
+#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_M  (BIT(3))
+#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_V  0x1
+#define DPORT_DBUS3_ACS_MSK_DCACHE_ST_S  3
+/* DPORT_DBUS2_ACS_MSK_DCACHE_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS2_ACS_MSK_DCACHE_ST  (BIT(2))
+#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_M  (BIT(2))
+#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_V  0x1
+#define DPORT_DBUS2_ACS_MSK_DCACHE_ST_S  2
+/* DPORT_DBUS1_ACS_MSK_DCACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS1_ACS_MSK_DCACHE_ST  (BIT(1))
+#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_M  (BIT(1))
+#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_V  0x1
+#define DPORT_DBUS1_ACS_MSK_DCACHE_ST_S  1
+/* DPORT_DBUS0_ACS_MSK_DCACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_DBUS0_ACS_MSK_DCACHE_ST  (BIT(0))
+#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_M  (BIT(0))
+#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_V  0x1
+#define DPORT_DBUS0_ACS_MSK_DCACHE_ST_S  0
+
+#define DPORT_PRO_CACHE_ACS_CNT_CLR_REG          (DR_REG_EXTMEM_BASE + 0x114)
+/* DPORT_PRO_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_ACS_CNT_CLR  (BIT(1))
+#define DPORT_PRO_ICACHE_ACS_CNT_CLR_M  (BIT(1))
+#define DPORT_PRO_ICACHE_ACS_CNT_CLR_V  0x1
+#define DPORT_PRO_ICACHE_ACS_CNT_CLR_S  1
+/* DPORT_PRO_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_ACS_CNT_CLR  (BIT(0))
+#define DPORT_PRO_DCACHE_ACS_CNT_CLR_M  (BIT(0))
+#define DPORT_PRO_DCACHE_ACS_CNT_CLR_V  0x1
+#define DPORT_PRO_DCACHE_ACS_CNT_CLR_S  0
+
+#define DPORT_PRO_DCACHE_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x118)
+/* DPORT_PRO_DCACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_CPU_ATTR  0x00000007
+#define DPORT_PRO_DCACHE_CPU_ATTR_M  ((DPORT_PRO_DCACHE_CPU_ATTR_V)<<(DPORT_PRO_DCACHE_CPU_ATTR_S))
+#define DPORT_PRO_DCACHE_CPU_ATTR_V  0x7
+#define DPORT_PRO_DCACHE_CPU_ATTR_S  3
+/* DPORT_PRO_DCACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_TAG_ATTR  0x00000007
+#define DPORT_PRO_DCACHE_TAG_ATTR_M  ((DPORT_PRO_DCACHE_TAG_ATTR_V)<<(DPORT_PRO_DCACHE_TAG_ATTR_S))
+#define DPORT_PRO_DCACHE_TAG_ATTR_V  0x7
+#define DPORT_PRO_DCACHE_TAG_ATTR_S  0
+
+#define DPORT_PRO_DCACHE_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x11C)
+/* DPORT_PRO_DCACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_CPU_VADDR  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_CPU_VADDR_M  ((DPORT_PRO_DCACHE_CPU_VADDR_V)<<(DPORT_PRO_DCACHE_CPU_VADDR_S))
+#define DPORT_PRO_DCACHE_CPU_VADDR_V  0xFFFFFFFF
+#define DPORT_PRO_DCACHE_CPU_VADDR_S  0
+
+#define DPORT_PRO_ICACHE_REJECT_ST_REG          (DR_REG_EXTMEM_BASE + 0x120)
+/* DPORT_PRO_ICACHE_CPU_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_CPU_ATTR  0x00000007
+#define DPORT_PRO_ICACHE_CPU_ATTR_M  ((DPORT_PRO_ICACHE_CPU_ATTR_V)<<(DPORT_PRO_ICACHE_CPU_ATTR_S))
+#define DPORT_PRO_ICACHE_CPU_ATTR_V  0x7
+#define DPORT_PRO_ICACHE_CPU_ATTR_S  3
+/* DPORT_PRO_ICACHE_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_TAG_ATTR  0x00000007
+#define DPORT_PRO_ICACHE_TAG_ATTR_M  ((DPORT_PRO_ICACHE_TAG_ATTR_V)<<(DPORT_PRO_ICACHE_TAG_ATTR_S))
+#define DPORT_PRO_ICACHE_TAG_ATTR_V  0x7
+#define DPORT_PRO_ICACHE_TAG_ATTR_S  0
+
+#define DPORT_PRO_ICACHE_REJECT_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x124)
+/* DPORT_PRO_ICACHE_CPU_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_CPU_VADDR  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_CPU_VADDR_M  ((DPORT_PRO_ICACHE_CPU_VADDR_V)<<(DPORT_PRO_ICACHE_CPU_VADDR_S))
+#define DPORT_PRO_ICACHE_CPU_VADDR_V  0xFFFFFFFF
+#define DPORT_PRO_ICACHE_CPU_VADDR_S  0
+
+#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_REG          (DR_REG_EXTMEM_BASE + 0x128)
+/* DPORT_PRO_CACHE_MMU_ERROR_CONTENT : RO ;bitpos:[16:0] ;default: 17'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT  0x0001FFFF
+#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_M  ((DPORT_PRO_CACHE_MMU_ERROR_CONTENT_V)<<(DPORT_PRO_CACHE_MMU_ERROR_CONTENT_S))
+#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_V  0x1FFFF
+#define DPORT_PRO_CACHE_MMU_ERROR_CONTENT_S  0
+
+#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_REG          (DR_REG_EXTMEM_BASE + 0x12C)
+/* DPORT_PRO_CACHE_MMU_ERROR_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MMU_ERROR_VADDR  0xFFFFFFFF
+#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_M  ((DPORT_PRO_CACHE_MMU_ERROR_VADDR_V)<<(DPORT_PRO_CACHE_MMU_ERROR_VADDR_S))
+#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_V  0xFFFFFFFF
+#define DPORT_PRO_CACHE_MMU_ERROR_VADDR_S  0
+
+#define DPORT_PRO_CACHE_WRAP_AROUND_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x130)
+/* DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND  (BIT(1))
+#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_M  (BIT(1))
+#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_V  0x1
+#define DPORT_PRO_CACHE_SRAM_RD_WRAP_AROUND_S  1
+/* DPORT_PRO_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND  (BIT(0))
+#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_M  (BIT(0))
+#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_V  0x1
+#define DPORT_PRO_CACHE_FLASH_WRAP_AROUND_S  0
+
+#define DPORT_PRO_CACHE_MMU_POWER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x134)
+/* DPORT_PRO_CACHE_MMU_MEM_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MMU_MEM_PD  (BIT(1))
+#define DPORT_PRO_CACHE_MMU_MEM_PD_M  (BIT(1))
+#define DPORT_PRO_CACHE_MMU_MEM_PD_V  0x1
+#define DPORT_PRO_CACHE_MMU_MEM_PD_S  1
+/* DPORT_PRO_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON  (BIT(0))
+#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_M  (BIT(0))
+#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_V  0x1
+#define DPORT_PRO_CACHE_MMU_MEM_FORCE_ON_S  0
+
+#define DPORT_PRO_CACHE_STATE_REG          (DR_REG_EXTMEM_BASE + 0x138)
+/* DPORT_PRO_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_STATE  0x00000FFF
+#define DPORT_PRO_DCACHE_STATE_M  ((DPORT_PRO_DCACHE_STATE_V)<<(DPORT_PRO_DCACHE_STATE_S))
+#define DPORT_PRO_DCACHE_STATE_V  0xFFF
+#define DPORT_PRO_DCACHE_STATE_S  12
+/* DPORT_PRO_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_STATE  0x00000FFF
+#define DPORT_PRO_ICACHE_STATE_M  ((DPORT_PRO_ICACHE_STATE_V)<<(DPORT_PRO_ICACHE_STATE_S))
+#define DPORT_PRO_ICACHE_STATE_V  0xFFF
+#define DPORT_PRO_ICACHE_STATE_S  0
+
+#define DPORT_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG          (DR_REG_EXTMEM_BASE + 0x13C)
+/* DPORT_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_RECORD_DISABLE_G0CB_DECRYPT  (BIT(1))
+#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_M  (BIT(1))
+#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_V  0x1
+#define DPORT_RECORD_DISABLE_G0CB_DECRYPT_S  1
+/* DPORT_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_RECORD_DISABLE_DB_ENCRYPT  (BIT(0))
+#define DPORT_RECORD_DISABLE_DB_ENCRYPT_M  (BIT(0))
+#define DPORT_RECORD_DISABLE_DB_ENCRYPT_V  0x1
+#define DPORT_RECORD_DISABLE_DB_ENCRYPT_S  0
+
+#define DPORT_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG          (DR_REG_EXTMEM_BASE + 0x140)
+/* DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT  (BIT(2))
+#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_M  (BIT(2))
+#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_V  0x1
+#define DPORT_CLK_FORCE_ON_AUTOMATIC_ENCRYPT_DECRYPT_S  2
+/* DPORT_CLK_FORCE_ON_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT  (BIT(1))
+#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_M  (BIT(1))
+#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_V  0x1
+#define DPORT_CLK_FORCE_ON_G0CB_DECRYPT_S  1
+/* DPORT_CLK_FORCE_ON_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_CLK_FORCE_ON_DB_ENCRYPT  (BIT(0))
+#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_M  (BIT(0))
+#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_V  0x1
+#define DPORT_CLK_FORCE_ON_DB_ENCRYPT_S  0
+
+#define DPORT_CACHE_BRIDGE_ARBITER_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x144)
+/* DPORT_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ALLOC_WB_HOLD_ARBITER  (BIT(0))
+#define DPORT_ALLOC_WB_HOLD_ARBITER_M  (BIT(0))
+#define DPORT_ALLOC_WB_HOLD_ARBITER_V  0x1
+#define DPORT_ALLOC_WB_HOLD_ARBITER_S  0
+
+#define DPORT_CACHE_PRELOAD_INT_CTRL_REG          (DR_REG_EXTMEM_BASE + 0x148)
+/* DPORT_PRO_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR  (BIT(5))
+#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_M  (BIT(5))
+#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_V  0x1
+#define DPORT_PRO_DCACHE_PRELOAD_INT_CLR_S  5
+/* DPORT_PRO_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA  (BIT(4))
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_M  (BIT(4))
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_V  0x1
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ENA_S  4
+/* DPORT_PRO_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ST  (BIT(3))
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_M  (BIT(3))
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_V  0x1
+#define DPORT_PRO_DCACHE_PRELOAD_INT_ST_S  3
+/* DPORT_PRO_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR  (BIT(2))
+#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_M  (BIT(2))
+#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_V  0x1
+#define DPORT_PRO_ICACHE_PRELOAD_INT_CLR_S  2
+/* DPORT_PRO_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA  (BIT(1))
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_M  (BIT(1))
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_V  0x1
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ENA_S  1
+/* DPORT_PRO_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ST  (BIT(0))
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_M  (BIT(0))
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_V  0x1
+#define DPORT_PRO_ICACHE_PRELOAD_INT_ST_S  0
+
+#define EXTMEM_CLOCK_GATE_REG          (DR_REG_EXTMEM_BASE + 0x14C)
+/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define EXTMEM_CLK_EN  (BIT(0))
+#define EXTMEM_CLK_EN_M  (BIT(0))
+#define EXTMEM_CLK_EN_V  0x1
+#define EXTMEM_CLK_EN_S  0
+
+#define EXTMEM_DATE_REG          (DR_REG_EXTMEM_BASE + 0x3FC)
+/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810250 ; */
+/*description: */
+#define EXTMEM_DATE  0x0FFFFFFF
+#define EXTMEM_DATE_M  ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S))
+#define EXTMEM_DATE_V  0xFFFFFFF
+#define EXTMEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_EXTMEM_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/fe_reg.h b/components/soc/esp32s2beta/include/soc/fe_reg.h
new file mode 100644
index 000000000..7705586d7
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/fe_reg.h
@@ -0,0 +1,41 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc.h"
+
+/* Some of the RF frontend control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
+#define FE_IQ_EST_FORCE_PU (BIT(5))
+#define FE_IQ_EST_FORCE_PU_M (BIT(5))
+#define FE_IQ_EST_FORCE_PU_V 1
+#define FE_IQ_EST_FORCE_PU_S 5
+#define FE_IQ_EST_FORCE_PD (BIT(4))
+#define FE_IQ_EST_FORCE_PD_M (BIT(4))
+#define FE_IQ_EST_FORCE_PD_V 1
+#define FE_IQ_EST_FORCE_PD_S 4
+
+#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
+#define FE2_TX_INF_FORCE_PU (BIT(10))
+#define FE2_TX_INF_FORCE_PU_M (BIT(10))
+#define FE2_TX_INF_FORCE_PU_V 1
+#define FE2_TX_INF_FORCE_PU_S 10
+#define FE2_TX_INF_FORCE_PD (BIT(9))
+#define FE2_TX_INF_FORCE_PD_M (BIT(9))
+#define FE2_TX_INF_FORCE_PD_V 1
+#define FE2_TX_INF_FORCE_PD_S 9
diff --git a/components/soc/esp32s2beta/include/soc/frc_timer_reg.h b/components/soc/esp32s2beta/include/soc/frc_timer_reg.h
new file mode 100644
index 000000000..a2152c5c9
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/frc_timer_reg.h
@@ -0,0 +1,52 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_FRC_TIMER_REG_H_
+#define _SOC_FRC_TIMER_REG_H_
+
+#include "soc.h"
+
+/**
+ * These are the register definitions for "legacy" timers
+ */
+
+#define REG_FRC_TIMER_BASE(i)           (DR_REG_FRC_TIMER_BASE + i*0x20)
+
+#define FRC_TIMER_LOAD_REG(i)           (REG_FRC_TIMER_BASE(i) + 0x0)   // timer load value (23 bit for i==0, 32 bit for i==1)
+#define FRC_TIMER_LOAD_VALUE(i)         ((i == 0)?0x007FFFFF:0xffffffff)
+#define FRC_TIMER_LOAD_VALUE_S          0
+
+#define FRC_TIMER_COUNT_REG(i)          (REG_FRC_TIMER_BASE(i) + 0x4)   // timer count value (23 bit for i==0, 32 bit for i==1)
+#define FRC_TIMER_COUNT                 ((i == 0)?0x007FFFFF:0xffffffff)
+#define FRC_TIMER_COUNT_S               0
+
+#define FRC_TIMER_CTRL_REG(i)           (REG_FRC_TIMER_BASE(i) + 0x8)
+#define FRC_TIMER_INT_STATUS            (BIT(8))        // interrupt status (RO)
+#define FRC_TIMER_ENABLE                (BIT(7))        // enable timer
+#define FRC_TIMER_AUTOLOAD              (BIT(6))        // enable autoload
+#define FRC_TIMER_PRESCALER             0x00000007
+#define FRC_TIMER_PRESCALER_S           1
+#define FRC_TIMER_PRESCALER_1           (0 << FRC_TIMER_PRESCALER_S)
+#define FRC_TIMER_PRESCALER_16          (2 << FRC_TIMER_PRESCALER_S)
+#define FRC_TIMER_PRESCALER_256         (4 << FRC_TIMER_PRESCALER_S)
+#define FRC_TIMER_LEVEL_INT             (BIT(0))        // 1: level, 0: edge
+
+#define FRC_TIMER_INT_REG(i)            (REG_FRC_TIMER_BASE(i) + 0xC)
+#define FRC_TIMER_INT_CLR               (BIT(0))        // clear interrupt
+
+#define FRC_TIMER_ALARM_REG(i)          (REG_FRC_TIMER_BASE(i) + 0x10)  // timer alarm value; register only present for i == 1
+#define FRC_TIMER_ALARM                 0xFFFFFFFF
+#define FRC_TIMER_ALARM_S               0
+
+#endif //_SOC_FRC_TIMER_REG_H_
diff --git a/components/soc/esp32s2beta/include/soc/gpio_reg.h b/components/soc/esp32s2beta/include/soc/gpio_reg.h
new file mode 100644
index 000000000..03ed89292
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/gpio_reg.h
@@ -0,0 +1,9222 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_REG_H_
+#define _SOC_GPIO_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define GPIO_PIN_CONFIG_MSB                    12
+#define GPIO_PIN_CONFIG_LSB                     11
+#define GPIO_PIN_CONFIG_MASK                   0x00001800
+#define GPIO_PIN_CONFIG_GET(x)                 (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB)
+#define GPIO_PIN_CONFIG_SET(x)                  (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK)
+
+#define GPIO_WAKEUP_ENABLE                     1
+#define GPIO_WAKEUP_DISABLE                    (~GPIO_WAKEUP_ENABLE)
+#define GPIO_PIN_WAKEUP_ENABLE_MSB             10
+#define GPIO_PIN_WAKEUP_ENABLE_LSB              10
+#define GPIO_PIN_WAKEUP_ENABLE_MASK            0x00000400
+#define GPIO_PIN_WAKEUP_ENABLE_GET(x)          (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB)
+#define GPIO_PIN_WAKEUP_ENABLE_SET(x)           (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK)
+
+#define GPIO_PIN_INT_TYPE_MASK                 0x380
+#define GPIO_PIN_INT_TYPE_MSB                  9
+#define GPIO_PIN_INT_TYPE_LSB                  7
+#define GPIO_PIN_INT_TYPE_GET(x)               (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB)
+#define GPIO_PIN_INT_TYPE_SET(x)               (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK)
+
+#define GPIO_PAD_DRIVER_ENABLE                 1
+#define GPIO_PAD_DRIVER_DISABLE                        (~GPIO_PAD_DRIVER_ENABLE)
+#define GPIO_PIN_PAD_DRIVER_MSB                        2
+#define GPIO_PIN_PAD_DRIVER_LSB                        2
+#define GPIO_PIN_PAD_DRIVER_MASK               0x00000004
+#define GPIO_PIN_PAD_DRIVER_GET(x)             (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB)
+#define GPIO_PIN_PAD_DRIVER_SET(x)             (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK)
+
+#define GPIO_BT_SELECT_REG          (DR_REG_GPIO_BASE + 0x0)
+/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_BT_SEL  0xFFFFFFFF
+#define GPIO_BT_SEL_M  ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S))
+#define GPIO_BT_SEL_V  0xFFFFFFFF
+#define GPIO_BT_SEL_S  0
+
+#define GPIO_OUT_REG          (DR_REG_GPIO_BASE + 0x4)
+/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_OUT_DATA  0xFFFFFFFF
+#define GPIO_OUT_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
+#define GPIO_OUT_DATA_V  0xFFFFFFFF
+#define GPIO_OUT_DATA_S  0
+
+#define GPIO_OUT_W1TS_REG          (DR_REG_GPIO_BASE + 0x8)
+/* GPIO_OUT_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_OUT_W1TS  0xFFFFFFFF
+#define GPIO_OUT_W1TS_M  ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S))
+#define GPIO_OUT_W1TS_V  0xFFFFFFFF
+#define GPIO_OUT_W1TS_S  0
+
+#define GPIO_OUT_W1TC_REG          (DR_REG_GPIO_BASE + 0xC)
+/* GPIO_OUT_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_OUT_W1TC  0xFFFFFFFF
+#define GPIO_OUT_W1TC_M  ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S))
+#define GPIO_OUT_W1TC_V  0xFFFFFFFF
+#define GPIO_OUT_W1TC_S  0
+
+#define GPIO_OUT1_REG          (DR_REG_GPIO_BASE + 0x10)
+/* GPIO_OUT1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_OUT1_DATA  0x003FFFFF
+#define GPIO_OUT1_DATA_M  ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S))
+#define GPIO_OUT1_DATA_V  0x3FFFFF
+#define GPIO_OUT1_DATA_S  0
+
+#define GPIO_OUT1_W1TS_REG          (DR_REG_GPIO_BASE + 0x14)
+/* GPIO_OUT1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_OUT1_W1TS  0x003FFFFF
+#define GPIO_OUT1_W1TS_M  ((GPIO_OUT1_W1TS_V)<<(GPIO_OUT1_W1TS_S))
+#define GPIO_OUT1_W1TS_V  0x3FFFFF
+#define GPIO_OUT1_W1TS_S  0
+
+#define GPIO_OUT1_W1TC_REG          (DR_REG_GPIO_BASE + 0x18)
+/* GPIO_OUT1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_OUT1_W1TC  0x003FFFFF
+#define GPIO_OUT1_W1TC_M  ((GPIO_OUT1_W1TC_V)<<(GPIO_OUT1_W1TC_S))
+#define GPIO_OUT1_W1TC_V  0x3FFFFF
+#define GPIO_OUT1_W1TC_S  0
+
+#define GPIO_SDIO_SELECT_REG          (DR_REG_GPIO_BASE + 0x1C)
+/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SDIO_SEL  0x000000FF
+#define GPIO_SDIO_SEL_M  ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S))
+#define GPIO_SDIO_SEL_V  0xFF
+#define GPIO_SDIO_SEL_S  0
+
+#define GPIO_ENABLE_REG          (DR_REG_GPIO_BASE + 0x20)
+/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_ENABLE_DATA  0xFFFFFFFF
+#define GPIO_ENABLE_DATA_M  ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S))
+#define GPIO_ENABLE_DATA_V  0xFFFFFFFF
+#define GPIO_ENABLE_DATA_S  0
+
+#define GPIO_ENABLE_W1TS_REG          (DR_REG_GPIO_BASE + 0x24)
+/* GPIO_ENABLE_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_ENABLE_W1TS  0xFFFFFFFF
+#define GPIO_ENABLE_W1TS_M  ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S))
+#define GPIO_ENABLE_W1TS_V  0xFFFFFFFF
+#define GPIO_ENABLE_W1TS_S  0
+
+#define GPIO_ENABLE_W1TC_REG          (DR_REG_GPIO_BASE + 0x28)
+/* GPIO_ENABLE_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_ENABLE_W1TC  0xFFFFFFFF
+#define GPIO_ENABLE_W1TC_M  ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S))
+#define GPIO_ENABLE_W1TC_V  0xFFFFFFFF
+#define GPIO_ENABLE_W1TC_S  0
+
+#define GPIO_ENABLE1_REG          (DR_REG_GPIO_BASE + 0x2C)
+/* GPIO_ENABLE1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_ENABLE1_DATA  0x003FFFFF
+#define GPIO_ENABLE1_DATA_M  ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S))
+#define GPIO_ENABLE1_DATA_V  0x3FFFFF
+#define GPIO_ENABLE1_DATA_S  0
+
+#define GPIO_ENABLE1_W1TS_REG          (DR_REG_GPIO_BASE + 0x30)
+/* GPIO_ENABLE1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_ENABLE1_W1TS  0x003FFFFF
+#define GPIO_ENABLE1_W1TS_M  ((GPIO_ENABLE1_W1TS_V)<<(GPIO_ENABLE1_W1TS_S))
+#define GPIO_ENABLE1_W1TS_V  0x3FFFFF
+#define GPIO_ENABLE1_W1TS_S  0
+
+#define GPIO_ENABLE1_W1TC_REG          (DR_REG_GPIO_BASE + 0x34)
+/* GPIO_ENABLE1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_ENABLE1_W1TC  0x003FFFFF
+#define GPIO_ENABLE1_W1TC_M  ((GPIO_ENABLE1_W1TC_V)<<(GPIO_ENABLE1_W1TC_S))
+#define GPIO_ENABLE1_W1TC_V  0x3FFFFF
+#define GPIO_ENABLE1_W1TC_S  0
+
+#define GPIO_STRAP_REG          (DR_REG_GPIO_BASE + 0x38)
+/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default:  ; */
+/*description: */
+#define GPIO_STRAPPING  0x0000FFFF
+#define GPIO_STRAPPING_M  ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S))
+#define GPIO_STRAPPING_V  0xFFFF
+#define GPIO_STRAPPING_S  0
+
+#define GPIO_IN_REG          (DR_REG_GPIO_BASE + 0x3C)
+/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default:  ; */
+/*description: */
+#define GPIO_IN_DATA  0xFFFFFFFF
+#define GPIO_IN_DATA_M  ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S))
+#define GPIO_IN_DATA_V  0xFFFFFFFF
+#define GPIO_IN_DATA_S  0
+
+#define GPIO_IN1_REG          (DR_REG_GPIO_BASE + 0x40)
+/* GPIO_IN1_DATA : RO ;bitpos:[21:0] ;default:  ; */
+/*description: */
+#define GPIO_IN1_DATA  0x003FFFFF
+#define GPIO_IN1_DATA_M  ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S))
+#define GPIO_IN1_DATA_V  0x3FFFFF
+#define GPIO_IN1_DATA_S  0
+
+#define GPIO_STATUS_REG          (DR_REG_GPIO_BASE + 0x44)
+/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_STATUS_INT  0xFFFFFFFF
+#define GPIO_STATUS_INT_M  ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S))
+#define GPIO_STATUS_INT_V  0xFFFFFFFF
+#define GPIO_STATUS_INT_S  0
+
+#define GPIO_STATUS_W1TS_REG          (DR_REG_GPIO_BASE + 0x48)
+/* GPIO_STATUS_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_STATUS_W1TS  0xFFFFFFFF
+#define GPIO_STATUS_W1TS_M  ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S))
+#define GPIO_STATUS_W1TS_V  0xFFFFFFFF
+#define GPIO_STATUS_W1TS_S  0
+
+#define GPIO_STATUS_W1TC_REG          (DR_REG_GPIO_BASE + 0x4C)
+/* GPIO_STATUS_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_STATUS_W1TC  0xFFFFFFFF
+#define GPIO_STATUS_W1TC_M  ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S))
+#define GPIO_STATUS_W1TC_V  0xFFFFFFFF
+#define GPIO_STATUS_W1TC_S  0
+
+#define GPIO_STATUS1_REG          (DR_REG_GPIO_BASE + 0x50)
+/* GPIO_STATUS1_INT : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_STATUS1_INT  0x003FFFFF
+#define GPIO_STATUS1_INT_M  ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S))
+#define GPIO_STATUS1_INT_V  0x3FFFFF
+#define GPIO_STATUS1_INT_S  0
+
+#define GPIO_STATUS1_W1TS_REG          (DR_REG_GPIO_BASE + 0x54)
+/* GPIO_STATUS1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_STATUS1_W1TS  0x003FFFFF
+#define GPIO_STATUS1_W1TS_M  ((GPIO_STATUS1_W1TS_V)<<(GPIO_STATUS1_W1TS_S))
+#define GPIO_STATUS1_W1TS_V  0x3FFFFF
+#define GPIO_STATUS1_W1TS_S  0
+
+#define GPIO_STATUS1_W1TC_REG          (DR_REG_GPIO_BASE + 0x58)
+/* GPIO_STATUS1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_STATUS1_W1TC  0x003FFFFF
+#define GPIO_STATUS1_W1TC_M  ((GPIO_STATUS1_W1TC_V)<<(GPIO_STATUS1_W1TC_S))
+#define GPIO_STATUS1_W1TC_V  0x3FFFFF
+#define GPIO_STATUS1_W1TC_S  0
+
+#define GPIO_PCPU_INT_REG          (DR_REG_GPIO_BASE + 0x5C)
+/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_PROCPU_INT  0xFFFFFFFF
+#define GPIO_PROCPU_INT_M  ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S))
+#define GPIO_PROCPU_INT_V  0xFFFFFFFF
+#define GPIO_PROCPU_INT_S  0
+
+#define GPIO_PCPU_NMI_INT_REG          (DR_REG_GPIO_BASE + 0x60)
+/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_PROCPU_NMI_INT  0xFFFFFFFF
+#define GPIO_PROCPU_NMI_INT_M  ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S))
+#define GPIO_PROCPU_NMI_INT_V  0xFFFFFFFF
+#define GPIO_PROCPU_NMI_INT_S  0
+
+#define GPIO_CPUSDIO_INT_REG          (DR_REG_GPIO_BASE + 0x64)
+/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_SDIO_INT  0xFFFFFFFF
+#define GPIO_SDIO_INT_M  ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S))
+#define GPIO_SDIO_INT_V  0xFFFFFFFF
+#define GPIO_SDIO_INT_S  0
+
+#define GPIO_PCPU_INT1_REG          (DR_REG_GPIO_BASE + 0x68)
+/* GPIO_PROCPU_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_PROCPU_INT_H  0x003FFFFF
+#define GPIO_PROCPU_INT_H_M  ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S))
+#define GPIO_PROCPU_INT_H_V  0x3FFFFF
+#define GPIO_PROCPU_INT_H_S  0
+
+#define GPIO_PCPU_NMI_INT1_REG          (DR_REG_GPIO_BASE + 0x6C)
+/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_PROCPU_NMI_INT_H  0x003FFFFF
+#define GPIO_PROCPU_NMI_INT_H_M  ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S))
+#define GPIO_PROCPU_NMI_INT_H_V  0x3FFFFF
+#define GPIO_PROCPU_NMI_INT_H_S  0
+
+#define GPIO_CPUSDIO_INT1_REG          (DR_REG_GPIO_BASE + 0x70)
+/* GPIO_SDIO_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_SDIO_INT_H  0x003FFFFF
+#define GPIO_SDIO_INT_H_M  ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S))
+#define GPIO_SDIO_INT_H_V  0x3FFFFF
+#define GPIO_SDIO_INT_H_S  0
+
+#define GPIO_PIN0_REG          (DR_REG_GPIO_BASE + 0x74)
+/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN0_INT_ENA  0x0000001F
+#define GPIO_PIN0_INT_ENA_M  ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S))
+#define GPIO_PIN0_INT_ENA_V  0x1F
+#define GPIO_PIN0_INT_ENA_S  13
+/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_CONFIG  0x00000003
+#define GPIO_PIN0_CONFIG_M  ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S))
+#define GPIO_PIN0_CONFIG_V  0x3
+#define GPIO_PIN0_CONFIG_S  11
+/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN0_WAKEUP_ENABLE_S  10
+/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN0_INT_TYPE  0x00000007
+#define GPIO_PIN0_INT_TYPE_M  ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S))
+#define GPIO_PIN0_INT_TYPE_V  0x7
+#define GPIO_PIN0_INT_TYPE_S  7
+/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN0_SYNC1_BYPASS_M  ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S))
+#define GPIO_PIN0_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC1_BYPASS_S  3
+/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN0_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN0_PAD_DRIVER_V  0x1
+#define GPIO_PIN0_PAD_DRIVER_S  2
+/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN0_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN0_SYNC2_BYPASS_M  ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S))
+#define GPIO_PIN0_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN0_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN1_REG          (DR_REG_GPIO_BASE + 0x78)
+/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN1_INT_ENA  0x0000001F
+#define GPIO_PIN1_INT_ENA_M  ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S))
+#define GPIO_PIN1_INT_ENA_V  0x1F
+#define GPIO_PIN1_INT_ENA_S  13
+/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_CONFIG  0x00000003
+#define GPIO_PIN1_CONFIG_M  ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S))
+#define GPIO_PIN1_CONFIG_V  0x3
+#define GPIO_PIN1_CONFIG_S  11
+/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN1_WAKEUP_ENABLE_S  10
+/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN1_INT_TYPE  0x00000007
+#define GPIO_PIN1_INT_TYPE_M  ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S))
+#define GPIO_PIN1_INT_TYPE_V  0x7
+#define GPIO_PIN1_INT_TYPE_S  7
+/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN1_SYNC1_BYPASS_M  ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S))
+#define GPIO_PIN1_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC1_BYPASS_S  3
+/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN1_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN1_PAD_DRIVER_V  0x1
+#define GPIO_PIN1_PAD_DRIVER_S  2
+/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN1_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN1_SYNC2_BYPASS_M  ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S))
+#define GPIO_PIN1_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN1_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN2_REG          (DR_REG_GPIO_BASE + 0x7C)
+/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN2_INT_ENA  0x0000001F
+#define GPIO_PIN2_INT_ENA_M  ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S))
+#define GPIO_PIN2_INT_ENA_V  0x1F
+#define GPIO_PIN2_INT_ENA_S  13
+/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_CONFIG  0x00000003
+#define GPIO_PIN2_CONFIG_M  ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S))
+#define GPIO_PIN2_CONFIG_V  0x3
+#define GPIO_PIN2_CONFIG_S  11
+/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN2_WAKEUP_ENABLE_S  10
+/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN2_INT_TYPE  0x00000007
+#define GPIO_PIN2_INT_TYPE_M  ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S))
+#define GPIO_PIN2_INT_TYPE_V  0x7
+#define GPIO_PIN2_INT_TYPE_S  7
+/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN2_SYNC1_BYPASS_M  ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S))
+#define GPIO_PIN2_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC1_BYPASS_S  3
+/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN2_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN2_PAD_DRIVER_V  0x1
+#define GPIO_PIN2_PAD_DRIVER_S  2
+/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN2_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN2_SYNC2_BYPASS_M  ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S))
+#define GPIO_PIN2_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN2_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN3_REG          (DR_REG_GPIO_BASE + 0x80)
+/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN3_INT_ENA  0x0000001F
+#define GPIO_PIN3_INT_ENA_M  ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S))
+#define GPIO_PIN3_INT_ENA_V  0x1F
+#define GPIO_PIN3_INT_ENA_S  13
+/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_CONFIG  0x00000003
+#define GPIO_PIN3_CONFIG_M  ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S))
+#define GPIO_PIN3_CONFIG_V  0x3
+#define GPIO_PIN3_CONFIG_S  11
+/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN3_WAKEUP_ENABLE_S  10
+/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN3_INT_TYPE  0x00000007
+#define GPIO_PIN3_INT_TYPE_M  ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S))
+#define GPIO_PIN3_INT_TYPE_V  0x7
+#define GPIO_PIN3_INT_TYPE_S  7
+/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN3_SYNC1_BYPASS_M  ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S))
+#define GPIO_PIN3_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC1_BYPASS_S  3
+/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN3_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN3_PAD_DRIVER_V  0x1
+#define GPIO_PIN3_PAD_DRIVER_S  2
+/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN3_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN3_SYNC2_BYPASS_M  ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S))
+#define GPIO_PIN3_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN3_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN4_REG          (DR_REG_GPIO_BASE + 0x84)
+/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN4_INT_ENA  0x0000001F
+#define GPIO_PIN4_INT_ENA_M  ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S))
+#define GPIO_PIN4_INT_ENA_V  0x1F
+#define GPIO_PIN4_INT_ENA_S  13
+/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_CONFIG  0x00000003
+#define GPIO_PIN4_CONFIG_M  ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S))
+#define GPIO_PIN4_CONFIG_V  0x3
+#define GPIO_PIN4_CONFIG_S  11
+/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN4_WAKEUP_ENABLE_S  10
+/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN4_INT_TYPE  0x00000007
+#define GPIO_PIN4_INT_TYPE_M  ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S))
+#define GPIO_PIN4_INT_TYPE_V  0x7
+#define GPIO_PIN4_INT_TYPE_S  7
+/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN4_SYNC1_BYPASS_M  ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S))
+#define GPIO_PIN4_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC1_BYPASS_S  3
+/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN4_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN4_PAD_DRIVER_V  0x1
+#define GPIO_PIN4_PAD_DRIVER_S  2
+/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN4_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN4_SYNC2_BYPASS_M  ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S))
+#define GPIO_PIN4_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN4_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN5_REG          (DR_REG_GPIO_BASE + 0x88)
+/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN5_INT_ENA  0x0000001F
+#define GPIO_PIN5_INT_ENA_M  ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S))
+#define GPIO_PIN5_INT_ENA_V  0x1F
+#define GPIO_PIN5_INT_ENA_S  13
+/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_CONFIG  0x00000003
+#define GPIO_PIN5_CONFIG_M  ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S))
+#define GPIO_PIN5_CONFIG_V  0x3
+#define GPIO_PIN5_CONFIG_S  11
+/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN5_WAKEUP_ENABLE_S  10
+/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN5_INT_TYPE  0x00000007
+#define GPIO_PIN5_INT_TYPE_M  ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S))
+#define GPIO_PIN5_INT_TYPE_V  0x7
+#define GPIO_PIN5_INT_TYPE_S  7
+/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN5_SYNC1_BYPASS_M  ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S))
+#define GPIO_PIN5_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC1_BYPASS_S  3
+/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN5_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN5_PAD_DRIVER_V  0x1
+#define GPIO_PIN5_PAD_DRIVER_S  2
+/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN5_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN5_SYNC2_BYPASS_M  ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S))
+#define GPIO_PIN5_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN5_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN6_REG          (DR_REG_GPIO_BASE + 0x8C)
+/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN6_INT_ENA  0x0000001F
+#define GPIO_PIN6_INT_ENA_M  ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S))
+#define GPIO_PIN6_INT_ENA_V  0x1F
+#define GPIO_PIN6_INT_ENA_S  13
+/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_CONFIG  0x00000003
+#define GPIO_PIN6_CONFIG_M  ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S))
+#define GPIO_PIN6_CONFIG_V  0x3
+#define GPIO_PIN6_CONFIG_S  11
+/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN6_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN6_WAKEUP_ENABLE_S  10
+/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN6_INT_TYPE  0x00000007
+#define GPIO_PIN6_INT_TYPE_M  ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S))
+#define GPIO_PIN6_INT_TYPE_V  0x7
+#define GPIO_PIN6_INT_TYPE_S  7
+/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN6_SYNC1_BYPASS_M  ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S))
+#define GPIO_PIN6_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC1_BYPASS_S  3
+/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN6_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN6_PAD_DRIVER_V  0x1
+#define GPIO_PIN6_PAD_DRIVER_S  2
+/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN6_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN6_SYNC2_BYPASS_M  ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S))
+#define GPIO_PIN6_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN6_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN7_REG          (DR_REG_GPIO_BASE + 0x90)
+/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN7_INT_ENA  0x0000001F
+#define GPIO_PIN7_INT_ENA_M  ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S))
+#define GPIO_PIN7_INT_ENA_V  0x1F
+#define GPIO_PIN7_INT_ENA_S  13
+/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_CONFIG  0x00000003
+#define GPIO_PIN7_CONFIG_M  ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S))
+#define GPIO_PIN7_CONFIG_V  0x3
+#define GPIO_PIN7_CONFIG_S  11
+/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN7_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN7_WAKEUP_ENABLE_S  10
+/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN7_INT_TYPE  0x00000007
+#define GPIO_PIN7_INT_TYPE_M  ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S))
+#define GPIO_PIN7_INT_TYPE_V  0x7
+#define GPIO_PIN7_INT_TYPE_S  7
+/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN7_SYNC1_BYPASS_M  ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S))
+#define GPIO_PIN7_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC1_BYPASS_S  3
+/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN7_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN7_PAD_DRIVER_V  0x1
+#define GPIO_PIN7_PAD_DRIVER_S  2
+/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN7_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN7_SYNC2_BYPASS_M  ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S))
+#define GPIO_PIN7_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN7_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN8_REG          (DR_REG_GPIO_BASE + 0x94)
+/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN8_INT_ENA  0x0000001F
+#define GPIO_PIN8_INT_ENA_M  ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S))
+#define GPIO_PIN8_INT_ENA_V  0x1F
+#define GPIO_PIN8_INT_ENA_S  13
+/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_CONFIG  0x00000003
+#define GPIO_PIN8_CONFIG_M  ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S))
+#define GPIO_PIN8_CONFIG_V  0x3
+#define GPIO_PIN8_CONFIG_S  11
+/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN8_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN8_WAKEUP_ENABLE_S  10
+/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN8_INT_TYPE  0x00000007
+#define GPIO_PIN8_INT_TYPE_M  ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S))
+#define GPIO_PIN8_INT_TYPE_V  0x7
+#define GPIO_PIN8_INT_TYPE_S  7
+/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN8_SYNC1_BYPASS_M  ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S))
+#define GPIO_PIN8_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC1_BYPASS_S  3
+/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN8_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN8_PAD_DRIVER_V  0x1
+#define GPIO_PIN8_PAD_DRIVER_S  2
+/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN8_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN8_SYNC2_BYPASS_M  ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S))
+#define GPIO_PIN8_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN8_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN9_REG          (DR_REG_GPIO_BASE + 0x98)
+/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN9_INT_ENA  0x0000001F
+#define GPIO_PIN9_INT_ENA_M  ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S))
+#define GPIO_PIN9_INT_ENA_V  0x1F
+#define GPIO_PIN9_INT_ENA_S  13
+/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_CONFIG  0x00000003
+#define GPIO_PIN9_CONFIG_M  ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S))
+#define GPIO_PIN9_CONFIG_V  0x3
+#define GPIO_PIN9_CONFIG_S  11
+/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN9_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN9_WAKEUP_ENABLE_S  10
+/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN9_INT_TYPE  0x00000007
+#define GPIO_PIN9_INT_TYPE_M  ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S))
+#define GPIO_PIN9_INT_TYPE_V  0x7
+#define GPIO_PIN9_INT_TYPE_S  7
+/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN9_SYNC1_BYPASS_M  ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S))
+#define GPIO_PIN9_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC1_BYPASS_S  3
+/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN9_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN9_PAD_DRIVER_V  0x1
+#define GPIO_PIN9_PAD_DRIVER_S  2
+/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN9_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN9_SYNC2_BYPASS_M  ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S))
+#define GPIO_PIN9_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN9_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN10_REG          (DR_REG_GPIO_BASE + 0x9C)
+/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN10_INT_ENA  0x0000001F
+#define GPIO_PIN10_INT_ENA_M  ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S))
+#define GPIO_PIN10_INT_ENA_V  0x1F
+#define GPIO_PIN10_INT_ENA_S  13
+/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_CONFIG  0x00000003
+#define GPIO_PIN10_CONFIG_M  ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S))
+#define GPIO_PIN10_CONFIG_V  0x3
+#define GPIO_PIN10_CONFIG_S  11
+/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN10_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN10_WAKEUP_ENABLE_S  10
+/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN10_INT_TYPE  0x00000007
+#define GPIO_PIN10_INT_TYPE_M  ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S))
+#define GPIO_PIN10_INT_TYPE_V  0x7
+#define GPIO_PIN10_INT_TYPE_S  7
+/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN10_SYNC1_BYPASS_M  ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S))
+#define GPIO_PIN10_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC1_BYPASS_S  3
+/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN10_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN10_PAD_DRIVER_V  0x1
+#define GPIO_PIN10_PAD_DRIVER_S  2
+/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN10_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN10_SYNC2_BYPASS_M  ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S))
+#define GPIO_PIN10_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN10_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN11_REG          (DR_REG_GPIO_BASE + 0xA0)
+/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN11_INT_ENA  0x0000001F
+#define GPIO_PIN11_INT_ENA_M  ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S))
+#define GPIO_PIN11_INT_ENA_V  0x1F
+#define GPIO_PIN11_INT_ENA_S  13
+/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_CONFIG  0x00000003
+#define GPIO_PIN11_CONFIG_M  ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S))
+#define GPIO_PIN11_CONFIG_V  0x3
+#define GPIO_PIN11_CONFIG_S  11
+/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN11_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN11_WAKEUP_ENABLE_S  10
+/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN11_INT_TYPE  0x00000007
+#define GPIO_PIN11_INT_TYPE_M  ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S))
+#define GPIO_PIN11_INT_TYPE_V  0x7
+#define GPIO_PIN11_INT_TYPE_S  7
+/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN11_SYNC1_BYPASS_M  ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S))
+#define GPIO_PIN11_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC1_BYPASS_S  3
+/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN11_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN11_PAD_DRIVER_V  0x1
+#define GPIO_PIN11_PAD_DRIVER_S  2
+/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN11_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN11_SYNC2_BYPASS_M  ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S))
+#define GPIO_PIN11_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN11_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN12_REG          (DR_REG_GPIO_BASE + 0xA4)
+/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN12_INT_ENA  0x0000001F
+#define GPIO_PIN12_INT_ENA_M  ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S))
+#define GPIO_PIN12_INT_ENA_V  0x1F
+#define GPIO_PIN12_INT_ENA_S  13
+/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_CONFIG  0x00000003
+#define GPIO_PIN12_CONFIG_M  ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S))
+#define GPIO_PIN12_CONFIG_V  0x3
+#define GPIO_PIN12_CONFIG_S  11
+/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN12_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN12_WAKEUP_ENABLE_S  10
+/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN12_INT_TYPE  0x00000007
+#define GPIO_PIN12_INT_TYPE_M  ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S))
+#define GPIO_PIN12_INT_TYPE_V  0x7
+#define GPIO_PIN12_INT_TYPE_S  7
+/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN12_SYNC1_BYPASS_M  ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S))
+#define GPIO_PIN12_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC1_BYPASS_S  3
+/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN12_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN12_PAD_DRIVER_V  0x1
+#define GPIO_PIN12_PAD_DRIVER_S  2
+/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN12_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN12_SYNC2_BYPASS_M  ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S))
+#define GPIO_PIN12_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN12_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN13_REG          (DR_REG_GPIO_BASE + 0xA8)
+/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN13_INT_ENA  0x0000001F
+#define GPIO_PIN13_INT_ENA_M  ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S))
+#define GPIO_PIN13_INT_ENA_V  0x1F
+#define GPIO_PIN13_INT_ENA_S  13
+/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_CONFIG  0x00000003
+#define GPIO_PIN13_CONFIG_M  ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S))
+#define GPIO_PIN13_CONFIG_V  0x3
+#define GPIO_PIN13_CONFIG_S  11
+/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN13_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN13_WAKEUP_ENABLE_S  10
+/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN13_INT_TYPE  0x00000007
+#define GPIO_PIN13_INT_TYPE_M  ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S))
+#define GPIO_PIN13_INT_TYPE_V  0x7
+#define GPIO_PIN13_INT_TYPE_S  7
+/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN13_SYNC1_BYPASS_M  ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S))
+#define GPIO_PIN13_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC1_BYPASS_S  3
+/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN13_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN13_PAD_DRIVER_V  0x1
+#define GPIO_PIN13_PAD_DRIVER_S  2
+/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN13_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN13_SYNC2_BYPASS_M  ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S))
+#define GPIO_PIN13_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN13_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN14_REG          (DR_REG_GPIO_BASE + 0xAC)
+/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN14_INT_ENA  0x0000001F
+#define GPIO_PIN14_INT_ENA_M  ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S))
+#define GPIO_PIN14_INT_ENA_V  0x1F
+#define GPIO_PIN14_INT_ENA_S  13
+/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_CONFIG  0x00000003
+#define GPIO_PIN14_CONFIG_M  ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S))
+#define GPIO_PIN14_CONFIG_V  0x3
+#define GPIO_PIN14_CONFIG_S  11
+/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN14_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN14_WAKEUP_ENABLE_S  10
+/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN14_INT_TYPE  0x00000007
+#define GPIO_PIN14_INT_TYPE_M  ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S))
+#define GPIO_PIN14_INT_TYPE_V  0x7
+#define GPIO_PIN14_INT_TYPE_S  7
+/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN14_SYNC1_BYPASS_M  ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S))
+#define GPIO_PIN14_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC1_BYPASS_S  3
+/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN14_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN14_PAD_DRIVER_V  0x1
+#define GPIO_PIN14_PAD_DRIVER_S  2
+/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN14_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN14_SYNC2_BYPASS_M  ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S))
+#define GPIO_PIN14_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN14_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN15_REG          (DR_REG_GPIO_BASE + 0xB0)
+/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN15_INT_ENA  0x0000001F
+#define GPIO_PIN15_INT_ENA_M  ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S))
+#define GPIO_PIN15_INT_ENA_V  0x1F
+#define GPIO_PIN15_INT_ENA_S  13
+/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_CONFIG  0x00000003
+#define GPIO_PIN15_CONFIG_M  ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S))
+#define GPIO_PIN15_CONFIG_V  0x3
+#define GPIO_PIN15_CONFIG_S  11
+/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN15_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN15_WAKEUP_ENABLE_S  10
+/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN15_INT_TYPE  0x00000007
+#define GPIO_PIN15_INT_TYPE_M  ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S))
+#define GPIO_PIN15_INT_TYPE_V  0x7
+#define GPIO_PIN15_INT_TYPE_S  7
+/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN15_SYNC1_BYPASS_M  ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S))
+#define GPIO_PIN15_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC1_BYPASS_S  3
+/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN15_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN15_PAD_DRIVER_V  0x1
+#define GPIO_PIN15_PAD_DRIVER_S  2
+/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN15_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN15_SYNC2_BYPASS_M  ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S))
+#define GPIO_PIN15_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN15_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN16_REG          (DR_REG_GPIO_BASE + 0xB4)
+/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN16_INT_ENA  0x0000001F
+#define GPIO_PIN16_INT_ENA_M  ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S))
+#define GPIO_PIN16_INT_ENA_V  0x1F
+#define GPIO_PIN16_INT_ENA_S  13
+/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_CONFIG  0x00000003
+#define GPIO_PIN16_CONFIG_M  ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S))
+#define GPIO_PIN16_CONFIG_V  0x3
+#define GPIO_PIN16_CONFIG_S  11
+/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN16_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN16_WAKEUP_ENABLE_S  10
+/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN16_INT_TYPE  0x00000007
+#define GPIO_PIN16_INT_TYPE_M  ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S))
+#define GPIO_PIN16_INT_TYPE_V  0x7
+#define GPIO_PIN16_INT_TYPE_S  7
+/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN16_SYNC1_BYPASS_M  ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S))
+#define GPIO_PIN16_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC1_BYPASS_S  3
+/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN16_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN16_PAD_DRIVER_V  0x1
+#define GPIO_PIN16_PAD_DRIVER_S  2
+/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN16_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN16_SYNC2_BYPASS_M  ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S))
+#define GPIO_PIN16_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN16_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN17_REG          (DR_REG_GPIO_BASE + 0xB8)
+/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN17_INT_ENA  0x0000001F
+#define GPIO_PIN17_INT_ENA_M  ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S))
+#define GPIO_PIN17_INT_ENA_V  0x1F
+#define GPIO_PIN17_INT_ENA_S  13
+/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_CONFIG  0x00000003
+#define GPIO_PIN17_CONFIG_M  ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S))
+#define GPIO_PIN17_CONFIG_V  0x3
+#define GPIO_PIN17_CONFIG_S  11
+/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN17_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN17_WAKEUP_ENABLE_S  10
+/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN17_INT_TYPE  0x00000007
+#define GPIO_PIN17_INT_TYPE_M  ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S))
+#define GPIO_PIN17_INT_TYPE_V  0x7
+#define GPIO_PIN17_INT_TYPE_S  7
+/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN17_SYNC1_BYPASS_M  ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S))
+#define GPIO_PIN17_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC1_BYPASS_S  3
+/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN17_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN17_PAD_DRIVER_V  0x1
+#define GPIO_PIN17_PAD_DRIVER_S  2
+/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN17_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN17_SYNC2_BYPASS_M  ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S))
+#define GPIO_PIN17_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN17_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN18_REG          (DR_REG_GPIO_BASE + 0xBC)
+/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN18_INT_ENA  0x0000001F
+#define GPIO_PIN18_INT_ENA_M  ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S))
+#define GPIO_PIN18_INT_ENA_V  0x1F
+#define GPIO_PIN18_INT_ENA_S  13
+/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_CONFIG  0x00000003
+#define GPIO_PIN18_CONFIG_M  ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S))
+#define GPIO_PIN18_CONFIG_V  0x3
+#define GPIO_PIN18_CONFIG_S  11
+/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN18_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN18_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN18_WAKEUP_ENABLE_S  10
+/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN18_INT_TYPE  0x00000007
+#define GPIO_PIN18_INT_TYPE_M  ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S))
+#define GPIO_PIN18_INT_TYPE_V  0x7
+#define GPIO_PIN18_INT_TYPE_S  7
+/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN18_SYNC1_BYPASS_M  ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S))
+#define GPIO_PIN18_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC1_BYPASS_S  3
+/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN18_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN18_PAD_DRIVER_V  0x1
+#define GPIO_PIN18_PAD_DRIVER_S  2
+/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN18_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN18_SYNC2_BYPASS_M  ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S))
+#define GPIO_PIN18_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN18_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN19_REG          (DR_REG_GPIO_BASE + 0xC0)
+/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN19_INT_ENA  0x0000001F
+#define GPIO_PIN19_INT_ENA_M  ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S))
+#define GPIO_PIN19_INT_ENA_V  0x1F
+#define GPIO_PIN19_INT_ENA_S  13
+/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_CONFIG  0x00000003
+#define GPIO_PIN19_CONFIG_M  ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S))
+#define GPIO_PIN19_CONFIG_V  0x3
+#define GPIO_PIN19_CONFIG_S  11
+/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN19_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN19_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN19_WAKEUP_ENABLE_S  10
+/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN19_INT_TYPE  0x00000007
+#define GPIO_PIN19_INT_TYPE_M  ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S))
+#define GPIO_PIN19_INT_TYPE_V  0x7
+#define GPIO_PIN19_INT_TYPE_S  7
+/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN19_SYNC1_BYPASS_M  ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S))
+#define GPIO_PIN19_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC1_BYPASS_S  3
+/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN19_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN19_PAD_DRIVER_V  0x1
+#define GPIO_PIN19_PAD_DRIVER_S  2
+/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN19_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN19_SYNC2_BYPASS_M  ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S))
+#define GPIO_PIN19_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN19_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN20_REG          (DR_REG_GPIO_BASE + 0xC4)
+/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN20_INT_ENA  0x0000001F
+#define GPIO_PIN20_INT_ENA_M  ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S))
+#define GPIO_PIN20_INT_ENA_V  0x1F
+#define GPIO_PIN20_INT_ENA_S  13
+/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_CONFIG  0x00000003
+#define GPIO_PIN20_CONFIG_M  ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S))
+#define GPIO_PIN20_CONFIG_V  0x3
+#define GPIO_PIN20_CONFIG_S  11
+/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN20_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN20_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN20_WAKEUP_ENABLE_S  10
+/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN20_INT_TYPE  0x00000007
+#define GPIO_PIN20_INT_TYPE_M  ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S))
+#define GPIO_PIN20_INT_TYPE_V  0x7
+#define GPIO_PIN20_INT_TYPE_S  7
+/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN20_SYNC1_BYPASS_M  ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S))
+#define GPIO_PIN20_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC1_BYPASS_S  3
+/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN20_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN20_PAD_DRIVER_V  0x1
+#define GPIO_PIN20_PAD_DRIVER_S  2
+/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN20_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN20_SYNC2_BYPASS_M  ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S))
+#define GPIO_PIN20_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN20_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN21_REG          (DR_REG_GPIO_BASE + 0xC8)
+/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN21_INT_ENA  0x0000001F
+#define GPIO_PIN21_INT_ENA_M  ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S))
+#define GPIO_PIN21_INT_ENA_V  0x1F
+#define GPIO_PIN21_INT_ENA_S  13
+/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_CONFIG  0x00000003
+#define GPIO_PIN21_CONFIG_M  ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S))
+#define GPIO_PIN21_CONFIG_V  0x3
+#define GPIO_PIN21_CONFIG_S  11
+/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN21_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN21_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN21_WAKEUP_ENABLE_S  10
+/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN21_INT_TYPE  0x00000007
+#define GPIO_PIN21_INT_TYPE_M  ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S))
+#define GPIO_PIN21_INT_TYPE_V  0x7
+#define GPIO_PIN21_INT_TYPE_S  7
+/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN21_SYNC1_BYPASS_M  ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S))
+#define GPIO_PIN21_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC1_BYPASS_S  3
+/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN21_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN21_PAD_DRIVER_V  0x1
+#define GPIO_PIN21_PAD_DRIVER_S  2
+/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN21_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN21_SYNC2_BYPASS_M  ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S))
+#define GPIO_PIN21_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN21_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN22_REG          (DR_REG_GPIO_BASE + 0xCC)
+/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN22_INT_ENA  0x0000001F
+#define GPIO_PIN22_INT_ENA_M  ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S))
+#define GPIO_PIN22_INT_ENA_V  0x1F
+#define GPIO_PIN22_INT_ENA_S  13
+/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_CONFIG  0x00000003
+#define GPIO_PIN22_CONFIG_M  ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S))
+#define GPIO_PIN22_CONFIG_V  0x3
+#define GPIO_PIN22_CONFIG_S  11
+/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN22_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN22_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN22_WAKEUP_ENABLE_S  10
+/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN22_INT_TYPE  0x00000007
+#define GPIO_PIN22_INT_TYPE_M  ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S))
+#define GPIO_PIN22_INT_TYPE_V  0x7
+#define GPIO_PIN22_INT_TYPE_S  7
+/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN22_SYNC1_BYPASS_M  ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S))
+#define GPIO_PIN22_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC1_BYPASS_S  3
+/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN22_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN22_PAD_DRIVER_V  0x1
+#define GPIO_PIN22_PAD_DRIVER_S  2
+/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN22_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN22_SYNC2_BYPASS_M  ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S))
+#define GPIO_PIN22_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN22_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN23_REG          (DR_REG_GPIO_BASE + 0xD0)
+/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN23_INT_ENA  0x0000001F
+#define GPIO_PIN23_INT_ENA_M  ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S))
+#define GPIO_PIN23_INT_ENA_V  0x1F
+#define GPIO_PIN23_INT_ENA_S  13
+/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_CONFIG  0x00000003
+#define GPIO_PIN23_CONFIG_M  ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S))
+#define GPIO_PIN23_CONFIG_V  0x3
+#define GPIO_PIN23_CONFIG_S  11
+/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN23_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN23_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN23_WAKEUP_ENABLE_S  10
+/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN23_INT_TYPE  0x00000007
+#define GPIO_PIN23_INT_TYPE_M  ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S))
+#define GPIO_PIN23_INT_TYPE_V  0x7
+#define GPIO_PIN23_INT_TYPE_S  7
+/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN23_SYNC1_BYPASS_M  ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S))
+#define GPIO_PIN23_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC1_BYPASS_S  3
+/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN23_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN23_PAD_DRIVER_V  0x1
+#define GPIO_PIN23_PAD_DRIVER_S  2
+/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN23_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN23_SYNC2_BYPASS_M  ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S))
+#define GPIO_PIN23_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN23_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN24_REG          (DR_REG_GPIO_BASE + 0xD4)
+/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN24_INT_ENA  0x0000001F
+#define GPIO_PIN24_INT_ENA_M  ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S))
+#define GPIO_PIN24_INT_ENA_V  0x1F
+#define GPIO_PIN24_INT_ENA_S  13
+/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_CONFIG  0x00000003
+#define GPIO_PIN24_CONFIG_M  ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S))
+#define GPIO_PIN24_CONFIG_V  0x3
+#define GPIO_PIN24_CONFIG_S  11
+/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN24_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN24_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN24_WAKEUP_ENABLE_S  10
+/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN24_INT_TYPE  0x00000007
+#define GPIO_PIN24_INT_TYPE_M  ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S))
+#define GPIO_PIN24_INT_TYPE_V  0x7
+#define GPIO_PIN24_INT_TYPE_S  7
+/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN24_SYNC1_BYPASS_M  ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S))
+#define GPIO_PIN24_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC1_BYPASS_S  3
+/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN24_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN24_PAD_DRIVER_V  0x1
+#define GPIO_PIN24_PAD_DRIVER_S  2
+/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN24_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN24_SYNC2_BYPASS_M  ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S))
+#define GPIO_PIN24_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN24_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN25_REG          (DR_REG_GPIO_BASE + 0xD8)
+/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN25_INT_ENA  0x0000001F
+#define GPIO_PIN25_INT_ENA_M  ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S))
+#define GPIO_PIN25_INT_ENA_V  0x1F
+#define GPIO_PIN25_INT_ENA_S  13
+/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_CONFIG  0x00000003
+#define GPIO_PIN25_CONFIG_M  ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S))
+#define GPIO_PIN25_CONFIG_V  0x3
+#define GPIO_PIN25_CONFIG_S  11
+/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN25_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN25_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN25_WAKEUP_ENABLE_S  10
+/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN25_INT_TYPE  0x00000007
+#define GPIO_PIN25_INT_TYPE_M  ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S))
+#define GPIO_PIN25_INT_TYPE_V  0x7
+#define GPIO_PIN25_INT_TYPE_S  7
+/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN25_SYNC1_BYPASS_M  ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S))
+#define GPIO_PIN25_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC1_BYPASS_S  3
+/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN25_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN25_PAD_DRIVER_V  0x1
+#define GPIO_PIN25_PAD_DRIVER_S  2
+/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN25_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN25_SYNC2_BYPASS_M  ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S))
+#define GPIO_PIN25_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN25_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN26_REG          (DR_REG_GPIO_BASE + 0xDC)
+/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN26_INT_ENA  0x0000001F
+#define GPIO_PIN26_INT_ENA_M  ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S))
+#define GPIO_PIN26_INT_ENA_V  0x1F
+#define GPIO_PIN26_INT_ENA_S  13
+/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN26_CONFIG  0x00000003
+#define GPIO_PIN26_CONFIG_M  ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S))
+#define GPIO_PIN26_CONFIG_V  0x3
+#define GPIO_PIN26_CONFIG_S  11
+/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN26_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN26_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN26_WAKEUP_ENABLE_S  10
+/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN26_INT_TYPE  0x00000007
+#define GPIO_PIN26_INT_TYPE_M  ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S))
+#define GPIO_PIN26_INT_TYPE_V  0x7
+#define GPIO_PIN26_INT_TYPE_S  7
+/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN26_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN26_SYNC1_BYPASS_M  ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S))
+#define GPIO_PIN26_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN26_SYNC1_BYPASS_S  3
+/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN26_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN26_PAD_DRIVER_V  0x1
+#define GPIO_PIN26_PAD_DRIVER_S  2
+/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN26_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN26_SYNC2_BYPASS_M  ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S))
+#define GPIO_PIN26_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN26_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN27_REG          (DR_REG_GPIO_BASE + 0xE0)
+/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN27_INT_ENA  0x0000001F
+#define GPIO_PIN27_INT_ENA_M  ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S))
+#define GPIO_PIN27_INT_ENA_V  0x1F
+#define GPIO_PIN27_INT_ENA_S  13
+/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN27_CONFIG  0x00000003
+#define GPIO_PIN27_CONFIG_M  ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S))
+#define GPIO_PIN27_CONFIG_V  0x3
+#define GPIO_PIN27_CONFIG_S  11
+/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN27_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN27_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN27_WAKEUP_ENABLE_S  10
+/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN27_INT_TYPE  0x00000007
+#define GPIO_PIN27_INT_TYPE_M  ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S))
+#define GPIO_PIN27_INT_TYPE_V  0x7
+#define GPIO_PIN27_INT_TYPE_S  7
+/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN27_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN27_SYNC1_BYPASS_M  ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S))
+#define GPIO_PIN27_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN27_SYNC1_BYPASS_S  3
+/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN27_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN27_PAD_DRIVER_V  0x1
+#define GPIO_PIN27_PAD_DRIVER_S  2
+/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN27_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN27_SYNC2_BYPASS_M  ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S))
+#define GPIO_PIN27_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN27_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN28_REG          (DR_REG_GPIO_BASE + 0xE4)
+/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN28_INT_ENA  0x0000001F
+#define GPIO_PIN28_INT_ENA_M  ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S))
+#define GPIO_PIN28_INT_ENA_V  0x1F
+#define GPIO_PIN28_INT_ENA_S  13
+/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN28_CONFIG  0x00000003
+#define GPIO_PIN28_CONFIG_M  ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S))
+#define GPIO_PIN28_CONFIG_V  0x3
+#define GPIO_PIN28_CONFIG_S  11
+/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN28_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN28_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN28_WAKEUP_ENABLE_S  10
+/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN28_INT_TYPE  0x00000007
+#define GPIO_PIN28_INT_TYPE_M  ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S))
+#define GPIO_PIN28_INT_TYPE_V  0x7
+#define GPIO_PIN28_INT_TYPE_S  7
+/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN28_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN28_SYNC1_BYPASS_M  ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S))
+#define GPIO_PIN28_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN28_SYNC1_BYPASS_S  3
+/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN28_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN28_PAD_DRIVER_V  0x1
+#define GPIO_PIN28_PAD_DRIVER_S  2
+/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN28_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN28_SYNC2_BYPASS_M  ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S))
+#define GPIO_PIN28_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN28_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN29_REG          (DR_REG_GPIO_BASE + 0xE8)
+/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN29_INT_ENA  0x0000001F
+#define GPIO_PIN29_INT_ENA_M  ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S))
+#define GPIO_PIN29_INT_ENA_V  0x1F
+#define GPIO_PIN29_INT_ENA_S  13
+/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN29_CONFIG  0x00000003
+#define GPIO_PIN29_CONFIG_M  ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S))
+#define GPIO_PIN29_CONFIG_V  0x3
+#define GPIO_PIN29_CONFIG_S  11
+/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN29_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN29_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN29_WAKEUP_ENABLE_S  10
+/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN29_INT_TYPE  0x00000007
+#define GPIO_PIN29_INT_TYPE_M  ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S))
+#define GPIO_PIN29_INT_TYPE_V  0x7
+#define GPIO_PIN29_INT_TYPE_S  7
+/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN29_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN29_SYNC1_BYPASS_M  ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S))
+#define GPIO_PIN29_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN29_SYNC1_BYPASS_S  3
+/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN29_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN29_PAD_DRIVER_V  0x1
+#define GPIO_PIN29_PAD_DRIVER_S  2
+/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN29_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN29_SYNC2_BYPASS_M  ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S))
+#define GPIO_PIN29_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN29_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN30_REG          (DR_REG_GPIO_BASE + 0xEC)
+/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN30_INT_ENA  0x0000001F
+#define GPIO_PIN30_INT_ENA_M  ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S))
+#define GPIO_PIN30_INT_ENA_V  0x1F
+#define GPIO_PIN30_INT_ENA_S  13
+/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN30_CONFIG  0x00000003
+#define GPIO_PIN30_CONFIG_M  ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S))
+#define GPIO_PIN30_CONFIG_V  0x3
+#define GPIO_PIN30_CONFIG_S  11
+/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN30_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN30_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN30_WAKEUP_ENABLE_S  10
+/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN30_INT_TYPE  0x00000007
+#define GPIO_PIN30_INT_TYPE_M  ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S))
+#define GPIO_PIN30_INT_TYPE_V  0x7
+#define GPIO_PIN30_INT_TYPE_S  7
+/* GPIO_PIN30_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN30_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN30_SYNC1_BYPASS_M  ((GPIO_PIN30_SYNC1_BYPASS_V)<<(GPIO_PIN30_SYNC1_BYPASS_S))
+#define GPIO_PIN30_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN30_SYNC1_BYPASS_S  3
+/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN30_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN30_PAD_DRIVER_V  0x1
+#define GPIO_PIN30_PAD_DRIVER_S  2
+/* GPIO_PIN30_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN30_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN30_SYNC2_BYPASS_M  ((GPIO_PIN30_SYNC2_BYPASS_V)<<(GPIO_PIN30_SYNC2_BYPASS_S))
+#define GPIO_PIN30_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN30_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN31_REG          (DR_REG_GPIO_BASE + 0xF0)
+/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN31_INT_ENA  0x0000001F
+#define GPIO_PIN31_INT_ENA_M  ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S))
+#define GPIO_PIN31_INT_ENA_V  0x1F
+#define GPIO_PIN31_INT_ENA_S  13
+/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN31_CONFIG  0x00000003
+#define GPIO_PIN31_CONFIG_M  ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S))
+#define GPIO_PIN31_CONFIG_V  0x3
+#define GPIO_PIN31_CONFIG_S  11
+/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN31_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN31_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN31_WAKEUP_ENABLE_S  10
+/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN31_INT_TYPE  0x00000007
+#define GPIO_PIN31_INT_TYPE_M  ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S))
+#define GPIO_PIN31_INT_TYPE_V  0x7
+#define GPIO_PIN31_INT_TYPE_S  7
+/* GPIO_PIN31_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN31_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN31_SYNC1_BYPASS_M  ((GPIO_PIN31_SYNC1_BYPASS_V)<<(GPIO_PIN31_SYNC1_BYPASS_S))
+#define GPIO_PIN31_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN31_SYNC1_BYPASS_S  3
+/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN31_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN31_PAD_DRIVER_V  0x1
+#define GPIO_PIN31_PAD_DRIVER_S  2
+/* GPIO_PIN31_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN31_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN31_SYNC2_BYPASS_M  ((GPIO_PIN31_SYNC2_BYPASS_V)<<(GPIO_PIN31_SYNC2_BYPASS_S))
+#define GPIO_PIN31_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN31_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN32_REG          (DR_REG_GPIO_BASE + 0xF4)
+/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN32_INT_ENA  0x0000001F
+#define GPIO_PIN32_INT_ENA_M  ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S))
+#define GPIO_PIN32_INT_ENA_V  0x1F
+#define GPIO_PIN32_INT_ENA_S  13
+/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN32_CONFIG  0x00000003
+#define GPIO_PIN32_CONFIG_M  ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S))
+#define GPIO_PIN32_CONFIG_V  0x3
+#define GPIO_PIN32_CONFIG_S  11
+/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN32_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN32_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN32_WAKEUP_ENABLE_S  10
+/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN32_INT_TYPE  0x00000007
+#define GPIO_PIN32_INT_TYPE_M  ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S))
+#define GPIO_PIN32_INT_TYPE_V  0x7
+#define GPIO_PIN32_INT_TYPE_S  7
+/* GPIO_PIN32_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN32_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN32_SYNC1_BYPASS_M  ((GPIO_PIN32_SYNC1_BYPASS_V)<<(GPIO_PIN32_SYNC1_BYPASS_S))
+#define GPIO_PIN32_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN32_SYNC1_BYPASS_S  3
+/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN32_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN32_PAD_DRIVER_V  0x1
+#define GPIO_PIN32_PAD_DRIVER_S  2
+/* GPIO_PIN32_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN32_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN32_SYNC2_BYPASS_M  ((GPIO_PIN32_SYNC2_BYPASS_V)<<(GPIO_PIN32_SYNC2_BYPASS_S))
+#define GPIO_PIN32_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN32_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN33_REG          (DR_REG_GPIO_BASE + 0xF8)
+/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN33_INT_ENA  0x0000001F
+#define GPIO_PIN33_INT_ENA_M  ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S))
+#define GPIO_PIN33_INT_ENA_V  0x1F
+#define GPIO_PIN33_INT_ENA_S  13
+/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN33_CONFIG  0x00000003
+#define GPIO_PIN33_CONFIG_M  ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S))
+#define GPIO_PIN33_CONFIG_V  0x3
+#define GPIO_PIN33_CONFIG_S  11
+/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN33_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN33_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN33_WAKEUP_ENABLE_S  10
+/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN33_INT_TYPE  0x00000007
+#define GPIO_PIN33_INT_TYPE_M  ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S))
+#define GPIO_PIN33_INT_TYPE_V  0x7
+#define GPIO_PIN33_INT_TYPE_S  7
+/* GPIO_PIN33_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN33_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN33_SYNC1_BYPASS_M  ((GPIO_PIN33_SYNC1_BYPASS_V)<<(GPIO_PIN33_SYNC1_BYPASS_S))
+#define GPIO_PIN33_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN33_SYNC1_BYPASS_S  3
+/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN33_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN33_PAD_DRIVER_V  0x1
+#define GPIO_PIN33_PAD_DRIVER_S  2
+/* GPIO_PIN33_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN33_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN33_SYNC2_BYPASS_M  ((GPIO_PIN33_SYNC2_BYPASS_V)<<(GPIO_PIN33_SYNC2_BYPASS_S))
+#define GPIO_PIN33_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN33_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN34_REG          (DR_REG_GPIO_BASE + 0xFC)
+/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN34_INT_ENA  0x0000001F
+#define GPIO_PIN34_INT_ENA_M  ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S))
+#define GPIO_PIN34_INT_ENA_V  0x1F
+#define GPIO_PIN34_INT_ENA_S  13
+/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN34_CONFIG  0x00000003
+#define GPIO_PIN34_CONFIG_M  ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S))
+#define GPIO_PIN34_CONFIG_V  0x3
+#define GPIO_PIN34_CONFIG_S  11
+/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN34_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN34_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN34_WAKEUP_ENABLE_S  10
+/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN34_INT_TYPE  0x00000007
+#define GPIO_PIN34_INT_TYPE_M  ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S))
+#define GPIO_PIN34_INT_TYPE_V  0x7
+#define GPIO_PIN34_INT_TYPE_S  7
+/* GPIO_PIN34_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN34_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN34_SYNC1_BYPASS_M  ((GPIO_PIN34_SYNC1_BYPASS_V)<<(GPIO_PIN34_SYNC1_BYPASS_S))
+#define GPIO_PIN34_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN34_SYNC1_BYPASS_S  3
+/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN34_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN34_PAD_DRIVER_V  0x1
+#define GPIO_PIN34_PAD_DRIVER_S  2
+/* GPIO_PIN34_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN34_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN34_SYNC2_BYPASS_M  ((GPIO_PIN34_SYNC2_BYPASS_V)<<(GPIO_PIN34_SYNC2_BYPASS_S))
+#define GPIO_PIN34_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN34_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN35_REG          (DR_REG_GPIO_BASE + 0x100)
+/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN35_INT_ENA  0x0000001F
+#define GPIO_PIN35_INT_ENA_M  ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S))
+#define GPIO_PIN35_INT_ENA_V  0x1F
+#define GPIO_PIN35_INT_ENA_S  13
+/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN35_CONFIG  0x00000003
+#define GPIO_PIN35_CONFIG_M  ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S))
+#define GPIO_PIN35_CONFIG_V  0x3
+#define GPIO_PIN35_CONFIG_S  11
+/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN35_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN35_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN35_WAKEUP_ENABLE_S  10
+/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN35_INT_TYPE  0x00000007
+#define GPIO_PIN35_INT_TYPE_M  ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S))
+#define GPIO_PIN35_INT_TYPE_V  0x7
+#define GPIO_PIN35_INT_TYPE_S  7
+/* GPIO_PIN35_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN35_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN35_SYNC1_BYPASS_M  ((GPIO_PIN35_SYNC1_BYPASS_V)<<(GPIO_PIN35_SYNC1_BYPASS_S))
+#define GPIO_PIN35_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN35_SYNC1_BYPASS_S  3
+/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN35_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN35_PAD_DRIVER_V  0x1
+#define GPIO_PIN35_PAD_DRIVER_S  2
+/* GPIO_PIN35_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN35_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN35_SYNC2_BYPASS_M  ((GPIO_PIN35_SYNC2_BYPASS_V)<<(GPIO_PIN35_SYNC2_BYPASS_S))
+#define GPIO_PIN35_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN35_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN36_REG          (DR_REG_GPIO_BASE + 0x104)
+/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN36_INT_ENA  0x0000001F
+#define GPIO_PIN36_INT_ENA_M  ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S))
+#define GPIO_PIN36_INT_ENA_V  0x1F
+#define GPIO_PIN36_INT_ENA_S  13
+/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN36_CONFIG  0x00000003
+#define GPIO_PIN36_CONFIG_M  ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S))
+#define GPIO_PIN36_CONFIG_V  0x3
+#define GPIO_PIN36_CONFIG_S  11
+/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN36_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN36_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN36_WAKEUP_ENABLE_S  10
+/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN36_INT_TYPE  0x00000007
+#define GPIO_PIN36_INT_TYPE_M  ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S))
+#define GPIO_PIN36_INT_TYPE_V  0x7
+#define GPIO_PIN36_INT_TYPE_S  7
+/* GPIO_PIN36_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN36_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN36_SYNC1_BYPASS_M  ((GPIO_PIN36_SYNC1_BYPASS_V)<<(GPIO_PIN36_SYNC1_BYPASS_S))
+#define GPIO_PIN36_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN36_SYNC1_BYPASS_S  3
+/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN36_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN36_PAD_DRIVER_V  0x1
+#define GPIO_PIN36_PAD_DRIVER_S  2
+/* GPIO_PIN36_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN36_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN36_SYNC2_BYPASS_M  ((GPIO_PIN36_SYNC2_BYPASS_V)<<(GPIO_PIN36_SYNC2_BYPASS_S))
+#define GPIO_PIN36_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN36_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN37_REG          (DR_REG_GPIO_BASE + 0x108)
+/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN37_INT_ENA  0x0000001F
+#define GPIO_PIN37_INT_ENA_M  ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S))
+#define GPIO_PIN37_INT_ENA_V  0x1F
+#define GPIO_PIN37_INT_ENA_S  13
+/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN37_CONFIG  0x00000003
+#define GPIO_PIN37_CONFIG_M  ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S))
+#define GPIO_PIN37_CONFIG_V  0x3
+#define GPIO_PIN37_CONFIG_S  11
+/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN37_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN37_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN37_WAKEUP_ENABLE_S  10
+/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN37_INT_TYPE  0x00000007
+#define GPIO_PIN37_INT_TYPE_M  ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S))
+#define GPIO_PIN37_INT_TYPE_V  0x7
+#define GPIO_PIN37_INT_TYPE_S  7
+/* GPIO_PIN37_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN37_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN37_SYNC1_BYPASS_M  ((GPIO_PIN37_SYNC1_BYPASS_V)<<(GPIO_PIN37_SYNC1_BYPASS_S))
+#define GPIO_PIN37_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN37_SYNC1_BYPASS_S  3
+/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN37_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN37_PAD_DRIVER_V  0x1
+#define GPIO_PIN37_PAD_DRIVER_S  2
+/* GPIO_PIN37_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN37_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN37_SYNC2_BYPASS_M  ((GPIO_PIN37_SYNC2_BYPASS_V)<<(GPIO_PIN37_SYNC2_BYPASS_S))
+#define GPIO_PIN37_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN37_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN38_REG          (DR_REG_GPIO_BASE + 0x10C)
+/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN38_INT_ENA  0x0000001F
+#define GPIO_PIN38_INT_ENA_M  ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S))
+#define GPIO_PIN38_INT_ENA_V  0x1F
+#define GPIO_PIN38_INT_ENA_S  13
+/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN38_CONFIG  0x00000003
+#define GPIO_PIN38_CONFIG_M  ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S))
+#define GPIO_PIN38_CONFIG_V  0x3
+#define GPIO_PIN38_CONFIG_S  11
+/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN38_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN38_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN38_WAKEUP_ENABLE_S  10
+/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN38_INT_TYPE  0x00000007
+#define GPIO_PIN38_INT_TYPE_M  ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S))
+#define GPIO_PIN38_INT_TYPE_V  0x7
+#define GPIO_PIN38_INT_TYPE_S  7
+/* GPIO_PIN38_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN38_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN38_SYNC1_BYPASS_M  ((GPIO_PIN38_SYNC1_BYPASS_V)<<(GPIO_PIN38_SYNC1_BYPASS_S))
+#define GPIO_PIN38_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN38_SYNC1_BYPASS_S  3
+/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN38_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN38_PAD_DRIVER_V  0x1
+#define GPIO_PIN38_PAD_DRIVER_S  2
+/* GPIO_PIN38_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN38_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN38_SYNC2_BYPASS_M  ((GPIO_PIN38_SYNC2_BYPASS_V)<<(GPIO_PIN38_SYNC2_BYPASS_S))
+#define GPIO_PIN38_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN38_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN39_REG          (DR_REG_GPIO_BASE + 0x110)
+/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN39_INT_ENA  0x0000001F
+#define GPIO_PIN39_INT_ENA_M  ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S))
+#define GPIO_PIN39_INT_ENA_V  0x1F
+#define GPIO_PIN39_INT_ENA_S  13
+/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN39_CONFIG  0x00000003
+#define GPIO_PIN39_CONFIG_M  ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S))
+#define GPIO_PIN39_CONFIG_V  0x3
+#define GPIO_PIN39_CONFIG_S  11
+/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN39_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN39_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN39_WAKEUP_ENABLE_S  10
+/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN39_INT_TYPE  0x00000007
+#define GPIO_PIN39_INT_TYPE_M  ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S))
+#define GPIO_PIN39_INT_TYPE_V  0x7
+#define GPIO_PIN39_INT_TYPE_S  7
+/* GPIO_PIN39_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN39_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN39_SYNC1_BYPASS_M  ((GPIO_PIN39_SYNC1_BYPASS_V)<<(GPIO_PIN39_SYNC1_BYPASS_S))
+#define GPIO_PIN39_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN39_SYNC1_BYPASS_S  3
+/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN39_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN39_PAD_DRIVER_V  0x1
+#define GPIO_PIN39_PAD_DRIVER_S  2
+/* GPIO_PIN39_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN39_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN39_SYNC2_BYPASS_M  ((GPIO_PIN39_SYNC2_BYPASS_V)<<(GPIO_PIN39_SYNC2_BYPASS_S))
+#define GPIO_PIN39_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN39_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN40_REG          (DR_REG_GPIO_BASE + 0x114)
+/* GPIO_PIN40_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN40_INT_ENA  0x0000001F
+#define GPIO_PIN40_INT_ENA_M  ((GPIO_PIN40_INT_ENA_V)<<(GPIO_PIN40_INT_ENA_S))
+#define GPIO_PIN40_INT_ENA_V  0x1F
+#define GPIO_PIN40_INT_ENA_S  13
+/* GPIO_PIN40_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN40_CONFIG  0x00000003
+#define GPIO_PIN40_CONFIG_M  ((GPIO_PIN40_CONFIG_V)<<(GPIO_PIN40_CONFIG_S))
+#define GPIO_PIN40_CONFIG_V  0x3
+#define GPIO_PIN40_CONFIG_S  11
+/* GPIO_PIN40_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN40_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN40_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN40_WAKEUP_ENABLE_S  10
+/* GPIO_PIN40_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN40_INT_TYPE  0x00000007
+#define GPIO_PIN40_INT_TYPE_M  ((GPIO_PIN40_INT_TYPE_V)<<(GPIO_PIN40_INT_TYPE_S))
+#define GPIO_PIN40_INT_TYPE_V  0x7
+#define GPIO_PIN40_INT_TYPE_S  7
+/* GPIO_PIN40_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN40_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN40_SYNC1_BYPASS_M  ((GPIO_PIN40_SYNC1_BYPASS_V)<<(GPIO_PIN40_SYNC1_BYPASS_S))
+#define GPIO_PIN40_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN40_SYNC1_BYPASS_S  3
+/* GPIO_PIN40_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN40_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN40_PAD_DRIVER_V  0x1
+#define GPIO_PIN40_PAD_DRIVER_S  2
+/* GPIO_PIN40_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN40_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN40_SYNC2_BYPASS_M  ((GPIO_PIN40_SYNC2_BYPASS_V)<<(GPIO_PIN40_SYNC2_BYPASS_S))
+#define GPIO_PIN40_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN40_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN41_REG          (DR_REG_GPIO_BASE + 0x118)
+/* GPIO_PIN41_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN41_INT_ENA  0x0000001F
+#define GPIO_PIN41_INT_ENA_M  ((GPIO_PIN41_INT_ENA_V)<<(GPIO_PIN41_INT_ENA_S))
+#define GPIO_PIN41_INT_ENA_V  0x1F
+#define GPIO_PIN41_INT_ENA_S  13
+/* GPIO_PIN41_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN41_CONFIG  0x00000003
+#define GPIO_PIN41_CONFIG_M  ((GPIO_PIN41_CONFIG_V)<<(GPIO_PIN41_CONFIG_S))
+#define GPIO_PIN41_CONFIG_V  0x3
+#define GPIO_PIN41_CONFIG_S  11
+/* GPIO_PIN41_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN41_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN41_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN41_WAKEUP_ENABLE_S  10
+/* GPIO_PIN41_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN41_INT_TYPE  0x00000007
+#define GPIO_PIN41_INT_TYPE_M  ((GPIO_PIN41_INT_TYPE_V)<<(GPIO_PIN41_INT_TYPE_S))
+#define GPIO_PIN41_INT_TYPE_V  0x7
+#define GPIO_PIN41_INT_TYPE_S  7
+/* GPIO_PIN41_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN41_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN41_SYNC1_BYPASS_M  ((GPIO_PIN41_SYNC1_BYPASS_V)<<(GPIO_PIN41_SYNC1_BYPASS_S))
+#define GPIO_PIN41_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN41_SYNC1_BYPASS_S  3
+/* GPIO_PIN41_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN41_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN41_PAD_DRIVER_V  0x1
+#define GPIO_PIN41_PAD_DRIVER_S  2
+/* GPIO_PIN41_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN41_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN41_SYNC2_BYPASS_M  ((GPIO_PIN41_SYNC2_BYPASS_V)<<(GPIO_PIN41_SYNC2_BYPASS_S))
+#define GPIO_PIN41_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN41_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN42_REG          (DR_REG_GPIO_BASE + 0x11C)
+/* GPIO_PIN42_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN42_INT_ENA  0x0000001F
+#define GPIO_PIN42_INT_ENA_M  ((GPIO_PIN42_INT_ENA_V)<<(GPIO_PIN42_INT_ENA_S))
+#define GPIO_PIN42_INT_ENA_V  0x1F
+#define GPIO_PIN42_INT_ENA_S  13
+/* GPIO_PIN42_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN42_CONFIG  0x00000003
+#define GPIO_PIN42_CONFIG_M  ((GPIO_PIN42_CONFIG_V)<<(GPIO_PIN42_CONFIG_S))
+#define GPIO_PIN42_CONFIG_V  0x3
+#define GPIO_PIN42_CONFIG_S  11
+/* GPIO_PIN42_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN42_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN42_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN42_WAKEUP_ENABLE_S  10
+/* GPIO_PIN42_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN42_INT_TYPE  0x00000007
+#define GPIO_PIN42_INT_TYPE_M  ((GPIO_PIN42_INT_TYPE_V)<<(GPIO_PIN42_INT_TYPE_S))
+#define GPIO_PIN42_INT_TYPE_V  0x7
+#define GPIO_PIN42_INT_TYPE_S  7
+/* GPIO_PIN42_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN42_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN42_SYNC1_BYPASS_M  ((GPIO_PIN42_SYNC1_BYPASS_V)<<(GPIO_PIN42_SYNC1_BYPASS_S))
+#define GPIO_PIN42_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN42_SYNC1_BYPASS_S  3
+/* GPIO_PIN42_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN42_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN42_PAD_DRIVER_V  0x1
+#define GPIO_PIN42_PAD_DRIVER_S  2
+/* GPIO_PIN42_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN42_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN42_SYNC2_BYPASS_M  ((GPIO_PIN42_SYNC2_BYPASS_V)<<(GPIO_PIN42_SYNC2_BYPASS_S))
+#define GPIO_PIN42_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN42_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN43_REG          (DR_REG_GPIO_BASE + 0x120)
+/* GPIO_PIN43_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN43_INT_ENA  0x0000001F
+#define GPIO_PIN43_INT_ENA_M  ((GPIO_PIN43_INT_ENA_V)<<(GPIO_PIN43_INT_ENA_S))
+#define GPIO_PIN43_INT_ENA_V  0x1F
+#define GPIO_PIN43_INT_ENA_S  13
+/* GPIO_PIN43_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN43_CONFIG  0x00000003
+#define GPIO_PIN43_CONFIG_M  ((GPIO_PIN43_CONFIG_V)<<(GPIO_PIN43_CONFIG_S))
+#define GPIO_PIN43_CONFIG_V  0x3
+#define GPIO_PIN43_CONFIG_S  11
+/* GPIO_PIN43_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN43_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN43_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN43_WAKEUP_ENABLE_S  10
+/* GPIO_PIN43_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN43_INT_TYPE  0x00000007
+#define GPIO_PIN43_INT_TYPE_M  ((GPIO_PIN43_INT_TYPE_V)<<(GPIO_PIN43_INT_TYPE_S))
+#define GPIO_PIN43_INT_TYPE_V  0x7
+#define GPIO_PIN43_INT_TYPE_S  7
+/* GPIO_PIN43_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN43_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN43_SYNC1_BYPASS_M  ((GPIO_PIN43_SYNC1_BYPASS_V)<<(GPIO_PIN43_SYNC1_BYPASS_S))
+#define GPIO_PIN43_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN43_SYNC1_BYPASS_S  3
+/* GPIO_PIN43_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN43_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN43_PAD_DRIVER_V  0x1
+#define GPIO_PIN43_PAD_DRIVER_S  2
+/* GPIO_PIN43_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN43_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN43_SYNC2_BYPASS_M  ((GPIO_PIN43_SYNC2_BYPASS_V)<<(GPIO_PIN43_SYNC2_BYPASS_S))
+#define GPIO_PIN43_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN43_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN44_REG          (DR_REG_GPIO_BASE + 0x124)
+/* GPIO_PIN44_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN44_INT_ENA  0x0000001F
+#define GPIO_PIN44_INT_ENA_M  ((GPIO_PIN44_INT_ENA_V)<<(GPIO_PIN44_INT_ENA_S))
+#define GPIO_PIN44_INT_ENA_V  0x1F
+#define GPIO_PIN44_INT_ENA_S  13
+/* GPIO_PIN44_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN44_CONFIG  0x00000003
+#define GPIO_PIN44_CONFIG_M  ((GPIO_PIN44_CONFIG_V)<<(GPIO_PIN44_CONFIG_S))
+#define GPIO_PIN44_CONFIG_V  0x3
+#define GPIO_PIN44_CONFIG_S  11
+/* GPIO_PIN44_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN44_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN44_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN44_WAKEUP_ENABLE_S  10
+/* GPIO_PIN44_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN44_INT_TYPE  0x00000007
+#define GPIO_PIN44_INT_TYPE_M  ((GPIO_PIN44_INT_TYPE_V)<<(GPIO_PIN44_INT_TYPE_S))
+#define GPIO_PIN44_INT_TYPE_V  0x7
+#define GPIO_PIN44_INT_TYPE_S  7
+/* GPIO_PIN44_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN44_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN44_SYNC1_BYPASS_M  ((GPIO_PIN44_SYNC1_BYPASS_V)<<(GPIO_PIN44_SYNC1_BYPASS_S))
+#define GPIO_PIN44_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN44_SYNC1_BYPASS_S  3
+/* GPIO_PIN44_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN44_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN44_PAD_DRIVER_V  0x1
+#define GPIO_PIN44_PAD_DRIVER_S  2
+/* GPIO_PIN44_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN44_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN44_SYNC2_BYPASS_M  ((GPIO_PIN44_SYNC2_BYPASS_V)<<(GPIO_PIN44_SYNC2_BYPASS_S))
+#define GPIO_PIN44_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN44_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN45_REG          (DR_REG_GPIO_BASE + 0x128)
+/* GPIO_PIN45_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN45_INT_ENA  0x0000001F
+#define GPIO_PIN45_INT_ENA_M  ((GPIO_PIN45_INT_ENA_V)<<(GPIO_PIN45_INT_ENA_S))
+#define GPIO_PIN45_INT_ENA_V  0x1F
+#define GPIO_PIN45_INT_ENA_S  13
+/* GPIO_PIN45_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN45_CONFIG  0x00000003
+#define GPIO_PIN45_CONFIG_M  ((GPIO_PIN45_CONFIG_V)<<(GPIO_PIN45_CONFIG_S))
+#define GPIO_PIN45_CONFIG_V  0x3
+#define GPIO_PIN45_CONFIG_S  11
+/* GPIO_PIN45_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN45_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN45_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN45_WAKEUP_ENABLE_S  10
+/* GPIO_PIN45_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN45_INT_TYPE  0x00000007
+#define GPIO_PIN45_INT_TYPE_M  ((GPIO_PIN45_INT_TYPE_V)<<(GPIO_PIN45_INT_TYPE_S))
+#define GPIO_PIN45_INT_TYPE_V  0x7
+#define GPIO_PIN45_INT_TYPE_S  7
+/* GPIO_PIN45_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN45_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN45_SYNC1_BYPASS_M  ((GPIO_PIN45_SYNC1_BYPASS_V)<<(GPIO_PIN45_SYNC1_BYPASS_S))
+#define GPIO_PIN45_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN45_SYNC1_BYPASS_S  3
+/* GPIO_PIN45_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN45_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN45_PAD_DRIVER_V  0x1
+#define GPIO_PIN45_PAD_DRIVER_S  2
+/* GPIO_PIN45_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN45_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN45_SYNC2_BYPASS_M  ((GPIO_PIN45_SYNC2_BYPASS_V)<<(GPIO_PIN45_SYNC2_BYPASS_S))
+#define GPIO_PIN45_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN45_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN46_REG          (DR_REG_GPIO_BASE + 0x12C)
+/* GPIO_PIN46_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN46_INT_ENA  0x0000001F
+#define GPIO_PIN46_INT_ENA_M  ((GPIO_PIN46_INT_ENA_V)<<(GPIO_PIN46_INT_ENA_S))
+#define GPIO_PIN46_INT_ENA_V  0x1F
+#define GPIO_PIN46_INT_ENA_S  13
+/* GPIO_PIN46_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN46_CONFIG  0x00000003
+#define GPIO_PIN46_CONFIG_M  ((GPIO_PIN46_CONFIG_V)<<(GPIO_PIN46_CONFIG_S))
+#define GPIO_PIN46_CONFIG_V  0x3
+#define GPIO_PIN46_CONFIG_S  11
+/* GPIO_PIN46_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN46_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN46_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN46_WAKEUP_ENABLE_S  10
+/* GPIO_PIN46_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN46_INT_TYPE  0x00000007
+#define GPIO_PIN46_INT_TYPE_M  ((GPIO_PIN46_INT_TYPE_V)<<(GPIO_PIN46_INT_TYPE_S))
+#define GPIO_PIN46_INT_TYPE_V  0x7
+#define GPIO_PIN46_INT_TYPE_S  7
+/* GPIO_PIN46_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN46_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN46_SYNC1_BYPASS_M  ((GPIO_PIN46_SYNC1_BYPASS_V)<<(GPIO_PIN46_SYNC1_BYPASS_S))
+#define GPIO_PIN46_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN46_SYNC1_BYPASS_S  3
+/* GPIO_PIN46_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN46_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN46_PAD_DRIVER_V  0x1
+#define GPIO_PIN46_PAD_DRIVER_S  2
+/* GPIO_PIN46_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN46_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN46_SYNC2_BYPASS_M  ((GPIO_PIN46_SYNC2_BYPASS_V)<<(GPIO_PIN46_SYNC2_BYPASS_S))
+#define GPIO_PIN46_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN46_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN47_REG          (DR_REG_GPIO_BASE + 0x130)
+/* GPIO_PIN47_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN47_INT_ENA  0x0000001F
+#define GPIO_PIN47_INT_ENA_M  ((GPIO_PIN47_INT_ENA_V)<<(GPIO_PIN47_INT_ENA_S))
+#define GPIO_PIN47_INT_ENA_V  0x1F
+#define GPIO_PIN47_INT_ENA_S  13
+/* GPIO_PIN47_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN47_CONFIG  0x00000003
+#define GPIO_PIN47_CONFIG_M  ((GPIO_PIN47_CONFIG_V)<<(GPIO_PIN47_CONFIG_S))
+#define GPIO_PIN47_CONFIG_V  0x3
+#define GPIO_PIN47_CONFIG_S  11
+/* GPIO_PIN47_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN47_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN47_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN47_WAKEUP_ENABLE_S  10
+/* GPIO_PIN47_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN47_INT_TYPE  0x00000007
+#define GPIO_PIN47_INT_TYPE_M  ((GPIO_PIN47_INT_TYPE_V)<<(GPIO_PIN47_INT_TYPE_S))
+#define GPIO_PIN47_INT_TYPE_V  0x7
+#define GPIO_PIN47_INT_TYPE_S  7
+/* GPIO_PIN47_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN47_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN47_SYNC1_BYPASS_M  ((GPIO_PIN47_SYNC1_BYPASS_V)<<(GPIO_PIN47_SYNC1_BYPASS_S))
+#define GPIO_PIN47_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN47_SYNC1_BYPASS_S  3
+/* GPIO_PIN47_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN47_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN47_PAD_DRIVER_V  0x1
+#define GPIO_PIN47_PAD_DRIVER_S  2
+/* GPIO_PIN47_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN47_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN47_SYNC2_BYPASS_M  ((GPIO_PIN47_SYNC2_BYPASS_V)<<(GPIO_PIN47_SYNC2_BYPASS_S))
+#define GPIO_PIN47_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN47_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN48_REG          (DR_REG_GPIO_BASE + 0x134)
+/* GPIO_PIN48_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN48_INT_ENA  0x0000001F
+#define GPIO_PIN48_INT_ENA_M  ((GPIO_PIN48_INT_ENA_V)<<(GPIO_PIN48_INT_ENA_S))
+#define GPIO_PIN48_INT_ENA_V  0x1F
+#define GPIO_PIN48_INT_ENA_S  13
+/* GPIO_PIN48_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN48_CONFIG  0x00000003
+#define GPIO_PIN48_CONFIG_M  ((GPIO_PIN48_CONFIG_V)<<(GPIO_PIN48_CONFIG_S))
+#define GPIO_PIN48_CONFIG_V  0x3
+#define GPIO_PIN48_CONFIG_S  11
+/* GPIO_PIN48_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN48_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN48_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN48_WAKEUP_ENABLE_S  10
+/* GPIO_PIN48_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN48_INT_TYPE  0x00000007
+#define GPIO_PIN48_INT_TYPE_M  ((GPIO_PIN48_INT_TYPE_V)<<(GPIO_PIN48_INT_TYPE_S))
+#define GPIO_PIN48_INT_TYPE_V  0x7
+#define GPIO_PIN48_INT_TYPE_S  7
+/* GPIO_PIN48_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN48_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN48_SYNC1_BYPASS_M  ((GPIO_PIN48_SYNC1_BYPASS_V)<<(GPIO_PIN48_SYNC1_BYPASS_S))
+#define GPIO_PIN48_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN48_SYNC1_BYPASS_S  3
+/* GPIO_PIN48_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN48_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN48_PAD_DRIVER_V  0x1
+#define GPIO_PIN48_PAD_DRIVER_S  2
+/* GPIO_PIN48_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN48_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN48_SYNC2_BYPASS_M  ((GPIO_PIN48_SYNC2_BYPASS_V)<<(GPIO_PIN48_SYNC2_BYPASS_S))
+#define GPIO_PIN48_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN48_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN49_REG          (DR_REG_GPIO_BASE + 0x138)
+/* GPIO_PIN49_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN49_INT_ENA  0x0000001F
+#define GPIO_PIN49_INT_ENA_M  ((GPIO_PIN49_INT_ENA_V)<<(GPIO_PIN49_INT_ENA_S))
+#define GPIO_PIN49_INT_ENA_V  0x1F
+#define GPIO_PIN49_INT_ENA_S  13
+/* GPIO_PIN49_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN49_CONFIG  0x00000003
+#define GPIO_PIN49_CONFIG_M  ((GPIO_PIN49_CONFIG_V)<<(GPIO_PIN49_CONFIG_S))
+#define GPIO_PIN49_CONFIG_V  0x3
+#define GPIO_PIN49_CONFIG_S  11
+/* GPIO_PIN49_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN49_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN49_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN49_WAKEUP_ENABLE_S  10
+/* GPIO_PIN49_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN49_INT_TYPE  0x00000007
+#define GPIO_PIN49_INT_TYPE_M  ((GPIO_PIN49_INT_TYPE_V)<<(GPIO_PIN49_INT_TYPE_S))
+#define GPIO_PIN49_INT_TYPE_V  0x7
+#define GPIO_PIN49_INT_TYPE_S  7
+/* GPIO_PIN49_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN49_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN49_SYNC1_BYPASS_M  ((GPIO_PIN49_SYNC1_BYPASS_V)<<(GPIO_PIN49_SYNC1_BYPASS_S))
+#define GPIO_PIN49_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN49_SYNC1_BYPASS_S  3
+/* GPIO_PIN49_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN49_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN49_PAD_DRIVER_V  0x1
+#define GPIO_PIN49_PAD_DRIVER_S  2
+/* GPIO_PIN49_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN49_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN49_SYNC2_BYPASS_M  ((GPIO_PIN49_SYNC2_BYPASS_V)<<(GPIO_PIN49_SYNC2_BYPASS_S))
+#define GPIO_PIN49_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN49_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN50_REG          (DR_REG_GPIO_BASE + 0x13C)
+/* GPIO_PIN50_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN50_INT_ENA  0x0000001F
+#define GPIO_PIN50_INT_ENA_M  ((GPIO_PIN50_INT_ENA_V)<<(GPIO_PIN50_INT_ENA_S))
+#define GPIO_PIN50_INT_ENA_V  0x1F
+#define GPIO_PIN50_INT_ENA_S  13
+/* GPIO_PIN50_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN50_CONFIG  0x00000003
+#define GPIO_PIN50_CONFIG_M  ((GPIO_PIN50_CONFIG_V)<<(GPIO_PIN50_CONFIG_S))
+#define GPIO_PIN50_CONFIG_V  0x3
+#define GPIO_PIN50_CONFIG_S  11
+/* GPIO_PIN50_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN50_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN50_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN50_WAKEUP_ENABLE_S  10
+/* GPIO_PIN50_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN50_INT_TYPE  0x00000007
+#define GPIO_PIN50_INT_TYPE_M  ((GPIO_PIN50_INT_TYPE_V)<<(GPIO_PIN50_INT_TYPE_S))
+#define GPIO_PIN50_INT_TYPE_V  0x7
+#define GPIO_PIN50_INT_TYPE_S  7
+/* GPIO_PIN50_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN50_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN50_SYNC1_BYPASS_M  ((GPIO_PIN50_SYNC1_BYPASS_V)<<(GPIO_PIN50_SYNC1_BYPASS_S))
+#define GPIO_PIN50_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN50_SYNC1_BYPASS_S  3
+/* GPIO_PIN50_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN50_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN50_PAD_DRIVER_V  0x1
+#define GPIO_PIN50_PAD_DRIVER_S  2
+/* GPIO_PIN50_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN50_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN50_SYNC2_BYPASS_M  ((GPIO_PIN50_SYNC2_BYPASS_V)<<(GPIO_PIN50_SYNC2_BYPASS_S))
+#define GPIO_PIN50_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN50_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN51_REG          (DR_REG_GPIO_BASE + 0x140)
+/* GPIO_PIN51_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN51_INT_ENA  0x0000001F
+#define GPIO_PIN51_INT_ENA_M  ((GPIO_PIN51_INT_ENA_V)<<(GPIO_PIN51_INT_ENA_S))
+#define GPIO_PIN51_INT_ENA_V  0x1F
+#define GPIO_PIN51_INT_ENA_S  13
+/* GPIO_PIN51_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN51_CONFIG  0x00000003
+#define GPIO_PIN51_CONFIG_M  ((GPIO_PIN51_CONFIG_V)<<(GPIO_PIN51_CONFIG_S))
+#define GPIO_PIN51_CONFIG_V  0x3
+#define GPIO_PIN51_CONFIG_S  11
+/* GPIO_PIN51_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN51_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN51_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN51_WAKEUP_ENABLE_S  10
+/* GPIO_PIN51_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN51_INT_TYPE  0x00000007
+#define GPIO_PIN51_INT_TYPE_M  ((GPIO_PIN51_INT_TYPE_V)<<(GPIO_PIN51_INT_TYPE_S))
+#define GPIO_PIN51_INT_TYPE_V  0x7
+#define GPIO_PIN51_INT_TYPE_S  7
+/* GPIO_PIN51_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN51_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN51_SYNC1_BYPASS_M  ((GPIO_PIN51_SYNC1_BYPASS_V)<<(GPIO_PIN51_SYNC1_BYPASS_S))
+#define GPIO_PIN51_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN51_SYNC1_BYPASS_S  3
+/* GPIO_PIN51_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN51_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN51_PAD_DRIVER_V  0x1
+#define GPIO_PIN51_PAD_DRIVER_S  2
+/* GPIO_PIN51_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN51_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN51_SYNC2_BYPASS_M  ((GPIO_PIN51_SYNC2_BYPASS_V)<<(GPIO_PIN51_SYNC2_BYPASS_S))
+#define GPIO_PIN51_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN51_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN52_REG          (DR_REG_GPIO_BASE + 0x144)
+/* GPIO_PIN52_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN52_INT_ENA  0x0000001F
+#define GPIO_PIN52_INT_ENA_M  ((GPIO_PIN52_INT_ENA_V)<<(GPIO_PIN52_INT_ENA_S))
+#define GPIO_PIN52_INT_ENA_V  0x1F
+#define GPIO_PIN52_INT_ENA_S  13
+/* GPIO_PIN52_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN52_CONFIG  0x00000003
+#define GPIO_PIN52_CONFIG_M  ((GPIO_PIN52_CONFIG_V)<<(GPIO_PIN52_CONFIG_S))
+#define GPIO_PIN52_CONFIG_V  0x3
+#define GPIO_PIN52_CONFIG_S  11
+/* GPIO_PIN52_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN52_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN52_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN52_WAKEUP_ENABLE_S  10
+/* GPIO_PIN52_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN52_INT_TYPE  0x00000007
+#define GPIO_PIN52_INT_TYPE_M  ((GPIO_PIN52_INT_TYPE_V)<<(GPIO_PIN52_INT_TYPE_S))
+#define GPIO_PIN52_INT_TYPE_V  0x7
+#define GPIO_PIN52_INT_TYPE_S  7
+/* GPIO_PIN52_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN52_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN52_SYNC1_BYPASS_M  ((GPIO_PIN52_SYNC1_BYPASS_V)<<(GPIO_PIN52_SYNC1_BYPASS_S))
+#define GPIO_PIN52_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN52_SYNC1_BYPASS_S  3
+/* GPIO_PIN52_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN52_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN52_PAD_DRIVER_V  0x1
+#define GPIO_PIN52_PAD_DRIVER_S  2
+/* GPIO_PIN52_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN52_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN52_SYNC2_BYPASS_M  ((GPIO_PIN52_SYNC2_BYPASS_V)<<(GPIO_PIN52_SYNC2_BYPASS_S))
+#define GPIO_PIN52_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN52_SYNC2_BYPASS_S  0
+
+#define GPIO_PIN53_REG          (DR_REG_GPIO_BASE + 0x148)
+/* GPIO_PIN53_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */
+/*description: */
+#define GPIO_PIN53_INT_ENA  0x0000001F
+#define GPIO_PIN53_INT_ENA_M  ((GPIO_PIN53_INT_ENA_V)<<(GPIO_PIN53_INT_ENA_S))
+#define GPIO_PIN53_INT_ENA_V  0x1F
+#define GPIO_PIN53_INT_ENA_S  13
+/* GPIO_PIN53_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN53_CONFIG  0x00000003
+#define GPIO_PIN53_CONFIG_M  ((GPIO_PIN53_CONFIG_V)<<(GPIO_PIN53_CONFIG_S))
+#define GPIO_PIN53_CONFIG_V  0x3
+#define GPIO_PIN53_CONFIG_S  11
+/* GPIO_PIN53_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN53_WAKEUP_ENABLE  (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_M  (BIT(10))
+#define GPIO_PIN53_WAKEUP_ENABLE_V  0x1
+#define GPIO_PIN53_WAKEUP_ENABLE_S  10
+/* GPIO_PIN53_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */
+/*description: */
+#define GPIO_PIN53_INT_TYPE  0x00000007
+#define GPIO_PIN53_INT_TYPE_M  ((GPIO_PIN53_INT_TYPE_V)<<(GPIO_PIN53_INT_TYPE_S))
+#define GPIO_PIN53_INT_TYPE_V  0x7
+#define GPIO_PIN53_INT_TYPE_S  7
+/* GPIO_PIN53_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN53_SYNC1_BYPASS  0x00000003
+#define GPIO_PIN53_SYNC1_BYPASS_M  ((GPIO_PIN53_SYNC1_BYPASS_V)<<(GPIO_PIN53_SYNC1_BYPASS_S))
+#define GPIO_PIN53_SYNC1_BYPASS_V  0x3
+#define GPIO_PIN53_SYNC1_BYPASS_S  3
+/* GPIO_PIN53_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_PIN53_PAD_DRIVER  (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_M  (BIT(2))
+#define GPIO_PIN53_PAD_DRIVER_V  0x1
+#define GPIO_PIN53_PAD_DRIVER_S  2
+/* GPIO_PIN53_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: */
+#define GPIO_PIN53_SYNC2_BYPASS  0x00000003
+#define GPIO_PIN53_SYNC2_BYPASS_M  ((GPIO_PIN53_SYNC2_BYPASS_V)<<(GPIO_PIN53_SYNC2_BYPASS_S))
+#define GPIO_PIN53_SYNC2_BYPASS_V  0x3
+#define GPIO_PIN53_SYNC2_BYPASS_S  0
+
+#define GPIO_STATUS_NEXT_REG          (DR_REG_GPIO_BASE + 0x14C)
+/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define GPIO_STATUS_INTERRUPT_NEXT  0xFFFFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_M  ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S))
+#define GPIO_STATUS_INTERRUPT_NEXT_V  0xFFFFFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT_S  0
+
+#define GPIO_STATUS_NEXT1_REG          (DR_REG_GPIO_BASE + 0x150)
+/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: */
+#define GPIO_STATUS_INTERRUPT_NEXT1  0x003FFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT1_M  ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S))
+#define GPIO_STATUS_INTERRUPT_NEXT1_V  0x3FFFFF
+#define GPIO_STATUS_INTERRUPT_NEXT1_S  0
+
+#define GPIO_FUNC0_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x154)
+/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG0_IN_SEL  (BIT(7))
+#define GPIO_SIG0_IN_SEL_M  (BIT(7))
+#define GPIO_SIG0_IN_SEL_V  0x1
+#define GPIO_SIG0_IN_SEL_S  7
+/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC0_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC0_IN_INV_SEL_V  0x1
+#define GPIO_FUNC0_IN_INV_SEL_S  6
+/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC0_IN_SEL  0x0000003F
+#define GPIO_FUNC0_IN_SEL_M  ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S))
+#define GPIO_FUNC0_IN_SEL_V  0x3F
+#define GPIO_FUNC0_IN_SEL_S  0
+
+#define GPIO_FUNC1_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x158)
+/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG1_IN_SEL  (BIT(7))
+#define GPIO_SIG1_IN_SEL_M  (BIT(7))
+#define GPIO_SIG1_IN_SEL_V  0x1
+#define GPIO_SIG1_IN_SEL_S  7
+/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC1_IN_INV_SEL_V  0x1
+#define GPIO_FUNC1_IN_INV_SEL_S  6
+/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC1_IN_SEL  0x0000003F
+#define GPIO_FUNC1_IN_SEL_M  ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S))
+#define GPIO_FUNC1_IN_SEL_V  0x3F
+#define GPIO_FUNC1_IN_SEL_S  0
+
+#define GPIO_FUNC2_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x15C)
+/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG2_IN_SEL  (BIT(7))
+#define GPIO_SIG2_IN_SEL_M  (BIT(7))
+#define GPIO_SIG2_IN_SEL_V  0x1
+#define GPIO_SIG2_IN_SEL_S  7
+/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC2_IN_INV_SEL_V  0x1
+#define GPIO_FUNC2_IN_INV_SEL_S  6
+/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC2_IN_SEL  0x0000003F
+#define GPIO_FUNC2_IN_SEL_M  ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S))
+#define GPIO_FUNC2_IN_SEL_V  0x3F
+#define GPIO_FUNC2_IN_SEL_S  0
+
+#define GPIO_FUNC3_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x160)
+/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG3_IN_SEL  (BIT(7))
+#define GPIO_SIG3_IN_SEL_M  (BIT(7))
+#define GPIO_SIG3_IN_SEL_V  0x1
+#define GPIO_SIG3_IN_SEL_S  7
+/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC3_IN_INV_SEL_V  0x1
+#define GPIO_FUNC3_IN_INV_SEL_S  6
+/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC3_IN_SEL  0x0000003F
+#define GPIO_FUNC3_IN_SEL_M  ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S))
+#define GPIO_FUNC3_IN_SEL_V  0x3F
+#define GPIO_FUNC3_IN_SEL_S  0
+
+#define GPIO_FUNC4_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x164)
+/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG4_IN_SEL  (BIT(7))
+#define GPIO_SIG4_IN_SEL_M  (BIT(7))
+#define GPIO_SIG4_IN_SEL_V  0x1
+#define GPIO_SIG4_IN_SEL_S  7
+/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC4_IN_INV_SEL_V  0x1
+#define GPIO_FUNC4_IN_INV_SEL_S  6
+/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC4_IN_SEL  0x0000003F
+#define GPIO_FUNC4_IN_SEL_M  ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S))
+#define GPIO_FUNC4_IN_SEL_V  0x3F
+#define GPIO_FUNC4_IN_SEL_S  0
+
+#define GPIO_FUNC5_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x168)
+/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG5_IN_SEL  (BIT(7))
+#define GPIO_SIG5_IN_SEL_M  (BIT(7))
+#define GPIO_SIG5_IN_SEL_V  0x1
+#define GPIO_SIG5_IN_SEL_S  7
+/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC5_IN_INV_SEL_V  0x1
+#define GPIO_FUNC5_IN_INV_SEL_S  6
+/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC5_IN_SEL  0x0000003F
+#define GPIO_FUNC5_IN_SEL_M  ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S))
+#define GPIO_FUNC5_IN_SEL_V  0x3F
+#define GPIO_FUNC5_IN_SEL_S  0
+
+#define GPIO_FUNC6_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x16C)
+/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG6_IN_SEL  (BIT(7))
+#define GPIO_SIG6_IN_SEL_M  (BIT(7))
+#define GPIO_SIG6_IN_SEL_V  0x1
+#define GPIO_SIG6_IN_SEL_S  7
+/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC6_IN_INV_SEL_V  0x1
+#define GPIO_FUNC6_IN_INV_SEL_S  6
+/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC6_IN_SEL  0x0000003F
+#define GPIO_FUNC6_IN_SEL_M  ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S))
+#define GPIO_FUNC6_IN_SEL_V  0x3F
+#define GPIO_FUNC6_IN_SEL_S  0
+
+#define GPIO_FUNC7_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x170)
+/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG7_IN_SEL  (BIT(7))
+#define GPIO_SIG7_IN_SEL_M  (BIT(7))
+#define GPIO_SIG7_IN_SEL_V  0x1
+#define GPIO_SIG7_IN_SEL_S  7
+/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC7_IN_INV_SEL_V  0x1
+#define GPIO_FUNC7_IN_INV_SEL_S  6
+/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC7_IN_SEL  0x0000003F
+#define GPIO_FUNC7_IN_SEL_M  ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S))
+#define GPIO_FUNC7_IN_SEL_V  0x3F
+#define GPIO_FUNC7_IN_SEL_S  0
+
+#define GPIO_FUNC8_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x174)
+/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG8_IN_SEL  (BIT(7))
+#define GPIO_SIG8_IN_SEL_M  (BIT(7))
+#define GPIO_SIG8_IN_SEL_V  0x1
+#define GPIO_SIG8_IN_SEL_S  7
+/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC8_IN_INV_SEL_V  0x1
+#define GPIO_FUNC8_IN_INV_SEL_S  6
+/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC8_IN_SEL  0x0000003F
+#define GPIO_FUNC8_IN_SEL_M  ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S))
+#define GPIO_FUNC8_IN_SEL_V  0x3F
+#define GPIO_FUNC8_IN_SEL_S  0
+
+#define GPIO_FUNC9_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x178)
+/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG9_IN_SEL  (BIT(7))
+#define GPIO_SIG9_IN_SEL_M  (BIT(7))
+#define GPIO_SIG9_IN_SEL_V  0x1
+#define GPIO_SIG9_IN_SEL_S  7
+/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC9_IN_INV_SEL_V  0x1
+#define GPIO_FUNC9_IN_INV_SEL_S  6
+/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC9_IN_SEL  0x0000003F
+#define GPIO_FUNC9_IN_SEL_M  ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S))
+#define GPIO_FUNC9_IN_SEL_V  0x3F
+#define GPIO_FUNC9_IN_SEL_S  0
+
+#define GPIO_FUNC10_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x17C)
+/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG10_IN_SEL  (BIT(7))
+#define GPIO_SIG10_IN_SEL_M  (BIT(7))
+#define GPIO_SIG10_IN_SEL_V  0x1
+#define GPIO_SIG10_IN_SEL_S  7
+/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC10_IN_INV_SEL_V  0x1
+#define GPIO_FUNC10_IN_INV_SEL_S  6
+/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC10_IN_SEL  0x0000003F
+#define GPIO_FUNC10_IN_SEL_M  ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S))
+#define GPIO_FUNC10_IN_SEL_V  0x3F
+#define GPIO_FUNC10_IN_SEL_S  0
+
+#define GPIO_FUNC11_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x180)
+/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG11_IN_SEL  (BIT(7))
+#define GPIO_SIG11_IN_SEL_M  (BIT(7))
+#define GPIO_SIG11_IN_SEL_V  0x1
+#define GPIO_SIG11_IN_SEL_S  7
+/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC11_IN_INV_SEL_V  0x1
+#define GPIO_FUNC11_IN_INV_SEL_S  6
+/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC11_IN_SEL  0x0000003F
+#define GPIO_FUNC11_IN_SEL_M  ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S))
+#define GPIO_FUNC11_IN_SEL_V  0x3F
+#define GPIO_FUNC11_IN_SEL_S  0
+
+#define GPIO_FUNC12_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x184)
+/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG12_IN_SEL  (BIT(7))
+#define GPIO_SIG12_IN_SEL_M  (BIT(7))
+#define GPIO_SIG12_IN_SEL_V  0x1
+#define GPIO_SIG12_IN_SEL_S  7
+/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC12_IN_INV_SEL_V  0x1
+#define GPIO_FUNC12_IN_INV_SEL_S  6
+/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC12_IN_SEL  0x0000003F
+#define GPIO_FUNC12_IN_SEL_M  ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S))
+#define GPIO_FUNC12_IN_SEL_V  0x3F
+#define GPIO_FUNC12_IN_SEL_S  0
+
+#define GPIO_FUNC13_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x188)
+/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG13_IN_SEL  (BIT(7))
+#define GPIO_SIG13_IN_SEL_M  (BIT(7))
+#define GPIO_SIG13_IN_SEL_V  0x1
+#define GPIO_SIG13_IN_SEL_S  7
+/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC13_IN_INV_SEL_V  0x1
+#define GPIO_FUNC13_IN_INV_SEL_S  6
+/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC13_IN_SEL  0x0000003F
+#define GPIO_FUNC13_IN_SEL_M  ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S))
+#define GPIO_FUNC13_IN_SEL_V  0x3F
+#define GPIO_FUNC13_IN_SEL_S  0
+
+#define GPIO_FUNC14_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x18C)
+/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG14_IN_SEL  (BIT(7))
+#define GPIO_SIG14_IN_SEL_M  (BIT(7))
+#define GPIO_SIG14_IN_SEL_V  0x1
+#define GPIO_SIG14_IN_SEL_S  7
+/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC14_IN_INV_SEL_V  0x1
+#define GPIO_FUNC14_IN_INV_SEL_S  6
+/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC14_IN_SEL  0x0000003F
+#define GPIO_FUNC14_IN_SEL_M  ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S))
+#define GPIO_FUNC14_IN_SEL_V  0x3F
+#define GPIO_FUNC14_IN_SEL_S  0
+
+#define GPIO_FUNC15_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x190)
+/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG15_IN_SEL  (BIT(7))
+#define GPIO_SIG15_IN_SEL_M  (BIT(7))
+#define GPIO_SIG15_IN_SEL_V  0x1
+#define GPIO_SIG15_IN_SEL_S  7
+/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC15_IN_INV_SEL_V  0x1
+#define GPIO_FUNC15_IN_INV_SEL_S  6
+/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC15_IN_SEL  0x0000003F
+#define GPIO_FUNC15_IN_SEL_M  ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S))
+#define GPIO_FUNC15_IN_SEL_V  0x3F
+#define GPIO_FUNC15_IN_SEL_S  0
+
+#define GPIO_FUNC16_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x194)
+/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG16_IN_SEL  (BIT(7))
+#define GPIO_SIG16_IN_SEL_M  (BIT(7))
+#define GPIO_SIG16_IN_SEL_V  0x1
+#define GPIO_SIG16_IN_SEL_S  7
+/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC16_IN_INV_SEL_V  0x1
+#define GPIO_FUNC16_IN_INV_SEL_S  6
+/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC16_IN_SEL  0x0000003F
+#define GPIO_FUNC16_IN_SEL_M  ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S))
+#define GPIO_FUNC16_IN_SEL_V  0x3F
+#define GPIO_FUNC16_IN_SEL_S  0
+
+#define GPIO_FUNC17_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x198)
+/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG17_IN_SEL  (BIT(7))
+#define GPIO_SIG17_IN_SEL_M  (BIT(7))
+#define GPIO_SIG17_IN_SEL_V  0x1
+#define GPIO_SIG17_IN_SEL_S  7
+/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC17_IN_INV_SEL_V  0x1
+#define GPIO_FUNC17_IN_INV_SEL_S  6
+/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC17_IN_SEL  0x0000003F
+#define GPIO_FUNC17_IN_SEL_M  ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S))
+#define GPIO_FUNC17_IN_SEL_V  0x3F
+#define GPIO_FUNC17_IN_SEL_S  0
+
+#define GPIO_FUNC18_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x19C)
+/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG18_IN_SEL  (BIT(7))
+#define GPIO_SIG18_IN_SEL_M  (BIT(7))
+#define GPIO_SIG18_IN_SEL_V  0x1
+#define GPIO_SIG18_IN_SEL_S  7
+/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC18_IN_INV_SEL_V  0x1
+#define GPIO_FUNC18_IN_INV_SEL_S  6
+/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC18_IN_SEL  0x0000003F
+#define GPIO_FUNC18_IN_SEL_M  ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S))
+#define GPIO_FUNC18_IN_SEL_V  0x3F
+#define GPIO_FUNC18_IN_SEL_S  0
+
+#define GPIO_FUNC19_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A0)
+/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG19_IN_SEL  (BIT(7))
+#define GPIO_SIG19_IN_SEL_M  (BIT(7))
+#define GPIO_SIG19_IN_SEL_V  0x1
+#define GPIO_SIG19_IN_SEL_S  7
+/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC19_IN_INV_SEL_V  0x1
+#define GPIO_FUNC19_IN_INV_SEL_S  6
+/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC19_IN_SEL  0x0000003F
+#define GPIO_FUNC19_IN_SEL_M  ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S))
+#define GPIO_FUNC19_IN_SEL_V  0x3F
+#define GPIO_FUNC19_IN_SEL_S  0
+
+#define GPIO_FUNC20_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A4)
+/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG20_IN_SEL  (BIT(7))
+#define GPIO_SIG20_IN_SEL_M  (BIT(7))
+#define GPIO_SIG20_IN_SEL_V  0x1
+#define GPIO_SIG20_IN_SEL_S  7
+/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC20_IN_INV_SEL_V  0x1
+#define GPIO_FUNC20_IN_INV_SEL_S  6
+/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC20_IN_SEL  0x0000003F
+#define GPIO_FUNC20_IN_SEL_M  ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S))
+#define GPIO_FUNC20_IN_SEL_V  0x3F
+#define GPIO_FUNC20_IN_SEL_S  0
+
+#define GPIO_FUNC21_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1A8)
+/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG21_IN_SEL  (BIT(7))
+#define GPIO_SIG21_IN_SEL_M  (BIT(7))
+#define GPIO_SIG21_IN_SEL_V  0x1
+#define GPIO_SIG21_IN_SEL_S  7
+/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC21_IN_INV_SEL_V  0x1
+#define GPIO_FUNC21_IN_INV_SEL_S  6
+/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC21_IN_SEL  0x0000003F
+#define GPIO_FUNC21_IN_SEL_M  ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S))
+#define GPIO_FUNC21_IN_SEL_V  0x3F
+#define GPIO_FUNC21_IN_SEL_S  0
+
+#define GPIO_FUNC22_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1AC)
+/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG22_IN_SEL  (BIT(7))
+#define GPIO_SIG22_IN_SEL_M  (BIT(7))
+#define GPIO_SIG22_IN_SEL_V  0x1
+#define GPIO_SIG22_IN_SEL_S  7
+/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC22_IN_INV_SEL_V  0x1
+#define GPIO_FUNC22_IN_INV_SEL_S  6
+/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC22_IN_SEL  0x0000003F
+#define GPIO_FUNC22_IN_SEL_M  ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S))
+#define GPIO_FUNC22_IN_SEL_V  0x3F
+#define GPIO_FUNC22_IN_SEL_S  0
+
+#define GPIO_FUNC23_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B0)
+/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG23_IN_SEL  (BIT(7))
+#define GPIO_SIG23_IN_SEL_M  (BIT(7))
+#define GPIO_SIG23_IN_SEL_V  0x1
+#define GPIO_SIG23_IN_SEL_S  7
+/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC23_IN_INV_SEL_V  0x1
+#define GPIO_FUNC23_IN_INV_SEL_S  6
+/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC23_IN_SEL  0x0000003F
+#define GPIO_FUNC23_IN_SEL_M  ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S))
+#define GPIO_FUNC23_IN_SEL_V  0x3F
+#define GPIO_FUNC23_IN_SEL_S  0
+
+#define GPIO_FUNC24_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B4)
+/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG24_IN_SEL  (BIT(7))
+#define GPIO_SIG24_IN_SEL_M  (BIT(7))
+#define GPIO_SIG24_IN_SEL_V  0x1
+#define GPIO_SIG24_IN_SEL_S  7
+/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC24_IN_INV_SEL_V  0x1
+#define GPIO_FUNC24_IN_INV_SEL_S  6
+/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC24_IN_SEL  0x0000003F
+#define GPIO_FUNC24_IN_SEL_M  ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S))
+#define GPIO_FUNC24_IN_SEL_V  0x3F
+#define GPIO_FUNC24_IN_SEL_S  0
+
+#define GPIO_FUNC25_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1B8)
+/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG25_IN_SEL  (BIT(7))
+#define GPIO_SIG25_IN_SEL_M  (BIT(7))
+#define GPIO_SIG25_IN_SEL_V  0x1
+#define GPIO_SIG25_IN_SEL_S  7
+/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC25_IN_INV_SEL_V  0x1
+#define GPIO_FUNC25_IN_INV_SEL_S  6
+/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC25_IN_SEL  0x0000003F
+#define GPIO_FUNC25_IN_SEL_M  ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S))
+#define GPIO_FUNC25_IN_SEL_V  0x3F
+#define GPIO_FUNC25_IN_SEL_S  0
+
+#define GPIO_FUNC26_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1BC)
+/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG26_IN_SEL  (BIT(7))
+#define GPIO_SIG26_IN_SEL_M  (BIT(7))
+#define GPIO_SIG26_IN_SEL_V  0x1
+#define GPIO_SIG26_IN_SEL_S  7
+/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC26_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC26_IN_INV_SEL_V  0x1
+#define GPIO_FUNC26_IN_INV_SEL_S  6
+/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC26_IN_SEL  0x0000003F
+#define GPIO_FUNC26_IN_SEL_M  ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S))
+#define GPIO_FUNC26_IN_SEL_V  0x3F
+#define GPIO_FUNC26_IN_SEL_S  0
+
+#define GPIO_FUNC27_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C0)
+/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG27_IN_SEL  (BIT(7))
+#define GPIO_SIG27_IN_SEL_M  (BIT(7))
+#define GPIO_SIG27_IN_SEL_V  0x1
+#define GPIO_SIG27_IN_SEL_S  7
+/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC27_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC27_IN_INV_SEL_V  0x1
+#define GPIO_FUNC27_IN_INV_SEL_S  6
+/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC27_IN_SEL  0x0000003F
+#define GPIO_FUNC27_IN_SEL_M  ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S))
+#define GPIO_FUNC27_IN_SEL_V  0x3F
+#define GPIO_FUNC27_IN_SEL_S  0
+
+#define GPIO_FUNC28_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C4)
+/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG28_IN_SEL  (BIT(7))
+#define GPIO_SIG28_IN_SEL_M  (BIT(7))
+#define GPIO_SIG28_IN_SEL_V  0x1
+#define GPIO_SIG28_IN_SEL_S  7
+/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC28_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC28_IN_INV_SEL_V  0x1
+#define GPIO_FUNC28_IN_INV_SEL_S  6
+/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC28_IN_SEL  0x0000003F
+#define GPIO_FUNC28_IN_SEL_M  ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S))
+#define GPIO_FUNC28_IN_SEL_V  0x3F
+#define GPIO_FUNC28_IN_SEL_S  0
+
+#define GPIO_FUNC29_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1C8)
+/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG29_IN_SEL  (BIT(7))
+#define GPIO_SIG29_IN_SEL_M  (BIT(7))
+#define GPIO_SIG29_IN_SEL_V  0x1
+#define GPIO_SIG29_IN_SEL_S  7
+/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC29_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC29_IN_INV_SEL_V  0x1
+#define GPIO_FUNC29_IN_INV_SEL_S  6
+/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC29_IN_SEL  0x0000003F
+#define GPIO_FUNC29_IN_SEL_M  ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S))
+#define GPIO_FUNC29_IN_SEL_V  0x3F
+#define GPIO_FUNC29_IN_SEL_S  0
+
+#define GPIO_FUNC30_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1CC)
+/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG30_IN_SEL  (BIT(7))
+#define GPIO_SIG30_IN_SEL_M  (BIT(7))
+#define GPIO_SIG30_IN_SEL_V  0x1
+#define GPIO_SIG30_IN_SEL_S  7
+/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC30_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC30_IN_INV_SEL_V  0x1
+#define GPIO_FUNC30_IN_INV_SEL_S  6
+/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC30_IN_SEL  0x0000003F
+#define GPIO_FUNC30_IN_SEL_M  ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S))
+#define GPIO_FUNC30_IN_SEL_V  0x3F
+#define GPIO_FUNC30_IN_SEL_S  0
+
+#define GPIO_FUNC31_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D0)
+/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG31_IN_SEL  (BIT(7))
+#define GPIO_SIG31_IN_SEL_M  (BIT(7))
+#define GPIO_SIG31_IN_SEL_V  0x1
+#define GPIO_SIG31_IN_SEL_S  7
+/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC31_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC31_IN_INV_SEL_V  0x1
+#define GPIO_FUNC31_IN_INV_SEL_S  6
+/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC31_IN_SEL  0x0000003F
+#define GPIO_FUNC31_IN_SEL_M  ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S))
+#define GPIO_FUNC31_IN_SEL_V  0x3F
+#define GPIO_FUNC31_IN_SEL_S  0
+
+#define GPIO_FUNC32_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D4)
+/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG32_IN_SEL  (BIT(7))
+#define GPIO_SIG32_IN_SEL_M  (BIT(7))
+#define GPIO_SIG32_IN_SEL_V  0x1
+#define GPIO_SIG32_IN_SEL_S  7
+/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC32_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC32_IN_INV_SEL_V  0x1
+#define GPIO_FUNC32_IN_INV_SEL_S  6
+/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC32_IN_SEL  0x0000003F
+#define GPIO_FUNC32_IN_SEL_M  ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S))
+#define GPIO_FUNC32_IN_SEL_V  0x3F
+#define GPIO_FUNC32_IN_SEL_S  0
+
+#define GPIO_FUNC33_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1D8)
+/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG33_IN_SEL  (BIT(7))
+#define GPIO_SIG33_IN_SEL_M  (BIT(7))
+#define GPIO_SIG33_IN_SEL_V  0x1
+#define GPIO_SIG33_IN_SEL_S  7
+/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC33_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC33_IN_INV_SEL_V  0x1
+#define GPIO_FUNC33_IN_INV_SEL_S  6
+/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC33_IN_SEL  0x0000003F
+#define GPIO_FUNC33_IN_SEL_M  ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S))
+#define GPIO_FUNC33_IN_SEL_V  0x3F
+#define GPIO_FUNC33_IN_SEL_S  0
+
+#define GPIO_FUNC34_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1DC)
+/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG34_IN_SEL  (BIT(7))
+#define GPIO_SIG34_IN_SEL_M  (BIT(7))
+#define GPIO_SIG34_IN_SEL_V  0x1
+#define GPIO_SIG34_IN_SEL_S  7
+/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC34_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC34_IN_INV_SEL_V  0x1
+#define GPIO_FUNC34_IN_INV_SEL_S  6
+/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC34_IN_SEL  0x0000003F
+#define GPIO_FUNC34_IN_SEL_M  ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S))
+#define GPIO_FUNC34_IN_SEL_V  0x3F
+#define GPIO_FUNC34_IN_SEL_S  0
+
+#define GPIO_FUNC35_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E0)
+/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG35_IN_SEL  (BIT(7))
+#define GPIO_SIG35_IN_SEL_M  (BIT(7))
+#define GPIO_SIG35_IN_SEL_V  0x1
+#define GPIO_SIG35_IN_SEL_S  7
+/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC35_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC35_IN_INV_SEL_V  0x1
+#define GPIO_FUNC35_IN_INV_SEL_S  6
+/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC35_IN_SEL  0x0000003F
+#define GPIO_FUNC35_IN_SEL_M  ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S))
+#define GPIO_FUNC35_IN_SEL_V  0x3F
+#define GPIO_FUNC35_IN_SEL_S  0
+
+#define GPIO_FUNC36_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E4)
+/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG36_IN_SEL  (BIT(7))
+#define GPIO_SIG36_IN_SEL_M  (BIT(7))
+#define GPIO_SIG36_IN_SEL_V  0x1
+#define GPIO_SIG36_IN_SEL_S  7
+/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC36_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC36_IN_INV_SEL_V  0x1
+#define GPIO_FUNC36_IN_INV_SEL_S  6
+/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC36_IN_SEL  0x0000003F
+#define GPIO_FUNC36_IN_SEL_M  ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S))
+#define GPIO_FUNC36_IN_SEL_V  0x3F
+#define GPIO_FUNC36_IN_SEL_S  0
+
+#define GPIO_FUNC37_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1E8)
+/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG37_IN_SEL  (BIT(7))
+#define GPIO_SIG37_IN_SEL_M  (BIT(7))
+#define GPIO_SIG37_IN_SEL_V  0x1
+#define GPIO_SIG37_IN_SEL_S  7
+/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC37_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC37_IN_INV_SEL_V  0x1
+#define GPIO_FUNC37_IN_INV_SEL_S  6
+/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC37_IN_SEL  0x0000003F
+#define GPIO_FUNC37_IN_SEL_M  ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S))
+#define GPIO_FUNC37_IN_SEL_V  0x3F
+#define GPIO_FUNC37_IN_SEL_S  0
+
+#define GPIO_FUNC38_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1EC)
+/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG38_IN_SEL  (BIT(7))
+#define GPIO_SIG38_IN_SEL_M  (BIT(7))
+#define GPIO_SIG38_IN_SEL_V  0x1
+#define GPIO_SIG38_IN_SEL_S  7
+/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC38_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC38_IN_INV_SEL_V  0x1
+#define GPIO_FUNC38_IN_INV_SEL_S  6
+/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC38_IN_SEL  0x0000003F
+#define GPIO_FUNC38_IN_SEL_M  ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S))
+#define GPIO_FUNC38_IN_SEL_V  0x3F
+#define GPIO_FUNC38_IN_SEL_S  0
+
+#define GPIO_FUNC39_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F0)
+/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG39_IN_SEL  (BIT(7))
+#define GPIO_SIG39_IN_SEL_M  (BIT(7))
+#define GPIO_SIG39_IN_SEL_V  0x1
+#define GPIO_SIG39_IN_SEL_S  7
+/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC39_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC39_IN_INV_SEL_V  0x1
+#define GPIO_FUNC39_IN_INV_SEL_S  6
+/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC39_IN_SEL  0x0000003F
+#define GPIO_FUNC39_IN_SEL_M  ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S))
+#define GPIO_FUNC39_IN_SEL_V  0x3F
+#define GPIO_FUNC39_IN_SEL_S  0
+
+#define GPIO_FUNC40_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F4)
+/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG40_IN_SEL  (BIT(7))
+#define GPIO_SIG40_IN_SEL_M  (BIT(7))
+#define GPIO_SIG40_IN_SEL_V  0x1
+#define GPIO_SIG40_IN_SEL_S  7
+/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC40_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC40_IN_INV_SEL_V  0x1
+#define GPIO_FUNC40_IN_INV_SEL_S  6
+/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC40_IN_SEL  0x0000003F
+#define GPIO_FUNC40_IN_SEL_M  ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S))
+#define GPIO_FUNC40_IN_SEL_V  0x3F
+#define GPIO_FUNC40_IN_SEL_S  0
+
+#define GPIO_FUNC41_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1F8)
+/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG41_IN_SEL  (BIT(7))
+#define GPIO_SIG41_IN_SEL_M  (BIT(7))
+#define GPIO_SIG41_IN_SEL_V  0x1
+#define GPIO_SIG41_IN_SEL_S  7
+/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC41_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC41_IN_INV_SEL_V  0x1
+#define GPIO_FUNC41_IN_INV_SEL_S  6
+/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC41_IN_SEL  0x0000003F
+#define GPIO_FUNC41_IN_SEL_M  ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S))
+#define GPIO_FUNC41_IN_SEL_V  0x3F
+#define GPIO_FUNC41_IN_SEL_S  0
+
+#define GPIO_FUNC42_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x1FC)
+/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG42_IN_SEL  (BIT(7))
+#define GPIO_SIG42_IN_SEL_M  (BIT(7))
+#define GPIO_SIG42_IN_SEL_V  0x1
+#define GPIO_SIG42_IN_SEL_S  7
+/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC42_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC42_IN_INV_SEL_V  0x1
+#define GPIO_FUNC42_IN_INV_SEL_S  6
+/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC42_IN_SEL  0x0000003F
+#define GPIO_FUNC42_IN_SEL_M  ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S))
+#define GPIO_FUNC42_IN_SEL_V  0x3F
+#define GPIO_FUNC42_IN_SEL_S  0
+
+#define GPIO_FUNC43_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x200)
+/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG43_IN_SEL  (BIT(7))
+#define GPIO_SIG43_IN_SEL_M  (BIT(7))
+#define GPIO_SIG43_IN_SEL_V  0x1
+#define GPIO_SIG43_IN_SEL_S  7
+/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC43_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC43_IN_INV_SEL_V  0x1
+#define GPIO_FUNC43_IN_INV_SEL_S  6
+/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC43_IN_SEL  0x0000003F
+#define GPIO_FUNC43_IN_SEL_M  ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S))
+#define GPIO_FUNC43_IN_SEL_V  0x3F
+#define GPIO_FUNC43_IN_SEL_S  0
+
+#define GPIO_FUNC44_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x204)
+/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG44_IN_SEL  (BIT(7))
+#define GPIO_SIG44_IN_SEL_M  (BIT(7))
+#define GPIO_SIG44_IN_SEL_V  0x1
+#define GPIO_SIG44_IN_SEL_S  7
+/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC44_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC44_IN_INV_SEL_V  0x1
+#define GPIO_FUNC44_IN_INV_SEL_S  6
+/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC44_IN_SEL  0x0000003F
+#define GPIO_FUNC44_IN_SEL_M  ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S))
+#define GPIO_FUNC44_IN_SEL_V  0x3F
+#define GPIO_FUNC44_IN_SEL_S  0
+
+#define GPIO_FUNC45_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x208)
+/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG45_IN_SEL  (BIT(7))
+#define GPIO_SIG45_IN_SEL_M  (BIT(7))
+#define GPIO_SIG45_IN_SEL_V  0x1
+#define GPIO_SIG45_IN_SEL_S  7
+/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC45_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC45_IN_INV_SEL_V  0x1
+#define GPIO_FUNC45_IN_INV_SEL_S  6
+/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC45_IN_SEL  0x0000003F
+#define GPIO_FUNC45_IN_SEL_M  ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S))
+#define GPIO_FUNC45_IN_SEL_V  0x3F
+#define GPIO_FUNC45_IN_SEL_S  0
+
+#define GPIO_FUNC46_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x20C)
+/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG46_IN_SEL  (BIT(7))
+#define GPIO_SIG46_IN_SEL_M  (BIT(7))
+#define GPIO_SIG46_IN_SEL_V  0x1
+#define GPIO_SIG46_IN_SEL_S  7
+/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC46_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC46_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC46_IN_INV_SEL_V  0x1
+#define GPIO_FUNC46_IN_INV_SEL_S  6
+/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC46_IN_SEL  0x0000003F
+#define GPIO_FUNC46_IN_SEL_M  ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S))
+#define GPIO_FUNC46_IN_SEL_V  0x3F
+#define GPIO_FUNC46_IN_SEL_S  0
+
+#define GPIO_FUNC47_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x210)
+/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG47_IN_SEL  (BIT(7))
+#define GPIO_SIG47_IN_SEL_M  (BIT(7))
+#define GPIO_SIG47_IN_SEL_V  0x1
+#define GPIO_SIG47_IN_SEL_S  7
+/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC47_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC47_IN_INV_SEL_V  0x1
+#define GPIO_FUNC47_IN_INV_SEL_S  6
+/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC47_IN_SEL  0x0000003F
+#define GPIO_FUNC47_IN_SEL_M  ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S))
+#define GPIO_FUNC47_IN_SEL_V  0x3F
+#define GPIO_FUNC47_IN_SEL_S  0
+
+#define GPIO_FUNC48_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x214)
+/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG48_IN_SEL  (BIT(7))
+#define GPIO_SIG48_IN_SEL_M  (BIT(7))
+#define GPIO_SIG48_IN_SEL_V  0x1
+#define GPIO_SIG48_IN_SEL_S  7
+/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC48_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC48_IN_INV_SEL_V  0x1
+#define GPIO_FUNC48_IN_INV_SEL_S  6
+/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC48_IN_SEL  0x0000003F
+#define GPIO_FUNC48_IN_SEL_M  ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S))
+#define GPIO_FUNC48_IN_SEL_V  0x3F
+#define GPIO_FUNC48_IN_SEL_S  0
+
+#define GPIO_FUNC49_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x218)
+/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG49_IN_SEL  (BIT(7))
+#define GPIO_SIG49_IN_SEL_M  (BIT(7))
+#define GPIO_SIG49_IN_SEL_V  0x1
+#define GPIO_SIG49_IN_SEL_S  7
+/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC49_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC49_IN_INV_SEL_V  0x1
+#define GPIO_FUNC49_IN_INV_SEL_S  6
+/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC49_IN_SEL  0x0000003F
+#define GPIO_FUNC49_IN_SEL_M  ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S))
+#define GPIO_FUNC49_IN_SEL_V  0x3F
+#define GPIO_FUNC49_IN_SEL_S  0
+
+#define GPIO_FUNC50_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x21C)
+/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG50_IN_SEL  (BIT(7))
+#define GPIO_SIG50_IN_SEL_M  (BIT(7))
+#define GPIO_SIG50_IN_SEL_V  0x1
+#define GPIO_SIG50_IN_SEL_S  7
+/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC50_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC50_IN_INV_SEL_V  0x1
+#define GPIO_FUNC50_IN_INV_SEL_S  6
+/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC50_IN_SEL  0x0000003F
+#define GPIO_FUNC50_IN_SEL_M  ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S))
+#define GPIO_FUNC50_IN_SEL_V  0x3F
+#define GPIO_FUNC50_IN_SEL_S  0
+
+#define GPIO_FUNC51_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x220)
+/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG51_IN_SEL  (BIT(7))
+#define GPIO_SIG51_IN_SEL_M  (BIT(7))
+#define GPIO_SIG51_IN_SEL_V  0x1
+#define GPIO_SIG51_IN_SEL_S  7
+/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC51_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC51_IN_INV_SEL_V  0x1
+#define GPIO_FUNC51_IN_INV_SEL_S  6
+/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC51_IN_SEL  0x0000003F
+#define GPIO_FUNC51_IN_SEL_M  ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S))
+#define GPIO_FUNC51_IN_SEL_V  0x3F
+#define GPIO_FUNC51_IN_SEL_S  0
+
+#define GPIO_FUNC52_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x224)
+/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG52_IN_SEL  (BIT(7))
+#define GPIO_SIG52_IN_SEL_M  (BIT(7))
+#define GPIO_SIG52_IN_SEL_V  0x1
+#define GPIO_SIG52_IN_SEL_S  7
+/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC52_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC52_IN_INV_SEL_V  0x1
+#define GPIO_FUNC52_IN_INV_SEL_S  6
+/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC52_IN_SEL  0x0000003F
+#define GPIO_FUNC52_IN_SEL_M  ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S))
+#define GPIO_FUNC52_IN_SEL_V  0x3F
+#define GPIO_FUNC52_IN_SEL_S  0
+
+#define GPIO_FUNC53_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x228)
+/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG53_IN_SEL  (BIT(7))
+#define GPIO_SIG53_IN_SEL_M  (BIT(7))
+#define GPIO_SIG53_IN_SEL_V  0x1
+#define GPIO_SIG53_IN_SEL_S  7
+/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC53_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC53_IN_INV_SEL_V  0x1
+#define GPIO_FUNC53_IN_INV_SEL_S  6
+/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC53_IN_SEL  0x0000003F
+#define GPIO_FUNC53_IN_SEL_M  ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S))
+#define GPIO_FUNC53_IN_SEL_V  0x3F
+#define GPIO_FUNC53_IN_SEL_S  0
+
+#define GPIO_FUNC54_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x22C)
+/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG54_IN_SEL  (BIT(7))
+#define GPIO_SIG54_IN_SEL_M  (BIT(7))
+#define GPIO_SIG54_IN_SEL_V  0x1
+#define GPIO_SIG54_IN_SEL_S  7
+/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC54_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC54_IN_INV_SEL_V  0x1
+#define GPIO_FUNC54_IN_INV_SEL_S  6
+/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC54_IN_SEL  0x0000003F
+#define GPIO_FUNC54_IN_SEL_M  ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S))
+#define GPIO_FUNC54_IN_SEL_V  0x3F
+#define GPIO_FUNC54_IN_SEL_S  0
+
+#define GPIO_FUNC55_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x230)
+/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG55_IN_SEL  (BIT(7))
+#define GPIO_SIG55_IN_SEL_M  (BIT(7))
+#define GPIO_SIG55_IN_SEL_V  0x1
+#define GPIO_SIG55_IN_SEL_S  7
+/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC55_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC55_IN_INV_SEL_V  0x1
+#define GPIO_FUNC55_IN_INV_SEL_S  6
+/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC55_IN_SEL  0x0000003F
+#define GPIO_FUNC55_IN_SEL_M  ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S))
+#define GPIO_FUNC55_IN_SEL_V  0x3F
+#define GPIO_FUNC55_IN_SEL_S  0
+
+#define GPIO_FUNC56_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x234)
+/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG56_IN_SEL  (BIT(7))
+#define GPIO_SIG56_IN_SEL_M  (BIT(7))
+#define GPIO_SIG56_IN_SEL_V  0x1
+#define GPIO_SIG56_IN_SEL_S  7
+/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC56_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC56_IN_INV_SEL_V  0x1
+#define GPIO_FUNC56_IN_INV_SEL_S  6
+/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC56_IN_SEL  0x0000003F
+#define GPIO_FUNC56_IN_SEL_M  ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S))
+#define GPIO_FUNC56_IN_SEL_V  0x3F
+#define GPIO_FUNC56_IN_SEL_S  0
+
+#define GPIO_FUNC57_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x238)
+/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG57_IN_SEL  (BIT(7))
+#define GPIO_SIG57_IN_SEL_M  (BIT(7))
+#define GPIO_SIG57_IN_SEL_V  0x1
+#define GPIO_SIG57_IN_SEL_S  7
+/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC57_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC57_IN_INV_SEL_V  0x1
+#define GPIO_FUNC57_IN_INV_SEL_S  6
+/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC57_IN_SEL  0x0000003F
+#define GPIO_FUNC57_IN_SEL_M  ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S))
+#define GPIO_FUNC57_IN_SEL_V  0x3F
+#define GPIO_FUNC57_IN_SEL_S  0
+
+#define GPIO_FUNC58_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x23C)
+/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG58_IN_SEL  (BIT(7))
+#define GPIO_SIG58_IN_SEL_M  (BIT(7))
+#define GPIO_SIG58_IN_SEL_V  0x1
+#define GPIO_SIG58_IN_SEL_S  7
+/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC58_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC58_IN_INV_SEL_V  0x1
+#define GPIO_FUNC58_IN_INV_SEL_S  6
+/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC58_IN_SEL  0x0000003F
+#define GPIO_FUNC58_IN_SEL_M  ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S))
+#define GPIO_FUNC58_IN_SEL_V  0x3F
+#define GPIO_FUNC58_IN_SEL_S  0
+
+#define GPIO_FUNC59_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x240)
+/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG59_IN_SEL  (BIT(7))
+#define GPIO_SIG59_IN_SEL_M  (BIT(7))
+#define GPIO_SIG59_IN_SEL_V  0x1
+#define GPIO_SIG59_IN_SEL_S  7
+/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC59_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC59_IN_INV_SEL_V  0x1
+#define GPIO_FUNC59_IN_INV_SEL_S  6
+/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC59_IN_SEL  0x0000003F
+#define GPIO_FUNC59_IN_SEL_M  ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S))
+#define GPIO_FUNC59_IN_SEL_V  0x3F
+#define GPIO_FUNC59_IN_SEL_S  0
+
+#define GPIO_FUNC60_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x244)
+/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG60_IN_SEL  (BIT(7))
+#define GPIO_SIG60_IN_SEL_M  (BIT(7))
+#define GPIO_SIG60_IN_SEL_V  0x1
+#define GPIO_SIG60_IN_SEL_S  7
+/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC60_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC60_IN_INV_SEL_V  0x1
+#define GPIO_FUNC60_IN_INV_SEL_S  6
+/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC60_IN_SEL  0x0000003F
+#define GPIO_FUNC60_IN_SEL_M  ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S))
+#define GPIO_FUNC60_IN_SEL_V  0x3F
+#define GPIO_FUNC60_IN_SEL_S  0
+
+#define GPIO_FUNC61_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x248)
+/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG61_IN_SEL  (BIT(7))
+#define GPIO_SIG61_IN_SEL_M  (BIT(7))
+#define GPIO_SIG61_IN_SEL_V  0x1
+#define GPIO_SIG61_IN_SEL_S  7
+/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC61_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC61_IN_INV_SEL_V  0x1
+#define GPIO_FUNC61_IN_INV_SEL_S  6
+/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC61_IN_SEL  0x0000003F
+#define GPIO_FUNC61_IN_SEL_M  ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S))
+#define GPIO_FUNC61_IN_SEL_V  0x3F
+#define GPIO_FUNC61_IN_SEL_S  0
+
+#define GPIO_FUNC62_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x24C)
+/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG62_IN_SEL  (BIT(7))
+#define GPIO_SIG62_IN_SEL_M  (BIT(7))
+#define GPIO_SIG62_IN_SEL_V  0x1
+#define GPIO_SIG62_IN_SEL_S  7
+/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC62_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC62_IN_INV_SEL_V  0x1
+#define GPIO_FUNC62_IN_INV_SEL_S  6
+/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC62_IN_SEL  0x0000003F
+#define GPIO_FUNC62_IN_SEL_M  ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S))
+#define GPIO_FUNC62_IN_SEL_V  0x3F
+#define GPIO_FUNC62_IN_SEL_S  0
+
+#define GPIO_FUNC63_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x250)
+/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG63_IN_SEL  (BIT(7))
+#define GPIO_SIG63_IN_SEL_M  (BIT(7))
+#define GPIO_SIG63_IN_SEL_V  0x1
+#define GPIO_SIG63_IN_SEL_S  7
+/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC63_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC63_IN_INV_SEL_V  0x1
+#define GPIO_FUNC63_IN_INV_SEL_S  6
+/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC63_IN_SEL  0x0000003F
+#define GPIO_FUNC63_IN_SEL_M  ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S))
+#define GPIO_FUNC63_IN_SEL_V  0x3F
+#define GPIO_FUNC63_IN_SEL_S  0
+
+#define GPIO_FUNC64_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x254)
+/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG64_IN_SEL  (BIT(7))
+#define GPIO_SIG64_IN_SEL_M  (BIT(7))
+#define GPIO_SIG64_IN_SEL_V  0x1
+#define GPIO_SIG64_IN_SEL_S  7
+/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC64_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC64_IN_INV_SEL_V  0x1
+#define GPIO_FUNC64_IN_INV_SEL_S  6
+/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC64_IN_SEL  0x0000003F
+#define GPIO_FUNC64_IN_SEL_M  ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S))
+#define GPIO_FUNC64_IN_SEL_V  0x3F
+#define GPIO_FUNC64_IN_SEL_S  0
+
+#define GPIO_FUNC65_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x258)
+/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG65_IN_SEL  (BIT(7))
+#define GPIO_SIG65_IN_SEL_M  (BIT(7))
+#define GPIO_SIG65_IN_SEL_V  0x1
+#define GPIO_SIG65_IN_SEL_S  7
+/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC65_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC65_IN_INV_SEL_V  0x1
+#define GPIO_FUNC65_IN_INV_SEL_S  6
+/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC65_IN_SEL  0x0000003F
+#define GPIO_FUNC65_IN_SEL_M  ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S))
+#define GPIO_FUNC65_IN_SEL_V  0x3F
+#define GPIO_FUNC65_IN_SEL_S  0
+
+#define GPIO_FUNC66_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x25C)
+/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG66_IN_SEL  (BIT(7))
+#define GPIO_SIG66_IN_SEL_M  (BIT(7))
+#define GPIO_SIG66_IN_SEL_V  0x1
+#define GPIO_SIG66_IN_SEL_S  7
+/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC66_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC66_IN_INV_SEL_V  0x1
+#define GPIO_FUNC66_IN_INV_SEL_S  6
+/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC66_IN_SEL  0x0000003F
+#define GPIO_FUNC66_IN_SEL_M  ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S))
+#define GPIO_FUNC66_IN_SEL_V  0x3F
+#define GPIO_FUNC66_IN_SEL_S  0
+
+#define GPIO_FUNC67_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x260)
+/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG67_IN_SEL  (BIT(7))
+#define GPIO_SIG67_IN_SEL_M  (BIT(7))
+#define GPIO_SIG67_IN_SEL_V  0x1
+#define GPIO_SIG67_IN_SEL_S  7
+/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC67_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC67_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC67_IN_INV_SEL_V  0x1
+#define GPIO_FUNC67_IN_INV_SEL_S  6
+/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC67_IN_SEL  0x0000003F
+#define GPIO_FUNC67_IN_SEL_M  ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S))
+#define GPIO_FUNC67_IN_SEL_V  0x3F
+#define GPIO_FUNC67_IN_SEL_S  0
+
+#define GPIO_FUNC68_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x264)
+/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG68_IN_SEL  (BIT(7))
+#define GPIO_SIG68_IN_SEL_M  (BIT(7))
+#define GPIO_SIG68_IN_SEL_V  0x1
+#define GPIO_SIG68_IN_SEL_S  7
+/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC68_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC68_IN_INV_SEL_V  0x1
+#define GPIO_FUNC68_IN_INV_SEL_S  6
+/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC68_IN_SEL  0x0000003F
+#define GPIO_FUNC68_IN_SEL_M  ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S))
+#define GPIO_FUNC68_IN_SEL_V  0x3F
+#define GPIO_FUNC68_IN_SEL_S  0
+
+#define GPIO_FUNC69_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x268)
+/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG69_IN_SEL  (BIT(7))
+#define GPIO_SIG69_IN_SEL_M  (BIT(7))
+#define GPIO_SIG69_IN_SEL_V  0x1
+#define GPIO_SIG69_IN_SEL_S  7
+/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC69_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC69_IN_INV_SEL_V  0x1
+#define GPIO_FUNC69_IN_INV_SEL_S  6
+/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC69_IN_SEL  0x0000003F
+#define GPIO_FUNC69_IN_SEL_M  ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S))
+#define GPIO_FUNC69_IN_SEL_V  0x3F
+#define GPIO_FUNC69_IN_SEL_S  0
+
+#define GPIO_FUNC70_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x26C)
+/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG70_IN_SEL  (BIT(7))
+#define GPIO_SIG70_IN_SEL_M  (BIT(7))
+#define GPIO_SIG70_IN_SEL_V  0x1
+#define GPIO_SIG70_IN_SEL_S  7
+/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC70_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC70_IN_INV_SEL_V  0x1
+#define GPIO_FUNC70_IN_INV_SEL_S  6
+/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC70_IN_SEL  0x0000003F
+#define GPIO_FUNC70_IN_SEL_M  ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S))
+#define GPIO_FUNC70_IN_SEL_V  0x3F
+#define GPIO_FUNC70_IN_SEL_S  0
+
+#define GPIO_FUNC71_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x270)
+/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG71_IN_SEL  (BIT(7))
+#define GPIO_SIG71_IN_SEL_M  (BIT(7))
+#define GPIO_SIG71_IN_SEL_V  0x1
+#define GPIO_SIG71_IN_SEL_S  7
+/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC71_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC71_IN_INV_SEL_V  0x1
+#define GPIO_FUNC71_IN_INV_SEL_S  6
+/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC71_IN_SEL  0x0000003F
+#define GPIO_FUNC71_IN_SEL_M  ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S))
+#define GPIO_FUNC71_IN_SEL_V  0x3F
+#define GPIO_FUNC71_IN_SEL_S  0
+
+#define GPIO_FUNC72_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x274)
+/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG72_IN_SEL  (BIT(7))
+#define GPIO_SIG72_IN_SEL_M  (BIT(7))
+#define GPIO_SIG72_IN_SEL_V  0x1
+#define GPIO_SIG72_IN_SEL_S  7
+/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC72_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC72_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC72_IN_INV_SEL_V  0x1
+#define GPIO_FUNC72_IN_INV_SEL_S  6
+/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC72_IN_SEL  0x0000003F
+#define GPIO_FUNC72_IN_SEL_M  ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S))
+#define GPIO_FUNC72_IN_SEL_V  0x3F
+#define GPIO_FUNC72_IN_SEL_S  0
+
+#define GPIO_FUNC73_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x278)
+/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG73_IN_SEL  (BIT(7))
+#define GPIO_SIG73_IN_SEL_M  (BIT(7))
+#define GPIO_SIG73_IN_SEL_V  0x1
+#define GPIO_SIG73_IN_SEL_S  7
+/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC73_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC73_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC73_IN_INV_SEL_V  0x1
+#define GPIO_FUNC73_IN_INV_SEL_S  6
+/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC73_IN_SEL  0x0000003F
+#define GPIO_FUNC73_IN_SEL_M  ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S))
+#define GPIO_FUNC73_IN_SEL_V  0x3F
+#define GPIO_FUNC73_IN_SEL_S  0
+
+#define GPIO_FUNC74_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x27C)
+/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG74_IN_SEL  (BIT(7))
+#define GPIO_SIG74_IN_SEL_M  (BIT(7))
+#define GPIO_SIG74_IN_SEL_V  0x1
+#define GPIO_SIG74_IN_SEL_S  7
+/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC74_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC74_IN_INV_SEL_V  0x1
+#define GPIO_FUNC74_IN_INV_SEL_S  6
+/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC74_IN_SEL  0x0000003F
+#define GPIO_FUNC74_IN_SEL_M  ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S))
+#define GPIO_FUNC74_IN_SEL_V  0x3F
+#define GPIO_FUNC74_IN_SEL_S  0
+
+#define GPIO_FUNC75_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x280)
+/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG75_IN_SEL  (BIT(7))
+#define GPIO_SIG75_IN_SEL_M  (BIT(7))
+#define GPIO_SIG75_IN_SEL_V  0x1
+#define GPIO_SIG75_IN_SEL_S  7
+/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC75_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC75_IN_INV_SEL_V  0x1
+#define GPIO_FUNC75_IN_INV_SEL_S  6
+/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC75_IN_SEL  0x0000003F
+#define GPIO_FUNC75_IN_SEL_M  ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S))
+#define GPIO_FUNC75_IN_SEL_V  0x3F
+#define GPIO_FUNC75_IN_SEL_S  0
+
+#define GPIO_FUNC76_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x284)
+/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG76_IN_SEL  (BIT(7))
+#define GPIO_SIG76_IN_SEL_M  (BIT(7))
+#define GPIO_SIG76_IN_SEL_V  0x1
+#define GPIO_SIG76_IN_SEL_S  7
+/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC76_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC76_IN_INV_SEL_V  0x1
+#define GPIO_FUNC76_IN_INV_SEL_S  6
+/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC76_IN_SEL  0x0000003F
+#define GPIO_FUNC76_IN_SEL_M  ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S))
+#define GPIO_FUNC76_IN_SEL_V  0x3F
+#define GPIO_FUNC76_IN_SEL_S  0
+
+#define GPIO_FUNC77_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x288)
+/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG77_IN_SEL  (BIT(7))
+#define GPIO_SIG77_IN_SEL_M  (BIT(7))
+#define GPIO_SIG77_IN_SEL_V  0x1
+#define GPIO_SIG77_IN_SEL_S  7
+/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC77_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC77_IN_INV_SEL_V  0x1
+#define GPIO_FUNC77_IN_INV_SEL_S  6
+/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC77_IN_SEL  0x0000003F
+#define GPIO_FUNC77_IN_SEL_M  ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S))
+#define GPIO_FUNC77_IN_SEL_V  0x3F
+#define GPIO_FUNC77_IN_SEL_S  0
+
+#define GPIO_FUNC78_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x28C)
+/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG78_IN_SEL  (BIT(7))
+#define GPIO_SIG78_IN_SEL_M  (BIT(7))
+#define GPIO_SIG78_IN_SEL_V  0x1
+#define GPIO_SIG78_IN_SEL_S  7
+/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC78_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC78_IN_INV_SEL_V  0x1
+#define GPIO_FUNC78_IN_INV_SEL_S  6
+/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC78_IN_SEL  0x0000003F
+#define GPIO_FUNC78_IN_SEL_M  ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S))
+#define GPIO_FUNC78_IN_SEL_V  0x3F
+#define GPIO_FUNC78_IN_SEL_S  0
+
+#define GPIO_FUNC79_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x290)
+/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG79_IN_SEL  (BIT(7))
+#define GPIO_SIG79_IN_SEL_M  (BIT(7))
+#define GPIO_SIG79_IN_SEL_V  0x1
+#define GPIO_SIG79_IN_SEL_S  7
+/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC79_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC79_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC79_IN_INV_SEL_V  0x1
+#define GPIO_FUNC79_IN_INV_SEL_S  6
+/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC79_IN_SEL  0x0000003F
+#define GPIO_FUNC79_IN_SEL_M  ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S))
+#define GPIO_FUNC79_IN_SEL_V  0x3F
+#define GPIO_FUNC79_IN_SEL_S  0
+
+#define GPIO_FUNC80_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x294)
+/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG80_IN_SEL  (BIT(7))
+#define GPIO_SIG80_IN_SEL_M  (BIT(7))
+#define GPIO_SIG80_IN_SEL_V  0x1
+#define GPIO_SIG80_IN_SEL_S  7
+/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC80_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC80_IN_INV_SEL_V  0x1
+#define GPIO_FUNC80_IN_INV_SEL_S  6
+/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC80_IN_SEL  0x0000003F
+#define GPIO_FUNC80_IN_SEL_M  ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S))
+#define GPIO_FUNC80_IN_SEL_V  0x3F
+#define GPIO_FUNC80_IN_SEL_S  0
+
+#define GPIO_FUNC81_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x298)
+/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG81_IN_SEL  (BIT(7))
+#define GPIO_SIG81_IN_SEL_M  (BIT(7))
+#define GPIO_SIG81_IN_SEL_V  0x1
+#define GPIO_SIG81_IN_SEL_S  7
+/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC81_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC81_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC81_IN_INV_SEL_V  0x1
+#define GPIO_FUNC81_IN_INV_SEL_S  6
+/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC81_IN_SEL  0x0000003F
+#define GPIO_FUNC81_IN_SEL_M  ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S))
+#define GPIO_FUNC81_IN_SEL_V  0x3F
+#define GPIO_FUNC81_IN_SEL_S  0
+
+#define GPIO_FUNC82_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x29C)
+/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG82_IN_SEL  (BIT(7))
+#define GPIO_SIG82_IN_SEL_M  (BIT(7))
+#define GPIO_SIG82_IN_SEL_V  0x1
+#define GPIO_SIG82_IN_SEL_S  7
+/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC82_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC82_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC82_IN_INV_SEL_V  0x1
+#define GPIO_FUNC82_IN_INV_SEL_S  6
+/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC82_IN_SEL  0x0000003F
+#define GPIO_FUNC82_IN_SEL_M  ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S))
+#define GPIO_FUNC82_IN_SEL_V  0x3F
+#define GPIO_FUNC82_IN_SEL_S  0
+
+#define GPIO_FUNC83_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A0)
+/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG83_IN_SEL  (BIT(7))
+#define GPIO_SIG83_IN_SEL_M  (BIT(7))
+#define GPIO_SIG83_IN_SEL_V  0x1
+#define GPIO_SIG83_IN_SEL_S  7
+/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC83_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC83_IN_INV_SEL_V  0x1
+#define GPIO_FUNC83_IN_INV_SEL_S  6
+/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC83_IN_SEL  0x0000003F
+#define GPIO_FUNC83_IN_SEL_M  ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S))
+#define GPIO_FUNC83_IN_SEL_V  0x3F
+#define GPIO_FUNC83_IN_SEL_S  0
+
+#define GPIO_FUNC84_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A4)
+/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG84_IN_SEL  (BIT(7))
+#define GPIO_SIG84_IN_SEL_M  (BIT(7))
+#define GPIO_SIG84_IN_SEL_V  0x1
+#define GPIO_SIG84_IN_SEL_S  7
+/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC84_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC84_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC84_IN_INV_SEL_V  0x1
+#define GPIO_FUNC84_IN_INV_SEL_S  6
+/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC84_IN_SEL  0x0000003F
+#define GPIO_FUNC84_IN_SEL_M  ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S))
+#define GPIO_FUNC84_IN_SEL_V  0x3F
+#define GPIO_FUNC84_IN_SEL_S  0
+
+#define GPIO_FUNC85_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2A8)
+/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG85_IN_SEL  (BIT(7))
+#define GPIO_SIG85_IN_SEL_M  (BIT(7))
+#define GPIO_SIG85_IN_SEL_V  0x1
+#define GPIO_SIG85_IN_SEL_S  7
+/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC85_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC85_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC85_IN_INV_SEL_V  0x1
+#define GPIO_FUNC85_IN_INV_SEL_S  6
+/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC85_IN_SEL  0x0000003F
+#define GPIO_FUNC85_IN_SEL_M  ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S))
+#define GPIO_FUNC85_IN_SEL_V  0x3F
+#define GPIO_FUNC85_IN_SEL_S  0
+
+#define GPIO_FUNC86_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2AC)
+/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG86_IN_SEL  (BIT(7))
+#define GPIO_SIG86_IN_SEL_M  (BIT(7))
+#define GPIO_SIG86_IN_SEL_V  0x1
+#define GPIO_SIG86_IN_SEL_S  7
+/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC86_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC86_IN_INV_SEL_V  0x1
+#define GPIO_FUNC86_IN_INV_SEL_S  6
+/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC86_IN_SEL  0x0000003F
+#define GPIO_FUNC86_IN_SEL_M  ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S))
+#define GPIO_FUNC86_IN_SEL_V  0x3F
+#define GPIO_FUNC86_IN_SEL_S  0
+
+#define GPIO_FUNC87_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B0)
+/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG87_IN_SEL  (BIT(7))
+#define GPIO_SIG87_IN_SEL_M  (BIT(7))
+#define GPIO_SIG87_IN_SEL_V  0x1
+#define GPIO_SIG87_IN_SEL_S  7
+/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC87_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC87_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC87_IN_INV_SEL_V  0x1
+#define GPIO_FUNC87_IN_INV_SEL_S  6
+/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC87_IN_SEL  0x0000003F
+#define GPIO_FUNC87_IN_SEL_M  ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S))
+#define GPIO_FUNC87_IN_SEL_V  0x3F
+#define GPIO_FUNC87_IN_SEL_S  0
+
+#define GPIO_FUNC88_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B4)
+/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG88_IN_SEL  (BIT(7))
+#define GPIO_SIG88_IN_SEL_M  (BIT(7))
+#define GPIO_SIG88_IN_SEL_V  0x1
+#define GPIO_SIG88_IN_SEL_S  7
+/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC88_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC88_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC88_IN_INV_SEL_V  0x1
+#define GPIO_FUNC88_IN_INV_SEL_S  6
+/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC88_IN_SEL  0x0000003F
+#define GPIO_FUNC88_IN_SEL_M  ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S))
+#define GPIO_FUNC88_IN_SEL_V  0x3F
+#define GPIO_FUNC88_IN_SEL_S  0
+
+#define GPIO_FUNC89_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2B8)
+/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG89_IN_SEL  (BIT(7))
+#define GPIO_SIG89_IN_SEL_M  (BIT(7))
+#define GPIO_SIG89_IN_SEL_V  0x1
+#define GPIO_SIG89_IN_SEL_S  7
+/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC89_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC89_IN_INV_SEL_V  0x1
+#define GPIO_FUNC89_IN_INV_SEL_S  6
+/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC89_IN_SEL  0x0000003F
+#define GPIO_FUNC89_IN_SEL_M  ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S))
+#define GPIO_FUNC89_IN_SEL_V  0x3F
+#define GPIO_FUNC89_IN_SEL_S  0
+
+#define GPIO_FUNC90_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2BC)
+/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG90_IN_SEL  (BIT(7))
+#define GPIO_SIG90_IN_SEL_M  (BIT(7))
+#define GPIO_SIG90_IN_SEL_V  0x1
+#define GPIO_SIG90_IN_SEL_S  7
+/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC90_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC90_IN_INV_SEL_V  0x1
+#define GPIO_FUNC90_IN_INV_SEL_S  6
+/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC90_IN_SEL  0x0000003F
+#define GPIO_FUNC90_IN_SEL_M  ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S))
+#define GPIO_FUNC90_IN_SEL_V  0x3F
+#define GPIO_FUNC90_IN_SEL_S  0
+
+#define GPIO_FUNC91_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C0)
+/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG91_IN_SEL  (BIT(7))
+#define GPIO_SIG91_IN_SEL_M  (BIT(7))
+#define GPIO_SIG91_IN_SEL_V  0x1
+#define GPIO_SIG91_IN_SEL_S  7
+/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC91_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC91_IN_INV_SEL_V  0x1
+#define GPIO_FUNC91_IN_INV_SEL_S  6
+/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC91_IN_SEL  0x0000003F
+#define GPIO_FUNC91_IN_SEL_M  ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S))
+#define GPIO_FUNC91_IN_SEL_V  0x3F
+#define GPIO_FUNC91_IN_SEL_S  0
+
+#define GPIO_FUNC92_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C4)
+/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG92_IN_SEL  (BIT(7))
+#define GPIO_SIG92_IN_SEL_M  (BIT(7))
+#define GPIO_SIG92_IN_SEL_V  0x1
+#define GPIO_SIG92_IN_SEL_S  7
+/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC92_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC92_IN_INV_SEL_V  0x1
+#define GPIO_FUNC92_IN_INV_SEL_S  6
+/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC92_IN_SEL  0x0000003F
+#define GPIO_FUNC92_IN_SEL_M  ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S))
+#define GPIO_FUNC92_IN_SEL_V  0x3F
+#define GPIO_FUNC92_IN_SEL_S  0
+
+#define GPIO_FUNC93_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2C8)
+/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG93_IN_SEL  (BIT(7))
+#define GPIO_SIG93_IN_SEL_M  (BIT(7))
+#define GPIO_SIG93_IN_SEL_V  0x1
+#define GPIO_SIG93_IN_SEL_S  7
+/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC93_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC93_IN_INV_SEL_V  0x1
+#define GPIO_FUNC93_IN_INV_SEL_S  6
+/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC93_IN_SEL  0x0000003F
+#define GPIO_FUNC93_IN_SEL_M  ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S))
+#define GPIO_FUNC93_IN_SEL_V  0x3F
+#define GPIO_FUNC93_IN_SEL_S  0
+
+#define GPIO_FUNC94_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2CC)
+/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG94_IN_SEL  (BIT(7))
+#define GPIO_SIG94_IN_SEL_M  (BIT(7))
+#define GPIO_SIG94_IN_SEL_V  0x1
+#define GPIO_SIG94_IN_SEL_S  7
+/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC94_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC94_IN_INV_SEL_V  0x1
+#define GPIO_FUNC94_IN_INV_SEL_S  6
+/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC94_IN_SEL  0x0000003F
+#define GPIO_FUNC94_IN_SEL_M  ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S))
+#define GPIO_FUNC94_IN_SEL_V  0x3F
+#define GPIO_FUNC94_IN_SEL_S  0
+
+#define GPIO_FUNC95_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D0)
+/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG95_IN_SEL  (BIT(7))
+#define GPIO_SIG95_IN_SEL_M  (BIT(7))
+#define GPIO_SIG95_IN_SEL_V  0x1
+#define GPIO_SIG95_IN_SEL_S  7
+/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC95_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC95_IN_INV_SEL_V  0x1
+#define GPIO_FUNC95_IN_INV_SEL_S  6
+/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC95_IN_SEL  0x0000003F
+#define GPIO_FUNC95_IN_SEL_M  ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S))
+#define GPIO_FUNC95_IN_SEL_V  0x3F
+#define GPIO_FUNC95_IN_SEL_S  0
+
+#define GPIO_FUNC96_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D4)
+/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG96_IN_SEL  (BIT(7))
+#define GPIO_SIG96_IN_SEL_M  (BIT(7))
+#define GPIO_SIG96_IN_SEL_V  0x1
+#define GPIO_SIG96_IN_SEL_S  7
+/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC96_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC96_IN_INV_SEL_V  0x1
+#define GPIO_FUNC96_IN_INV_SEL_S  6
+/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC96_IN_SEL  0x0000003F
+#define GPIO_FUNC96_IN_SEL_M  ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S))
+#define GPIO_FUNC96_IN_SEL_V  0x3F
+#define GPIO_FUNC96_IN_SEL_S  0
+
+#define GPIO_FUNC97_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2D8)
+/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG97_IN_SEL  (BIT(7))
+#define GPIO_SIG97_IN_SEL_M  (BIT(7))
+#define GPIO_SIG97_IN_SEL_V  0x1
+#define GPIO_SIG97_IN_SEL_S  7
+/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC97_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC97_IN_INV_SEL_V  0x1
+#define GPIO_FUNC97_IN_INV_SEL_S  6
+/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC97_IN_SEL  0x0000003F
+#define GPIO_FUNC97_IN_SEL_M  ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S))
+#define GPIO_FUNC97_IN_SEL_V  0x3F
+#define GPIO_FUNC97_IN_SEL_S  0
+
+#define GPIO_FUNC98_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2DC)
+/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG98_IN_SEL  (BIT(7))
+#define GPIO_SIG98_IN_SEL_M  (BIT(7))
+#define GPIO_SIG98_IN_SEL_V  0x1
+#define GPIO_SIG98_IN_SEL_S  7
+/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC98_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC98_IN_INV_SEL_V  0x1
+#define GPIO_FUNC98_IN_INV_SEL_S  6
+/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC98_IN_SEL  0x0000003F
+#define GPIO_FUNC98_IN_SEL_M  ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S))
+#define GPIO_FUNC98_IN_SEL_V  0x3F
+#define GPIO_FUNC98_IN_SEL_S  0
+
+#define GPIO_FUNC99_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E0)
+/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG99_IN_SEL  (BIT(7))
+#define GPIO_SIG99_IN_SEL_M  (BIT(7))
+#define GPIO_SIG99_IN_SEL_V  0x1
+#define GPIO_SIG99_IN_SEL_S  7
+/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC99_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC99_IN_INV_SEL_V  0x1
+#define GPIO_FUNC99_IN_INV_SEL_S  6
+/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC99_IN_SEL  0x0000003F
+#define GPIO_FUNC99_IN_SEL_M  ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S))
+#define GPIO_FUNC99_IN_SEL_V  0x3F
+#define GPIO_FUNC99_IN_SEL_S  0
+
+#define GPIO_FUNC100_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E4)
+/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG100_IN_SEL  (BIT(7))
+#define GPIO_SIG100_IN_SEL_M  (BIT(7))
+#define GPIO_SIG100_IN_SEL_V  0x1
+#define GPIO_SIG100_IN_SEL_S  7
+/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC100_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC100_IN_INV_SEL_V  0x1
+#define GPIO_FUNC100_IN_INV_SEL_S  6
+/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC100_IN_SEL  0x0000003F
+#define GPIO_FUNC100_IN_SEL_M  ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S))
+#define GPIO_FUNC100_IN_SEL_V  0x3F
+#define GPIO_FUNC100_IN_SEL_S  0
+
+#define GPIO_FUNC101_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2E8)
+/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG101_IN_SEL  (BIT(7))
+#define GPIO_SIG101_IN_SEL_M  (BIT(7))
+#define GPIO_SIG101_IN_SEL_V  0x1
+#define GPIO_SIG101_IN_SEL_S  7
+/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC101_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC101_IN_INV_SEL_V  0x1
+#define GPIO_FUNC101_IN_INV_SEL_S  6
+/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC101_IN_SEL  0x0000003F
+#define GPIO_FUNC101_IN_SEL_M  ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S))
+#define GPIO_FUNC101_IN_SEL_V  0x3F
+#define GPIO_FUNC101_IN_SEL_S  0
+
+#define GPIO_FUNC102_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2EC)
+/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG102_IN_SEL  (BIT(7))
+#define GPIO_SIG102_IN_SEL_M  (BIT(7))
+#define GPIO_SIG102_IN_SEL_V  0x1
+#define GPIO_SIG102_IN_SEL_S  7
+/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC102_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC102_IN_INV_SEL_V  0x1
+#define GPIO_FUNC102_IN_INV_SEL_S  6
+/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC102_IN_SEL  0x0000003F
+#define GPIO_FUNC102_IN_SEL_M  ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S))
+#define GPIO_FUNC102_IN_SEL_V  0x3F
+#define GPIO_FUNC102_IN_SEL_S  0
+
+#define GPIO_FUNC103_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F0)
+/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG103_IN_SEL  (BIT(7))
+#define GPIO_SIG103_IN_SEL_M  (BIT(7))
+#define GPIO_SIG103_IN_SEL_V  0x1
+#define GPIO_SIG103_IN_SEL_S  7
+/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC103_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC103_IN_INV_SEL_V  0x1
+#define GPIO_FUNC103_IN_INV_SEL_S  6
+/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC103_IN_SEL  0x0000003F
+#define GPIO_FUNC103_IN_SEL_M  ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S))
+#define GPIO_FUNC103_IN_SEL_V  0x3F
+#define GPIO_FUNC103_IN_SEL_S  0
+
+#define GPIO_FUNC104_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F4)
+/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG104_IN_SEL  (BIT(7))
+#define GPIO_SIG104_IN_SEL_M  (BIT(7))
+#define GPIO_SIG104_IN_SEL_V  0x1
+#define GPIO_SIG104_IN_SEL_S  7
+/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC104_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC104_IN_INV_SEL_V  0x1
+#define GPIO_FUNC104_IN_INV_SEL_S  6
+/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC104_IN_SEL  0x0000003F
+#define GPIO_FUNC104_IN_SEL_M  ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S))
+#define GPIO_FUNC104_IN_SEL_V  0x3F
+#define GPIO_FUNC104_IN_SEL_S  0
+
+#define GPIO_FUNC105_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2F8)
+/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG105_IN_SEL  (BIT(7))
+#define GPIO_SIG105_IN_SEL_M  (BIT(7))
+#define GPIO_SIG105_IN_SEL_V  0x1
+#define GPIO_SIG105_IN_SEL_S  7
+/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC105_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC105_IN_INV_SEL_V  0x1
+#define GPIO_FUNC105_IN_INV_SEL_S  6
+/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC105_IN_SEL  0x0000003F
+#define GPIO_FUNC105_IN_SEL_M  ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S))
+#define GPIO_FUNC105_IN_SEL_V  0x3F
+#define GPIO_FUNC105_IN_SEL_S  0
+
+#define GPIO_FUNC106_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x2FC)
+/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG106_IN_SEL  (BIT(7))
+#define GPIO_SIG106_IN_SEL_M  (BIT(7))
+#define GPIO_SIG106_IN_SEL_V  0x1
+#define GPIO_SIG106_IN_SEL_S  7
+/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC106_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC106_IN_INV_SEL_V  0x1
+#define GPIO_FUNC106_IN_INV_SEL_S  6
+/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC106_IN_SEL  0x0000003F
+#define GPIO_FUNC106_IN_SEL_M  ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S))
+#define GPIO_FUNC106_IN_SEL_V  0x3F
+#define GPIO_FUNC106_IN_SEL_S  0
+
+#define GPIO_FUNC107_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x300)
+/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG107_IN_SEL  (BIT(7))
+#define GPIO_SIG107_IN_SEL_M  (BIT(7))
+#define GPIO_SIG107_IN_SEL_V  0x1
+#define GPIO_SIG107_IN_SEL_S  7
+/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC107_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC107_IN_INV_SEL_V  0x1
+#define GPIO_FUNC107_IN_INV_SEL_S  6
+/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC107_IN_SEL  0x0000003F
+#define GPIO_FUNC107_IN_SEL_M  ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S))
+#define GPIO_FUNC107_IN_SEL_V  0x3F
+#define GPIO_FUNC107_IN_SEL_S  0
+
+#define GPIO_FUNC108_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x304)
+/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG108_IN_SEL  (BIT(7))
+#define GPIO_SIG108_IN_SEL_M  (BIT(7))
+#define GPIO_SIG108_IN_SEL_V  0x1
+#define GPIO_SIG108_IN_SEL_S  7
+/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC108_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC108_IN_INV_SEL_V  0x1
+#define GPIO_FUNC108_IN_INV_SEL_S  6
+/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC108_IN_SEL  0x0000003F
+#define GPIO_FUNC108_IN_SEL_M  ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S))
+#define GPIO_FUNC108_IN_SEL_V  0x3F
+#define GPIO_FUNC108_IN_SEL_S  0
+
+#define GPIO_FUNC109_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x308)
+/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG109_IN_SEL  (BIT(7))
+#define GPIO_SIG109_IN_SEL_M  (BIT(7))
+#define GPIO_SIG109_IN_SEL_V  0x1
+#define GPIO_SIG109_IN_SEL_S  7
+/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC109_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC109_IN_INV_SEL_V  0x1
+#define GPIO_FUNC109_IN_INV_SEL_S  6
+/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC109_IN_SEL  0x0000003F
+#define GPIO_FUNC109_IN_SEL_M  ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S))
+#define GPIO_FUNC109_IN_SEL_V  0x3F
+#define GPIO_FUNC109_IN_SEL_S  0
+
+#define GPIO_FUNC110_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x30C)
+/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG110_IN_SEL  (BIT(7))
+#define GPIO_SIG110_IN_SEL_M  (BIT(7))
+#define GPIO_SIG110_IN_SEL_V  0x1
+#define GPIO_SIG110_IN_SEL_S  7
+/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC110_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC110_IN_INV_SEL_V  0x1
+#define GPIO_FUNC110_IN_INV_SEL_S  6
+/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC110_IN_SEL  0x0000003F
+#define GPIO_FUNC110_IN_SEL_M  ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S))
+#define GPIO_FUNC110_IN_SEL_V  0x3F
+#define GPIO_FUNC110_IN_SEL_S  0
+
+#define GPIO_FUNC111_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x310)
+/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG111_IN_SEL  (BIT(7))
+#define GPIO_SIG111_IN_SEL_M  (BIT(7))
+#define GPIO_SIG111_IN_SEL_V  0x1
+#define GPIO_SIG111_IN_SEL_S  7
+/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC111_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC111_IN_INV_SEL_V  0x1
+#define GPIO_FUNC111_IN_INV_SEL_S  6
+/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC111_IN_SEL  0x0000003F
+#define GPIO_FUNC111_IN_SEL_M  ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S))
+#define GPIO_FUNC111_IN_SEL_V  0x3F
+#define GPIO_FUNC111_IN_SEL_S  0
+
+#define GPIO_FUNC112_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x314)
+/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG112_IN_SEL  (BIT(7))
+#define GPIO_SIG112_IN_SEL_M  (BIT(7))
+#define GPIO_SIG112_IN_SEL_V  0x1
+#define GPIO_SIG112_IN_SEL_S  7
+/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC112_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC112_IN_INV_SEL_V  0x1
+#define GPIO_FUNC112_IN_INV_SEL_S  6
+/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC112_IN_SEL  0x0000003F
+#define GPIO_FUNC112_IN_SEL_M  ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S))
+#define GPIO_FUNC112_IN_SEL_V  0x3F
+#define GPIO_FUNC112_IN_SEL_S  0
+
+#define GPIO_FUNC113_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x318)
+/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG113_IN_SEL  (BIT(7))
+#define GPIO_SIG113_IN_SEL_M  (BIT(7))
+#define GPIO_SIG113_IN_SEL_V  0x1
+#define GPIO_SIG113_IN_SEL_S  7
+/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC113_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC113_IN_INV_SEL_V  0x1
+#define GPIO_FUNC113_IN_INV_SEL_S  6
+/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC113_IN_SEL  0x0000003F
+#define GPIO_FUNC113_IN_SEL_M  ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S))
+#define GPIO_FUNC113_IN_SEL_V  0x3F
+#define GPIO_FUNC113_IN_SEL_S  0
+
+#define GPIO_FUNC114_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x31C)
+/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG114_IN_SEL  (BIT(7))
+#define GPIO_SIG114_IN_SEL_M  (BIT(7))
+#define GPIO_SIG114_IN_SEL_V  0x1
+#define GPIO_SIG114_IN_SEL_S  7
+/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC114_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC114_IN_INV_SEL_V  0x1
+#define GPIO_FUNC114_IN_INV_SEL_S  6
+/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC114_IN_SEL  0x0000003F
+#define GPIO_FUNC114_IN_SEL_M  ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S))
+#define GPIO_FUNC114_IN_SEL_V  0x3F
+#define GPIO_FUNC114_IN_SEL_S  0
+
+#define GPIO_FUNC115_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x320)
+/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG115_IN_SEL  (BIT(7))
+#define GPIO_SIG115_IN_SEL_M  (BIT(7))
+#define GPIO_SIG115_IN_SEL_V  0x1
+#define GPIO_SIG115_IN_SEL_S  7
+/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC115_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC115_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC115_IN_INV_SEL_V  0x1
+#define GPIO_FUNC115_IN_INV_SEL_S  6
+/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC115_IN_SEL  0x0000003F
+#define GPIO_FUNC115_IN_SEL_M  ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S))
+#define GPIO_FUNC115_IN_SEL_V  0x3F
+#define GPIO_FUNC115_IN_SEL_S  0
+
+#define GPIO_FUNC116_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x324)
+/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG116_IN_SEL  (BIT(7))
+#define GPIO_SIG116_IN_SEL_M  (BIT(7))
+#define GPIO_SIG116_IN_SEL_V  0x1
+#define GPIO_SIG116_IN_SEL_S  7
+/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC116_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC116_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC116_IN_INV_SEL_V  0x1
+#define GPIO_FUNC116_IN_INV_SEL_S  6
+/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC116_IN_SEL  0x0000003F
+#define GPIO_FUNC116_IN_SEL_M  ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S))
+#define GPIO_FUNC116_IN_SEL_V  0x3F
+#define GPIO_FUNC116_IN_SEL_S  0
+
+#define GPIO_FUNC117_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x328)
+/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG117_IN_SEL  (BIT(7))
+#define GPIO_SIG117_IN_SEL_M  (BIT(7))
+#define GPIO_SIG117_IN_SEL_V  0x1
+#define GPIO_SIG117_IN_SEL_S  7
+/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC117_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC117_IN_INV_SEL_V  0x1
+#define GPIO_FUNC117_IN_INV_SEL_S  6
+/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC117_IN_SEL  0x0000003F
+#define GPIO_FUNC117_IN_SEL_M  ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S))
+#define GPIO_FUNC117_IN_SEL_V  0x3F
+#define GPIO_FUNC117_IN_SEL_S  0
+
+#define GPIO_FUNC118_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x32C)
+/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG118_IN_SEL  (BIT(7))
+#define GPIO_SIG118_IN_SEL_M  (BIT(7))
+#define GPIO_SIG118_IN_SEL_V  0x1
+#define GPIO_SIG118_IN_SEL_S  7
+/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC118_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC118_IN_INV_SEL_V  0x1
+#define GPIO_FUNC118_IN_INV_SEL_S  6
+/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC118_IN_SEL  0x0000003F
+#define GPIO_FUNC118_IN_SEL_M  ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S))
+#define GPIO_FUNC118_IN_SEL_V  0x3F
+#define GPIO_FUNC118_IN_SEL_S  0
+
+#define GPIO_FUNC119_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x330)
+/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG119_IN_SEL  (BIT(7))
+#define GPIO_SIG119_IN_SEL_M  (BIT(7))
+#define GPIO_SIG119_IN_SEL_V  0x1
+#define GPIO_SIG119_IN_SEL_S  7
+/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC119_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC119_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC119_IN_INV_SEL_V  0x1
+#define GPIO_FUNC119_IN_INV_SEL_S  6
+/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC119_IN_SEL  0x0000003F
+#define GPIO_FUNC119_IN_SEL_M  ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S))
+#define GPIO_FUNC119_IN_SEL_V  0x3F
+#define GPIO_FUNC119_IN_SEL_S  0
+
+#define GPIO_FUNC120_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x334)
+/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG120_IN_SEL  (BIT(7))
+#define GPIO_SIG120_IN_SEL_M  (BIT(7))
+#define GPIO_SIG120_IN_SEL_V  0x1
+#define GPIO_SIG120_IN_SEL_S  7
+/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC120_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC120_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC120_IN_INV_SEL_V  0x1
+#define GPIO_FUNC120_IN_INV_SEL_S  6
+/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC120_IN_SEL  0x0000003F
+#define GPIO_FUNC120_IN_SEL_M  ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S))
+#define GPIO_FUNC120_IN_SEL_V  0x3F
+#define GPIO_FUNC120_IN_SEL_S  0
+
+#define GPIO_FUNC121_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x338)
+/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG121_IN_SEL  (BIT(7))
+#define GPIO_SIG121_IN_SEL_M  (BIT(7))
+#define GPIO_SIG121_IN_SEL_V  0x1
+#define GPIO_SIG121_IN_SEL_S  7
+/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC121_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC121_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC121_IN_INV_SEL_V  0x1
+#define GPIO_FUNC121_IN_INV_SEL_S  6
+/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC121_IN_SEL  0x0000003F
+#define GPIO_FUNC121_IN_SEL_M  ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S))
+#define GPIO_FUNC121_IN_SEL_V  0x3F
+#define GPIO_FUNC121_IN_SEL_S  0
+
+#define GPIO_FUNC122_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x33C)
+/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG122_IN_SEL  (BIT(7))
+#define GPIO_SIG122_IN_SEL_M  (BIT(7))
+#define GPIO_SIG122_IN_SEL_V  0x1
+#define GPIO_SIG122_IN_SEL_S  7
+/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC122_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC122_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC122_IN_INV_SEL_V  0x1
+#define GPIO_FUNC122_IN_INV_SEL_S  6
+/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC122_IN_SEL  0x0000003F
+#define GPIO_FUNC122_IN_SEL_M  ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S))
+#define GPIO_FUNC122_IN_SEL_V  0x3F
+#define GPIO_FUNC122_IN_SEL_S  0
+
+#define GPIO_FUNC123_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x340)
+/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG123_IN_SEL  (BIT(7))
+#define GPIO_SIG123_IN_SEL_M  (BIT(7))
+#define GPIO_SIG123_IN_SEL_V  0x1
+#define GPIO_SIG123_IN_SEL_S  7
+/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC123_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC123_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC123_IN_INV_SEL_V  0x1
+#define GPIO_FUNC123_IN_INV_SEL_S  6
+/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC123_IN_SEL  0x0000003F
+#define GPIO_FUNC123_IN_SEL_M  ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S))
+#define GPIO_FUNC123_IN_SEL_V  0x3F
+#define GPIO_FUNC123_IN_SEL_S  0
+
+#define GPIO_FUNC124_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x344)
+/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG124_IN_SEL  (BIT(7))
+#define GPIO_SIG124_IN_SEL_M  (BIT(7))
+#define GPIO_SIG124_IN_SEL_V  0x1
+#define GPIO_SIG124_IN_SEL_S  7
+/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC124_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC124_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC124_IN_INV_SEL_V  0x1
+#define GPIO_FUNC124_IN_INV_SEL_S  6
+/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC124_IN_SEL  0x0000003F
+#define GPIO_FUNC124_IN_SEL_M  ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S))
+#define GPIO_FUNC124_IN_SEL_V  0x3F
+#define GPIO_FUNC124_IN_SEL_S  0
+
+#define GPIO_FUNC125_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x348)
+/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG125_IN_SEL  (BIT(7))
+#define GPIO_SIG125_IN_SEL_M  (BIT(7))
+#define GPIO_SIG125_IN_SEL_V  0x1
+#define GPIO_SIG125_IN_SEL_S  7
+/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC125_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC125_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC125_IN_INV_SEL_V  0x1
+#define GPIO_FUNC125_IN_INV_SEL_S  6
+/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC125_IN_SEL  0x0000003F
+#define GPIO_FUNC125_IN_SEL_M  ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S))
+#define GPIO_FUNC125_IN_SEL_V  0x3F
+#define GPIO_FUNC125_IN_SEL_S  0
+
+#define GPIO_FUNC126_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x34C)
+/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG126_IN_SEL  (BIT(7))
+#define GPIO_SIG126_IN_SEL_M  (BIT(7))
+#define GPIO_SIG126_IN_SEL_V  0x1
+#define GPIO_SIG126_IN_SEL_S  7
+/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC126_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC126_IN_INV_SEL_V  0x1
+#define GPIO_FUNC126_IN_INV_SEL_S  6
+/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC126_IN_SEL  0x0000003F
+#define GPIO_FUNC126_IN_SEL_M  ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S))
+#define GPIO_FUNC126_IN_SEL_V  0x3F
+#define GPIO_FUNC126_IN_SEL_S  0
+
+#define GPIO_FUNC127_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x350)
+/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG127_IN_SEL  (BIT(7))
+#define GPIO_SIG127_IN_SEL_M  (BIT(7))
+#define GPIO_SIG127_IN_SEL_V  0x1
+#define GPIO_SIG127_IN_SEL_S  7
+/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC127_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC127_IN_INV_SEL_V  0x1
+#define GPIO_FUNC127_IN_INV_SEL_S  6
+/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC127_IN_SEL  0x0000003F
+#define GPIO_FUNC127_IN_SEL_M  ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S))
+#define GPIO_FUNC127_IN_SEL_V  0x3F
+#define GPIO_FUNC127_IN_SEL_S  0
+
+#define GPIO_FUNC128_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x354)
+/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG128_IN_SEL  (BIT(7))
+#define GPIO_SIG128_IN_SEL_M  (BIT(7))
+#define GPIO_SIG128_IN_SEL_V  0x1
+#define GPIO_SIG128_IN_SEL_S  7
+/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC128_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC128_IN_INV_SEL_V  0x1
+#define GPIO_FUNC128_IN_INV_SEL_S  6
+/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC128_IN_SEL  0x0000003F
+#define GPIO_FUNC128_IN_SEL_M  ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S))
+#define GPIO_FUNC128_IN_SEL_V  0x3F
+#define GPIO_FUNC128_IN_SEL_S  0
+
+#define GPIO_FUNC129_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x358)
+/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG129_IN_SEL  (BIT(7))
+#define GPIO_SIG129_IN_SEL_M  (BIT(7))
+#define GPIO_SIG129_IN_SEL_V  0x1
+#define GPIO_SIG129_IN_SEL_S  7
+/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC129_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC129_IN_INV_SEL_V  0x1
+#define GPIO_FUNC129_IN_INV_SEL_S  6
+/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC129_IN_SEL  0x0000003F
+#define GPIO_FUNC129_IN_SEL_M  ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S))
+#define GPIO_FUNC129_IN_SEL_V  0x3F
+#define GPIO_FUNC129_IN_SEL_S  0
+
+#define GPIO_FUNC130_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x35C)
+/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG130_IN_SEL  (BIT(7))
+#define GPIO_SIG130_IN_SEL_M  (BIT(7))
+#define GPIO_SIG130_IN_SEL_V  0x1
+#define GPIO_SIG130_IN_SEL_S  7
+/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC130_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC130_IN_INV_SEL_V  0x1
+#define GPIO_FUNC130_IN_INV_SEL_S  6
+/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC130_IN_SEL  0x0000003F
+#define GPIO_FUNC130_IN_SEL_M  ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S))
+#define GPIO_FUNC130_IN_SEL_V  0x3F
+#define GPIO_FUNC130_IN_SEL_S  0
+
+#define GPIO_FUNC131_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x360)
+/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG131_IN_SEL  (BIT(7))
+#define GPIO_SIG131_IN_SEL_M  (BIT(7))
+#define GPIO_SIG131_IN_SEL_V  0x1
+#define GPIO_SIG131_IN_SEL_S  7
+/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC131_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC131_IN_INV_SEL_V  0x1
+#define GPIO_FUNC131_IN_INV_SEL_S  6
+/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC131_IN_SEL  0x0000003F
+#define GPIO_FUNC131_IN_SEL_M  ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S))
+#define GPIO_FUNC131_IN_SEL_V  0x3F
+#define GPIO_FUNC131_IN_SEL_S  0
+
+#define GPIO_FUNC132_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x364)
+/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG132_IN_SEL  (BIT(7))
+#define GPIO_SIG132_IN_SEL_M  (BIT(7))
+#define GPIO_SIG132_IN_SEL_V  0x1
+#define GPIO_SIG132_IN_SEL_S  7
+/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC132_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC132_IN_INV_SEL_V  0x1
+#define GPIO_FUNC132_IN_INV_SEL_S  6
+/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC132_IN_SEL  0x0000003F
+#define GPIO_FUNC132_IN_SEL_M  ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S))
+#define GPIO_FUNC132_IN_SEL_V  0x3F
+#define GPIO_FUNC132_IN_SEL_S  0
+
+#define GPIO_FUNC133_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x368)
+/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG133_IN_SEL  (BIT(7))
+#define GPIO_SIG133_IN_SEL_M  (BIT(7))
+#define GPIO_SIG133_IN_SEL_V  0x1
+#define GPIO_SIG133_IN_SEL_S  7
+/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC133_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC133_IN_INV_SEL_V  0x1
+#define GPIO_FUNC133_IN_INV_SEL_S  6
+/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC133_IN_SEL  0x0000003F
+#define GPIO_FUNC133_IN_SEL_M  ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S))
+#define GPIO_FUNC133_IN_SEL_V  0x3F
+#define GPIO_FUNC133_IN_SEL_S  0
+
+#define GPIO_FUNC134_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x36C)
+/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG134_IN_SEL  (BIT(7))
+#define GPIO_SIG134_IN_SEL_M  (BIT(7))
+#define GPIO_SIG134_IN_SEL_V  0x1
+#define GPIO_SIG134_IN_SEL_S  7
+/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC134_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC134_IN_INV_SEL_V  0x1
+#define GPIO_FUNC134_IN_INV_SEL_S  6
+/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC134_IN_SEL  0x0000003F
+#define GPIO_FUNC134_IN_SEL_M  ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S))
+#define GPIO_FUNC134_IN_SEL_V  0x3F
+#define GPIO_FUNC134_IN_SEL_S  0
+
+#define GPIO_FUNC135_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x370)
+/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG135_IN_SEL  (BIT(7))
+#define GPIO_SIG135_IN_SEL_M  (BIT(7))
+#define GPIO_SIG135_IN_SEL_V  0x1
+#define GPIO_SIG135_IN_SEL_S  7
+/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC135_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC135_IN_INV_SEL_V  0x1
+#define GPIO_FUNC135_IN_INV_SEL_S  6
+/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC135_IN_SEL  0x0000003F
+#define GPIO_FUNC135_IN_SEL_M  ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S))
+#define GPIO_FUNC135_IN_SEL_V  0x3F
+#define GPIO_FUNC135_IN_SEL_S  0
+
+#define GPIO_FUNC136_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x374)
+/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG136_IN_SEL  (BIT(7))
+#define GPIO_SIG136_IN_SEL_M  (BIT(7))
+#define GPIO_SIG136_IN_SEL_V  0x1
+#define GPIO_SIG136_IN_SEL_S  7
+/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC136_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC136_IN_INV_SEL_V  0x1
+#define GPIO_FUNC136_IN_INV_SEL_S  6
+/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC136_IN_SEL  0x0000003F
+#define GPIO_FUNC136_IN_SEL_M  ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S))
+#define GPIO_FUNC136_IN_SEL_V  0x3F
+#define GPIO_FUNC136_IN_SEL_S  0
+
+#define GPIO_FUNC137_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x378)
+/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG137_IN_SEL  (BIT(7))
+#define GPIO_SIG137_IN_SEL_M  (BIT(7))
+#define GPIO_SIG137_IN_SEL_V  0x1
+#define GPIO_SIG137_IN_SEL_S  7
+/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC137_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC137_IN_INV_SEL_V  0x1
+#define GPIO_FUNC137_IN_INV_SEL_S  6
+/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC137_IN_SEL  0x0000003F
+#define GPIO_FUNC137_IN_SEL_M  ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S))
+#define GPIO_FUNC137_IN_SEL_V  0x3F
+#define GPIO_FUNC137_IN_SEL_S  0
+
+#define GPIO_FUNC138_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x37C)
+/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG138_IN_SEL  (BIT(7))
+#define GPIO_SIG138_IN_SEL_M  (BIT(7))
+#define GPIO_SIG138_IN_SEL_V  0x1
+#define GPIO_SIG138_IN_SEL_S  7
+/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC138_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC138_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC138_IN_INV_SEL_V  0x1
+#define GPIO_FUNC138_IN_INV_SEL_S  6
+/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC138_IN_SEL  0x0000003F
+#define GPIO_FUNC138_IN_SEL_M  ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S))
+#define GPIO_FUNC138_IN_SEL_V  0x3F
+#define GPIO_FUNC138_IN_SEL_S  0
+
+#define GPIO_FUNC139_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x380)
+/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG139_IN_SEL  (BIT(7))
+#define GPIO_SIG139_IN_SEL_M  (BIT(7))
+#define GPIO_SIG139_IN_SEL_V  0x1
+#define GPIO_SIG139_IN_SEL_S  7
+/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC139_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC139_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC139_IN_INV_SEL_V  0x1
+#define GPIO_FUNC139_IN_INV_SEL_S  6
+/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC139_IN_SEL  0x0000003F
+#define GPIO_FUNC139_IN_SEL_M  ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S))
+#define GPIO_FUNC139_IN_SEL_V  0x3F
+#define GPIO_FUNC139_IN_SEL_S  0
+
+#define GPIO_FUNC140_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x384)
+/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG140_IN_SEL  (BIT(7))
+#define GPIO_SIG140_IN_SEL_M  (BIT(7))
+#define GPIO_SIG140_IN_SEL_V  0x1
+#define GPIO_SIG140_IN_SEL_S  7
+/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC140_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC140_IN_INV_SEL_V  0x1
+#define GPIO_FUNC140_IN_INV_SEL_S  6
+/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC140_IN_SEL  0x0000003F
+#define GPIO_FUNC140_IN_SEL_M  ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S))
+#define GPIO_FUNC140_IN_SEL_V  0x3F
+#define GPIO_FUNC140_IN_SEL_S  0
+
+#define GPIO_FUNC141_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x388)
+/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG141_IN_SEL  (BIT(7))
+#define GPIO_SIG141_IN_SEL_M  (BIT(7))
+#define GPIO_SIG141_IN_SEL_V  0x1
+#define GPIO_SIG141_IN_SEL_S  7
+/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC141_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC141_IN_INV_SEL_V  0x1
+#define GPIO_FUNC141_IN_INV_SEL_S  6
+/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC141_IN_SEL  0x0000003F
+#define GPIO_FUNC141_IN_SEL_M  ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S))
+#define GPIO_FUNC141_IN_SEL_V  0x3F
+#define GPIO_FUNC141_IN_SEL_S  0
+
+#define GPIO_FUNC142_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x38C)
+/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG142_IN_SEL  (BIT(7))
+#define GPIO_SIG142_IN_SEL_M  (BIT(7))
+#define GPIO_SIG142_IN_SEL_V  0x1
+#define GPIO_SIG142_IN_SEL_S  7
+/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC142_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC142_IN_INV_SEL_V  0x1
+#define GPIO_FUNC142_IN_INV_SEL_S  6
+/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC142_IN_SEL  0x0000003F
+#define GPIO_FUNC142_IN_SEL_M  ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S))
+#define GPIO_FUNC142_IN_SEL_V  0x3F
+#define GPIO_FUNC142_IN_SEL_S  0
+
+#define GPIO_FUNC143_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x390)
+/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG143_IN_SEL  (BIT(7))
+#define GPIO_SIG143_IN_SEL_M  (BIT(7))
+#define GPIO_SIG143_IN_SEL_V  0x1
+#define GPIO_SIG143_IN_SEL_S  7
+/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC143_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC143_IN_INV_SEL_V  0x1
+#define GPIO_FUNC143_IN_INV_SEL_S  6
+/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC143_IN_SEL  0x0000003F
+#define GPIO_FUNC143_IN_SEL_M  ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S))
+#define GPIO_FUNC143_IN_SEL_V  0x3F
+#define GPIO_FUNC143_IN_SEL_S  0
+
+#define GPIO_FUNC144_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x394)
+/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG144_IN_SEL  (BIT(7))
+#define GPIO_SIG144_IN_SEL_M  (BIT(7))
+#define GPIO_SIG144_IN_SEL_V  0x1
+#define GPIO_SIG144_IN_SEL_S  7
+/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC144_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC144_IN_INV_SEL_V  0x1
+#define GPIO_FUNC144_IN_INV_SEL_S  6
+/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC144_IN_SEL  0x0000003F
+#define GPIO_FUNC144_IN_SEL_M  ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S))
+#define GPIO_FUNC144_IN_SEL_V  0x3F
+#define GPIO_FUNC144_IN_SEL_S  0
+
+#define GPIO_FUNC145_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x398)
+/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG145_IN_SEL  (BIT(7))
+#define GPIO_SIG145_IN_SEL_M  (BIT(7))
+#define GPIO_SIG145_IN_SEL_V  0x1
+#define GPIO_SIG145_IN_SEL_S  7
+/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC145_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC145_IN_INV_SEL_V  0x1
+#define GPIO_FUNC145_IN_INV_SEL_S  6
+/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC145_IN_SEL  0x0000003F
+#define GPIO_FUNC145_IN_SEL_M  ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S))
+#define GPIO_FUNC145_IN_SEL_V  0x3F
+#define GPIO_FUNC145_IN_SEL_S  0
+
+#define GPIO_FUNC146_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x39C)
+/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG146_IN_SEL  (BIT(7))
+#define GPIO_SIG146_IN_SEL_M  (BIT(7))
+#define GPIO_SIG146_IN_SEL_V  0x1
+#define GPIO_SIG146_IN_SEL_S  7
+/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC146_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC146_IN_INV_SEL_V  0x1
+#define GPIO_FUNC146_IN_INV_SEL_S  6
+/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC146_IN_SEL  0x0000003F
+#define GPIO_FUNC146_IN_SEL_M  ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S))
+#define GPIO_FUNC146_IN_SEL_V  0x3F
+#define GPIO_FUNC146_IN_SEL_S  0
+
+#define GPIO_FUNC147_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A0)
+/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG147_IN_SEL  (BIT(7))
+#define GPIO_SIG147_IN_SEL_M  (BIT(7))
+#define GPIO_SIG147_IN_SEL_V  0x1
+#define GPIO_SIG147_IN_SEL_S  7
+/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC147_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC147_IN_INV_SEL_V  0x1
+#define GPIO_FUNC147_IN_INV_SEL_S  6
+/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC147_IN_SEL  0x0000003F
+#define GPIO_FUNC147_IN_SEL_M  ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S))
+#define GPIO_FUNC147_IN_SEL_V  0x3F
+#define GPIO_FUNC147_IN_SEL_S  0
+
+#define GPIO_FUNC148_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A4)
+/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG148_IN_SEL  (BIT(7))
+#define GPIO_SIG148_IN_SEL_M  (BIT(7))
+#define GPIO_SIG148_IN_SEL_V  0x1
+#define GPIO_SIG148_IN_SEL_S  7
+/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC148_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC148_IN_INV_SEL_V  0x1
+#define GPIO_FUNC148_IN_INV_SEL_S  6
+/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC148_IN_SEL  0x0000003F
+#define GPIO_FUNC148_IN_SEL_M  ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S))
+#define GPIO_FUNC148_IN_SEL_V  0x3F
+#define GPIO_FUNC148_IN_SEL_S  0
+
+#define GPIO_FUNC149_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3A8)
+/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG149_IN_SEL  (BIT(7))
+#define GPIO_SIG149_IN_SEL_M  (BIT(7))
+#define GPIO_SIG149_IN_SEL_V  0x1
+#define GPIO_SIG149_IN_SEL_S  7
+/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC149_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC149_IN_INV_SEL_V  0x1
+#define GPIO_FUNC149_IN_INV_SEL_S  6
+/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC149_IN_SEL  0x0000003F
+#define GPIO_FUNC149_IN_SEL_M  ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S))
+#define GPIO_FUNC149_IN_SEL_V  0x3F
+#define GPIO_FUNC149_IN_SEL_S  0
+
+#define GPIO_FUNC150_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3AC)
+/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG150_IN_SEL  (BIT(7))
+#define GPIO_SIG150_IN_SEL_M  (BIT(7))
+#define GPIO_SIG150_IN_SEL_V  0x1
+#define GPIO_SIG150_IN_SEL_S  7
+/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC150_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC150_IN_INV_SEL_V  0x1
+#define GPIO_FUNC150_IN_INV_SEL_S  6
+/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC150_IN_SEL  0x0000003F
+#define GPIO_FUNC150_IN_SEL_M  ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S))
+#define GPIO_FUNC150_IN_SEL_V  0x3F
+#define GPIO_FUNC150_IN_SEL_S  0
+
+#define GPIO_FUNC151_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B0)
+/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG151_IN_SEL  (BIT(7))
+#define GPIO_SIG151_IN_SEL_M  (BIT(7))
+#define GPIO_SIG151_IN_SEL_V  0x1
+#define GPIO_SIG151_IN_SEL_S  7
+/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC151_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC151_IN_INV_SEL_V  0x1
+#define GPIO_FUNC151_IN_INV_SEL_S  6
+/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC151_IN_SEL  0x0000003F
+#define GPIO_FUNC151_IN_SEL_M  ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S))
+#define GPIO_FUNC151_IN_SEL_V  0x3F
+#define GPIO_FUNC151_IN_SEL_S  0
+
+#define GPIO_FUNC152_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B4)
+/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG152_IN_SEL  (BIT(7))
+#define GPIO_SIG152_IN_SEL_M  (BIT(7))
+#define GPIO_SIG152_IN_SEL_V  0x1
+#define GPIO_SIG152_IN_SEL_S  7
+/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC152_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC152_IN_INV_SEL_V  0x1
+#define GPIO_FUNC152_IN_INV_SEL_S  6
+/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC152_IN_SEL  0x0000003F
+#define GPIO_FUNC152_IN_SEL_M  ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S))
+#define GPIO_FUNC152_IN_SEL_V  0x3F
+#define GPIO_FUNC152_IN_SEL_S  0
+
+#define GPIO_FUNC153_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3B8)
+/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG153_IN_SEL  (BIT(7))
+#define GPIO_SIG153_IN_SEL_M  (BIT(7))
+#define GPIO_SIG153_IN_SEL_V  0x1
+#define GPIO_SIG153_IN_SEL_S  7
+/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC153_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC153_IN_INV_SEL_V  0x1
+#define GPIO_FUNC153_IN_INV_SEL_S  6
+/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC153_IN_SEL  0x0000003F
+#define GPIO_FUNC153_IN_SEL_M  ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S))
+#define GPIO_FUNC153_IN_SEL_V  0x3F
+#define GPIO_FUNC153_IN_SEL_S  0
+
+#define GPIO_FUNC154_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3BC)
+/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG154_IN_SEL  (BIT(7))
+#define GPIO_SIG154_IN_SEL_M  (BIT(7))
+#define GPIO_SIG154_IN_SEL_V  0x1
+#define GPIO_SIG154_IN_SEL_S  7
+/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC154_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC154_IN_INV_SEL_V  0x1
+#define GPIO_FUNC154_IN_INV_SEL_S  6
+/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC154_IN_SEL  0x0000003F
+#define GPIO_FUNC154_IN_SEL_M  ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S))
+#define GPIO_FUNC154_IN_SEL_V  0x3F
+#define GPIO_FUNC154_IN_SEL_S  0
+
+#define GPIO_FUNC155_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C0)
+/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG155_IN_SEL  (BIT(7))
+#define GPIO_SIG155_IN_SEL_M  (BIT(7))
+#define GPIO_SIG155_IN_SEL_V  0x1
+#define GPIO_SIG155_IN_SEL_S  7
+/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC155_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC155_IN_INV_SEL_V  0x1
+#define GPIO_FUNC155_IN_INV_SEL_S  6
+/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC155_IN_SEL  0x0000003F
+#define GPIO_FUNC155_IN_SEL_M  ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S))
+#define GPIO_FUNC155_IN_SEL_V  0x3F
+#define GPIO_FUNC155_IN_SEL_S  0
+
+#define GPIO_FUNC156_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C4)
+/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG156_IN_SEL  (BIT(7))
+#define GPIO_SIG156_IN_SEL_M  (BIT(7))
+#define GPIO_SIG156_IN_SEL_V  0x1
+#define GPIO_SIG156_IN_SEL_S  7
+/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC156_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC156_IN_INV_SEL_V  0x1
+#define GPIO_FUNC156_IN_INV_SEL_S  6
+/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC156_IN_SEL  0x0000003F
+#define GPIO_FUNC156_IN_SEL_M  ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S))
+#define GPIO_FUNC156_IN_SEL_V  0x3F
+#define GPIO_FUNC156_IN_SEL_S  0
+
+#define GPIO_FUNC157_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3C8)
+/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG157_IN_SEL  (BIT(7))
+#define GPIO_SIG157_IN_SEL_M  (BIT(7))
+#define GPIO_SIG157_IN_SEL_V  0x1
+#define GPIO_SIG157_IN_SEL_S  7
+/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC157_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC157_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC157_IN_INV_SEL_V  0x1
+#define GPIO_FUNC157_IN_INV_SEL_S  6
+/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC157_IN_SEL  0x0000003F
+#define GPIO_FUNC157_IN_SEL_M  ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S))
+#define GPIO_FUNC157_IN_SEL_V  0x3F
+#define GPIO_FUNC157_IN_SEL_S  0
+
+#define GPIO_FUNC158_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3CC)
+/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG158_IN_SEL  (BIT(7))
+#define GPIO_SIG158_IN_SEL_M  (BIT(7))
+#define GPIO_SIG158_IN_SEL_V  0x1
+#define GPIO_SIG158_IN_SEL_S  7
+/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC158_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC158_IN_INV_SEL_V  0x1
+#define GPIO_FUNC158_IN_INV_SEL_S  6
+/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC158_IN_SEL  0x0000003F
+#define GPIO_FUNC158_IN_SEL_M  ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S))
+#define GPIO_FUNC158_IN_SEL_V  0x3F
+#define GPIO_FUNC158_IN_SEL_S  0
+
+#define GPIO_FUNC159_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D0)
+/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG159_IN_SEL  (BIT(7))
+#define GPIO_SIG159_IN_SEL_M  (BIT(7))
+#define GPIO_SIG159_IN_SEL_V  0x1
+#define GPIO_SIG159_IN_SEL_S  7
+/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC159_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC159_IN_INV_SEL_V  0x1
+#define GPIO_FUNC159_IN_INV_SEL_S  6
+/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC159_IN_SEL  0x0000003F
+#define GPIO_FUNC159_IN_SEL_M  ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S))
+#define GPIO_FUNC159_IN_SEL_V  0x3F
+#define GPIO_FUNC159_IN_SEL_S  0
+
+#define GPIO_FUNC160_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D4)
+/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG160_IN_SEL  (BIT(7))
+#define GPIO_SIG160_IN_SEL_M  (BIT(7))
+#define GPIO_SIG160_IN_SEL_V  0x1
+#define GPIO_SIG160_IN_SEL_S  7
+/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC160_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC160_IN_INV_SEL_V  0x1
+#define GPIO_FUNC160_IN_INV_SEL_S  6
+/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC160_IN_SEL  0x0000003F
+#define GPIO_FUNC160_IN_SEL_M  ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S))
+#define GPIO_FUNC160_IN_SEL_V  0x3F
+#define GPIO_FUNC160_IN_SEL_S  0
+
+#define GPIO_FUNC161_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3D8)
+/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG161_IN_SEL  (BIT(7))
+#define GPIO_SIG161_IN_SEL_M  (BIT(7))
+#define GPIO_SIG161_IN_SEL_V  0x1
+#define GPIO_SIG161_IN_SEL_S  7
+/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC161_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC161_IN_INV_SEL_V  0x1
+#define GPIO_FUNC161_IN_INV_SEL_S  6
+/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC161_IN_SEL  0x0000003F
+#define GPIO_FUNC161_IN_SEL_M  ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S))
+#define GPIO_FUNC161_IN_SEL_V  0x3F
+#define GPIO_FUNC161_IN_SEL_S  0
+
+#define GPIO_FUNC162_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3DC)
+/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG162_IN_SEL  (BIT(7))
+#define GPIO_SIG162_IN_SEL_M  (BIT(7))
+#define GPIO_SIG162_IN_SEL_V  0x1
+#define GPIO_SIG162_IN_SEL_S  7
+/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC162_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC162_IN_INV_SEL_V  0x1
+#define GPIO_FUNC162_IN_INV_SEL_S  6
+/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC162_IN_SEL  0x0000003F
+#define GPIO_FUNC162_IN_SEL_M  ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S))
+#define GPIO_FUNC162_IN_SEL_V  0x3F
+#define GPIO_FUNC162_IN_SEL_S  0
+
+#define GPIO_FUNC163_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E0)
+/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG163_IN_SEL  (BIT(7))
+#define GPIO_SIG163_IN_SEL_M  (BIT(7))
+#define GPIO_SIG163_IN_SEL_V  0x1
+#define GPIO_SIG163_IN_SEL_S  7
+/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC163_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC163_IN_INV_SEL_V  0x1
+#define GPIO_FUNC163_IN_INV_SEL_S  6
+/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC163_IN_SEL  0x0000003F
+#define GPIO_FUNC163_IN_SEL_M  ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S))
+#define GPIO_FUNC163_IN_SEL_V  0x3F
+#define GPIO_FUNC163_IN_SEL_S  0
+
+#define GPIO_FUNC164_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E4)
+/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG164_IN_SEL  (BIT(7))
+#define GPIO_SIG164_IN_SEL_M  (BIT(7))
+#define GPIO_SIG164_IN_SEL_V  0x1
+#define GPIO_SIG164_IN_SEL_S  7
+/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC164_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC164_IN_INV_SEL_V  0x1
+#define GPIO_FUNC164_IN_INV_SEL_S  6
+/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC164_IN_SEL  0x0000003F
+#define GPIO_FUNC164_IN_SEL_M  ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S))
+#define GPIO_FUNC164_IN_SEL_V  0x3F
+#define GPIO_FUNC164_IN_SEL_S  0
+
+#define GPIO_FUNC165_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3E8)
+/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG165_IN_SEL  (BIT(7))
+#define GPIO_SIG165_IN_SEL_M  (BIT(7))
+#define GPIO_SIG165_IN_SEL_V  0x1
+#define GPIO_SIG165_IN_SEL_S  7
+/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC165_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC165_IN_INV_SEL_V  0x1
+#define GPIO_FUNC165_IN_INV_SEL_S  6
+/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC165_IN_SEL  0x0000003F
+#define GPIO_FUNC165_IN_SEL_M  ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S))
+#define GPIO_FUNC165_IN_SEL_V  0x3F
+#define GPIO_FUNC165_IN_SEL_S  0
+
+#define GPIO_FUNC166_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3EC)
+/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG166_IN_SEL  (BIT(7))
+#define GPIO_SIG166_IN_SEL_M  (BIT(7))
+#define GPIO_SIG166_IN_SEL_V  0x1
+#define GPIO_SIG166_IN_SEL_S  7
+/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC166_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC166_IN_INV_SEL_V  0x1
+#define GPIO_FUNC166_IN_INV_SEL_S  6
+/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC166_IN_SEL  0x0000003F
+#define GPIO_FUNC166_IN_SEL_M  ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S))
+#define GPIO_FUNC166_IN_SEL_V  0x3F
+#define GPIO_FUNC166_IN_SEL_S  0
+
+#define GPIO_FUNC167_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F0)
+/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG167_IN_SEL  (BIT(7))
+#define GPIO_SIG167_IN_SEL_M  (BIT(7))
+#define GPIO_SIG167_IN_SEL_V  0x1
+#define GPIO_SIG167_IN_SEL_S  7
+/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC167_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC167_IN_INV_SEL_V  0x1
+#define GPIO_FUNC167_IN_INV_SEL_S  6
+/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC167_IN_SEL  0x0000003F
+#define GPIO_FUNC167_IN_SEL_M  ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S))
+#define GPIO_FUNC167_IN_SEL_V  0x3F
+#define GPIO_FUNC167_IN_SEL_S  0
+
+#define GPIO_FUNC168_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F4)
+/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG168_IN_SEL  (BIT(7))
+#define GPIO_SIG168_IN_SEL_M  (BIT(7))
+#define GPIO_SIG168_IN_SEL_V  0x1
+#define GPIO_SIG168_IN_SEL_S  7
+/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC168_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC168_IN_INV_SEL_V  0x1
+#define GPIO_FUNC168_IN_INV_SEL_S  6
+/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC168_IN_SEL  0x0000003F
+#define GPIO_FUNC168_IN_SEL_M  ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S))
+#define GPIO_FUNC168_IN_SEL_V  0x3F
+#define GPIO_FUNC168_IN_SEL_S  0
+
+#define GPIO_FUNC169_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3F8)
+/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG169_IN_SEL  (BIT(7))
+#define GPIO_SIG169_IN_SEL_M  (BIT(7))
+#define GPIO_SIG169_IN_SEL_V  0x1
+#define GPIO_SIG169_IN_SEL_S  7
+/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC169_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC169_IN_INV_SEL_V  0x1
+#define GPIO_FUNC169_IN_INV_SEL_S  6
+/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC169_IN_SEL  0x0000003F
+#define GPIO_FUNC169_IN_SEL_M  ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S))
+#define GPIO_FUNC169_IN_SEL_V  0x3F
+#define GPIO_FUNC169_IN_SEL_S  0
+
+#define GPIO_FUNC170_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x3FC)
+/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG170_IN_SEL  (BIT(7))
+#define GPIO_SIG170_IN_SEL_M  (BIT(7))
+#define GPIO_SIG170_IN_SEL_V  0x1
+#define GPIO_SIG170_IN_SEL_S  7
+/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC170_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC170_IN_INV_SEL_V  0x1
+#define GPIO_FUNC170_IN_INV_SEL_S  6
+/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC170_IN_SEL  0x0000003F
+#define GPIO_FUNC170_IN_SEL_M  ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S))
+#define GPIO_FUNC170_IN_SEL_V  0x3F
+#define GPIO_FUNC170_IN_SEL_S  0
+
+#define GPIO_FUNC171_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x400)
+/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG171_IN_SEL  (BIT(7))
+#define GPIO_SIG171_IN_SEL_M  (BIT(7))
+#define GPIO_SIG171_IN_SEL_V  0x1
+#define GPIO_SIG171_IN_SEL_S  7
+/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC171_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC171_IN_INV_SEL_V  0x1
+#define GPIO_FUNC171_IN_INV_SEL_S  6
+/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC171_IN_SEL  0x0000003F
+#define GPIO_FUNC171_IN_SEL_M  ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S))
+#define GPIO_FUNC171_IN_SEL_V  0x3F
+#define GPIO_FUNC171_IN_SEL_S  0
+
+#define GPIO_FUNC172_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x404)
+/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG172_IN_SEL  (BIT(7))
+#define GPIO_SIG172_IN_SEL_M  (BIT(7))
+#define GPIO_SIG172_IN_SEL_V  0x1
+#define GPIO_SIG172_IN_SEL_S  7
+/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC172_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC172_IN_INV_SEL_V  0x1
+#define GPIO_FUNC172_IN_INV_SEL_S  6
+/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC172_IN_SEL  0x0000003F
+#define GPIO_FUNC172_IN_SEL_M  ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S))
+#define GPIO_FUNC172_IN_SEL_V  0x3F
+#define GPIO_FUNC172_IN_SEL_S  0
+
+#define GPIO_FUNC173_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x408)
+/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG173_IN_SEL  (BIT(7))
+#define GPIO_SIG173_IN_SEL_M  (BIT(7))
+#define GPIO_SIG173_IN_SEL_V  0x1
+#define GPIO_SIG173_IN_SEL_S  7
+/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC173_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC173_IN_INV_SEL_V  0x1
+#define GPIO_FUNC173_IN_INV_SEL_S  6
+/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC173_IN_SEL  0x0000003F
+#define GPIO_FUNC173_IN_SEL_M  ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S))
+#define GPIO_FUNC173_IN_SEL_V  0x3F
+#define GPIO_FUNC173_IN_SEL_S  0
+
+#define GPIO_FUNC174_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x40C)
+/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG174_IN_SEL  (BIT(7))
+#define GPIO_SIG174_IN_SEL_M  (BIT(7))
+#define GPIO_SIG174_IN_SEL_V  0x1
+#define GPIO_SIG174_IN_SEL_S  7
+/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC174_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC174_IN_INV_SEL_V  0x1
+#define GPIO_FUNC174_IN_INV_SEL_S  6
+/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC174_IN_SEL  0x0000003F
+#define GPIO_FUNC174_IN_SEL_M  ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S))
+#define GPIO_FUNC174_IN_SEL_V  0x3F
+#define GPIO_FUNC174_IN_SEL_S  0
+
+#define GPIO_FUNC175_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x410)
+/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG175_IN_SEL  (BIT(7))
+#define GPIO_SIG175_IN_SEL_M  (BIT(7))
+#define GPIO_SIG175_IN_SEL_V  0x1
+#define GPIO_SIG175_IN_SEL_S  7
+/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC175_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC175_IN_INV_SEL_V  0x1
+#define GPIO_FUNC175_IN_INV_SEL_S  6
+/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC175_IN_SEL  0x0000003F
+#define GPIO_FUNC175_IN_SEL_M  ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S))
+#define GPIO_FUNC175_IN_SEL_V  0x3F
+#define GPIO_FUNC175_IN_SEL_S  0
+
+#define GPIO_FUNC176_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x414)
+/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG176_IN_SEL  (BIT(7))
+#define GPIO_SIG176_IN_SEL_M  (BIT(7))
+#define GPIO_SIG176_IN_SEL_V  0x1
+#define GPIO_SIG176_IN_SEL_S  7
+/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC176_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC176_IN_INV_SEL_V  0x1
+#define GPIO_FUNC176_IN_INV_SEL_S  6
+/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC176_IN_SEL  0x0000003F
+#define GPIO_FUNC176_IN_SEL_M  ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S))
+#define GPIO_FUNC176_IN_SEL_V  0x3F
+#define GPIO_FUNC176_IN_SEL_S  0
+
+#define GPIO_FUNC177_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x418)
+/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG177_IN_SEL  (BIT(7))
+#define GPIO_SIG177_IN_SEL_M  (BIT(7))
+#define GPIO_SIG177_IN_SEL_V  0x1
+#define GPIO_SIG177_IN_SEL_S  7
+/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC177_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC177_IN_INV_SEL_V  0x1
+#define GPIO_FUNC177_IN_INV_SEL_S  6
+/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC177_IN_SEL  0x0000003F
+#define GPIO_FUNC177_IN_SEL_M  ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S))
+#define GPIO_FUNC177_IN_SEL_V  0x3F
+#define GPIO_FUNC177_IN_SEL_S  0
+
+#define GPIO_FUNC178_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x41C)
+/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG178_IN_SEL  (BIT(7))
+#define GPIO_SIG178_IN_SEL_M  (BIT(7))
+#define GPIO_SIG178_IN_SEL_V  0x1
+#define GPIO_SIG178_IN_SEL_S  7
+/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC178_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC178_IN_INV_SEL_V  0x1
+#define GPIO_FUNC178_IN_INV_SEL_S  6
+/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC178_IN_SEL  0x0000003F
+#define GPIO_FUNC178_IN_SEL_M  ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S))
+#define GPIO_FUNC178_IN_SEL_V  0x3F
+#define GPIO_FUNC178_IN_SEL_S  0
+
+#define GPIO_FUNC179_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x420)
+/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG179_IN_SEL  (BIT(7))
+#define GPIO_SIG179_IN_SEL_M  (BIT(7))
+#define GPIO_SIG179_IN_SEL_V  0x1
+#define GPIO_SIG179_IN_SEL_S  7
+/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC179_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC179_IN_INV_SEL_V  0x1
+#define GPIO_FUNC179_IN_INV_SEL_S  6
+/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC179_IN_SEL  0x0000003F
+#define GPIO_FUNC179_IN_SEL_M  ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S))
+#define GPIO_FUNC179_IN_SEL_V  0x3F
+#define GPIO_FUNC179_IN_SEL_S  0
+
+#define GPIO_FUNC180_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x424)
+/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG180_IN_SEL  (BIT(7))
+#define GPIO_SIG180_IN_SEL_M  (BIT(7))
+#define GPIO_SIG180_IN_SEL_V  0x1
+#define GPIO_SIG180_IN_SEL_S  7
+/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC180_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC180_IN_INV_SEL_V  0x1
+#define GPIO_FUNC180_IN_INV_SEL_S  6
+/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC180_IN_SEL  0x0000003F
+#define GPIO_FUNC180_IN_SEL_M  ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S))
+#define GPIO_FUNC180_IN_SEL_V  0x3F
+#define GPIO_FUNC180_IN_SEL_S  0
+
+#define GPIO_FUNC181_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x428)
+/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG181_IN_SEL  (BIT(7))
+#define GPIO_SIG181_IN_SEL_M  (BIT(7))
+#define GPIO_SIG181_IN_SEL_V  0x1
+#define GPIO_SIG181_IN_SEL_S  7
+/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC181_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC181_IN_INV_SEL_V  0x1
+#define GPIO_FUNC181_IN_INV_SEL_S  6
+/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC181_IN_SEL  0x0000003F
+#define GPIO_FUNC181_IN_SEL_M  ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S))
+#define GPIO_FUNC181_IN_SEL_V  0x3F
+#define GPIO_FUNC181_IN_SEL_S  0
+
+#define GPIO_FUNC182_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x42C)
+/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG182_IN_SEL  (BIT(7))
+#define GPIO_SIG182_IN_SEL_M  (BIT(7))
+#define GPIO_SIG182_IN_SEL_V  0x1
+#define GPIO_SIG182_IN_SEL_S  7
+/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC182_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC182_IN_INV_SEL_V  0x1
+#define GPIO_FUNC182_IN_INV_SEL_S  6
+/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC182_IN_SEL  0x0000003F
+#define GPIO_FUNC182_IN_SEL_M  ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S))
+#define GPIO_FUNC182_IN_SEL_V  0x3F
+#define GPIO_FUNC182_IN_SEL_S  0
+
+#define GPIO_FUNC183_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x430)
+/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG183_IN_SEL  (BIT(7))
+#define GPIO_SIG183_IN_SEL_M  (BIT(7))
+#define GPIO_SIG183_IN_SEL_V  0x1
+#define GPIO_SIG183_IN_SEL_S  7
+/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC183_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC183_IN_INV_SEL_V  0x1
+#define GPIO_FUNC183_IN_INV_SEL_S  6
+/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC183_IN_SEL  0x0000003F
+#define GPIO_FUNC183_IN_SEL_M  ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S))
+#define GPIO_FUNC183_IN_SEL_V  0x3F
+#define GPIO_FUNC183_IN_SEL_S  0
+
+#define GPIO_FUNC184_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x434)
+/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG184_IN_SEL  (BIT(7))
+#define GPIO_SIG184_IN_SEL_M  (BIT(7))
+#define GPIO_SIG184_IN_SEL_V  0x1
+#define GPIO_SIG184_IN_SEL_S  7
+/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC184_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC184_IN_INV_SEL_V  0x1
+#define GPIO_FUNC184_IN_INV_SEL_S  6
+/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC184_IN_SEL  0x0000003F
+#define GPIO_FUNC184_IN_SEL_M  ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S))
+#define GPIO_FUNC184_IN_SEL_V  0x3F
+#define GPIO_FUNC184_IN_SEL_S  0
+
+#define GPIO_FUNC185_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x438)
+/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG185_IN_SEL  (BIT(7))
+#define GPIO_SIG185_IN_SEL_M  (BIT(7))
+#define GPIO_SIG185_IN_SEL_V  0x1
+#define GPIO_SIG185_IN_SEL_S  7
+/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC185_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC185_IN_INV_SEL_V  0x1
+#define GPIO_FUNC185_IN_INV_SEL_S  6
+/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC185_IN_SEL  0x0000003F
+#define GPIO_FUNC185_IN_SEL_M  ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S))
+#define GPIO_FUNC185_IN_SEL_V  0x3F
+#define GPIO_FUNC185_IN_SEL_S  0
+
+#define GPIO_FUNC186_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x43C)
+/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG186_IN_SEL  (BIT(7))
+#define GPIO_SIG186_IN_SEL_M  (BIT(7))
+#define GPIO_SIG186_IN_SEL_V  0x1
+#define GPIO_SIG186_IN_SEL_S  7
+/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC186_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC186_IN_INV_SEL_V  0x1
+#define GPIO_FUNC186_IN_INV_SEL_S  6
+/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC186_IN_SEL  0x0000003F
+#define GPIO_FUNC186_IN_SEL_M  ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S))
+#define GPIO_FUNC186_IN_SEL_V  0x3F
+#define GPIO_FUNC186_IN_SEL_S  0
+
+#define GPIO_FUNC187_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x440)
+/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG187_IN_SEL  (BIT(7))
+#define GPIO_SIG187_IN_SEL_M  (BIT(7))
+#define GPIO_SIG187_IN_SEL_V  0x1
+#define GPIO_SIG187_IN_SEL_S  7
+/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC187_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC187_IN_INV_SEL_V  0x1
+#define GPIO_FUNC187_IN_INV_SEL_S  6
+/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC187_IN_SEL  0x0000003F
+#define GPIO_FUNC187_IN_SEL_M  ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S))
+#define GPIO_FUNC187_IN_SEL_V  0x3F
+#define GPIO_FUNC187_IN_SEL_S  0
+
+#define GPIO_FUNC188_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x444)
+/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG188_IN_SEL  (BIT(7))
+#define GPIO_SIG188_IN_SEL_M  (BIT(7))
+#define GPIO_SIG188_IN_SEL_V  0x1
+#define GPIO_SIG188_IN_SEL_S  7
+/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC188_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC188_IN_INV_SEL_V  0x1
+#define GPIO_FUNC188_IN_INV_SEL_S  6
+/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC188_IN_SEL  0x0000003F
+#define GPIO_FUNC188_IN_SEL_M  ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S))
+#define GPIO_FUNC188_IN_SEL_V  0x3F
+#define GPIO_FUNC188_IN_SEL_S  0
+
+#define GPIO_FUNC189_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x448)
+/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG189_IN_SEL  (BIT(7))
+#define GPIO_SIG189_IN_SEL_M  (BIT(7))
+#define GPIO_SIG189_IN_SEL_V  0x1
+#define GPIO_SIG189_IN_SEL_S  7
+/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC189_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC189_IN_INV_SEL_V  0x1
+#define GPIO_FUNC189_IN_INV_SEL_S  6
+/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC189_IN_SEL  0x0000003F
+#define GPIO_FUNC189_IN_SEL_M  ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S))
+#define GPIO_FUNC189_IN_SEL_V  0x3F
+#define GPIO_FUNC189_IN_SEL_S  0
+
+#define GPIO_FUNC190_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x44C)
+/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG190_IN_SEL  (BIT(7))
+#define GPIO_SIG190_IN_SEL_M  (BIT(7))
+#define GPIO_SIG190_IN_SEL_V  0x1
+#define GPIO_SIG190_IN_SEL_S  7
+/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC190_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC190_IN_INV_SEL_V  0x1
+#define GPIO_FUNC190_IN_INV_SEL_S  6
+/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC190_IN_SEL  0x0000003F
+#define GPIO_FUNC190_IN_SEL_M  ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S))
+#define GPIO_FUNC190_IN_SEL_V  0x3F
+#define GPIO_FUNC190_IN_SEL_S  0
+
+#define GPIO_FUNC191_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x450)
+/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG191_IN_SEL  (BIT(7))
+#define GPIO_SIG191_IN_SEL_M  (BIT(7))
+#define GPIO_SIG191_IN_SEL_V  0x1
+#define GPIO_SIG191_IN_SEL_S  7
+/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC191_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC191_IN_INV_SEL_V  0x1
+#define GPIO_FUNC191_IN_INV_SEL_S  6
+/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC191_IN_SEL  0x0000003F
+#define GPIO_FUNC191_IN_SEL_M  ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S))
+#define GPIO_FUNC191_IN_SEL_V  0x3F
+#define GPIO_FUNC191_IN_SEL_S  0
+
+#define GPIO_FUNC192_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x454)
+/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG192_IN_SEL  (BIT(7))
+#define GPIO_SIG192_IN_SEL_M  (BIT(7))
+#define GPIO_SIG192_IN_SEL_V  0x1
+#define GPIO_SIG192_IN_SEL_S  7
+/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC192_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC192_IN_INV_SEL_V  0x1
+#define GPIO_FUNC192_IN_INV_SEL_S  6
+/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC192_IN_SEL  0x0000003F
+#define GPIO_FUNC192_IN_SEL_M  ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S))
+#define GPIO_FUNC192_IN_SEL_V  0x3F
+#define GPIO_FUNC192_IN_SEL_S  0
+
+#define GPIO_FUNC193_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x458)
+/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG193_IN_SEL  (BIT(7))
+#define GPIO_SIG193_IN_SEL_M  (BIT(7))
+#define GPIO_SIG193_IN_SEL_V  0x1
+#define GPIO_SIG193_IN_SEL_S  7
+/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC193_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC193_IN_INV_SEL_V  0x1
+#define GPIO_FUNC193_IN_INV_SEL_S  6
+/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC193_IN_SEL  0x0000003F
+#define GPIO_FUNC193_IN_SEL_M  ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S))
+#define GPIO_FUNC193_IN_SEL_V  0x3F
+#define GPIO_FUNC193_IN_SEL_S  0
+
+#define GPIO_FUNC194_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x45C)
+/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG194_IN_SEL  (BIT(7))
+#define GPIO_SIG194_IN_SEL_M  (BIT(7))
+#define GPIO_SIG194_IN_SEL_V  0x1
+#define GPIO_SIG194_IN_SEL_S  7
+/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC194_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC194_IN_INV_SEL_V  0x1
+#define GPIO_FUNC194_IN_INV_SEL_S  6
+/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC194_IN_SEL  0x0000003F
+#define GPIO_FUNC194_IN_SEL_M  ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S))
+#define GPIO_FUNC194_IN_SEL_V  0x3F
+#define GPIO_FUNC194_IN_SEL_S  0
+
+#define GPIO_FUNC195_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x460)
+/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG195_IN_SEL  (BIT(7))
+#define GPIO_SIG195_IN_SEL_M  (BIT(7))
+#define GPIO_SIG195_IN_SEL_V  0x1
+#define GPIO_SIG195_IN_SEL_S  7
+/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC195_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC195_IN_INV_SEL_V  0x1
+#define GPIO_FUNC195_IN_INV_SEL_S  6
+/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC195_IN_SEL  0x0000003F
+#define GPIO_FUNC195_IN_SEL_M  ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S))
+#define GPIO_FUNC195_IN_SEL_V  0x3F
+#define GPIO_FUNC195_IN_SEL_S  0
+
+#define GPIO_FUNC196_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x464)
+/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG196_IN_SEL  (BIT(7))
+#define GPIO_SIG196_IN_SEL_M  (BIT(7))
+#define GPIO_SIG196_IN_SEL_V  0x1
+#define GPIO_SIG196_IN_SEL_S  7
+/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC196_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC196_IN_INV_SEL_V  0x1
+#define GPIO_FUNC196_IN_INV_SEL_S  6
+/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC196_IN_SEL  0x0000003F
+#define GPIO_FUNC196_IN_SEL_M  ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S))
+#define GPIO_FUNC196_IN_SEL_V  0x3F
+#define GPIO_FUNC196_IN_SEL_S  0
+
+#define GPIO_FUNC197_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x468)
+/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG197_IN_SEL  (BIT(7))
+#define GPIO_SIG197_IN_SEL_M  (BIT(7))
+#define GPIO_SIG197_IN_SEL_V  0x1
+#define GPIO_SIG197_IN_SEL_S  7
+/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC197_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC197_IN_INV_SEL_V  0x1
+#define GPIO_FUNC197_IN_INV_SEL_S  6
+/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC197_IN_SEL  0x0000003F
+#define GPIO_FUNC197_IN_SEL_M  ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S))
+#define GPIO_FUNC197_IN_SEL_V  0x3F
+#define GPIO_FUNC197_IN_SEL_S  0
+
+#define GPIO_FUNC198_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x46C)
+/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG198_IN_SEL  (BIT(7))
+#define GPIO_SIG198_IN_SEL_M  (BIT(7))
+#define GPIO_SIG198_IN_SEL_V  0x1
+#define GPIO_SIG198_IN_SEL_S  7
+/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC198_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC198_IN_INV_SEL_V  0x1
+#define GPIO_FUNC198_IN_INV_SEL_S  6
+/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC198_IN_SEL  0x0000003F
+#define GPIO_FUNC198_IN_SEL_M  ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S))
+#define GPIO_FUNC198_IN_SEL_V  0x3F
+#define GPIO_FUNC198_IN_SEL_S  0
+
+#define GPIO_FUNC199_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x470)
+/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG199_IN_SEL  (BIT(7))
+#define GPIO_SIG199_IN_SEL_M  (BIT(7))
+#define GPIO_SIG199_IN_SEL_V  0x1
+#define GPIO_SIG199_IN_SEL_S  7
+/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC199_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC199_IN_INV_SEL_V  0x1
+#define GPIO_FUNC199_IN_INV_SEL_S  6
+/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC199_IN_SEL  0x0000003F
+#define GPIO_FUNC199_IN_SEL_M  ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S))
+#define GPIO_FUNC199_IN_SEL_V  0x3F
+#define GPIO_FUNC199_IN_SEL_S  0
+
+#define GPIO_FUNC200_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x474)
+/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG200_IN_SEL  (BIT(7))
+#define GPIO_SIG200_IN_SEL_M  (BIT(7))
+#define GPIO_SIG200_IN_SEL_V  0x1
+#define GPIO_SIG200_IN_SEL_S  7
+/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC200_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC200_IN_INV_SEL_V  0x1
+#define GPIO_FUNC200_IN_INV_SEL_S  6
+/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC200_IN_SEL  0x0000003F
+#define GPIO_FUNC200_IN_SEL_M  ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S))
+#define GPIO_FUNC200_IN_SEL_V  0x3F
+#define GPIO_FUNC200_IN_SEL_S  0
+
+#define GPIO_FUNC201_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x478)
+/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG201_IN_SEL  (BIT(7))
+#define GPIO_SIG201_IN_SEL_M  (BIT(7))
+#define GPIO_SIG201_IN_SEL_V  0x1
+#define GPIO_SIG201_IN_SEL_S  7
+/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC201_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC201_IN_INV_SEL_V  0x1
+#define GPIO_FUNC201_IN_INV_SEL_S  6
+/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC201_IN_SEL  0x0000003F
+#define GPIO_FUNC201_IN_SEL_M  ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S))
+#define GPIO_FUNC201_IN_SEL_V  0x3F
+#define GPIO_FUNC201_IN_SEL_S  0
+
+#define GPIO_FUNC202_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x47C)
+/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG202_IN_SEL  (BIT(7))
+#define GPIO_SIG202_IN_SEL_M  (BIT(7))
+#define GPIO_SIG202_IN_SEL_V  0x1
+#define GPIO_SIG202_IN_SEL_S  7
+/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC202_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC202_IN_INV_SEL_V  0x1
+#define GPIO_FUNC202_IN_INV_SEL_S  6
+/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC202_IN_SEL  0x0000003F
+#define GPIO_FUNC202_IN_SEL_M  ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S))
+#define GPIO_FUNC202_IN_SEL_V  0x3F
+#define GPIO_FUNC202_IN_SEL_S  0
+
+#define GPIO_FUNC203_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x480)
+/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG203_IN_SEL  (BIT(7))
+#define GPIO_SIG203_IN_SEL_M  (BIT(7))
+#define GPIO_SIG203_IN_SEL_V  0x1
+#define GPIO_SIG203_IN_SEL_S  7
+/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC203_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC203_IN_INV_SEL_V  0x1
+#define GPIO_FUNC203_IN_INV_SEL_S  6
+/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC203_IN_SEL  0x0000003F
+#define GPIO_FUNC203_IN_SEL_M  ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S))
+#define GPIO_FUNC203_IN_SEL_V  0x3F
+#define GPIO_FUNC203_IN_SEL_S  0
+
+#define GPIO_FUNC204_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x484)
+/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG204_IN_SEL  (BIT(7))
+#define GPIO_SIG204_IN_SEL_M  (BIT(7))
+#define GPIO_SIG204_IN_SEL_V  0x1
+#define GPIO_SIG204_IN_SEL_S  7
+/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC204_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC204_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC204_IN_INV_SEL_V  0x1
+#define GPIO_FUNC204_IN_INV_SEL_S  6
+/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC204_IN_SEL  0x0000003F
+#define GPIO_FUNC204_IN_SEL_M  ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S))
+#define GPIO_FUNC204_IN_SEL_V  0x3F
+#define GPIO_FUNC204_IN_SEL_S  0
+
+#define GPIO_FUNC205_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x488)
+/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG205_IN_SEL  (BIT(7))
+#define GPIO_SIG205_IN_SEL_M  (BIT(7))
+#define GPIO_SIG205_IN_SEL_V  0x1
+#define GPIO_SIG205_IN_SEL_S  7
+/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC205_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC205_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC205_IN_INV_SEL_V  0x1
+#define GPIO_FUNC205_IN_INV_SEL_S  6
+/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC205_IN_SEL  0x0000003F
+#define GPIO_FUNC205_IN_SEL_M  ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S))
+#define GPIO_FUNC205_IN_SEL_V  0x3F
+#define GPIO_FUNC205_IN_SEL_S  0
+
+#define GPIO_FUNC206_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x48C)
+/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG206_IN_SEL  (BIT(7))
+#define GPIO_SIG206_IN_SEL_M  (BIT(7))
+#define GPIO_SIG206_IN_SEL_V  0x1
+#define GPIO_SIG206_IN_SEL_S  7
+/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC206_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC206_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC206_IN_INV_SEL_V  0x1
+#define GPIO_FUNC206_IN_INV_SEL_S  6
+/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC206_IN_SEL  0x0000003F
+#define GPIO_FUNC206_IN_SEL_M  ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S))
+#define GPIO_FUNC206_IN_SEL_V  0x3F
+#define GPIO_FUNC206_IN_SEL_S  0
+
+#define GPIO_FUNC207_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x490)
+/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG207_IN_SEL  (BIT(7))
+#define GPIO_SIG207_IN_SEL_M  (BIT(7))
+#define GPIO_SIG207_IN_SEL_V  0x1
+#define GPIO_SIG207_IN_SEL_S  7
+/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC207_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC207_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC207_IN_INV_SEL_V  0x1
+#define GPIO_FUNC207_IN_INV_SEL_S  6
+/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC207_IN_SEL  0x0000003F
+#define GPIO_FUNC207_IN_SEL_M  ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S))
+#define GPIO_FUNC207_IN_SEL_V  0x3F
+#define GPIO_FUNC207_IN_SEL_S  0
+
+#define GPIO_FUNC208_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x494)
+/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG208_IN_SEL  (BIT(7))
+#define GPIO_SIG208_IN_SEL_M  (BIT(7))
+#define GPIO_SIG208_IN_SEL_V  0x1
+#define GPIO_SIG208_IN_SEL_S  7
+/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC208_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC208_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC208_IN_INV_SEL_V  0x1
+#define GPIO_FUNC208_IN_INV_SEL_S  6
+/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC208_IN_SEL  0x0000003F
+#define GPIO_FUNC208_IN_SEL_M  ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S))
+#define GPIO_FUNC208_IN_SEL_V  0x3F
+#define GPIO_FUNC208_IN_SEL_S  0
+
+#define GPIO_FUNC209_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x498)
+/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG209_IN_SEL  (BIT(7))
+#define GPIO_SIG209_IN_SEL_M  (BIT(7))
+#define GPIO_SIG209_IN_SEL_V  0x1
+#define GPIO_SIG209_IN_SEL_S  7
+/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC209_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC209_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC209_IN_INV_SEL_V  0x1
+#define GPIO_FUNC209_IN_INV_SEL_S  6
+/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC209_IN_SEL  0x0000003F
+#define GPIO_FUNC209_IN_SEL_M  ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S))
+#define GPIO_FUNC209_IN_SEL_V  0x3F
+#define GPIO_FUNC209_IN_SEL_S  0
+
+#define GPIO_FUNC210_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x49C)
+/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG210_IN_SEL  (BIT(7))
+#define GPIO_SIG210_IN_SEL_M  (BIT(7))
+#define GPIO_SIG210_IN_SEL_V  0x1
+#define GPIO_SIG210_IN_SEL_S  7
+/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC210_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC210_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC210_IN_INV_SEL_V  0x1
+#define GPIO_FUNC210_IN_INV_SEL_S  6
+/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC210_IN_SEL  0x0000003F
+#define GPIO_FUNC210_IN_SEL_M  ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S))
+#define GPIO_FUNC210_IN_SEL_V  0x3F
+#define GPIO_FUNC210_IN_SEL_S  0
+
+#define GPIO_FUNC211_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A0)
+/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG211_IN_SEL  (BIT(7))
+#define GPIO_SIG211_IN_SEL_M  (BIT(7))
+#define GPIO_SIG211_IN_SEL_V  0x1
+#define GPIO_SIG211_IN_SEL_S  7
+/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC211_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC211_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC211_IN_INV_SEL_V  0x1
+#define GPIO_FUNC211_IN_INV_SEL_S  6
+/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC211_IN_SEL  0x0000003F
+#define GPIO_FUNC211_IN_SEL_M  ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S))
+#define GPIO_FUNC211_IN_SEL_V  0x3F
+#define GPIO_FUNC211_IN_SEL_S  0
+
+#define GPIO_FUNC212_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A4)
+/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG212_IN_SEL  (BIT(7))
+#define GPIO_SIG212_IN_SEL_M  (BIT(7))
+#define GPIO_SIG212_IN_SEL_V  0x1
+#define GPIO_SIG212_IN_SEL_S  7
+/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC212_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC212_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC212_IN_INV_SEL_V  0x1
+#define GPIO_FUNC212_IN_INV_SEL_S  6
+/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC212_IN_SEL  0x0000003F
+#define GPIO_FUNC212_IN_SEL_M  ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S))
+#define GPIO_FUNC212_IN_SEL_V  0x3F
+#define GPIO_FUNC212_IN_SEL_S  0
+
+#define GPIO_FUNC213_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4A8)
+/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG213_IN_SEL  (BIT(7))
+#define GPIO_SIG213_IN_SEL_M  (BIT(7))
+#define GPIO_SIG213_IN_SEL_V  0x1
+#define GPIO_SIG213_IN_SEL_S  7
+/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC213_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC213_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC213_IN_INV_SEL_V  0x1
+#define GPIO_FUNC213_IN_INV_SEL_S  6
+/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC213_IN_SEL  0x0000003F
+#define GPIO_FUNC213_IN_SEL_M  ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S))
+#define GPIO_FUNC213_IN_SEL_V  0x3F
+#define GPIO_FUNC213_IN_SEL_S  0
+
+#define GPIO_FUNC214_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4AC)
+/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG214_IN_SEL  (BIT(7))
+#define GPIO_SIG214_IN_SEL_M  (BIT(7))
+#define GPIO_SIG214_IN_SEL_V  0x1
+#define GPIO_SIG214_IN_SEL_S  7
+/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC214_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC214_IN_INV_SEL_V  0x1
+#define GPIO_FUNC214_IN_INV_SEL_S  6
+/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC214_IN_SEL  0x0000003F
+#define GPIO_FUNC214_IN_SEL_M  ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S))
+#define GPIO_FUNC214_IN_SEL_V  0x3F
+#define GPIO_FUNC214_IN_SEL_S  0
+
+#define GPIO_FUNC215_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B0)
+/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG215_IN_SEL  (BIT(7))
+#define GPIO_SIG215_IN_SEL_M  (BIT(7))
+#define GPIO_SIG215_IN_SEL_V  0x1
+#define GPIO_SIG215_IN_SEL_S  7
+/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC215_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC215_IN_INV_SEL_V  0x1
+#define GPIO_FUNC215_IN_INV_SEL_S  6
+/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC215_IN_SEL  0x0000003F
+#define GPIO_FUNC215_IN_SEL_M  ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S))
+#define GPIO_FUNC215_IN_SEL_V  0x3F
+#define GPIO_FUNC215_IN_SEL_S  0
+
+#define GPIO_FUNC216_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B4)
+/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG216_IN_SEL  (BIT(7))
+#define GPIO_SIG216_IN_SEL_M  (BIT(7))
+#define GPIO_SIG216_IN_SEL_V  0x1
+#define GPIO_SIG216_IN_SEL_S  7
+/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC216_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC216_IN_INV_SEL_V  0x1
+#define GPIO_FUNC216_IN_INV_SEL_S  6
+/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC216_IN_SEL  0x0000003F
+#define GPIO_FUNC216_IN_SEL_M  ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S))
+#define GPIO_FUNC216_IN_SEL_V  0x3F
+#define GPIO_FUNC216_IN_SEL_S  0
+
+#define GPIO_FUNC217_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4B8)
+/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG217_IN_SEL  (BIT(7))
+#define GPIO_SIG217_IN_SEL_M  (BIT(7))
+#define GPIO_SIG217_IN_SEL_V  0x1
+#define GPIO_SIG217_IN_SEL_S  7
+/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC217_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC217_IN_INV_SEL_V  0x1
+#define GPIO_FUNC217_IN_INV_SEL_S  6
+/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC217_IN_SEL  0x0000003F
+#define GPIO_FUNC217_IN_SEL_M  ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S))
+#define GPIO_FUNC217_IN_SEL_V  0x3F
+#define GPIO_FUNC217_IN_SEL_S  0
+
+#define GPIO_FUNC218_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4BC)
+/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG218_IN_SEL  (BIT(7))
+#define GPIO_SIG218_IN_SEL_M  (BIT(7))
+#define GPIO_SIG218_IN_SEL_V  0x1
+#define GPIO_SIG218_IN_SEL_S  7
+/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC218_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC218_IN_INV_SEL_V  0x1
+#define GPIO_FUNC218_IN_INV_SEL_S  6
+/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC218_IN_SEL  0x0000003F
+#define GPIO_FUNC218_IN_SEL_M  ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S))
+#define GPIO_FUNC218_IN_SEL_V  0x3F
+#define GPIO_FUNC218_IN_SEL_S  0
+
+#define GPIO_FUNC219_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C0)
+/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG219_IN_SEL  (BIT(7))
+#define GPIO_SIG219_IN_SEL_M  (BIT(7))
+#define GPIO_SIG219_IN_SEL_V  0x1
+#define GPIO_SIG219_IN_SEL_S  7
+/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC219_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC219_IN_INV_SEL_V  0x1
+#define GPIO_FUNC219_IN_INV_SEL_S  6
+/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC219_IN_SEL  0x0000003F
+#define GPIO_FUNC219_IN_SEL_M  ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S))
+#define GPIO_FUNC219_IN_SEL_V  0x3F
+#define GPIO_FUNC219_IN_SEL_S  0
+
+#define GPIO_FUNC220_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C4)
+/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG220_IN_SEL  (BIT(7))
+#define GPIO_SIG220_IN_SEL_M  (BIT(7))
+#define GPIO_SIG220_IN_SEL_V  0x1
+#define GPIO_SIG220_IN_SEL_S  7
+/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC220_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC220_IN_INV_SEL_V  0x1
+#define GPIO_FUNC220_IN_INV_SEL_S  6
+/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC220_IN_SEL  0x0000003F
+#define GPIO_FUNC220_IN_SEL_M  ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S))
+#define GPIO_FUNC220_IN_SEL_V  0x3F
+#define GPIO_FUNC220_IN_SEL_S  0
+
+#define GPIO_FUNC221_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4C8)
+/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG221_IN_SEL  (BIT(7))
+#define GPIO_SIG221_IN_SEL_M  (BIT(7))
+#define GPIO_SIG221_IN_SEL_V  0x1
+#define GPIO_SIG221_IN_SEL_S  7
+/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC221_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC221_IN_INV_SEL_V  0x1
+#define GPIO_FUNC221_IN_INV_SEL_S  6
+/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC221_IN_SEL  0x0000003F
+#define GPIO_FUNC221_IN_SEL_M  ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S))
+#define GPIO_FUNC221_IN_SEL_V  0x3F
+#define GPIO_FUNC221_IN_SEL_S  0
+
+#define GPIO_FUNC222_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4CC)
+/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG222_IN_SEL  (BIT(7))
+#define GPIO_SIG222_IN_SEL_M  (BIT(7))
+#define GPIO_SIG222_IN_SEL_V  0x1
+#define GPIO_SIG222_IN_SEL_S  7
+/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC222_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC222_IN_INV_SEL_V  0x1
+#define GPIO_FUNC222_IN_INV_SEL_S  6
+/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC222_IN_SEL  0x0000003F
+#define GPIO_FUNC222_IN_SEL_M  ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S))
+#define GPIO_FUNC222_IN_SEL_V  0x3F
+#define GPIO_FUNC222_IN_SEL_S  0
+
+#define GPIO_FUNC223_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D0)
+/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG223_IN_SEL  (BIT(7))
+#define GPIO_SIG223_IN_SEL_M  (BIT(7))
+#define GPIO_SIG223_IN_SEL_V  0x1
+#define GPIO_SIG223_IN_SEL_S  7
+/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC223_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC223_IN_INV_SEL_V  0x1
+#define GPIO_FUNC223_IN_INV_SEL_S  6
+/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC223_IN_SEL  0x0000003F
+#define GPIO_FUNC223_IN_SEL_M  ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S))
+#define GPIO_FUNC223_IN_SEL_V  0x3F
+#define GPIO_FUNC223_IN_SEL_S  0
+
+#define GPIO_FUNC224_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D4)
+/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG224_IN_SEL  (BIT(7))
+#define GPIO_SIG224_IN_SEL_M  (BIT(7))
+#define GPIO_SIG224_IN_SEL_V  0x1
+#define GPIO_SIG224_IN_SEL_S  7
+/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC224_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC224_IN_INV_SEL_V  0x1
+#define GPIO_FUNC224_IN_INV_SEL_S  6
+/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC224_IN_SEL  0x0000003F
+#define GPIO_FUNC224_IN_SEL_M  ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S))
+#define GPIO_FUNC224_IN_SEL_V  0x3F
+#define GPIO_FUNC224_IN_SEL_S  0
+
+#define GPIO_FUNC225_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4D8)
+/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG225_IN_SEL  (BIT(7))
+#define GPIO_SIG225_IN_SEL_M  (BIT(7))
+#define GPIO_SIG225_IN_SEL_V  0x1
+#define GPIO_SIG225_IN_SEL_S  7
+/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC225_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC225_IN_INV_SEL_V  0x1
+#define GPIO_FUNC225_IN_INV_SEL_S  6
+/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC225_IN_SEL  0x0000003F
+#define GPIO_FUNC225_IN_SEL_M  ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S))
+#define GPIO_FUNC225_IN_SEL_V  0x3F
+#define GPIO_FUNC225_IN_SEL_S  0
+
+#define GPIO_FUNC226_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4DC)
+/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG226_IN_SEL  (BIT(7))
+#define GPIO_SIG226_IN_SEL_M  (BIT(7))
+#define GPIO_SIG226_IN_SEL_V  0x1
+#define GPIO_SIG226_IN_SEL_S  7
+/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC226_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC226_IN_INV_SEL_V  0x1
+#define GPIO_FUNC226_IN_INV_SEL_S  6
+/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC226_IN_SEL  0x0000003F
+#define GPIO_FUNC226_IN_SEL_M  ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S))
+#define GPIO_FUNC226_IN_SEL_V  0x3F
+#define GPIO_FUNC226_IN_SEL_S  0
+
+#define GPIO_FUNC227_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E0)
+/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG227_IN_SEL  (BIT(7))
+#define GPIO_SIG227_IN_SEL_M  (BIT(7))
+#define GPIO_SIG227_IN_SEL_V  0x1
+#define GPIO_SIG227_IN_SEL_S  7
+/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC227_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC227_IN_INV_SEL_V  0x1
+#define GPIO_FUNC227_IN_INV_SEL_S  6
+/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC227_IN_SEL  0x0000003F
+#define GPIO_FUNC227_IN_SEL_M  ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S))
+#define GPIO_FUNC227_IN_SEL_V  0x3F
+#define GPIO_FUNC227_IN_SEL_S  0
+
+#define GPIO_FUNC228_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E4)
+/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG228_IN_SEL  (BIT(7))
+#define GPIO_SIG228_IN_SEL_M  (BIT(7))
+#define GPIO_SIG228_IN_SEL_V  0x1
+#define GPIO_SIG228_IN_SEL_S  7
+/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC228_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC228_IN_INV_SEL_V  0x1
+#define GPIO_FUNC228_IN_INV_SEL_S  6
+/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC228_IN_SEL  0x0000003F
+#define GPIO_FUNC228_IN_SEL_M  ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S))
+#define GPIO_FUNC228_IN_SEL_V  0x3F
+#define GPIO_FUNC228_IN_SEL_S  0
+
+#define GPIO_FUNC229_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4E8)
+/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG229_IN_SEL  (BIT(7))
+#define GPIO_SIG229_IN_SEL_M  (BIT(7))
+#define GPIO_SIG229_IN_SEL_V  0x1
+#define GPIO_SIG229_IN_SEL_S  7
+/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC229_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC229_IN_INV_SEL_V  0x1
+#define GPIO_FUNC229_IN_INV_SEL_S  6
+/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC229_IN_SEL  0x0000003F
+#define GPIO_FUNC229_IN_SEL_M  ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S))
+#define GPIO_FUNC229_IN_SEL_V  0x3F
+#define GPIO_FUNC229_IN_SEL_S  0
+
+#define GPIO_FUNC230_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4EC)
+/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG230_IN_SEL  (BIT(7))
+#define GPIO_SIG230_IN_SEL_M  (BIT(7))
+#define GPIO_SIG230_IN_SEL_V  0x1
+#define GPIO_SIG230_IN_SEL_S  7
+/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC230_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC230_IN_INV_SEL_V  0x1
+#define GPIO_FUNC230_IN_INV_SEL_S  6
+/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC230_IN_SEL  0x0000003F
+#define GPIO_FUNC230_IN_SEL_M  ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S))
+#define GPIO_FUNC230_IN_SEL_V  0x3F
+#define GPIO_FUNC230_IN_SEL_S  0
+
+#define GPIO_FUNC231_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F0)
+/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG231_IN_SEL  (BIT(7))
+#define GPIO_SIG231_IN_SEL_M  (BIT(7))
+#define GPIO_SIG231_IN_SEL_V  0x1
+#define GPIO_SIG231_IN_SEL_S  7
+/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC231_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC231_IN_INV_SEL_V  0x1
+#define GPIO_FUNC231_IN_INV_SEL_S  6
+/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC231_IN_SEL  0x0000003F
+#define GPIO_FUNC231_IN_SEL_M  ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S))
+#define GPIO_FUNC231_IN_SEL_V  0x3F
+#define GPIO_FUNC231_IN_SEL_S  0
+
+#define GPIO_FUNC232_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F4)
+/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG232_IN_SEL  (BIT(7))
+#define GPIO_SIG232_IN_SEL_M  (BIT(7))
+#define GPIO_SIG232_IN_SEL_V  0x1
+#define GPIO_SIG232_IN_SEL_S  7
+/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC232_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC232_IN_INV_SEL_V  0x1
+#define GPIO_FUNC232_IN_INV_SEL_S  6
+/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC232_IN_SEL  0x0000003F
+#define GPIO_FUNC232_IN_SEL_M  ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S))
+#define GPIO_FUNC232_IN_SEL_V  0x3F
+#define GPIO_FUNC232_IN_SEL_S  0
+
+#define GPIO_FUNC233_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4F8)
+/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG233_IN_SEL  (BIT(7))
+#define GPIO_SIG233_IN_SEL_M  (BIT(7))
+#define GPIO_SIG233_IN_SEL_V  0x1
+#define GPIO_SIG233_IN_SEL_S  7
+/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC233_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC233_IN_INV_SEL_V  0x1
+#define GPIO_FUNC233_IN_INV_SEL_S  6
+/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC233_IN_SEL  0x0000003F
+#define GPIO_FUNC233_IN_SEL_M  ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S))
+#define GPIO_FUNC233_IN_SEL_V  0x3F
+#define GPIO_FUNC233_IN_SEL_S  0
+
+#define GPIO_FUNC234_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x4FC)
+/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG234_IN_SEL  (BIT(7))
+#define GPIO_SIG234_IN_SEL_M  (BIT(7))
+#define GPIO_SIG234_IN_SEL_V  0x1
+#define GPIO_SIG234_IN_SEL_S  7
+/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC234_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC234_IN_INV_SEL_V  0x1
+#define GPIO_FUNC234_IN_INV_SEL_S  6
+/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC234_IN_SEL  0x0000003F
+#define GPIO_FUNC234_IN_SEL_M  ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S))
+#define GPIO_FUNC234_IN_SEL_V  0x3F
+#define GPIO_FUNC234_IN_SEL_S  0
+
+#define GPIO_FUNC235_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x500)
+/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG235_IN_SEL  (BIT(7))
+#define GPIO_SIG235_IN_SEL_M  (BIT(7))
+#define GPIO_SIG235_IN_SEL_V  0x1
+#define GPIO_SIG235_IN_SEL_S  7
+/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC235_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC235_IN_INV_SEL_V  0x1
+#define GPIO_FUNC235_IN_INV_SEL_S  6
+/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC235_IN_SEL  0x0000003F
+#define GPIO_FUNC235_IN_SEL_M  ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S))
+#define GPIO_FUNC235_IN_SEL_V  0x3F
+#define GPIO_FUNC235_IN_SEL_S  0
+
+#define GPIO_FUNC236_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x504)
+/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG236_IN_SEL  (BIT(7))
+#define GPIO_SIG236_IN_SEL_M  (BIT(7))
+#define GPIO_SIG236_IN_SEL_V  0x1
+#define GPIO_SIG236_IN_SEL_S  7
+/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC236_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC236_IN_INV_SEL_V  0x1
+#define GPIO_FUNC236_IN_INV_SEL_S  6
+/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC236_IN_SEL  0x0000003F
+#define GPIO_FUNC236_IN_SEL_M  ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S))
+#define GPIO_FUNC236_IN_SEL_V  0x3F
+#define GPIO_FUNC236_IN_SEL_S  0
+
+#define GPIO_FUNC237_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x508)
+/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG237_IN_SEL  (BIT(7))
+#define GPIO_SIG237_IN_SEL_M  (BIT(7))
+#define GPIO_SIG237_IN_SEL_V  0x1
+#define GPIO_SIG237_IN_SEL_S  7
+/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC237_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC237_IN_INV_SEL_V  0x1
+#define GPIO_FUNC237_IN_INV_SEL_S  6
+/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC237_IN_SEL  0x0000003F
+#define GPIO_FUNC237_IN_SEL_M  ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S))
+#define GPIO_FUNC237_IN_SEL_V  0x3F
+#define GPIO_FUNC237_IN_SEL_S  0
+
+#define GPIO_FUNC238_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x50C)
+/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG238_IN_SEL  (BIT(7))
+#define GPIO_SIG238_IN_SEL_M  (BIT(7))
+#define GPIO_SIG238_IN_SEL_V  0x1
+#define GPIO_SIG238_IN_SEL_S  7
+/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC238_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC238_IN_INV_SEL_V  0x1
+#define GPIO_FUNC238_IN_INV_SEL_S  6
+/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC238_IN_SEL  0x0000003F
+#define GPIO_FUNC238_IN_SEL_M  ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S))
+#define GPIO_FUNC238_IN_SEL_V  0x3F
+#define GPIO_FUNC238_IN_SEL_S  0
+
+#define GPIO_FUNC239_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x510)
+/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG239_IN_SEL  (BIT(7))
+#define GPIO_SIG239_IN_SEL_M  (BIT(7))
+#define GPIO_SIG239_IN_SEL_V  0x1
+#define GPIO_SIG239_IN_SEL_S  7
+/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC239_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC239_IN_INV_SEL_V  0x1
+#define GPIO_FUNC239_IN_INV_SEL_S  6
+/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC239_IN_SEL  0x0000003F
+#define GPIO_FUNC239_IN_SEL_M  ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S))
+#define GPIO_FUNC239_IN_SEL_V  0x3F
+#define GPIO_FUNC239_IN_SEL_S  0
+
+#define GPIO_FUNC240_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x514)
+/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG240_IN_SEL  (BIT(7))
+#define GPIO_SIG240_IN_SEL_M  (BIT(7))
+#define GPIO_SIG240_IN_SEL_V  0x1
+#define GPIO_SIG240_IN_SEL_S  7
+/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC240_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC240_IN_INV_SEL_V  0x1
+#define GPIO_FUNC240_IN_INV_SEL_S  6
+/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC240_IN_SEL  0x0000003F
+#define GPIO_FUNC240_IN_SEL_M  ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S))
+#define GPIO_FUNC240_IN_SEL_V  0x3F
+#define GPIO_FUNC240_IN_SEL_S  0
+
+#define GPIO_FUNC241_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x518)
+/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG241_IN_SEL  (BIT(7))
+#define GPIO_SIG241_IN_SEL_M  (BIT(7))
+#define GPIO_SIG241_IN_SEL_V  0x1
+#define GPIO_SIG241_IN_SEL_S  7
+/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC241_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC241_IN_INV_SEL_V  0x1
+#define GPIO_FUNC241_IN_INV_SEL_S  6
+/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC241_IN_SEL  0x0000003F
+#define GPIO_FUNC241_IN_SEL_M  ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S))
+#define GPIO_FUNC241_IN_SEL_V  0x3F
+#define GPIO_FUNC241_IN_SEL_S  0
+
+#define GPIO_FUNC242_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x51C)
+/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG242_IN_SEL  (BIT(7))
+#define GPIO_SIG242_IN_SEL_M  (BIT(7))
+#define GPIO_SIG242_IN_SEL_V  0x1
+#define GPIO_SIG242_IN_SEL_S  7
+/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC242_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC242_IN_INV_SEL_V  0x1
+#define GPIO_FUNC242_IN_INV_SEL_S  6
+/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC242_IN_SEL  0x0000003F
+#define GPIO_FUNC242_IN_SEL_M  ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S))
+#define GPIO_FUNC242_IN_SEL_V  0x3F
+#define GPIO_FUNC242_IN_SEL_S  0
+
+#define GPIO_FUNC243_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x520)
+/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG243_IN_SEL  (BIT(7))
+#define GPIO_SIG243_IN_SEL_M  (BIT(7))
+#define GPIO_SIG243_IN_SEL_V  0x1
+#define GPIO_SIG243_IN_SEL_S  7
+/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC243_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC243_IN_INV_SEL_V  0x1
+#define GPIO_FUNC243_IN_INV_SEL_S  6
+/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC243_IN_SEL  0x0000003F
+#define GPIO_FUNC243_IN_SEL_M  ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S))
+#define GPIO_FUNC243_IN_SEL_V  0x3F
+#define GPIO_FUNC243_IN_SEL_S  0
+
+#define GPIO_FUNC244_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x524)
+/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG244_IN_SEL  (BIT(7))
+#define GPIO_SIG244_IN_SEL_M  (BIT(7))
+#define GPIO_SIG244_IN_SEL_V  0x1
+#define GPIO_SIG244_IN_SEL_S  7
+/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC244_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC244_IN_INV_SEL_V  0x1
+#define GPIO_FUNC244_IN_INV_SEL_S  6
+/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC244_IN_SEL  0x0000003F
+#define GPIO_FUNC244_IN_SEL_M  ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S))
+#define GPIO_FUNC244_IN_SEL_V  0x3F
+#define GPIO_FUNC244_IN_SEL_S  0
+
+#define GPIO_FUNC245_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x528)
+/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG245_IN_SEL  (BIT(7))
+#define GPIO_SIG245_IN_SEL_M  (BIT(7))
+#define GPIO_SIG245_IN_SEL_V  0x1
+#define GPIO_SIG245_IN_SEL_S  7
+/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC245_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC245_IN_INV_SEL_V  0x1
+#define GPIO_FUNC245_IN_INV_SEL_S  6
+/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC245_IN_SEL  0x0000003F
+#define GPIO_FUNC245_IN_SEL_M  ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S))
+#define GPIO_FUNC245_IN_SEL_V  0x3F
+#define GPIO_FUNC245_IN_SEL_S  0
+
+#define GPIO_FUNC246_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x52C)
+/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG246_IN_SEL  (BIT(7))
+#define GPIO_SIG246_IN_SEL_M  (BIT(7))
+#define GPIO_SIG246_IN_SEL_V  0x1
+#define GPIO_SIG246_IN_SEL_S  7
+/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC246_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC246_IN_INV_SEL_V  0x1
+#define GPIO_FUNC246_IN_INV_SEL_S  6
+/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC246_IN_SEL  0x0000003F
+#define GPIO_FUNC246_IN_SEL_M  ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S))
+#define GPIO_FUNC246_IN_SEL_V  0x3F
+#define GPIO_FUNC246_IN_SEL_S  0
+
+#define GPIO_FUNC247_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x530)
+/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG247_IN_SEL  (BIT(7))
+#define GPIO_SIG247_IN_SEL_M  (BIT(7))
+#define GPIO_SIG247_IN_SEL_V  0x1
+#define GPIO_SIG247_IN_SEL_S  7
+/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC247_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC247_IN_INV_SEL_V  0x1
+#define GPIO_FUNC247_IN_INV_SEL_S  6
+/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC247_IN_SEL  0x0000003F
+#define GPIO_FUNC247_IN_SEL_M  ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S))
+#define GPIO_FUNC247_IN_SEL_V  0x3F
+#define GPIO_FUNC247_IN_SEL_S  0
+
+#define GPIO_FUNC248_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x534)
+/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG248_IN_SEL  (BIT(7))
+#define GPIO_SIG248_IN_SEL_M  (BIT(7))
+#define GPIO_SIG248_IN_SEL_V  0x1
+#define GPIO_SIG248_IN_SEL_S  7
+/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC248_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC248_IN_INV_SEL_V  0x1
+#define GPIO_FUNC248_IN_INV_SEL_S  6
+/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC248_IN_SEL  0x0000003F
+#define GPIO_FUNC248_IN_SEL_M  ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S))
+#define GPIO_FUNC248_IN_SEL_V  0x3F
+#define GPIO_FUNC248_IN_SEL_S  0
+
+#define GPIO_FUNC249_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x538)
+/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG249_IN_SEL  (BIT(7))
+#define GPIO_SIG249_IN_SEL_M  (BIT(7))
+#define GPIO_SIG249_IN_SEL_V  0x1
+#define GPIO_SIG249_IN_SEL_S  7
+/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC249_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC249_IN_INV_SEL_V  0x1
+#define GPIO_FUNC249_IN_INV_SEL_S  6
+/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC249_IN_SEL  0x0000003F
+#define GPIO_FUNC249_IN_SEL_M  ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S))
+#define GPIO_FUNC249_IN_SEL_V  0x3F
+#define GPIO_FUNC249_IN_SEL_S  0
+
+#define GPIO_FUNC250_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x53C)
+/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG250_IN_SEL  (BIT(7))
+#define GPIO_SIG250_IN_SEL_M  (BIT(7))
+#define GPIO_SIG250_IN_SEL_V  0x1
+#define GPIO_SIG250_IN_SEL_S  7
+/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC250_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC250_IN_INV_SEL_V  0x1
+#define GPIO_FUNC250_IN_INV_SEL_S  6
+/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC250_IN_SEL  0x0000003F
+#define GPIO_FUNC250_IN_SEL_M  ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S))
+#define GPIO_FUNC250_IN_SEL_V  0x3F
+#define GPIO_FUNC250_IN_SEL_S  0
+
+#define GPIO_FUNC251_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x540)
+/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG251_IN_SEL  (BIT(7))
+#define GPIO_SIG251_IN_SEL_M  (BIT(7))
+#define GPIO_SIG251_IN_SEL_V  0x1
+#define GPIO_SIG251_IN_SEL_S  7
+/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC251_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC251_IN_INV_SEL_V  0x1
+#define GPIO_FUNC251_IN_INV_SEL_S  6
+/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC251_IN_SEL  0x0000003F
+#define GPIO_FUNC251_IN_SEL_M  ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S))
+#define GPIO_FUNC251_IN_SEL_V  0x3F
+#define GPIO_FUNC251_IN_SEL_S  0
+
+#define GPIO_FUNC252_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x544)
+/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG252_IN_SEL  (BIT(7))
+#define GPIO_SIG252_IN_SEL_M  (BIT(7))
+#define GPIO_SIG252_IN_SEL_V  0x1
+#define GPIO_SIG252_IN_SEL_S  7
+/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC252_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC252_IN_INV_SEL_V  0x1
+#define GPIO_FUNC252_IN_INV_SEL_S  6
+/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC252_IN_SEL  0x0000003F
+#define GPIO_FUNC252_IN_SEL_M  ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S))
+#define GPIO_FUNC252_IN_SEL_V  0x3F
+#define GPIO_FUNC252_IN_SEL_S  0
+
+#define GPIO_FUNC253_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x548)
+/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG253_IN_SEL  (BIT(7))
+#define GPIO_SIG253_IN_SEL_M  (BIT(7))
+#define GPIO_SIG253_IN_SEL_V  0x1
+#define GPIO_SIG253_IN_SEL_S  7
+/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC253_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC253_IN_INV_SEL_V  0x1
+#define GPIO_FUNC253_IN_INV_SEL_S  6
+/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC253_IN_SEL  0x0000003F
+#define GPIO_FUNC253_IN_SEL_M  ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S))
+#define GPIO_FUNC253_IN_SEL_V  0x3F
+#define GPIO_FUNC253_IN_SEL_S  0
+
+#define GPIO_FUNC254_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x54C)
+/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG254_IN_SEL  (BIT(7))
+#define GPIO_SIG254_IN_SEL_M  (BIT(7))
+#define GPIO_SIG254_IN_SEL_V  0x1
+#define GPIO_SIG254_IN_SEL_S  7
+/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC254_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC254_IN_INV_SEL_V  0x1
+#define GPIO_FUNC254_IN_INV_SEL_S  6
+/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC254_IN_SEL  0x0000003F
+#define GPIO_FUNC254_IN_SEL_M  ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S))
+#define GPIO_FUNC254_IN_SEL_V  0x3F
+#define GPIO_FUNC254_IN_SEL_S  0
+
+#define GPIO_FUNC255_IN_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x550)
+/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SIG255_IN_SEL  (BIT(7))
+#define GPIO_SIG255_IN_SEL_M  (BIT(7))
+#define GPIO_SIG255_IN_SEL_V  0x1
+#define GPIO_SIG255_IN_SEL_S  7
+/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC255_IN_INV_SEL  (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_M  (BIT(6))
+#define GPIO_FUNC255_IN_INV_SEL_V  0x1
+#define GPIO_FUNC255_IN_INV_SEL_S  6
+/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */
+/*description: */
+#define GPIO_FUNC255_IN_SEL  0x0000003F
+#define GPIO_FUNC255_IN_SEL_M  ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S))
+#define GPIO_FUNC255_IN_SEL_V  0x3F
+#define GPIO_FUNC255_IN_SEL_S  0
+
+#define GPIO_FUNC0_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x554)
+/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC0_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC0_OEN_INV_SEL_S  11
+/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OEN_SEL  (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC0_OEN_SEL_V  0x1
+#define GPIO_FUNC0_OEN_SEL_S  10
+/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC0_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC0_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC0_OUT_INV_SEL_S  9
+/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC0_OUT_SEL  0x000001FF
+#define GPIO_FUNC0_OUT_SEL_M  ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S))
+#define GPIO_FUNC0_OUT_SEL_V  0x1FF
+#define GPIO_FUNC0_OUT_SEL_S  0
+
+#define GPIO_FUNC1_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x558)
+/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC1_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC1_OEN_INV_SEL_S  11
+/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OEN_SEL  (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC1_OEN_SEL_V  0x1
+#define GPIO_FUNC1_OEN_SEL_S  10
+/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC1_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC1_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC1_OUT_INV_SEL_S  9
+/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC1_OUT_SEL  0x000001FF
+#define GPIO_FUNC1_OUT_SEL_M  ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S))
+#define GPIO_FUNC1_OUT_SEL_V  0x1FF
+#define GPIO_FUNC1_OUT_SEL_S  0
+
+#define GPIO_FUNC2_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x55C)
+/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC2_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC2_OEN_INV_SEL_S  11
+/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OEN_SEL  (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC2_OEN_SEL_V  0x1
+#define GPIO_FUNC2_OEN_SEL_S  10
+/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC2_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC2_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC2_OUT_INV_SEL_S  9
+/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC2_OUT_SEL  0x000001FF
+#define GPIO_FUNC2_OUT_SEL_M  ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S))
+#define GPIO_FUNC2_OUT_SEL_V  0x1FF
+#define GPIO_FUNC2_OUT_SEL_S  0
+
+#define GPIO_FUNC3_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x560)
+/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC3_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC3_OEN_INV_SEL_S  11
+/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OEN_SEL  (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC3_OEN_SEL_V  0x1
+#define GPIO_FUNC3_OEN_SEL_S  10
+/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC3_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC3_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC3_OUT_INV_SEL_S  9
+/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC3_OUT_SEL  0x000001FF
+#define GPIO_FUNC3_OUT_SEL_M  ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S))
+#define GPIO_FUNC3_OUT_SEL_V  0x1FF
+#define GPIO_FUNC3_OUT_SEL_S  0
+
+#define GPIO_FUNC4_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x564)
+/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC4_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC4_OEN_INV_SEL_S  11
+/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OEN_SEL  (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC4_OEN_SEL_V  0x1
+#define GPIO_FUNC4_OEN_SEL_S  10
+/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC4_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC4_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC4_OUT_INV_SEL_S  9
+/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC4_OUT_SEL  0x000001FF
+#define GPIO_FUNC4_OUT_SEL_M  ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S))
+#define GPIO_FUNC4_OUT_SEL_V  0x1FF
+#define GPIO_FUNC4_OUT_SEL_S  0
+
+#define GPIO_FUNC5_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x568)
+/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC5_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC5_OEN_INV_SEL_S  11
+/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OEN_SEL  (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC5_OEN_SEL_V  0x1
+#define GPIO_FUNC5_OEN_SEL_S  10
+/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC5_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC5_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC5_OUT_INV_SEL_S  9
+/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC5_OUT_SEL  0x000001FF
+#define GPIO_FUNC5_OUT_SEL_M  ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S))
+#define GPIO_FUNC5_OUT_SEL_V  0x1FF
+#define GPIO_FUNC5_OUT_SEL_S  0
+
+#define GPIO_FUNC6_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x56C)
+/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC6_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC6_OEN_INV_SEL_S  11
+/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OEN_SEL  (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC6_OEN_SEL_V  0x1
+#define GPIO_FUNC6_OEN_SEL_S  10
+/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC6_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC6_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC6_OUT_INV_SEL_S  9
+/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC6_OUT_SEL  0x000001FF
+#define GPIO_FUNC6_OUT_SEL_M  ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S))
+#define GPIO_FUNC6_OUT_SEL_V  0x1FF
+#define GPIO_FUNC6_OUT_SEL_S  0
+
+#define GPIO_FUNC7_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x570)
+/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC7_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC7_OEN_INV_SEL_S  11
+/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OEN_SEL  (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC7_OEN_SEL_V  0x1
+#define GPIO_FUNC7_OEN_SEL_S  10
+/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC7_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC7_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC7_OUT_INV_SEL_S  9
+/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC7_OUT_SEL  0x000001FF
+#define GPIO_FUNC7_OUT_SEL_M  ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S))
+#define GPIO_FUNC7_OUT_SEL_V  0x1FF
+#define GPIO_FUNC7_OUT_SEL_S  0
+
+#define GPIO_FUNC8_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x574)
+/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC8_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC8_OEN_INV_SEL_S  11
+/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OEN_SEL  (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC8_OEN_SEL_V  0x1
+#define GPIO_FUNC8_OEN_SEL_S  10
+/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC8_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC8_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC8_OUT_INV_SEL_S  9
+/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC8_OUT_SEL  0x000001FF
+#define GPIO_FUNC8_OUT_SEL_M  ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S))
+#define GPIO_FUNC8_OUT_SEL_V  0x1FF
+#define GPIO_FUNC8_OUT_SEL_S  0
+
+#define GPIO_FUNC9_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x578)
+/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC9_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC9_OEN_INV_SEL_S  11
+/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OEN_SEL  (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC9_OEN_SEL_V  0x1
+#define GPIO_FUNC9_OEN_SEL_S  10
+/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC9_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC9_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC9_OUT_INV_SEL_S  9
+/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC9_OUT_SEL  0x000001FF
+#define GPIO_FUNC9_OUT_SEL_M  ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S))
+#define GPIO_FUNC9_OUT_SEL_V  0x1FF
+#define GPIO_FUNC9_OUT_SEL_S  0
+
+#define GPIO_FUNC10_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x57C)
+/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC10_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC10_OEN_INV_SEL_S  11
+/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OEN_SEL  (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC10_OEN_SEL_V  0x1
+#define GPIO_FUNC10_OEN_SEL_S  10
+/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC10_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC10_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC10_OUT_INV_SEL_S  9
+/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC10_OUT_SEL  0x000001FF
+#define GPIO_FUNC10_OUT_SEL_M  ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S))
+#define GPIO_FUNC10_OUT_SEL_V  0x1FF
+#define GPIO_FUNC10_OUT_SEL_S  0
+
+#define GPIO_FUNC11_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x580)
+/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC11_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC11_OEN_INV_SEL_S  11
+/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OEN_SEL  (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC11_OEN_SEL_V  0x1
+#define GPIO_FUNC11_OEN_SEL_S  10
+/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC11_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC11_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC11_OUT_INV_SEL_S  9
+/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC11_OUT_SEL  0x000001FF
+#define GPIO_FUNC11_OUT_SEL_M  ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S))
+#define GPIO_FUNC11_OUT_SEL_V  0x1FF
+#define GPIO_FUNC11_OUT_SEL_S  0
+
+#define GPIO_FUNC12_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x584)
+/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC12_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC12_OEN_INV_SEL_S  11
+/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OEN_SEL  (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC12_OEN_SEL_V  0x1
+#define GPIO_FUNC12_OEN_SEL_S  10
+/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC12_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC12_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC12_OUT_INV_SEL_S  9
+/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC12_OUT_SEL  0x000001FF
+#define GPIO_FUNC12_OUT_SEL_M  ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S))
+#define GPIO_FUNC12_OUT_SEL_V  0x1FF
+#define GPIO_FUNC12_OUT_SEL_S  0
+
+#define GPIO_FUNC13_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x588)
+/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC13_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC13_OEN_INV_SEL_S  11
+/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OEN_SEL  (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC13_OEN_SEL_V  0x1
+#define GPIO_FUNC13_OEN_SEL_S  10
+/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC13_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC13_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC13_OUT_INV_SEL_S  9
+/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC13_OUT_SEL  0x000001FF
+#define GPIO_FUNC13_OUT_SEL_M  ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S))
+#define GPIO_FUNC13_OUT_SEL_V  0x1FF
+#define GPIO_FUNC13_OUT_SEL_S  0
+
+#define GPIO_FUNC14_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x58C)
+/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC14_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC14_OEN_INV_SEL_S  11
+/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OEN_SEL  (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC14_OEN_SEL_V  0x1
+#define GPIO_FUNC14_OEN_SEL_S  10
+/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC14_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC14_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC14_OUT_INV_SEL_S  9
+/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC14_OUT_SEL  0x000001FF
+#define GPIO_FUNC14_OUT_SEL_M  ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S))
+#define GPIO_FUNC14_OUT_SEL_V  0x1FF
+#define GPIO_FUNC14_OUT_SEL_S  0
+
+#define GPIO_FUNC15_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x590)
+/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC15_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC15_OEN_INV_SEL_S  11
+/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OEN_SEL  (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC15_OEN_SEL_V  0x1
+#define GPIO_FUNC15_OEN_SEL_S  10
+/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC15_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC15_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC15_OUT_INV_SEL_S  9
+/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC15_OUT_SEL  0x000001FF
+#define GPIO_FUNC15_OUT_SEL_M  ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S))
+#define GPIO_FUNC15_OUT_SEL_V  0x1FF
+#define GPIO_FUNC15_OUT_SEL_S  0
+
+#define GPIO_FUNC16_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x594)
+/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC16_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC16_OEN_INV_SEL_S  11
+/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OEN_SEL  (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC16_OEN_SEL_V  0x1
+#define GPIO_FUNC16_OEN_SEL_S  10
+/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC16_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC16_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC16_OUT_INV_SEL_S  9
+/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC16_OUT_SEL  0x000001FF
+#define GPIO_FUNC16_OUT_SEL_M  ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S))
+#define GPIO_FUNC16_OUT_SEL_V  0x1FF
+#define GPIO_FUNC16_OUT_SEL_S  0
+
+#define GPIO_FUNC17_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x598)
+/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC17_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC17_OEN_INV_SEL_S  11
+/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OEN_SEL  (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC17_OEN_SEL_V  0x1
+#define GPIO_FUNC17_OEN_SEL_S  10
+/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC17_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC17_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC17_OUT_INV_SEL_S  9
+/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC17_OUT_SEL  0x000001FF
+#define GPIO_FUNC17_OUT_SEL_M  ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S))
+#define GPIO_FUNC17_OUT_SEL_V  0x1FF
+#define GPIO_FUNC17_OUT_SEL_S  0
+
+#define GPIO_FUNC18_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x59C)
+/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC18_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC18_OEN_INV_SEL_S  11
+/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OEN_SEL  (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC18_OEN_SEL_V  0x1
+#define GPIO_FUNC18_OEN_SEL_S  10
+/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC18_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC18_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC18_OUT_INV_SEL_S  9
+/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC18_OUT_SEL  0x000001FF
+#define GPIO_FUNC18_OUT_SEL_M  ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S))
+#define GPIO_FUNC18_OUT_SEL_V  0x1FF
+#define GPIO_FUNC18_OUT_SEL_S  0
+
+#define GPIO_FUNC19_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A0)
+/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC19_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC19_OEN_INV_SEL_S  11
+/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OEN_SEL  (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC19_OEN_SEL_V  0x1
+#define GPIO_FUNC19_OEN_SEL_S  10
+/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC19_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC19_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC19_OUT_INV_SEL_S  9
+/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC19_OUT_SEL  0x000001FF
+#define GPIO_FUNC19_OUT_SEL_M  ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S))
+#define GPIO_FUNC19_OUT_SEL_V  0x1FF
+#define GPIO_FUNC19_OUT_SEL_S  0
+
+#define GPIO_FUNC20_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A4)
+/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC20_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC20_OEN_INV_SEL_S  11
+/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OEN_SEL  (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC20_OEN_SEL_V  0x1
+#define GPIO_FUNC20_OEN_SEL_S  10
+/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC20_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC20_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC20_OUT_INV_SEL_S  9
+/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC20_OUT_SEL  0x000001FF
+#define GPIO_FUNC20_OUT_SEL_M  ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S))
+#define GPIO_FUNC20_OUT_SEL_V  0x1FF
+#define GPIO_FUNC20_OUT_SEL_S  0
+
+#define GPIO_FUNC21_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5A8)
+/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC21_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC21_OEN_INV_SEL_S  11
+/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OEN_SEL  (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC21_OEN_SEL_V  0x1
+#define GPIO_FUNC21_OEN_SEL_S  10
+/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC21_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC21_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC21_OUT_INV_SEL_S  9
+/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC21_OUT_SEL  0x000001FF
+#define GPIO_FUNC21_OUT_SEL_M  ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S))
+#define GPIO_FUNC21_OUT_SEL_V  0x1FF
+#define GPIO_FUNC21_OUT_SEL_S  0
+
+#define GPIO_FUNC22_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5AC)
+/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC22_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC22_OEN_INV_SEL_S  11
+/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OEN_SEL  (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC22_OEN_SEL_V  0x1
+#define GPIO_FUNC22_OEN_SEL_S  10
+/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC22_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC22_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC22_OUT_INV_SEL_S  9
+/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC22_OUT_SEL  0x000001FF
+#define GPIO_FUNC22_OUT_SEL_M  ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S))
+#define GPIO_FUNC22_OUT_SEL_V  0x1FF
+#define GPIO_FUNC22_OUT_SEL_S  0
+
+#define GPIO_FUNC23_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B0)
+/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC23_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC23_OEN_INV_SEL_S  11
+/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OEN_SEL  (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC23_OEN_SEL_V  0x1
+#define GPIO_FUNC23_OEN_SEL_S  10
+/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC23_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC23_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC23_OUT_INV_SEL_S  9
+/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC23_OUT_SEL  0x000001FF
+#define GPIO_FUNC23_OUT_SEL_M  ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S))
+#define GPIO_FUNC23_OUT_SEL_V  0x1FF
+#define GPIO_FUNC23_OUT_SEL_S  0
+
+#define GPIO_FUNC24_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B4)
+/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC24_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC24_OEN_INV_SEL_S  11
+/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OEN_SEL  (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC24_OEN_SEL_V  0x1
+#define GPIO_FUNC24_OEN_SEL_S  10
+/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC24_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC24_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC24_OUT_INV_SEL_S  9
+/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC24_OUT_SEL  0x000001FF
+#define GPIO_FUNC24_OUT_SEL_M  ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S))
+#define GPIO_FUNC24_OUT_SEL_V  0x1FF
+#define GPIO_FUNC24_OUT_SEL_S  0
+
+#define GPIO_FUNC25_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5B8)
+/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC25_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC25_OEN_INV_SEL_S  11
+/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OEN_SEL  (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC25_OEN_SEL_V  0x1
+#define GPIO_FUNC25_OEN_SEL_S  10
+/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC25_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC25_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC25_OUT_INV_SEL_S  9
+/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC25_OUT_SEL  0x000001FF
+#define GPIO_FUNC25_OUT_SEL_M  ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S))
+#define GPIO_FUNC25_OUT_SEL_V  0x1FF
+#define GPIO_FUNC25_OUT_SEL_S  0
+
+#define GPIO_FUNC26_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5BC)
+/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC26_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC26_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC26_OEN_INV_SEL_S  11
+/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC26_OEN_SEL  (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC26_OEN_SEL_V  0x1
+#define GPIO_FUNC26_OEN_SEL_S  10
+/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC26_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC26_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC26_OUT_INV_SEL_S  9
+/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC26_OUT_SEL  0x000001FF
+#define GPIO_FUNC26_OUT_SEL_M  ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S))
+#define GPIO_FUNC26_OUT_SEL_V  0x1FF
+#define GPIO_FUNC26_OUT_SEL_S  0
+
+#define GPIO_FUNC27_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C0)
+/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC27_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC27_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC27_OEN_INV_SEL_S  11
+/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC27_OEN_SEL  (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC27_OEN_SEL_V  0x1
+#define GPIO_FUNC27_OEN_SEL_S  10
+/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC27_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC27_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC27_OUT_INV_SEL_S  9
+/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC27_OUT_SEL  0x000001FF
+#define GPIO_FUNC27_OUT_SEL_M  ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S))
+#define GPIO_FUNC27_OUT_SEL_V  0x1FF
+#define GPIO_FUNC27_OUT_SEL_S  0
+
+#define GPIO_FUNC28_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C4)
+/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC28_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC28_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC28_OEN_INV_SEL_S  11
+/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC28_OEN_SEL  (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC28_OEN_SEL_V  0x1
+#define GPIO_FUNC28_OEN_SEL_S  10
+/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC28_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC28_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC28_OUT_INV_SEL_S  9
+/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC28_OUT_SEL  0x000001FF
+#define GPIO_FUNC28_OUT_SEL_M  ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S))
+#define GPIO_FUNC28_OUT_SEL_V  0x1FF
+#define GPIO_FUNC28_OUT_SEL_S  0
+
+#define GPIO_FUNC29_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5C8)
+/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC29_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC29_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC29_OEN_INV_SEL_S  11
+/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC29_OEN_SEL  (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC29_OEN_SEL_V  0x1
+#define GPIO_FUNC29_OEN_SEL_S  10
+/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC29_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC29_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC29_OUT_INV_SEL_S  9
+/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC29_OUT_SEL  0x000001FF
+#define GPIO_FUNC29_OUT_SEL_M  ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S))
+#define GPIO_FUNC29_OUT_SEL_V  0x1FF
+#define GPIO_FUNC29_OUT_SEL_S  0
+
+#define GPIO_FUNC30_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5CC)
+/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC30_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC30_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC30_OEN_INV_SEL_S  11
+/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC30_OEN_SEL  (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC30_OEN_SEL_V  0x1
+#define GPIO_FUNC30_OEN_SEL_S  10
+/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC30_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC30_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC30_OUT_INV_SEL_S  9
+/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC30_OUT_SEL  0x000001FF
+#define GPIO_FUNC30_OUT_SEL_M  ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S))
+#define GPIO_FUNC30_OUT_SEL_V  0x1FF
+#define GPIO_FUNC30_OUT_SEL_S  0
+
+#define GPIO_FUNC31_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D0)
+/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC31_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC31_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC31_OEN_INV_SEL_S  11
+/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC31_OEN_SEL  (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC31_OEN_SEL_V  0x1
+#define GPIO_FUNC31_OEN_SEL_S  10
+/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC31_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC31_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC31_OUT_INV_SEL_S  9
+/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC31_OUT_SEL  0x000001FF
+#define GPIO_FUNC31_OUT_SEL_M  ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S))
+#define GPIO_FUNC31_OUT_SEL_V  0x1FF
+#define GPIO_FUNC31_OUT_SEL_S  0
+
+#define GPIO_FUNC32_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D4)
+/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC32_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC32_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC32_OEN_INV_SEL_S  11
+/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC32_OEN_SEL  (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC32_OEN_SEL_V  0x1
+#define GPIO_FUNC32_OEN_SEL_S  10
+/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC32_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC32_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC32_OUT_INV_SEL_S  9
+/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC32_OUT_SEL  0x000001FF
+#define GPIO_FUNC32_OUT_SEL_M  ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S))
+#define GPIO_FUNC32_OUT_SEL_V  0x1FF
+#define GPIO_FUNC32_OUT_SEL_S  0
+
+#define GPIO_FUNC33_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5D8)
+/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC33_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC33_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC33_OEN_INV_SEL_S  11
+/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC33_OEN_SEL  (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC33_OEN_SEL_V  0x1
+#define GPIO_FUNC33_OEN_SEL_S  10
+/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC33_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC33_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC33_OUT_INV_SEL_S  9
+/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC33_OUT_SEL  0x000001FF
+#define GPIO_FUNC33_OUT_SEL_M  ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S))
+#define GPIO_FUNC33_OUT_SEL_V  0x1FF
+#define GPIO_FUNC33_OUT_SEL_S  0
+
+#define GPIO_FUNC34_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5DC)
+/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC34_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC34_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC34_OEN_INV_SEL_S  11
+/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC34_OEN_SEL  (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC34_OEN_SEL_V  0x1
+#define GPIO_FUNC34_OEN_SEL_S  10
+/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC34_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC34_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC34_OUT_INV_SEL_S  9
+/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC34_OUT_SEL  0x000001FF
+#define GPIO_FUNC34_OUT_SEL_M  ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S))
+#define GPIO_FUNC34_OUT_SEL_V  0x1FF
+#define GPIO_FUNC34_OUT_SEL_S  0
+
+#define GPIO_FUNC35_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E0)
+/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC35_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC35_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC35_OEN_INV_SEL_S  11
+/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC35_OEN_SEL  (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC35_OEN_SEL_V  0x1
+#define GPIO_FUNC35_OEN_SEL_S  10
+/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC35_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC35_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC35_OUT_INV_SEL_S  9
+/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC35_OUT_SEL  0x000001FF
+#define GPIO_FUNC35_OUT_SEL_M  ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S))
+#define GPIO_FUNC35_OUT_SEL_V  0x1FF
+#define GPIO_FUNC35_OUT_SEL_S  0
+
+#define GPIO_FUNC36_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E4)
+/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC36_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC36_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC36_OEN_INV_SEL_S  11
+/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC36_OEN_SEL  (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC36_OEN_SEL_V  0x1
+#define GPIO_FUNC36_OEN_SEL_S  10
+/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC36_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC36_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC36_OUT_INV_SEL_S  9
+/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC36_OUT_SEL  0x000001FF
+#define GPIO_FUNC36_OUT_SEL_M  ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S))
+#define GPIO_FUNC36_OUT_SEL_V  0x1FF
+#define GPIO_FUNC36_OUT_SEL_S  0
+
+#define GPIO_FUNC37_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5E8)
+/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC37_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC37_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC37_OEN_INV_SEL_S  11
+/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC37_OEN_SEL  (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC37_OEN_SEL_V  0x1
+#define GPIO_FUNC37_OEN_SEL_S  10
+/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC37_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC37_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC37_OUT_INV_SEL_S  9
+/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC37_OUT_SEL  0x000001FF
+#define GPIO_FUNC37_OUT_SEL_M  ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S))
+#define GPIO_FUNC37_OUT_SEL_V  0x1FF
+#define GPIO_FUNC37_OUT_SEL_S  0
+
+#define GPIO_FUNC38_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5EC)
+/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC38_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC38_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC38_OEN_INV_SEL_S  11
+/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC38_OEN_SEL  (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC38_OEN_SEL_V  0x1
+#define GPIO_FUNC38_OEN_SEL_S  10
+/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC38_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC38_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC38_OUT_INV_SEL_S  9
+/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC38_OUT_SEL  0x000001FF
+#define GPIO_FUNC38_OUT_SEL_M  ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S))
+#define GPIO_FUNC38_OUT_SEL_V  0x1FF
+#define GPIO_FUNC38_OUT_SEL_S  0
+
+#define GPIO_FUNC39_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F0)
+/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC39_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC39_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC39_OEN_INV_SEL_S  11
+/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC39_OEN_SEL  (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC39_OEN_SEL_V  0x1
+#define GPIO_FUNC39_OEN_SEL_S  10
+/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC39_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC39_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC39_OUT_INV_SEL_S  9
+/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC39_OUT_SEL  0x000001FF
+#define GPIO_FUNC39_OUT_SEL_M  ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S))
+#define GPIO_FUNC39_OUT_SEL_V  0x1FF
+#define GPIO_FUNC39_OUT_SEL_S  0
+
+#define GPIO_FUNC40_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F4)
+/* GPIO_FUNC40_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC40_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC40_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC40_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC40_OEN_INV_SEL_S  11
+/* GPIO_FUNC40_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC40_OEN_SEL  (BIT(10))
+#define GPIO_FUNC40_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC40_OEN_SEL_V  0x1
+#define GPIO_FUNC40_OEN_SEL_S  10
+/* GPIO_FUNC40_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC40_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC40_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC40_OUT_INV_SEL_S  9
+/* GPIO_FUNC40_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC40_OUT_SEL  0x000001FF
+#define GPIO_FUNC40_OUT_SEL_M  ((GPIO_FUNC40_OUT_SEL_V)<<(GPIO_FUNC40_OUT_SEL_S))
+#define GPIO_FUNC40_OUT_SEL_V  0x1FF
+#define GPIO_FUNC40_OUT_SEL_S  0
+
+#define GPIO_FUNC41_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5F8)
+/* GPIO_FUNC41_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC41_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC41_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC41_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC41_OEN_INV_SEL_S  11
+/* GPIO_FUNC41_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC41_OEN_SEL  (BIT(10))
+#define GPIO_FUNC41_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC41_OEN_SEL_V  0x1
+#define GPIO_FUNC41_OEN_SEL_S  10
+/* GPIO_FUNC41_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC41_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC41_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC41_OUT_INV_SEL_S  9
+/* GPIO_FUNC41_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC41_OUT_SEL  0x000001FF
+#define GPIO_FUNC41_OUT_SEL_M  ((GPIO_FUNC41_OUT_SEL_V)<<(GPIO_FUNC41_OUT_SEL_S))
+#define GPIO_FUNC41_OUT_SEL_V  0x1FF
+#define GPIO_FUNC41_OUT_SEL_S  0
+
+#define GPIO_FUNC42_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x5FC)
+/* GPIO_FUNC42_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC42_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC42_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC42_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC42_OEN_INV_SEL_S  11
+/* GPIO_FUNC42_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC42_OEN_SEL  (BIT(10))
+#define GPIO_FUNC42_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC42_OEN_SEL_V  0x1
+#define GPIO_FUNC42_OEN_SEL_S  10
+/* GPIO_FUNC42_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC42_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC42_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC42_OUT_INV_SEL_S  9
+/* GPIO_FUNC42_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC42_OUT_SEL  0x000001FF
+#define GPIO_FUNC42_OUT_SEL_M  ((GPIO_FUNC42_OUT_SEL_V)<<(GPIO_FUNC42_OUT_SEL_S))
+#define GPIO_FUNC42_OUT_SEL_V  0x1FF
+#define GPIO_FUNC42_OUT_SEL_S  0
+
+#define GPIO_FUNC43_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x600)
+/* GPIO_FUNC43_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC43_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC43_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC43_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC43_OEN_INV_SEL_S  11
+/* GPIO_FUNC43_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC43_OEN_SEL  (BIT(10))
+#define GPIO_FUNC43_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC43_OEN_SEL_V  0x1
+#define GPIO_FUNC43_OEN_SEL_S  10
+/* GPIO_FUNC43_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC43_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC43_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC43_OUT_INV_SEL_S  9
+/* GPIO_FUNC43_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC43_OUT_SEL  0x000001FF
+#define GPIO_FUNC43_OUT_SEL_M  ((GPIO_FUNC43_OUT_SEL_V)<<(GPIO_FUNC43_OUT_SEL_S))
+#define GPIO_FUNC43_OUT_SEL_V  0x1FF
+#define GPIO_FUNC43_OUT_SEL_S  0
+
+#define GPIO_FUNC44_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x604)
+/* GPIO_FUNC44_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC44_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC44_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC44_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC44_OEN_INV_SEL_S  11
+/* GPIO_FUNC44_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC44_OEN_SEL  (BIT(10))
+#define GPIO_FUNC44_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC44_OEN_SEL_V  0x1
+#define GPIO_FUNC44_OEN_SEL_S  10
+/* GPIO_FUNC44_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC44_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC44_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC44_OUT_INV_SEL_S  9
+/* GPIO_FUNC44_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC44_OUT_SEL  0x000001FF
+#define GPIO_FUNC44_OUT_SEL_M  ((GPIO_FUNC44_OUT_SEL_V)<<(GPIO_FUNC44_OUT_SEL_S))
+#define GPIO_FUNC44_OUT_SEL_V  0x1FF
+#define GPIO_FUNC44_OUT_SEL_S  0
+
+#define GPIO_FUNC45_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x608)
+/* GPIO_FUNC45_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC45_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC45_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC45_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC45_OEN_INV_SEL_S  11
+/* GPIO_FUNC45_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC45_OEN_SEL  (BIT(10))
+#define GPIO_FUNC45_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC45_OEN_SEL_V  0x1
+#define GPIO_FUNC45_OEN_SEL_S  10
+/* GPIO_FUNC45_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC45_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC45_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC45_OUT_INV_SEL_S  9
+/* GPIO_FUNC45_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC45_OUT_SEL  0x000001FF
+#define GPIO_FUNC45_OUT_SEL_M  ((GPIO_FUNC45_OUT_SEL_V)<<(GPIO_FUNC45_OUT_SEL_S))
+#define GPIO_FUNC45_OUT_SEL_V  0x1FF
+#define GPIO_FUNC45_OUT_SEL_S  0
+
+#define GPIO_FUNC46_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x60C)
+/* GPIO_FUNC46_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC46_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC46_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC46_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC46_OEN_INV_SEL_S  11
+/* GPIO_FUNC46_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC46_OEN_SEL  (BIT(10))
+#define GPIO_FUNC46_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC46_OEN_SEL_V  0x1
+#define GPIO_FUNC46_OEN_SEL_S  10
+/* GPIO_FUNC46_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC46_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC46_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC46_OUT_INV_SEL_S  9
+/* GPIO_FUNC46_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC46_OUT_SEL  0x000001FF
+#define GPIO_FUNC46_OUT_SEL_M  ((GPIO_FUNC46_OUT_SEL_V)<<(GPIO_FUNC46_OUT_SEL_S))
+#define GPIO_FUNC46_OUT_SEL_V  0x1FF
+#define GPIO_FUNC46_OUT_SEL_S  0
+
+#define GPIO_FUNC47_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x610)
+/* GPIO_FUNC47_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC47_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC47_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC47_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC47_OEN_INV_SEL_S  11
+/* GPIO_FUNC47_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC47_OEN_SEL  (BIT(10))
+#define GPIO_FUNC47_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC47_OEN_SEL_V  0x1
+#define GPIO_FUNC47_OEN_SEL_S  10
+/* GPIO_FUNC47_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC47_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC47_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC47_OUT_INV_SEL_S  9
+/* GPIO_FUNC47_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC47_OUT_SEL  0x000001FF
+#define GPIO_FUNC47_OUT_SEL_M  ((GPIO_FUNC47_OUT_SEL_V)<<(GPIO_FUNC47_OUT_SEL_S))
+#define GPIO_FUNC47_OUT_SEL_V  0x1FF
+#define GPIO_FUNC47_OUT_SEL_S  0
+
+#define GPIO_FUNC48_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x614)
+/* GPIO_FUNC48_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC48_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC48_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC48_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC48_OEN_INV_SEL_S  11
+/* GPIO_FUNC48_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC48_OEN_SEL  (BIT(10))
+#define GPIO_FUNC48_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC48_OEN_SEL_V  0x1
+#define GPIO_FUNC48_OEN_SEL_S  10
+/* GPIO_FUNC48_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC48_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC48_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC48_OUT_INV_SEL_S  9
+/* GPIO_FUNC48_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC48_OUT_SEL  0x000001FF
+#define GPIO_FUNC48_OUT_SEL_M  ((GPIO_FUNC48_OUT_SEL_V)<<(GPIO_FUNC48_OUT_SEL_S))
+#define GPIO_FUNC48_OUT_SEL_V  0x1FF
+#define GPIO_FUNC48_OUT_SEL_S  0
+
+#define GPIO_FUNC49_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x618)
+/* GPIO_FUNC49_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC49_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC49_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC49_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC49_OEN_INV_SEL_S  11
+/* GPIO_FUNC49_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC49_OEN_SEL  (BIT(10))
+#define GPIO_FUNC49_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC49_OEN_SEL_V  0x1
+#define GPIO_FUNC49_OEN_SEL_S  10
+/* GPIO_FUNC49_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC49_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC49_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC49_OUT_INV_SEL_S  9
+/* GPIO_FUNC49_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC49_OUT_SEL  0x000001FF
+#define GPIO_FUNC49_OUT_SEL_M  ((GPIO_FUNC49_OUT_SEL_V)<<(GPIO_FUNC49_OUT_SEL_S))
+#define GPIO_FUNC49_OUT_SEL_V  0x1FF
+#define GPIO_FUNC49_OUT_SEL_S  0
+
+#define GPIO_FUNC50_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x61C)
+/* GPIO_FUNC50_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC50_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC50_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC50_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC50_OEN_INV_SEL_S  11
+/* GPIO_FUNC50_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC50_OEN_SEL  (BIT(10))
+#define GPIO_FUNC50_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC50_OEN_SEL_V  0x1
+#define GPIO_FUNC50_OEN_SEL_S  10
+/* GPIO_FUNC50_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC50_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC50_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC50_OUT_INV_SEL_S  9
+/* GPIO_FUNC50_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC50_OUT_SEL  0x000001FF
+#define GPIO_FUNC50_OUT_SEL_M  ((GPIO_FUNC50_OUT_SEL_V)<<(GPIO_FUNC50_OUT_SEL_S))
+#define GPIO_FUNC50_OUT_SEL_V  0x1FF
+#define GPIO_FUNC50_OUT_SEL_S  0
+
+#define GPIO_FUNC51_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x620)
+/* GPIO_FUNC51_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC51_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC51_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC51_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC51_OEN_INV_SEL_S  11
+/* GPIO_FUNC51_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC51_OEN_SEL  (BIT(10))
+#define GPIO_FUNC51_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC51_OEN_SEL_V  0x1
+#define GPIO_FUNC51_OEN_SEL_S  10
+/* GPIO_FUNC51_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC51_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC51_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC51_OUT_INV_SEL_S  9
+/* GPIO_FUNC51_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC51_OUT_SEL  0x000001FF
+#define GPIO_FUNC51_OUT_SEL_M  ((GPIO_FUNC51_OUT_SEL_V)<<(GPIO_FUNC51_OUT_SEL_S))
+#define GPIO_FUNC51_OUT_SEL_V  0x1FF
+#define GPIO_FUNC51_OUT_SEL_S  0
+
+#define GPIO_FUNC52_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x624)
+/* GPIO_FUNC52_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC52_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC52_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC52_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC52_OEN_INV_SEL_S  11
+/* GPIO_FUNC52_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC52_OEN_SEL  (BIT(10))
+#define GPIO_FUNC52_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC52_OEN_SEL_V  0x1
+#define GPIO_FUNC52_OEN_SEL_S  10
+/* GPIO_FUNC52_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC52_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC52_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC52_OUT_INV_SEL_S  9
+/* GPIO_FUNC52_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC52_OUT_SEL  0x000001FF
+#define GPIO_FUNC52_OUT_SEL_M  ((GPIO_FUNC52_OUT_SEL_V)<<(GPIO_FUNC52_OUT_SEL_S))
+#define GPIO_FUNC52_OUT_SEL_V  0x1FF
+#define GPIO_FUNC52_OUT_SEL_S  0
+
+#define GPIO_FUNC53_OUT_SEL_CFG_REG          (DR_REG_GPIO_BASE + 0x628)
+/* GPIO_FUNC53_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC53_OEN_INV_SEL  (BIT(11))
+#define GPIO_FUNC53_OEN_INV_SEL_M  (BIT(11))
+#define GPIO_FUNC53_OEN_INV_SEL_V  0x1
+#define GPIO_FUNC53_OEN_INV_SEL_S  11
+/* GPIO_FUNC53_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC53_OEN_SEL  (BIT(10))
+#define GPIO_FUNC53_OEN_SEL_M  (BIT(10))
+#define GPIO_FUNC53_OEN_SEL_V  0x1
+#define GPIO_FUNC53_OEN_SEL_S  10
+/* GPIO_FUNC53_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_FUNC53_OUT_INV_SEL  (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_M  (BIT(9))
+#define GPIO_FUNC53_OUT_INV_SEL_V  0x1
+#define GPIO_FUNC53_OUT_INV_SEL_S  9
+/* GPIO_FUNC53_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */
+/*description: */
+#define GPIO_FUNC53_OUT_SEL  0x000001FF
+#define GPIO_FUNC53_OUT_SEL_M  ((GPIO_FUNC53_OUT_SEL_V)<<(GPIO_FUNC53_OUT_SEL_S))
+#define GPIO_FUNC53_OUT_SEL_V  0x1FF
+#define GPIO_FUNC53_OUT_SEL_S  0
+
+#define GPIO_CLOCK_GATE_REG          (DR_REG_GPIO_BASE + 0x62C)
+/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define GPIO_CLK_EN  (BIT(0))
+#define GPIO_CLK_EN_M  (BIT(0))
+#define GPIO_CLK_EN_V  0x1
+#define GPIO_CLK_EN_S  0
+
+#define GPIO_DATE_REG          (DR_REG_GPIO_BASE + 0x6FC)
+/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809040 ; */
+/*description: */
+#define GPIO_DATE  0x0FFFFFFF
+#define GPIO_DATE_M  ((GPIO_DATE_V)<<(GPIO_DATE_S))
+#define GPIO_DATE_V  0xFFFFFFF
+#define GPIO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_GPIO_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/gpio_sd_reg.h b/components/soc/esp32s2beta/include/soc/gpio_sd_reg.h
new file mode 100644
index 000000000..f2bd9115f
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/gpio_sd_reg.h
@@ -0,0 +1,172 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_SD_REG_H_
+#define _SOC_GPIO_SD_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define GPIO_SIGMADELTA0_REG          (DR_REG_GPIO_SD_BASE + 0x0000)
+/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD0_PRESCALE  0x000000FF
+#define GPIO_SD0_PRESCALE_M  ((GPIO_SD0_PRESCALE_V)<<(GPIO_SD0_PRESCALE_S))
+#define GPIO_SD0_PRESCALE_V  0xFF
+#define GPIO_SD0_PRESCALE_S  8
+/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD0_IN  0x000000FF
+#define GPIO_SD0_IN_M  ((GPIO_SD0_IN_V)<<(GPIO_SD0_IN_S))
+#define GPIO_SD0_IN_V  0xFF
+#define GPIO_SD0_IN_S  0
+
+#define GPIO_SIGMADELTA1_REG          (DR_REG_GPIO_SD_BASE + 0x0004)
+/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD1_PRESCALE  0x000000FF
+#define GPIO_SD1_PRESCALE_M  ((GPIO_SD1_PRESCALE_V)<<(GPIO_SD1_PRESCALE_S))
+#define GPIO_SD1_PRESCALE_V  0xFF
+#define GPIO_SD1_PRESCALE_S  8
+/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD1_IN  0x000000FF
+#define GPIO_SD1_IN_M  ((GPIO_SD1_IN_V)<<(GPIO_SD1_IN_S))
+#define GPIO_SD1_IN_V  0xFF
+#define GPIO_SD1_IN_S  0
+
+#define GPIO_SIGMADELTA2_REG          (DR_REG_GPIO_SD_BASE + 0x0008)
+/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD2_PRESCALE  0x000000FF
+#define GPIO_SD2_PRESCALE_M  ((GPIO_SD2_PRESCALE_V)<<(GPIO_SD2_PRESCALE_S))
+#define GPIO_SD2_PRESCALE_V  0xFF
+#define GPIO_SD2_PRESCALE_S  8
+/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD2_IN  0x000000FF
+#define GPIO_SD2_IN_M  ((GPIO_SD2_IN_V)<<(GPIO_SD2_IN_S))
+#define GPIO_SD2_IN_V  0xFF
+#define GPIO_SD2_IN_S  0
+
+#define GPIO_SIGMADELTA3_REG          (DR_REG_GPIO_SD_BASE + 0x000c)
+/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD3_PRESCALE  0x000000FF
+#define GPIO_SD3_PRESCALE_M  ((GPIO_SD3_PRESCALE_V)<<(GPIO_SD3_PRESCALE_S))
+#define GPIO_SD3_PRESCALE_V  0xFF
+#define GPIO_SD3_PRESCALE_S  8
+/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD3_IN  0x000000FF
+#define GPIO_SD3_IN_M  ((GPIO_SD3_IN_V)<<(GPIO_SD3_IN_S))
+#define GPIO_SD3_IN_V  0xFF
+#define GPIO_SD3_IN_S  0
+
+#define GPIO_SIGMADELTA4_REG          (DR_REG_GPIO_SD_BASE + 0x0010)
+/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD4_PRESCALE  0x000000FF
+#define GPIO_SD4_PRESCALE_M  ((GPIO_SD4_PRESCALE_V)<<(GPIO_SD4_PRESCALE_S))
+#define GPIO_SD4_PRESCALE_V  0xFF
+#define GPIO_SD4_PRESCALE_S  8
+/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD4_IN  0x000000FF
+#define GPIO_SD4_IN_M  ((GPIO_SD4_IN_V)<<(GPIO_SD4_IN_S))
+#define GPIO_SD4_IN_V  0xFF
+#define GPIO_SD4_IN_S  0
+
+#define GPIO_SIGMADELTA5_REG          (DR_REG_GPIO_SD_BASE + 0x0014)
+/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD5_PRESCALE  0x000000FF
+#define GPIO_SD5_PRESCALE_M  ((GPIO_SD5_PRESCALE_V)<<(GPIO_SD5_PRESCALE_S))
+#define GPIO_SD5_PRESCALE_V  0xFF
+#define GPIO_SD5_PRESCALE_S  8
+/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD5_IN  0x000000FF
+#define GPIO_SD5_IN_M  ((GPIO_SD5_IN_V)<<(GPIO_SD5_IN_S))
+#define GPIO_SD5_IN_V  0xFF
+#define GPIO_SD5_IN_S  0
+
+#define GPIO_SIGMADELTA6_REG          (DR_REG_GPIO_SD_BASE + 0x0018)
+/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD6_PRESCALE  0x000000FF
+#define GPIO_SD6_PRESCALE_M  ((GPIO_SD6_PRESCALE_V)<<(GPIO_SD6_PRESCALE_S))
+#define GPIO_SD6_PRESCALE_V  0xFF
+#define GPIO_SD6_PRESCALE_S  8
+/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD6_IN  0x000000FF
+#define GPIO_SD6_IN_M  ((GPIO_SD6_IN_V)<<(GPIO_SD6_IN_S))
+#define GPIO_SD6_IN_V  0xFF
+#define GPIO_SD6_IN_S  0
+
+#define GPIO_SIGMADELTA7_REG          (DR_REG_GPIO_SD_BASE + 0x001c)
+/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
+/*description: */
+#define GPIO_SD7_PRESCALE  0x000000FF
+#define GPIO_SD7_PRESCALE_M  ((GPIO_SD7_PRESCALE_V)<<(GPIO_SD7_PRESCALE_S))
+#define GPIO_SD7_PRESCALE_V  0xFF
+#define GPIO_SD7_PRESCALE_S  8
+/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define GPIO_SD7_IN  0x000000FF
+#define GPIO_SD7_IN_M  ((GPIO_SD7_IN_V)<<(GPIO_SD7_IN_S))
+#define GPIO_SD7_IN_V  0xFF
+#define GPIO_SD7_IN_S  0
+
+#define GPIO_SIGMADELTA_CG_REG          (DR_REG_GPIO_SD_BASE + 0x0020)
+/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SD_CLK_EN  (BIT(31))
+#define GPIO_SD_CLK_EN_M  (BIT(31))
+#define GPIO_SD_CLK_EN_V  0x1
+#define GPIO_SD_CLK_EN_S  31
+
+#define GPIO_SIGMADELTA_MISC_REG          (DR_REG_GPIO_SD_BASE + 0x0024)
+/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define GPIO_SPI_SWAP  (BIT(31))
+#define GPIO_SPI_SWAP_M  (BIT(31))
+#define GPIO_SPI_SWAP_V  0x1
+#define GPIO_SPI_SWAP_S  31
+/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: */
+#define GPIO_FUNCTION_CLK_EN  (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_M  (BIT(30))
+#define GPIO_FUNCTION_CLK_EN_V  0x1
+#define GPIO_FUNCTION_CLK_EN_S  30
+
+#define GPIO_SIGMADELTA_VERSION_REG          (DR_REG_GPIO_SD_BASE + 0x0028)
+/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
+/*description: */
+#define GPIO_SD_DATE  0x0FFFFFFF
+#define GPIO_SD_DATE_M  ((GPIO_SD_DATE_V)<<(GPIO_SD_DATE_S))
+#define GPIO_SD_DATE_V  0xFFFFFFF
+#define GPIO_SD_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_GPIO_SD_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/gpio_sd_struct.h b/components/soc/esp32s2beta/include/soc/gpio_sd_struct.h
new file mode 100644
index 000000000..6c28df52a
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/gpio_sd_struct.h
@@ -0,0 +1,57 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_SD_STRUCT_H_
+#define _SOC_GPIO_SD_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t duty:         8;
+            uint32_t prescale:     8;
+            uint32_t reserved16:  16;
+        };
+        uint32_t val;
+    } channel[8];
+    union {
+        struct {
+            uint32_t reserved0: 31;
+            uint32_t clk_en:     1;
+        };
+        uint32_t val;
+    } cg;
+    union {
+        struct {
+            uint32_t reserved0:      30;
+            uint32_t function_clk_en: 1;
+            uint32_t spi_swap:        1;
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } version;
+} gpio_sd_dev_t;
+extern gpio_sd_dev_t SIGMADELTA;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_GPIO_SD_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/gpio_sig_map.h b/components/soc/esp32s2beta/include/soc/gpio_sig_map.h
new file mode 100644
index 000000000..6215328d1
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/gpio_sig_map.h
@@ -0,0 +1,288 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+#define SPICLK_OUT_IDX			SPICLK_OUT_MUX_IDX
+#define CLK_I2S_IDX			    CLK_I2S_MUX_IDX
+
+#define SPIQ_IN_IDX			0
+#define SPIQ_OUT_IDX			0
+#define SPID_IN_IDX			1
+#define SPID_OUT_IDX			1
+#define SPIHD_IN_IDX			2
+#define SPIHD_OUT_IDX			2
+#define SPIWP_IN_IDX			3
+#define SPIWP_OUT_IDX			3
+#define SPICLK_OUT_MUX_IDX			4
+#define SPICS0_OUT_IDX			5
+#define SPICS1_OUT_IDX			6
+#define FSPICD_OUT_IDX			9
+#define SPI3_CD_OUT_IDX			10
+#define SPI4_CD_OUT_IDX			11
+#define U0RXD_IN_IDX			14
+#define U0TXD_OUT_IDX			14
+#define U0CTS_IN_IDX			15
+#define U0RTS_OUT_IDX			15
+#define U0DSR_IN_IDX			16
+#define U0DTR_OUT_IDX			16
+#define U1RXD_IN_IDX			17
+#define U1TXD_OUT_IDX			17
+#define U1CTS_IN_IDX			18
+#define U1RTS_OUT_IDX			18
+#define U1DSR_IN_IDX			21
+#define U1DTR_OUT_IDX			21
+#define I2S0O_BCK_IN_IDX			23
+#define I2S0O_BCK_OUT_IDX			23
+#define I2S0O_WS_IN_IDX			25
+#define I2S0O_WS_OUT_IDX			25
+#define I2S0I_BCK_IN_IDX			27
+#define I2S0I_BCK_OUT_IDX			27
+#define I2S0I_WS_IN_IDX			28
+#define I2S0I_WS_OUT_IDX			28
+#define I2CEXT0_SCL_IN_IDX			29
+#define I2CEXT0_SCL_OUT_IDX			29
+#define I2CEXT0_SDA_IN_IDX			30
+#define I2CEXT0_SDA_OUT_IDX			30
+#define SDIO_TOHOST_INT_OUT_IDX			31
+#define GPIO_BT_ACTIVE_IDX			37
+#define GPIO_BT_PRIORITY_IDX			38
+#define PCNT_SIG_CH0_IN0_IDX			39
+#define GPIO_WLAN_PRIO_IDX			39
+#define PCNT_SIG_CH1_IN0_IDX			40
+#define GPIO_WLAN_ACTIVE_IDX			40
+#define PCNT_CTRL_CH0_IN0_IDX			41
+#define BB_DIAG0_IDX			41
+#define PCNT_CTRL_CH1_IN0_IDX			42
+#define BB_DIAG1_IDX			42
+#define PCNT_SIG_CH0_IN1_IDX			43
+#define BB_DIAG2_IDX			43
+#define PCNT_SIG_CH1_IN1_IDX			44
+#define BB_DIAG3_IDX			44
+#define PCNT_CTRL_CH0_IN1_IDX			45
+#define BB_DIAG4_IDX			45
+#define PCNT_CTRL_CH1_IN1_IDX			46
+#define BB_DIAG5_IDX			46
+#define PCNT_SIG_CH0_IN2_IDX			47
+#define BB_DIAG6_IDX			47
+#define PCNT_SIG_CH1_IN2_IDX			48
+#define BB_DIAG7_IDX			48
+#define PCNT_CTRL_CH0_IN2_IDX			49
+#define BB_DIAG8_IDX			49
+#define PCNT_CTRL_CH1_IN2_IDX			50
+#define BB_DIAG9_IDX			50
+#define PCNT_SIG_CH0_IN3_IDX			51
+#define BB_DIAG10_IDX			51
+#define PCNT_SIG_CH1_IN3_IDX			52
+#define BB_DIAG11_IDX			52
+#define PCNT_CTRL_CH0_IN3_IDX			53
+#define BB_DIAG12_IDX			53
+#define PCNT_CTRL_CH1_IN3_IDX			54
+#define BB_DIAG13_IDX			54
+#define BB_DIAG14_IDX			55
+#define BB_DIAG15_IDX			56
+#define BB_DIAG16_IDX			57
+#define BB_DIAG17_IDX			58
+#define BB_DIAG18_IDX			59
+#define BB_DIAG19_IDX			60
+#define USB_EXTPHY_VP_IDX			61
+#define USB_EXTPHY_OEN_IDX			61
+#define USB_EXTPHY_VM_IDX			62
+#define USB_EXTPHY_SPEED_IDX			62
+#define USB_EXTPHY_RCV_IDX			63
+#define USB_EXTPHY_VPO_IDX			63
+#define USB_OTG_IDDIG_IN_IDX			64
+#define USB_EXTPHY_VMO_IDX			64
+#define USB_OTG_AVALID_IN_IDX			65
+#define USB_EXTPHY_SUSPND_IDX			65
+#define USB_SRP_BVALID_IN_IDX			66
+#define USB_OTG_IDPULLUP_IDX			66
+#define USB_OTG_VBUSVALID_IN_IDX			67
+#define USB_OTG_DPPULLDOWN_IDX			67
+#define USB_SRP_SESSEND_IN_IDX			68
+#define USB_OTG_DMPULLDOWN_IDX			68
+#define USB_OTG_DRVVBUS_IDX			69
+#define USB_SRP_CHRGVBUS_IDX			70
+#define USB_SRP_DISCHRGVBUS_IDX			71
+#define SPI3_CLK_IN_IDX			72
+#define SPI3_CLK_OUT_MUX_IDX			72
+#define SPI3_Q_IN_IDX			73
+#define SPI3_Q_OUT_IDX			73
+#define SPI3_D_IN_IDX			74
+#define SPI3_D_OUT_IDX			74
+#define SPI3_HD_IN_IDX			75
+#define SPI3_HD_OUT_IDX			75
+#define SPI3_CS0_IN_IDX			76
+#define SPI3_CS0_OUT_IDX			76
+#define SPI3_CS1_OUT_IDX			77
+#define SPI3_CS2_OUT_IDX			78
+#define LEDC_LS_SIG_OUT0_IDX			79
+#define LEDC_LS_SIG_OUT1_IDX			80
+#define LEDC_LS_SIG_OUT2_IDX			81
+#define LEDC_LS_SIG_OUT3_IDX			82
+#define RMT_SIG_IN0_IDX			83
+#define LEDC_LS_SIG_OUT4_IDX			83
+#define RMT_SIG_IN1_IDX			84
+#define LEDC_LS_SIG_OUT5_IDX			84
+#define RMT_SIG_IN2_IDX			85
+#define LEDC_LS_SIG_OUT6_IDX			85
+#define RMT_SIG_IN3_IDX			86
+#define LEDC_LS_SIG_OUT7_IDX			86
+#define RMT_SIG_OUT0_IDX			87
+#define RMT_SIG_OUT1_IDX			88
+#define RMT_SIG_OUT2_IDX			89
+#define RMT_SIG_OUT3_IDX			90
+#define EXT_ADC_START_IDX			93
+#define I2CEXT1_SCL_IN_IDX			95
+#define I2CEXT1_SCL_OUT_IDX			95
+#define I2CEXT1_SDA_IN_IDX			96
+#define I2CEXT1_SDA_OUT_IDX			96
+#define GPIO_SD0_OUT_IDX			100
+#define GPIO_SD1_OUT_IDX			101
+#define GPIO_SD2_OUT_IDX			102
+#define GPIO_SD3_OUT_IDX			103
+#define GPIO_SD4_OUT_IDX			104
+#define GPIO_SD5_OUT_IDX			105
+#define GPIO_SD6_OUT_IDX			106
+#define GPIO_SD7_OUT_IDX			107
+#define SPI4_CLK_IN_IDX			108
+#define SPI4_CLK_OUT_MUX_IDX			108
+#define SPI4_Q_IN_IDX			109
+#define SPI4_Q_OUT_IDX			109
+#define SPI4_D_IN_IDX			110
+#define SPI4_D_OUT_IDX			110
+#define SPI4_HD_IN_IDX			111
+#define SPI4_HD_OUT_IDX			111
+#define SPI4_CS0_IN_IDX			112
+#define SPI4_CS0_OUT_IDX			112
+#define SPI4_CS1_OUT_IDX			113
+#define SPI4_CS2_OUT_IDX			114
+#define FSPICLK_IN_IDX			115
+#define FSPICLK_OUT_MUX_IDX			115
+#define FSPIQ_IN_IDX			116
+#define FSPIQ_OUT_IDX			116
+#define FSPID_IN_IDX			117
+#define FSPID_OUT_IDX			117
+#define FSPIHD_IN_IDX			118
+#define FSPIHD_OUT_IDX			118
+#define FSPIWP_IN_IDX			119
+#define FSPIWP_OUT_IDX			119
+#define FSPICS0_IN_IDX			120
+#define FSPICS0_OUT_IDX			120
+#define FSPICS1_OUT_IDX			121
+#define FSPICS2_OUT_IDX			122
+#define CAN_RX_IDX			123
+#define CAN_TX_IDX			123
+#define CAN_BUS_OFF_ON_IDX			124
+#define CAN_CLKOUT_IDX			125
+#define SUBSPICLK_OUT_MUX_IDX			126
+#define SUBSPIQ_IN_IDX			127
+#define SUBSPIQ_OUT_IDX			127
+#define SUBSPID_IN_IDX			128
+#define SUBSPID_OUT_IDX			128
+#define SUBSPIHD_IN_IDX			129
+#define SUBSPIHD_OUT_IDX			129
+#define SUBSPIWP_IN_IDX			130
+#define SUBSPIWP_OUT_IDX			130
+#define SUBSPICS0_OUT_IDX			131
+#define SUBSPICS1_OUT_IDX			132
+#define FSPIDQS_OUT_IDX			133
+#define SPI3_DQS_OUT_IDX			134
+#define SPI4_DQS_OUT_IDX			135
+#define I2S0I_DATA_IN0_IDX			143
+#define I2S0O_DATA_OUT0_IDX			143
+#define I2S0I_DATA_IN1_IDX			144
+#define I2S0O_DATA_OUT1_IDX			144
+#define I2S0I_DATA_IN2_IDX			145
+#define I2S0O_DATA_OUT2_IDX			145
+#define I2S0I_DATA_IN3_IDX			146
+#define I2S0O_DATA_OUT3_IDX			146
+#define I2S0I_DATA_IN4_IDX			147
+#define I2S0O_DATA_OUT4_IDX			147
+#define I2S0I_DATA_IN5_IDX			148
+#define I2S0O_DATA_OUT5_IDX			148
+#define I2S0I_DATA_IN6_IDX			149
+#define I2S0O_DATA_OUT6_IDX			149
+#define I2S0I_DATA_IN7_IDX			150
+#define I2S0O_DATA_OUT7_IDX			150
+#define I2S0I_DATA_IN8_IDX			151
+#define I2S0O_DATA_OUT8_IDX			151
+#define I2S0I_DATA_IN9_IDX			152
+#define I2S0O_DATA_OUT9_IDX			152
+#define I2S0I_DATA_IN10_IDX			153
+#define I2S0O_DATA_OUT10_IDX			153
+#define I2S0I_DATA_IN11_IDX			154
+#define I2S0O_DATA_OUT11_IDX			154
+#define I2S0I_DATA_IN12_IDX			155
+#define I2S0O_DATA_OUT12_IDX			155
+#define I2S0I_DATA_IN13_IDX			156
+#define I2S0O_DATA_OUT13_IDX			156
+#define I2S0I_DATA_IN14_IDX			157
+#define I2S0O_DATA_OUT14_IDX			157
+#define I2S0I_DATA_IN15_IDX			158
+#define I2S0O_DATA_OUT15_IDX			158
+#define I2S0O_DATA_OUT16_IDX			159
+#define I2S0O_DATA_OUT17_IDX			160
+#define I2S0O_DATA_OUT18_IDX			161
+#define I2S0O_DATA_OUT19_IDX			162
+#define I2S0O_DATA_OUT20_IDX			163
+#define I2S0O_DATA_OUT21_IDX			164
+#define I2S0O_DATA_OUT22_IDX			165
+#define I2S0O_DATA_OUT23_IDX			166
+#define I2S0I_H_SYNC_IDX			193
+#define I2S0I_V_SYNC_IDX			194
+#define I2S0I_H_ENABLE_IDX			195
+#define PCMFSYNC_IN_IDX			203
+#define BT_AUDIO0_IRQ_IDX			203
+#define PCMCLK_IN_IDX			204
+#define BT_AUDIO1_IRQ_IDX			204
+#define PCMDIN_IDX			205
+#define BT_AUDIO2_IRQ_IDX			205
+#define RW_WAKEUP_REQ_IDX			206
+#define BLE_AUDIO0_IRQ_IDX			206
+#define BLE_AUDIO1_IRQ_IDX			207
+#define BLE_AUDIO2_IRQ_IDX			208
+#define PCMFSYNC_OUT_IDX			209
+#define PCMCLK_OUT_IDX			210
+#define PCMDOUT_IDX			211
+#define BLE_AUDIO_SYNC0_P_IDX			212
+#define BLE_AUDIO_SYNC1_P_IDX			213
+#define BLE_AUDIO_SYNC2_P_IDX			214
+#define ANT_SEL0_IDX			215
+#define ANT_SEL1_IDX			216
+#define ANT_SEL2_IDX			217
+#define ANT_SEL3_IDX			218
+#define ANT_SEL4_IDX			219
+#define ANT_SEL5_IDX			220
+#define ANT_SEL6_IDX			221
+#define ANT_SEL7_IDX			222
+#define SIG_IN_FUNC_223_IDX			223
+#define SIG_IN_FUNC223_IDX			223
+#define SIG_IN_FUNC_224_IDX			224
+#define SIG_IN_FUNC224_IDX			224
+#define SIG_IN_FUNC_225_IDX			225
+#define SIG_IN_FUNC225_IDX			225
+#define SIG_IN_FUNC_226_IDX			226
+#define SIG_IN_FUNC226_IDX			226
+#define SIG_IN_FUNC_227_IDX			227
+#define SIG_IN_FUNC227_IDX			227
+#define PRO_ALONEGPIO_IN0_IDX			235
+#define PRO_ALONEGPIO_OUT0_IDX			235
+#define PRO_ALONEGPIO_IN1_IDX			236
+#define PRO_ALONEGPIO_OUT1_IDX			236
+#define PRO_ALONEGPIO_IN2_IDX			237
+#define PRO_ALONEGPIO_OUT2_IDX			237
+#define PRO_ALONEGPIO_IN3_IDX			238
+#define PRO_ALONEGPIO_OUT3_IDX			238
+#define PRO_ALONEGPIO_IN4_IDX			239
+#define PRO_ALONEGPIO_OUT4_IDX			239
+#define PRO_ALONEGPIO_IN5_IDX			240
+#define PRO_ALONEGPIO_OUT5_IDX			240
+#define PRO_ALONEGPIO_IN6_IDX			241
+#define PRO_ALONEGPIO_OUT6_IDX			241
+#define PRO_ALONEGPIO_IN7_IDX			242
+#define PRO_ALONEGPIO_OUT7_IDX			242
+#define CLK_I2S_MUX_IDX			251
+#define SIG_GPIO_OUT_IDX            256
+#define GPIO_MAP_DATE_IDX			0x18102600
diff --git a/components/soc/esp32s2beta/include/soc/gpio_struct.h b/components/soc/esp32s2beta/include/soc/gpio_struct.h
new file mode 100644
index 000000000..d5544b7e3
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/gpio_struct.h
@@ -0,0 +1,196 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_GPIO_STRUCT_H_
+#define _SOC_GPIO_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t bt_select;                             /**/
+    uint32_t out;                                   /**/
+    uint32_t out_w1ts;                              /**/
+    uint32_t out_w1tc;                              /**/
+    union {
+        struct {
+            uint32_t data:      22;
+            uint32_t reserved22:10;
+        };
+        uint32_t val;
+    } out1;
+    union {
+        struct {
+            uint32_t data:      22;
+            uint32_t reserved22:10;
+        };
+        uint32_t val;
+    } out1_w1ts;
+    union {
+        struct {
+            uint32_t data:      22;
+            uint32_t reserved22:10;
+        };
+        uint32_t val;
+    } out1_w1tc;
+    union {
+        struct {
+            uint32_t sel:        8;
+            uint32_t reserved8: 24;
+        };
+        uint32_t val;
+    } sdio_select;
+    uint32_t enable;                                /**/
+    uint32_t enable_w1ts;                           /**/
+    uint32_t enable_w1tc;                           /**/
+    union {
+        struct {
+            uint32_t data:       22;
+            uint32_t reserved22: 10;
+        };
+        uint32_t val;
+    } enable1;
+    union {
+        struct {
+            uint32_t data:       22;
+            uint32_t reserved22: 10;
+        };
+        uint32_t val;
+    } enable1_w1ts;
+    union {
+        struct {
+            uint32_t data:       22;
+            uint32_t reserved22: 10;
+        };
+        uint32_t val;
+    } enable1_w1tc;
+    union {
+        struct {
+            uint32_t strapping: 16;
+            uint32_t reserved16:16;
+        };
+        uint32_t val;
+    } strap;
+    uint32_t in;                                    /**/
+    union {
+        struct {
+            uint32_t data:        22;
+            uint32_t reserved22:  10;
+        };
+        uint32_t val;
+    } in1;
+    uint32_t status;                                /**/
+    uint32_t status_w1ts;                           /**/
+    uint32_t status_w1tc;                           /**/
+    union {
+        struct {
+            uint32_t intr_st:         22;
+            uint32_t reserved22:      10;
+        };
+        uint32_t val;
+    } status1;
+    union {
+        struct {
+            uint32_t intr_st:         22;
+            uint32_t reserved22:      10;
+        };
+        uint32_t val;
+    } status1_w1ts;
+    union {
+        struct {
+            uint32_t intr_st:         22;
+            uint32_t reserved22:      10;
+        };
+        uint32_t val;
+    } status1_w1tc;
+    uint32_t pcpu_int;                              /**/
+    uint32_t pcpu_nmi_int;                          /**/
+    uint32_t cpusdio_int;                           /**/
+    union {
+        struct {
+            uint32_t intr:      22;
+            uint32_t reserved22:10;
+        };
+        uint32_t val;
+    } pcpu_int1;
+    union {
+        struct {
+            uint32_t intr:          22;
+            uint32_t reserved22:    10;
+        };
+        uint32_t val;
+    } pcpu_nmi_int1;
+    union {
+        struct {
+            uint32_t intr:      22;
+            uint32_t reserved22:10;
+        };
+        uint32_t val;
+    } cpusdio_int1;
+    union {
+        struct {
+            uint32_t sync2_bypass:       2;
+            uint32_t pad_driver:         1;
+            uint32_t sync1_bypass:       2;
+            uint32_t reserved5:          2;
+            uint32_t int_type:           3;
+            uint32_t wakeup_enable:      1;
+            uint32_t config:             2;
+            uint32_t int_ena:            5;
+            uint32_t reserved18:        14;
+        };
+        uint32_t val;
+    } pin[54];
+    union {
+        struct {
+            uint32_t rtc_max:     10;
+            uint32_t reserved10:  21;
+            uint32_t start:        1;
+        };
+        uint32_t val;
+    } cali_conf;
+    union {
+        struct {
+            uint32_t value_sync2:     20;
+            uint32_t reserved20:      10;
+            uint32_t rdy_real:         1;
+            uint32_t rdy_sync2:        1;
+        };
+        uint32_t val;
+    } cali_data;
+    union {
+        struct {
+            uint32_t func_sel:         6;
+            uint32_t sig_in_inv:       1;
+            uint32_t sig_in_sel:       1;
+            uint32_t reserved8:       24;
+        };
+        uint32_t val;
+    } func_in_sel_cfg[256];
+    union {
+        struct {
+            uint32_t func_sel:          9;
+            uint32_t inv_sel:           1;
+            uint32_t oen_sel:           1;
+            uint32_t oen_inv_sel:       1;
+            uint32_t reserved12:       20;
+        };
+        uint32_t val;
+    } func_out_sel_cfg[54];
+} gpio_dev_t;
+extern gpio_dev_t GPIO;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_GPIO_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/hinf_reg.h b/components/soc/esp32s2beta/include/soc/hinf_reg.h
new file mode 100644
index 000000000..aad357864
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/hinf_reg.h
@@ -0,0 +1,248 @@
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HINF_REG_H_
+#define _SOC_HINF_REG_H_
+
+
+#include "soc.h"
+#define HINF_CFG_DATA0_REG          (DR_REG_HINF_BASE + 0x0)
+/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
+/*description: */
+#define HINF_DEVICE_ID_FN1  0x0000FFFF
+#define HINF_DEVICE_ID_FN1_M  ((HINF_DEVICE_ID_FN1_V)<<(HINF_DEVICE_ID_FN1_S))
+#define HINF_DEVICE_ID_FN1_V  0xFFFF
+#define HINF_DEVICE_ID_FN1_S  16
+/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
+/*description: */
+#define HINF_USER_ID_FN1  0x0000FFFF
+#define HINF_USER_ID_FN1_M  ((HINF_USER_ID_FN1_V)<<(HINF_USER_ID_FN1_S))
+#define HINF_USER_ID_FN1_V  0xFFFF
+#define HINF_USER_ID_FN1_S  0
+
+#define HINF_CFG_DATA1_REG          (DR_REG_HINF_BASE + 0x4)
+/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
+/*description: */
+#define HINF_SDIO20_CONF1  0x00000007
+#define HINF_SDIO20_CONF1_M  ((HINF_SDIO20_CONF1_V)<<(HINF_SDIO20_CONF1_S))
+#define HINF_SDIO20_CONF1_V  0x7
+#define HINF_SDIO20_CONF1_S  29
+/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define HINF_FUNC2_EPS  (BIT(28))
+#define HINF_FUNC2_EPS_M  (BIT(28))
+#define HINF_FUNC2_EPS_V  0x1
+#define HINF_FUNC2_EPS_S  28
+/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
+/*description: */
+#define HINF_SDIO_VER  0x00000FFF
+#define HINF_SDIO_VER_M  ((HINF_SDIO_VER_V)<<(HINF_SDIO_VER_S))
+#define HINF_SDIO_VER_V  0xFFF
+#define HINF_SDIO_VER_S  16
+/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
+/*description: */
+#define HINF_SDIO20_CONF0  0x0000000F
+#define HINF_SDIO20_CONF0_M  ((HINF_SDIO20_CONF0_V)<<(HINF_SDIO20_CONF0_S))
+#define HINF_SDIO20_CONF0_V  0xF
+#define HINF_SDIO20_CONF0_S  12
+/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HINF_IOENABLE1  (BIT(11))
+#define HINF_IOENABLE1_M  (BIT(11))
+#define HINF_IOENABLE1_V  0x1
+#define HINF_IOENABLE1_S  11
+/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HINF_EMP  (BIT(10))
+#define HINF_EMP_M  (BIT(10))
+#define HINF_EMP_V  0x1
+#define HINF_EMP_S  10
+/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HINF_FUNC1_EPS  (BIT(9))
+#define HINF_FUNC1_EPS_M  (BIT(9))
+#define HINF_FUNC1_EPS_V  0x1
+#define HINF_FUNC1_EPS_S  9
+/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HINF_CD_DISABLE  (BIT(8))
+#define HINF_CD_DISABLE_M  (BIT(8))
+#define HINF_CD_DISABLE_V  0x1
+#define HINF_CD_DISABLE_S  8
+/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HINF_IOENABLE2  (BIT(7))
+#define HINF_IOENABLE2_M  (BIT(7))
+#define HINF_IOENABLE2_V  0x1
+#define HINF_IOENABLE2_S  7
+/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_INT_MASK  (BIT(6))
+#define HINF_SDIO_INT_MASK_M  (BIT(6))
+#define HINF_SDIO_INT_MASK_V  0x1
+#define HINF_SDIO_INT_MASK_S  6
+/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_IOREADY2  (BIT(5))
+#define HINF_SDIO_IOREADY2_M  (BIT(5))
+#define HINF_SDIO_IOREADY2_V  0x1
+#define HINF_SDIO_IOREADY2_S  5
+/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define HINF_SDIO_CD_ENABLE  (BIT(4))
+#define HINF_SDIO_CD_ENABLE_M  (BIT(4))
+#define HINF_SDIO_CD_ENABLE_V  0x1
+#define HINF_SDIO_CD_ENABLE_S  4
+/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HINF_HIGHSPEED_MODE  (BIT(3))
+#define HINF_HIGHSPEED_MODE_M  (BIT(3))
+#define HINF_HIGHSPEED_MODE_V  0x1
+#define HINF_HIGHSPEED_MODE_S  3
+/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HINF_HIGHSPEED_ENABLE  (BIT(2))
+#define HINF_HIGHSPEED_ENABLE_M  (BIT(2))
+#define HINF_HIGHSPEED_ENABLE_V  0x1
+#define HINF_HIGHSPEED_ENABLE_S  2
+/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_IOREADY1  (BIT(1))
+#define HINF_SDIO_IOREADY1_M  (BIT(1))
+#define HINF_SDIO_IOREADY1_V  0x1
+#define HINF_SDIO_IOREADY1_S  1
+/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define HINF_SDIO_ENABLE  (BIT(0))
+#define HINF_SDIO_ENABLE_M  (BIT(0))
+#define HINF_SDIO_ENABLE_V  0x1
+#define HINF_SDIO_ENABLE_S  0
+
+#define HINF_CFG_DATA7_REG          (DR_REG_HINF_BASE + 0x1C)
+/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define HINF_SDIO_IOREADY0  (BIT(17))
+#define HINF_SDIO_IOREADY0_M  (BIT(17))
+#define HINF_SDIO_IOREADY0_V  0x1
+#define HINF_SDIO_IOREADY0_S  17
+/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HINF_SDIO_RST  (BIT(16))
+#define HINF_SDIO_RST_M  (BIT(16))
+#define HINF_SDIO_RST_V  0x1
+#define HINF_SDIO_RST_S  16
+/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: */
+#define HINF_CHIP_STATE  0x000000FF
+#define HINF_CHIP_STATE_M  ((HINF_CHIP_STATE_V)<<(HINF_CHIP_STATE_S))
+#define HINF_CHIP_STATE_V  0xFF
+#define HINF_CHIP_STATE_S  8
+/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define HINF_PIN_STATE  0x000000FF
+#define HINF_PIN_STATE_M  ((HINF_PIN_STATE_V)<<(HINF_PIN_STATE_S))
+#define HINF_PIN_STATE_V  0xFF
+#define HINF_PIN_STATE_S  0
+
+#define HINF_CIS_CONF0_REG          (DR_REG_HINF_BASE + 0x20)
+/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W0  0xFFFFFFFF
+#define HINF_CIS_CONF_W0_M  ((HINF_CIS_CONF_W0_V)<<(HINF_CIS_CONF_W0_S))
+#define HINF_CIS_CONF_W0_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W0_S  0
+
+#define HINF_CIS_CONF1_REG          (DR_REG_HINF_BASE + 0x24)
+/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W1  0xFFFFFFFF
+#define HINF_CIS_CONF_W1_M  ((HINF_CIS_CONF_W1_V)<<(HINF_CIS_CONF_W1_S))
+#define HINF_CIS_CONF_W1_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W1_S  0
+
+#define HINF_CIS_CONF2_REG          (DR_REG_HINF_BASE + 0x28)
+/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W2  0xFFFFFFFF
+#define HINF_CIS_CONF_W2_M  ((HINF_CIS_CONF_W2_V)<<(HINF_CIS_CONF_W2_S))
+#define HINF_CIS_CONF_W2_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W2_S  0
+
+#define HINF_CIS_CONF3_REG          (DR_REG_HINF_BASE + 0x2C)
+/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W3  0xFFFFFFFF
+#define HINF_CIS_CONF_W3_M  ((HINF_CIS_CONF_W3_V)<<(HINF_CIS_CONF_W3_S))
+#define HINF_CIS_CONF_W3_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W3_S  0
+
+#define HINF_CIS_CONF4_REG          (DR_REG_HINF_BASE + 0x30)
+/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W4  0xFFFFFFFF
+#define HINF_CIS_CONF_W4_M  ((HINF_CIS_CONF_W4_V)<<(HINF_CIS_CONF_W4_S))
+#define HINF_CIS_CONF_W4_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W4_S  0
+
+#define HINF_CIS_CONF5_REG          (DR_REG_HINF_BASE + 0x34)
+/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W5  0xFFFFFFFF
+#define HINF_CIS_CONF_W5_M  ((HINF_CIS_CONF_W5_V)<<(HINF_CIS_CONF_W5_S))
+#define HINF_CIS_CONF_W5_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W5_S  0
+
+#define HINF_CIS_CONF6_REG          (DR_REG_HINF_BASE + 0x38)
+/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W6  0xFFFFFFFF
+#define HINF_CIS_CONF_W6_M  ((HINF_CIS_CONF_W6_V)<<(HINF_CIS_CONF_W6_S))
+#define HINF_CIS_CONF_W6_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W6_S  0
+
+#define HINF_CIS_CONF7_REG          (DR_REG_HINF_BASE + 0x3C)
+/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: */
+#define HINF_CIS_CONF_W7  0xFFFFFFFF
+#define HINF_CIS_CONF_W7_M  ((HINF_CIS_CONF_W7_V)<<(HINF_CIS_CONF_W7_S))
+#define HINF_CIS_CONF_W7_V  0xFFFFFFFF
+#define HINF_CIS_CONF_W7_S  0
+
+#define HINF_CFG_DATA16_REG          (DR_REG_HINF_BASE + 0x40)
+/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
+/*description: */
+#define HINF_DEVICE_ID_FN2  0x0000FFFF
+#define HINF_DEVICE_ID_FN2_M  ((HINF_DEVICE_ID_FN2_V)<<(HINF_DEVICE_ID_FN2_S))
+#define HINF_DEVICE_ID_FN2_V  0xFFFF
+#define HINF_DEVICE_ID_FN2_S  16
+/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
+/*description: */
+#define HINF_USER_ID_FN2  0x0000FFFF
+#define HINF_USER_ID_FN2_M  ((HINF_USER_ID_FN2_V)<<(HINF_USER_ID_FN2_S))
+#define HINF_USER_ID_FN2_V  0xFFFF
+#define HINF_USER_ID_FN2_S  0
+
+#define HINF_DATE_REG          (DR_REG_HINF_BASE + 0xFC)
+/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
+/*description: */
+#define HINF_SDIO_DATE  0xFFFFFFFF
+#define HINF_SDIO_DATE_M  ((HINF_SDIO_DATE_V)<<(HINF_SDIO_DATE_S))
+#define HINF_SDIO_DATE_V  0xFFFFFFFF
+#define HINF_SDIO_DATE_S  0
+
+
+
+
+#endif /*_SOC_HINF_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/hinf_struct.h b/components/soc/esp32s2beta/include/soc/hinf_struct.h
new file mode 100644
index 000000000..1c2d9e3b7
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/hinf_struct.h
@@ -0,0 +1,134 @@
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HINF_STRUCT_H_
+#define _SOC_HINF_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t user_id_fn1:  16;
+            uint32_t device_id_fn1:16;
+        };
+        uint32_t val;
+    } cfg_data0;
+    union {
+        struct {
+            uint32_t sdio_enable:      1;
+            uint32_t sdio_ioready1:    1;
+            uint32_t highspeed_enable: 1;
+            uint32_t highspeed_mode:   1;
+            uint32_t sdio_cd_enable:   1;
+            uint32_t sdio_ioready2:    1;
+            uint32_t sdio_int_mask:    1;
+            uint32_t ioenable2:        1;
+            uint32_t cd_disable:       1;
+            uint32_t func1_eps:        1;
+            uint32_t emp:              1;
+            uint32_t ioenable1:        1;
+            uint32_t sdio20_conf0:     4;
+            uint32_t sdio_ver:        12;
+            uint32_t func2_eps:        1;
+            uint32_t sdio20_conf1:     3;
+        };
+        uint32_t val;
+    } cfg_data1;
+    uint32_t reserved_8;
+    uint32_t reserved_c;
+    uint32_t reserved_10;
+    uint32_t reserved_14;
+    uint32_t reserved_18;
+    union {
+        struct {
+            uint32_t pin_state:     8;
+            uint32_t chip_state:    8;
+            uint32_t sdio_rst:      1;
+            uint32_t sdio_ioready0: 1;
+            uint32_t reserved18:   14;
+        };
+        uint32_t val;
+    } cfg_data7;
+    uint32_t cis_conf0;                     /**/
+    uint32_t cis_conf1;                     /**/
+    uint32_t cis_conf2;                     /**/
+    uint32_t cis_conf3;                     /**/
+    uint32_t cis_conf4;                     /**/
+    uint32_t cis_conf5;                     /**/
+    uint32_t cis_conf6;                     /**/
+    uint32_t cis_conf7;                     /**/
+    union {
+        struct {
+            uint32_t user_id_fn2:  16;
+            uint32_t device_id_fn2:16;
+        };
+        uint32_t val;
+    } cfg_data16;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t date;                          /**/
+} hinf_dev_t;
+extern hinf_dev_t HINF;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_HINF_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/host_reg.h b/components/soc/esp32s2beta/include/soc/host_reg.h
new file mode 100644
index 000000000..37aa62146
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/host_reg.h
@@ -0,0 +1,1806 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HOST_REG_H_
+#define _SOC_HOST_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define HOST_SLCHOST_FUNC2_2_REG          (DR_REG_SLCHOST_BASE + 0x20)
+/* HOST_SLC_FUNC1_MDSTAT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define HOST_SLC_FUNC1_MDSTAT  (BIT(0))
+#define HOST_SLC_FUNC1_MDSTAT_M  (BIT(0))
+#define HOST_SLC_FUNC1_MDSTAT_V  0x1
+#define HOST_SLC_FUNC1_MDSTAT_S  0
+
+#define HOST_SLCHOST_GPIO_STATUS0_REG          (DR_REG_SLCHOST_BASE + 0x34)
+/* HOST_GPIO_SDIO_INT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT0  0xFFFFFFFF
+#define HOST_GPIO_SDIO_INT0_M  ((HOST_GPIO_SDIO_INT0_V)<<(HOST_GPIO_SDIO_INT0_S))
+#define HOST_GPIO_SDIO_INT0_V  0xFFFFFFFF
+#define HOST_GPIO_SDIO_INT0_S  0
+
+#define HOST_SLCHOST_GPIO_STATUS1_REG          (DR_REG_SLCHOST_BASE + 0x38)
+/* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT1  0x003FFFFF
+#define HOST_GPIO_SDIO_INT1_M  ((HOST_GPIO_SDIO_INT1_V)<<(HOST_GPIO_SDIO_INT1_S))
+#define HOST_GPIO_SDIO_INT1_V  0x3FFFFF
+#define HOST_GPIO_SDIO_INT1_S  0
+
+#define HOST_SLCHOST_GPIO_IN0_REG          (DR_REG_SLCHOST_BASE + 0x3C)
+/* HOST_GPIO_SDIO_IN0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_IN0  0xFFFFFFFF
+#define HOST_GPIO_SDIO_IN0_M  ((HOST_GPIO_SDIO_IN0_V)<<(HOST_GPIO_SDIO_IN0_S))
+#define HOST_GPIO_SDIO_IN0_V  0xFFFFFFFF
+#define HOST_GPIO_SDIO_IN0_S  0
+
+#define HOST_SLCHOST_GPIO_IN1_REG          (DR_REG_SLCHOST_BASE + 0x40)
+/* HOST_GPIO_SDIO_IN1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_IN1  0x003FFFFF
+#define HOST_GPIO_SDIO_IN1_M  ((HOST_GPIO_SDIO_IN1_V)<<(HOST_GPIO_SDIO_IN1_S))
+#define HOST_GPIO_SDIO_IN1_V  0x3FFFFF
+#define HOST_GPIO_SDIO_IN1_S  0
+
+#define HOST_SLC0HOST_TOKEN_RDATA_REG          (DR_REG_SLCHOST_BASE + 0x44)
+/* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_EOF  0x0000000F
+#define HOST_SLC0_RX_PF_EOF_M  ((HOST_SLC0_RX_PF_EOF_V)<<(HOST_SLC0_RX_PF_EOF_S))
+#define HOST_SLC0_RX_PF_EOF_V  0xF
+#define HOST_SLC0_RX_PF_EOF_S  28
+/* HOST_HOSTSLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_TOKEN1  0x00000FFF
+#define HOST_HOSTSLC0_TOKEN1_M  ((HOST_HOSTSLC0_TOKEN1_V)<<(HOST_HOSTSLC0_TOKEN1_S))
+#define HOST_HOSTSLC0_TOKEN1_V  0xFFF
+#define HOST_HOSTSLC0_TOKEN1_S  16
+/* HOST_SLC0_RX_PF_VALID : RO ;bitpos:[12] ;default: 4'h0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID  (BIT(12))
+#define HOST_SLC0_RX_PF_VALID_M  (BIT(12))
+#define HOST_SLC0_RX_PF_VALID_V  0x1
+#define HOST_SLC0_RX_PF_VALID_S  12
+/* HOST_SLC0_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0  0x00000FFF
+#define HOST_SLC0_TOKEN0_M  ((HOST_SLC0_TOKEN0_V)<<(HOST_SLC0_TOKEN0_S))
+#define HOST_SLC0_TOKEN0_V  0xFFF
+#define HOST_SLC0_TOKEN0_S  0
+
+#define HOST_SLC0_HOST_PF_REG          (DR_REG_SLCHOST_BASE + 0x48)
+/* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define HOST_SLC0_PF_DATA  0xFFFFFFFF
+#define HOST_SLC0_PF_DATA_M  ((HOST_SLC0_PF_DATA_V)<<(HOST_SLC0_PF_DATA_S))
+#define HOST_SLC0_PF_DATA_V  0xFFFFFFFF
+#define HOST_SLC0_PF_DATA_S  0
+
+#define HOST_SLC0HOST_INT_RAW_REG          (DR_REG_SLCHOST_BASE + 0x50)
+/* HOST_GPIO_SDIO_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_RAW  (BIT(25))
+#define HOST_GPIO_SDIO_INT_RAW_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_RAW_V  0x1
+#define HOST_GPIO_SDIO_INT_RAW_S  25
+/* HOST_SLC0_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S  24
+/* HOST_SLC0_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S  23
+/* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_RAW  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_RAW_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_RAW_S  22
+/* HOST_SLC0_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_RAW  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_RAW_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_RAW_S  21
+/* HOST_SLC0_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_RAW  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_RAW_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_RAW_S  20
+/* HOST_SLC0_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_RAW  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_RAW_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_RAW_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_RAW_S  19
+/* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_RAW  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_RAW_S  18
+/* HOST_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_RAW  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_RAW_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_RAW_V  0x1
+#define HOST_SLC0_TX_OVF_INT_RAW_S  17
+/* HOST_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_RAW  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_RAW_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_RAW_V  0x1
+#define HOST_SLC0_RX_UDF_INT_RAW_S  16
+/* HOST_SLC0HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_RAW  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_RAW_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_RAW_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_RAW_S  15
+/* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_RAW  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_RAW_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_RAW_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_RAW_S  14
+/* HOST_SLC0HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_RAW  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_RAW_S  13
+/* HOST_SLC0HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_RAW  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_RAW_S  12
+/* HOST_SLC0_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S  11
+/* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S  10
+/* HOST_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S  9
+/* HOST_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S  8
+/* HOST_SLC0_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S  7
+/* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S  6
+/* HOST_SLC0_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S  5
+/* HOST_SLC0_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S  4
+/* HOST_SLC0_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S  3
+/* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S  2
+/* HOST_SLC0_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S  1
+/* HOST_SLC0_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S  0
+
+#define HOST_SLC0HOST_INT_ST_REG          (DR_REG_SLCHOST_BASE + 0x58)
+/* HOST_GPIO_SDIO_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_ST  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ST_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ST_V  0x1
+#define HOST_GPIO_SDIO_INT_ST_S  25
+/* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S  24
+/* HOST_SLC0_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S  23
+/* HOST_SLC0_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_ST  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ST_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_ST_S  22
+/* HOST_SLC0_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_ST  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ST_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_ST_S  21
+/* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_ST  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ST_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_ST_S  20
+/* HOST_SLC0_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_ST  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ST_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ST_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_ST_S  19
+/* HOST_SLC0_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_ST  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ST_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ST_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ST_S  18
+/* HOST_SLC0_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_ST  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ST_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ST_V  0x1
+#define HOST_SLC0_TX_OVF_INT_ST_S  17
+/* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_ST  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ST_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ST_V  0x1
+#define HOST_SLC0_RX_UDF_INT_ST_S  16
+/* HOST_SLC0HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_ST  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ST_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ST_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_ST_S  15
+/* HOST_SLC0HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_ST  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ST_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ST_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_ST_S  14
+/* HOST_SLC0HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_ST  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ST_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ST_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ST_S  13
+/* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_ST  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ST_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ST_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ST_S  12
+/* HOST_SLC0_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S  11
+/* HOST_SLC0_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S  10
+/* HOST_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S  9
+/* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S  8
+/* HOST_SLC0_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_ST  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ST_S  7
+/* HOST_SLC0_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_ST  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ST_S  6
+/* HOST_SLC0_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_ST  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ST_S  5
+/* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_ST  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ST_S  4
+/* HOST_SLC0_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_ST  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ST_S  3
+/* HOST_SLC0_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_ST  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ST_S  2
+/* HOST_SLC0_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_ST  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ST_S  1
+/* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_ST  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ST_S  0
+
+#define HOST_SLCHOST_PKT_LEN_REG          (DR_REG_SLCHOST_BASE + 0x60)
+/* HOST_HOSTSLC0_LEN_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN_CHECK  0x00000FFF
+#define HOST_HOSTSLC0_LEN_CHECK_M  ((HOST_HOSTSLC0_LEN_CHECK_V)<<(HOST_HOSTSLC0_LEN_CHECK_S))
+#define HOST_HOSTSLC0_LEN_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN_CHECK_S  20
+/* HOST_HOSTSLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN  0x000FFFFF
+#define HOST_HOSTSLC0_LEN_M  ((HOST_HOSTSLC0_LEN_V)<<(HOST_HOSTSLC0_LEN_S))
+#define HOST_HOSTSLC0_LEN_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN_S  0
+
+#define HOST_SLCHOST_STATE_W0_REG          (DR_REG_SLCHOST_BASE + 0x64)
+/* HOST_SLCHOST_STATE3 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE3  0x000000FF
+#define HOST_SLCHOST_STATE3_M  ((HOST_SLCHOST_STATE3_V)<<(HOST_SLCHOST_STATE3_S))
+#define HOST_SLCHOST_STATE3_V  0xFF
+#define HOST_SLCHOST_STATE3_S  24
+/* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE2  0x000000FF
+#define HOST_SLCHOST_STATE2_M  ((HOST_SLCHOST_STATE2_V)<<(HOST_SLCHOST_STATE2_S))
+#define HOST_SLCHOST_STATE2_V  0xFF
+#define HOST_SLCHOST_STATE2_S  16
+/* HOST_SLCHOST_STATE1 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE1  0x000000FF
+#define HOST_SLCHOST_STATE1_M  ((HOST_SLCHOST_STATE1_V)<<(HOST_SLCHOST_STATE1_S))
+#define HOST_SLCHOST_STATE1_V  0xFF
+#define HOST_SLCHOST_STATE1_S  8
+/* HOST_SLCHOST_STATE0 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE0  0x000000FF
+#define HOST_SLCHOST_STATE0_M  ((HOST_SLCHOST_STATE0_V)<<(HOST_SLCHOST_STATE0_S))
+#define HOST_SLCHOST_STATE0_V  0xFF
+#define HOST_SLCHOST_STATE0_S  0
+
+#define HOST_SLCHOST_STATE_W1_REG          (DR_REG_SLCHOST_BASE + 0x68)
+/* HOST_SLCHOST_STATE7 : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE7  0x000000FF
+#define HOST_SLCHOST_STATE7_M  ((HOST_SLCHOST_STATE7_V)<<(HOST_SLCHOST_STATE7_S))
+#define HOST_SLCHOST_STATE7_V  0xFF
+#define HOST_SLCHOST_STATE7_S  24
+/* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE6  0x000000FF
+#define HOST_SLCHOST_STATE6_M  ((HOST_SLCHOST_STATE6_V)<<(HOST_SLCHOST_STATE6_S))
+#define HOST_SLCHOST_STATE6_V  0xFF
+#define HOST_SLCHOST_STATE6_S  16
+/* HOST_SLCHOST_STATE5 : RO ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE5  0x000000FF
+#define HOST_SLCHOST_STATE5_M  ((HOST_SLCHOST_STATE5_V)<<(HOST_SLCHOST_STATE5_S))
+#define HOST_SLCHOST_STATE5_V  0xFF
+#define HOST_SLCHOST_STATE5_S  8
+/* HOST_SLCHOST_STATE4 : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_STATE4  0x000000FF
+#define HOST_SLCHOST_STATE4_M  ((HOST_SLCHOST_STATE4_V)<<(HOST_SLCHOST_STATE4_S))
+#define HOST_SLCHOST_STATE4_V  0xFF
+#define HOST_SLCHOST_STATE4_S  0
+
+#define HOST_SLCHOST_CONF_W_REG(pos) (HOST_SLCHOST_CONF_W0_REG+pos+(pos>23?4:0)+(pos>31?12:0))
+
+#define HOST_SLCHOST_CONF_W0_REG          (DR_REG_SLCHOST_BASE + 0x6C)
+/* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF3  0x000000FF
+#define HOST_SLCHOST_CONF3_M  ((HOST_SLCHOST_CONF3_V)<<(HOST_SLCHOST_CONF3_S))
+#define HOST_SLCHOST_CONF3_V  0xFF
+#define HOST_SLCHOST_CONF3_S  24
+/* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF2  0x000000FF
+#define HOST_SLCHOST_CONF2_M  ((HOST_SLCHOST_CONF2_V)<<(HOST_SLCHOST_CONF2_S))
+#define HOST_SLCHOST_CONF2_V  0xFF
+#define HOST_SLCHOST_CONF2_S  16
+/* HOST_SLCHOST_CONF1 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF1  0x000000FF
+#define HOST_SLCHOST_CONF1_M  ((HOST_SLCHOST_CONF1_V)<<(HOST_SLCHOST_CONF1_S))
+#define HOST_SLCHOST_CONF1_V  0xFF
+#define HOST_SLCHOST_CONF1_S  8
+/* HOST_SLCHOST_CONF0 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF0  0x000000FF
+#define HOST_SLCHOST_CONF0_M  ((HOST_SLCHOST_CONF0_V)<<(HOST_SLCHOST_CONF0_S))
+#define HOST_SLCHOST_CONF0_V  0xFF
+#define HOST_SLCHOST_CONF0_S  0
+
+#define HOST_SLCHOST_CONF_W1_REG          (DR_REG_SLCHOST_BASE + 0x70)
+/* HOST_SLCHOST_CONF7 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF7  0x000000FF
+#define HOST_SLCHOST_CONF7_M  ((HOST_SLCHOST_CONF7_V)<<(HOST_SLCHOST_CONF7_S))
+#define HOST_SLCHOST_CONF7_V  0xFF
+#define HOST_SLCHOST_CONF7_S  24
+/* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF6  0x000000FF
+#define HOST_SLCHOST_CONF6_M  ((HOST_SLCHOST_CONF6_V)<<(HOST_SLCHOST_CONF6_S))
+#define HOST_SLCHOST_CONF6_V  0xFF
+#define HOST_SLCHOST_CONF6_S  16
+/* HOST_SLCHOST_CONF5 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF5  0x000000FF
+#define HOST_SLCHOST_CONF5_M  ((HOST_SLCHOST_CONF5_V)<<(HOST_SLCHOST_CONF5_S))
+#define HOST_SLCHOST_CONF5_V  0xFF
+#define HOST_SLCHOST_CONF5_S  8
+/* HOST_SLCHOST_CONF4 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF4  0x000000FF
+#define HOST_SLCHOST_CONF4_M  ((HOST_SLCHOST_CONF4_V)<<(HOST_SLCHOST_CONF4_S))
+#define HOST_SLCHOST_CONF4_V  0xFF
+#define HOST_SLCHOST_CONF4_S  0
+
+#define HOST_SLCHOST_CONF_W2_REG          (DR_REG_SLCHOST_BASE + 0x74)
+/* HOST_SLCHOST_CONF11 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF11  0x000000FF
+#define HOST_SLCHOST_CONF11_M  ((HOST_SLCHOST_CONF11_V)<<(HOST_SLCHOST_CONF11_S))
+#define HOST_SLCHOST_CONF11_V  0xFF
+#define HOST_SLCHOST_CONF11_S  24
+/* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF10  0x000000FF
+#define HOST_SLCHOST_CONF10_M  ((HOST_SLCHOST_CONF10_V)<<(HOST_SLCHOST_CONF10_S))
+#define HOST_SLCHOST_CONF10_V  0xFF
+#define HOST_SLCHOST_CONF10_S  16
+/* HOST_SLCHOST_CONF9 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF9  0x000000FF
+#define HOST_SLCHOST_CONF9_M  ((HOST_SLCHOST_CONF9_V)<<(HOST_SLCHOST_CONF9_S))
+#define HOST_SLCHOST_CONF9_V  0xFF
+#define HOST_SLCHOST_CONF9_S  8
+/* HOST_SLCHOST_CONF8 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF8  0x000000FF
+#define HOST_SLCHOST_CONF8_M  ((HOST_SLCHOST_CONF8_V)<<(HOST_SLCHOST_CONF8_S))
+#define HOST_SLCHOST_CONF8_V  0xFF
+#define HOST_SLCHOST_CONF8_S  0
+
+#define HOST_SLCHOST_CONF_W3_REG          (DR_REG_SLCHOST_BASE + 0x78)
+/* HOST_SLCHOST_CONF15 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF15  0x000000FF
+#define HOST_SLCHOST_CONF15_M  ((HOST_SLCHOST_CONF15_V)<<(HOST_SLCHOST_CONF15_S))
+#define HOST_SLCHOST_CONF15_V  0xFF
+#define HOST_SLCHOST_CONF15_S  24
+/* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF14  0x000000FF
+#define HOST_SLCHOST_CONF14_M  ((HOST_SLCHOST_CONF14_V)<<(HOST_SLCHOST_CONF14_S))
+#define HOST_SLCHOST_CONF14_V  0xFF
+#define HOST_SLCHOST_CONF14_S  16
+/* HOST_SLCHOST_CONF13 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF13  0x000000FF
+#define HOST_SLCHOST_CONF13_M  ((HOST_SLCHOST_CONF13_V)<<(HOST_SLCHOST_CONF13_S))
+#define HOST_SLCHOST_CONF13_V  0xFF
+#define HOST_SLCHOST_CONF13_S  8
+/* HOST_SLCHOST_CONF12 : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF12  0x000000FF
+#define HOST_SLCHOST_CONF12_M  ((HOST_SLCHOST_CONF12_V)<<(HOST_SLCHOST_CONF12_S))
+#define HOST_SLCHOST_CONF12_V  0xFF
+#define HOST_SLCHOST_CONF12_S  0
+
+#define HOST_SLCHOST_CONF_W4_REG          (DR_REG_SLCHOST_BASE + 0x7C)
+/* HOST_SLCHOST_CONF19 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: Interrupt to target CPU*/
+#define HOST_SLCHOST_CONF19  0x000000FF
+#define HOST_SLCHOST_CONF19_M  ((HOST_SLCHOST_CONF19_V)<<(HOST_SLCHOST_CONF19_S))
+#define HOST_SLCHOST_CONF19_V  0xFF
+#define HOST_SLCHOST_CONF19_S  24
+/* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF18  0x000000FF
+#define HOST_SLCHOST_CONF18_M  ((HOST_SLCHOST_CONF18_V)<<(HOST_SLCHOST_CONF18_S))
+#define HOST_SLCHOST_CONF18_V  0xFF
+#define HOST_SLCHOST_CONF18_S  16
+/* HOST_SLCHOST_CONF17 : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: SLC timeout enable*/
+#define HOST_SLCHOST_CONF17  0x000000FF
+#define HOST_SLCHOST_CONF17_M  ((HOST_SLCHOST_CONF17_V)<<(HOST_SLCHOST_CONF17_S))
+#define HOST_SLCHOST_CONF17_V  0xFF
+#define HOST_SLCHOST_CONF17_S  8
+/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hFF ; */
+/*description: SLC timeout value*/
+#define HOST_SLCHOST_CONF16  0x000000FF
+#define HOST_SLCHOST_CONF16_M  ((HOST_SLCHOST_CONF16_V)<<(HOST_SLCHOST_CONF16_S))
+#define HOST_SLCHOST_CONF16_V  0xFF
+#define HOST_SLCHOST_CONF16_S  0
+
+#define HOST_SLCHOST_CONF_W5_REG          (DR_REG_SLCHOST_BASE + 0x80)
+/* HOST_SLCHOST_CONF23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF23  0x000000FF
+#define HOST_SLCHOST_CONF23_M  ((HOST_SLCHOST_CONF23_V)<<(HOST_SLCHOST_CONF23_S))
+#define HOST_SLCHOST_CONF23_V  0xFF
+#define HOST_SLCHOST_CONF23_S  24
+/* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF22  0x000000FF
+#define HOST_SLCHOST_CONF22_M  ((HOST_SLCHOST_CONF22_V)<<(HOST_SLCHOST_CONF22_S))
+#define HOST_SLCHOST_CONF22_V  0xFF
+#define HOST_SLCHOST_CONF22_S  16
+/* HOST_SLCHOST_CONF21 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF21  0x000000FF
+#define HOST_SLCHOST_CONF21_M  ((HOST_SLCHOST_CONF21_V)<<(HOST_SLCHOST_CONF21_S))
+#define HOST_SLCHOST_CONF21_V  0xFF
+#define HOST_SLCHOST_CONF21_S  8
+/* HOST_SLCHOST_CONF20 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF20  0x000000FF
+#define HOST_SLCHOST_CONF20_M  ((HOST_SLCHOST_CONF20_V)<<(HOST_SLCHOST_CONF20_S))
+#define HOST_SLCHOST_CONF20_V  0xFF
+#define HOST_SLCHOST_CONF20_S  0
+
+#define HOST_SLCHOST_WIN_CMD_REG          (DR_REG_SLCHOST_BASE + 0x84)
+/* HOST_SLCHOST_WIN_CMD : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: */
+#define HOST_SLCHOST_WIN_CMD  0x0000FFFF
+#define HOST_SLCHOST_WIN_CMD_M  ((HOST_SLCHOST_WIN_CMD_V)<<(HOST_SLCHOST_WIN_CMD_S))
+#define HOST_SLCHOST_WIN_CMD_V  0xFFFF
+#define HOST_SLCHOST_WIN_CMD_S  0
+
+#define HOST_SLCHOST_CONF_W6_REG          (DR_REG_SLCHOST_BASE + 0x88)
+/* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF27  0x000000FF
+#define HOST_SLCHOST_CONF27_M  ((HOST_SLCHOST_CONF27_V)<<(HOST_SLCHOST_CONF27_S))
+#define HOST_SLCHOST_CONF27_V  0xFF
+#define HOST_SLCHOST_CONF27_S  24
+/* HOST_SLCHOST_CONF26 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF26  0x000000FF
+#define HOST_SLCHOST_CONF26_M  ((HOST_SLCHOST_CONF26_V)<<(HOST_SLCHOST_CONF26_S))
+#define HOST_SLCHOST_CONF26_V  0xFF
+#define HOST_SLCHOST_CONF26_S  16
+/* HOST_SLCHOST_CONF25 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF25  0x000000FF
+#define HOST_SLCHOST_CONF25_M  ((HOST_SLCHOST_CONF25_V)<<(HOST_SLCHOST_CONF25_S))
+#define HOST_SLCHOST_CONF25_V  0xFF
+#define HOST_SLCHOST_CONF25_S  8
+/* HOST_SLCHOST_CONF24 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF24  0x000000FF
+#define HOST_SLCHOST_CONF24_M  ((HOST_SLCHOST_CONF24_V)<<(HOST_SLCHOST_CONF24_S))
+#define HOST_SLCHOST_CONF24_V  0xFF
+#define HOST_SLCHOST_CONF24_S  0
+
+#define HOST_SLCHOST_CONF_W7_REG          (DR_REG_SLCHOST_BASE + 0x8C)
+/* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF31  0x000000FF
+#define HOST_SLCHOST_CONF31_M  ((HOST_SLCHOST_CONF31_V)<<(HOST_SLCHOST_CONF31_S))
+#define HOST_SLCHOST_CONF31_V  0xFF
+#define HOST_SLCHOST_CONF31_S  24
+/* HOST_SLCHOST_CONF30 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF30  0x000000FF
+#define HOST_SLCHOST_CONF30_M  ((HOST_SLCHOST_CONF30_V)<<(HOST_SLCHOST_CONF30_S))
+#define HOST_SLCHOST_CONF30_V  0xFF
+#define HOST_SLCHOST_CONF30_S  16
+/* HOST_SLCHOST_CONF29 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF29  0x000000FF
+#define HOST_SLCHOST_CONF29_M  ((HOST_SLCHOST_CONF29_V)<<(HOST_SLCHOST_CONF29_S))
+#define HOST_SLCHOST_CONF29_V  0xFF
+#define HOST_SLCHOST_CONF29_S  8
+/* HOST_SLCHOST_CONF28 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF28  0x000000FF
+#define HOST_SLCHOST_CONF28_M  ((HOST_SLCHOST_CONF28_V)<<(HOST_SLCHOST_CONF28_S))
+#define HOST_SLCHOST_CONF28_V  0xFF
+#define HOST_SLCHOST_CONF28_S  0
+
+#define HOST_SLCHOST_PKT_LEN0_REG          (DR_REG_SLCHOST_BASE + 0x90)
+/* HOST_HOSTSLC0_LEN0_CHECK : RO ;bitpos:[31:20] ;default: 12'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN0_CHECK  0x00000FFF
+#define HOST_HOSTSLC0_LEN0_CHECK_M  ((HOST_HOSTSLC0_LEN0_CHECK_V)<<(HOST_HOSTSLC0_LEN0_CHECK_S))
+#define HOST_HOSTSLC0_LEN0_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN0_CHECK_S  20
+/* HOST_HOSTSLC0_LEN0 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN0  0x000FFFFF
+#define HOST_HOSTSLC0_LEN0_M  ((HOST_HOSTSLC0_LEN0_V)<<(HOST_HOSTSLC0_LEN0_S))
+#define HOST_HOSTSLC0_LEN0_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN0_S  0
+
+#define HOST_SLCHOST_PKT_LEN1_REG          (DR_REG_SLCHOST_BASE + 0x94)
+/* HOST_HOSTSLC0_LEN1_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN1_CHECK  0x00000FFF
+#define HOST_HOSTSLC0_LEN1_CHECK_M  ((HOST_HOSTSLC0_LEN1_CHECK_V)<<(HOST_HOSTSLC0_LEN1_CHECK_S))
+#define HOST_HOSTSLC0_LEN1_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN1_CHECK_S  20
+/* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN1  0x000FFFFF
+#define HOST_HOSTSLC0_LEN1_M  ((HOST_HOSTSLC0_LEN1_V)<<(HOST_HOSTSLC0_LEN1_S))
+#define HOST_HOSTSLC0_LEN1_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN1_S  0
+
+#define HOST_SLCHOST_PKT_LEN2_REG          (DR_REG_SLCHOST_BASE + 0x98)
+/* HOST_HOSTSLC0_LEN2_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN2_CHECK  0x00000FFF
+#define HOST_HOSTSLC0_LEN2_CHECK_M  ((HOST_HOSTSLC0_LEN2_CHECK_V)<<(HOST_HOSTSLC0_LEN2_CHECK_S))
+#define HOST_HOSTSLC0_LEN2_CHECK_V  0xFFF
+#define HOST_HOSTSLC0_LEN2_CHECK_S  20
+/* HOST_HOSTSLC0_LEN2 : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define HOST_HOSTSLC0_LEN2  0x000FFFFF
+#define HOST_HOSTSLC0_LEN2_M  ((HOST_HOSTSLC0_LEN2_V)<<(HOST_HOSTSLC0_LEN2_S))
+#define HOST_HOSTSLC0_LEN2_V  0xFFFFF
+#define HOST_HOSTSLC0_LEN2_S  0
+
+#define HOST_SLCHOST_CONF_W8_REG          (DR_REG_SLCHOST_BASE + 0x9C)
+/* HOST_SLCHOST_CONF35 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF35  0x000000FF
+#define HOST_SLCHOST_CONF35_M  ((HOST_SLCHOST_CONF35_V)<<(HOST_SLCHOST_CONF35_S))
+#define HOST_SLCHOST_CONF35_V  0xFF
+#define HOST_SLCHOST_CONF35_S  24
+/* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF34  0x000000FF
+#define HOST_SLCHOST_CONF34_M  ((HOST_SLCHOST_CONF34_V)<<(HOST_SLCHOST_CONF34_S))
+#define HOST_SLCHOST_CONF34_V  0xFF
+#define HOST_SLCHOST_CONF34_S  16
+/* HOST_SLCHOST_CONF33 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF33  0x000000FF
+#define HOST_SLCHOST_CONF33_M  ((HOST_SLCHOST_CONF33_V)<<(HOST_SLCHOST_CONF33_S))
+#define HOST_SLCHOST_CONF33_V  0xFF
+#define HOST_SLCHOST_CONF33_S  8
+/* HOST_SLCHOST_CONF32 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF32  0x000000FF
+#define HOST_SLCHOST_CONF32_M  ((HOST_SLCHOST_CONF32_V)<<(HOST_SLCHOST_CONF32_S))
+#define HOST_SLCHOST_CONF32_V  0xFF
+#define HOST_SLCHOST_CONF32_S  0
+
+#define HOST_SLCHOST_CONF_W9_REG          (DR_REG_SLCHOST_BASE + 0xA0)
+/* HOST_SLCHOST_CONF39 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF39  0x000000FF
+#define HOST_SLCHOST_CONF39_M  ((HOST_SLCHOST_CONF39_V)<<(HOST_SLCHOST_CONF39_S))
+#define HOST_SLCHOST_CONF39_V  0xFF
+#define HOST_SLCHOST_CONF39_S  24
+/* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF38  0x000000FF
+#define HOST_SLCHOST_CONF38_M  ((HOST_SLCHOST_CONF38_V)<<(HOST_SLCHOST_CONF38_S))
+#define HOST_SLCHOST_CONF38_V  0xFF
+#define HOST_SLCHOST_CONF38_S  16
+/* HOST_SLCHOST_CONF37 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF37  0x000000FF
+#define HOST_SLCHOST_CONF37_M  ((HOST_SLCHOST_CONF37_V)<<(HOST_SLCHOST_CONF37_S))
+#define HOST_SLCHOST_CONF37_V  0xFF
+#define HOST_SLCHOST_CONF37_S  8
+/* HOST_SLCHOST_CONF36 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF36  0x000000FF
+#define HOST_SLCHOST_CONF36_M  ((HOST_SLCHOST_CONF36_V)<<(HOST_SLCHOST_CONF36_S))
+#define HOST_SLCHOST_CONF36_V  0xFF
+#define HOST_SLCHOST_CONF36_S  0
+
+#define HOST_SLCHOST_CONF_W10_REG          (DR_REG_SLCHOST_BASE + 0xA4)
+/* HOST_SLCHOST_CONF43 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF43  0x000000FF
+#define HOST_SLCHOST_CONF43_M  ((HOST_SLCHOST_CONF43_V)<<(HOST_SLCHOST_CONF43_S))
+#define HOST_SLCHOST_CONF43_V  0xFF
+#define HOST_SLCHOST_CONF43_S  24
+/* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF42  0x000000FF
+#define HOST_SLCHOST_CONF42_M  ((HOST_SLCHOST_CONF42_V)<<(HOST_SLCHOST_CONF42_S))
+#define HOST_SLCHOST_CONF42_V  0xFF
+#define HOST_SLCHOST_CONF42_S  16
+/* HOST_SLCHOST_CONF41 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF41  0x000000FF
+#define HOST_SLCHOST_CONF41_M  ((HOST_SLCHOST_CONF41_V)<<(HOST_SLCHOST_CONF41_S))
+#define HOST_SLCHOST_CONF41_V  0xFF
+#define HOST_SLCHOST_CONF41_S  8
+/* HOST_SLCHOST_CONF40 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF40  0x000000FF
+#define HOST_SLCHOST_CONF40_M  ((HOST_SLCHOST_CONF40_V)<<(HOST_SLCHOST_CONF40_S))
+#define HOST_SLCHOST_CONF40_V  0xFF
+#define HOST_SLCHOST_CONF40_S  0
+
+#define HOST_SLCHOST_CONF_W11_REG          (DR_REG_SLCHOST_BASE + 0xA8)
+/* HOST_SLCHOST_CONF47 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF47  0x000000FF
+#define HOST_SLCHOST_CONF47_M  ((HOST_SLCHOST_CONF47_V)<<(HOST_SLCHOST_CONF47_S))
+#define HOST_SLCHOST_CONF47_V  0xFF
+#define HOST_SLCHOST_CONF47_S  24
+/* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF46  0x000000FF
+#define HOST_SLCHOST_CONF46_M  ((HOST_SLCHOST_CONF46_V)<<(HOST_SLCHOST_CONF46_S))
+#define HOST_SLCHOST_CONF46_V  0xFF
+#define HOST_SLCHOST_CONF46_S  16
+/* HOST_SLCHOST_CONF45 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF45  0x000000FF
+#define HOST_SLCHOST_CONF45_M  ((HOST_SLCHOST_CONF45_V)<<(HOST_SLCHOST_CONF45_S))
+#define HOST_SLCHOST_CONF45_V  0xFF
+#define HOST_SLCHOST_CONF45_S  8
+/* HOST_SLCHOST_CONF44 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF44  0x000000FF
+#define HOST_SLCHOST_CONF44_M  ((HOST_SLCHOST_CONF44_V)<<(HOST_SLCHOST_CONF44_S))
+#define HOST_SLCHOST_CONF44_V  0xFF
+#define HOST_SLCHOST_CONF44_S  0
+
+#define HOST_SLCHOST_CONF_W12_REG          (DR_REG_SLCHOST_BASE + 0xAC)
+/* HOST_SLCHOST_CONF51 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF51  0x000000FF
+#define HOST_SLCHOST_CONF51_M  ((HOST_SLCHOST_CONF51_V)<<(HOST_SLCHOST_CONF51_S))
+#define HOST_SLCHOST_CONF51_V  0xFF
+#define HOST_SLCHOST_CONF51_S  24
+/* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF50  0x000000FF
+#define HOST_SLCHOST_CONF50_M  ((HOST_SLCHOST_CONF50_V)<<(HOST_SLCHOST_CONF50_S))
+#define HOST_SLCHOST_CONF50_V  0xFF
+#define HOST_SLCHOST_CONF50_S  16
+/* HOST_SLCHOST_CONF49 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF49  0x000000FF
+#define HOST_SLCHOST_CONF49_M  ((HOST_SLCHOST_CONF49_V)<<(HOST_SLCHOST_CONF49_S))
+#define HOST_SLCHOST_CONF49_V  0xFF
+#define HOST_SLCHOST_CONF49_S  8
+/* HOST_SLCHOST_CONF48 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF48  0x000000FF
+#define HOST_SLCHOST_CONF48_M  ((HOST_SLCHOST_CONF48_V)<<(HOST_SLCHOST_CONF48_S))
+#define HOST_SLCHOST_CONF48_V  0xFF
+#define HOST_SLCHOST_CONF48_S  0
+
+#define HOST_SLCHOST_CONF_W13_REG          (DR_REG_SLCHOST_BASE + 0xB0)
+/* HOST_SLCHOST_CONF55 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF55  0x000000FF
+#define HOST_SLCHOST_CONF55_M  ((HOST_SLCHOST_CONF55_V)<<(HOST_SLCHOST_CONF55_S))
+#define HOST_SLCHOST_CONF55_V  0xFF
+#define HOST_SLCHOST_CONF55_S  24
+/* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF54  0x000000FF
+#define HOST_SLCHOST_CONF54_M  ((HOST_SLCHOST_CONF54_V)<<(HOST_SLCHOST_CONF54_S))
+#define HOST_SLCHOST_CONF54_V  0xFF
+#define HOST_SLCHOST_CONF54_S  16
+/* HOST_SLCHOST_CONF53 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF53  0x000000FF
+#define HOST_SLCHOST_CONF53_M  ((HOST_SLCHOST_CONF53_V)<<(HOST_SLCHOST_CONF53_S))
+#define HOST_SLCHOST_CONF53_V  0xFF
+#define HOST_SLCHOST_CONF53_S  8
+/* HOST_SLCHOST_CONF52 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF52  0x000000FF
+#define HOST_SLCHOST_CONF52_M  ((HOST_SLCHOST_CONF52_V)<<(HOST_SLCHOST_CONF52_S))
+#define HOST_SLCHOST_CONF52_V  0xFF
+#define HOST_SLCHOST_CONF52_S  0
+
+#define HOST_SLCHOST_CONF_W14_REG          (DR_REG_SLCHOST_BASE + 0xB4)
+/* HOST_SLCHOST_CONF59 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF59  0x000000FF
+#define HOST_SLCHOST_CONF59_M  ((HOST_SLCHOST_CONF59_V)<<(HOST_SLCHOST_CONF59_S))
+#define HOST_SLCHOST_CONF59_V  0xFF
+#define HOST_SLCHOST_CONF59_S  24
+/* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF58  0x000000FF
+#define HOST_SLCHOST_CONF58_M  ((HOST_SLCHOST_CONF58_V)<<(HOST_SLCHOST_CONF58_S))
+#define HOST_SLCHOST_CONF58_V  0xFF
+#define HOST_SLCHOST_CONF58_S  16
+/* HOST_SLCHOST_CONF57 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF57  0x000000FF
+#define HOST_SLCHOST_CONF57_M  ((HOST_SLCHOST_CONF57_V)<<(HOST_SLCHOST_CONF57_S))
+#define HOST_SLCHOST_CONF57_V  0xFF
+#define HOST_SLCHOST_CONF57_S  8
+/* HOST_SLCHOST_CONF56 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF56  0x000000FF
+#define HOST_SLCHOST_CONF56_M  ((HOST_SLCHOST_CONF56_V)<<(HOST_SLCHOST_CONF56_S))
+#define HOST_SLCHOST_CONF56_V  0xFF
+#define HOST_SLCHOST_CONF56_S  0
+
+#define HOST_SLCHOST_CONF_W15_REG          (DR_REG_SLCHOST_BASE + 0xB8)
+/* HOST_SLCHOST_CONF63 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF63  0x000000FF
+#define HOST_SLCHOST_CONF63_M  ((HOST_SLCHOST_CONF63_V)<<(HOST_SLCHOST_CONF63_S))
+#define HOST_SLCHOST_CONF63_V  0xFF
+#define HOST_SLCHOST_CONF63_S  24
+/* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF62  0x000000FF
+#define HOST_SLCHOST_CONF62_M  ((HOST_SLCHOST_CONF62_V)<<(HOST_SLCHOST_CONF62_S))
+#define HOST_SLCHOST_CONF62_V  0xFF
+#define HOST_SLCHOST_CONF62_S  16
+/* HOST_SLCHOST_CONF61 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF61  0x000000FF
+#define HOST_SLCHOST_CONF61_M  ((HOST_SLCHOST_CONF61_V)<<(HOST_SLCHOST_CONF61_S))
+#define HOST_SLCHOST_CONF61_V  0xFF
+#define HOST_SLCHOST_CONF61_S  8
+/* HOST_SLCHOST_CONF60 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define HOST_SLCHOST_CONF60  0x000000FF
+#define HOST_SLCHOST_CONF60_M  ((HOST_SLCHOST_CONF60_V)<<(HOST_SLCHOST_CONF60_S))
+#define HOST_SLCHOST_CONF60_V  0xFF
+#define HOST_SLCHOST_CONF60_S  0
+
+#define HOST_SLCHOST_CHECK_SUM0_REG          (DR_REG_SLCHOST_BASE + 0xBC)
+/* HOST_SLCHOST_CHECK_SUM0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLCHOST_CHECK_SUM0  0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM0_M  ((HOST_SLCHOST_CHECK_SUM0_V)<<(HOST_SLCHOST_CHECK_SUM0_S))
+#define HOST_SLCHOST_CHECK_SUM0_V  0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM0_S  0
+
+#define HOST_SLCHOST_CHECK_SUM1_REG          (DR_REG_SLCHOST_BASE + 0xC0)
+/* HOST_SLCHOST_CHECK_SUM1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLCHOST_CHECK_SUM1  0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM1_M  ((HOST_SLCHOST_CHECK_SUM1_V)<<(HOST_SLCHOST_CHECK_SUM1_S))
+#define HOST_SLCHOST_CHECK_SUM1_V  0xFFFFFFFF
+#define HOST_SLCHOST_CHECK_SUM1_S  0
+
+#define HOST_SLC0HOST_TOKEN_WDATA_REG          (DR_REG_SLCHOST_BASE + 0xC8)
+/* HOST_SLC0HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN1_WD  0x00000FFF
+#define HOST_SLC0HOST_TOKEN1_WD_M  ((HOST_SLC0HOST_TOKEN1_WD_V)<<(HOST_SLC0HOST_TOKEN1_WD_S))
+#define HOST_SLC0HOST_TOKEN1_WD_V  0xFFF
+#define HOST_SLC0HOST_TOKEN1_WD_S  16
+/* HOST_SLC0HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN0_WD  0x00000FFF
+#define HOST_SLC0HOST_TOKEN0_WD_M  ((HOST_SLC0HOST_TOKEN0_WD_V)<<(HOST_SLC0HOST_TOKEN0_WD_S))
+#define HOST_SLC0HOST_TOKEN0_WD_V  0xFFF
+#define HOST_SLC0HOST_TOKEN0_WD_S  0
+
+#define HOST_SLCHOST_TOKEN_CON_REG          (DR_REG_SLCHOST_BASE + 0xD0)
+/* HOST_SLC0HOST_LEN_WR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_LEN_WR  (BIT(8))
+#define HOST_SLC0HOST_LEN_WR_M  (BIT(8))
+#define HOST_SLC0HOST_LEN_WR_V  0x1
+#define HOST_SLC0HOST_LEN_WR_S  8
+/* HOST_SLC0HOST_TOKEN1_WR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN1_WR  (BIT(3))
+#define HOST_SLC0HOST_TOKEN1_WR_M  (BIT(3))
+#define HOST_SLC0HOST_TOKEN1_WR_V  0x1
+#define HOST_SLC0HOST_TOKEN1_WR_S  3
+/* HOST_SLC0HOST_TOKEN0_WR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN0_WR  (BIT(2))
+#define HOST_SLC0HOST_TOKEN0_WR_M  (BIT(2))
+#define HOST_SLC0HOST_TOKEN0_WR_V  0x1
+#define HOST_SLC0HOST_TOKEN0_WR_S  2
+/* HOST_SLC0HOST_TOKEN1_DEC : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN1_DEC  (BIT(1))
+#define HOST_SLC0HOST_TOKEN1_DEC_M  (BIT(1))
+#define HOST_SLC0HOST_TOKEN1_DEC_V  0x1
+#define HOST_SLC0HOST_TOKEN1_DEC_S  1
+/* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TOKEN0_DEC  (BIT(0))
+#define HOST_SLC0HOST_TOKEN0_DEC_M  (BIT(0))
+#define HOST_SLC0HOST_TOKEN0_DEC_V  0x1
+#define HOST_SLC0HOST_TOKEN0_DEC_S  0
+
+#define HOST_SLC0HOST_INT_CLR_REG          (DR_REG_SLCHOST_BASE + 0xD4)
+/* HOST_GPIO_SDIO_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_CLR  (BIT(25))
+#define HOST_GPIO_SDIO_INT_CLR_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_CLR_V  0x1
+#define HOST_GPIO_SDIO_INT_CLR_S  25
+/* HOST_SLC0_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S  24
+/* HOST_SLC0_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S  23
+/* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_CLR  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_CLR_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_CLR_S  22
+/* HOST_SLC0_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_CLR  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_CLR_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_CLR_S  21
+/* HOST_SLC0_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_CLR  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_CLR_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_CLR_S  20
+/* HOST_SLC0_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_CLR  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_CLR_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_CLR_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_CLR_S  19
+/* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_CLR  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_CLR_S  18
+/* HOST_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_CLR  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_CLR_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_CLR_V  0x1
+#define HOST_SLC0_TX_OVF_INT_CLR_S  17
+/* HOST_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_CLR  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_CLR_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_CLR_V  0x1
+#define HOST_SLC0_RX_UDF_INT_CLR_S  16
+/* HOST_SLC0HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_CLR  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_CLR_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_CLR_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_CLR_S  15
+/* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_CLR  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_CLR_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_CLR_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_CLR_S  14
+/* HOST_SLC0HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_CLR  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_CLR_S  13
+/* HOST_SLC0HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_CLR  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_CLR_S  12
+/* HOST_SLC0_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S  11
+/* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S  10
+/* HOST_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S  9
+/* HOST_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S  8
+/* HOST_SLC0_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S  7
+/* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S  6
+/* HOST_SLC0_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S  5
+/* HOST_SLC0_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S  4
+/* HOST_SLC0_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S  3
+/* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S  2
+/* HOST_SLC0_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S  1
+/* HOST_SLC0_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S  0
+
+#define HOST_SLC0HOST_FUNC1_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xDC)
+/* HOST_FN1_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_GPIO_SDIO_INT_ENA  (BIT(25))
+#define HOST_FN1_GPIO_SDIO_INT_ENA_M  (BIT(25))
+#define HOST_FN1_GPIO_SDIO_INT_ENA_V  0x1
+#define HOST_FN1_GPIO_SDIO_INT_ENA_S  25
+/* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA  (BIT(24))
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S  24
+/* HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA  (BIT(23))
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S  23
+/* HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA  (BIT(22))
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M  (BIT(22))
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S  22
+/* HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA  (BIT(21))
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M  (BIT(21))
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S  21
+/* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA  (BIT(20))
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M  (BIT(20))
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S  20
+/* HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA  (BIT(19))
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M  (BIT(19))
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S  19
+/* HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA  (BIT(18))
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M  (BIT(18))
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S  18
+/* HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA  (BIT(17))
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M  (BIT(17))
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S  17
+/* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA  (BIT(16))
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M  (BIT(16))
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S  16
+/* HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA  (BIT(15))
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M  (BIT(15))
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S  15
+/* HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA  (BIT(14))
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M  (BIT(14))
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S  14
+/* HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA  (BIT(13))
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M  (BIT(13))
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S  13
+/* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA  (BIT(12))
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M  (BIT(12))
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V  0x1
+#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S  12
+/* HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA  (BIT(11))
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S  11
+/* HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA  (BIT(10))
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S  10
+/* HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(9))
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S  9
+/* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(8))
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S  8
+/* HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA  (BIT(7))
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M  (BIT(7))
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S  7
+/* HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA  (BIT(6))
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M  (BIT(6))
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S  6
+/* HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA  (BIT(5))
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M  (BIT(5))
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S  5
+/* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA  (BIT(4))
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M  (BIT(4))
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S  4
+/* HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA  (BIT(3))
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M  (BIT(3))
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S  3
+/* HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA  (BIT(2))
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M  (BIT(2))
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S  2
+/* HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA  (BIT(1))
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M  (BIT(1))
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S  1
+/* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA  (BIT(0))
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M  (BIT(0))
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V  0x1
+#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S  0
+
+#define HOST_SLC0HOST_INT_ENA_REG          (DR_REG_SLCHOST_BASE + 0xEC)
+/* HOST_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_ENA  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA_V  0x1
+#define HOST_GPIO_SDIO_INT_ENA_S  25
+/* HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S  24
+/* HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S  23
+/* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_ENA  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_ENA_S  22
+/* HOST_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_ENA  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_ENA_S  21
+/* HOST_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_ENA  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_ENA_S  20
+/* HOST_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_ENA  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_ENA_S  19
+/* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_ENA  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ENA_S  18
+/* HOST_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_ENA  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA_V  0x1
+#define HOST_SLC0_TX_OVF_INT_ENA_S  17
+/* HOST_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_ENA  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA_V  0x1
+#define HOST_SLC0_RX_UDF_INT_ENA_S  16
+/* HOST_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_ENA  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_ENA_S  15
+/* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_ENA  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_ENA_S  14
+/* HOST_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_ENA  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ENA_S  13
+/* HOST_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_ENA  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ENA_S  12
+/* HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S  11
+/* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S  10
+/* HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S  9
+/* HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S  8
+/* HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S  7
+/* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S  6
+/* HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S  5
+/* HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S  4
+/* HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S  3
+/* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S  2
+/* HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S  1
+/* HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S  0
+
+#define HOST_SLC0HOST_RX_INFOR_REG          (DR_REG_SLCHOST_BASE + 0xF4)
+/* HOST_SLC0HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_INFOR  0x000FFFFF
+#define HOST_SLC0HOST_RX_INFOR_M  ((HOST_SLC0HOST_RX_INFOR_V)<<(HOST_SLC0HOST_RX_INFOR_S))
+#define HOST_SLC0HOST_RX_INFOR_V  0xFFFFF
+#define HOST_SLC0HOST_RX_INFOR_S  0
+
+#define HOST_SLC0HOST_LEN_WD_REG          (DR_REG_SLCHOST_BASE + 0xFC)
+/* HOST_SLC0HOST_LEN_WD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_LEN_WD  0xFFFFFFFF
+#define HOST_SLC0HOST_LEN_WD_M  ((HOST_SLC0HOST_LEN_WD_V)<<(HOST_SLC0HOST_LEN_WD_S))
+#define HOST_SLC0HOST_LEN_WD_V  0xFFFFFFFF
+#define HOST_SLC0HOST_LEN_WD_S  0
+
+#define HOST_SLC_APBWIN_WDATA_REG          (DR_REG_SLCHOST_BASE + 0x100)
+/* HOST_SLC_APBWIN_WDATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_WDATA  0xFFFFFFFF
+#define HOST_SLC_APBWIN_WDATA_M  ((HOST_SLC_APBWIN_WDATA_V)<<(HOST_SLC_APBWIN_WDATA_S))
+#define HOST_SLC_APBWIN_WDATA_V  0xFFFFFFFF
+#define HOST_SLC_APBWIN_WDATA_S  0
+
+#define HOST_SLC_APBWIN_CONF_REG          (DR_REG_SLCHOST_BASE + 0x104)
+/* HOST_SLC_APBWIN_BUS : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_BUS  (BIT(30))
+#define HOST_SLC_APBWIN_BUS_M  (BIT(30))
+#define HOST_SLC_APBWIN_BUS_V  0x1
+#define HOST_SLC_APBWIN_BUS_S  30
+/* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_START  (BIT(29))
+#define HOST_SLC_APBWIN_START_M  (BIT(29))
+#define HOST_SLC_APBWIN_START_V  0x1
+#define HOST_SLC_APBWIN_START_S  29
+/* HOST_SLC_APBWIN_WR : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_WR  (BIT(28))
+#define HOST_SLC_APBWIN_WR_M  (BIT(28))
+#define HOST_SLC_APBWIN_WR_V  0x1
+#define HOST_SLC_APBWIN_WR_S  28
+/* HOST_SLC_APBWIN_ADDR : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_ADDR  0x0FFFFFFF
+#define HOST_SLC_APBWIN_ADDR_M  ((HOST_SLC_APBWIN_ADDR_V)<<(HOST_SLC_APBWIN_ADDR_S))
+#define HOST_SLC_APBWIN_ADDR_V  0xFFFFFFF
+#define HOST_SLC_APBWIN_ADDR_S  0
+
+#define HOST_SLC_APBWIN_RDATA_REG          (DR_REG_SLCHOST_BASE + 0x108)
+/* HOST_SLC_APBWIN_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define HOST_SLC_APBWIN_RDATA  0xFFFFFFFF
+#define HOST_SLC_APBWIN_RDATA_M  ((HOST_SLC_APBWIN_RDATA_V)<<(HOST_SLC_APBWIN_RDATA_S))
+#define HOST_SLC_APBWIN_RDATA_V  0xFFFFFFFF
+#define HOST_SLC_APBWIN_RDATA_S  0
+
+#define HOST_SLCHOST_RDCLR0_REG          (DR_REG_SLCHOST_BASE + 0x10C)
+/* HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */
+/*description: */
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR  0x000001FF
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M  ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT6_CLRADDR_S))
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V  0x1FF
+#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S  9
+/* HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h44 ; */
+/*description: */
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR  0x000001FF
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M  ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V)<<(HOST_SLCHOST_SLC0_BIT7_CLRADDR_S))
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V  0x1FF
+#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S  0
+
+#define HOST_SLC0HOST_INT_ENA1_REG          (DR_REG_SLCHOST_BASE + 0x114)
+/* HOST_GPIO_SDIO_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_GPIO_SDIO_INT_ENA1  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA1_M  (BIT(25))
+#define HOST_GPIO_SDIO_INT_ENA1_V  0x1
+#define HOST_GPIO_SDIO_INT_ENA1_S  25
+/* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M  (BIT(24))
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V  0x1
+#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S  24
+/* HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M  (BIT(23))
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V  0x1
+#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S  23
+/* HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT3_INT_ENA1  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_M  (BIT(22))
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT3_INT_ENA1_S  22
+/* HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT2_INT_ENA1  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_M  (BIT(21))
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT2_INT_ENA1_S  21
+/* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT1_INT_ENA1  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_M  (BIT(20))
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT1_INT_ENA1_S  20
+/* HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_EXT_BIT0_INT_ENA1  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_M  (BIT(19))
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_V  0x1
+#define HOST_SLC0_EXT_BIT0_INT_ENA1_S  19
+/* HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M  (BIT(18))
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V  0x1
+#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S  18
+/* HOST_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TX_OVF_INT_ENA1  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA1_M  (BIT(17))
+#define HOST_SLC0_TX_OVF_INT_ENA1_V  0x1
+#define HOST_SLC0_TX_OVF_INT_ENA1_S  17
+/* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_RX_UDF_INT_ENA1  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA1_M  (BIT(16))
+#define HOST_SLC0_RX_UDF_INT_ENA1_V  0x1
+#define HOST_SLC0_RX_UDF_INT_ENA1_S  16
+/* HOST_SLC0HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_TX_START_INT_ENA1  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA1_M  (BIT(15))
+#define HOST_SLC0HOST_TX_START_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_TX_START_INT_ENA1_S  15
+/* HOST_SLC0HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_START_INT_ENA1  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA1_M  (BIT(14))
+#define HOST_SLC0HOST_RX_START_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_RX_START_INT_ENA1_S  14
+/* HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M  (BIT(13))
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S  13
+/* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M  (BIT(12))
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V  0x1
+#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S  12
+/* HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M  (BIT(11))
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S  11
+/* HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M  (BIT(10))
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S  10
+/* HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(9))
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S  9
+/* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(8))
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
+#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S  8
+/* HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M  (BIT(7))
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S  7
+/* HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M  (BIT(6))
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S  6
+/* HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M  (BIT(5))
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S  5
+/* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M  (BIT(4))
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S  4
+/* HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M  (BIT(3))
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S  3
+/* HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M  (BIT(2))
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S  2
+/* HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M  (BIT(1))
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S  1
+/* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M  (BIT(0))
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V  0x1
+#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S  0
+
+#define HOST_SLCHOSTDATE_REG          (DR_REG_SLCHOST_BASE + 0x178)
+/* HOST_SLCHOST_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */
+/*description: */
+#define HOST_SLCHOST_DATE  0xFFFFFFFF
+#define HOST_SLCHOST_DATE_M  ((HOST_SLCHOST_DATE_V)<<(HOST_SLCHOST_DATE_S))
+#define HOST_SLCHOST_DATE_V  0xFFFFFFFF
+#define HOST_SLCHOST_DATE_S  0
+
+#define HOST_SLCHOSTID_REG          (DR_REG_SLCHOST_BASE + 0x17C)
+/* HOST_SLCHOST_ID : R/W ;bitpos:[31:0] ;default: 32'h0600 ; */
+/*description: */
+#define HOST_SLCHOST_ID  0xFFFFFFFF
+#define HOST_SLCHOST_ID_M  ((HOST_SLCHOST_ID_V)<<(HOST_SLCHOST_ID_S))
+#define HOST_SLCHOST_ID_V  0xFFFFFFFF
+#define HOST_SLCHOST_ID_S  0
+
+#define HOST_SLCHOST_CONF_REG          (DR_REG_SLCHOST_BASE + 0x1F0)
+/* HOST_HSPEED_CON_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define HOST_HSPEED_CON_EN  (BIT(27))
+#define HOST_HSPEED_CON_EN_M  (BIT(27))
+#define HOST_HSPEED_CON_EN_V  0x1
+#define HOST_HSPEED_CON_EN_S  27
+/* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SDIO_PAD_PULLUP  (BIT(26))
+#define HOST_SDIO_PAD_PULLUP_M  (BIT(26))
+#define HOST_SDIO_PAD_PULLUP_V  0x1
+#define HOST_SDIO_PAD_PULLUP_S  26
+/* HOST_SDIO20_INT_DELAY : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define HOST_SDIO20_INT_DELAY  (BIT(25))
+#define HOST_SDIO20_INT_DELAY_M  (BIT(25))
+#define HOST_SDIO20_INT_DELAY_V  0x1
+#define HOST_SDIO20_INT_DELAY_S  25
+/* HOST_FRC_QUICK_IN : R/W ;bitpos:[24:20] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_QUICK_IN  0x0000001F
+#define HOST_FRC_QUICK_IN_M  ((HOST_FRC_QUICK_IN_V)<<(HOST_FRC_QUICK_IN_S))
+#define HOST_FRC_QUICK_IN_V  0x1F
+#define HOST_FRC_QUICK_IN_S  20
+/* HOST_FRC_POS_SAMP : R/W ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_POS_SAMP  0x0000001F
+#define HOST_FRC_POS_SAMP_M  ((HOST_FRC_POS_SAMP_V)<<(HOST_FRC_POS_SAMP_S))
+#define HOST_FRC_POS_SAMP_V  0x1F
+#define HOST_FRC_POS_SAMP_S  15
+/* HOST_FRC_NEG_SAMP : R/W ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_NEG_SAMP  0x0000001F
+#define HOST_FRC_NEG_SAMP_M  ((HOST_FRC_NEG_SAMP_V)<<(HOST_FRC_NEG_SAMP_S))
+#define HOST_FRC_NEG_SAMP_V  0x1F
+#define HOST_FRC_NEG_SAMP_S  10
+/* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_SDIO20  0x0000001F
+#define HOST_FRC_SDIO20_M  ((HOST_FRC_SDIO20_V)<<(HOST_FRC_SDIO20_S))
+#define HOST_FRC_SDIO20_V  0x1F
+#define HOST_FRC_SDIO20_S  5
+/* HOST_FRC_SDIO11 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: */
+#define HOST_FRC_SDIO11  0x0000001F
+#define HOST_FRC_SDIO11_M  ((HOST_FRC_SDIO11_V)<<(HOST_FRC_SDIO11_S))
+#define HOST_FRC_SDIO11_V  0x1F
+#define HOST_FRC_SDIO11_S  0
+
+#define HOST_SLCHOST_INF_ST_REG          (DR_REG_SLCHOST_BASE + 0x1F4)
+/* HOST_SDIO_QUICK_IN : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: */
+#define HOST_SDIO_QUICK_IN  0x0000001F
+#define HOST_SDIO_QUICK_IN_M  ((HOST_SDIO_QUICK_IN_V)<<(HOST_SDIO_QUICK_IN_S))
+#define HOST_SDIO_QUICK_IN_V  0x1F
+#define HOST_SDIO_QUICK_IN_S  10
+/* HOST_SDIO_NEG_SAMP : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: */
+#define HOST_SDIO_NEG_SAMP  0x0000001F
+#define HOST_SDIO_NEG_SAMP_M  ((HOST_SDIO_NEG_SAMP_V)<<(HOST_SDIO_NEG_SAMP_S))
+#define HOST_SDIO_NEG_SAMP_V  0x1F
+#define HOST_SDIO_NEG_SAMP_S  5
+/* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: */
+#define HOST_SDIO20_MODE  0x0000001F
+#define HOST_SDIO20_MODE_M  ((HOST_SDIO20_MODE_V)<<(HOST_SDIO20_MODE_S))
+#define HOST_SDIO20_MODE_V  0x1F
+#define HOST_SDIO20_MODE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_HOST_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/host_struct.h b/components/soc/esp32s2beta/include/soc/host_struct.h
new file mode 100644
index 000000000..fd7844c38
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/host_struct.h
@@ -0,0 +1,602 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_HOST_STRUCT_H_
+#define _SOC_HOST_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t reserved_0;
+    uint32_t reserved_4;
+    uint32_t reserved_8;
+    uint32_t reserved_c;
+    uint32_t reserved_10;
+    uint32_t reserved_14;
+    uint32_t reserved_18;
+    uint32_t reserved_1c;
+    union {
+        struct {
+            uint32_t func1_mdstat:     1;
+            uint32_t reserved1:       31;
+        };
+        uint32_t val;
+    } func2_2;
+    uint32_t reserved_24;
+    uint32_t reserved_28;
+    uint32_t reserved_2c;
+    uint32_t reserved_30;
+    uint32_t gpio_status0;                             /**/
+    union {
+        struct {
+            uint32_t sdio_int1:     22;
+            uint32_t reserved22:    10;
+        };
+        uint32_t val;
+    } gpio_status1;
+    uint32_t gpio_in0;                                 /**/
+    union {
+        struct {
+            uint32_t sdio_in1:     22;
+            uint32_t reserved22:   10;
+        };
+        uint32_t val;
+    } gpio_in1;
+    union {
+        struct {
+            uint32_t token0:          12;
+            uint32_t rx_pf_valid:      1;
+            uint32_t reserved13:       3;
+            uint32_t reg_token1:      12;
+            uint32_t rx_pf_eof:        4;
+        };
+        uint32_t val;
+    } slc0_token_rdata;
+    uint32_t slc0_pf;                                     /**/
+    uint32_t reserved_4c;
+    union {
+        struct {
+            uint32_t tohost_bit0:                1;
+            uint32_t tohost_bit1:                1;
+            uint32_t tohost_bit2:                1;
+            uint32_t tohost_bit3:                1;
+            uint32_t tohost_bit4:                1;
+            uint32_t tohost_bit5:                1;
+            uint32_t tohost_bit6:                1;
+            uint32_t tohost_bit7:                1;
+            uint32_t token0_1to0:                1;
+            uint32_t token1_1to0:                1;
+            uint32_t token0_0to1:                1;
+            uint32_t token1_0to1:                1;
+            uint32_t rx_sof:                     1;
+            uint32_t rx_eof:                     1;
+            uint32_t rx_start:                   1;
+            uint32_t tx_start:                   1;
+            uint32_t rx_udf:                     1;
+            uint32_t tx_ovf:                     1;
+            uint32_t rx_pf_valid:                1;
+            uint32_t ext_bit0:                   1;
+            uint32_t ext_bit1:                   1;
+            uint32_t ext_bit2:                   1;
+            uint32_t ext_bit3:                   1;
+            uint32_t rx_new_packet:              1;
+            uint32_t rd_retry:                   1;
+            uint32_t gpio_sdio:                  1;
+            uint32_t reserved26:                 6;
+        };
+        uint32_t val;
+    } slc0_int_raw;
+    uint32_t reserved_54;
+    union {
+        struct {
+            uint32_t tohost_bit0:               1;
+            uint32_t tohost_bit1:               1;
+            uint32_t tohost_bit2:               1;
+            uint32_t tohost_bit3:               1;
+            uint32_t tohost_bit4:               1;
+            uint32_t tohost_bit5:               1;
+            uint32_t tohost_bit6:               1;
+            uint32_t tohost_bit7:               1;
+            uint32_t token0_1to0:               1;
+            uint32_t token1_1to0:               1;
+            uint32_t token0_0to1:               1;
+            uint32_t token1_0to1:               1;
+            uint32_t rx_sof:                    1;
+            uint32_t rx_eof:                    1;
+            uint32_t rx_start:                  1;
+            uint32_t tx_start:                  1;
+            uint32_t rx_udf:                    1;
+            uint32_t tx_ovf:                    1;
+            uint32_t rx_pf_valid:               1;
+            uint32_t ext_bit0:                  1;
+            uint32_t ext_bit1:                  1;
+            uint32_t ext_bit2:                  1;
+            uint32_t ext_bit3:                  1;
+            uint32_t rx_new_packet:             1;
+            uint32_t rd_retry:                  1;
+            uint32_t gpio_sdio:                 1;
+            uint32_t reserved26:                6;
+        };
+        uint32_t val;
+    } slc0_int_st;
+    uint32_t reserved_5c;
+    union {
+        struct {
+            uint32_t reg_slc0_len:      20;
+            uint32_t reg_slc0_len_check:12;
+        };
+        uint32_t val;
+    } pkt_len;
+    union {
+        struct {
+            uint32_t state0:         8;
+            uint32_t state1:         8;
+            uint32_t state2:         8;
+            uint32_t state3:         8;
+        };
+        uint32_t val;
+    } state_w0;
+    union {
+        struct {
+            uint32_t state4:         8;
+            uint32_t state5:         8;
+            uint32_t state6:         8;
+            uint32_t state7:         8;
+        };
+        uint32_t val;
+    } state_w1;
+    union {
+        struct {
+            uint32_t conf0:         8;
+            uint32_t conf1:         8;
+            uint32_t conf2:         8;
+            uint32_t conf3:         8;
+        };
+        uint32_t val;
+    } conf_w0;
+    union {
+        struct {
+            uint32_t conf4:         8;
+            uint32_t conf5:         8;
+            uint32_t conf6:         8;
+            uint32_t conf7:         8;
+        };
+        uint32_t val;
+    } conf_w1;
+    union {
+        struct {
+            uint32_t conf8:          8;
+            uint32_t conf9:          8;
+            uint32_t conf10:         8;
+            uint32_t conf11:         8;
+        };
+        uint32_t val;
+    } conf_w2;
+    union {
+        struct {
+            uint32_t conf12:         8;
+            uint32_t conf13:         8;
+            uint32_t conf14:         8;
+            uint32_t conf15:         8;
+        };
+        uint32_t val;
+    } conf_w3;
+    union {
+        struct {
+            uint32_t conf16:         8;                   /*SLC timeout value*/
+            uint32_t conf17:         8;                   /*SLC timeout enable*/
+            uint32_t conf18:         8;
+            uint32_t conf19:         8;                   /*Interrupt to target CPU*/
+        };
+        uint32_t val;
+    } conf_w4;
+    union {
+        struct {
+            uint32_t conf20:         8;
+            uint32_t conf21:         8;
+            uint32_t conf22:         8;
+            uint32_t conf23:         8;
+        };
+        uint32_t val;
+    } conf_w5;
+    union {
+        struct {
+            uint32_t win_cmd:        16;
+            uint32_t reserved16:     16;
+        };
+        uint32_t val;
+    } win_cmd;
+    union {
+        struct {
+            uint32_t conf24:         8;
+            uint32_t conf25:         8;
+            uint32_t conf26:         8;
+            uint32_t conf27:         8;
+        };
+        uint32_t val;
+    } conf_w6;
+    union {
+        struct {
+            uint32_t conf28:         8;
+            uint32_t conf29:         8;
+            uint32_t conf30:         8;
+            uint32_t conf31:         8;
+        };
+        uint32_t val;
+    } conf_w7;
+    union {
+        struct {
+            uint32_t reg_slc0_len0:      20;
+            uint32_t reg_slc0_len0_check:12;
+        };
+        uint32_t val;
+    } pkt_len0;
+    union {
+        struct {
+            uint32_t reg_slc0_len1:      20;
+            uint32_t reg_slc0_len1_check:12;
+        };
+        uint32_t val;
+    } pkt_len1;
+    union {
+        struct {
+            uint32_t reg_slc0_len2:      20;
+            uint32_t reg_slc0_len2_check:12;
+        };
+        uint32_t val;
+    } pkt_len2;
+    union {
+        struct {
+            uint32_t conf32:         8;
+            uint32_t conf33:         8;
+            uint32_t conf34:         8;
+            uint32_t conf35:         8;
+        };
+        uint32_t val;
+    } conf_w8;
+    union {
+        struct {
+            uint32_t conf36:         8;
+            uint32_t conf37:         8;
+            uint32_t conf38:         8;
+            uint32_t conf39:         8;
+        };
+        uint32_t val;
+    } conf_w9;
+    union {
+        struct {
+            uint32_t conf40:         8;
+            uint32_t conf41:         8;
+            uint32_t conf42:         8;
+            uint32_t conf43:         8;
+        };
+        uint32_t val;
+    } conf_w10;
+    union {
+        struct {
+            uint32_t conf44:         8;
+            uint32_t conf45:         8;
+            uint32_t conf46:         8;
+            uint32_t conf47:         8;
+        };
+        uint32_t val;
+    } conf_w11;
+    union {
+        struct {
+            uint32_t conf48:         8;
+            uint32_t conf49:         8;
+            uint32_t conf50:         8;
+            uint32_t conf51:         8;
+        };
+        uint32_t val;
+    } conf_w12;
+    union {
+        struct {
+            uint32_t conf52:         8;
+            uint32_t conf53:         8;
+            uint32_t conf54:         8;
+            uint32_t conf55:         8;
+        };
+        uint32_t val;
+    } conf_w13;
+    union {
+        struct {
+            uint32_t conf56:         8;
+            uint32_t conf57:         8;
+            uint32_t conf58:         8;
+            uint32_t conf59:         8;
+        };
+        uint32_t val;
+    } conf_w14;
+    union {
+        struct {
+            uint32_t conf60:         8;
+            uint32_t conf61:         8;
+            uint32_t conf62:         8;
+            uint32_t conf63:         8;
+        };
+        uint32_t val;
+    } conf_w15;
+    uint32_t check_sum0;                               /**/
+    uint32_t check_sum1;                               /**/
+    uint32_t reserved_c4;
+    union {
+        struct {
+            uint32_t token0_wd:         12;
+            uint32_t reserved12:         4;
+            uint32_t token1_wd:         12;
+            uint32_t reserved28:         4;
+        };
+        uint32_t val;
+    } slc0_token_wdata;
+    uint32_t reserved_cc;
+    union {
+        struct {
+            uint32_t slc0_token0_dec:     1;
+            uint32_t slc0_token1_dec:     1;
+            uint32_t slc0_token0_wr:      1;
+            uint32_t slc0_token1_wr:      1;
+            uint32_t reserved4:           4;
+            uint32_t slc0_len_wr:         1;
+            uint32_t reserved9:          23;
+        };
+        uint32_t val;
+    } token_con;
+    union {
+        struct {
+            uint32_t tohost_bit0:                1;
+            uint32_t tohost_bit1:                1;
+            uint32_t tohost_bit2:                1;
+            uint32_t tohost_bit3:                1;
+            uint32_t tohost_bit4:                1;
+            uint32_t tohost_bit5:                1;
+            uint32_t tohost_bit6:                1;
+            uint32_t tohost_bit7:                1;
+            uint32_t token0_1to0:                1;
+            uint32_t token1_1to0:                1;
+            uint32_t token0_0to1:                1;
+            uint32_t token1_0to1:                1;
+            uint32_t rx_sof:                     1;
+            uint32_t rx_eof:                     1;
+            uint32_t rx_start:                   1;
+            uint32_t tx_start:                   1;
+            uint32_t rx_udf:                     1;
+            uint32_t tx_ovf:                     1;
+            uint32_t rx_pf_valid:                1;
+            uint32_t ext_bit0:                   1;
+            uint32_t ext_bit1:                   1;
+            uint32_t ext_bit2:                   1;
+            uint32_t ext_bit3:                   1;
+            uint32_t rx_new_packet:              1;
+            uint32_t rd_retry:                   1;
+            uint32_t gpio_sdio:                  1;
+            uint32_t reserved26:                 6;
+        };
+        uint32_t val;
+    } slc0_int_clr;
+    uint32_t reserved_d8;
+    union {
+        struct {
+            uint32_t tohost_bit0:                    1;
+            uint32_t tohost_bit1:                    1;
+            uint32_t tohost_bit2:                    1;
+            uint32_t tohost_bit3:                    1;
+            uint32_t tohost_bit4:                    1;
+            uint32_t tohost_bit5:                    1;
+            uint32_t tohost_bit6:                    1;
+            uint32_t tohost_bit7:                    1;
+            uint32_t token0_1to0:                    1;
+            uint32_t token1_1to0:                    1;
+            uint32_t token0_0to1:                    1;
+            uint32_t token1_0to1:                    1;
+            uint32_t rx_sof:                         1;
+            uint32_t rx_eof:                         1;
+            uint32_t rx_start:                       1;
+            uint32_t tx_start:                       1;
+            uint32_t rx_udf:                         1;
+            uint32_t tx_ovf:                         1;
+            uint32_t rx_pf_valid:                    1;
+            uint32_t ext_bit0:                       1;
+            uint32_t ext_bit1:                       1;
+            uint32_t ext_bit2:                       1;
+            uint32_t ext_bit3:                       1;
+            uint32_t rx_new_packet:                  1;
+            uint32_t rd_retry:                       1;
+            uint32_t gpio_sdio:                      1;
+            uint32_t reserved26:                     6;
+        };
+        uint32_t val;
+    } slc0_func1_int_ena;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    union {
+        struct {
+            uint32_t tohost_bit0:                1;
+            uint32_t tohost_bit1:                1;
+            uint32_t tohost_bit2:                1;
+            uint32_t tohost_bit3:                1;
+            uint32_t tohost_bit4:                1;
+            uint32_t tohost_bit5:                1;
+            uint32_t tohost_bit6:                1;
+            uint32_t tohost_bit7:                1;
+            uint32_t token0_1to0:                1;
+            uint32_t token1_1to0:                1;
+            uint32_t token0_0to1:                1;
+            uint32_t token1_0to1:                1;
+            uint32_t rx_sof:                     1;
+            uint32_t rx_eof:                     1;
+            uint32_t rx_start:                   1;
+            uint32_t tx_start:                   1;
+            uint32_t rx_udf:                     1;
+            uint32_t tx_ovf:                     1;
+            uint32_t rx_pf_valid:                1;
+            uint32_t ext_bit0:                   1;
+            uint32_t ext_bit1:                   1;
+            uint32_t ext_bit2:                   1;
+            uint32_t ext_bit3:                   1;
+            uint32_t rx_new_packet:              1;
+            uint32_t rd_retry:                   1;
+            uint32_t gpio_sdio:                  1;
+            uint32_t reserved26:                 6;
+        };
+        uint32_t val;
+    } slc0_int_ena;
+    uint32_t reserved_f0;
+    union {
+        struct {
+            uint32_t infor:            20;
+            uint32_t reserved20:       12;
+        };
+        uint32_t val;
+    } slc0_rx_infor;
+    uint32_t reserved_f8;
+    uint32_t slc0_len_wd;                                  /**/
+    uint32_t apbwin_wdata;                            /**/
+    union {
+        struct {
+            uint32_t addr:            28;
+            uint32_t wr:               1;
+            uint32_t start:            1;
+            uint32_t bus:              1;
+            uint32_t reserved31:       1;
+        };
+        uint32_t val;
+    } apbwin_conf;
+    uint32_t apbwin_rdata;                            /**/
+    union {
+        struct {
+            uint32_t bit7_clraddr:              9;
+            uint32_t bit6_clraddr:              9;
+            uint32_t reserved18:               14;
+        };
+        uint32_t val;
+    } slc0_rdclr;
+    uint32_t reserved_110;
+    union {
+        struct {
+            uint32_t tohost_bit01:                1;
+            uint32_t tohost_bit11:                1;
+            uint32_t tohost_bit21:                1;
+            uint32_t tohost_bit31:                1;
+            uint32_t tohost_bit41:                1;
+            uint32_t tohost_bit51:                1;
+            uint32_t tohost_bit61:                1;
+            uint32_t tohost_bit71:                1;
+            uint32_t token0_1to01:                1;
+            uint32_t token1_1to01:                1;
+            uint32_t token0_0to11:                1;
+            uint32_t token1_0to11:                1;
+            uint32_t rx_sof1:                     1;
+            uint32_t rx_eof1:                     1;
+            uint32_t rx_start1:                   1;
+            uint32_t tx_start1:                   1;
+            uint32_t rx_udf1:                     1;
+            uint32_t tx_ovf1:                     1;
+            uint32_t rx_pf_valid1:                1;
+            uint32_t ext_bit01:                   1;
+            uint32_t ext_bit11:                   1;
+            uint32_t ext_bit21:                   1;
+            uint32_t ext_bit31:                   1;
+            uint32_t rx_new_packet1:              1;
+            uint32_t rd_retry1:                   1;
+            uint32_t gpio_sdio1:                  1;
+            uint32_t reserved26:                  6;
+        };
+        uint32_t val;
+    } slc0_int_ena1;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t date;                                 /**/
+    uint32_t id;                                   /**/
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    union {
+        struct {
+            uint32_t frc_sdio11:       5;
+            uint32_t frc_sdio20:       5;
+            uint32_t frc_neg_samp:     5;
+            uint32_t frc_pos_samp:     5;
+            uint32_t frc_quick_in:     5;
+            uint32_t sdio20_int_delay: 1;
+            uint32_t sdio_pad_pullup:  1;
+            uint32_t hspeed_con_en:    1;
+            uint32_t reserved28:       4;
+        };
+        uint32_t val;
+    } conf;
+    union {
+        struct {
+            uint32_t sdio20_mode:   5;
+            uint32_t sdio_neg_samp: 5;
+            uint32_t sdio_quick_in: 5;
+            uint32_t reserved15:   17;
+        };
+        uint32_t val;
+    } inf_st;
+} host_dev_t;
+extern host_dev_t HOST;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_HOST_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/hwcrypto_reg.h b/components/soc/esp32s2beta/include/soc/hwcrypto_reg.h
new file mode 100644
index 000000000..cccd2fbee
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/hwcrypto_reg.h
@@ -0,0 +1,107 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef __HWCRYPTO_REG_H__
+#define __HWCRYPTO_REG_H__
+
+#include "soc.h"
+
+/* registers for RSA acceleration via Multiple Precision Integer ops */
+#define RSA_MEM_M_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x000)
+/* RB & Z use the same memory block, depending on phase of operation */
+#define RSA_MEM_RB_BLOCK_BASE         ((DR_REG_RSA_BASE)+0x200)
+#define RSA_MEM_Z_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x200)
+#define RSA_MEM_Y_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x400)
+#define RSA_MEM_X_BLOCK_BASE          ((DR_REG_RSA_BASE)+0x600)
+
+/* Configuration registers */
+#define RSA_M_DASH_REG                (DR_REG_RSA_BASE + 0x800)
+#define RSA_LENGTH_REG                (DR_REG_RSA_BASE + 0x804)
+#define RSA_CONSTANT_TIME_REG         (DR_REG_RSA_BASE + 0x820)
+#define RSA_SEARCH_OPEN_REG           (DR_REG_RSA_BASE + 0x824)
+#define RSA_SEARCH_POS_REG            (DR_REG_RSA_BASE + 0x828)
+
+/* Initialization registers */
+#define RSA_QUERY_CLEAN_REG           (DR_REG_RSA_BASE + 0x808)
+
+/* Calculation start registers */
+#define RSA_MODEXP_START_REG          (DR_REG_RSA_BASE + 0x80c)
+#define RSA_MOD_MULT_START_REG        (DR_REG_RSA_BASE + 0x810)
+#define RSA_MULT_START_REG            (DR_REG_RSA_BASE + 0x814)
+
+/* Interrupt registers */
+#define RSA_QUERY_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x818)
+#define RSA_CLEAR_INTERRUPT_REG       (DR_REG_RSA_BASE + 0x81C)
+
+/* SHA acceleration registers */
+#define SHA_MODE_REG                  ((DR_REG_SHA_BASE) + 0x00)
+
+#define SHA_MODE_SHA1 0
+#define SHA_MODE_SHA224 1
+#define SHA_MODE_SHA256 2
+#define SHA_MODE_SHA384 3
+#define SHA_MODE_SHA512 4
+#define SHA_MODE_SHA512_224 5
+#define SHA_MODE_SHA512_256 6
+#define SHA_MODE_SHA512_T 7
+
+#define SHA_T_STRING_REG              ((DR_REG_SHA_BASE) + 0x04)
+#define SHA_T_LENGTH_REG              ((DR_REG_SHA_BASE) + 0x08)
+#define SHA_START_REG                 ((DR_REG_SHA_BASE) + 0x0c)
+#define SHA_CONTINUE_REG              ((DR_REG_SHA_BASE) + 0x10)
+#define SHA_BUSY_REG                  ((DR_REG_SHA_BASE) + 0x14)
+
+#define SHA_H_BASE                    ((DR_REG_SHA_BASE) + 0x40)
+#define SHA_M_BASE                    ((DR_REG_SHA_BASE) + 0x80)
+
+/* AES acceleration registers */
+#define AES_MODE_REG            ((DR_REG_AES_BASE) + 0x40)
+#define AES_ENDIAN_REG          ((DR_REG_AES_BASE) + 0x44)
+#define AES_TRIGGER_REG         ((DR_REG_AES_BASE) + 0x48)
+#define AES_STATE_REG           ((DR_REG_AES_BASE) + 0x4c)
+
+#define AES_KEY_BASE            ((DR_REG_AES_BASE) + 0x00)
+#define AES_TEXT_IN_BASE        ((DR_REG_AES_BASE) + 0x20)
+#define AES_TEXT_OUT_BASE       ((DR_REG_AES_BASE) + 0x30)
+
+/* HMAC Module */
+#define HMAC_SET_START_REG             ((DR_REG_HMAC_BASE) + 0x40)
+#define HMAC_SET_PARA_PURPOSE_REG      ((DR_REG_HMAC_BASE) + 0x44)
+#define HMAC_SET_PARA_KEY_REG          ((DR_REG_HMAC_BASE) + 0x48)
+#define HMAC_SET_PARA_FINISH_REG       ((DR_REG_HMAC_BASE) + 0x4c)
+#define HMAC_SET_MESSAGE_ONE_REG       ((DR_REG_HMAC_BASE) + 0x50)
+#define HMAC_SET_MESSAGE_ING_REG       ((DR_REG_HMAC_BASE) + 0x54)
+#define HMAC_SET_MESSAGE_END_REG       ((DR_REG_HMAC_BASE) + 0x58)
+#define HMAC_SET_RESULT_FINISH_REG     ((DR_REG_HMAC_BASE) + 0x5c)
+#define HMAC_SET_INVALIDATE_JTAG_REG   ((DR_REG_HMAC_BASE) + 0x60)
+#define HMAC_SET_INVALIDATE_DS_REG     ((DR_REG_HMAC_BASE) + 0x64)
+#define HMAC_QUERY_ERROR_REG           ((DR_REG_HMAC_BASE) + 0x68)
+#define HMAC_QUERY_BUSY_REG            ((DR_REG_HMAC_BASE) + 0x6c)
+
+
+#define HMAC_WDATA_BASE                ((DR_REG_HMAC_BASE) + 0x80)
+#define HMAC_RDATA_BASE                ((DR_REG_HMAC_BASE) + 0xC0)
+#define HMAC_SET_MESSAGE_PAD_REG       ((DR_REG_HMAC_BASE) + 0xF0)
+
+/* AES-XTS registers */
+#define AES_XTS_PLAIN_BASE        ((DR_REG_AES_BASE) + 0x80)
+#define AES_XTS_SIZE_REG          ((DR_REG_AES_BASE) + 0xC0)
+#define AES_XTS_DESTINATION_REG   ((DR_REG_AES_BASE) + 0xC4)
+#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0xC8)
+
+#define AES_XTS_TRIGGER_REG       ((DR_REG_AES_BASE) + 0xCC)
+#define AES_XTS_RELEASE_REG       ((DR_REG_AES_BASE) + 0xD0)
+#define AES_XTS_DESTROY_REG       ((DR_REG_AES_BASE) + 0xD4)
+#define AES_XTS_STATE_REG         ((DR_REG_AES_BASE) + 0xD8)
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/i2c_reg.h b/components/soc/esp32s2beta/include/soc/i2c_reg.h
new file mode 100644
index 000000000..721fd2434
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/i2c_reg.h
@@ -0,0 +1,1122 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2C_REG_H_
+#define _SOC_I2C_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define I2C_SCL_LOW_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0000)
+/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This register is used to configure the  low level width of SCL clock.*/
+#define I2C_SCL_LOW_PERIOD  0x00003FFF
+#define I2C_SCL_LOW_PERIOD_M  ((I2C_SCL_LOW_PERIOD_V)<<(I2C_SCL_LOW_PERIOD_S))
+#define I2C_SCL_LOW_PERIOD_V  0x3FFF
+#define I2C_SCL_LOW_PERIOD_S  0
+
+#define I2C_CTR_REG(i)          (REG_I2C_BASE(i) + 0x0004)
+/* I2C_REF_ALWAYS_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define I2C_REF_ALWAYS_ON  (BIT(11))
+#define I2C_REF_ALWAYS_ON_M  (BIT(11))
+#define I2C_REF_ALWAYS_ON_V  0x1
+#define I2C_REF_ALWAYS_ON_S  11
+/* I2C_FSM_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2C_FSM_RST  (BIT(10))
+#define I2C_FSM_RST_M  (BIT(10))
+#define I2C_FSM_RST_V  0x1
+#define I2C_FSM_RST_S  10
+/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define I2C_ARBITRATION_EN  (BIT(9))
+#define I2C_ARBITRATION_EN_M  (BIT(9))
+#define I2C_ARBITRATION_EN_V  0x1
+#define I2C_ARBITRATION_EN_S  9
+/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: This is the clock gating control bit for reading or writing registers.*/
+#define I2C_CLK_EN  (BIT(8))
+#define I2C_CLK_EN_M  (BIT(8))
+#define I2C_CLK_EN_V  0x1
+#define I2C_CLK_EN_S  8
+/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: This bit is used to control the storage mode for received datas.
+ 1: receive data from most significant bit    0: receive data from least significant bit*/
+#define I2C_RX_LSB_FIRST  (BIT(7))
+#define I2C_RX_LSB_FIRST_M  (BIT(7))
+#define I2C_RX_LSB_FIRST_V  0x1
+#define I2C_RX_LSB_FIRST_S  7
+/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This bit is used to control the sending mode for  data need to
+ be send. 1: receive data from most significant bit    0: receive data from least significant bit*/
+#define I2C_TX_LSB_FIRST  (BIT(6))
+#define I2C_TX_LSB_FIRST_M  (BIT(6))
+#define I2C_TX_LSB_FIRST_V  0x1
+#define I2C_TX_LSB_FIRST_S  6
+/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to start sending data in txfifo.*/
+#define I2C_TRANS_START  (BIT(5))
+#define I2C_TRANS_START_M  (BIT(5))
+#define I2C_TRANS_START_V  0x1
+#define I2C_TRANS_START_S  5
+/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to configure the module as i2c master  clear this
+ bit to configure the module as i2c slave.*/
+#define I2C_MS_MODE  (BIT(4))
+#define I2C_MS_MODE_M  (BIT(4))
+#define I2C_MS_MODE_V  0x1
+#define I2C_MS_MODE_S  4
+/* I2C_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define I2C_ACK_LEVEL  (BIT(3))
+#define I2C_ACK_LEVEL_M  (BIT(3))
+#define I2C_ACK_LEVEL_V  0x1
+#define I2C_ACK_LEVEL_S  3
+/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to sample data in SCL low level. clear this bit
+ to sample data in SCL high level.*/
+#define I2C_SAMPLE_SCL_LEVEL  (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_M  (BIT(2))
+#define I2C_SAMPLE_SCL_LEVEL_V  0x1
+#define I2C_SAMPLE_SCL_LEVEL_S  2
+/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: 1: normally ouput scl clock  0: exchange the function of scl_o
+ and scl_oe (scl_o is the original internal output scl signal  scl_oe is the enable bit for the internal output scl signal)*/
+#define I2C_SCL_FORCE_OUT  (BIT(1))
+#define I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define I2C_SCL_FORCE_OUT_V  0x1
+#define I2C_SCL_FORCE_OUT_S  1
+/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: normally ouput sda data   0: exchange the function of sda_o
+ and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
+#define I2C_SDA_FORCE_OUT  (BIT(0))
+#define I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define I2C_SDA_FORCE_OUT_V  0x1
+#define I2C_SDA_FORCE_OUT_S  0
+
+#define I2C_SR_REG(i)          (REG_I2C_BASE(i) + 0x0008)
+/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: This register stores the value of state machine to produce SCL.
+ 3'h0: SCL_IDLE  3'h1:SCL_START   3'h2:SCL_LOW_EDGE  3'h3: SCL_LOW   3'h4:SCL_HIGH_EDGE   3'h5:SCL_HIGH  3'h6:SCL_STOP*/
+#define I2C_SCL_STATE_LAST  0x00000007
+#define I2C_SCL_STATE_LAST_M  ((I2C_SCL_STATE_LAST_V)<<(I2C_SCL_STATE_LAST_S))
+#define I2C_SCL_STATE_LAST_V  0x7
+#define I2C_SCL_STATE_LAST_S  28
+/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: This register stores the value of state machine for i2c module.
+  3'h0: SCL_MAIN_IDLE  3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS  3'h3: SCL_RX_DATA  3'h4 SCL_TX_DATA  3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
+#define I2C_SCL_MAIN_STATE_LAST  0x00000007
+#define I2C_SCL_MAIN_STATE_LAST_M  ((I2C_SCL_MAIN_STATE_LAST_V)<<(I2C_SCL_MAIN_STATE_LAST_S))
+#define I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define I2C_SCL_MAIN_STATE_LAST_S  24
+/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */
+/*description: This register stores the amount of received data  in ram.*/
+#define I2C_TXFIFO_CNT  0x0000003F
+#define I2C_TXFIFO_CNT_M  ((I2C_TXFIFO_CNT_V)<<(I2C_TXFIFO_CNT_S))
+#define I2C_TXFIFO_CNT_V  0x3F
+#define I2C_TXFIFO_CNT_S  18
+/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */
+/*description: This register represent the amount of data need to send.*/
+#define I2C_RXFIFO_CNT  0x0000003F
+#define I2C_RXFIFO_CNT_M  ((I2C_RXFIFO_CNT_V)<<(I2C_RXFIFO_CNT_S))
+#define I2C_RXFIFO_CNT_V  0x3F
+#define I2C_RXFIFO_CNT_S  8
+/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This register changes to high level when one byte is transferred.*/
+#define I2C_BYTE_TRANS  (BIT(6))
+#define I2C_BYTE_TRANS_M  (BIT(6))
+#define I2C_BYTE_TRANS_V  0x1
+#define I2C_BYTE_TRANS_S  6
+/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: when configured as i2c slave  and the address send by master
+ is equal to slave's address  then this bit will be high level.*/
+#define I2C_SLAVE_ADDRESSED  (BIT(5))
+#define I2C_SLAVE_ADDRESSED_M  (BIT(5))
+#define I2C_SLAVE_ADDRESSED_V  0x1
+#define I2C_SLAVE_ADDRESSED_S  5
+/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: 1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
+#define I2C_BUS_BUSY  (BIT(4))
+#define I2C_BUS_BUSY_M  (BIT(4))
+#define I2C_BUS_BUSY_V  0x1
+#define I2C_BUS_BUSY_S  4
+/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: when I2C lost control of SDA line  this register changes to high level.*/
+#define I2C_ARB_LOST  (BIT(3))
+#define I2C_ARB_LOST_M  (BIT(3))
+#define I2C_ARB_LOST_V  0x1
+#define I2C_ARB_LOST_S  3
+/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: when I2C takes more than time_out_reg clocks to receive a data
+ then this register changes to high level.*/
+#define I2C_TIME_OUT  (BIT(2))
+#define I2C_TIME_OUT_M  (BIT(2))
+#define I2C_TIME_OUT_V  0x1
+#define I2C_TIME_OUT_S  2
+/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: when in slave mode  1: master read slave  0: master write slave.*/
+#define I2C_SLAVE_RW  (BIT(1))
+#define I2C_SLAVE_RW_M  (BIT(1))
+#define I2C_SLAVE_RW_V  0x1
+#define I2C_SLAVE_RW_S  1
+/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This register stores the value of ACK bit.*/
+#define I2C_ACK_REC  (BIT(0))
+#define I2C_ACK_REC_M  (BIT(0))
+#define I2C_ACK_REC_V  0x1
+#define I2C_ACK_REC_S  0
+
+#define I2C_TO_REG(i)          (REG_I2C_BASE(i) + 0x000c)
+/* I2C_TIME_OUT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define I2C_TIME_OUT_EN  (BIT(24))
+#define I2C_TIME_OUT_EN_M  (BIT(24))
+#define I2C_TIME_OUT_EN_V  0x1
+#define I2C_TIME_OUT_EN_S  24
+/* I2C_TIME_OUT_REG : R/W ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: */
+#define I2C_TIME_OUT_REG  0x00FFFFFF
+#define I2C_TIME_OUT_REG_M  ((I2C_TIME_OUT_REG_V)<<(I2C_TIME_OUT_REG_S))
+#define I2C_TIME_OUT_REG_V  0xFFFFFF
+#define I2C_TIME_OUT_REG_S  0
+
+#define I2C_SLAVE_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x0010)
+/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: This register is used to enable slave 10bit address mode.*/
+#define I2C_ADDR_10BIT_EN  (BIT(31))
+#define I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define I2C_ADDR_10BIT_EN_V  0x1
+#define I2C_ADDR_10BIT_EN_S  31
+/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: when configured as i2c slave  this register is used to configure
+ slave's address.*/
+#define I2C_SLAVE_ADDR  0x00007FFF
+#define I2C_SLAVE_ADDR_M  ((I2C_SLAVE_ADDR_V)<<(I2C_SLAVE_ADDR_S))
+#define I2C_SLAVE_ADDR_V  0x7FFF
+#define I2C_SLAVE_ADDR_S  0
+
+#define I2C_RXFIFO_ST_REG(i)          (REG_I2C_BASE(i) + 0x0014)
+/* I2C_RXFIFO_INIT_WADDR : RO ;bitpos:[31:27] ;default: 5'b0 ; */
+/*description: */
+#define I2C_RXFIFO_INIT_WADDR  0x0000001F
+#define I2C_RXFIFO_INIT_WADDR_M  ((I2C_RXFIFO_INIT_WADDR_V)<<(I2C_RXFIFO_INIT_WADDR_S))
+#define I2C_RXFIFO_INIT_WADDR_V  0x1F
+#define I2C_RXFIFO_INIT_WADDR_S  27
+/* I2C_TXFIFO_INIT_RADDR : RO ;bitpos:[26:22] ;default: 5'b0 ; */
+/*description: */
+#define I2C_TXFIFO_INIT_RADDR  0x0000001F
+#define I2C_TXFIFO_INIT_RADDR_M  ((I2C_TXFIFO_INIT_RADDR_V)<<(I2C_TXFIFO_INIT_RADDR_S))
+#define I2C_TXFIFO_INIT_RADDR_V  0x1F
+#define I2C_TXFIFO_INIT_RADDR_S  22
+/* I2C_TX_UPDATE : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define I2C_TX_UPDATE  (BIT(21))
+#define I2C_TX_UPDATE_M  (BIT(21))
+#define I2C_TX_UPDATE_V  0x1
+#define I2C_TX_UPDATE_S  21
+/* I2C_RX_UPDATE : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define I2C_RX_UPDATE  (BIT(20))
+#define I2C_RX_UPDATE_M  (BIT(20))
+#define I2C_RX_UPDATE_V  0x1
+#define I2C_RX_UPDATE_S  20
+/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */
+/*description: This is the offset address of the last  sending data as described
+ in nonfifo_tx_thres register.*/
+#define I2C_TXFIFO_END_ADDR  0x0000001F
+#define I2C_TXFIFO_END_ADDR_M  ((I2C_TXFIFO_END_ADDR_V)<<(I2C_TXFIFO_END_ADDR_S))
+#define I2C_TXFIFO_END_ADDR_V  0x1F
+#define I2C_TXFIFO_END_ADDR_S  15
+/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */
+/*description: This is the offset address of the first  sending data as described
+ in nonfifo_tx_thres register.*/
+#define I2C_TXFIFO_START_ADDR  0x0000001F
+#define I2C_TXFIFO_START_ADDR_M  ((I2C_TXFIFO_START_ADDR_V)<<(I2C_TXFIFO_START_ADDR_S))
+#define I2C_TXFIFO_START_ADDR_V  0x1F
+#define I2C_TXFIFO_START_ADDR_S  10
+/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */
+/*description: This is the offset address of the first receiving data as described
+ in nonfifo_rx_thres_register.*/
+#define I2C_RXFIFO_END_ADDR  0x0000001F
+#define I2C_RXFIFO_END_ADDR_M  ((I2C_RXFIFO_END_ADDR_V)<<(I2C_RXFIFO_END_ADDR_S))
+#define I2C_RXFIFO_END_ADDR_V  0x1F
+#define I2C_RXFIFO_END_ADDR_S  5
+/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */
+/*description: This is the offset address of the last receiving data as described
+ in nonfifo_rx_thres_register.*/
+#define I2C_RXFIFO_START_ADDR  0x0000001F
+#define I2C_RXFIFO_START_ADDR_M  ((I2C_RXFIFO_START_ADDR_V)<<(I2C_RXFIFO_START_ADDR_S))
+#define I2C_RXFIFO_START_ADDR_V  0x1F
+#define I2C_RXFIFO_START_ADDR_S  0
+
+#define I2C_FIFO_CONF_REG(i)          (REG_I2C_BASE(i) + 0x0018)
+/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */
+/*description: when I2C sends more than nonfifo_tx_thres data  it will produce
+ tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
+#define I2C_NONFIFO_TX_THRES  0x0000003F
+#define I2C_NONFIFO_TX_THRES_M  ((I2C_NONFIFO_TX_THRES_V)<<(I2C_NONFIFO_TX_THRES_S))
+#define I2C_NONFIFO_TX_THRES_V  0x3F
+#define I2C_NONFIFO_TX_THRES_S  20
+/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */
+/*description: when I2C receives more than nonfifo_rx_thres data  it will produce
+ rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
+#define I2C_NONFIFO_RX_THRES  0x0000003F
+#define I2C_NONFIFO_RX_THRES_M  ((I2C_NONFIFO_RX_THRES_V)<<(I2C_NONFIFO_RX_THRES_S))
+#define I2C_NONFIFO_RX_THRES_V  0x3F
+#define I2C_NONFIFO_RX_THRES_S  14
+/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to reset tx fifo when using apb fifo access.*/
+#define I2C_TX_FIFO_RST  (BIT(13))
+#define I2C_TX_FIFO_RST_M  (BIT(13))
+#define I2C_TX_FIFO_RST_V  0x1
+#define I2C_TX_FIFO_RST_S  13
+/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to reset rx fifo when using apb fifo access.*/
+#define I2C_RX_FIFO_RST  (BIT(12))
+#define I2C_RX_FIFO_RST_M  (BIT(12))
+#define I2C_RX_FIFO_RST_V  0x1
+#define I2C_RX_FIFO_RST_S  12
+/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: When this bit is set to 1 then the byte after address represent
+ the offset address of I2C Slave's ram.*/
+#define I2C_FIFO_ADDR_CFG_EN  (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_M  (BIT(11))
+#define I2C_FIFO_ADDR_CFG_EN_V  0x1
+#define I2C_FIFO_ADDR_CFG_EN_S  11
+/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to enble apb nonfifo access.*/
+#define I2C_NONFIFO_EN  (BIT(10))
+#define I2C_NONFIFO_EN_M  (BIT(10))
+#define I2C_NONFIFO_EN_V  0x1
+#define I2C_NONFIFO_EN_S  10
+/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */
+/*description: Config txfifo empty threhd value when using apb fifo access*/
+#define I2C_TXFIFO_EMPTY_THRHD  0x0000001F
+#define I2C_TXFIFO_EMPTY_THRHD_M  ((I2C_TXFIFO_EMPTY_THRHD_V)<<(I2C_TXFIFO_EMPTY_THRHD_S))
+#define I2C_TXFIFO_EMPTY_THRHD_V  0x1F
+#define I2C_TXFIFO_EMPTY_THRHD_S  5
+/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */
+/*description: */
+#define I2C_RXFIFO_FULL_THRHD  0x0000001F
+#define I2C_RXFIFO_FULL_THRHD_M  ((I2C_RXFIFO_FULL_THRHD_V)<<(I2C_RXFIFO_FULL_THRHD_S))
+#define I2C_RXFIFO_FULL_THRHD_V  0x1F
+#define I2C_RXFIFO_FULL_THRHD_S  0
+
+#define I2C_DATA_APB_REG(i)      (0x60013000 + (i) * 0x14000 + 0x001c)
+
+#define I2C_DATA_REG(i)          (REG_I2C_BASE(i) + 0x001c)
+/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: The register represent the byte  data read from rxfifo when use apb fifo access*/
+#define I2C_FIFO_RDATA  0x000000FF
+#define I2C_FIFO_RDATA_M  ((I2C_FIFO_RDATA_V)<<(I2C_FIFO_RDATA_S))
+#define I2C_FIFO_RDATA_V  0xFF
+#define I2C_FIFO_RDATA_S  0
+
+#define I2C_INT_RAW_REG(i)          (REG_I2C_BASE(i) + 0x0020)
+/* I2C_DET_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2C_DET_START_INT_RAW  (BIT(15))
+#define I2C_DET_START_INT_RAW_M  (BIT(15))
+#define I2C_DET_START_INT_RAW_V  0x1
+#define I2C_DET_START_INT_RAW_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_RAW  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_RAW_S  14
+/* I2C_SCL_ST_TO_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_ST_TO_INT_RAW  (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_RAW_V  0x1
+#define I2C_SCL_ST_TO_INT_RAW_S  13
+/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for tx_send_empty_int interrupt.when
+ I2C sends more data than nonfifo_tx_thres  it will produce tx_send_empty_int interrupt..*/
+#define I2C_TX_SEND_EMPTY_INT_RAW  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_RAW_M  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_RAW_V  0x1
+#define I2C_TX_SEND_EMPTY_INT_RAW_S  12
+/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for rx_rec_full_int interrupt. when
+ I2C receives more data  than nonfifo_rx_thres  it will produce rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_RAW  (BIT(11))
+#define I2C_RX_REC_FULL_INT_RAW_M  (BIT(11))
+#define I2C_RX_REC_FULL_INT_RAW_V  0x1
+#define I2C_RX_REC_FULL_INT_RAW_S  11
+/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for ack_err_int interrupt. when
+ I2C receives a wrong ACK bit  it will produce ack_err_int interrupt..*/
+#define I2C_ACK_ERR_INT_RAW  (BIT(10))
+#define I2C_ACK_ERR_INT_RAW_M  (BIT(10))
+#define I2C_ACK_ERR_INT_RAW_V  0x1
+#define I2C_ACK_ERR_INT_RAW_S  10
+/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for trans_start_int interrupt. when
+ I2C sends the START bit it will produce trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_RAW  (BIT(9))
+#define I2C_TRANS_START_INT_RAW_M  (BIT(9))
+#define I2C_TRANS_START_INT_RAW_V  0x1
+#define I2C_TRANS_START_INT_RAW_S  9
+/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for time_out_int interrupt. when
+ I2C takes a lot of time to receive a data  it will produce  time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_RAW  (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_M  (BIT(8))
+#define I2C_TIME_OUT_INT_RAW_V  0x1
+#define I2C_TIME_OUT_INT_RAW_S  8
+/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for trans_complete_int interrupt.
+ when I2C Master finished STOP command  it will produce trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_RAW  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define I2C_TRANS_COMPLETE_INT_RAW_S  7
+/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for master_tra_comp_int interrupt.
+ when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_RAW  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_RAW_M  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_RAW_V  0x1
+#define I2C_MASTER_TRAN_COMP_INT_RAW_S  6
+/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for arbitration_lost_int interrupt.when
+ I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_RAW  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define I2C_ARBITRATION_LOST_INT_RAW_S  5
+/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for slave_tran_comp_int interrupt.
+ when I2C Slave detectsthe STOP bit  it will produce slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_RAW  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_M  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x1
+#define I2C_SLAVE_TRAN_COMP_INT_RAW_S  4
+/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for end_detect_int interrupt. when
+ I2C deals with  the END command  it will produce end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_RAW  (BIT(3))
+#define I2C_END_DETECT_INT_RAW_M  (BIT(3))
+#define I2C_END_DETECT_INT_RAW_V  0x1
+#define I2C_END_DETECT_INT_RAW_S  3
+/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for receiving data overflow when
+ use apb fifo access.*/
+#define I2C_RXFIFO_OVF_INT_RAW  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_RAW_V  0x1
+#define I2C_RXFIFO_OVF_INT_RAW_S  2
+/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for txfifo empty when use apb fifo access.*/
+#define I2C_TXFIFO_EMPTY_INT_RAW  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_RAW_V  0x1
+#define I2C_TXFIFO_EMPTY_INT_RAW_S  1
+/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit for rxfifo full when use apb fifo access.*/
+#define I2C_RXFIFO_FULL_INT_RAW  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_RAW_M  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_RAW_V  0x1
+#define I2C_RXFIFO_FULL_INT_RAW_S  0
+
+#define I2C_INT_CLR_REG(i)          (REG_I2C_BASE(i) + 0x0024)
+/* I2C_DET_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2C_DET_START_INT_CLR  (BIT(15))
+#define I2C_DET_START_INT_CLR_M  (BIT(15))
+#define I2C_DET_START_INT_CLR_V  0x1
+#define I2C_DET_START_INT_CLR_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_CLR  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_CLR_S  14
+/* I2C_SCL_ST_TO_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_ST_TO_INT_CLR  (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_CLR_V  0x1
+#define I2C_SCL_ST_TO_INT_CLR_S  13
+/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the tx_send_empty_int interrupt.*/
+#define I2C_TX_SEND_EMPTY_INT_CLR  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_CLR_M  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_CLR_V  0x1
+#define I2C_TX_SEND_EMPTY_INT_CLR_S  12
+/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_CLR  (BIT(11))
+#define I2C_RX_REC_FULL_INT_CLR_M  (BIT(11))
+#define I2C_RX_REC_FULL_INT_CLR_V  0x1
+#define I2C_RX_REC_FULL_INT_CLR_S  11
+/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the ack_err_int interrupt.*/
+#define I2C_ACK_ERR_INT_CLR  (BIT(10))
+#define I2C_ACK_ERR_INT_CLR_M  (BIT(10))
+#define I2C_ACK_ERR_INT_CLR_V  0x1
+#define I2C_ACK_ERR_INT_CLR_S  10
+/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_CLR  (BIT(9))
+#define I2C_TRANS_START_INT_CLR_M  (BIT(9))
+#define I2C_TRANS_START_INT_CLR_V  0x1
+#define I2C_TRANS_START_INT_CLR_S  9
+/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_CLR  (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_M  (BIT(8))
+#define I2C_TIME_OUT_INT_CLR_V  0x1
+#define I2C_TIME_OUT_INT_CLR_S  8
+/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_CLR  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define I2C_TRANS_COMPLETE_INT_CLR_S  7
+/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the master_tran_comp interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_CLR  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_CLR_M  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_CLR_V  0x1
+#define I2C_MASTER_TRAN_COMP_INT_CLR_S  6
+/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_CLR  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define I2C_ARBITRATION_LOST_INT_CLR_S  5
+/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_CLR  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_M  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x1
+#define I2C_SLAVE_TRAN_COMP_INT_CLR_S  4
+/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_CLR  (BIT(3))
+#define I2C_END_DETECT_INT_CLR_M  (BIT(3))
+#define I2C_END_DETECT_INT_CLR_V  0x1
+#define I2C_END_DETECT_INT_CLR_S  3
+/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_ovf_int interrupt.*/
+#define I2C_RXFIFO_OVF_INT_CLR  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_CLR_V  0x1
+#define I2C_RXFIFO_OVF_INT_CLR_S  2
+/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the txfifo_empty_int interrupt.*/
+#define I2C_TXFIFO_EMPTY_INT_CLR  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_CLR_V  0x1
+#define I2C_TXFIFO_EMPTY_INT_CLR_S  1
+/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rxfifo_full_int interrupt.*/
+#define I2C_RXFIFO_FULL_INT_CLR  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_CLR_M  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_CLR_V  0x1
+#define I2C_RXFIFO_FULL_INT_CLR_S  0
+
+#define I2C_INT_ENA_REG(i)          (REG_I2C_BASE(i) + 0x0028)
+/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2C_DET_START_INT_ENA  (BIT(15))
+#define I2C_DET_START_INT_ENA_M  (BIT(15))
+#define I2C_DET_START_INT_ENA_V  0x1
+#define I2C_DET_START_INT_ENA_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_ENA  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ENA_S  14
+/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_ST_TO_INT_ENA  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ENA_V  0x1
+#define I2C_SCL_ST_TO_INT_ENA_S  13
+/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The enable bit for tx_send_empty_int interrupt.*/
+#define I2C_TX_SEND_EMPTY_INT_ENA  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ENA_M  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ENA_V  0x1
+#define I2C_TX_SEND_EMPTY_INT_ENA_S  12
+/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The enable bit for rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_ENA  (BIT(11))
+#define I2C_RX_REC_FULL_INT_ENA_M  (BIT(11))
+#define I2C_RX_REC_FULL_INT_ENA_V  0x1
+#define I2C_RX_REC_FULL_INT_ENA_S  11
+/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The enable bit for ack_err_int interrupt.*/
+#define I2C_ACK_ERR_INT_ENA  (BIT(10))
+#define I2C_ACK_ERR_INT_ENA_M  (BIT(10))
+#define I2C_ACK_ERR_INT_ENA_V  0x1
+#define I2C_ACK_ERR_INT_ENA_S  10
+/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The enable bit for trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_ENA  (BIT(9))
+#define I2C_TRANS_START_INT_ENA_M  (BIT(9))
+#define I2C_TRANS_START_INT_ENA_V  0x1
+#define I2C_TRANS_START_INT_ENA_S  9
+/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_ENA  (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ENA_V  0x1
+#define I2C_TIME_OUT_INT_ENA_S  8
+/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_ENA  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ENA_S  7
+/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for master_tran_comp_int interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_ENA  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ENA_M  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ENA_V  0x1
+#define I2C_MASTER_TRAN_COMP_INT_ENA_S  6
+/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_ENA  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ENA_S  5
+/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_ENA  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_M  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x1
+#define I2C_SLAVE_TRAN_COMP_INT_ENA_S  4
+/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_ENA  (BIT(3))
+#define I2C_END_DETECT_INT_ENA_M  (BIT(3))
+#define I2C_END_DETECT_INT_ENA_V  0x1
+#define I2C_END_DETECT_INT_ENA_S  3
+/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for rxfifo_ovf_int interrupt.*/
+#define I2C_RXFIFO_OVF_INT_ENA  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ENA_V  0x1
+#define I2C_RXFIFO_OVF_INT_ENA_S  2
+/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for txfifo_empty_int interrupt.*/
+#define I2C_TXFIFO_EMPTY_INT_ENA  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ENA_V  0x1
+#define I2C_TXFIFO_EMPTY_INT_ENA_S  1
+/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for rxfifo_full_int interrupt.*/
+#define I2C_RXFIFO_FULL_INT_ENA  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ENA_M  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ENA_V  0x1
+#define I2C_RXFIFO_FULL_INT_ENA_S  0
+
+#define I2C_INT_STATUS_REG(i)          (REG_I2C_BASE(i) + 0x002c)
+/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define I2C_DET_START_INT_ST  (BIT(15))
+#define I2C_DET_START_INT_ST_M  (BIT(15))
+#define I2C_DET_START_INT_ST_V  0x1
+#define I2C_DET_START_INT_ST_S  15
+/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_MAIN_ST_TO_INT_ST  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_M  (BIT(14))
+#define I2C_SCL_MAIN_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_MAIN_ST_TO_INT_ST_S  14
+/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_ST_TO_INT_ST  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_M  (BIT(13))
+#define I2C_SCL_ST_TO_INT_ST_V  0x1
+#define I2C_SCL_ST_TO_INT_ST_S  13
+/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The masked interrupt status for tx_send_empty_int interrupt.*/
+#define I2C_TX_SEND_EMPTY_INT_ST  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ST_M  (BIT(12))
+#define I2C_TX_SEND_EMPTY_INT_ST_V  0x1
+#define I2C_TX_SEND_EMPTY_INT_ST_S  12
+/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The masked interrupt status for rx_rec_full_int interrupt.*/
+#define I2C_RX_REC_FULL_INT_ST  (BIT(11))
+#define I2C_RX_REC_FULL_INT_ST_M  (BIT(11))
+#define I2C_RX_REC_FULL_INT_ST_V  0x1
+#define I2C_RX_REC_FULL_INT_ST_S  11
+/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The masked interrupt status for ack_err_int interrupt.*/
+#define I2C_ACK_ERR_INT_ST  (BIT(10))
+#define I2C_ACK_ERR_INT_ST_M  (BIT(10))
+#define I2C_ACK_ERR_INT_ST_V  0x1
+#define I2C_ACK_ERR_INT_ST_S  10
+/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The masked interrupt status for trans_start_int interrupt.*/
+#define I2C_TRANS_START_INT_ST  (BIT(9))
+#define I2C_TRANS_START_INT_ST_M  (BIT(9))
+#define I2C_TRANS_START_INT_ST_V  0x1
+#define I2C_TRANS_START_INT_ST_S  9
+/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The masked interrupt status for time_out_int interrupt.*/
+#define I2C_TIME_OUT_INT_ST  (BIT(8))
+#define I2C_TIME_OUT_INT_ST_M  (BIT(8))
+#define I2C_TIME_OUT_INT_ST_V  0x1
+#define I2C_TIME_OUT_INT_ST_S  8
+/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The masked interrupt status for trans_complete_int interrupt.*/
+#define I2C_TRANS_COMPLETE_INT_ST  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_M  (BIT(7))
+#define I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define I2C_TRANS_COMPLETE_INT_ST_S  7
+/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The masked interrupt status for master_tran_comp_int interrupt.*/
+#define I2C_MASTER_TRAN_COMP_INT_ST  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ST_M  (BIT(6))
+#define I2C_MASTER_TRAN_COMP_INT_ST_V  0x1
+#define I2C_MASTER_TRAN_COMP_INT_ST_S  6
+/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The masked interrupt status for arbitration_lost_int interrupt.*/
+#define I2C_ARBITRATION_LOST_INT_ST  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_M  (BIT(5))
+#define I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define I2C_ARBITRATION_LOST_INT_ST_S  5
+/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The masked interrupt status for slave_tran_comp_int interrupt.*/
+#define I2C_SLAVE_TRAN_COMP_INT_ST  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ST_M  (BIT(4))
+#define I2C_SLAVE_TRAN_COMP_INT_ST_V  0x1
+#define I2C_SLAVE_TRAN_COMP_INT_ST_S  4
+/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The masked interrupt status for end_detect_int interrupt.*/
+#define I2C_END_DETECT_INT_ST  (BIT(3))
+#define I2C_END_DETECT_INT_ST_M  (BIT(3))
+#define I2C_END_DETECT_INT_ST_V  0x1
+#define I2C_END_DETECT_INT_ST_S  3
+/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The masked interrupt status for rxfifo_ovf_int interrupt.*/
+#define I2C_RXFIFO_OVF_INT_ST  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_M  (BIT(2))
+#define I2C_RXFIFO_OVF_INT_ST_V  0x1
+#define I2C_RXFIFO_OVF_INT_ST_S  2
+/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The masked interrupt status for txfifo_empty_int interrupt.*/
+#define I2C_TXFIFO_EMPTY_INT_ST  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
+#define I2C_TXFIFO_EMPTY_INT_ST_V  0x1
+#define I2C_TXFIFO_EMPTY_INT_ST_S  1
+/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status for rxfifo_full_int interrupt.*/
+#define I2C_RXFIFO_FULL_INT_ST  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ST_M  (BIT(0))
+#define I2C_RXFIFO_FULL_INT_ST_V  0x1
+#define I2C_RXFIFO_FULL_INT_ST_S  0
+
+#define I2C_SDA_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0030)
+/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: This register is used to configure the clock num I2C used to
+ hold the data after the negedge of SCL.*/
+#define I2C_SDA_HOLD_TIME  0x000003FF
+#define I2C_SDA_HOLD_TIME_M  ((I2C_SDA_HOLD_TIME_V)<<(I2C_SDA_HOLD_TIME_S))
+#define I2C_SDA_HOLD_TIME_V  0x3FF
+#define I2C_SDA_HOLD_TIME_S  0
+
+#define I2C_SDA_SAMPLE_REG(i)          (REG_I2C_BASE(i) + 0x0034)
+/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: This register is used to configure the clock num I2C used to
+ sample data on SDA after the posedge of SCL*/
+#define I2C_SDA_SAMPLE_TIME  0x000003FF
+#define I2C_SDA_SAMPLE_TIME_M  ((I2C_SDA_SAMPLE_TIME_V)<<(I2C_SDA_SAMPLE_TIME_S))
+#define I2C_SDA_SAMPLE_TIME_V  0x3FF
+#define I2C_SDA_SAMPLE_TIME_S  0
+
+#define I2C_SCL_HIGH_PERIOD_REG(i)          (REG_I2C_BASE(i) + 0x0038)
+/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This register is used to configure the clock num during SCL is low level.*/
+#define I2C_SCL_HIGH_PERIOD  0x00003FFF
+#define I2C_SCL_HIGH_PERIOD_M  ((I2C_SCL_HIGH_PERIOD_V)<<(I2C_SCL_HIGH_PERIOD_S))
+#define I2C_SCL_HIGH_PERIOD_V  0x3FFF
+#define I2C_SCL_HIGH_PERIOD_S  0
+
+#define I2C_SCL_START_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0040)
+/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
+/*description: This register is used to configure the clock num between the
+ negedge of SDA and negedge of SCL for start mark.*/
+#define I2C_SCL_START_HOLD_TIME  0x000003FF
+#define I2C_SCL_START_HOLD_TIME_M  ((I2C_SCL_START_HOLD_TIME_V)<<(I2C_SCL_START_HOLD_TIME_S))
+#define I2C_SCL_START_HOLD_TIME_V  0x3FF
+#define I2C_SCL_START_HOLD_TIME_S  0
+
+#define I2C_SCL_RSTART_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x0044)
+/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */
+/*description: This register is used to configure the clock num between the
+ posedge of SCL and the negedge of SDA for restart mark.*/
+#define I2C_SCL_RSTART_SETUP_TIME  0x000003FF
+#define I2C_SCL_RSTART_SETUP_TIME_M  ((I2C_SCL_RSTART_SETUP_TIME_V)<<(I2C_SCL_RSTART_SETUP_TIME_S))
+#define I2C_SCL_RSTART_SETUP_TIME_V  0x3FF
+#define I2C_SCL_RSTART_SETUP_TIME_S  0
+
+#define I2C_SCL_STOP_HOLD_REG(i)          (REG_I2C_BASE(i) + 0x0048)
+/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This register is used to configure the clock num after the STOP bit's posedge.*/
+#define I2C_SCL_STOP_HOLD_TIME  0x00003FFF
+#define I2C_SCL_STOP_HOLD_TIME_M  ((I2C_SCL_STOP_HOLD_TIME_V)<<(I2C_SCL_STOP_HOLD_TIME_S))
+#define I2C_SCL_STOP_HOLD_TIME_V  0x3FFF
+#define I2C_SCL_STOP_HOLD_TIME_S  0
+
+#define I2C_SCL_STOP_SETUP_REG(i)          (REG_I2C_BASE(i) + 0x004C)
+/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: This register is used to configure the clock num between the
+ posedge of SCL and the posedge of SDA.*/
+#define I2C_SCL_STOP_SETUP_TIME  0x000003FF
+#define I2C_SCL_STOP_SETUP_TIME_M  ((I2C_SCL_STOP_SETUP_TIME_V)<<(I2C_SCL_STOP_SETUP_TIME_S))
+#define I2C_SCL_STOP_SETUP_TIME_V  0x3FF
+#define I2C_SCL_STOP_SETUP_TIME_S  0
+
+#define I2C_SCL_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x0050)
+/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: This is the filter enable bit for SCL.*/
+#define I2C_SCL_FILTER_EN  (BIT(3))
+#define I2C_SCL_FILTER_EN_M  (BIT(3))
+#define I2C_SCL_FILTER_EN_V  0x1
+#define I2C_SCL_FILTER_EN_S  3
+/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: When input SCL's pulse width is smaller than this register value
+  I2C ignores this pulse.*/
+#define I2C_SCL_FILTER_THRES  0x00000007
+#define I2C_SCL_FILTER_THRES_M  ((I2C_SCL_FILTER_THRES_V)<<(I2C_SCL_FILTER_THRES_S))
+#define I2C_SCL_FILTER_THRES_V  0x7
+#define I2C_SCL_FILTER_THRES_S  0
+
+#define I2C_SDA_FILTER_CFG_REG(i)          (REG_I2C_BASE(i) + 0x0054)
+/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: This is the filter enable bit for SDA.*/
+#define I2C_SDA_FILTER_EN  (BIT(3))
+#define I2C_SDA_FILTER_EN_M  (BIT(3))
+#define I2C_SDA_FILTER_EN_V  0x1
+#define I2C_SDA_FILTER_EN_S  3
+/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: When input SCL's pulse width is smaller than this register value
+  I2C ignores this pulse.*/
+#define I2C_SDA_FILTER_THRES  0x00000007
+#define I2C_SDA_FILTER_THRES_M  ((I2C_SDA_FILTER_THRES_V)<<(I2C_SDA_FILTER_THRES_S))
+#define I2C_SDA_FILTER_THRES_V  0x7
+#define I2C_SDA_FILTER_THRES_S  0
+
+#define I2C_COMD0_REG(i)          (REG_I2C_BASE(i) + 0x0058)
+/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command0 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND0_DONE  (BIT(31))
+#define I2C_COMMAND0_DONE_M  (BIT(31))
+#define I2C_COMMAND0_DONE_V  0x1
+#define I2C_COMMAND0_DONE_S  31
+/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command0. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND0  0x00003FFF
+#define I2C_COMMAND0_M  ((I2C_COMMAND0_V)<<(I2C_COMMAND0_S))
+#define I2C_COMMAND0_V  0x3FFF
+#define I2C_COMMAND0_S  0
+
+#define I2C_COMD1_REG(i)          (REG_I2C_BASE(i) + 0x005C)
+/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command1 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND1_DONE  (BIT(31))
+#define I2C_COMMAND1_DONE_M  (BIT(31))
+#define I2C_COMMAND1_DONE_V  0x1
+#define I2C_COMMAND1_DONE_S  31
+/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command1. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND1  0x00003FFF
+#define I2C_COMMAND1_M  ((I2C_COMMAND1_V)<<(I2C_COMMAND1_S))
+#define I2C_COMMAND1_V  0x3FFF
+#define I2C_COMMAND1_S  0
+
+#define I2C_COMD2_REG(i)          (REG_I2C_BASE(i) + 0x0060)
+/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command2 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND2_DONE  (BIT(31))
+#define I2C_COMMAND2_DONE_M  (BIT(31))
+#define I2C_COMMAND2_DONE_V  0x1
+#define I2C_COMMAND2_DONE_S  31
+/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command2. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND2  0x00003FFF
+#define I2C_COMMAND2_M  ((I2C_COMMAND2_V)<<(I2C_COMMAND2_S))
+#define I2C_COMMAND2_V  0x3FFF
+#define I2C_COMMAND2_S  0
+
+#define I2C_COMD3_REG(i)          (REG_I2C_BASE(i) + 0x0064)
+/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command3 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND3_DONE  (BIT(31))
+#define I2C_COMMAND3_DONE_M  (BIT(31))
+#define I2C_COMMAND3_DONE_V  0x1
+#define I2C_COMMAND3_DONE_S  31
+/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command3. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND3  0x00003FFF
+#define I2C_COMMAND3_M  ((I2C_COMMAND3_V)<<(I2C_COMMAND3_S))
+#define I2C_COMMAND3_V  0x3FFF
+#define I2C_COMMAND3_S  0
+
+#define I2C_COMD4_REG(i)          (REG_I2C_BASE(i) + 0x0068)
+/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command4 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND4_DONE  (BIT(31))
+#define I2C_COMMAND4_DONE_M  (BIT(31))
+#define I2C_COMMAND4_DONE_V  0x1
+#define I2C_COMMAND4_DONE_S  31
+/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command4. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND4  0x00003FFF
+#define I2C_COMMAND4_M  ((I2C_COMMAND4_V)<<(I2C_COMMAND4_S))
+#define I2C_COMMAND4_V  0x3FFF
+#define I2C_COMMAND4_S  0
+
+#define I2C_COMD5_REG(i)          (REG_I2C_BASE(i) + 0x006C)
+/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command5 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND5_DONE  (BIT(31))
+#define I2C_COMMAND5_DONE_M  (BIT(31))
+#define I2C_COMMAND5_DONE_V  0x1
+#define I2C_COMMAND5_DONE_S  31
+/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command5. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND5  0x00003FFF
+#define I2C_COMMAND5_M  ((I2C_COMMAND5_V)<<(I2C_COMMAND5_S))
+#define I2C_COMMAND5_V  0x3FFF
+#define I2C_COMMAND5_S  0
+
+#define I2C_COMD6_REG(i)          (REG_I2C_BASE(i) + 0x0070)
+/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command6 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND6_DONE  (BIT(31))
+#define I2C_COMMAND6_DONE_M  (BIT(31))
+#define I2C_COMMAND6_DONE_V  0x1
+#define I2C_COMMAND6_DONE_S  31
+/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command6. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND6  0x00003FFF
+#define I2C_COMMAND6_M  ((I2C_COMMAND6_V)<<(I2C_COMMAND6_S))
+#define I2C_COMMAND6_V  0x3FFF
+#define I2C_COMMAND6_S  0
+
+#define I2C_COMD7_REG(i)          (REG_I2C_BASE(i) + 0x0074)
+/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command7 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND7_DONE  (BIT(31))
+#define I2C_COMMAND7_DONE_M  (BIT(31))
+#define I2C_COMMAND7_DONE_V  0x1
+#define I2C_COMMAND7_DONE_S  31
+/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command7. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND7  0x00003FFF
+#define I2C_COMMAND7_M  ((I2C_COMMAND7_V)<<(I2C_COMMAND7_S))
+#define I2C_COMMAND7_V  0x3FFF
+#define I2C_COMMAND7_S  0
+
+#define I2C_COMD8_REG(i)          (REG_I2C_BASE(i) + 0x0078)
+/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command8 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND8_DONE  (BIT(31))
+#define I2C_COMMAND8_DONE_M  (BIT(31))
+#define I2C_COMMAND8_DONE_V  0x1
+#define I2C_COMMAND8_DONE_S  31
+/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command8. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND8  0x00003FFF
+#define I2C_COMMAND8_M  ((I2C_COMMAND8_V)<<(I2C_COMMAND8_S))
+#define I2C_COMMAND8_V  0x3FFF
+#define I2C_COMMAND8_S  0
+
+#define I2C_COMD9_REG(i)          (REG_I2C_BASE(i) + 0x007C)
+/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command9 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND9_DONE  (BIT(31))
+#define I2C_COMMAND9_DONE_M  (BIT(31))
+#define I2C_COMMAND9_DONE_V  0x1
+#define I2C_COMMAND9_DONE_S  31
+/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command9. It consists of three part. op_code
+ is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND9  0x00003FFF
+#define I2C_COMMAND9_M  ((I2C_COMMAND9_V)<<(I2C_COMMAND9_S))
+#define I2C_COMMAND9_V  0x3FFF
+#define I2C_COMMAND9_S  0
+
+#define I2C_COMD10_REG(i)          (REG_I2C_BASE(i) + 0x0080)
+/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command10 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND10_DONE  (BIT(31))
+#define I2C_COMMAND10_DONE_M  (BIT(31))
+#define I2C_COMMAND10_DONE_V  0x1
+#define I2C_COMMAND10_DONE_S  31
+/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command10. It consists of three part.
+ op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND10  0x00003FFF
+#define I2C_COMMAND10_M  ((I2C_COMMAND10_V)<<(I2C_COMMAND10_S))
+#define I2C_COMMAND10_V  0x3FFF
+#define I2C_COMMAND10_S  0
+
+#define I2C_COMD11_REG(i)          (REG_I2C_BASE(i) + 0x0084)
+/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command11 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND11_DONE  (BIT(31))
+#define I2C_COMMAND11_DONE_M  (BIT(31))
+#define I2C_COMMAND11_DONE_V  0x1
+#define I2C_COMMAND11_DONE_S  31
+/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command11. It consists of three part.
+ op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND11  0x00003FFF
+#define I2C_COMMAND11_M  ((I2C_COMMAND11_V)<<(I2C_COMMAND11_S))
+#define I2C_COMMAND11_V  0x3FFF
+#define I2C_COMMAND11_S  0
+
+#define I2C_COMD12_REG(i)          (REG_I2C_BASE(i) + 0x0088)
+/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command12 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND12_DONE  (BIT(31))
+#define I2C_COMMAND12_DONE_M  (BIT(31))
+#define I2C_COMMAND12_DONE_V  0x1
+#define I2C_COMMAND12_DONE_S  31
+/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command12. It consists of three part.
+ op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND12  0x00003FFF
+#define I2C_COMMAND12_M  ((I2C_COMMAND12_V)<<(I2C_COMMAND12_S))
+#define I2C_COMMAND12_V  0x3FFF
+#define I2C_COMMAND12_S  0
+
+#define I2C_COMD13_REG(i)          (REG_I2C_BASE(i) + 0x008C)
+/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command13 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND13_DONE  (BIT(31))
+#define I2C_COMMAND13_DONE_M  (BIT(31))
+#define I2C_COMMAND13_DONE_V  0x1
+#define I2C_COMMAND13_DONE_S  31
+/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command13. It consists of three part.
+ op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND13  0x00003FFF
+#define I2C_COMMAND13_M  ((I2C_COMMAND13_V)<<(I2C_COMMAND13_S))
+#define I2C_COMMAND13_V  0x3FFF
+#define I2C_COMMAND13_S  0
+
+#define I2C_COMD14_REG(i)          (REG_I2C_BASE(i) + 0x0090)
+/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command14 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND14_DONE  (BIT(31))
+#define I2C_COMMAND14_DONE_M  (BIT(31))
+#define I2C_COMMAND14_DONE_V  0x1
+#define I2C_COMMAND14_DONE_S  31
+/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command14. It consists of three part.
+ op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND14  0x00003FFF
+#define I2C_COMMAND14_M  ((I2C_COMMAND14_V)<<(I2C_COMMAND14_S))
+#define I2C_COMMAND14_V  0x3FFF
+#define I2C_COMMAND14_S  0
+
+#define I2C_COMD15_REG(i)          (REG_I2C_BASE(i) + 0x0094)
+/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When command15 is done in I2C Master mode  this bit changes to high level.*/
+#define I2C_COMMAND15_DONE  (BIT(31))
+#define I2C_COMMAND15_DONE_M  (BIT(31))
+#define I2C_COMMAND15_DONE_V  0x1
+#define I2C_COMMAND15_DONE_S  31
+/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */
+/*description: This is the content of command15. It consists of three part.
+ op_code is the command  0: RSTART   1: WRITE  2: READ  3: STOP . 4:END.  Byte_num represent the number of data need to be send or data need to be received. ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+#define I2C_COMMAND15  0x00003FFF
+#define I2C_COMMAND15_M  ((I2C_COMMAND15_V)<<(I2C_COMMAND15_S))
+#define I2C_COMMAND15_V  0x3FFF
+#define I2C_COMMAND15_S  0
+
+#define I2C_SCL_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x0098)
+/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[23:0] ;default: 24'h100 ; */
+/*description: */
+#define I2C_SCL_ST_TO_REG  0x00FFFFFF
+#define I2C_SCL_ST_TO_REG_M  ((I2C_SCL_ST_TO_REG_V)<<(I2C_SCL_ST_TO_REG_S))
+#define I2C_SCL_ST_TO_REG_V  0xFFFFFF
+#define I2C_SCL_ST_TO_REG_S  0
+
+#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i)          (REG_I2C_BASE(i) + 0x009c)
+/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[23:0] ;default: 24'h100 ; */
+/*description: */
+#define I2C_SCL_MAIN_ST_TO_REG  0x00FFFFFF
+#define I2C_SCL_MAIN_ST_TO_REG_M  ((I2C_SCL_MAIN_ST_TO_REG_V)<<(I2C_SCL_MAIN_ST_TO_REG_S))
+#define I2C_SCL_MAIN_ST_TO_REG_V  0xFFFFFF
+#define I2C_SCL_MAIN_ST_TO_REG_S  0
+
+#define I2C_SCL_SP_CONF_REG(i)          (REG_I2C_BASE(i) + 0x00a0)
+/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SDA_PD_EN  (BIT(7))
+#define I2C_SDA_PD_EN_M  (BIT(7))
+#define I2C_SDA_PD_EN_V  0x1
+#define I2C_SDA_PD_EN_S  7
+/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_PD_EN  (BIT(6))
+#define I2C_SCL_PD_EN_M  (BIT(6))
+#define I2C_SCL_PD_EN_V  0x1
+#define I2C_SCL_PD_EN_S  6
+/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */
+/*description: */
+#define I2C_SCL_RST_SLV_NUM  0x0000001F
+#define I2C_SCL_RST_SLV_NUM_M  ((I2C_SCL_RST_SLV_NUM_V)<<(I2C_SCL_RST_SLV_NUM_S))
+#define I2C_SCL_RST_SLV_NUM_V  0x1F
+#define I2C_SCL_RST_SLV_NUM_S  1
+/* I2C_SCL_RST_SLV_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define I2C_SCL_RST_SLV_EN  (BIT(0))
+#define I2C_SCL_RST_SLV_EN_M  (BIT(0))
+#define I2C_SCL_RST_SLV_EN_V  0x1
+#define I2C_SCL_RST_SLV_EN_S  0
+
+#define I2C_DATE_REG(i)          (REG_I2C_BASE(i) + 0x00F8)
+/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h18051600 ; */
+/*description: */
+#define I2C_DATE  0xFFFFFFFF
+#define I2C_DATE_M  ((I2C_DATE_V)<<(I2C_DATE_S))
+#define I2C_DATE_V  0xFFFFFFFF
+#define I2C_DATE_S  0
+
+#define I2C_FIFO_START_ADDR_REG(i)          (REG_I2C_BASE(i) + 0x0100)
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2C_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/i2c_struct.h b/components/soc/esp32s2beta/include/soc/i2c_struct.h
new file mode 100644
index 000000000..ec018b5e0
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/i2c_struct.h
@@ -0,0 +1,339 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2C_STRUCT_H_
+#define _SOC_I2C_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t period:14;             /*This register is used to configure the  low level width of SCL clock.*/
+            uint32_t reserved14:    18;
+        };
+        uint32_t val;
+    } scl_low_period;
+    union {
+        struct {
+            uint32_t sda_force_out:    1;           /*1：normally output sda data   0: exchange the function of sda_o and sda_oe (sda_o is the original internal output sda signal sda_oe is the enable bit for the internal output sda signal)*/
+            uint32_t scl_force_out:    1;           /*1：normally output scl clock  0: exchange the function of scl_o and scl_oe (scl_o is the original internal output scl signal  scl_oe is the enable bit for the internal output scl signal)*/
+            uint32_t sample_scl_level: 1;           /*Set this bit to sample data in SCL low level. clear this bit to sample data in SCL high level.*/
+            uint32_t ack_level:        1;
+            uint32_t ms_mode:          1;           /*Set this bit to configure the module as i2c master  clear this bit to configure the module as i2c slave.*/
+            uint32_t trans_start:      1;           /*Set this bit to start sending data in tx_fifo.*/
+            uint32_t tx_lsb_first:     1;           /*This bit is used to control the sending mode for  data need to be send. 1：receive data from most significant bit    0：receive data from least significant bit*/
+            uint32_t rx_lsb_first:     1;           /*This bit is used to control the storage mode for received data. 1：receive data from most significant bit    0：receive data from least significant bit*/
+            uint32_t clk_en:           1;           /*This is the clock gating control bit for reading or writing registers.*/
+            uint32_t arbitration_en:   1;
+            uint32_t fsm_rst:          1;
+            uint32_t ref_always_on:    1;
+            uint32_t reserved12:      20;
+        };
+        uint32_t val;
+    } ctr;
+    union {
+        struct {
+            uint32_t ack_rec:             1;        /*This register stores the value of ACK bit.*/
+            uint32_t slave_rw:            1;        /*when in slave mode  1：master read slave  0: master write slave.*/
+            uint32_t time_out:            1;        /*when I2C takes more than time_out_reg clocks to receive a data then this register changes to high level.*/
+            uint32_t arb_lost:            1;        /*when I2C lost control of SDA line  this register changes to high level.*/
+            uint32_t bus_busy:            1;        /*1:I2C bus is busy transferring data. 0:I2C bus is in idle state.*/
+            uint32_t slave_addressed:     1;        /*when configured as i2c slave  and the address send by master is equal to slave's address  then this bit will be high level.*/
+            uint32_t byte_trans:          1;        /*This register changes to high level when one byte is transferred.*/
+            uint32_t reserved7:           1;
+            uint32_t rx_fifo_cnt:         6;        /*This register represent the amount of data need to send.*/
+            uint32_t reserved14:          4;
+            uint32_t tx_fifo_cnt:         6;        /*This register stores the amount of received data  in ram.*/
+            uint32_t scl_main_state_last: 3;        /*This register stores the value of state machine for i2c module.  3'h0: SCL_MAIN_IDLE  3'h1: SCL_ADDRESS_SHIFT 3'h2: SCL_ACK_ADDRESS  3'h3: SCL_RX_DATA  3'h4 SCL_TX_DATA  3'h5:SCL_SEND_ACK 3'h6:SCL_WAIT_ACK*/
+            uint32_t reserved27:          1;
+            uint32_t scl_state_last:      3;        /*This register stores the value of state machine to produce SCL. 3'h0: SCL_IDLE  3'h1:SCL_START   3'h2:SCL_LOW_EDGE  3'h3: SCL_LOW   3'h4:SCL_HIGH_EDGE   3'h5:SCL_HIGH  3'h6:SCL_STOP*/
+            uint32_t reserved31:          1;
+        };
+        uint32_t val;
+    } status_reg;
+    union {
+        struct {
+            uint32_t tout:       24;
+            uint32_t time_out_en: 1;
+            uint32_t reserved25:  7;
+        };
+        uint32_t val;
+    } timeout;
+    union {
+        struct {
+            uint32_t addr:       15;                /*when configured as i2c slave  this register is used to configure slave's address.*/
+            uint32_t reserved15: 16;
+            uint32_t en_10bit:    1;                /*This register is used to enable slave 10bit address mode.*/
+        };
+        uint32_t val;
+    } slave_addr;
+    union {
+        struct {
+            uint32_t rx_fifo_start_addr: 5;         /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
+            uint32_t rx_fifo_end_addr:   5;         /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
+            uint32_t tx_fifo_start_addr: 5;         /*This is the offset address of the first  sending data as described in nonfifo_tx_thres register.*/
+            uint32_t tx_fifo_end_addr:   5;         /*This is the offset address of the last  sending data as described in nonfifo_tx_thres register.*/
+            uint32_t rx_update:         1;
+            uint32_t tx_update:         1;
+            uint32_t tx_fifo_init_raddr: 5;
+            uint32_t rx_fifo_init_waddr: 5;
+        };
+        uint32_t val;
+    } fifo_st;
+    union {
+        struct {
+            uint32_t rx_fifo_full_thrhd: 5;
+            uint32_t tx_fifo_empty_thrhd:5;         /*Config tx_fifo empty threhd value when using apb fifo access*/
+            uint32_t nonfifo_en:         1;         /*Set this bit to enble apb nonfifo access.*/
+            uint32_t fifo_addr_cfg_en:   1;         /*When this bit is set to 1 then the byte after address represent the offset address of I2C Slave's ram.*/
+            uint32_t rx_fifo_rst:        1;         /*Set this bit to reset rx fifo when using apb fifo access.*/
+            uint32_t tx_fifo_rst:        1;         /*Set this bit to reset tx fifo when using apb fifo access.*/
+            uint32_t nonfifo_rx_thres:   6;         /*when I2C receives more than nonfifo_rx_thres data  it will produce rx_send_full_int_raw interrupt and update the current offset address of the receiving data.*/
+            uint32_t nonfifo_tx_thres:   6;         /*when I2C sends more than nonfifo_tx_thres data  it will produce tx_send_empty_int_raw interrupt and update the current offset address of the sending data.*/
+            uint32_t reserved26:         6;
+        };
+        uint32_t val;
+    } fifo_conf;
+    union {
+        struct {
+            uint8_t data;                           /*The register represent the byte  data read from rx_fifo when use apb fifo access*/
+            uint8_t reserved[3];
+        };
+        uint32_t val;
+    } fifo_data;
+    union {
+        struct {
+            uint32_t rx_fifo_full:     1;           /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
+            uint32_t tx_fifo_empty:    1;           /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
+            uint32_t rx_fifo_ovf:      1;           /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
+            uint32_t end_detect:       1;           /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with  the END command  it will produce end_detect_int interrupt.*/
+            uint32_t slave_tran_comp:  1;           /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit  it will produce slave_tran_comp_int interrupt.*/
+            uint32_t arbitration_lost: 1;           /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
+            uint32_t master_tran_comp: 1;           /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
+            uint32_t trans_complete:   1;           /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command  it will produce trans_complete_int interrupt.*/
+            uint32_t time_out:         1;           /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data  it will produce  time_out_int interrupt.*/
+            uint32_t trans_start:      1;           /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
+            uint32_t ack_err:          1;           /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit  it will produce ack_err_int interrupt..*/
+            uint32_t rx_rec_full:      1;           /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data  than nonfifo_rx_thres  it will produce rx_rec_full_int interrupt.*/
+            uint32_t tx_send_empty:    1;           /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres  it will produce tx_send_empty_int interrupt..*/
+            uint32_t scl_st_to:                1;
+            uint32_t scl_main_st_to:           1;
+            uint32_t det_start:                1;
+            uint32_t reserved16:              16;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_fifo_full:     1;           /*Set this bit to clear the rx_fifo_full_int interrupt.*/
+            uint32_t tx_fifo_empty:    1;           /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
+            uint32_t rx_fifo_ovf:      1;           /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
+            uint32_t end_detect:       1;           /*Set this bit to clear the end_detect_int interrupt.*/
+            uint32_t slave_tran_comp:  1;           /*Set this bit to clear the slave_tran_comp_int interrupt.*/
+            uint32_t arbitration_lost: 1;           /*Set this bit to clear the arbitration_lost_int interrupt.*/
+            uint32_t master_tran_comp: 1;           /*Set this bit to clear the master_tran_comp interrupt.*/
+            uint32_t trans_complete:   1;           /*Set this bit to clear the trans_complete_int interrupt.*/
+            uint32_t time_out:         1;           /*Set this bit to clear the time_out_int interrupt.*/
+            uint32_t trans_start:      1;           /*Set this bit to clear the trans_start_int interrupt.*/
+            uint32_t ack_err:          1;           /*Set this bit to clear the ack_err_int interrupt.*/
+            uint32_t rx_rec_full:      1;           /*Set this bit to clear the rx_rec_full_int interrupt.*/
+            uint32_t tx_send_empty:    1;           /*Set this bit to clear the tx_send_empty_int interrupt.*/
+            uint32_t scl_st_to:                1;
+            uint32_t scl_main_st_to:           1;
+            uint32_t det_start:                1;
+            uint32_t reserved16:              16;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t rx_fifo_full:     1;           /*The enable bit for rx_fifo_full_int interrupt.*/
+            uint32_t tx_fifo_empty:    1;           /*The enable bit for tx_fifo_empty_int interrupt.*/
+            uint32_t rx_fifo_ovf:      1;           /*The enable bit for rx_fifo_ovf_int interrupt.*/
+            uint32_t end_detect:       1;           /*The enable bit for end_detect_int interrupt.*/
+            uint32_t slave_tran_comp:  1;           /*The enable bit for slave_tran_comp_int interrupt.*/
+            uint32_t arbitration_lost: 1;           /*The enable bit for arbitration_lost_int interrupt.*/
+            uint32_t master_tran_comp: 1;           /*The enable bit for master_tran_comp_int interrupt.*/
+            uint32_t trans_complete:   1;           /*The enable bit for trans_complete_int interrupt.*/
+            uint32_t time_out:         1;           /*The enable bit for time_out_int interrupt.*/
+            uint32_t trans_start:      1;           /*The enable bit for trans_start_int interrupt.*/
+            uint32_t ack_err:          1;           /*The enable bit for ack_err_int interrupt.*/
+            uint32_t rx_rec_full:      1;           /*The enable bit for rx_rec_full_int interrupt.*/
+            uint32_t tx_send_empty:    1;           /*The enable bit for tx_send_empty_int interrupt.*/
+            uint32_t scl_st_to:                1;
+            uint32_t scl_main_st_to:           1;
+            uint32_t det_start:                1;
+            uint32_t reserved16:              16;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_fifo_full:     1;            /*The masked interrupt status for rx_fifo_full_int interrupt.*/
+            uint32_t tx_fifo_empty:    1;            /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
+            uint32_t rx_fifo_ovf:      1;            /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
+            uint32_t end_detect:       1;            /*The masked interrupt status for end_detect_int interrupt.*/
+            uint32_t slave_tran_comp:  1;            /*The masked interrupt status for slave_tran_comp_int interrupt.*/
+            uint32_t arbitration_lost: 1;            /*The masked interrupt status for arbitration_lost_int interrupt.*/
+            uint32_t master_tran_comp: 1;            /*The masked interrupt status for master_tran_comp_int interrupt.*/
+            uint32_t trans_complete:   1;            /*The masked interrupt status for trans_complete_int interrupt.*/
+            uint32_t time_out:         1;            /*The masked interrupt status for time_out_int interrupt.*/
+            uint32_t trans_start:      1;            /*The masked interrupt status for trans_start_int interrupt.*/
+            uint32_t ack_err:          1;            /*The masked interrupt status for ack_err_int interrupt.*/
+            uint32_t rx_rec_full:      1;            /*The masked interrupt status for rx_rec_full_int interrupt.*/
+            uint32_t tx_send_empty:    1;            /*The masked interrupt status for tx_send_empty_int interrupt.*/
+            uint32_t scl_st_to:               1;
+            uint32_t scl_main_st_to:          1;
+            uint32_t det_start:               1;
+            uint32_t reserved16:             16;
+        };
+        uint32_t val;
+    } int_status;
+    union {
+        struct {
+            uint32_t time:        10;                /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
+            uint32_t reserved10:  22;
+        };
+        uint32_t val;
+    } sda_hold;
+    union {
+        struct {
+            uint32_t time:       10;                 /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
+            uint32_t reserved10: 22;
+        };
+        uint32_t val;
+    } sda_sample;
+    union {
+        struct {
+            uint32_t period:     14;                 /*This register is used to configure the clock num during SCL is low level.*/
+            uint32_t reserved14: 18;
+        };
+        uint32_t val;
+    } scl_high_period;
+    uint32_t reserved_3c;
+    union {
+        struct {
+            uint32_t time:       10;                /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
+            uint32_t reserved10: 22;
+        };
+        uint32_t val;
+    } scl_start_hold;
+    union {
+        struct {
+            uint32_t time:       10;                /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
+            uint32_t reserved10: 22;
+        };
+        uint32_t val;
+    } scl_rstart_setup;
+    union {
+        struct {
+            uint32_t time:       14;                /*This register is used to configure the clock num after the STOP bit's posedge.*/
+            uint32_t reserved14: 18;
+        };
+        uint32_t val;
+    } scl_stop_hold;
+    union {
+        struct {
+            uint32_t time:       10;                /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
+            uint32_t reserved10: 22;
+        };
+        uint32_t val;
+    } scl_stop_setup;
+    union {
+        struct {
+            uint32_t thres:      3;                 /*When input SCL's pulse width is smaller than this register value  I2C ignores this pulse.*/
+            uint32_t en:         1;                 /*This is the filter enable bit for SCL.*/
+            uint32_t reserved4: 28;
+        };
+        uint32_t val;
+    } scl_filter_cfg;
+    union {
+        struct {
+            uint32_t thres:      3;                 /*When input SCL's pulse width is smaller than this register value  I2C ignores this pulse.*/
+            uint32_t en:         1;                 /*This is the filter enable bit for SDA.*/
+            uint32_t reserved4: 28;
+        };
+        uint32_t val;
+    } sda_filter_cfg;
+    union {
+        struct {
+            uint32_t byte_num:      8;              /*Byte_num represent the number of data need to be send or data need to be received.*/
+            uint32_t ack_en:        1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+            uint32_t ack_exp:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+            uint32_t ack_val:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+            uint32_t op_code:       3;              /*op_code is the command  0：RSTART   1：WRITE  2：READ  3：STOP . 4:END.*/
+            uint32_t reserved14:   17;
+            uint32_t done:  1;                      /*When command0 is done in I2C Master mode  this bit changes to high level.*/
+        };
+        uint32_t val;
+    } command[16];
+    union {
+        struct {
+            uint32_t scl_st_to: 24;
+            uint32_t reserved24: 8;
+        };
+        uint32_t val;
+    } scl_st_time_out;
+    union {
+        struct {
+            uint32_t scl_main_st_to:24;
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } scl_main_st_time_out;
+    union {
+        struct {
+            uint32_t scl_rst_slv_en:  1;
+            uint32_t scl_rst_slv_num: 5;
+            uint32_t scl_pd_en:       1;
+            uint32_t sda_pd_en:       1;
+            uint32_t reserved8:      24;
+        };
+        uint32_t val;
+    } scl_sp_conf;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t date;                                  /**/
+    uint32_t reserved_fc;
+    uint32_t ram_data[32];                          /*This the start address for ram when use apb nonfifo access.*/
+} i2c_dev_t;
+extern i2c_dev_t I2C0;
+extern i2c_dev_t I2C1;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_I2C_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/i2s_reg.h b/components/soc/esp32s2beta/include/soc/i2s_reg.h
new file mode 100644
index 000000000..219401a79
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/i2s_reg.h
@@ -0,0 +1,1728 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2S_REG_H_
+#define _SOC_I2S_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define I2S_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0008)
+/* I2S_RX_RESET_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_RESET_ST  (BIT(29))
+#define I2S_RX_RESET_ST_M  (BIT(29))
+#define I2S_RX_RESET_ST_V  0x1
+#define I2S_RX_RESET_ST_S  29
+/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define I2S_RX_BIG_ENDIAN  (BIT(28))
+#define I2S_RX_BIG_ENDIAN_M  (BIT(28))
+#define I2S_RX_BIG_ENDIAN_V  0x1
+#define I2S_RX_BIG_ENDIAN_S  28
+/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define I2S_TX_BIG_ENDIAN  (BIT(27))
+#define I2S_TX_BIG_ENDIAN_M  (BIT(27))
+#define I2S_TX_BIG_ENDIAN_V  0x1
+#define I2S_TX_BIG_ENDIAN_S  27
+/* I2S_PRE_REQ_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: set this bit to enable i2s to prepare data earlier*/
+#define I2S_PRE_REQ_EN  (BIT(26))
+#define I2S_PRE_REQ_EN_M  (BIT(26))
+#define I2S_PRE_REQ_EN_V  0x1
+#define I2S_PRE_REQ_EN_S  26
+/* I2S_RX_DMA_EQUAL : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1:data in left channel is equal to data in right channel*/
+#define I2S_RX_DMA_EQUAL  (BIT(25))
+#define I2S_RX_DMA_EQUAL_M  (BIT(25))
+#define I2S_RX_DMA_EQUAL_V  0x1
+#define I2S_RX_DMA_EQUAL_S  25
+/* I2S_TX_DMA_EQUAL : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1:data in left channel is equal to data in right channel*/
+#define I2S_TX_DMA_EQUAL  (BIT(24))
+#define I2S_TX_DMA_EQUAL_M  (BIT(24))
+#define I2S_TX_DMA_EQUAL_V  0x1
+#define I2S_TX_DMA_EQUAL_S  24
+/* I2S_TX_RESET_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: i2s_tx_reset is not ok   0: i2s_tx_reset is ok*/
+#define I2S_TX_RESET_ST  (BIT(23))
+#define I2S_TX_RESET_ST_M  (BIT(23))
+#define I2S_TX_RESET_ST_V  0x1
+#define I2S_TX_RESET_ST_S  23
+/* I2S_RX_FIFO_RESET_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1:i2s_rx_fifo_reset is not ok   0:i2s_rx_fifo reset is ok*/
+#define I2S_RX_FIFO_RESET_ST  (BIT(22))
+#define I2S_RX_FIFO_RESET_ST_M  (BIT(22))
+#define I2S_RX_FIFO_RESET_ST_V  0x1
+#define I2S_RX_FIFO_RESET_ST_S  22
+/* I2S_TX_FIFO_RESET_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: 1:i2s_tx_fifo reset is not ok   0:i2s_tx_fifo_reset is ok*/
+#define I2S_TX_FIFO_RESET_ST  (BIT(21))
+#define I2S_TX_FIFO_RESET_ST_M  (BIT(21))
+#define I2S_TX_FIFO_RESET_ST_V  0x1
+#define I2S_TX_FIFO_RESET_ST_S  21
+/* I2S_SIG_LOOPBACK : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Enable signal loopback mode with transmitter module and receiver
+ module sharing the same WS and BCK signals.*/
+#define I2S_SIG_LOOPBACK  (BIT(20))
+#define I2S_SIG_LOOPBACK_M  (BIT(20))
+#define I2S_SIG_LOOPBACK_V  0x1
+#define I2S_SIG_LOOPBACK_S  20
+/* I2S_RX_LSB_FIRST_DMA : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: 1:the data in DMA/APB transform from low bits*/
+#define I2S_RX_LSB_FIRST_DMA  (BIT(19))
+#define I2S_RX_LSB_FIRST_DMA_M  (BIT(19))
+#define I2S_RX_LSB_FIRST_DMA_V  0x1
+#define I2S_RX_LSB_FIRST_DMA_S  19
+/* I2S_TX_LSB_FIRST_DMA : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: 1:the data in DMA/APB transform from low bits*/
+#define I2S_TX_LSB_FIRST_DMA  (BIT(18))
+#define I2S_TX_LSB_FIRST_DMA_M  (BIT(18))
+#define I2S_TX_LSB_FIRST_DMA_V  0x1
+#define I2S_TX_LSB_FIRST_DMA_S  18
+/* I2S_RX_MSB_RIGHT : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to place right channel data at the MSB in the receive FIFO.*/
+#define I2S_RX_MSB_RIGHT  (BIT(17))
+#define I2S_RX_MSB_RIGHT_M  (BIT(17))
+#define I2S_RX_MSB_RIGHT_V  0x1
+#define I2S_RX_MSB_RIGHT_S  17
+/* I2S_TX_MSB_RIGHT : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to place right channel data at the MSB in the transmit FIFO.*/
+#define I2S_TX_MSB_RIGHT  (BIT(16))
+#define I2S_TX_MSB_RIGHT_M  (BIT(16))
+#define I2S_TX_MSB_RIGHT_V  0x1
+#define I2S_TX_MSB_RIGHT_S  16
+/* I2S_RX_MONO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver  in mono mode*/
+#define I2S_RX_MONO  (BIT(15))
+#define I2S_RX_MONO_M  (BIT(15))
+#define I2S_RX_MONO_V  0x1
+#define I2S_RX_MONO_S  15
+/* I2S_TX_MONO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter in mono mode*/
+#define I2S_TX_MONO  (BIT(14))
+#define I2S_TX_MONO_M  (BIT(14))
+#define I2S_TX_MONO_V  0x1
+#define I2S_TX_MONO_S  14
+/* I2S_RX_SHORT_SYNC : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver in PCM standard mode*/
+#define I2S_RX_SHORT_SYNC  (BIT(13))
+#define I2S_RX_SHORT_SYNC_M  (BIT(13))
+#define I2S_RX_SHORT_SYNC_V  0x1
+#define I2S_RX_SHORT_SYNC_S  13
+/* I2S_TX_SHORT_SYNC : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter in PCM standard mode*/
+#define I2S_TX_SHORT_SYNC  (BIT(12))
+#define I2S_TX_SHORT_SYNC_M  (BIT(12))
+#define I2S_TX_SHORT_SYNC_V  0x1
+#define I2S_TX_SHORT_SYNC_S  12
+/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to enable receiver in Phillips standard mode*/
+#define I2S_RX_MSB_SHIFT  (BIT(11))
+#define I2S_RX_MSB_SHIFT_M  (BIT(11))
+#define I2S_RX_MSB_SHIFT_V  0x1
+#define I2S_RX_MSB_SHIFT_S  11
+/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to enable transmitter in Phillips standard mode*/
+#define I2S_TX_MSB_SHIFT  (BIT(10))
+#define I2S_TX_MSB_SHIFT_M  (BIT(10))
+#define I2S_TX_MSB_SHIFT_V  0x1
+#define I2S_TX_MSB_SHIFT_S  10
+/* I2S_RX_RIGHT_FIRST : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: Set this bit to receive right channel data first*/
+#define I2S_RX_RIGHT_FIRST  (BIT(9))
+#define I2S_RX_RIGHT_FIRST_M  (BIT(9))
+#define I2S_RX_RIGHT_FIRST_V  0x1
+#define I2S_RX_RIGHT_FIRST_S  9
+/* I2S_TX_RIGHT_FIRST : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: Set this bit to transmit right channel data first*/
+#define I2S_TX_RIGHT_FIRST  (BIT(8))
+#define I2S_TX_RIGHT_FIRST_M  (BIT(8))
+#define I2S_TX_RIGHT_FIRST_V  0x1
+#define I2S_TX_RIGHT_FIRST_S  8
+/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave receiver mode*/
+#define I2S_RX_SLAVE_MOD  (BIT(7))
+#define I2S_RX_SLAVE_MOD_M  (BIT(7))
+#define I2S_RX_SLAVE_MOD_V  0x1
+#define I2S_RX_SLAVE_MOD_S  7
+/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to enable slave transmitter mode*/
+#define I2S_TX_SLAVE_MOD  (BIT(6))
+#define I2S_TX_SLAVE_MOD_M  (BIT(6))
+#define I2S_TX_SLAVE_MOD_V  0x1
+#define I2S_TX_SLAVE_MOD_S  6
+/* I2S_RX_START : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to start receiving data*/
+#define I2S_RX_START  (BIT(5))
+#define I2S_RX_START_M  (BIT(5))
+#define I2S_RX_START_V  0x1
+#define I2S_RX_START_S  5
+/* I2S_TX_START : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to start transmitting data*/
+#define I2S_TX_START  (BIT(4))
+#define I2S_TX_START_M  (BIT(4))
+#define I2S_TX_START_V  0x1
+#define I2S_TX_START_S  4
+/* I2S_RX_FIFO_RESET : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset rxFIFO*/
+#define I2S_RX_FIFO_RESET  (BIT(3))
+#define I2S_RX_FIFO_RESET_M  (BIT(3))
+#define I2S_RX_FIFO_RESET_V  0x1
+#define I2S_RX_FIFO_RESET_S  3
+/* I2S_TX_FIFO_RESET : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to reset txFIFO*/
+#define I2S_TX_FIFO_RESET  (BIT(2))
+#define I2S_TX_FIFO_RESET_M  (BIT(2))
+#define I2S_TX_FIFO_RESET_V  0x1
+#define I2S_TX_FIFO_RESET_S  2
+/* I2S_RX_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset receiver*/
+#define I2S_RX_RESET  (BIT(1))
+#define I2S_RX_RESET_M  (BIT(1))
+#define I2S_RX_RESET_V  0x1
+#define I2S_RX_RESET_S  1
+/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to reset transmitter*/
+#define I2S_TX_RESET  (BIT(0))
+#define I2S_TX_RESET_M  (BIT(0))
+#define I2S_TX_RESET_V  0x1
+#define I2S_TX_RESET_S  0
+
+#define I2S_INT_RAW_REG(i)          (REG_I2S_BASE(i) + 0x000c)
+/* I2S_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_out_total_eof_int interrupt*/
+#define I2S_OUT_TOTAL_EOF_INT_RAW  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_RAW_M  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_RAW_V  0x1
+#define I2S_OUT_TOTAL_EOF_INT_RAW_S  16
+/* I2S_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_in_dscr_empty_int interrupt*/
+#define I2S_IN_DSCR_EMPTY_INT_RAW  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_RAW_M  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_RAW_V  0x1
+#define I2S_IN_DSCR_EMPTY_INT_RAW_S  15
+/* I2S_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_out_dscr_err_int interrupt*/
+#define I2S_OUT_DSCR_ERR_INT_RAW  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_RAW_M  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_RAW_V  0x1
+#define I2S_OUT_DSCR_ERR_INT_RAW_S  14
+/* I2S_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_in_dscr_err_int interrupt*/
+#define I2S_IN_DSCR_ERR_INT_RAW  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_RAW_M  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_RAW_V  0x1
+#define I2S_IN_DSCR_ERR_INT_RAW_S  13
+/* I2S_OUT_EOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_out_eof_int interrupt*/
+#define I2S_OUT_EOF_INT_RAW  (BIT(12))
+#define I2S_OUT_EOF_INT_RAW_M  (BIT(12))
+#define I2S_OUT_EOF_INT_RAW_V  0x1
+#define I2S_OUT_EOF_INT_RAW_S  12
+/* I2S_OUT_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_out_done_int interrupt*/
+#define I2S_OUT_DONE_INT_RAW  (BIT(11))
+#define I2S_OUT_DONE_INT_RAW_M  (BIT(11))
+#define I2S_OUT_DONE_INT_RAW_V  0x1
+#define I2S_OUT_DONE_INT_RAW_S  11
+/* I2S_IN_ERR_EOF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_IN_ERR_EOF_INT_RAW  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_RAW_M  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_RAW_V  0x1
+#define I2S_IN_ERR_EOF_INT_RAW_S  10
+/* I2S_IN_SUC_EOF_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_in_suc_eof_int interrupt*/
+#define I2S_IN_SUC_EOF_INT_RAW  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_RAW_M  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_RAW_V  0x1
+#define I2S_IN_SUC_EOF_INT_RAW_S  9
+/* I2S_IN_DONE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_in_done_int interrupt*/
+#define I2S_IN_DONE_INT_RAW  (BIT(8))
+#define I2S_IN_DONE_INT_RAW_M  (BIT(8))
+#define I2S_IN_DONE_INT_RAW_V  0x1
+#define I2S_IN_DONE_INT_RAW_S  8
+/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_RAW  (BIT(7))
+#define I2S_TX_HUNG_INT_RAW_M  (BIT(7))
+#define I2S_TX_HUNG_INT_RAW_V  0x1
+#define I2S_TX_HUNG_INT_RAW_S  7
+/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_RAW  (BIT(6))
+#define I2S_RX_HUNG_INT_RAW_M  (BIT(6))
+#define I2S_RX_HUNG_INT_RAW_V  0x1
+#define I2S_RX_HUNG_INT_RAW_S  6
+/* I2S_TX_REMPTY_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_rempty_int interrupt*/
+#define I2S_TX_REMPTY_INT_RAW  (BIT(5))
+#define I2S_TX_REMPTY_INT_RAW_M  (BIT(5))
+#define I2S_TX_REMPTY_INT_RAW_V  0x1
+#define I2S_TX_REMPTY_INT_RAW_S  5
+/* I2S_TX_WFULL_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_wfull_int interrupt*/
+#define I2S_TX_WFULL_INT_RAW  (BIT(4))
+#define I2S_TX_WFULL_INT_RAW_M  (BIT(4))
+#define I2S_TX_WFULL_INT_RAW_V  0x1
+#define I2S_TX_WFULL_INT_RAW_S  4
+/* I2S_RX_REMPTY_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_rempty_int interrupt*/
+#define I2S_RX_REMPTY_INT_RAW  (BIT(3))
+#define I2S_RX_REMPTY_INT_RAW_M  (BIT(3))
+#define I2S_RX_REMPTY_INT_RAW_V  0x1
+#define I2S_RX_REMPTY_INT_RAW_S  3
+/* I2S_RX_WFULL_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_wfull_int interrupt*/
+#define I2S_RX_WFULL_INT_RAW  (BIT(2))
+#define I2S_RX_WFULL_INT_RAW_M  (BIT(2))
+#define I2S_RX_WFULL_INT_RAW_V  0x1
+#define I2S_RX_WFULL_INT_RAW_S  2
+/* I2S_TX_PUT_DATA_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_tx_put_data_int interrupt*/
+#define I2S_TX_PUT_DATA_INT_RAW  (BIT(1))
+#define I2S_TX_PUT_DATA_INT_RAW_M  (BIT(1))
+#define I2S_TX_PUT_DATA_INT_RAW_V  0x1
+#define I2S_TX_PUT_DATA_INT_RAW_S  1
+/* I2S_RX_TAKE_DATA_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw interrupt status bit  for the i2s_rx_take_data_int interrupt*/
+#define I2S_RX_TAKE_DATA_INT_RAW  (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_RAW_M  (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_RAW_V  0x1
+#define I2S_RX_TAKE_DATA_INT_RAW_S  0
+
+#define I2S_INT_ST_REG(i)          (REG_I2S_BASE(i) + 0x0010)
+/* I2S_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_out_total_eof_int interrupt*/
+#define I2S_OUT_TOTAL_EOF_INT_ST  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ST_M  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ST_V  0x1
+#define I2S_OUT_TOTAL_EOF_INT_ST_S  16
+/* I2S_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_in_dscr_empty_int interrupt*/
+#define I2S_IN_DSCR_EMPTY_INT_ST  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ST_M  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ST_V  0x1
+#define I2S_IN_DSCR_EMPTY_INT_ST_S  15
+/* I2S_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_out_dscr_err_int interrupt*/
+#define I2S_OUT_DSCR_ERR_INT_ST  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ST_M  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ST_V  0x1
+#define I2S_OUT_DSCR_ERR_INT_ST_S  14
+/* I2S_IN_DSCR_ERR_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_in_dscr_err_int interrupt*/
+#define I2S_IN_DSCR_ERR_INT_ST  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ST_M  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ST_V  0x1
+#define I2S_IN_DSCR_ERR_INT_ST_S  13
+/* I2S_OUT_EOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_out_eof_int interrupt*/
+#define I2S_OUT_EOF_INT_ST  (BIT(12))
+#define I2S_OUT_EOF_INT_ST_M  (BIT(12))
+#define I2S_OUT_EOF_INT_ST_V  0x1
+#define I2S_OUT_EOF_INT_ST_S  12
+/* I2S_OUT_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_out_done_int interrupt*/
+#define I2S_OUT_DONE_INT_ST  (BIT(11))
+#define I2S_OUT_DONE_INT_ST_M  (BIT(11))
+#define I2S_OUT_DONE_INT_ST_V  0x1
+#define I2S_OUT_DONE_INT_ST_S  11
+/* I2S_IN_ERR_EOF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_IN_ERR_EOF_INT_ST  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ST_M  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ST_V  0x1
+#define I2S_IN_ERR_EOF_INT_ST_S  10
+/* I2S_IN_SUC_EOF_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_in_suc_eof_int interrupt*/
+#define I2S_IN_SUC_EOF_INT_ST  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ST_M  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ST_V  0x1
+#define I2S_IN_SUC_EOF_INT_ST_S  9
+/* I2S_IN_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_in_done_int interrupt*/
+#define I2S_IN_DONE_INT_ST  (BIT(8))
+#define I2S_IN_DONE_INT_ST_M  (BIT(8))
+#define I2S_IN_DONE_INT_ST_V  0x1
+#define I2S_IN_DONE_INT_ST_S  8
+/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_ST  (BIT(7))
+#define I2S_TX_HUNG_INT_ST_M  (BIT(7))
+#define I2S_TX_HUNG_INT_ST_V  0x1
+#define I2S_TX_HUNG_INT_ST_S  7
+/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_ST  (BIT(6))
+#define I2S_RX_HUNG_INT_ST_M  (BIT(6))
+#define I2S_RX_HUNG_INT_ST_V  0x1
+#define I2S_RX_HUNG_INT_ST_S  6
+/* I2S_TX_REMPTY_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_rempty_int interrupt*/
+#define I2S_TX_REMPTY_INT_ST  (BIT(5))
+#define I2S_TX_REMPTY_INT_ST_M  (BIT(5))
+#define I2S_TX_REMPTY_INT_ST_V  0x1
+#define I2S_TX_REMPTY_INT_ST_S  5
+/* I2S_TX_WFULL_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_wfull_int interrupt*/
+#define I2S_TX_WFULL_INT_ST  (BIT(4))
+#define I2S_TX_WFULL_INT_ST_M  (BIT(4))
+#define I2S_TX_WFULL_INT_ST_V  0x1
+#define I2S_TX_WFULL_INT_ST_S  4
+/* I2S_RX_REMPTY_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_rempty_int interrupt*/
+#define I2S_RX_REMPTY_INT_ST  (BIT(3))
+#define I2S_RX_REMPTY_INT_ST_M  (BIT(3))
+#define I2S_RX_REMPTY_INT_ST_V  0x1
+#define I2S_RX_REMPTY_INT_ST_S  3
+/* I2S_RX_WFULL_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_wfull_int interrupt*/
+#define I2S_RX_WFULL_INT_ST  (BIT(2))
+#define I2S_RX_WFULL_INT_ST_M  (BIT(2))
+#define I2S_RX_WFULL_INT_ST_V  0x1
+#define I2S_RX_WFULL_INT_ST_S  2
+/* I2S_TX_PUT_DATA_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_tx_put_data_int interrupt*/
+#define I2S_TX_PUT_DATA_INT_ST  (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ST_M  (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ST_V  0x1
+#define I2S_TX_PUT_DATA_INT_ST_S  1
+/* I2S_RX_TAKE_DATA_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The masked interrupt status bit  for the i2s_rx_take_data_int interrupt*/
+#define I2S_RX_TAKE_DATA_INT_ST  (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ST_M  (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ST_V  0x1
+#define I2S_RX_TAKE_DATA_INT_ST_S  0
+
+#define I2S_INT_ENA_REG(i)          (REG_I2S_BASE(i) + 0x0014)
+/* I2S_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_out_total_eof_int interrupt*/
+#define I2S_OUT_TOTAL_EOF_INT_ENA  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ENA_M  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_ENA_V  0x1
+#define I2S_OUT_TOTAL_EOF_INT_ENA_S  16
+/* I2S_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_in_dscr_empty_int interrupt*/
+#define I2S_IN_DSCR_EMPTY_INT_ENA  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ENA_M  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_ENA_V  0x1
+#define I2S_IN_DSCR_EMPTY_INT_ENA_S  15
+/* I2S_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_out_dscr_err_int interrupt*/
+#define I2S_OUT_DSCR_ERR_INT_ENA  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ENA_M  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_ENA_V  0x1
+#define I2S_OUT_DSCR_ERR_INT_ENA_S  14
+/* I2S_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_in_dscr_err_int interrupt*/
+#define I2S_IN_DSCR_ERR_INT_ENA  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ENA_M  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_ENA_V  0x1
+#define I2S_IN_DSCR_ERR_INT_ENA_S  13
+/* I2S_OUT_EOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_out_eof_int interrupt*/
+#define I2S_OUT_EOF_INT_ENA  (BIT(12))
+#define I2S_OUT_EOF_INT_ENA_M  (BIT(12))
+#define I2S_OUT_EOF_INT_ENA_V  0x1
+#define I2S_OUT_EOF_INT_ENA_S  12
+/* I2S_OUT_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_out_done_int interrupt*/
+#define I2S_OUT_DONE_INT_ENA  (BIT(11))
+#define I2S_OUT_DONE_INT_ENA_M  (BIT(11))
+#define I2S_OUT_DONE_INT_ENA_V  0x1
+#define I2S_OUT_DONE_INT_ENA_S  11
+/* I2S_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_IN_ERR_EOF_INT_ENA  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ENA_M  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_ENA_V  0x1
+#define I2S_IN_ERR_EOF_INT_ENA_S  10
+/* I2S_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_in_suc_eof_int interrupt*/
+#define I2S_IN_SUC_EOF_INT_ENA  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ENA_M  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_ENA_V  0x1
+#define I2S_IN_SUC_EOF_INT_ENA_S  9
+/* I2S_IN_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_in_done_int interrupt*/
+#define I2S_IN_DONE_INT_ENA  (BIT(8))
+#define I2S_IN_DONE_INT_ENA_M  (BIT(8))
+#define I2S_IN_DONE_INT_ENA_V  0x1
+#define I2S_IN_DONE_INT_ENA_S  8
+/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_ENA  (BIT(7))
+#define I2S_TX_HUNG_INT_ENA_M  (BIT(7))
+#define I2S_TX_HUNG_INT_ENA_V  0x1
+#define I2S_TX_HUNG_INT_ENA_S  7
+/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_ENA  (BIT(6))
+#define I2S_RX_HUNG_INT_ENA_M  (BIT(6))
+#define I2S_RX_HUNG_INT_ENA_V  0x1
+#define I2S_RX_HUNG_INT_ENA_S  6
+/* I2S_TX_REMPTY_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_rempty_int interrupt*/
+#define I2S_TX_REMPTY_INT_ENA  (BIT(5))
+#define I2S_TX_REMPTY_INT_ENA_M  (BIT(5))
+#define I2S_TX_REMPTY_INT_ENA_V  0x1
+#define I2S_TX_REMPTY_INT_ENA_S  5
+/* I2S_TX_WFULL_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_wfull_int interrupt*/
+#define I2S_TX_WFULL_INT_ENA  (BIT(4))
+#define I2S_TX_WFULL_INT_ENA_M  (BIT(4))
+#define I2S_TX_WFULL_INT_ENA_V  0x1
+#define I2S_TX_WFULL_INT_ENA_S  4
+/* I2S_RX_REMPTY_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_rempty_int interrupt*/
+#define I2S_RX_REMPTY_INT_ENA  (BIT(3))
+#define I2S_RX_REMPTY_INT_ENA_M  (BIT(3))
+#define I2S_RX_REMPTY_INT_ENA_V  0x1
+#define I2S_RX_REMPTY_INT_ENA_S  3
+/* I2S_RX_WFULL_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_wfull_int interrupt*/
+#define I2S_RX_WFULL_INT_ENA  (BIT(2))
+#define I2S_RX_WFULL_INT_ENA_M  (BIT(2))
+#define I2S_RX_WFULL_INT_ENA_V  0x1
+#define I2S_RX_WFULL_INT_ENA_S  2
+/* I2S_TX_PUT_DATA_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_tx_put_data_int interrupt*/
+#define I2S_TX_PUT_DATA_INT_ENA  (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ENA_M  (BIT(1))
+#define I2S_TX_PUT_DATA_INT_ENA_V  0x1
+#define I2S_TX_PUT_DATA_INT_ENA_S  1
+/* I2S_RX_TAKE_DATA_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit  for the i2s_rx_take_data_int interrupt*/
+#define I2S_RX_TAKE_DATA_INT_ENA  (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ENA_M  (BIT(0))
+#define I2S_RX_TAKE_DATA_INT_ENA_V  0x1
+#define I2S_RX_TAKE_DATA_INT_ENA_S  0
+
+#define I2S_INT_CLR_REG(i)          (REG_I2S_BASE(i) + 0x0018)
+/* I2S_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_out_total_eof_int interrupt*/
+#define I2S_OUT_TOTAL_EOF_INT_CLR  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_CLR_M  (BIT(16))
+#define I2S_OUT_TOTAL_EOF_INT_CLR_V  0x1
+#define I2S_OUT_TOTAL_EOF_INT_CLR_S  16
+/* I2S_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_in_dscr_empty_int interrupt*/
+#define I2S_IN_DSCR_EMPTY_INT_CLR  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_CLR_M  (BIT(15))
+#define I2S_IN_DSCR_EMPTY_INT_CLR_V  0x1
+#define I2S_IN_DSCR_EMPTY_INT_CLR_S  15
+/* I2S_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_out_dscr_err_int interrupt*/
+#define I2S_OUT_DSCR_ERR_INT_CLR  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_CLR_M  (BIT(14))
+#define I2S_OUT_DSCR_ERR_INT_CLR_V  0x1
+#define I2S_OUT_DSCR_ERR_INT_CLR_S  14
+/* I2S_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_in_dscr_err_int interrupt*/
+#define I2S_IN_DSCR_ERR_INT_CLR  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_CLR_M  (BIT(13))
+#define I2S_IN_DSCR_ERR_INT_CLR_V  0x1
+#define I2S_IN_DSCR_ERR_INT_CLR_S  13
+/* I2S_OUT_EOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_out_eof_int interrupt*/
+#define I2S_OUT_EOF_INT_CLR  (BIT(12))
+#define I2S_OUT_EOF_INT_CLR_M  (BIT(12))
+#define I2S_OUT_EOF_INT_CLR_V  0x1
+#define I2S_OUT_EOF_INT_CLR_S  12
+/* I2S_OUT_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_out_done_int interrupt*/
+#define I2S_OUT_DONE_INT_CLR  (BIT(11))
+#define I2S_OUT_DONE_INT_CLR_M  (BIT(11))
+#define I2S_OUT_DONE_INT_CLR_V  0x1
+#define I2S_OUT_DONE_INT_CLR_S  11
+/* I2S_IN_ERR_EOF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_IN_ERR_EOF_INT_CLR  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_CLR_M  (BIT(10))
+#define I2S_IN_ERR_EOF_INT_CLR_V  0x1
+#define I2S_IN_ERR_EOF_INT_CLR_S  10
+/* I2S_IN_SUC_EOF_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_in_suc_eof_int interrupt*/
+#define I2S_IN_SUC_EOF_INT_CLR  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_CLR_M  (BIT(9))
+#define I2S_IN_SUC_EOF_INT_CLR_V  0x1
+#define I2S_IN_SUC_EOF_INT_CLR_S  9
+/* I2S_IN_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_in_done_int interrupt*/
+#define I2S_IN_DONE_INT_CLR  (BIT(8))
+#define I2S_IN_DONE_INT_CLR_M  (BIT(8))
+#define I2S_IN_DONE_INT_CLR_V  0x1
+#define I2S_IN_DONE_INT_CLR_S  8
+/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/
+#define I2S_TX_HUNG_INT_CLR  (BIT(7))
+#define I2S_TX_HUNG_INT_CLR_M  (BIT(7))
+#define I2S_TX_HUNG_INT_CLR_V  0x1
+#define I2S_TX_HUNG_INT_CLR_S  7
+/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/
+#define I2S_RX_HUNG_INT_CLR  (BIT(6))
+#define I2S_RX_HUNG_INT_CLR_M  (BIT(6))
+#define I2S_RX_HUNG_INT_CLR_V  0x1
+#define I2S_RX_HUNG_INT_CLR_S  6
+/* I2S_TX_REMPTY_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_rempty_int interrupt*/
+#define I2S_TX_REMPTY_INT_CLR  (BIT(5))
+#define I2S_TX_REMPTY_INT_CLR_M  (BIT(5))
+#define I2S_TX_REMPTY_INT_CLR_V  0x1
+#define I2S_TX_REMPTY_INT_CLR_S  5
+/* I2S_TX_WFULL_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_wfull_int interrupt*/
+#define I2S_TX_WFULL_INT_CLR  (BIT(4))
+#define I2S_TX_WFULL_INT_CLR_M  (BIT(4))
+#define I2S_TX_WFULL_INT_CLR_V  0x1
+#define I2S_TX_WFULL_INT_CLR_S  4
+/* I2S_RX_REMPTY_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_rempty_int interrupt*/
+#define I2S_RX_REMPTY_INT_CLR  (BIT(3))
+#define I2S_RX_REMPTY_INT_CLR_M  (BIT(3))
+#define I2S_RX_REMPTY_INT_CLR_V  0x1
+#define I2S_RX_REMPTY_INT_CLR_S  3
+/* I2S_RX_WFULL_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_wfull_int interrupt*/
+#define I2S_RX_WFULL_INT_CLR  (BIT(2))
+#define I2S_RX_WFULL_INT_CLR_M  (BIT(2))
+#define I2S_RX_WFULL_INT_CLR_V  0x1
+#define I2S_RX_WFULL_INT_CLR_S  2
+/* I2S_PUT_DATA_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_tx_put_data_int interrupt*/
+#define I2S_PUT_DATA_INT_CLR  (BIT(1))
+#define I2S_PUT_DATA_INT_CLR_M  (BIT(1))
+#define I2S_PUT_DATA_INT_CLR_V  0x1
+#define I2S_PUT_DATA_INT_CLR_S  1
+/* I2S_TAKE_DATA_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the i2s_rx_take_data_int interrupt*/
+#define I2S_TAKE_DATA_INT_CLR  (BIT(0))
+#define I2S_TAKE_DATA_INT_CLR_M  (BIT(0))
+#define I2S_TAKE_DATA_INT_CLR_V  0x1
+#define I2S_TAKE_DATA_INT_CLR_S  0
+
+#define I2S_TIMING_REG(i)          (REG_I2S_BASE(i) + 0x001c)
+/* I2S_TX_BCK_IN_INV : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to invert BCK signal input to the slave transmitter*/
+#define I2S_TX_BCK_IN_INV  (BIT(24))
+#define I2S_TX_BCK_IN_INV_M  (BIT(24))
+#define I2S_TX_BCK_IN_INV_V  0x1
+#define I2S_TX_BCK_IN_INV_S  24
+/* I2S_DATA_ENABLE_DELAY : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: Number of delay cycles for data valid flag.*/
+#define I2S_DATA_ENABLE_DELAY  0x00000003
+#define I2S_DATA_ENABLE_DELAY_M  ((I2S_DATA_ENABLE_DELAY_V)<<(I2S_DATA_ENABLE_DELAY_S))
+#define I2S_DATA_ENABLE_DELAY_V  0x3
+#define I2S_DATA_ENABLE_DELAY_S  22
+/* I2S_RX_DSYNC_SW : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to synchronize signals with the double sync method
+ into the receiver*/
+#define I2S_RX_DSYNC_SW  (BIT(21))
+#define I2S_RX_DSYNC_SW_M  (BIT(21))
+#define I2S_RX_DSYNC_SW_V  0x1
+#define I2S_RX_DSYNC_SW_S  21
+/* I2S_TX_DSYNC_SW : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to synchronize signals with the double sync method
+ into the transmitter*/
+#define I2S_TX_DSYNC_SW  (BIT(20))
+#define I2S_TX_DSYNC_SW_M  (BIT(20))
+#define I2S_TX_DSYNC_SW_V  0x1
+#define I2S_TX_DSYNC_SW_S  20
+/* I2S_RX_BCK_OUT_DELAY : R/W ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: Number of delay cycles for BCK out of the receiver*/
+#define I2S_RX_BCK_OUT_DELAY  0x00000003
+#define I2S_RX_BCK_OUT_DELAY_M  ((I2S_RX_BCK_OUT_DELAY_V)<<(I2S_RX_BCK_OUT_DELAY_S))
+#define I2S_RX_BCK_OUT_DELAY_V  0x3
+#define I2S_RX_BCK_OUT_DELAY_S  18
+/* I2S_RX_WS_OUT_DELAY : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: Number of delay cycles for WS out of the receiver*/
+#define I2S_RX_WS_OUT_DELAY  0x00000003
+#define I2S_RX_WS_OUT_DELAY_M  ((I2S_RX_WS_OUT_DELAY_V)<<(I2S_RX_WS_OUT_DELAY_S))
+#define I2S_RX_WS_OUT_DELAY_V  0x3
+#define I2S_RX_WS_OUT_DELAY_S  16
+/* I2S_TX_SD_OUT_DELAY : R/W ;bitpos:[15:14] ;default: 2'b0 ; */
+/*description: Number of delay cycles for SD out of the transmitter*/
+#define I2S_TX_SD_OUT_DELAY  0x00000003
+#define I2S_TX_SD_OUT_DELAY_M  ((I2S_TX_SD_OUT_DELAY_V)<<(I2S_TX_SD_OUT_DELAY_S))
+#define I2S_TX_SD_OUT_DELAY_V  0x3
+#define I2S_TX_SD_OUT_DELAY_S  14
+/* I2S_TX_WS_OUT_DELAY : R/W ;bitpos:[13:12] ;default: 2'b0 ; */
+/*description: Number of delay cycles for WS out of the transmitter*/
+#define I2S_TX_WS_OUT_DELAY  0x00000003
+#define I2S_TX_WS_OUT_DELAY_M  ((I2S_TX_WS_OUT_DELAY_V)<<(I2S_TX_WS_OUT_DELAY_S))
+#define I2S_TX_WS_OUT_DELAY_V  0x3
+#define I2S_TX_WS_OUT_DELAY_S  12
+/* I2S_TX_BCK_OUT_DELAY : R/W ;bitpos:[11:10] ;default: 2'b0 ; */
+/*description: Number of delay cycles for BCK out of the transmitter*/
+#define I2S_TX_BCK_OUT_DELAY  0x00000003
+#define I2S_TX_BCK_OUT_DELAY_M  ((I2S_TX_BCK_OUT_DELAY_V)<<(I2S_TX_BCK_OUT_DELAY_S))
+#define I2S_TX_BCK_OUT_DELAY_V  0x3
+#define I2S_TX_BCK_OUT_DELAY_S  10
+/* I2S_RX_SD_IN_DELAY : R/W ;bitpos:[9:8] ;default: 2'b0 ; */
+/*description: Number of delay cycles for SD into the receiver*/
+#define I2S_RX_SD_IN_DELAY  0x00000003
+#define I2S_RX_SD_IN_DELAY_M  ((I2S_RX_SD_IN_DELAY_V)<<(I2S_RX_SD_IN_DELAY_S))
+#define I2S_RX_SD_IN_DELAY_V  0x3
+#define I2S_RX_SD_IN_DELAY_S  8
+/* I2S_RX_WS_IN_DELAY : R/W ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: Number of delay cycles for WS into the receiver*/
+#define I2S_RX_WS_IN_DELAY  0x00000003
+#define I2S_RX_WS_IN_DELAY_M  ((I2S_RX_WS_IN_DELAY_V)<<(I2S_RX_WS_IN_DELAY_S))
+#define I2S_RX_WS_IN_DELAY_V  0x3
+#define I2S_RX_WS_IN_DELAY_S  6
+/* I2S_RX_BCK_IN_DELAY : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: Number of delay cycles for BCK into the receiver*/
+#define I2S_RX_BCK_IN_DELAY  0x00000003
+#define I2S_RX_BCK_IN_DELAY_M  ((I2S_RX_BCK_IN_DELAY_V)<<(I2S_RX_BCK_IN_DELAY_S))
+#define I2S_RX_BCK_IN_DELAY_V  0x3
+#define I2S_RX_BCK_IN_DELAY_S  4
+/* I2S_TX_WS_IN_DELAY : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: Number of delay cycles for WS into the transmitter*/
+#define I2S_TX_WS_IN_DELAY  0x00000003
+#define I2S_TX_WS_IN_DELAY_M  ((I2S_TX_WS_IN_DELAY_V)<<(I2S_TX_WS_IN_DELAY_S))
+#define I2S_TX_WS_IN_DELAY_V  0x3
+#define I2S_TX_WS_IN_DELAY_S  2
+/* I2S_TX_BCK_IN_DELAY : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: Number of delay cycles for BCK into the transmitter*/
+#define I2S_TX_BCK_IN_DELAY  0x00000003
+#define I2S_TX_BCK_IN_DELAY_M  ((I2S_TX_BCK_IN_DELAY_V)<<(I2S_TX_BCK_IN_DELAY_S))
+#define I2S_TX_BCK_IN_DELAY_V  0x3
+#define I2S_TX_BCK_IN_DELAY_S  0
+
+#define I2S_FIFO_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0020)
+/* I2S_TX_24MSB_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Only useful in tx 24bit mode. 1: the high 24 bits are effective
+ in i2s fifo   0: the low 24 bits are effective in i2s fifo*/
+#define I2S_TX_24MSB_EN  (BIT(23))
+#define I2S_TX_24MSB_EN_M  (BIT(23))
+#define I2S_TX_24MSB_EN_V  0x1
+#define I2S_TX_24MSB_EN_S  23
+/* I2S_RX_24MSB_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Only useful in rx 24bit mode. 1: the high 24 bits are effective
+ in i2s fifo   0: the low 24 bits are effective in i2s fifo*/
+#define I2S_RX_24MSB_EN  (BIT(22))
+#define I2S_RX_24MSB_EN_M  (BIT(22))
+#define I2S_RX_24MSB_EN_V  0x1
+#define I2S_RX_24MSB_EN_S  22
+/* I2S_RX_FIFO_SYNC : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: force write back rx data to memory*/
+#define I2S_RX_FIFO_SYNC  (BIT(21))
+#define I2S_RX_FIFO_SYNC_M  (BIT(21))
+#define I2S_RX_FIFO_SYNC_V  0x1
+#define I2S_RX_FIFO_SYNC_S  21
+/* I2S_RX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The bit should always be set to 1*/
+#define I2S_RX_FIFO_MOD_FORCE_EN  (BIT(20))
+#define I2S_RX_FIFO_MOD_FORCE_EN_M  (BIT(20))
+#define I2S_RX_FIFO_MOD_FORCE_EN_V  0x1
+#define I2S_RX_FIFO_MOD_FORCE_EN_S  20
+/* I2S_TX_FIFO_MOD_FORCE_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The bit should always be set to 1*/
+#define I2S_TX_FIFO_MOD_FORCE_EN  (BIT(19))
+#define I2S_TX_FIFO_MOD_FORCE_EN_M  (BIT(19))
+#define I2S_TX_FIFO_MOD_FORCE_EN_V  0x1
+#define I2S_TX_FIFO_MOD_FORCE_EN_S  19
+/* I2S_RX_FIFO_MOD : R/W ;bitpos:[18:16] ;default: 3'b0 ; */
+/*description: Receiver FIFO mode configuration bits*/
+#define I2S_RX_FIFO_MOD  0x00000007
+#define I2S_RX_FIFO_MOD_M  ((I2S_RX_FIFO_MOD_V)<<(I2S_RX_FIFO_MOD_S))
+#define I2S_RX_FIFO_MOD_V  0x7
+#define I2S_RX_FIFO_MOD_S  16
+/* I2S_TX_FIFO_MOD : R/W ;bitpos:[15:13] ;default: 3'b0 ; */
+/*description: Transmitter FIFO mode configuration bits*/
+#define I2S_TX_FIFO_MOD  0x00000007
+#define I2S_TX_FIFO_MOD_M  ((I2S_TX_FIFO_MOD_V)<<(I2S_TX_FIFO_MOD_S))
+#define I2S_TX_FIFO_MOD_V  0x7
+#define I2S_TX_FIFO_MOD_S  13
+/* I2S_DSCR_EN : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: Set this bit to enable I2S DMA mode*/
+#define I2S_DSCR_EN  (BIT(12))
+#define I2S_DSCR_EN_M  (BIT(12))
+#define I2S_DSCR_EN_V  0x1
+#define I2S_DSCR_EN_S  12
+/* I2S_TX_DATA_NUM : R/W ;bitpos:[11:6] ;default: 6'd32 ; */
+/*description: Threshold of data length in transmitter FIFO*/
+#define I2S_TX_DATA_NUM  0x0000003F
+#define I2S_TX_DATA_NUM_M  ((I2S_TX_DATA_NUM_V)<<(I2S_TX_DATA_NUM_S))
+#define I2S_TX_DATA_NUM_V  0x3F
+#define I2S_TX_DATA_NUM_S  6
+/* I2S_RX_DATA_NUM : R/W ;bitpos:[5:0] ;default: 6'd32 ; */
+/*description: Threshold of data length in receiver FIFO*/
+#define I2S_RX_DATA_NUM  0x0000003F
+#define I2S_RX_DATA_NUM_M  ((I2S_RX_DATA_NUM_V)<<(I2S_RX_DATA_NUM_S))
+#define I2S_RX_DATA_NUM_V  0x3F
+#define I2S_RX_DATA_NUM_S  0
+
+#define I2S_RXEOF_NUM_REG(i)          (REG_I2S_BASE(i) + 0x0024)
+/* I2S_RX_EOF_NUM : R/W ;bitpos:[31:0] ;default: 32'd64 ; */
+/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
+#define I2S_RX_EOF_NUM  0xFFFFFFFF
+#define I2S_RX_EOF_NUM_M  ((I2S_RX_EOF_NUM_V)<<(I2S_RX_EOF_NUM_S))
+#define I2S_RX_EOF_NUM_V  0xFFFFFFFF
+#define I2S_RX_EOF_NUM_S  0
+
+#define I2S_CONF_SIGLE_DATA_REG(i)          (REG_I2S_BASE(i) + 0x0028)
+/* I2S_SIGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: the right channel or left channel put out constant value stored
+ in this register according to tx_chan_mod and reg_tx_msb_right*/
+#define I2S_SIGLE_DATA  0xFFFFFFFF
+#define I2S_SIGLE_DATA_M  ((I2S_SIGLE_DATA_V)<<(I2S_SIGLE_DATA_S))
+#define I2S_SIGLE_DATA_V  0xFFFFFFFF
+#define I2S_SIGLE_DATA_S  0
+
+#define I2S_CONF_CHAN_REG(i)          (REG_I2S_BASE(i) + 0x002c)
+/* I2S_RX_CHAN_MOD : R/W ;bitpos:[4:3] ;default: 2'b0 ; */
+/*description: I2S receiver channel mode configuration bits.*/
+#define I2S_RX_CHAN_MOD  0x00000003
+#define I2S_RX_CHAN_MOD_M  ((I2S_RX_CHAN_MOD_V)<<(I2S_RX_CHAN_MOD_S))
+#define I2S_RX_CHAN_MOD_V  0x3
+#define I2S_RX_CHAN_MOD_S  3
+/* I2S_TX_CHAN_MOD : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: I2S transmitter channel mode configuration bits.*/
+#define I2S_TX_CHAN_MOD  0x00000007
+#define I2S_TX_CHAN_MOD_M  ((I2S_TX_CHAN_MOD_V)<<(I2S_TX_CHAN_MOD_S))
+#define I2S_TX_CHAN_MOD_V  0x7
+#define I2S_TX_CHAN_MOD_S  0
+
+#define I2S_OUT_LINK_REG(i)          (REG_I2S_BASE(i) + 0x0030)
+/* I2S_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define I2S_OUTLINK_PARK  (BIT(31))
+#define I2S_OUTLINK_PARK_M  (BIT(31))
+#define I2S_OUTLINK_PARK_V  0x1
+#define I2S_OUTLINK_PARK_S  31
+/* I2S_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to restart outlink descriptor*/
+#define I2S_OUTLINK_RESTART  (BIT(30))
+#define I2S_OUTLINK_RESTART_M  (BIT(30))
+#define I2S_OUTLINK_RESTART_V  0x1
+#define I2S_OUTLINK_RESTART_S  30
+/* I2S_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to start outlink descriptor*/
+#define I2S_OUTLINK_START  (BIT(29))
+#define I2S_OUTLINK_START_M  (BIT(29))
+#define I2S_OUTLINK_START_V  0x1
+#define I2S_OUTLINK_START_S  29
+/* I2S_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to stop outlink descriptor*/
+#define I2S_OUTLINK_STOP  (BIT(28))
+#define I2S_OUTLINK_STOP_M  (BIT(28))
+#define I2S_OUTLINK_STOP_V  0x1
+#define I2S_OUTLINK_STOP_S  28
+/* I2S_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of first outlink descriptor*/
+#define I2S_OUTLINK_ADDR  0x000FFFFF
+#define I2S_OUTLINK_ADDR_M  ((I2S_OUTLINK_ADDR_V)<<(I2S_OUTLINK_ADDR_S))
+#define I2S_OUTLINK_ADDR_V  0xFFFFF
+#define I2S_OUTLINK_ADDR_S  0
+
+#define I2S_IN_LINK_REG(i)          (REG_I2S_BASE(i) + 0x0034)
+/* I2S_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define I2S_INLINK_PARK  (BIT(31))
+#define I2S_INLINK_PARK_M  (BIT(31))
+#define I2S_INLINK_PARK_V  0x1
+#define I2S_INLINK_PARK_S  31
+/* I2S_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to restart inlink descriptor*/
+#define I2S_INLINK_RESTART  (BIT(30))
+#define I2S_INLINK_RESTART_M  (BIT(30))
+#define I2S_INLINK_RESTART_V  0x1
+#define I2S_INLINK_RESTART_S  30
+/* I2S_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to start inlink descriptor*/
+#define I2S_INLINK_START  (BIT(29))
+#define I2S_INLINK_START_M  (BIT(29))
+#define I2S_INLINK_START_V  0x1
+#define I2S_INLINK_START_S  29
+/* I2S_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to stop inlink descriptor*/
+#define I2S_INLINK_STOP  (BIT(28))
+#define I2S_INLINK_STOP_M  (BIT(28))
+#define I2S_INLINK_STOP_V  0x1
+#define I2S_INLINK_STOP_S  28
+/* I2S_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of first inlink descriptor*/
+#define I2S_INLINK_ADDR  0x000FFFFF
+#define I2S_INLINK_ADDR_M  ((I2S_INLINK_ADDR_V)<<(I2S_INLINK_ADDR_S))
+#define I2S_INLINK_ADDR_V  0xFFFFF
+#define I2S_INLINK_ADDR_S  0
+
+#define I2S_OUT_EOF_DES_ADDR_REG(i)          (REG_I2S_BASE(i) + 0x0038)
+/* I2S_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The address of outlink descriptor that produces EOF*/
+#define I2S_OUT_EOF_DES_ADDR  0xFFFFFFFF
+#define I2S_OUT_EOF_DES_ADDR_M  ((I2S_OUT_EOF_DES_ADDR_V)<<(I2S_OUT_EOF_DES_ADDR_S))
+#define I2S_OUT_EOF_DES_ADDR_V  0xFFFFFFFF
+#define I2S_OUT_EOF_DES_ADDR_S  0
+
+#define I2S_IN_EOF_DES_ADDR_REG(i)          (REG_I2S_BASE(i) + 0x003c)
+/* I2S_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The address of inlink descriptor that produces EOF*/
+#define I2S_IN_SUC_EOF_DES_ADDR  0xFFFFFFFF
+#define I2S_IN_SUC_EOF_DES_ADDR_M  ((I2S_IN_SUC_EOF_DES_ADDR_V)<<(I2S_IN_SUC_EOF_DES_ADDR_S))
+#define I2S_IN_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
+#define I2S_IN_SUC_EOF_DES_ADDR_S  0
+
+#define I2S_OUT_EOF_BFR_DES_ADDR_REG(i)          (REG_I2S_BASE(i) + 0x0040)
+/* I2S_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: The address of buffer relative to the outlink descriptor that produces EOF*/
+#define I2S_OUT_EOF_BFR_DES_ADDR  0xFFFFFFFF
+#define I2S_OUT_EOF_BFR_DES_ADDR_M  ((I2S_OUT_EOF_BFR_DES_ADDR_V)<<(I2S_OUT_EOF_BFR_DES_ADDR_S))
+#define I2S_OUT_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
+#define I2S_OUT_EOF_BFR_DES_ADDR_S  0
+
+#define I2S_AHB_TEST_REG(i)          (REG_I2S_BASE(i) + 0x0044)
+/* I2S_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define I2S_AHB_TESTADDR  0x00000003
+#define I2S_AHB_TESTADDR_M  ((I2S_AHB_TESTADDR_V)<<(I2S_AHB_TESTADDR_S))
+#define I2S_AHB_TESTADDR_V  0x3
+#define I2S_AHB_TESTADDR_S  4
+/* I2S_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define I2S_AHB_TESTMODE  0x00000007
+#define I2S_AHB_TESTMODE_M  ((I2S_AHB_TESTMODE_V)<<(I2S_AHB_TESTMODE_S))
+#define I2S_AHB_TESTMODE_V  0x7
+#define I2S_AHB_TESTMODE_S  0
+
+#define I2S_INLINK_DSCR_REG(i)          (REG_I2S_BASE(i) + 0x0048)
+/* I2S_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of current inlink descriptor*/
+#define I2S_INLINK_DSCR  0xFFFFFFFF
+#define I2S_INLINK_DSCR_M  ((I2S_INLINK_DSCR_V)<<(I2S_INLINK_DSCR_S))
+#define I2S_INLINK_DSCR_V  0xFFFFFFFF
+#define I2S_INLINK_DSCR_S  0
+
+#define I2S_INLINK_DSCR_BF0_REG(i)          (REG_I2S_BASE(i) + 0x004C)
+/* I2S_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of next inlink descriptor*/
+#define I2S_INLINK_DSCR_BF0  0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF0_M  ((I2S_INLINK_DSCR_BF0_V)<<(I2S_INLINK_DSCR_BF0_S))
+#define I2S_INLINK_DSCR_BF0_V  0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF0_S  0
+
+#define I2S_INLINK_DSCR_BF1_REG(i)          (REG_I2S_BASE(i) + 0x0050)
+/* I2S_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of next inlink data buffer*/
+#define I2S_INLINK_DSCR_BF1  0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF1_M  ((I2S_INLINK_DSCR_BF1_V)<<(I2S_INLINK_DSCR_BF1_S))
+#define I2S_INLINK_DSCR_BF1_V  0xFFFFFFFF
+#define I2S_INLINK_DSCR_BF1_S  0
+
+#define I2S_OUTLINK_DSCR_REG(i)          (REG_I2S_BASE(i) + 0x0054)
+/* I2S_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of current outlink descriptor*/
+#define I2S_OUTLINK_DSCR  0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_M  ((I2S_OUTLINK_DSCR_V)<<(I2S_OUTLINK_DSCR_S))
+#define I2S_OUTLINK_DSCR_V  0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_S  0
+
+#define I2S_OUTLINK_DSCR_BF0_REG(i)          (REG_I2S_BASE(i) + 0x0058)
+/* I2S_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of next outlink descriptor*/
+#define I2S_OUTLINK_DSCR_BF0  0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF0_M  ((I2S_OUTLINK_DSCR_BF0_V)<<(I2S_OUTLINK_DSCR_BF0_S))
+#define I2S_OUTLINK_DSCR_BF0_V  0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF0_S  0
+
+#define I2S_OUTLINK_DSCR_BF1_REG(i)          (REG_I2S_BASE(i) + 0x005C)
+/* I2S_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of next outlink data buffer*/
+#define I2S_OUTLINK_DSCR_BF1  0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF1_M  ((I2S_OUTLINK_DSCR_BF1_V)<<(I2S_OUTLINK_DSCR_BF1_S))
+#define I2S_OUTLINK_DSCR_BF1_V  0xFFFFFFFF
+#define I2S_OUTLINK_DSCR_BF1_S  0
+
+#define I2S_LC_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0060)
+/* I2S_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_MEM_TRANS_EN  (BIT(13))
+#define I2S_MEM_TRANS_EN_M  (BIT(13))
+#define I2S_MEM_TRANS_EN_V  0x1
+#define I2S_MEM_TRANS_EN_S  13
+/* I2S_CHECK_OWNER : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable check owner bit by hardware*/
+#define I2S_CHECK_OWNER  (BIT(12))
+#define I2S_CHECK_OWNER_M  (BIT(12))
+#define I2S_CHECK_OWNER_V  0x1
+#define I2S_CHECK_OWNER_S  12
+/* I2S_OUT_DATA_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Transmitter data transfer mode configuration bit. 1:  to prepare
+ out data with burst mode      0: to prepare out data with byte mode*/
+#define I2S_OUT_DATA_BURST_EN  (BIT(11))
+#define I2S_OUT_DATA_BURST_EN_M  (BIT(11))
+#define I2S_OUT_DATA_BURST_EN_V  0x1
+#define I2S_OUT_DATA_BURST_EN_S  11
+/* I2S_INDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: DMA inlink descriptor transfer mode configuration bit. 1:  to
+ prepare inlink descriptor with burst mode    0: to prepare inlink descriptor with byte mode*/
+#define I2S_INDSCR_BURST_EN  (BIT(10))
+#define I2S_INDSCR_BURST_EN_M  (BIT(10))
+#define I2S_INDSCR_BURST_EN_V  0x1
+#define I2S_INDSCR_BURST_EN_S  10
+/* I2S_OUTDSCR_BURST_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: DMA outlink descriptor transfer mode configuration bit. 1:  to
+ prepare outlink descriptor with burst mode    0: to prepare outlink descriptor with byte mode*/
+#define I2S_OUTDSCR_BURST_EN  (BIT(9))
+#define I2S_OUTDSCR_BURST_EN_M  (BIT(9))
+#define I2S_OUTDSCR_BURST_EN_V  0x1
+#define I2S_OUTDSCR_BURST_EN_S  9
+/* I2S_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: DMA out EOF flag generation mode . 1: when dma has popped all
+ data from the FIFO  0:when ahb has pushed all data to the FIFO*/
+#define I2S_OUT_EOF_MODE  (BIT(8))
+#define I2S_OUT_EOF_MODE_M  (BIT(8))
+#define I2S_OUT_EOF_MODE_V  0x1
+#define I2S_OUT_EOF_MODE_S  8
+/* I2S_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_OUT_NO_RESTART_CLR  (BIT(7))
+#define I2S_OUT_NO_RESTART_CLR_M  (BIT(7))
+#define I2S_OUT_NO_RESTART_CLR_V  0x1
+#define I2S_OUT_NO_RESTART_CLR_S  7
+/* I2S_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to enable outlink-written-back automatically when
+ out buffer is transmitted done.*/
+#define I2S_OUT_AUTO_WRBACK  (BIT(6))
+#define I2S_OUT_AUTO_WRBACK_M  (BIT(6))
+#define I2S_OUT_AUTO_WRBACK_V  0x1
+#define I2S_OUT_AUTO_WRBACK_S  6
+/* I2S_IN_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to loop test outlink*/
+#define I2S_IN_LOOP_TEST  (BIT(5))
+#define I2S_IN_LOOP_TEST_M  (BIT(5))
+#define I2S_IN_LOOP_TEST_V  0x1
+#define I2S_IN_LOOP_TEST_S  5
+/* I2S_OUT_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to loop test inlink*/
+#define I2S_OUT_LOOP_TEST  (BIT(4))
+#define I2S_OUT_LOOP_TEST_M  (BIT(4))
+#define I2S_OUT_LOOP_TEST_V  0x1
+#define I2S_OUT_LOOP_TEST_S  4
+/* I2S_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset ahb interface of DMA*/
+#define I2S_AHBM_RST  (BIT(3))
+#define I2S_AHBM_RST_M  (BIT(3))
+#define I2S_AHBM_RST_V  0x1
+#define I2S_AHBM_RST_S  3
+/* I2S_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to reset ahb interface cmdFIFO of DMA*/
+#define I2S_AHBM_FIFO_RST  (BIT(2))
+#define I2S_AHBM_FIFO_RST_M  (BIT(2))
+#define I2S_AHBM_FIFO_RST_V  0x1
+#define I2S_AHBM_FIFO_RST_S  2
+/* I2S_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to reset out dma FSM*/
+#define I2S_OUT_RST  (BIT(1))
+#define I2S_OUT_RST_M  (BIT(1))
+#define I2S_OUT_RST_V  0x1
+#define I2S_OUT_RST_S  1
+/* I2S_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to reset in dma FSM*/
+#define I2S_IN_RST  (BIT(0))
+#define I2S_IN_RST_M  (BIT(0))
+#define I2S_IN_RST_V  0x1
+#define I2S_IN_RST_S  0
+
+#define I2S_OUTFIFO_PUSH_REG(i)          (REG_I2S_BASE(i) + 0x0064)
+/* I2S_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define I2S_OUTFIFO_PUSH  (BIT(16))
+#define I2S_OUTFIFO_PUSH_M  (BIT(16))
+#define I2S_OUTFIFO_PUSH_V  0x1
+#define I2S_OUTFIFO_PUSH_S  16
+/* I2S_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define I2S_OUTFIFO_WDATA  0x000001FF
+#define I2S_OUTFIFO_WDATA_M  ((I2S_OUTFIFO_WDATA_V)<<(I2S_OUTFIFO_WDATA_S))
+#define I2S_OUTFIFO_WDATA_V  0x1FF
+#define I2S_OUTFIFO_WDATA_S  0
+
+#define I2S_INFIFO_POP_REG(i)          (REG_I2S_BASE(i) + 0x0068)
+/* I2S_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define I2S_INFIFO_POP  (BIT(16))
+#define I2S_INFIFO_POP_M  (BIT(16))
+#define I2S_INFIFO_POP_V  0x1
+#define I2S_INFIFO_POP_S  16
+/* I2S_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define I2S_INFIFO_RDATA  0x00000FFF
+#define I2S_INFIFO_RDATA_M  ((I2S_INFIFO_RDATA_V)<<(I2S_INFIFO_RDATA_S))
+#define I2S_INFIFO_RDATA_V  0xFFF
+#define I2S_INFIFO_RDATA_S  0
+
+#define I2S_LC_STATE0_REG(i)          (REG_I2S_BASE(i) + 0x006C)
+/* I2S_OUT_EMPTY : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: DMA transmitter status register*/
+#define I2S_OUT_EMPTY  (BIT(31))
+#define I2S_OUT_EMPTY_M  (BIT(31))
+#define I2S_OUT_EMPTY_V  0x1
+#define I2S_OUT_EMPTY_S  31
+/* I2S_OUT_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define I2S_OUT_FULL  (BIT(30))
+#define I2S_OUT_FULL_M  (BIT(30))
+#define I2S_OUT_FULL_V  0x1
+#define I2S_OUT_FULL_S  30
+/* I2S_OUTFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */
+/*description: */
+#define I2S_OUTFIFO_CNT  0x0000007F
+#define I2S_OUTFIFO_CNT_M  ((I2S_OUTFIFO_CNT_V)<<(I2S_OUTFIFO_CNT_S))
+#define I2S_OUTFIFO_CNT_V  0x7F
+#define I2S_OUTFIFO_CNT_S  23
+/* I2S_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define I2S_OUT_STATE  0x00000007
+#define I2S_OUT_STATE_M  ((I2S_OUT_STATE_V)<<(I2S_OUT_STATE_S))
+#define I2S_OUT_STATE_V  0x7
+#define I2S_OUT_STATE_S  20
+/* I2S_OUT_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: */
+#define I2S_OUT_DSCR_STATE  0x00000003
+#define I2S_OUT_DSCR_STATE_M  ((I2S_OUT_DSCR_STATE_V)<<(I2S_OUT_DSCR_STATE_S))
+#define I2S_OUT_DSCR_STATE_V  0x3
+#define I2S_OUT_DSCR_STATE_S  18
+/* I2S_OUTLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: */
+#define I2S_OUTLINK_DSCR_ADDR  0x0003FFFF
+#define I2S_OUTLINK_DSCR_ADDR_M  ((I2S_OUTLINK_DSCR_ADDR_V)<<(I2S_OUTLINK_DSCR_ADDR_S))
+#define I2S_OUTLINK_DSCR_ADDR_V  0x3FFFF
+#define I2S_OUTLINK_DSCR_ADDR_S  0
+
+#define I2S_LC_STATE1_REG(i)          (REG_I2S_BASE(i) + 0x0070)
+/* I2S_IN_EMPTY : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: DMA receiver status register*/
+#define I2S_IN_EMPTY  (BIT(31))
+#define I2S_IN_EMPTY_M  (BIT(31))
+#define I2S_IN_EMPTY_V  0x1
+#define I2S_IN_EMPTY_S  31
+/* I2S_IN_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define I2S_IN_FULL  (BIT(30))
+#define I2S_IN_FULL_M  (BIT(30))
+#define I2S_IN_FULL_V  0x1
+#define I2S_IN_FULL_S  30
+/* I2S_INFIFO_CNT_DEBUG : RO ;bitpos:[29:23] ;default: 7'b0 ; */
+/*description: */
+#define I2S_INFIFO_CNT_DEBUG  0x0000007F
+#define I2S_INFIFO_CNT_DEBUG_M  ((I2S_INFIFO_CNT_DEBUG_V)<<(I2S_INFIFO_CNT_DEBUG_S))
+#define I2S_INFIFO_CNT_DEBUG_V  0x7F
+#define I2S_INFIFO_CNT_DEBUG_S  23
+/* I2S_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define I2S_IN_STATE  0x00000007
+#define I2S_IN_STATE_M  ((I2S_IN_STATE_V)<<(I2S_IN_STATE_S))
+#define I2S_IN_STATE_V  0x7
+#define I2S_IN_STATE_S  20
+/* I2S_IN_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: */
+#define I2S_IN_DSCR_STATE  0x00000003
+#define I2S_IN_DSCR_STATE_M  ((I2S_IN_DSCR_STATE_V)<<(I2S_IN_DSCR_STATE_S))
+#define I2S_IN_DSCR_STATE_V  0x3
+#define I2S_IN_DSCR_STATE_S  18
+/* I2S_INLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: */
+#define I2S_INLINK_DSCR_ADDR  0x0003FFFF
+#define I2S_INLINK_DSCR_ADDR_M  ((I2S_INLINK_DSCR_ADDR_V)<<(I2S_INLINK_DSCR_ADDR_S))
+#define I2S_INLINK_DSCR_ADDR_V  0x3FFFF
+#define I2S_INLINK_DSCR_ADDR_S  0
+
+#define I2S_LC_HUNG_CONF_REG(i)          (REG_I2S_BASE(i) + 0x0074)
+/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: The enable bit for FIFO timeout*/
+#define I2S_LC_FIFO_TIMEOUT_ENA  (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_M  (BIT(11))
+#define I2S_LC_FIFO_TIMEOUT_ENA_V  0x1
+#define I2S_LC_FIFO_TIMEOUT_ENA_S  11
+/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: The bits are used to scale tick counter threshold. The tick counter
+ is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+#define I2S_LC_FIFO_TIMEOUT_SHIFT  0x00000007
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_M  ((I2S_LC_FIFO_TIMEOUT_SHIFT_V)<<(I2S_LC_FIFO_TIMEOUT_SHIFT_S))
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_V  0x7
+#define I2S_LC_FIFO_TIMEOUT_SHIFT_S  8
+/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt
+ will be triggered when fifo hung counter is equal to this value*/
+#define I2S_LC_FIFO_TIMEOUT  0x000000FF
+#define I2S_LC_FIFO_TIMEOUT_M  ((I2S_LC_FIFO_TIMEOUT_V)<<(I2S_LC_FIFO_TIMEOUT_S))
+#define I2S_LC_FIFO_TIMEOUT_V  0xFF
+#define I2S_LC_FIFO_TIMEOUT_S  0
+
+#define I2S_CVSD_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x0080)
+/* I2S_CVSD_Y_MIN : R/W ;bitpos:[31:16] ;default: 16'h8000 ; */
+/*description: don't use*/
+#define I2S_CVSD_Y_MIN  0x0000FFFF
+#define I2S_CVSD_Y_MIN_M  ((I2S_CVSD_Y_MIN_V)<<(I2S_CVSD_Y_MIN_S))
+#define I2S_CVSD_Y_MIN_V  0xFFFF
+#define I2S_CVSD_Y_MIN_S  16
+/* I2S_CVSD_Y_MAX : R/W ;bitpos:[15:0] ;default: 16'h7fff ; */
+/*description: don't use*/
+#define I2S_CVSD_Y_MAX  0x0000FFFF
+#define I2S_CVSD_Y_MAX_M  ((I2S_CVSD_Y_MAX_V)<<(I2S_CVSD_Y_MAX_S))
+#define I2S_CVSD_Y_MAX_V  0xFFFF
+#define I2S_CVSD_Y_MAX_S  0
+
+#define I2S_CVSD_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x0084)
+/* I2S_CVSD_SIGMA_MIN : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
+/*description: don't use*/
+#define I2S_CVSD_SIGMA_MIN  0x0000FFFF
+#define I2S_CVSD_SIGMA_MIN_M  ((I2S_CVSD_SIGMA_MIN_V)<<(I2S_CVSD_SIGMA_MIN_S))
+#define I2S_CVSD_SIGMA_MIN_V  0xFFFF
+#define I2S_CVSD_SIGMA_MIN_S  16
+/* I2S_CVSD_SIGMA_MAX : R/W ;bitpos:[15:0] ;default: 16'd1280 ; */
+/*description: don't use*/
+#define I2S_CVSD_SIGMA_MAX  0x0000FFFF
+#define I2S_CVSD_SIGMA_MAX_M  ((I2S_CVSD_SIGMA_MAX_V)<<(I2S_CVSD_SIGMA_MAX_S))
+#define I2S_CVSD_SIGMA_MAX_V  0xFFFF
+#define I2S_CVSD_SIGMA_MAX_S  0
+
+#define I2S_CVSD_CONF2_REG(i)          (REG_I2S_BASE(i) + 0x0088)
+/* I2S_CVSD_H : R/W ;bitpos:[18:16] ;default: 3'd5 ; */
+/*description: don't use*/
+#define I2S_CVSD_H  0x00000007
+#define I2S_CVSD_H_M  ((I2S_CVSD_H_V)<<(I2S_CVSD_H_S))
+#define I2S_CVSD_H_V  0x7
+#define I2S_CVSD_H_S  16
+/* I2S_CVSD_BETA : R/W ;bitpos:[15:6] ;default: 10'd10 ; */
+/*description: don't use*/
+#define I2S_CVSD_BETA  0x000003FF
+#define I2S_CVSD_BETA_M  ((I2S_CVSD_BETA_V)<<(I2S_CVSD_BETA_S))
+#define I2S_CVSD_BETA_V  0x3FF
+#define I2S_CVSD_BETA_S  6
+/* I2S_CVSD_J : R/W ;bitpos:[5:3] ;default: 3'h4 ; */
+/*description: don't use*/
+#define I2S_CVSD_J  0x00000007
+#define I2S_CVSD_J_M  ((I2S_CVSD_J_V)<<(I2S_CVSD_J_S))
+#define I2S_CVSD_J_V  0x7
+#define I2S_CVSD_J_S  3
+/* I2S_CVSD_K : R/W ;bitpos:[2:0] ;default: 3'h4 ; */
+/*description: don't use*/
+#define I2S_CVSD_K  0x00000007
+#define I2S_CVSD_K_M  ((I2S_CVSD_K_V)<<(I2S_CVSD_K_S))
+#define I2S_CVSD_K_V  0x7
+#define I2S_CVSD_K_S  0
+
+#define I2S_PLC_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x008C)
+/* I2S_N_MIN_ERR : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
+/*description: don't use*/
+#define I2S_N_MIN_ERR  0x00000007
+#define I2S_N_MIN_ERR_M  ((I2S_N_MIN_ERR_V)<<(I2S_N_MIN_ERR_S))
+#define I2S_N_MIN_ERR_V  0x7
+#define I2S_N_MIN_ERR_S  25
+/* I2S_PACK_LEN_8K : R/W ;bitpos:[24:20] ;default: 5'd10 ; */
+/*description: don't use*/
+#define I2S_PACK_LEN_8K  0x0000001F
+#define I2S_PACK_LEN_8K_M  ((I2S_PACK_LEN_8K_V)<<(I2S_PACK_LEN_8K_S))
+#define I2S_PACK_LEN_8K_V  0x1F
+#define I2S_PACK_LEN_8K_S  20
+/* I2S_MAX_SLIDE_SAMPLE : R/W ;bitpos:[19:12] ;default: 8'd128 ; */
+/*description: don't use*/
+#define I2S_MAX_SLIDE_SAMPLE  0x000000FF
+#define I2S_MAX_SLIDE_SAMPLE_M  ((I2S_MAX_SLIDE_SAMPLE_V)<<(I2S_MAX_SLIDE_SAMPLE_S))
+#define I2S_MAX_SLIDE_SAMPLE_V  0xFF
+#define I2S_MAX_SLIDE_SAMPLE_S  12
+/* I2S_SHIFT_RATE : R/W ;bitpos:[11:9] ;default: 3'h1 ; */
+/*description: don't use*/
+#define I2S_SHIFT_RATE  0x00000007
+#define I2S_SHIFT_RATE_M  ((I2S_SHIFT_RATE_V)<<(I2S_SHIFT_RATE_S))
+#define I2S_SHIFT_RATE_V  0x7
+#define I2S_SHIFT_RATE_S  9
+/* I2S_N_ERR_SEG : R/W ;bitpos:[8:6] ;default: 3'h4 ; */
+/*description: don't use*/
+#define I2S_N_ERR_SEG  0x00000007
+#define I2S_N_ERR_SEG_M  ((I2S_N_ERR_SEG_V)<<(I2S_N_ERR_SEG_S))
+#define I2S_N_ERR_SEG_V  0x7
+#define I2S_N_ERR_SEG_S  6
+/* I2S_GOOD_PACK_MAX : R/W ;bitpos:[5:0] ;default: 6'h39 ; */
+/*description: don't use*/
+#define I2S_GOOD_PACK_MAX  0x0000003F
+#define I2S_GOOD_PACK_MAX_M  ((I2S_GOOD_PACK_MAX_V)<<(I2S_GOOD_PACK_MAX_S))
+#define I2S_GOOD_PACK_MAX_V  0x3F
+#define I2S_GOOD_PACK_MAX_S  0
+
+#define I2S_PLC_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x0090)
+/* I2S_SLIDE_WIN_LEN : R/W ;bitpos:[31:24] ;default: 8'd160 ; */
+/*description: don't use*/
+#define I2S_SLIDE_WIN_LEN  0x000000FF
+#define I2S_SLIDE_WIN_LEN_M  ((I2S_SLIDE_WIN_LEN_V)<<(I2S_SLIDE_WIN_LEN_S))
+#define I2S_SLIDE_WIN_LEN_V  0xFF
+#define I2S_SLIDE_WIN_LEN_S  24
+/* I2S_BAD_OLA_WIN2_PARA : R/W ;bitpos:[23:16] ;default: 8'd23 ; */
+/*description: don't use*/
+#define I2S_BAD_OLA_WIN2_PARA  0x000000FF
+#define I2S_BAD_OLA_WIN2_PARA_M  ((I2S_BAD_OLA_WIN2_PARA_V)<<(I2S_BAD_OLA_WIN2_PARA_S))
+#define I2S_BAD_OLA_WIN2_PARA_V  0xFF
+#define I2S_BAD_OLA_WIN2_PARA_S  16
+/* I2S_BAD_OLA_WIN2_PARA_SHIFT : R/W ;bitpos:[15:12] ;default: 4'd8 ; */
+/*description: don't use*/
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT  0x0000000F
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT_M  ((I2S_BAD_OLA_WIN2_PARA_SHIFT_V)<<(I2S_BAD_OLA_WIN2_PARA_SHIFT_S))
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT_V  0xF
+#define I2S_BAD_OLA_WIN2_PARA_SHIFT_S  12
+/* I2S_BAD_CEF_ATTEN_PARA_SHIFT : R/W ;bitpos:[11:8] ;default: 4'd10 ; */
+/*description: don't use*/
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT  0x0000000F
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_M  ((I2S_BAD_CEF_ATTEN_PARA_SHIFT_V)<<(I2S_BAD_CEF_ATTEN_PARA_SHIFT_S))
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_V  0xF
+#define I2S_BAD_CEF_ATTEN_PARA_SHIFT_S  8
+/* I2S_BAD_CEF_ATTEN_PARA : R/W ;bitpos:[7:0] ;default: 8'd5 ; */
+/*description: don't use*/
+#define I2S_BAD_CEF_ATTEN_PARA  0x000000FF
+#define I2S_BAD_CEF_ATTEN_PARA_M  ((I2S_BAD_CEF_ATTEN_PARA_V)<<(I2S_BAD_CEF_ATTEN_PARA_S))
+#define I2S_BAD_CEF_ATTEN_PARA_V  0xFF
+#define I2S_BAD_CEF_ATTEN_PARA_S  0
+
+#define I2S_PLC_CONF2_REG(i)          (REG_I2S_BASE(i) + 0x0094)
+/* I2S_MIN_PERIOD : R/W ;bitpos:[6:2] ;default: 5'd10 ; */
+/*description: don't use*/
+#define I2S_MIN_PERIOD  0x0000001F
+#define I2S_MIN_PERIOD_M  ((I2S_MIN_PERIOD_V)<<(I2S_MIN_PERIOD_S))
+#define I2S_MIN_PERIOD_V  0x1F
+#define I2S_MIN_PERIOD_S  2
+/* I2S_CVSD_SEG_MOD : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: don't use*/
+#define I2S_CVSD_SEG_MOD  0x00000003
+#define I2S_CVSD_SEG_MOD_M  ((I2S_CVSD_SEG_MOD_V)<<(I2S_CVSD_SEG_MOD_S))
+#define I2S_CVSD_SEG_MOD_V  0x3
+#define I2S_CVSD_SEG_MOD_S  0
+
+#define I2S_ESCO_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x0098)
+/* I2S_PLC2DMA_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_PLC2DMA_EN  (BIT(12))
+#define I2S_PLC2DMA_EN_M  (BIT(12))
+#define I2S_PLC2DMA_EN_V  0x1
+#define I2S_PLC2DMA_EN_S  12
+/* I2S_PLC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_PLC_EN  (BIT(11))
+#define I2S_PLC_EN_M  (BIT(11))
+#define I2S_PLC_EN_V  0x1
+#define I2S_PLC_EN_S  11
+/* I2S_CVSD_DEC_RESET : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_CVSD_DEC_RESET  (BIT(10))
+#define I2S_CVSD_DEC_RESET_M  (BIT(10))
+#define I2S_CVSD_DEC_RESET_V  0x1
+#define I2S_CVSD_DEC_RESET_S  10
+/* I2S_CVSD_DEC_START : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_CVSD_DEC_START  (BIT(9))
+#define I2S_CVSD_DEC_START_M  (BIT(9))
+#define I2S_CVSD_DEC_START_V  0x1
+#define I2S_CVSD_DEC_START_S  9
+/* I2S_ESCO_CVSD_INF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_ESCO_CVSD_INF_EN  (BIT(8))
+#define I2S_ESCO_CVSD_INF_EN_M  (BIT(8))
+#define I2S_ESCO_CVSD_INF_EN_V  0x1
+#define I2S_ESCO_CVSD_INF_EN_S  8
+/* I2S_ESCO_CVSD_PACK_LEN_8K : R/W ;bitpos:[7:3] ;default: 5'b0 ; */
+/*description: don't use*/
+#define I2S_ESCO_CVSD_PACK_LEN_8K  0x0000001F
+#define I2S_ESCO_CVSD_PACK_LEN_8K_M  ((I2S_ESCO_CVSD_PACK_LEN_8K_V)<<(I2S_ESCO_CVSD_PACK_LEN_8K_S))
+#define I2S_ESCO_CVSD_PACK_LEN_8K_V  0x1F
+#define I2S_ESCO_CVSD_PACK_LEN_8K_S  3
+/* I2S_ESCO_CVSD_DEC_PACK_ERR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: don't use*/
+#define I2S_ESCO_CVSD_DEC_PACK_ERR  (BIT(2))
+#define I2S_ESCO_CVSD_DEC_PACK_ERR_M  (BIT(2))
+#define I2S_ESCO_CVSD_DEC_PACK_ERR_V  0x1
+#define I2S_ESCO_CVSD_DEC_PACK_ERR_S  2
+/* I2S_ESCO_CHAN_MOD : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: don't use*/
+#define I2S_ESCO_CHAN_MOD  (BIT(1))
+#define I2S_ESCO_CHAN_MOD_M  (BIT(1))
+#define I2S_ESCO_CHAN_MOD_V  0x1
+#define I2S_ESCO_CHAN_MOD_S  1
+/* I2S_ESCO_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: don't use*/
+#define I2S_ESCO_EN  (BIT(0))
+#define I2S_ESCO_EN_M  (BIT(0))
+#define I2S_ESCO_EN_V  0x1
+#define I2S_ESCO_EN_S  0
+
+#define I2S_SCO_CONF0_REG(i)          (REG_I2S_BASE(i) + 0x009c)
+/* I2S_CVSD_ENC_RESET : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: don't use*/
+#define I2S_CVSD_ENC_RESET  (BIT(3))
+#define I2S_CVSD_ENC_RESET_M  (BIT(3))
+#define I2S_CVSD_ENC_RESET_V  0x1
+#define I2S_CVSD_ENC_RESET_S  3
+/* I2S_CVSD_ENC_START : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: don't use*/
+#define I2S_CVSD_ENC_START  (BIT(2))
+#define I2S_CVSD_ENC_START_M  (BIT(2))
+#define I2S_CVSD_ENC_START_V  0x1
+#define I2S_CVSD_ENC_START_S  2
+/* I2S_SCO_NO_I2S_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: don't use*/
+#define I2S_SCO_NO_I2S_EN  (BIT(1))
+#define I2S_SCO_NO_I2S_EN_M  (BIT(1))
+#define I2S_SCO_NO_I2S_EN_V  0x1
+#define I2S_SCO_NO_I2S_EN_S  1
+/* I2S_SCO_WITH_I2S_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: don't use*/
+#define I2S_SCO_WITH_I2S_EN  (BIT(0))
+#define I2S_SCO_WITH_I2S_EN_M  (BIT(0))
+#define I2S_SCO_WITH_I2S_EN_V  0x1
+#define I2S_SCO_WITH_I2S_EN_S  0
+
+#define I2S_CONF1_REG(i)          (REG_I2S_BASE(i) + 0x00a0)
+/* I2S_TX_ZEROS_RM_EN : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: don't use*/
+#define I2S_TX_ZEROS_RM_EN  (BIT(9))
+#define I2S_TX_ZEROS_RM_EN_M  (BIT(9))
+#define I2S_TX_ZEROS_RM_EN_V  0x1
+#define I2S_TX_ZEROS_RM_EN_S  9
+/* I2S_TX_STOP_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set this bit to stop disable output BCK signal and WS signal
+ when tx FIFO is emtpy*/
+#define I2S_TX_STOP_EN  (BIT(8))
+#define I2S_TX_STOP_EN_M  (BIT(8))
+#define I2S_TX_STOP_EN_V  0x1
+#define I2S_TX_STOP_EN_S  8
+/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[7] ;default: 1'h1 ; */
+/*description: Set this bit to bypass Compress/Decompress module for received data.*/
+#define I2S_RX_PCM_BYPASS  (BIT(7))
+#define I2S_RX_PCM_BYPASS_M  (BIT(7))
+#define I2S_RX_PCM_BYPASS_V  0x1
+#define I2S_RX_PCM_BYPASS_S  7
+/* I2S_RX_PCM_CONF : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: Compress/Decompress module configuration bits. 0: decompress
+ received data  1:compress received data*/
+#define I2S_RX_PCM_CONF  0x00000007
+#define I2S_RX_PCM_CONF_M  ((I2S_RX_PCM_CONF_V)<<(I2S_RX_PCM_CONF_S))
+#define I2S_RX_PCM_CONF_V  0x7
+#define I2S_RX_PCM_CONF_S  4
+/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: Set this bit to bypass  Compress/Decompress module for transmitted data.*/
+#define I2S_TX_PCM_BYPASS  (BIT(3))
+#define I2S_TX_PCM_BYPASS_M  (BIT(3))
+#define I2S_TX_PCM_BYPASS_V  0x1
+#define I2S_TX_PCM_BYPASS_S  3
+/* I2S_TX_PCM_CONF : R/W ;bitpos:[2:0] ;default: 3'h1 ; */
+/*description: Compress/Decompress module configuration bits. 0: decompress
+ transmitted data  1:compress transmitted data*/
+#define I2S_TX_PCM_CONF  0x00000007
+#define I2S_TX_PCM_CONF_M  ((I2S_TX_PCM_CONF_V)<<(I2S_TX_PCM_CONF_S))
+#define I2S_TX_PCM_CONF_V  0x7
+#define I2S_TX_PCM_CONF_S  0
+
+#define I2S_PD_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00a4)
+/* I2S_PLC_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'h1 ; */
+/*description: */
+#define I2S_PLC_MEM_FORCE_PU  (BIT(3))
+#define I2S_PLC_MEM_FORCE_PU_M  (BIT(3))
+#define I2S_PLC_MEM_FORCE_PU_V  0x1
+#define I2S_PLC_MEM_FORCE_PU_S  3
+/* I2S_PLC_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define I2S_PLC_MEM_FORCE_PD  (BIT(2))
+#define I2S_PLC_MEM_FORCE_PD_M  (BIT(2))
+#define I2S_PLC_MEM_FORCE_PD_V  0x1
+#define I2S_PLC_MEM_FORCE_PD_S  2
+/* I2S_FIFO_FORCE_PU : R/W ;bitpos:[1] ;default: 1'h1 ; */
+/*description: Force FIFO power-up*/
+#define I2S_FIFO_FORCE_PU  (BIT(1))
+#define I2S_FIFO_FORCE_PU_M  (BIT(1))
+#define I2S_FIFO_FORCE_PU_V  0x1
+#define I2S_FIFO_FORCE_PU_S  1
+/* I2S_FIFO_FORCE_PD : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Force FIFO power-down*/
+#define I2S_FIFO_FORCE_PD  (BIT(0))
+#define I2S_FIFO_FORCE_PD_M  (BIT(0))
+#define I2S_FIFO_FORCE_PD_V  0x1
+#define I2S_FIFO_FORCE_PD_S  0
+
+#define I2S_CONF2_REG(i)          (REG_I2S_BASE(i) + 0x00a8)
+/* I2S_I2SI_V_SYNC_FILTER_THRES : R/W ;bitpos:[13:11] ;default: 3'b0 ; */
+/*description: */
+#define I2S_I2SI_V_SYNC_FILTER_THRES  0x00000007
+#define I2S_I2SI_V_SYNC_FILTER_THRES_M  ((I2S_I2SI_V_SYNC_FILTER_THRES_V)<<(I2S_I2SI_V_SYNC_FILTER_THRES_S))
+#define I2S_I2SI_V_SYNC_FILTER_THRES_V  0x7
+#define I2S_I2SI_V_SYNC_FILTER_THRES_S  11
+/* I2S_I2SI_V_SYNC_FILTER_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define I2S_I2SI_V_SYNC_FILTER_EN  (BIT(10))
+#define I2S_I2SI_V_SYNC_FILTER_EN_M  (BIT(10))
+#define I2S_I2SI_V_SYNC_FILTER_EN_V  0x1
+#define I2S_I2SI_V_SYNC_FILTER_EN_S  10
+/* I2S_CAM_CLK_LOOPBACK : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to loopback cam_clk from i2s_rx*/
+#define I2S_CAM_CLK_LOOPBACK  (BIT(9))
+#define I2S_CAM_CLK_LOOPBACK_M  (BIT(9))
+#define I2S_CAM_CLK_LOOPBACK_V  0x1
+#define I2S_CAM_CLK_LOOPBACK_S  9
+/* I2S_CAM_SYNC_FIFO_RESET : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to reset cam_sync_fifo*/
+#define I2S_CAM_SYNC_FIFO_RESET  (BIT(8))
+#define I2S_CAM_SYNC_FIFO_RESET_M  (BIT(8))
+#define I2S_CAM_SYNC_FIFO_RESET_V  0x1
+#define I2S_CAM_SYNC_FIFO_RESET_S  8
+/* I2S_INTER_VALID_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable camera internal valid*/
+#define I2S_INTER_VALID_EN  (BIT(7))
+#define I2S_INTER_VALID_EN_M  (BIT(7))
+#define I2S_INTER_VALID_EN_V  0x1
+#define I2S_INTER_VALID_EN_S  7
+/* I2S_EXT_ADC_START_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to enable the function that ADC mode is triggered
+ by external signal.*/
+#define I2S_EXT_ADC_START_EN  (BIT(6))
+#define I2S_EXT_ADC_START_EN_M  (BIT(6))
+#define I2S_EXT_ADC_START_EN_V  0x1
+#define I2S_EXT_ADC_START_EN_S  6
+/* I2S_LCD_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable LCD mode*/
+#define I2S_LCD_EN  (BIT(5))
+#define I2S_LCD_EN_M  (BIT(5))
+#define I2S_LCD_EN_V  0x1
+#define I2S_LCD_EN_S  5
+/* I2S_DATA_ENABLE : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: for debug camera mode enable*/
+#define I2S_DATA_ENABLE  (BIT(4))
+#define I2S_DATA_ENABLE_M  (BIT(4))
+#define I2S_DATA_ENABLE_V  0x1
+#define I2S_DATA_ENABLE_S  4
+/* I2S_DATA_ENABLE_TEST_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: for debug camera mode enable*/
+#define I2S_DATA_ENABLE_TEST_EN  (BIT(3))
+#define I2S_DATA_ENABLE_TEST_EN_M  (BIT(3))
+#define I2S_DATA_ENABLE_TEST_EN_V  0x1
+#define I2S_DATA_ENABLE_TEST_EN_S  3
+/* I2S_LCD_TX_SDX2_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
+#define I2S_LCD_TX_SDX2_EN  (BIT(2))
+#define I2S_LCD_TX_SDX2_EN_M  (BIT(2))
+#define I2S_LCD_TX_SDX2_EN_V  0x1
+#define I2S_LCD_TX_SDX2_EN_S  2
+/* I2S_LCD_TX_WRX2_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: LCD WR double for one datum.*/
+#define I2S_LCD_TX_WRX2_EN  (BIT(1))
+#define I2S_LCD_TX_WRX2_EN_M  (BIT(1))
+#define I2S_LCD_TX_WRX2_EN_V  0x1
+#define I2S_LCD_TX_WRX2_EN_S  1
+/* I2S_CAMERA_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to enable camera mode*/
+#define I2S_CAMERA_EN  (BIT(0))
+#define I2S_CAMERA_EN_M  (BIT(0))
+#define I2S_CAMERA_EN_V  0x1
+#define I2S_CAMERA_EN_S  0
+
+#define I2S_CLKM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00ac)
+/* I2S_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
+/*description: Set this bit to enable clk_apll*/
+#define I2S_CLK_SEL  0x00000003
+#define I2S_CLK_SEL_M  ((I2S_CLK_SEL_V)<<(I2S_CLK_SEL_S))
+#define I2S_CLK_SEL_V  0x3
+#define I2S_CLK_SEL_S  21
+#define I2S_CLK_AUDIO_PLL 1
+#define I2S_CLK_160M_PLL 2
+/* I2S_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to enable clk gate*/
+#define I2S_CLK_EN  (BIT(20))
+#define I2S_CLK_EN_M  (BIT(20))
+#define I2S_CLK_EN_V  0x1
+#define I2S_CLK_EN_S  20
+/* I2S_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
+/*description: Fractional clock divider denominator value*/
+#define I2S_CLKM_DIV_A  0x0000003F
+#define I2S_CLKM_DIV_A_M  ((I2S_CLKM_DIV_A_V)<<(I2S_CLKM_DIV_A_S))
+#define I2S_CLKM_DIV_A_V  0x3F
+#define I2S_CLKM_DIV_A_S  14
+/* I2S_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
+/*description: Fractional clock divider numerator value*/
+#define I2S_CLKM_DIV_B  0x0000003F
+#define I2S_CLKM_DIV_B_M  ((I2S_CLKM_DIV_B_V)<<(I2S_CLKM_DIV_B_S))
+#define I2S_CLKM_DIV_B_V  0x3F
+#define I2S_CLKM_DIV_B_S  8
+/* I2S_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
+/*description: Integral I2S clock divider value*/
+#define I2S_CLKM_DIV_NUM  0x000000FF
+#define I2S_CLKM_DIV_NUM_M  ((I2S_CLKM_DIV_NUM_V)<<(I2S_CLKM_DIV_NUM_S))
+#define I2S_CLKM_DIV_NUM_V  0xFF
+#define I2S_CLKM_DIV_NUM_S  0
+
+#define I2S_SAMPLE_RATE_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00b0)
+/* I2S_RX_BITS_MOD : R/W ;bitpos:[23:18] ;default: 6'd16 ; */
+/*description: Set the bits to configure bit length of I2S receiver channel.*/
+#define I2S_RX_BITS_MOD  0x0000003F
+#define I2S_RX_BITS_MOD_M  ((I2S_RX_BITS_MOD_V)<<(I2S_RX_BITS_MOD_S))
+#define I2S_RX_BITS_MOD_V  0x3F
+#define I2S_RX_BITS_MOD_S  18
+/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:12] ;default: 6'd16 ; */
+/*description: Set the bits to configure bit length of I2S transmitter channel.*/
+#define I2S_TX_BITS_MOD  0x0000003F
+#define I2S_TX_BITS_MOD_M  ((I2S_TX_BITS_MOD_V)<<(I2S_TX_BITS_MOD_S))
+#define I2S_TX_BITS_MOD_V  0x3F
+#define I2S_TX_BITS_MOD_S  12
+/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[11:6] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in receiver mode.*/
+#define I2S_RX_BCK_DIV_NUM  0x0000003F
+#define I2S_RX_BCK_DIV_NUM_M  ((I2S_RX_BCK_DIV_NUM_V)<<(I2S_RX_BCK_DIV_NUM_S))
+#define I2S_RX_BCK_DIV_NUM_V  0x3F
+#define I2S_RX_BCK_DIV_NUM_S  6
+/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[5:0] ;default: 6'd6 ; */
+/*description: Bit clock configuration bits in transmitter mode.*/
+#define I2S_TX_BCK_DIV_NUM  0x0000003F
+#define I2S_TX_BCK_DIV_NUM_M  ((I2S_TX_BCK_DIV_NUM_V)<<(I2S_TX_BCK_DIV_NUM_S))
+#define I2S_TX_BCK_DIV_NUM_V  0x3F
+#define I2S_TX_BCK_DIV_NUM_S  0
+
+#define I2S_PDM_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00b4)
+/* I2S_RX_PDM_WAY_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
+/*description: 0/1 pdm rx use one-way*/
+#define I2S_RX_PDM_WAY_MODE  0x00000003
+#define I2S_RX_PDM_WAY_MODE_M  ((I2S_RX_PDM_WAY_MODE_V)<<(I2S_RX_PDM_WAY_MODE_S))
+#define I2S_RX_PDM_WAY_MODE_V  0x3
+#define I2S_RX_PDM_WAY_MODE_S  30
+/* I2S_TX_PDM_WAY_MODE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */
+/*description: 0/1 pdm rx use one-way*/
+#define I2S_TX_PDM_WAY_MODE  0x00000003
+#define I2S_TX_PDM_WAY_MODE_M  ((I2S_TX_PDM_WAY_MODE_V)<<(I2S_TX_PDM_WAY_MODE_S))
+#define I2S_TX_PDM_WAY_MODE_V  0x3
+#define I2S_TX_PDM_WAY_MODE_S  28
+/* I2S_TX_PDM_CHAN_MOD : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
+/*description: pdm tx channel mode*/
+#define I2S_TX_PDM_CHAN_MOD  0x00000003
+#define I2S_TX_PDM_CHAN_MOD_M  ((I2S_TX_PDM_CHAN_MOD_V)<<(I2S_TX_PDM_CHAN_MOD_S))
+#define I2S_TX_PDM_CHAN_MOD_V  0x3
+#define I2S_TX_PDM_CHAN_MOD_S  26
+/* I2S_TX_PDM_HP_BYPASS : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: Set this bit to enable tx pdm hp filter bypass*/
+#define I2S_TX_PDM_HP_BYPASS  (BIT(25))
+#define I2S_TX_PDM_HP_BYPASS_M  (BIT(25))
+#define I2S_TX_PDM_HP_BYPASS_V  0x1
+#define I2S_TX_PDM_HP_BYPASS_S  25
+/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[24] ;default: 1'h1 ; */
+/*description: PDM down-sampling rate for filter group1 in receiver mode. 0:
+ downsample rate = 64  1:downsample rate = 128*/
+#define I2S_RX_PDM_SINC_DSR_16_EN  (BIT(24))
+#define I2S_RX_PDM_SINC_DSR_16_EN_M  (BIT(24))
+#define I2S_RX_PDM_SINC_DSR_16_EN_V  0x1
+#define I2S_RX_PDM_SINC_DSR_16_EN_S  24
+/* I2S_TX_PDM_SIGMADELTA_IN_SHIFT : R/W ;bitpos:[23:22] ;default: 2'h1 ; */
+/*description: Adjust size of input signal to filter module. 0: divided by 2
+  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT  0x00000003
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_M  ((I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V)<<(I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S))
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SIGMADELTA_IN_SHIFT_S  22
+/* I2S_TX_PDM_SINC_IN_SHIFT : R/W ;bitpos:[21:20] ;default: 2'h1 ; */
+/*description: Adjust size of input signal to filter module. 0: divided by 2
+  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+#define I2S_TX_PDM_SINC_IN_SHIFT  0x00000003
+#define I2S_TX_PDM_SINC_IN_SHIFT_M  ((I2S_TX_PDM_SINC_IN_SHIFT_V)<<(I2S_TX_PDM_SINC_IN_SHIFT_S))
+#define I2S_TX_PDM_SINC_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_SINC_IN_SHIFT_S  20
+/* I2S_TX_PDM_LP_IN_SHIFT : R/W ;bitpos:[19:18] ;default: 2'h1 ; */
+/*description: Adjust size of input signal to filter module. 0: divided by 2
+  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+#define I2S_TX_PDM_LP_IN_SHIFT  0x00000003
+#define I2S_TX_PDM_LP_IN_SHIFT_M  ((I2S_TX_PDM_LP_IN_SHIFT_V)<<(I2S_TX_PDM_LP_IN_SHIFT_S))
+#define I2S_TX_PDM_LP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_LP_IN_SHIFT_S  18
+/* I2S_TX_PDM_HP_IN_SHIFT : R/W ;bitpos:[17:16] ;default: 2'h1 ; */
+/*description: Adjust size of input signal to filter module. 0: divided by 2
+  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+#define I2S_TX_PDM_HP_IN_SHIFT  0x00000003
+#define I2S_TX_PDM_HP_IN_SHIFT_M  ((I2S_TX_PDM_HP_IN_SHIFT_V)<<(I2S_TX_PDM_HP_IN_SHIFT_S))
+#define I2S_TX_PDM_HP_IN_SHIFT_V  0x3
+#define I2S_TX_PDM_HP_IN_SHIFT_S  16
+/* I2S_TX_PDM_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: set to 0*/
+#define I2S_TX_PDM_PRESCALE  0x000000FF
+#define I2S_TX_PDM_PRESCALE_M  ((I2S_TX_PDM_PRESCALE_V)<<(I2S_TX_PDM_PRESCALE_S))
+#define I2S_TX_PDM_PRESCALE_V  0xFF
+#define I2S_TX_PDM_PRESCALE_S  8
+/* I2S_TX_PDM_SINC_OSR2 : R/W ;bitpos:[7:4] ;default: 4'h2 ; */
+/*description: upsample rate = 64 * reg_tx_pdm_sinc_osr2*/
+#define I2S_TX_PDM_SINC_OSR2  0x0000000F
+#define I2S_TX_PDM_SINC_OSR2_M  ((I2S_TX_PDM_SINC_OSR2_V)<<(I2S_TX_PDM_SINC_OSR2_S))
+#define I2S_TX_PDM_SINC_OSR2_V  0xF
+#define I2S_TX_PDM_SINC_OSR2_S  4
+/* I2S_PDM2PCM_CONV_EN : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: Set this bit to enable PDM-to-PCM converter*/
+#define I2S_PDM2PCM_CONV_EN  (BIT(3))
+#define I2S_PDM2PCM_CONV_EN_M  (BIT(3))
+#define I2S_PDM2PCM_CONV_EN_V  0x1
+#define I2S_PDM2PCM_CONV_EN_S  3
+/* I2S_PCM2PDM_CONV_EN : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to enable PCM-to-PDM converter*/
+#define I2S_PCM2PDM_CONV_EN  (BIT(2))
+#define I2S_PCM2PDM_CONV_EN_M  (BIT(2))
+#define I2S_PCM2PDM_CONV_EN_V  0x1
+#define I2S_PCM2PDM_CONV_EN_S  2
+/* I2S_RX_PDM_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enable receiver PDM mode*/
+#define I2S_RX_PDM_EN  (BIT(1))
+#define I2S_RX_PDM_EN_M  (BIT(1))
+#define I2S_RX_PDM_EN_V  0x1
+#define I2S_RX_PDM_EN_S  1
+/* I2S_TX_PDM_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to enable transmitter PDM mode*/
+#define I2S_TX_PDM_EN  (BIT(0))
+#define I2S_TX_PDM_EN_M  (BIT(0))
+#define I2S_TX_PDM_EN_V  0x1
+#define I2S_TX_PDM_EN_S  0
+
+#define I2S_PDM_FREQ_CONF_REG(i)          (REG_I2S_BASE(i) + 0x00b8)
+/* I2S_TX_PDM_FP : R/W ;bitpos:[19:10] ;default: 10'd960 ; */
+/*description: PCM-to-PDM converter PDM frequency parameter*/
+#define I2S_TX_PDM_FP  0x000003FF
+#define I2S_TX_PDM_FP_M  ((I2S_TX_PDM_FP_V)<<(I2S_TX_PDM_FP_S))
+#define I2S_TX_PDM_FP_V  0x3FF
+#define I2S_TX_PDM_FP_S  10
+/* I2S_TX_PDM_FS : R/W ;bitpos:[9:0] ;default: 10'd480 ; */
+/*description: PCM-to-PDM converter PCM frequency parameter*/
+#define I2S_TX_PDM_FS  0x000003FF
+#define I2S_TX_PDM_FS_M  ((I2S_TX_PDM_FS_V)<<(I2S_TX_PDM_FS_S))
+#define I2S_TX_PDM_FS_V  0x3FF
+#define I2S_TX_PDM_FS_S  0
+
+#define I2S_STATE_REG(i)          (REG_I2S_BASE(i) + 0x00bc)
+/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
+/*description: 1: i2s_tx is idle state*/
+#define I2S_TX_IDLE  (BIT(0))
+#define I2S_TX_IDLE_M  (BIT(0))
+#define I2S_TX_IDLE_V  0x1
+#define I2S_TX_IDLE_S  0
+
+#define I2S_DATE_REG(i)          (REG_I2S_BASE(i) + 0x00fc)
+/* I2S_I2SDATE : R/W ;bitpos:[31:0] ;default: 32'h18092900 ; */
+/*description: */
+#define I2S_I2SDATE  0xFFFFFFFF
+#define I2S_I2SDATE_M  ((I2S_I2SDATE_V)<<(I2S_I2SDATE_S))
+#define I2S_I2SDATE_V  0xFFFFFFFF
+#define I2S_I2SDATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_I2S_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/i2s_struct.h b/components/soc/esp32s2beta/include/soc/i2s_struct.h
new file mode 100644
index 000000000..c9a24e6b2
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/i2s_struct.h
@@ -0,0 +1,505 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_I2S_STRUCT_H_
+#define _SOC_I2S_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t reserved_0;
+    uint32_t reserved_4;
+    union {
+        struct {
+            uint32_t tx_reset:         1;                 /*Set this bit to reset transmitter*/
+            uint32_t rx_reset:         1;                 /*Set this bit to reset receiver*/
+            uint32_t tx_fifo_reset:    1;                 /*Set this bit to reset txFIFO*/
+            uint32_t rx_fifo_reset:    1;                 /*Set this bit to reset rxFIFO*/
+            uint32_t tx_start:         1;                 /*Set this bit to start transmitting data*/
+            uint32_t rx_start:         1;                 /*Set this bit to start receiving data*/
+            uint32_t tx_slave_mod:     1;                 /*Set this bit to enable slave transmitter mode*/
+            uint32_t rx_slave_mod:     1;                 /*Set this bit to enable slave receiver mode*/
+            uint32_t tx_right_first:   1;                 /*Set this bit to transmit right channel data first*/
+            uint32_t rx_right_first:   1;                 /*Set this bit to receive right channel data first*/
+            uint32_t tx_msb_shift:     1;                 /*Set this bit to enable transmitter in Phillips standard mode*/
+            uint32_t rx_msb_shift:     1;                 /*Set this bit to enable receiver in Phillips standard mode*/
+            uint32_t tx_short_sync:    1;                 /*Set this bit to enable transmitter in PCM standard mode*/
+            uint32_t rx_short_sync:    1;                 /*Set this bit to enable receiver in PCM standard mode*/
+            uint32_t tx_mono:          1;                 /*Set this bit to enable transmitter in mono mode*/
+            uint32_t rx_mono:          1;                 /*Set this bit to enable receiver  in mono mode*/
+            uint32_t tx_msb_right:     1;                 /*Set this bit to place right channel data at the MSB in the transmit FIFO.*/
+            uint32_t rx_msb_right:     1;                 /*Set this bit to place right channel data at the MSB in the receive FIFO.*/
+            uint32_t tx_lsb_first_dma: 1;                 /*1:the data in DMA/APB transform from low bits*/
+            uint32_t rx_lsb_first_dma: 1;                 /*1:the data in DMA/APB transform from low bits*/
+            uint32_t sig_loopback:     1;                 /*Enable signal loopback mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
+            uint32_t tx_fifo_reset_st: 1;                 /*1:i2s_tx_fifo reset is not ok   0:i2s_tx_fifo_reset is ok*/
+            uint32_t rx_fifo_reset_st: 1;                 /*1:i2s_rx_fifo_reset is not ok   0:i2s_rx_fifo reset is ok*/
+            uint32_t tx_reset_st:      1;                 /*1: i2s_tx_reset is not ok   0: i2s_tx_reset is ok*/
+            uint32_t tx_dma_equal:     1;                 /*1:data in left channel is equal to data in right channel*/
+            uint32_t rx_dma_equal:     1;                 /*1:data in left channel is equal to data in right channel*/
+            uint32_t pre_req_en:       1;                 /*set this bit to enable i2s to prepare data earlier*/
+            uint32_t tx_big_endian:    1;
+            uint32_t rx_big_endian:    1;
+            uint32_t rx_reset_st:      1;
+            uint32_t reserved30:       2;
+        };
+        uint32_t val;
+    } conf;
+    union {
+        struct {
+            uint32_t rx_take_data:          1;            /*The raw interrupt status bit  for the i2s_rx_take_data_int interrupt*/
+            uint32_t tx_put_data:           1;            /*The raw interrupt status bit  for the i2s_tx_put_data_int interrupt*/
+            uint32_t rx_wfull:              1;            /*The raw interrupt status bit  for the i2s_rx_wfull_int interrupt*/
+            uint32_t rx_rempty:             1;            /*The raw interrupt status bit  for the i2s_rx_rempty_int interrupt*/
+            uint32_t tx_wfull:              1;            /*The raw interrupt status bit  for the i2s_tx_wfull_int interrupt*/
+            uint32_t tx_rempty:             1;            /*The raw interrupt status bit  for the i2s_tx_rempty_int interrupt*/
+            uint32_t rx_hung:               1;            /*The raw interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:               1;            /*The raw interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t in_done:               1;            /*The raw interrupt status bit  for the i2s_in_done_int interrupt*/
+            uint32_t in_suc_eof:            1;            /*The raw interrupt status bit  for the i2s_in_suc_eof_int interrupt*/
+            uint32_t in_err_eof:            1;            /*don't use*/
+            uint32_t out_done:              1;            /*The raw interrupt status bit  for the i2s_out_done_int interrupt*/
+            uint32_t out_eof:               1;            /*The raw interrupt status bit  for the i2s_out_eof_int interrupt*/
+            uint32_t in_dscr_err:           1;            /*The raw interrupt status bit  for the i2s_in_dscr_err_int interrupt*/
+            uint32_t out_dscr_err:          1;            /*The raw interrupt status bit  for the i2s_out_dscr_err_int interrupt*/
+            uint32_t in_dscr_empty:         1;            /*The raw interrupt status bit  for the i2s_in_dscr_empty_int interrupt*/
+            uint32_t out_total_eof:         1;            /*The raw interrupt status bit  for the i2s_out_total_eof_int interrupt*/
+            uint32_t reserved17:           15;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_take_data:         1;             /*The masked interrupt status bit  for the i2s_rx_take_data_int interrupt*/
+            uint32_t tx_put_data:          1;             /*The masked interrupt status bit  for the i2s_tx_put_data_int interrupt*/
+            uint32_t rx_wfull:             1;             /*The masked interrupt status bit  for the i2s_rx_wfull_int interrupt*/
+            uint32_t rx_rempty:            1;             /*The masked interrupt status bit  for the i2s_rx_rempty_int interrupt*/
+            uint32_t tx_wfull:             1;             /*The masked interrupt status bit  for the i2s_tx_wfull_int interrupt*/
+            uint32_t tx_rempty:            1;             /*The masked interrupt status bit  for the i2s_tx_rempty_int interrupt*/
+            uint32_t rx_hung:              1;             /*The masked interrupt status bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:              1;             /*The masked interrupt status bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t in_done:              1;             /*The masked interrupt status bit  for the i2s_in_done_int interrupt*/
+            uint32_t in_suc_eof:           1;             /*The masked interrupt status bit  for the i2s_in_suc_eof_int interrupt*/
+            uint32_t in_err_eof:           1;             /*don't use*/
+            uint32_t out_done:             1;             /*The masked interrupt status bit  for the i2s_out_done_int interrupt*/
+            uint32_t out_eof:              1;             /*The masked interrupt status bit  for the i2s_out_eof_int interrupt*/
+            uint32_t in_dscr_err:          1;             /*The masked interrupt status bit  for the i2s_in_dscr_err_int interrupt*/
+            uint32_t out_dscr_err:         1;             /*The masked interrupt status bit  for the i2s_out_dscr_err_int interrupt*/
+            uint32_t in_dscr_empty:        1;             /*The masked interrupt status bit  for the i2s_in_dscr_empty_int interrupt*/
+            uint32_t out_total_eof:        1;             /*The masked interrupt status bit  for the i2s_out_total_eof_int interrupt*/
+            uint32_t reserved17:          15;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rx_take_data:          1;            /*The interrupt enable bit  for the i2s_rx_take_data_int interrupt*/
+            uint32_t tx_put_data:           1;            /*The interrupt enable bit  for the i2s_tx_put_data_int interrupt*/
+            uint32_t rx_wfull:              1;            /*The interrupt enable bit  for the i2s_rx_wfull_int interrupt*/
+            uint32_t rx_rempty:             1;            /*The interrupt enable bit  for the i2s_rx_rempty_int interrupt*/
+            uint32_t tx_wfull:              1;            /*The interrupt enable bit  for the i2s_tx_wfull_int interrupt*/
+            uint32_t tx_rempty:             1;            /*The interrupt enable bit  for the i2s_tx_rempty_int interrupt*/
+            uint32_t rx_hung:               1;            /*The interrupt enable bit  for the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:               1;            /*The interrupt enable bit  for the i2s_tx_hung_int interrupt*/
+            uint32_t in_done:               1;            /*The interrupt enable bit  for the i2s_in_done_int interrupt*/
+            uint32_t in_suc_eof:            1;            /*The interrupt enable bit  for the i2s_in_suc_eof_int interrupt*/
+            uint32_t in_err_eof:            1;            /*don't use*/
+            uint32_t out_done:              1;            /*The interrupt enable bit  for the i2s_out_done_int interrupt*/
+            uint32_t out_eof:               1;            /*The interrupt enable bit  for the i2s_out_eof_int interrupt*/
+            uint32_t in_dscr_err:           1;            /*The interrupt enable bit  for the i2s_in_dscr_err_int interrupt*/
+            uint32_t out_dscr_err:          1;            /*The interrupt enable bit  for the i2s_out_dscr_err_int interrupt*/
+            uint32_t in_dscr_empty:         1;            /*The interrupt enable bit  for the i2s_in_dscr_empty_int interrupt*/
+            uint32_t out_total_eof:         1;            /*The interrupt enable bit  for the i2s_out_total_eof_int interrupt*/
+            uint32_t reserved17:           15;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t take_data:             1;            /*Set this bit to clear the i2s_rx_take_data_int interrupt*/
+            uint32_t put_data:              1;            /*Set this bit to clear the i2s_tx_put_data_int interrupt*/
+            uint32_t rx_wfull:              1;            /*Set this bit to clear the i2s_rx_wfull_int interrupt*/
+            uint32_t rx_rempty:             1;            /*Set this bit to clear the i2s_rx_rempty_int interrupt*/
+            uint32_t tx_wfull:              1;            /*Set this bit to clear the i2s_tx_wfull_int interrupt*/
+            uint32_t tx_rempty:             1;            /*Set this bit to clear the i2s_tx_rempty_int interrupt*/
+            uint32_t rx_hung:               1;            /*Set this bit to clear the i2s_rx_hung_int interrupt*/
+            uint32_t tx_hung:               1;            /*Set this bit to clear the i2s_tx_hung_int interrupt*/
+            uint32_t in_done:               1;            /*Set this bit to clear the i2s_in_done_int interrupt*/
+            uint32_t in_suc_eof:            1;            /*Set this bit to clear the i2s_in_suc_eof_int interrupt*/
+            uint32_t in_err_eof:            1;            /*don't use*/
+            uint32_t out_done:              1;            /*Set this bit to clear the i2s_out_done_int interrupt*/
+            uint32_t out_eof:               1;            /*Set this bit to clear the i2s_out_eof_int interrupt*/
+            uint32_t in_dscr_err:           1;            /*Set this bit to clear the i2s_in_dscr_err_int interrupt*/
+            uint32_t out_dscr_err:          1;            /*Set this bit to clear the i2s_out_dscr_err_int interrupt*/
+            uint32_t in_dscr_empty:         1;            /*Set this bit to clear the i2s_in_dscr_empty_int interrupt*/
+            uint32_t out_total_eof:         1;            /*Set this bit to clear the i2s_out_total_eof_int interrupt*/
+            uint32_t reserved17:           15;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t tx_bck_in_delay:   2;                /*Number of delay cycles for BCK into the transmitter*/
+            uint32_t tx_ws_in_delay:    2;                /*Number of delay cycles for WS into the transmitter*/
+            uint32_t rx_bck_in_delay:   2;                /*Number of delay cycles for BCK into the receiver*/
+            uint32_t rx_ws_in_delay:    2;                /*Number of delay cycles for WS into the receiver*/
+            uint32_t rx_sd_in_delay:    2;                /*Number of delay cycles for SD into the receiver*/
+            uint32_t tx_bck_out_delay:  2;                /*Number of delay cycles for BCK out of the transmitter*/
+            uint32_t tx_ws_out_delay:   2;                /*Number of delay cycles for WS out of the transmitter*/
+            uint32_t tx_sd_out_delay:   2;                /*Number of delay cycles for SD out of the transmitter*/
+            uint32_t rx_ws_out_delay:   2;                /*Number of delay cycles for WS out of the receiver*/
+            uint32_t rx_bck_out_delay:  2;                /*Number of delay cycles for BCK out of the receiver*/
+            uint32_t tx_dsync_sw:       1;                /*Set this bit to synchronize signals with the double sync method into the transmitter*/
+            uint32_t rx_dsync_sw:       1;                /*Set this bit to synchronize signals with the double sync method into the receiver*/
+            uint32_t data_enable_delay: 2;                /*Number of delay cycles for data valid flag.*/
+            uint32_t tx_bck_in_inv:     1;                /*Set this bit to invert BCK signal input to the slave transmitter*/
+            uint32_t reserved25:        7;
+        };
+        uint32_t val;
+    } timing;
+    union {
+        struct {
+            uint32_t rx_data_num:          6;             /*Threshold of data length in receiver FIFO*/
+            uint32_t tx_data_num:          6;             /*Threshold of data length in transmitter FIFO*/
+            uint32_t dscr_en:              1;             /*Set this bit to enable I2S DMA mode*/
+            uint32_t tx_fifo_mod:          3;             /*Transmitter FIFO mode configuration bits*/
+            uint32_t rx_fifo_mod:          3;             /*Receiver FIFO mode configuration bits*/
+            uint32_t tx_fifo_mod_force_en: 1;             /*The bit should always be set to 1*/
+            uint32_t rx_fifo_mod_force_en: 1;             /*The bit should always be set to 1*/
+            uint32_t rx_fifo_sync:         1;             /*force write back rx data to memory*/
+            uint32_t rx_24msb_en:          1;             /*Only useful in rx 24bit mode. 1: the high 24 bits are effective in i2s fifo   0: the low 24 bits are effective in i2s fifo*/
+            uint32_t tx_24msb_en:          1;             /*Only useful in tx 24bit mode. 1: the high 24 bits are effective in i2s fifo   0: the low 24 bits are effective in i2s fifo*/
+            uint32_t reserved24:           8;
+        };
+        uint32_t val;
+    } fifo_conf;
+    uint32_t rx_eof_num;                                /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
+    uint32_t conf_single_data;                          /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
+    union {
+        struct {
+            uint32_t tx_chan_mod: 3;                      /*I2S transmitter channel mode configuration bits.*/
+            uint32_t rx_chan_mod: 2;                      /*I2S receiver channel mode configuration bits.*/
+            uint32_t reserved5:  27;
+        };
+        uint32_t val;
+    } conf_chan;
+    union {
+        struct {
+            uint32_t addr:           20;                  /*The address of first outlink descriptor*/
+            uint32_t reserved20:      8;
+            uint32_t stop:            1;                  /*Set this bit to stop outlink descriptor*/
+            uint32_t start:           1;                  /*Set this bit to start outlink descriptor*/
+            uint32_t restart:         1;                  /*Set this bit to restart outlink descriptor*/
+            uint32_t park:            1;
+        };
+        uint32_t val;
+    } out_link;
+    union {
+        struct {
+            uint32_t addr:          20;                   /*The address of first inlink descriptor*/
+            uint32_t reserved20:     8;
+            uint32_t stop:           1;                   /*Set this bit to stop inlink descriptor*/
+            uint32_t start:          1;                   /*Set this bit to start inlink descriptor*/
+            uint32_t restart:        1;                   /*Set this bit to restart inlink descriptor*/
+            uint32_t park:           1;
+        };
+        uint32_t val;
+    } in_link;
+    uint32_t out_eof_des_addr;                            /*The address of outlink descriptor that produces EOF*/
+    uint32_t in_eof_des_addr;                             /*The address of inlink descriptor that produces EOF*/
+    uint32_t out_eof_bfr_des_addr;                        /*The address of buffer relative to the outlink descriptor that produces EOF*/
+    union {
+        struct {
+            uint32_t mode:         3;
+            uint32_t reserved3:    1;
+            uint32_t addr:         2;
+            uint32_t reserved6:   26;
+        };
+        uint32_t val;
+    } ahb_test;
+    uint32_t in_link_dscr;                                 /*The address of current inlink descriptor*/
+    uint32_t in_link_dscr_bf0;                             /*The address of next inlink descriptor*/
+    uint32_t in_link_dscr_bf1;                             /*The address of next inlink data buffer*/
+    uint32_t out_link_dscr;                                /*The address of current outlink descriptor*/
+    uint32_t out_link_dscr_bf0;                            /*The address of next outlink descriptor*/
+    uint32_t out_link_dscr_bf1;                            /*The address of next outlink data buffer*/
+    union {
+        struct {
+            uint32_t in_rst:             1;               /*Set this bit to reset in dma FSM*/
+            uint32_t out_rst:            1;               /*Set this bit to reset out dma FSM*/
+            uint32_t ahbm_fifo_rst:      1;               /*Set this bit to reset ahb interface cmdFIFO of DMA*/
+            uint32_t ahbm_rst:           1;               /*Set this bit to reset ahb interface of DMA*/
+            uint32_t out_loop_test:      1;               /*Set this bit to loop test inlink*/
+            uint32_t in_loop_test:       1;               /*Set this bit to loop test outlink*/
+            uint32_t out_auto_wrback:    1;               /*Set this bit to enable outlink-written-back automatically when out buffer is transmitted done.*/
+            uint32_t out_no_restart_clr: 1;               /*don't use*/
+            uint32_t out_eof_mode:       1;               /*DMA out EOF flag generation mode . 1: when dma has popped all data from the FIFO  0:when ahb has pushed all data to the FIFO*/
+            uint32_t outdscr_burst_en:   1;               /*DMA outlink descriptor transfer mode configuration bit. 1:  to prepare outlink descriptor with burst mode    0: to prepare outlink descriptor with byte mode*/
+            uint32_t indscr_burst_en:    1;               /*DMA inlink descriptor transfer mode configuration bit. 1:  to prepare inlink descriptor with burst mode    0: to prepare inlink descriptor with byte mode*/
+            uint32_t out_data_burst_en:  1;               /*Transmitter data transfer mode configuration bit. 1:  to prepare out data with burst mode      0: to prepare out data with byte mode*/
+            uint32_t check_owner:        1;               /*Set this bit to enable check owner bit by hardware*/
+            uint32_t mem_trans_en:       1;               /*don't use*/
+            uint32_t reserved14:        18;
+        };
+        uint32_t val;
+    } lc_conf;
+    union {
+        struct {
+            uint32_t wdata:         9;
+            uint32_t reserved9:     7;
+            uint32_t push:          1;
+            uint32_t reserved17:   15;
+        };
+        uint32_t val;
+    } out_fifo_push;
+    union {
+        struct {
+            uint32_t rdata:       12;
+            uint32_t reserved12:   4;
+            uint32_t pop:          1;
+            uint32_t reserved17:  15;
+        };
+        uint32_t val;
+    } in_fifo_pop;
+    union {
+        struct {
+            uint32_t dscr_addr:        18;
+            uint32_t out_dscr_state:    2;
+            uint32_t out_state:         3;
+            uint32_t cnt:               7;
+            uint32_t out_full:          1;
+            uint32_t out_empty:         1;                /*DMA transmitter status register*/
+        };
+        uint32_t val;
+    } lc_state0;
+    union {
+        struct {
+            uint32_t dscr_addr:       18;
+            uint32_t in_dscr_state:    2;
+            uint32_t in_state:         3;
+            uint32_t cnt_debug:        7;
+            uint32_t in_full:          1;
+            uint32_t in_empty:         1;                 /*DMA receiver status register*/
+        };
+        uint32_t val;
+    } lc_state1;
+    union {
+        struct {
+            uint32_t fifo_timeout:          8;            /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
+            uint32_t fifo_timeout_shift:    3;            /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
+            uint32_t fifo_timeout_ena:      1;            /*The enable bit for FIFO timeout*/
+            uint32_t reserved12:           20;
+        };
+        uint32_t val;
+    } lc_hung_conf;
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    union {
+        struct {
+            uint32_t y_max:     16;                       /*don't use*/
+            uint32_t y_min:     16;                       /*don't use*/
+        };
+        uint32_t val;
+    } cvsd_conf0;
+    union {
+        struct {
+            uint32_t sigma_max:     16;                   /*don't use*/
+            uint32_t sigma_min:     16;                   /*don't use*/
+        };
+        uint32_t val;
+    } cvsd_conf1;
+    union {
+        struct {
+            uint32_t cvsd_k:     3;                       /*don't use*/
+            uint32_t cvsd_j:     3;                       /*don't use*/
+            uint32_t cvsd_beta: 10;                       /*don't use*/
+            uint32_t cvsd_h:     3;                       /*don't use*/
+            uint32_t reserved19:13;                       /*don't use*/
+        };
+        uint32_t val;
+    } cvsd_conf2;
+    union {
+        struct {
+            uint32_t good_pack_max:    6;                 /*don't use*/
+            uint32_t n_err_seg:        3;                 /*don't use*/
+            uint32_t shift_rate:       3;                 /*don't use*/
+            uint32_t max_slide_sample: 8;                 /*don't use*/
+            uint32_t pack_len_8k:      5;                 /*don't use*/
+            uint32_t n_min_err:        3;                 /*don't use*/
+            uint32_t reserved28:       4;                 /*don't use*/
+        };
+        uint32_t val;
+    } plc_conf0;
+    union {
+        struct {
+            uint32_t bad_cef_atten_para:       8;         /*don't use*/
+            uint32_t bad_cef_atten_para_shift: 4;         /*don't use*/
+            uint32_t bad_ola_win2_para_shift:  4;         /*don't use*/
+            uint32_t bad_ola_win2_para:        8;         /*don't use*/
+            uint32_t slide_win_len:            8;         /*don't use*/
+        };
+        uint32_t val;
+    } plc_conf1;
+    union {
+        struct {
+            uint32_t cvsd_seg_mod: 2;                     /*don't use*/
+            uint32_t min_period:   5;                     /*don't use*/
+            uint32_t reserved7:   25;                     /*don't use*/
+        };
+        uint32_t val;
+    } plc_conf2;
+    union {
+        struct {
+            uint32_t en:                     1;           /*don't use*/
+            uint32_t chan_mod:               1;           /*don't use*/
+            uint32_t cvsd_dec_pack_err:      1;           /*don't use*/
+            uint32_t cvsd_pack_len_8k:       5;           /*don't use*/
+            uint32_t cvsd_inf_en:            1;           /*don't use*/
+            uint32_t cvsd_dec_start:         1;           /*don't use*/
+            uint32_t cvsd_dec_reset:         1;           /*don't use*/
+            uint32_t plc_en:                 1;           /*don't use*/
+            uint32_t plc2dma_en:             1;           /*don't use*/
+            uint32_t reserved13:            19;           /*don't use*/
+        };
+        uint32_t val;
+    } esco_conf0;
+    union {
+        struct {
+            uint32_t with_en:        1;                   /*don't use*/
+            uint32_t no_en:          1;                   /*don't use*/
+            uint32_t cvsd_enc_start: 1;                   /*don't use*/
+            uint32_t cvsd_enc_reset: 1;                   /*don't use*/
+            uint32_t reserved4:     28;                   /*don't use*/
+        };
+        uint32_t val;
+    } sco_conf0;
+    union {
+        struct {
+            uint32_t tx_pcm_conf:    3;                   /*Compress/Decompress module configuration bits. 0: decompress transmitted data  1:compress transmitted data*/
+            uint32_t tx_pcm_bypass:  1;                   /*Set this bit to bypass  Compress/Decompress module for transmitted data.*/
+            uint32_t rx_pcm_conf:    3;                   /*Compress/Decompress module configuration bits. 0: decompress received data  1:compress received data*/
+            uint32_t rx_pcm_bypass:  1;                   /*Set this bit to bypass Compress/Decompress module for received data.*/
+            uint32_t tx_stop_en:     1;                   /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
+            uint32_t tx_zeros_rm_en: 1;                   /*don't use*/
+            uint32_t reserved10:    22;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t fifo_force_pd:    1;                 /*Force FIFO power-down*/
+            uint32_t fifo_force_pu:    1;                 /*Force FIFO power-up*/
+            uint32_t plc_mem_force_pd: 1;
+            uint32_t plc_mem_force_pu: 1;
+            uint32_t reserved4:       28;
+        };
+        uint32_t val;
+    } pd_conf;
+    union {
+        struct {
+            uint32_t camera_en:              1;           /*Set this bit to enable camera mode*/
+            uint32_t lcd_tx_wrx2_en:         1;           /*LCD WR double for one datum.*/
+            uint32_t lcd_tx_sdx2_en:         1;           /*Set this bit to duplicate data pairs (Frame Form 2) in LCD mode.*/
+            uint32_t data_enable_test_en:    1;           /*for debug camera mode enable*/
+            uint32_t data_enable:            1;           /*for debug camera mode enable*/
+            uint32_t lcd_en:                 1;           /*Set this bit to enable LCD mode*/
+            uint32_t ext_adc_start_en:       1;           /*Set this bit to enable the function that ADC mode is triggered by external signal.*/
+            uint32_t inter_valid_en:         1;           /*Set this bit to enable camera internal valid*/
+            uint32_t cam_sync_fifo_reset:    1;           /*Set this bit to reset cam_sync_fifo*/
+            uint32_t cam_clk_loopback:       1;           /*Set this bit to loopback cam_clk from i2s_rx*/
+            uint32_t cam_sync_fifo_reset_st: 1;
+            uint32_t reserved11:            21;
+        };
+        uint32_t val;
+    } conf2;
+    union {
+        struct {
+            uint32_t clkm_div_num: 8;                     /*Integral I2S clock divider value*/
+            uint32_t clkm_div_b:   6;                     /*Fractional clock divider numerator value*/
+            uint32_t clkm_div_a:   6;                     /*Fractional clock divider denominator value*/
+            uint32_t clk_en:       1;                     /*Set this bit to enable clk gate*/
+            uint32_t clk_sel:      2;                     /*Set this bit to enable clk_apll*/
+            uint32_t reserved23:   9;
+        };
+        uint32_t val;
+    } clkm_conf;
+    union {
+        struct {
+            uint32_t tx_bck_div_num: 6;                   /*Bit clock configuration bits in transmitter mode.*/
+            uint32_t rx_bck_div_num: 6;                   /*Bit clock configuration bits in receiver mode.*/
+            uint32_t tx_bits_mod:    6;                   /*Set the bits to configure bit length of I2S transmitter channel.*/
+            uint32_t rx_bits_mod:    6;                   /*Set the bits to configure bit length of I2S receiver channel.*/
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } sample_rate_conf;
+    union {
+        struct {
+            uint32_t tx_pdm_en:                  1;       /*Set this bit to enable transmitter PDM mode*/
+            uint32_t rx_pdm_en:                  1;       /*Set this bit to enable receiver PDM mode*/
+            uint32_t pcm2pdm_conv_en:            1;       /*Set this bit to enable PCM-to-PDM converter*/
+            uint32_t pdm2pcm_conv_en:            1;       /*Set this bit to enable PDM-to-PCM converter*/
+            uint32_t tx_sinc_osr2:               4;       /*upsample rate = 64 * reg_tx_pdm_sinc_osr2*/
+            uint32_t tx_prescale:                8;       /*set to 0*/
+            uint32_t tx_hp_in_shift:             2;       /*Adjust size of input signal to filter module. 0: divided by 2  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+            uint32_t tx_lp_in_shift:             2;       /*Adjust size of input signal to filter module. 0: divided by 2  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+            uint32_t tx_sinc_in_shift:           2;       /*Adjust size of input signal to filter module. 0: divided by 2  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+            uint32_t tx_sigmadelta_in_shift:     2;       /*Adjust size of input signal to filter module. 0: divided by 2  1:multiplied by 1  2:multiplied by 2  3:multiplied by 4*/
+            uint32_t rx_sinc_dsr_16_en:          1;       /*PDM down-sampling rate for filter group1 in receiver mode. 0: downsample rate = 64  1:downsample rate = 128*/
+            uint32_t txhp_bypass:                1;       /*Set this bit to enable tx pdm hp filter bypass*/
+            uint32_t tx_chan_mod:                2;       /*pdm tx channel mode*/
+            uint32_t tx_way_mode:                2;       /*0/1 pdm rx use one-way*/
+            uint32_t rx_way_mode:                2;       /*0/1 pdm rx use one-way*/
+        };
+        uint32_t val;
+    } pdm_conf;
+    union {
+        struct {
+            uint32_t tx_pdm_fs: 10;                       /*PCM-to-PDM converter PCM frequency parameter*/
+            uint32_t tx_pdm_fp: 10;                       /*PCM-to-PDM converter PDM frequency parameter*/
+            uint32_t reserved20:12;
+        };
+        uint32_t val;
+    } pdm_freq_conf;
+    union {
+        struct {
+            uint32_t tx_idle:    1;                       /*1: i2s_tx is idle state*/
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    } state;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t date;                                        /**/
+} i2s_dev_t;
+extern i2s_dev_t I2S0;
+extern i2s_dev_t I2S1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_I2S_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/interrupt_reg.h b/components/soc/esp32s2beta/include/soc/interrupt_reg.h
new file mode 100644
index 000000000..d04f22928
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/interrupt_reg.h
@@ -0,0 +1,772 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_INTERRUPT_REG_H_
+#define _SOC_INTERRUPT_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define DPORT_PRO_MAC_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x000)
+/* DPORT_PRO_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_MAC_INTR_MAP  0x0000001F
+#define DPORT_PRO_MAC_INTR_MAP_M  ((DPORT_PRO_MAC_INTR_MAP_V)<<(DPORT_PRO_MAC_INTR_MAP_S))
+#define DPORT_PRO_MAC_INTR_MAP_V  0x1F
+#define DPORT_PRO_MAC_INTR_MAP_S  0
+
+#define DPORT_PRO_MAC_NMI_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x004)
+/* DPORT_PRO_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_MAC_NMI_MAP  0x0000001F
+#define DPORT_PRO_MAC_NMI_MAP_M  ((DPORT_PRO_MAC_NMI_MAP_V)<<(DPORT_PRO_MAC_NMI_MAP_S))
+#define DPORT_PRO_MAC_NMI_MAP_V  0x1F
+#define DPORT_PRO_MAC_NMI_MAP_S  0
+
+#define DPORT_PRO_PWR_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x008)
+/* DPORT_PRO_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWR_INTR_MAP  0x0000001F
+#define DPORT_PRO_PWR_INTR_MAP_M  ((DPORT_PRO_PWR_INTR_MAP_V)<<(DPORT_PRO_PWR_INTR_MAP_S))
+#define DPORT_PRO_PWR_INTR_MAP_V  0x1F
+#define DPORT_PRO_PWR_INTR_MAP_S  0
+
+#define DPORT_PRO_BB_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x00C)
+/* DPORT_PRO_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BB_INT_MAP  0x0000001F
+#define DPORT_PRO_BB_INT_MAP_M  ((DPORT_PRO_BB_INT_MAP_V)<<(DPORT_PRO_BB_INT_MAP_S))
+#define DPORT_PRO_BB_INT_MAP_V  0x1F
+#define DPORT_PRO_BB_INT_MAP_S  0
+
+#define DPORT_PRO_BT_MAC_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x010)
+/* DPORT_PRO_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BT_MAC_INT_MAP  0x0000001F
+#define DPORT_PRO_BT_MAC_INT_MAP_M  ((DPORT_PRO_BT_MAC_INT_MAP_V)<<(DPORT_PRO_BT_MAC_INT_MAP_S))
+#define DPORT_PRO_BT_MAC_INT_MAP_V  0x1F
+#define DPORT_PRO_BT_MAC_INT_MAP_S  0
+
+#define DPORT_PRO_BT_BB_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x014)
+/* DPORT_PRO_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BT_BB_INT_MAP  0x0000001F
+#define DPORT_PRO_BT_BB_INT_MAP_M  ((DPORT_PRO_BT_BB_INT_MAP_V)<<(DPORT_PRO_BT_BB_INT_MAP_S))
+#define DPORT_PRO_BT_BB_INT_MAP_V  0x1F
+#define DPORT_PRO_BT_BB_INT_MAP_S  0
+
+#define DPORT_PRO_BT_BB_NMI_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x018)
+/* DPORT_PRO_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_BT_BB_NMI_MAP  0x0000001F
+#define DPORT_PRO_BT_BB_NMI_MAP_M  ((DPORT_PRO_BT_BB_NMI_MAP_V)<<(DPORT_PRO_BT_BB_NMI_MAP_S))
+#define DPORT_PRO_BT_BB_NMI_MAP_V  0x1F
+#define DPORT_PRO_BT_BB_NMI_MAP_S  0
+
+#define DPORT_PRO_RWBT_IRQ_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x01C)
+/* DPORT_PRO_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBT_IRQ_MAP  0x0000001F
+#define DPORT_PRO_RWBT_IRQ_MAP_M  ((DPORT_PRO_RWBT_IRQ_MAP_V)<<(DPORT_PRO_RWBT_IRQ_MAP_S))
+#define DPORT_PRO_RWBT_IRQ_MAP_V  0x1F
+#define DPORT_PRO_RWBT_IRQ_MAP_S  0
+
+#define DPORT_PRO_RWBLE_IRQ_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x020)
+/* DPORT_PRO_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBLE_IRQ_MAP  0x0000001F
+#define DPORT_PRO_RWBLE_IRQ_MAP_M  ((DPORT_PRO_RWBLE_IRQ_MAP_V)<<(DPORT_PRO_RWBLE_IRQ_MAP_S))
+#define DPORT_PRO_RWBLE_IRQ_MAP_V  0x1F
+#define DPORT_PRO_RWBLE_IRQ_MAP_S  0
+
+#define DPORT_PRO_RWBT_NMI_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x024)
+/* DPORT_PRO_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBT_NMI_MAP  0x0000001F
+#define DPORT_PRO_RWBT_NMI_MAP_M  ((DPORT_PRO_RWBT_NMI_MAP_V)<<(DPORT_PRO_RWBT_NMI_MAP_S))
+#define DPORT_PRO_RWBT_NMI_MAP_V  0x1F
+#define DPORT_PRO_RWBT_NMI_MAP_S  0
+
+#define DPORT_PRO_RWBLE_NMI_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x028)
+/* DPORT_PRO_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RWBLE_NMI_MAP  0x0000001F
+#define DPORT_PRO_RWBLE_NMI_MAP_M  ((DPORT_PRO_RWBLE_NMI_MAP_V)<<(DPORT_PRO_RWBLE_NMI_MAP_S))
+#define DPORT_PRO_RWBLE_NMI_MAP_V  0x1F
+#define DPORT_PRO_RWBLE_NMI_MAP_S  0
+
+#define DPORT_PRO_SLC0_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x02C)
+/* DPORT_PRO_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SLC0_INTR_MAP  0x0000001F
+#define DPORT_PRO_SLC0_INTR_MAP_M  ((DPORT_PRO_SLC0_INTR_MAP_V)<<(DPORT_PRO_SLC0_INTR_MAP_S))
+#define DPORT_PRO_SLC0_INTR_MAP_V  0x1F
+#define DPORT_PRO_SLC0_INTR_MAP_S  0
+
+#define DPORT_PRO_SLC1_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x030)
+/* DPORT_PRO_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SLC1_INTR_MAP  0x0000001F
+#define DPORT_PRO_SLC1_INTR_MAP_M  ((DPORT_PRO_SLC1_INTR_MAP_V)<<(DPORT_PRO_SLC1_INTR_MAP_S))
+#define DPORT_PRO_SLC1_INTR_MAP_V  0x1F
+#define DPORT_PRO_SLC1_INTR_MAP_S  0
+
+#define DPORT_PRO_UHCI0_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x034)
+/* DPORT_PRO_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UHCI0_INTR_MAP  0x0000001F
+#define DPORT_PRO_UHCI0_INTR_MAP_M  ((DPORT_PRO_UHCI0_INTR_MAP_V)<<(DPORT_PRO_UHCI0_INTR_MAP_S))
+#define DPORT_PRO_UHCI0_INTR_MAP_V  0x1F
+#define DPORT_PRO_UHCI0_INTR_MAP_S  0
+
+#define DPORT_PRO_UHCI1_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x038)
+/* DPORT_PRO_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UHCI1_INTR_MAP  0x0000001F
+#define DPORT_PRO_UHCI1_INTR_MAP_M  ((DPORT_PRO_UHCI1_INTR_MAP_V)<<(DPORT_PRO_UHCI1_INTR_MAP_S))
+#define DPORT_PRO_UHCI1_INTR_MAP_V  0x1F
+#define DPORT_PRO_UHCI1_INTR_MAP_S  0
+
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x03C)
+/* DPORT_PRO_TG_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T0_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_T0_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x040)
+/* DPORT_PRO_TG_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_T1_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_T1_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x044)
+/* DPORT_PRO_TG_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_WDT_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x048)
+/* DPORT_PRO_TG_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_LACT_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x04C)
+/* DPORT_PRO_TG1_T0_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_T0_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x050)
+/* DPORT_PRO_TG1_T1_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_T1_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x054)
+/* DPORT_PRO_TG1_WDT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_WDT_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x058)
+/* DPORT_PRO_TG1_LACT_LEVEL_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_M  ((DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S))
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_LACT_LEVEL_INT_MAP_S  0
+
+#define DPORT_PRO_GPIO_DPORT_PRO_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x05C)
+/* DPORT_PRO_GPIO_DPORT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_GPIO_DPORT_PRO_MAP  0x0000001F
+#define DPORT_PRO_GPIO_DPORT_PRO_MAP_M  ((DPORT_PRO_GPIO_DPORT_PRO_MAP_V)<<(DPORT_PRO_GPIO_DPORT_PRO_MAP_S))
+#define DPORT_PRO_GPIO_DPORT_PRO_MAP_V  0x1F
+#define DPORT_PRO_GPIO_DPORT_PRO_MAP_S  0
+
+#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x060)
+/* DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP  0x0000001F
+#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_M  ((DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_V)<<(DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_S))
+#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_V  0x1F
+#define DPORT_PRO_GPIO_DPORT_PRO_NMI_MAP_S  0
+
+#define DPORT_PRO_GPIO_DPORT_APP_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x064)
+/* DPORT_PRO_GPIO_DPORT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_GPIO_DPORT_APP_MAP  0x0000001F
+#define DPORT_PRO_GPIO_DPORT_APP_MAP_M  ((DPORT_PRO_GPIO_DPORT_APP_MAP_V)<<(DPORT_PRO_GPIO_DPORT_APP_MAP_S))
+#define DPORT_PRO_GPIO_DPORT_APP_MAP_V  0x1F
+#define DPORT_PRO_GPIO_DPORT_APP_MAP_S  0
+
+#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x068)
+/* DPORT_PRO_GPIO_DPORT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP  0x0000001F
+#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_M  ((DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_V)<<(DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_S))
+#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_V  0x1F
+#define DPORT_PRO_GPIO_DPORT_APP_NMI_MAP_S  0
+
+#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x06C)
+/* DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP  0x0000001F
+#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_M  ((DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V)<<(DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S))
+#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_V  0x1F
+#define DPORT_PRO_DEDICATED_GPIO_IN_INTR_MAP_S  0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x070)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP  0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_V  0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_0_MAP_S  0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x074)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP  0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_V  0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_1_MAP_S  0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x078)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP  0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_V  0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_2_MAP_S  0
+
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x07C)
+/* DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP  0x0000001F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_M  ((DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V)<<(DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S))
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_V  0x1F
+#define DPORT_PRO_CPU_INTR_FROM_CPU_3_MAP_S  0
+
+#define DPORT_PRO_SPI_INTR_1_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x080)
+/* DPORT_PRO_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_1_MAP  0x0000001F
+#define DPORT_PRO_SPI_INTR_1_MAP_M  ((DPORT_PRO_SPI_INTR_1_MAP_V)<<(DPORT_PRO_SPI_INTR_1_MAP_S))
+#define DPORT_PRO_SPI_INTR_1_MAP_V  0x1F
+#define DPORT_PRO_SPI_INTR_1_MAP_S  0
+
+#define DPORT_PRO_SPI_INTR_2_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x084)
+/* DPORT_PRO_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_2_MAP  0x0000001F
+#define DPORT_PRO_SPI_INTR_2_MAP_M  ((DPORT_PRO_SPI_INTR_2_MAP_V)<<(DPORT_PRO_SPI_INTR_2_MAP_S))
+#define DPORT_PRO_SPI_INTR_2_MAP_V  0x1F
+#define DPORT_PRO_SPI_INTR_2_MAP_S  0
+
+#define DPORT_PRO_SPI_INTR_3_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x088)
+/* DPORT_PRO_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_3_MAP  0x0000001F
+#define DPORT_PRO_SPI_INTR_3_MAP_M  ((DPORT_PRO_SPI_INTR_3_MAP_V)<<(DPORT_PRO_SPI_INTR_3_MAP_S))
+#define DPORT_PRO_SPI_INTR_3_MAP_V  0x1F
+#define DPORT_PRO_SPI_INTR_3_MAP_S  0
+
+#define DPORT_PRO_I2S0_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x08C)
+/* DPORT_PRO_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2S0_INT_MAP  0x0000001F
+#define DPORT_PRO_I2S0_INT_MAP_M  ((DPORT_PRO_I2S0_INT_MAP_V)<<(DPORT_PRO_I2S0_INT_MAP_S))
+#define DPORT_PRO_I2S0_INT_MAP_V  0x1F
+#define DPORT_PRO_I2S0_INT_MAP_S  0
+
+#define DPORT_PRO_I2S1_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x090)
+/* DPORT_PRO_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2S1_INT_MAP  0x0000001F
+#define DPORT_PRO_I2S1_INT_MAP_M  ((DPORT_PRO_I2S1_INT_MAP_V)<<(DPORT_PRO_I2S1_INT_MAP_S))
+#define DPORT_PRO_I2S1_INT_MAP_V  0x1F
+#define DPORT_PRO_I2S1_INT_MAP_S  0
+
+#define DPORT_PRO_UART_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x094)
+/* DPORT_PRO_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UART_INTR_MAP  0x0000001F
+#define DPORT_PRO_UART_INTR_MAP_M  ((DPORT_PRO_UART_INTR_MAP_V)<<(DPORT_PRO_UART_INTR_MAP_S))
+#define DPORT_PRO_UART_INTR_MAP_V  0x1F
+#define DPORT_PRO_UART_INTR_MAP_S  0
+
+#define DPORT_PRO_UART1_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x098)
+/* DPORT_PRO_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UART1_INTR_MAP  0x0000001F
+#define DPORT_PRO_UART1_INTR_MAP_M  ((DPORT_PRO_UART1_INTR_MAP_V)<<(DPORT_PRO_UART1_INTR_MAP_S))
+#define DPORT_PRO_UART1_INTR_MAP_V  0x1F
+#define DPORT_PRO_UART1_INTR_MAP_S  0
+
+#define DPORT_PRO_UART2_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x09C)
+/* DPORT_PRO_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_UART2_INTR_MAP  0x0000001F
+#define DPORT_PRO_UART2_INTR_MAP_M  ((DPORT_PRO_UART2_INTR_MAP_V)<<(DPORT_PRO_UART2_INTR_MAP_S))
+#define DPORT_PRO_UART2_INTR_MAP_V  0x1F
+#define DPORT_PRO_UART2_INTR_MAP_S  0
+
+#define DPORT_PRO_SDIO_HOST_DPORT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0A0)
+/* DPORT_PRO_SDIO_HOST_DPORT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SDIO_HOST_DPORT_MAP  0x0000001F
+#define DPORT_PRO_SDIO_HOST_DPORT_MAP_M  ((DPORT_PRO_SDIO_HOST_DPORT_MAP_V)<<(DPORT_PRO_SDIO_HOST_DPORT_MAP_S))
+#define DPORT_PRO_SDIO_HOST_DPORT_MAP_V  0x1F
+#define DPORT_PRO_SDIO_HOST_DPORT_MAP_S  0
+
+#define DPORT_PRO_PWM0_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0A4)
+/* DPORT_PRO_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM0_INTR_MAP  0x0000001F
+#define DPORT_PRO_PWM0_INTR_MAP_M  ((DPORT_PRO_PWM0_INTR_MAP_V)<<(DPORT_PRO_PWM0_INTR_MAP_S))
+#define DPORT_PRO_PWM0_INTR_MAP_V  0x1F
+#define DPORT_PRO_PWM0_INTR_MAP_S  0
+
+#define DPORT_PRO_PWM1_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0A8)
+/* DPORT_PRO_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM1_INTR_MAP  0x0000001F
+#define DPORT_PRO_PWM1_INTR_MAP_M  ((DPORT_PRO_PWM1_INTR_MAP_V)<<(DPORT_PRO_PWM1_INTR_MAP_S))
+#define DPORT_PRO_PWM1_INTR_MAP_V  0x1F
+#define DPORT_PRO_PWM1_INTR_MAP_S  0
+
+#define DPORT_PRO_PWM2_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0AC)
+/* DPORT_PRO_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM2_INTR_MAP  0x0000001F
+#define DPORT_PRO_PWM2_INTR_MAP_M  ((DPORT_PRO_PWM2_INTR_MAP_V)<<(DPORT_PRO_PWM2_INTR_MAP_S))
+#define DPORT_PRO_PWM2_INTR_MAP_V  0x1F
+#define DPORT_PRO_PWM2_INTR_MAP_S  0
+
+#define DPORT_PRO_PWM3_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0B0)
+/* DPORT_PRO_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PWM3_INTR_MAP  0x0000001F
+#define DPORT_PRO_PWM3_INTR_MAP_M  ((DPORT_PRO_PWM3_INTR_MAP_V)<<(DPORT_PRO_PWM3_INTR_MAP_S))
+#define DPORT_PRO_PWM3_INTR_MAP_V  0x1F
+#define DPORT_PRO_PWM3_INTR_MAP_S  0
+
+#define DPORT_PRO_LEDC_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0B4)
+/* DPORT_PRO_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_LEDC_INT_MAP  0x0000001F
+#define DPORT_PRO_LEDC_INT_MAP_M  ((DPORT_PRO_LEDC_INT_MAP_V)<<(DPORT_PRO_LEDC_INT_MAP_S))
+#define DPORT_PRO_LEDC_INT_MAP_V  0x1F
+#define DPORT_PRO_LEDC_INT_MAP_S  0
+
+#define DPORT_PRO_EFUSE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0B8)
+/* DPORT_PRO_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_EFUSE_INT_MAP  0x0000001F
+#define DPORT_PRO_EFUSE_INT_MAP_M  ((DPORT_PRO_EFUSE_INT_MAP_V)<<(DPORT_PRO_EFUSE_INT_MAP_S))
+#define DPORT_PRO_EFUSE_INT_MAP_V  0x1F
+#define DPORT_PRO_EFUSE_INT_MAP_S  0
+
+#define DPORT_PRO_CAN_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0BC)
+/* DPORT_PRO_CAN_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CAN_INT_MAP  0x0000001F
+#define DPORT_PRO_CAN_INT_MAP_M  ((DPORT_PRO_CAN_INT_MAP_V)<<(DPORT_PRO_CAN_INT_MAP_S))
+#define DPORT_PRO_CAN_INT_MAP_V  0x1F
+#define DPORT_PRO_CAN_INT_MAP_S  0
+
+#define DPORT_PRO_USB_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0C0)
+/* DPORT_PRO_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_USB_INTR_MAP  0x0000001F
+#define DPORT_PRO_USB_INTR_MAP_M  ((DPORT_PRO_USB_INTR_MAP_V)<<(DPORT_PRO_USB_INTR_MAP_S))
+#define DPORT_PRO_USB_INTR_MAP_V  0x1F
+#define DPORT_PRO_USB_INTR_MAP_S  0
+
+#define DPORT_PRO_RTC_CORE_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0C4)
+/* DPORT_PRO_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RTC_CORE_INTR_MAP  0x0000001F
+#define DPORT_PRO_RTC_CORE_INTR_MAP_M  ((DPORT_PRO_RTC_CORE_INTR_MAP_V)<<(DPORT_PRO_RTC_CORE_INTR_MAP_S))
+#define DPORT_PRO_RTC_CORE_INTR_MAP_V  0x1F
+#define DPORT_PRO_RTC_CORE_INTR_MAP_S  0
+
+#define DPORT_PRO_RMT_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0C8)
+/* DPORT_PRO_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RMT_INTR_MAP  0x0000001F
+#define DPORT_PRO_RMT_INTR_MAP_M  ((DPORT_PRO_RMT_INTR_MAP_V)<<(DPORT_PRO_RMT_INTR_MAP_S))
+#define DPORT_PRO_RMT_INTR_MAP_V  0x1F
+#define DPORT_PRO_RMT_INTR_MAP_S  0
+
+#define DPORT_PRO_PCNT_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0CC)
+/* DPORT_PRO_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PCNT_INTR_MAP  0x0000001F
+#define DPORT_PRO_PCNT_INTR_MAP_M  ((DPORT_PRO_PCNT_INTR_MAP_V)<<(DPORT_PRO_PCNT_INTR_MAP_S))
+#define DPORT_PRO_PCNT_INTR_MAP_V  0x1F
+#define DPORT_PRO_PCNT_INTR_MAP_S  0
+
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0D0)
+/* DPORT_PRO_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2C_EXT0_INTR_MAP  0x0000001F
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_M  ((DPORT_PRO_I2C_EXT0_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT0_INTR_MAP_S))
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_V  0x1F
+#define DPORT_PRO_I2C_EXT0_INTR_MAP_S  0
+
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0D4)
+/* DPORT_PRO_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_I2C_EXT1_INTR_MAP  0x0000001F
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_M  ((DPORT_PRO_I2C_EXT1_INTR_MAP_V)<<(DPORT_PRO_I2C_EXT1_INTR_MAP_S))
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_V  0x1F
+#define DPORT_PRO_I2C_EXT1_INTR_MAP_S  0
+
+#define DPORT_PRO_RSA_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0D8)
+/* DPORT_PRO_RSA_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_RSA_INTR_MAP  0x0000001F
+#define DPORT_PRO_RSA_INTR_MAP_M  ((DPORT_PRO_RSA_INTR_MAP_V)<<(DPORT_PRO_RSA_INTR_MAP_S))
+#define DPORT_PRO_RSA_INTR_MAP_V  0x1F
+#define DPORT_PRO_RSA_INTR_MAP_S  0
+
+#define DPORT_PRO_SPI1_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0DC)
+/* DPORT_PRO_SPI1_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI1_DMA_INT_MAP  0x0000001F
+#define DPORT_PRO_SPI1_DMA_INT_MAP_M  ((DPORT_PRO_SPI1_DMA_INT_MAP_V)<<(DPORT_PRO_SPI1_DMA_INT_MAP_S))
+#define DPORT_PRO_SPI1_DMA_INT_MAP_V  0x1F
+#define DPORT_PRO_SPI1_DMA_INT_MAP_S  0
+
+#define DPORT_PRO_SPI2_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0E0)
+/* DPORT_PRO_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI2_DMA_INT_MAP  0x0000001F
+#define DPORT_PRO_SPI2_DMA_INT_MAP_M  ((DPORT_PRO_SPI2_DMA_INT_MAP_V)<<(DPORT_PRO_SPI2_DMA_INT_MAP_S))
+#define DPORT_PRO_SPI2_DMA_INT_MAP_V  0x1F
+#define DPORT_PRO_SPI2_DMA_INT_MAP_S  0
+
+#define DPORT_PRO_SPI3_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0E4)
+/* DPORT_PRO_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI3_DMA_INT_MAP  0x0000001F
+#define DPORT_PRO_SPI3_DMA_INT_MAP_M  ((DPORT_PRO_SPI3_DMA_INT_MAP_V)<<(DPORT_PRO_SPI3_DMA_INT_MAP_S))
+#define DPORT_PRO_SPI3_DMA_INT_MAP_V  0x1F
+#define DPORT_PRO_SPI3_DMA_INT_MAP_S  0
+
+#define DPORT_PRO_WDG_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0E8)
+/* DPORT_PRO_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_WDG_INT_MAP  0x0000001F
+#define DPORT_PRO_WDG_INT_MAP_M  ((DPORT_PRO_WDG_INT_MAP_V)<<(DPORT_PRO_WDG_INT_MAP_S))
+#define DPORT_PRO_WDG_INT_MAP_V  0x1F
+#define DPORT_PRO_WDG_INT_MAP_S  0
+
+#define DPORT_PRO_TIMER_INT1_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0EC)
+/* DPORT_PRO_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TIMER_INT1_MAP  0x0000001F
+#define DPORT_PRO_TIMER_INT1_MAP_M  ((DPORT_PRO_TIMER_INT1_MAP_V)<<(DPORT_PRO_TIMER_INT1_MAP_S))
+#define DPORT_PRO_TIMER_INT1_MAP_V  0x1F
+#define DPORT_PRO_TIMER_INT1_MAP_S  0
+
+#define DPORT_PRO_TIMER_INT2_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0F0)
+/* DPORT_PRO_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TIMER_INT2_MAP  0x0000001F
+#define DPORT_PRO_TIMER_INT2_MAP_M  ((DPORT_PRO_TIMER_INT2_MAP_V)<<(DPORT_PRO_TIMER_INT2_MAP_S))
+#define DPORT_PRO_TIMER_INT2_MAP_V  0x1F
+#define DPORT_PRO_TIMER_INT2_MAP_S  0
+
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0F4)
+/* DPORT_PRO_TG_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_M  ((DPORT_PRO_TG_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T0_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_T0_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0F8)
+/* DPORT_PRO_TG_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_M  ((DPORT_PRO_TG_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_T1_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_T1_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x0FC)
+/* DPORT_PRO_TG_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_M  ((DPORT_PRO_TG_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_WDT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_WDT_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x100)
+/* DPORT_PRO_TG_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_M  ((DPORT_PRO_TG_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG_LACT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG_LACT_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x104)
+/* DPORT_PRO_TG1_T0_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_T0_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T0_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_T0_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x108)
+/* DPORT_PRO_TG1_T1_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_T1_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_T1_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_T1_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x10C)
+/* DPORT_PRO_TG1_WDT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_WDT_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x110)
+/* DPORT_PRO_TG1_LACT_EDGE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP  0x0000001F
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_M  ((DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V)<<(DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S))
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_V  0x1F
+#define DPORT_PRO_TG1_LACT_EDGE_INT_MAP_S  0
+
+#define DPORT_PRO_CACHE_IA_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x114)
+/* DPORT_PRO_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_CACHE_IA_INT_MAP  0x0000001F
+#define DPORT_PRO_CACHE_IA_INT_MAP_M  ((DPORT_PRO_CACHE_IA_INT_MAP_V)<<(DPORT_PRO_CACHE_IA_INT_MAP_S))
+#define DPORT_PRO_CACHE_IA_INT_MAP_V  0x1F
+#define DPORT_PRO_CACHE_IA_INT_MAP_S  0
+
+#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x118)
+/* DPORT_PRO_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP  0x0000001F
+#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_M  ((DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S))
+#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_V  0x1F
+#define DPORT_PRO_SYSTIMER_TARGET0_INT_MAP_S  0
+
+#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x11C)
+/* DPORT_PRO_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP  0x0000001F
+#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_M  ((DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S))
+#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_V  0x1F
+#define DPORT_PRO_SYSTIMER_TARGET1_INT_MAP_S  0
+
+#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x120)
+/* DPORT_PRO_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP  0x0000001F
+#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_M  ((DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V)<<(DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S))
+#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_V  0x1F
+#define DPORT_PRO_SYSTIMER_TARGET2_INT_MAP_S  0
+
+#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x124)
+/* DPORT_PRO_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP  0x0000001F
+#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_M  ((DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V)<<(DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S))
+#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_V  0x1F
+#define DPORT_PRO_ASSIST_DEBUG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x128)
+/* DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_PRO_IRAM0_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x12C)
+/* DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_PRO_DRAM0_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x130)
+/* DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_PRO_DPORT_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x134)
+/* DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_PRO_AHB_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x138)
+/* DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_PRO_CACHE_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x13C)
+/* DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_DMA_APB_I_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x140)
+/* DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_DMA_RX_I_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x144)
+/* DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP  0x0000001F
+#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_M  ((DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V)<<(DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S))
+#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_V  0x1F
+#define DPORT_PRO_PMS_DMA_TX_I_ILG_INTR_MAP_S  0
+
+#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x148)
+/* DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP  0x0000001F
+#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_M  ((DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V)<<(DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S))
+#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_V  0x1F
+#define DPORT_PRO_SPI0_REJECT_CACHE_INTR_MAP_S  0
+
+#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x14C)
+/* DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP  0x0000001F
+#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_M  ((DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V)<<(DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S))
+#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_V  0x1F
+#define DPORT_PRO_SPI1_REJECT_CPU_INTR_MAP_S  0
+
+#define DPORT_PRO_DMA_COPY_INTR_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x150)
+/* DPORT_PRO_DMA_COPY_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_DMA_COPY_INTR_MAP  0x0000001F
+#define DPORT_PRO_DMA_COPY_INTR_MAP_M  ((DPORT_PRO_DMA_COPY_INTR_MAP_V)<<(DPORT_PRO_DMA_COPY_INTR_MAP_S))
+#define DPORT_PRO_DMA_COPY_INTR_MAP_V  0x1F
+#define DPORT_PRO_DMA_COPY_INTR_MAP_S  0
+
+#define DPORT_PRO_SPI4_DMA_INT_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x154)
+/* DPORT_PRO_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI4_DMA_INT_MAP  0x0000001F
+#define DPORT_PRO_SPI4_DMA_INT_MAP_M  ((DPORT_PRO_SPI4_DMA_INT_MAP_V)<<(DPORT_PRO_SPI4_DMA_INT_MAP_S))
+#define DPORT_PRO_SPI4_DMA_INT_MAP_V  0x1F
+#define DPORT_PRO_SPI4_DMA_INT_MAP_S  0
+
+#define DPORT_PRO_SPI_INTR_4_MAP_REG          (DR_REG_INTERRUPT_BASE + 0x158)
+/* DPORT_PRO_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
+/*description: */
+#define DPORT_PRO_SPI_INTR_4_MAP  0x0000001F
+#define DPORT_PRO_SPI_INTR_4_MAP_M  ((DPORT_PRO_SPI_INTR_4_MAP_V)<<(DPORT_PRO_SPI_INTR_4_MAP_S))
+#define DPORT_PRO_SPI_INTR_4_MAP_V  0x1F
+#define DPORT_PRO_SPI_INTR_4_MAP_S  0
+
+#define DPORT_PRO_INTR_STATUS_0_REG          (DR_REG_INTERRUPT_BASE + 0x15C)
+/* DPORT_PRO_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_INTR_STATUS_0  0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_0_M  ((DPORT_PRO_INTR_STATUS_0_V)<<(DPORT_PRO_INTR_STATUS_0_S))
+#define DPORT_PRO_INTR_STATUS_0_V  0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_0_S  0
+
+#define DPORT_PRO_INTR_STATUS_1_REG          (DR_REG_INTERRUPT_BASE + 0x160)
+/* DPORT_PRO_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_INTR_STATUS_1  0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_1_M  ((DPORT_PRO_INTR_STATUS_1_V)<<(DPORT_PRO_INTR_STATUS_1_S))
+#define DPORT_PRO_INTR_STATUS_1_V  0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_1_S  0
+
+#define DPORT_PRO_INTR_STATUS_2_REG          (DR_REG_INTERRUPT_BASE + 0x164)
+/* DPORT_PRO_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_PRO_INTR_STATUS_2  0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_2_M  ((DPORT_PRO_INTR_STATUS_2_V)<<(DPORT_PRO_INTR_STATUS_2_S))
+#define DPORT_PRO_INTR_STATUS_2_V  0xFFFFFFFF
+#define DPORT_PRO_INTR_STATUS_2_S  0
+
+#define INTERRUPT_CLOCK_GATE_REG          (DR_REG_INTERRUPT_BASE + 0x168)
+/* DPORT_PRO_NMI_MASK_HW : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_NMI_MASK_HW  (BIT(1))
+#define DPORT_PRO_NMI_MASK_HW_M  (BIT(1))
+#define DPORT_PRO_NMI_MASK_HW_V  0x1
+#define DPORT_PRO_NMI_MASK_HW_S  1
+/* INTERRUPT_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define INTERRUPT_CLK_EN  (BIT(0))
+#define INTERRUPT_CLK_EN_M  (BIT(0))
+#define INTERRUPT_CLK_EN_V  0x1
+#define INTERRUPT_CLK_EN_S  0
+
+#define INTERRUPT_DATE_REG          (DR_REG_INTERRUPT_BASE + 0xFFC)
+/* INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809110 ; */
+/*description: */
+#define INTERRUPT_DATE  0x0FFFFFFF
+#define INTERRUPT_DATE_M  ((INTERRUPT_DATE_V)<<(INTERRUPT_DATE_S))
+#define INTERRUPT_DATE_V  0xFFFFFFF
+#define INTERRUPT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_INTERRUPT_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/io_mux_reg.h b/components/soc/esp32s2beta/include/soc/io_mux_reg.h
new file mode 100644
index 000000000..da10d62d9
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/io_mux_reg.h
@@ -0,0 +1,391 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_IO_MUX_REG_H_
+#define _SOC_IO_MUX_REG_H_
+
+#include "soc.h"
+
+/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
+/* Output enable in sleep mode */
+#define SLP_OE (BIT(0))
+#define SLP_OE_M (BIT(0))
+#define SLP_OE_V 1
+#define SLP_OE_S 0
+/* Pin used for wakeup from sleep */
+#define SLP_SEL (BIT(1))
+#define SLP_SEL_M (BIT(1))
+#define SLP_SEL_V 1
+#define SLP_SEL_S 1
+/* Pulldown enable in sleep mode */
+#define SLP_PD (BIT(2))
+#define SLP_PD_M (BIT(2))
+#define SLP_PD_V 1
+#define SLP_PD_S 2
+/* Pullup enable in sleep mode */
+#define SLP_PU (BIT(3))
+#define SLP_PU_M (BIT(3))
+#define SLP_PU_V 1
+#define SLP_PU_S 3
+/* Input enable in sleep mode */
+#define SLP_IE (BIT(4))
+#define SLP_IE_M (BIT(4))
+#define SLP_IE_V 1
+#define SLP_IE_S 4
+/* Drive strength in sleep mode */
+#define SLP_DRV 0x3
+#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
+#define SLP_DRV_V 0x3
+#define SLP_DRV_S 5
+/* Pulldown enable */
+#define FUN_PD (BIT(7))
+#define FUN_PD_M (BIT(7))
+#define FUN_PD_V 1
+#define FUN_PD_S 7
+/* Pullup enable */
+#define FUN_PU (BIT(8))
+#define FUN_PU_M (BIT(8))
+#define FUN_PU_V 1
+#define FUN_PU_S 8
+/* Input enable */
+#define FUN_IE (BIT(9))
+#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
+#define FUN_IE_V 1
+#define FUN_IE_S 9
+/* Drive strength */
+#define FUN_DRV 0x3
+#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
+#define FUN_DRV_V 0x3
+#define FUN_DRV_S 10
+/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
+#define MCU_SEL 0x7
+#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
+#define MCU_SEL_V 0x7
+#define MCU_SEL_S 12
+
+#define PIN_INPUT_ENABLE(PIN_NAME)               SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_INPUT_DISABLE(PIN_NAME)              CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
+#define PIN_SET_DRV(PIN_NAME, drv)            REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
+#define PIN_PULLUP_DIS(PIN_NAME)                 REG_CLR_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLUP_EN(PIN_NAME)                  REG_SET_BIT(PIN_NAME, FUN_PU)
+#define PIN_PULLDWN_DIS(PIN_NAME)             REG_CLR_BIT(PIN_NAME, FUN_PD)
+#define PIN_PULLDWN_EN(PIN_NAME)              REG_SET_BIT(PIN_NAME, FUN_PD)
+#define PIN_FUNC_SELECT(PIN_NAME, FUNC)      REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
+
+#define IO_MUX_GPIO0_REG		PERIPHS_IO_MUX_GPIO0_U
+#define IO_MUX_GPIO1_REG		PERIPHS_IO_MUX_GPIO1_U
+#define IO_MUX_GPIO2_REG		PERIPHS_IO_MUX_GPIO2_U
+#define IO_MUX_GPIO3_REG		PERIPHS_IO_MUX_GPIO3_U
+#define IO_MUX_GPIO4_REG		PERIPHS_IO_MUX_GPIO4_U
+#define IO_MUX_GPIO5_REG		PERIPHS_IO_MUX_GPIO5_U
+#define IO_MUX_GPIO6_REG		PERIPHS_IO_MUX_GPIO6_U
+#define IO_MUX_GPIO7_REG		PERIPHS_IO_MUX_GPIO7_U
+#define IO_MUX_GPIO8_REG		PERIPHS_IO_MUX_GPIO8_U
+#define IO_MUX_GPIO9_REG		PERIPHS_IO_MUX_GPIO9_U
+#define IO_MUX_GPIO10_REG	PERIPHS_IO_MUX_GPIO10_U
+#define IO_MUX_GPIO11_REG	PERIPHS_IO_MUX_GPIO11_U
+#define IO_MUX_GPIO12_REG	PERIPHS_IO_MUX_GPIO12_U
+#define IO_MUX_GPIO13_REG	PERIPHS_IO_MUX_GPIO13_U
+#define IO_MUX_GPIO14_REG	PERIPHS_IO_MUX_GPIO14_U
+#define IO_MUX_GPIO15_REG	PERIPHS_IO_MUX_XTAL_32K_P_U
+#define IO_MUX_GPIO16_REG	PERIPHS_IO_MUX_XTAL_32K_N_U
+#define IO_MUX_GPIO17_REG	PERIPHS_IO_MUX_DAC_1_U
+#define IO_MUX_GPIO18_REG	PERIPHS_IO_MUX_DAC_2_U
+#define IO_MUX_GPIO19_REG	PERIPHS_IO_MUX_GPIO19_U
+#define IO_MUX_GPIO20_REG	PERIPHS_IO_MUX_GPIO20_U
+#define IO_MUX_GPIO21_REG	PERIPHS_IO_MUX_GPIO21_U
+#define IO_MUX_GPIO26_REG	PERIPHS_IO_MUX_SPICS1_U
+#define IO_MUX_GPIO27_REG	PERIPHS_IO_MUX_SPIHD_U
+#define IO_MUX_GPIO28_REG	PERIPHS_IO_MUX_SPIWP_U
+#define IO_MUX_GPIO29_REG	PERIPHS_IO_MUX_SPICS0_U
+#define IO_MUX_GPIO30_REG	PERIPHS_IO_MUX_SPICLK_U
+#define IO_MUX_GPIO31_REG	PERIPHS_IO_MUX_SPIQ_U
+#define IO_MUX_GPIO32_REG	PERIPHS_IO_MUX_SPID_U
+#define IO_MUX_GPIO33_REG	PERIPHS_IO_MUX_GPIO33_U
+#define IO_MUX_GPIO34_REG	PERIPHS_IO_MUX_GPIO34_U
+#define IO_MUX_GPIO35_REG	PERIPHS_IO_MUX_GPIO35_U
+#define IO_MUX_GPIO36_REG	PERIPHS_IO_MUX_GPIO36_U
+#define IO_MUX_GPIO37_REG	PERIPHS_IO_MUX_GPIO37_U
+#define IO_MUX_GPIO38_REG	PERIPHS_IO_MUX_GPIO38_U
+#define IO_MUX_GPIO39_REG	PERIPHS_IO_MUX_MTCK_U
+#define IO_MUX_GPIO40_REG	PERIPHS_IO_MUX_MTDO_U
+#define IO_MUX_GPIO41_REG	PERIPHS_IO_MUX_MTDI_U
+#define IO_MUX_GPIO42_REG	PERIPHS_IO_MUX_MTMS_U
+#define IO_MUX_GPIO43_REG	PERIPHS_IO_MUX_U0TXD_U
+#define IO_MUX_GPIO44_REG	PERIPHS_IO_MUX_U0RXD_U
+#define IO_MUX_GPIO45_REG	PERIPHS_IO_MUX_GPIO45_U
+#define IO_MUX_GPIO46_REG	PERIPHS_IO_MUX_GPIO46_U
+
+
+#define FUNC_GPIO_GPIO                              1
+#define PIN_FUNC_GPIO								1
+
+#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDOWN_EN(IOMUX_REG_GPIO##num);}while(0)
+#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
+
+#define U1RXD_GPIO_NUM 18
+#define U1TXD_GPIO_NUM 17
+#define U0RXD_GPIO_NUM 44
+#define U0TXD_GPIO_NUM 43
+
+#define SPI_CLK_GPIO_NUM 30
+#define SPI_Q_GPIO_NUM 31
+#define SPI_D_GPIO_NUM 32
+#define SPI_CS0_GPIO_NUM 29
+#define SPI_HD_GPIO_NUM 27
+#define SPI_WP_GPIO_NUM 28
+#define SD_CLK_GPIO_NUM 12
+#define SD_CMD_GPIO_NUM 11
+#define SD_DATA0_GPIO_NUM 13
+#define SD_DATA1_GPIO_NUM 14
+#define SD_DATA2_GPIO_NUM 9
+#define SD_DATA3_GPIO_NUM 10
+
+#define MAX_RTC_GPIO_NUM 21
+#define MAX_PAD_GPIO_NUM 46
+#define MAX_GPIO_NUM    53
+
+#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
+#define PIN_CTRL                          (REG_IO_MUX_BASE +0x00)
+#define CLK_OUT3                                    0xf
+#define CLK_OUT3_V                                  CLK_OUT3
+#define CLK_OUT3_S                                  8
+#define CLK_OUT3_M                                  (CLK_OUT3_V << CLK_OUT3_S)
+#define CLK_OUT2                                    0xf
+#define CLK_OUT2_V                                  CLK_OUT2
+#define CLK_OUT2_S                                  4
+#define CLK_OUT2_M                                  (CLK_OUT2_V << CLK_OUT2_S)
+#define CLK_OUT1                                    0xf
+#define CLK_OUT1_V                                  CLK_OUT1
+#define CLK_OUT1_S                                  0
+#define CLK_OUT1_M                                  (CLK_OUT1_V << CLK_OUT1_S)
+
+#define PERIPHS_IO_MUX_GPIO0_U            (REG_IO_MUX_BASE +0x04)
+#define FUNC_GPIO0_GPIO0                            1
+#define FUNC_GPIO0_GPIO0_0                          0
+
+#define PERIPHS_IO_MUX_GPIO1_U            (REG_IO_MUX_BASE +0x08)
+#define FUNC_GPIO1_GPIO1                            1
+#define FUNC_GPIO1_GPIO1_0                          0
+
+#define PERIPHS_IO_MUX_GPIO2_U            (REG_IO_MUX_BASE +0x0c)
+#define FUNC_GPIO2_GPIO2                            1
+#define FUNC_GPIO2_GPIO2_0                          0
+
+#define PERIPHS_IO_MUX_GPIO3_U            (REG_IO_MUX_BASE +0x10)
+#define FUNC_GPIO3_GPIO3                            1
+#define FUNC_GPIO3_GPIO3_0                          0
+
+#define PERIPHS_IO_MUX_GPIO4_U            (REG_IO_MUX_BASE +0x14)
+#define FUNC_GPIO4_GPIO4                            1
+#define FUNC_GPIO4_GPIO4_0                          0
+
+#define PERIPHS_IO_MUX_GPIO5_U            (REG_IO_MUX_BASE +0x18)
+#define FUNC_GPIO5_GPIO5                            1
+#define FUNC_GPIO5_GPIO5_0                          0
+
+#define PERIPHS_IO_MUX_GPIO6_U            (REG_IO_MUX_BASE +0x1c)
+#define FUNC_GPIO6_GPIO6                            1
+#define FUNC_GPIO6_GPIO6_0                          0
+
+#define PERIPHS_IO_MUX_GPIO7_U            (REG_IO_MUX_BASE +0x20)
+#define FUNC_GPIO7_GPIO7                            1
+#define FUNC_GPIO7_GPIO7_0                          0
+
+#define PERIPHS_IO_MUX_GPIO8_U            (REG_IO_MUX_BASE +0x24)
+#define FUNC_GPIO8_SUBSPICS1                        3
+#define FUNC_GPIO8_GPIO8                            1
+#define FUNC_GPIO8_GPIO8_0                          0
+
+#define PERIPHS_IO_MUX_GPIO9_U            (REG_IO_MUX_BASE +0x28)
+#define FUNC_GPIO9_SUBSPIHD                         3
+#define FUNC_GPIO9_FSPIHD                           2
+#define FUNC_GPIO9_GPIO9                            1
+#define FUNC_GPIO9_SD_DATA2                         0
+
+#define PERIPHS_IO_MUX_GPIO10_U           (REG_IO_MUX_BASE +0x2c)
+#define FUNC_GPIO10_SUBSPICS0                       3
+#define FUNC_GPIO10_FSPICS0                         2
+#define FUNC_GPIO10_GPIO10                          1
+#define FUNC_GPIO10_SD_DATA3                        0
+
+#define PERIPHS_IO_MUX_GPIO11_U           (REG_IO_MUX_BASE +0x30)
+#define FUNC_GPIO11_SUBSPID                         3
+#define FUNC_GPIO11_FSPID                           2
+#define FUNC_GPIO11_GPIO11                          1
+#define FUNC_GPIO11_SD_CMD                          0
+
+#define PERIPHS_IO_MUX_GPIO12_U           (REG_IO_MUX_BASE +0x34)
+#define FUNC_GPIO12_SUBSPICLK                       3
+#define FUNC_GPIO12_FSPICLK                         2
+#define FUNC_GPIO12_GPIO12                          1
+#define FUNC_GPIO12_SD_CLK                          0
+
+#define PERIPHS_IO_MUX_GPIO13_U           (REG_IO_MUX_BASE +0x38)
+#define FUNC_GPIO13_SUBSPIQ                         3
+#define FUNC_GPIO13_FSPIQ                           2
+#define FUNC_GPIO13_GPIO13                          1
+#define FUNC_GPIO13_SD_DATA0                        0
+
+#define PERIPHS_IO_MUX_GPIO14_U           (REG_IO_MUX_BASE +0x3c)
+#define FUNC_GPIO14_SUBSPIWP                        3
+#define FUNC_GPIO14_FSPIWP                          2
+#define FUNC_GPIO14_GPIO14                          1
+#define FUNC_GPIO14_SD_DATA1                        0
+
+#define PERIPHS_IO_MUX_XTAL_32K_P_U       (REG_IO_MUX_BASE +0x40)
+#define FUNC_XTAL_32K_P_U0RTS                       2
+#define FUNC_XTAL_32K_P_GPIO15                      1
+#define FUNC_XTAL_32K_P_GPIO15_0                    0
+
+#define PERIPHS_IO_MUX_XTAL_32K_N_U       (REG_IO_MUX_BASE +0x44)
+#define FUNC_XTAL_32K_N_U0CTS                       2
+#define FUNC_XTAL_32K_N_GPIO16                      1
+#define FUNC_XTAL_32K_N_GPIO16_0                    0
+
+#define PERIPHS_IO_MUX_DAC_1_U            (REG_IO_MUX_BASE +0x48)
+#define FUNC_DAC_1_U1TXD                            2
+#define FUNC_DAC_1_GPIO17                           1
+#define FUNC_DAC_1_GPIO17_0                         0
+
+#define PERIPHS_IO_MUX_DAC_2_U            (REG_IO_MUX_BASE +0x4c)
+#define FUNC_DAC_2_CLK_OUT3                         3
+#define FUNC_DAC_2_U1RXD                            2
+#define FUNC_DAC_2_GPIO18                           1
+#define FUNC_DAC_2_GPIO18_0                         0
+
+#define PERIPHS_IO_MUX_GPIO19_U           (REG_IO_MUX_BASE +0x50)
+#define FUNC_GPIO19_CLK_OUT2                        3
+#define FUNC_GPIO19_U1RTS                           2
+#define FUNC_GPIO19_GPIO19                          1
+#define FUNC_GPIO19_GPIO19_0                        0
+
+#define PERIPHS_IO_MUX_GPIO20_U           (REG_IO_MUX_BASE +0x54)
+#define FUNC_GPIO20_CLK_OUT1                        3
+#define FUNC_GPIO20_U1CTS                           2
+#define FUNC_GPIO20_GPIO20                          1
+#define FUNC_GPIO20_GPIO20_0                        0
+
+#define PERIPHS_IO_MUX_GPIO21_U           (REG_IO_MUX_BASE +0x58)
+#define FUNC_GPIO21_GPIO21                          1
+#define FUNC_GPIO21_GPIO21_0                        0
+
+#define PERIPHS_IO_MUX_SPICS1_U           (REG_IO_MUX_BASE +0x6c)
+#define FUNC_SPICS1_GPIO26                          1
+#define FUNC_SPICS1_SPICS1                          0
+
+#define PERIPHS_IO_MUX_SPIHD_U            (REG_IO_MUX_BASE +0x70)
+#define FUNC_SPIHD_GPIO27                           1
+#define FUNC_SPIHD_SPIHD                            0
+
+#define PERIPHS_IO_MUX_SPIWP_U            (REG_IO_MUX_BASE +0x74)
+#define FUNC_SPIWP_GPIO28                           1
+#define FUNC_SPIWP_SPIWP                            0
+
+#define PERIPHS_IO_MUX_SPICS0_U           (REG_IO_MUX_BASE +0x78)
+#define FUNC_SPICS0_GPIO29                          1
+#define FUNC_SPICS0_SPICS0                          0
+
+#define PERIPHS_IO_MUX_SPICLK_U           (REG_IO_MUX_BASE +0x7c)
+#define FUNC_SPICLK_GPIO30                          1
+#define FUNC_SPICLK_SPICLK                          0
+
+#define PERIPHS_IO_MUX_SPIQ_U             (REG_IO_MUX_BASE +0x80)
+#define FUNC_SPIQ_GPIO31                            1
+#define FUNC_SPIQ_SPIQ                              0
+
+#define PERIPHS_IO_MUX_SPID_U             (REG_IO_MUX_BASE +0x84)
+#define FUNC_SPID_GPIO32                            1
+#define FUNC_SPID_SPID                              0
+
+#define PERIPHS_IO_MUX_GPIO33_U           (REG_IO_MUX_BASE +0x88)
+#define FUNC_GPIO33_SUBSPIHD                        3
+#define FUNC_GPIO33_SD_DATA2                        2
+#define FUNC_GPIO33_GPIO33                          1
+#define FUNC_GPIO33_FSPIHD                          0
+
+#define PERIPHS_IO_MUX_GPIO34_U           (REG_IO_MUX_BASE +0x8c)
+#define FUNC_GPIO34_SUBSPICS0                       3
+#define FUNC_GPIO34_SD_DATA3                        2
+#define FUNC_GPIO34_GPIO34                          1
+#define FUNC_GPIO34_FSPICS0                         0
+
+#define PERIPHS_IO_MUX_GPIO35_U           (REG_IO_MUX_BASE +0x90)
+#define FUNC_GPIO35_SUBSPID                         3
+#define FUNC_GPIO35_SD_CMD                          2
+#define FUNC_GPIO35_GPIO35                          1
+#define FUNC_GPIO35_FSPID                           0
+
+#define PERIPHS_IO_MUX_GPIO36_U           (REG_IO_MUX_BASE +0x94)
+#define FUNC_GPIO36_SUBSPICLK                       3
+#define FUNC_GPIO36_SD_CLK                          2
+#define FUNC_GPIO36_GPIO36                          1
+#define FUNC_GPIO36_FSPICLK                         0
+
+#define PERIPHS_IO_MUX_GPIO37_U           (REG_IO_MUX_BASE +0x98)
+#define FUNC_GPIO37_SUBSPIQ                         3
+#define FUNC_GPIO37_SD_DATA0                        2
+#define FUNC_GPIO37_GPIO37                          1
+#define FUNC_GPIO37_FSPIQ                           0
+
+#define PERIPHS_IO_MUX_GPIO38_U           (REG_IO_MUX_BASE +0x9c)
+#define FUNC_GPIO38_SUBSPIWP                        3
+#define FUNC_GPIO38_SD_DATA1                        2
+#define FUNC_GPIO38_GPIO38                          1
+#define FUNC_GPIO38_FSPIWP                          0
+
+#define PERIPHS_IO_MUX_MTCK_U             (REG_IO_MUX_BASE +0xa0)
+#define FUNC_MTCK_SUBSPICS1                         3
+#define FUNC_MTCK_CLK_OUT3                          2
+#define FUNC_MTCK_GPIO39                            1
+#define FUNC_MTCK_MTCK                              0
+
+#define PERIPHS_IO_MUX_MTDO_U             (REG_IO_MUX_BASE +0xa4)
+#define FUNC_MTDO_CLK_OUT2                          2
+#define FUNC_MTDO_GPIO40                            1
+#define FUNC_MTDO_MTDO                              0
+
+#define PERIPHS_IO_MUX_MTDI_U             (REG_IO_MUX_BASE +0xa8)
+#define FUNC_MTDI_CLK_OUT1                          2
+#define FUNC_MTDI_GPIO41                            1
+#define FUNC_MTDI_MTDI                              0
+
+#define PERIPHS_IO_MUX_MTMS_U             (REG_IO_MUX_BASE +0xac)
+#define FUNC_MTMS_GPIO42                            1
+#define FUNC_MTMS_MTMS                              0
+
+#define PERIPHS_IO_MUX_U0TXD_U            (REG_IO_MUX_BASE +0xb0)
+#define FUNC_U0TXD_CLK_OUT1                         2
+#define FUNC_U0TXD_GPIO43                           1
+#define FUNC_U0TXD_U0TXD                            0
+
+#define PERIPHS_IO_MUX_U0RXD_U            (REG_IO_MUX_BASE +0xb4)
+#define FUNC_U0RXD_CLK_OUT2                         2
+#define FUNC_U0RXD_GPIO44                           1
+#define FUNC_U0RXD_U0RXD                            0
+
+#define PERIPHS_IO_MUX_GPIO45_U           (REG_IO_MUX_BASE +0xb8)
+#define FUNC_GPIO45_GPIO45                          1
+#define FUNC_GPIO45_GPIO45_0                        0
+
+#define PERIPHS_IO_MUX_GPIO46_U           (REG_IO_MUX_BASE +0xbc)
+#define FUNC_GPIO46_GPIO46                          1
+#define FUNC_GPIO46_GPIO46_0                        0
+
+#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
+#define IO_MUX_DATE 0xFFFFFFFF
+#define IO_MUX_DATE_S 0
+#define IO_MUX_DATE_VERSION 0x1809060
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/ledc_reg.h b/components/soc/esp32s2beta/include/soc/ledc_reg.h
new file mode 100644
index 000000000..f3fcdd03b
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/ledc_reg.h
@@ -0,0 +1,3002 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_LEDC_REG_H_
+#define _SOC_LEDC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define LEDC_HSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x0000)
+/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: This bit is clock gating control signal. when software config
+ LED_PWM internal registers  it controls the register clock.*/
+#define LEDC_CLK_EN  (BIT(31))
+#define LEDC_CLK_EN_M  (BIT(31))
+#define LEDC_CLK_EN_V  0x1
+#define LEDC_CLK_EN_S  31
+/* LEDC_OVF_CNT_EN_HSCH0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH0  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH0_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH0_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH0_S  14
+/* LEDC_OVF_NUM_HSCH0 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH0  0x000003FF
+#define LEDC_OVF_NUM_HSCH0_M  ((LEDC_OVF_NUM_HSCH0_V)<<(LEDC_OVF_NUM_HSCH0_S))
+#define LEDC_OVF_NUM_HSCH0_V  0x3FF
+#define LEDC_OVF_NUM_HSCH0_S  4
+/* LEDC_IDLE_LV_HSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel0 is off.*/
+#define LEDC_IDLE_LV_HSCH0  (BIT(3))
+#define LEDC_IDLE_LV_HSCH0_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH0_V  0x1
+#define LEDC_IDLE_LV_HSCH0_S  3
+/* LEDC_SIG_OUT_EN_HSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel0*/
+#define LEDC_SIG_OUT_EN_HSCH0  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH0_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH0_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH0_S  2
+/* LEDC_TIMER_SEL_HSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel0.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH0  0x00000003
+#define LEDC_TIMER_SEL_HSCH0_M  ((LEDC_TIMER_SEL_HSCH0_V)<<(LEDC_TIMER_SEL_HSCH0_S))
+#define LEDC_TIMER_SEL_HSCH0_V  0x3
+#define LEDC_TIMER_SEL_HSCH0_S  0
+
+#define LEDC_HSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0004)
+/* LEDC_HPOINT_HSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel0 has reached reg_hpoint_hsch0[19:0]*/
+#define LEDC_HPOINT_HSCH0  0x000FFFFF
+#define LEDC_HPOINT_HSCH0_M  ((LEDC_HPOINT_HSCH0_V)<<(LEDC_HPOINT_HSCH0_S))
+#define LEDC_HPOINT_HSCH0_V  0xFFFFF
+#define LEDC_HPOINT_HSCH0_S  0
+
+#define LEDC_HSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x0008)
+/* LEDC_DUTY_HSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel0  has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4])          (1)  reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH0  0x01FFFFFF
+#define LEDC_DUTY_HSCH0_M  ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
+#define LEDC_DUTY_HSCH0_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH0_S  0
+
+#define LEDC_HSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x000C)
+/* LEDC_DUTY_START_HSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0
+ has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH0  (BIT(31))
+#define LEDC_DUTY_START_HSCH0_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH0_V  0x1
+#define LEDC_DUTY_START_HSCH0_S  31
+/* LEDC_DUTY_INC_HSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel0.*/
+#define LEDC_DUTY_INC_HSCH0  (BIT(30))
+#define LEDC_DUTY_INC_HSCH0_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH0_V  0x1
+#define LEDC_DUTY_INC_HSCH0_S  30
+/* LEDC_DUTY_NUM_HSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel0.*/
+#define LEDC_DUTY_NUM_HSCH0  0x000003FF
+#define LEDC_DUTY_NUM_HSCH0_M  ((LEDC_DUTY_NUM_HSCH0_V)<<(LEDC_DUTY_NUM_HSCH0_S))
+#define LEDC_DUTY_NUM_HSCH0_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH0_S  20
+/* LEDC_DUTY_CYCLE_HSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch0 cycles for high speed channel0.*/
+#define LEDC_DUTY_CYCLE_HSCH0  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH0_M  ((LEDC_DUTY_CYCLE_HSCH0_V)<<(LEDC_DUTY_CYCLE_HSCH0_S))
+#define LEDC_DUTY_CYCLE_HSCH0_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH0_S  10
+/* LEDC_DUTY_SCALE_HSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel0.*/
+#define LEDC_DUTY_SCALE_HSCH0  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH0_M  ((LEDC_DUTY_SCALE_HSCH0_V)<<(LEDC_DUTY_SCALE_HSCH0_S))
+#define LEDC_DUTY_SCALE_HSCH0_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH0_S  0
+
+#define LEDC_HSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0010)
+/* LEDC_DUTY_HSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel0.*/
+#define LEDC_DUTY_HSCH0  0x01FFFFFF
+#define LEDC_DUTY_HSCH0_M  ((LEDC_DUTY_HSCH0_V)<<(LEDC_DUTY_HSCH0_S))
+#define LEDC_DUTY_HSCH0_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH0_S  0
+
+#define LEDC_HSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x0014)
+/* LEDC_OVF_CNT_EN_HSCH1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH1  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH1_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH1_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH1_S  14
+/* LEDC_OVF_NUM_HSCH1 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH1  0x000003FF
+#define LEDC_OVF_NUM_HSCH1_M  ((LEDC_OVF_NUM_HSCH1_V)<<(LEDC_OVF_NUM_HSCH1_S))
+#define LEDC_OVF_NUM_HSCH1_V  0x3FF
+#define LEDC_OVF_NUM_HSCH1_S  4
+/* LEDC_IDLE_LV_HSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel1 is off.*/
+#define LEDC_IDLE_LV_HSCH1  (BIT(3))
+#define LEDC_IDLE_LV_HSCH1_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH1_V  0x1
+#define LEDC_IDLE_LV_HSCH1_S  3
+/* LEDC_SIG_OUT_EN_HSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel1*/
+#define LEDC_SIG_OUT_EN_HSCH1  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH1_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH1_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH1_S  2
+/* LEDC_TIMER_SEL_HSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel1.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH1  0x00000003
+#define LEDC_TIMER_SEL_HSCH1_M  ((LEDC_TIMER_SEL_HSCH1_V)<<(LEDC_TIMER_SEL_HSCH1_S))
+#define LEDC_TIMER_SEL_HSCH1_V  0x3
+#define LEDC_TIMER_SEL_HSCH1_S  0
+
+#define LEDC_HSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0018)
+/* LEDC_HPOINT_HSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel1 has reached reg_hpoint_hsch1[19:0]*/
+#define LEDC_HPOINT_HSCH1  0x000FFFFF
+#define LEDC_HPOINT_HSCH1_M  ((LEDC_HPOINT_HSCH1_V)<<(LEDC_HPOINT_HSCH1_S))
+#define LEDC_HPOINT_HSCH1_V  0xFFFFF
+#define LEDC_HPOINT_HSCH1_S  0
+
+#define LEDC_HSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x001C)
+/* LEDC_DUTY_HSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel1 has reached reg_lpoint_hsch1 the output signal changes to low. reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4])          (1)  reg_lpoint_hsch1=(reg_hpoint_hsch1[19:0]+reg_duty_hsch1[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH1  0x01FFFFFF
+#define LEDC_DUTY_HSCH1_M  ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
+#define LEDC_DUTY_HSCH1_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH1_S  0
+
+#define LEDC_HSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x0020)
+/* LEDC_DUTY_START_HSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH1  (BIT(31))
+#define LEDC_DUTY_START_HSCH1_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH1_V  0x1
+#define LEDC_DUTY_START_HSCH1_S  31
+/* LEDC_DUTY_INC_HSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel1.*/
+#define LEDC_DUTY_INC_HSCH1  (BIT(30))
+#define LEDC_DUTY_INC_HSCH1_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH1_V  0x1
+#define LEDC_DUTY_INC_HSCH1_S  30
+/* LEDC_DUTY_NUM_HSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel1.*/
+#define LEDC_DUTY_NUM_HSCH1  0x000003FF
+#define LEDC_DUTY_NUM_HSCH1_M  ((LEDC_DUTY_NUM_HSCH1_V)<<(LEDC_DUTY_NUM_HSCH1_S))
+#define LEDC_DUTY_NUM_HSCH1_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH1_S  20
+/* LEDC_DUTY_CYCLE_HSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch1 cycles for high speed channel1.*/
+#define LEDC_DUTY_CYCLE_HSCH1  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH1_M  ((LEDC_DUTY_CYCLE_HSCH1_V)<<(LEDC_DUTY_CYCLE_HSCH1_S))
+#define LEDC_DUTY_CYCLE_HSCH1_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH1_S  10
+/* LEDC_DUTY_SCALE_HSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel1.*/
+#define LEDC_DUTY_SCALE_HSCH1  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH1_M  ((LEDC_DUTY_SCALE_HSCH1_V)<<(LEDC_DUTY_SCALE_HSCH1_S))
+#define LEDC_DUTY_SCALE_HSCH1_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH1_S  0
+
+#define LEDC_HSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0024)
+/* LEDC_DUTY_HSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel1.*/
+#define LEDC_DUTY_HSCH1  0x01FFFFFF
+#define LEDC_DUTY_HSCH1_M  ((LEDC_DUTY_HSCH1_V)<<(LEDC_DUTY_HSCH1_S))
+#define LEDC_DUTY_HSCH1_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH1_S  0
+
+#define LEDC_HSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x0028)
+/* LEDC_OVF_CNT_EN_HSCH2 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH2  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH2_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH2_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH2_S  14
+/* LEDC_OVF_NUM_HSCH2 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH2  0x000003FF
+#define LEDC_OVF_NUM_HSCH2_M  ((LEDC_OVF_NUM_HSCH2_V)<<(LEDC_OVF_NUM_HSCH2_S))
+#define LEDC_OVF_NUM_HSCH2_V  0x3FF
+#define LEDC_OVF_NUM_HSCH2_S  4
+/* LEDC_IDLE_LV_HSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel2 is off.*/
+#define LEDC_IDLE_LV_HSCH2  (BIT(3))
+#define LEDC_IDLE_LV_HSCH2_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH2_V  0x1
+#define LEDC_IDLE_LV_HSCH2_S  3
+/* LEDC_SIG_OUT_EN_HSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel2*/
+#define LEDC_SIG_OUT_EN_HSCH2  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH2_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH2_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH2_S  2
+/* LEDC_TIMER_SEL_HSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel2.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH2  0x00000003
+#define LEDC_TIMER_SEL_HSCH2_M  ((LEDC_TIMER_SEL_HSCH2_V)<<(LEDC_TIMER_SEL_HSCH2_S))
+#define LEDC_TIMER_SEL_HSCH2_V  0x3
+#define LEDC_TIMER_SEL_HSCH2_S  0
+
+#define LEDC_HSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x002C)
+/* LEDC_HPOINT_HSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel2 has reached reg_hpoint_hsch2[19:0]*/
+#define LEDC_HPOINT_HSCH2  0x000FFFFF
+#define LEDC_HPOINT_HSCH2_M  ((LEDC_HPOINT_HSCH2_V)<<(LEDC_HPOINT_HSCH2_S))
+#define LEDC_HPOINT_HSCH2_V  0xFFFFF
+#define LEDC_HPOINT_HSCH2_S  0
+
+#define LEDC_HSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x0030)
+/* LEDC_DUTY_HSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel2 has reached reg_lpoint_hsch2 the output signal changes to low. reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4])          (1)  reg_lpoint_hsch2=(reg_hpoint_hsch2[19:0]+reg_duty_hsch2[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH2  0x01FFFFFF
+#define LEDC_DUTY_HSCH2_M  ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
+#define LEDC_DUTY_HSCH2_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH2_S  0
+
+#define LEDC_HSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x0034)
+/* LEDC_DUTY_START_HSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2
+ has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH2  (BIT(31))
+#define LEDC_DUTY_START_HSCH2_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH2_V  0x1
+#define LEDC_DUTY_START_HSCH2_S  31
+/* LEDC_DUTY_INC_HSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel2.*/
+#define LEDC_DUTY_INC_HSCH2  (BIT(30))
+#define LEDC_DUTY_INC_HSCH2_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH2_V  0x1
+#define LEDC_DUTY_INC_HSCH2_S  30
+/* LEDC_DUTY_NUM_HSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel2.*/
+#define LEDC_DUTY_NUM_HSCH2  0x000003FF
+#define LEDC_DUTY_NUM_HSCH2_M  ((LEDC_DUTY_NUM_HSCH2_V)<<(LEDC_DUTY_NUM_HSCH2_S))
+#define LEDC_DUTY_NUM_HSCH2_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH2_S  20
+/* LEDC_DUTY_CYCLE_HSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch2 cycles for high speed channel2.*/
+#define LEDC_DUTY_CYCLE_HSCH2  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH2_M  ((LEDC_DUTY_CYCLE_HSCH2_V)<<(LEDC_DUTY_CYCLE_HSCH2_S))
+#define LEDC_DUTY_CYCLE_HSCH2_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH2_S  10
+/* LEDC_DUTY_SCALE_HSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel2.*/
+#define LEDC_DUTY_SCALE_HSCH2  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH2_M  ((LEDC_DUTY_SCALE_HSCH2_V)<<(LEDC_DUTY_SCALE_HSCH2_S))
+#define LEDC_DUTY_SCALE_HSCH2_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH2_S  0
+
+#define LEDC_HSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0038)
+/* LEDC_DUTY_HSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel2.*/
+#define LEDC_DUTY_HSCH2  0x01FFFFFF
+#define LEDC_DUTY_HSCH2_M  ((LEDC_DUTY_HSCH2_V)<<(LEDC_DUTY_HSCH2_S))
+#define LEDC_DUTY_HSCH2_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH2_S  0
+
+#define LEDC_HSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x003C)
+/* LEDC_OVF_CNT_EN_HSCH3 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH3  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH3_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH3_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH3_S  14
+/* LEDC_OVF_NUM_HSCH3 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH3  0x000003FF
+#define LEDC_OVF_NUM_HSCH3_M  ((LEDC_OVF_NUM_HSCH3_V)<<(LEDC_OVF_NUM_HSCH3_S))
+#define LEDC_OVF_NUM_HSCH3_V  0x3FF
+#define LEDC_OVF_NUM_HSCH3_S  4
+/* LEDC_IDLE_LV_HSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel3 is off.*/
+#define LEDC_IDLE_LV_HSCH3  (BIT(3))
+#define LEDC_IDLE_LV_HSCH3_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH3_V  0x1
+#define LEDC_IDLE_LV_HSCH3_S  3
+/* LEDC_SIG_OUT_EN_HSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel3*/
+#define LEDC_SIG_OUT_EN_HSCH3  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH3_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH3_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH3_S  2
+/* LEDC_TIMER_SEL_HSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel3.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH3  0x00000003
+#define LEDC_TIMER_SEL_HSCH3_M  ((LEDC_TIMER_SEL_HSCH3_V)<<(LEDC_TIMER_SEL_HSCH3_S))
+#define LEDC_TIMER_SEL_HSCH3_V  0x3
+#define LEDC_TIMER_SEL_HSCH3_S  0
+
+#define LEDC_HSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0040)
+/* LEDC_HPOINT_HSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel3 has reached reg_hpoint_hsch3[19:0]*/
+#define LEDC_HPOINT_HSCH3  0x000FFFFF
+#define LEDC_HPOINT_HSCH3_M  ((LEDC_HPOINT_HSCH3_V)<<(LEDC_HPOINT_HSCH3_S))
+#define LEDC_HPOINT_HSCH3_V  0xFFFFF
+#define LEDC_HPOINT_HSCH3_S  0
+
+#define LEDC_HSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x0044)
+/* LEDC_DUTY_HSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel3 has reached reg_lpoint_hsch3 the output signal changes to low. reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4])          (1)  reg_lpoint_hsch3=(reg_hpoint_hsch3[19:0]+reg_duty_hsch3[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH3  0x01FFFFFF
+#define LEDC_DUTY_HSCH3_M  ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
+#define LEDC_DUTY_HSCH3_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH3_S  0
+
+#define LEDC_HSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x0048)
+/* LEDC_DUTY_START_HSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3
+ has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH3  (BIT(31))
+#define LEDC_DUTY_START_HSCH3_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH3_V  0x1
+#define LEDC_DUTY_START_HSCH3_S  31
+/* LEDC_DUTY_INC_HSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel3.*/
+#define LEDC_DUTY_INC_HSCH3  (BIT(30))
+#define LEDC_DUTY_INC_HSCH3_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH3_V  0x1
+#define LEDC_DUTY_INC_HSCH3_S  30
+/* LEDC_DUTY_NUM_HSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel3.*/
+#define LEDC_DUTY_NUM_HSCH3  0x000003FF
+#define LEDC_DUTY_NUM_HSCH3_M  ((LEDC_DUTY_NUM_HSCH3_V)<<(LEDC_DUTY_NUM_HSCH3_S))
+#define LEDC_DUTY_NUM_HSCH3_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH3_S  20
+/* LEDC_DUTY_CYCLE_HSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch3 cycles for high speed channel3.*/
+#define LEDC_DUTY_CYCLE_HSCH3  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH3_M  ((LEDC_DUTY_CYCLE_HSCH3_V)<<(LEDC_DUTY_CYCLE_HSCH3_S))
+#define LEDC_DUTY_CYCLE_HSCH3_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH3_S  10
+/* LEDC_DUTY_SCALE_HSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel3.*/
+#define LEDC_DUTY_SCALE_HSCH3  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH3_M  ((LEDC_DUTY_SCALE_HSCH3_V)<<(LEDC_DUTY_SCALE_HSCH3_S))
+#define LEDC_DUTY_SCALE_HSCH3_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH3_S  0
+
+#define LEDC_HSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x004C)
+/* LEDC_DUTY_HSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel3.*/
+#define LEDC_DUTY_HSCH3  0x01FFFFFF
+#define LEDC_DUTY_HSCH3_M  ((LEDC_DUTY_HSCH3_V)<<(LEDC_DUTY_HSCH3_S))
+#define LEDC_DUTY_HSCH3_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH3_S  0
+
+#define LEDC_HSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x0050)
+/* LEDC_OVF_CNT_EN_HSCH4 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH4  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH4_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH4_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH4_S  14
+/* LEDC_OVF_NUM_HSCH4 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH4  0x000003FF
+#define LEDC_OVF_NUM_HSCH4_M  ((LEDC_OVF_NUM_HSCH4_V)<<(LEDC_OVF_NUM_HSCH4_S))
+#define LEDC_OVF_NUM_HSCH4_V  0x3FF
+#define LEDC_OVF_NUM_HSCH4_S  4
+/* LEDC_IDLE_LV_HSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel4 is off.*/
+#define LEDC_IDLE_LV_HSCH4  (BIT(3))
+#define LEDC_IDLE_LV_HSCH4_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH4_V  0x1
+#define LEDC_IDLE_LV_HSCH4_S  3
+/* LEDC_SIG_OUT_EN_HSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel4*/
+#define LEDC_SIG_OUT_EN_HSCH4  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH4_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH4_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH4_S  2
+/* LEDC_TIMER_SEL_HSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel4.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH4  0x00000003
+#define LEDC_TIMER_SEL_HSCH4_M  ((LEDC_TIMER_SEL_HSCH4_V)<<(LEDC_TIMER_SEL_HSCH4_S))
+#define LEDC_TIMER_SEL_HSCH4_V  0x3
+#define LEDC_TIMER_SEL_HSCH4_S  0
+
+#define LEDC_HSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0054)
+/* LEDC_HPOINT_HSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel4 has reached reg_hpoint_hsch4[19:0]*/
+#define LEDC_HPOINT_HSCH4  0x000FFFFF
+#define LEDC_HPOINT_HSCH4_M  ((LEDC_HPOINT_HSCH4_V)<<(LEDC_HPOINT_HSCH4_S))
+#define LEDC_HPOINT_HSCH4_V  0xFFFFF
+#define LEDC_HPOINT_HSCH4_S  0
+
+#define LEDC_HSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x0058)
+/* LEDC_DUTY_HSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel4 has reached reg_lpoint_hsch4 the output signal changes to low. reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4])          (1)  reg_lpoint_hsch4=(reg_hpoint_hsch4[19:0]+reg_duty_hsch4[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH4  0x01FFFFFF
+#define LEDC_DUTY_HSCH4_M  ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
+#define LEDC_DUTY_HSCH4_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH4_S  0
+
+#define LEDC_HSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x005C)
+/* LEDC_DUTY_START_HSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH4  (BIT(31))
+#define LEDC_DUTY_START_HSCH4_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH4_V  0x1
+#define LEDC_DUTY_START_HSCH4_S  31
+/* LEDC_DUTY_INC_HSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel4.*/
+#define LEDC_DUTY_INC_HSCH4  (BIT(30))
+#define LEDC_DUTY_INC_HSCH4_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH4_V  0x1
+#define LEDC_DUTY_INC_HSCH4_S  30
+/* LEDC_DUTY_NUM_HSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel1.*/
+#define LEDC_DUTY_NUM_HSCH4  0x000003FF
+#define LEDC_DUTY_NUM_HSCH4_M  ((LEDC_DUTY_NUM_HSCH4_V)<<(LEDC_DUTY_NUM_HSCH4_S))
+#define LEDC_DUTY_NUM_HSCH4_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH4_S  20
+/* LEDC_DUTY_CYCLE_HSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch4 cycles for high speed channel4.*/
+#define LEDC_DUTY_CYCLE_HSCH4  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH4_M  ((LEDC_DUTY_CYCLE_HSCH4_V)<<(LEDC_DUTY_CYCLE_HSCH4_S))
+#define LEDC_DUTY_CYCLE_HSCH4_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH4_S  10
+/* LEDC_DUTY_SCALE_HSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel4.*/
+#define LEDC_DUTY_SCALE_HSCH4  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH4_M  ((LEDC_DUTY_SCALE_HSCH4_V)<<(LEDC_DUTY_SCALE_HSCH4_S))
+#define LEDC_DUTY_SCALE_HSCH4_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH4_S  0
+
+#define LEDC_HSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0060)
+/* LEDC_DUTY_HSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel4.*/
+#define LEDC_DUTY_HSCH4  0x01FFFFFF
+#define LEDC_DUTY_HSCH4_M  ((LEDC_DUTY_HSCH4_V)<<(LEDC_DUTY_HSCH4_S))
+#define LEDC_DUTY_HSCH4_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH4_S  0
+
+#define LEDC_HSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0064)
+/* LEDC_OVF_CNT_EN_HSCH5 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH5  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH5_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH5_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH5_S  14
+/* LEDC_OVF_NUM_HSCH5 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH5  0x000003FF
+#define LEDC_OVF_NUM_HSCH5_M  ((LEDC_OVF_NUM_HSCH5_V)<<(LEDC_OVF_NUM_HSCH5_S))
+#define LEDC_OVF_NUM_HSCH5_V  0x3FF
+#define LEDC_OVF_NUM_HSCH5_S  4
+/* LEDC_IDLE_LV_HSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel5 is off.*/
+#define LEDC_IDLE_LV_HSCH5  (BIT(3))
+#define LEDC_IDLE_LV_HSCH5_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH5_V  0x1
+#define LEDC_IDLE_LV_HSCH5_S  3
+/* LEDC_SIG_OUT_EN_HSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel5.*/
+#define LEDC_SIG_OUT_EN_HSCH5  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH5_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH5_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH5_S  2
+/* LEDC_TIMER_SEL_HSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel5.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH5  0x00000003
+#define LEDC_TIMER_SEL_HSCH5_M  ((LEDC_TIMER_SEL_HSCH5_V)<<(LEDC_TIMER_SEL_HSCH5_S))
+#define LEDC_TIMER_SEL_HSCH5_V  0x3
+#define LEDC_TIMER_SEL_HSCH5_S  0
+
+#define LEDC_HSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0068)
+/* LEDC_HPOINT_HSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel5 has reached reg_hpoint_hsch5[19:0]*/
+#define LEDC_HPOINT_HSCH5  0x000FFFFF
+#define LEDC_HPOINT_HSCH5_M  ((LEDC_HPOINT_HSCH5_V)<<(LEDC_HPOINT_HSCH5_S))
+#define LEDC_HPOINT_HSCH5_V  0xFFFFF
+#define LEDC_HPOINT_HSCH5_S  0
+
+#define LEDC_HSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x006C)
+/* LEDC_DUTY_HSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel5 has reached reg_lpoint_hsch5 the output signal changes to low. reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4])          (1)  reg_lpoint_hsch5=(reg_hpoint_hsch5[19:0]+reg_duty_hsch5[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH5  0x01FFFFFF
+#define LEDC_DUTY_HSCH5_M  ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
+#define LEDC_DUTY_HSCH5_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH5_S  0
+
+#define LEDC_HSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0070)
+/* LEDC_DUTY_START_HSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch5 reg_duty_cycle_hsch5 and reg_duty_scale_hsch5
+ has been configured. these register won't take effect until set reg_duty_start_hsch5. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH5  (BIT(31))
+#define LEDC_DUTY_START_HSCH5_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH5_V  0x1
+#define LEDC_DUTY_START_HSCH5_S  31
+/* LEDC_DUTY_INC_HSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel5.*/
+#define LEDC_DUTY_INC_HSCH5  (BIT(30))
+#define LEDC_DUTY_INC_HSCH5_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH5_V  0x1
+#define LEDC_DUTY_INC_HSCH5_S  30
+/* LEDC_DUTY_NUM_HSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel5.*/
+#define LEDC_DUTY_NUM_HSCH5  0x000003FF
+#define LEDC_DUTY_NUM_HSCH5_M  ((LEDC_DUTY_NUM_HSCH5_V)<<(LEDC_DUTY_NUM_HSCH5_S))
+#define LEDC_DUTY_NUM_HSCH5_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH5_S  20
+/* LEDC_DUTY_CYCLE_HSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch5 cycles for high speed channel5.*/
+#define LEDC_DUTY_CYCLE_HSCH5  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH5_M  ((LEDC_DUTY_CYCLE_HSCH5_V)<<(LEDC_DUTY_CYCLE_HSCH5_S))
+#define LEDC_DUTY_CYCLE_HSCH5_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH5_S  10
+/* LEDC_DUTY_SCALE_HSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel5.*/
+#define LEDC_DUTY_SCALE_HSCH5  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH5_M  ((LEDC_DUTY_SCALE_HSCH5_V)<<(LEDC_DUTY_SCALE_HSCH5_S))
+#define LEDC_DUTY_SCALE_HSCH5_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH5_S  0
+
+#define LEDC_HSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0074)
+/* LEDC_DUTY_HSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel5.*/
+#define LEDC_DUTY_HSCH5  0x01FFFFFF
+#define LEDC_DUTY_HSCH5_M  ((LEDC_DUTY_HSCH5_V)<<(LEDC_DUTY_HSCH5_S))
+#define LEDC_DUTY_HSCH5_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH5_S  0
+
+#define LEDC_HSCH6_CONF0_REG          (DR_REG_LEDC_BASE + 0x0078)
+/* LEDC_OVF_CNT_EN_HSCH6 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH6  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH6_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH6_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH6_S  14
+/* LEDC_OVF_NUM_HSCH6 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH6  0x000003FF
+#define LEDC_OVF_NUM_HSCH6_M  ((LEDC_OVF_NUM_HSCH6_V)<<(LEDC_OVF_NUM_HSCH6_S))
+#define LEDC_OVF_NUM_HSCH6_V  0x3FF
+#define LEDC_OVF_NUM_HSCH6_S  4
+/* LEDC_IDLE_LV_HSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel6 is off.*/
+#define LEDC_IDLE_LV_HSCH6  (BIT(3))
+#define LEDC_IDLE_LV_HSCH6_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH6_V  0x1
+#define LEDC_IDLE_LV_HSCH6_S  3
+/* LEDC_SIG_OUT_EN_HSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel6*/
+#define LEDC_SIG_OUT_EN_HSCH6  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH6_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH6_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH6_S  2
+/* LEDC_TIMER_SEL_HSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel6.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH6  0x00000003
+#define LEDC_TIMER_SEL_HSCH6_M  ((LEDC_TIMER_SEL_HSCH6_V)<<(LEDC_TIMER_SEL_HSCH6_S))
+#define LEDC_TIMER_SEL_HSCH6_V  0x3
+#define LEDC_TIMER_SEL_HSCH6_S  0
+
+#define LEDC_HSCH6_HPOINT_REG          (DR_REG_LEDC_BASE + 0x007C)
+/* LEDC_HPOINT_HSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel6 has reached reg_hpoint_hsch6[19:0]*/
+#define LEDC_HPOINT_HSCH6  0x000FFFFF
+#define LEDC_HPOINT_HSCH6_M  ((LEDC_HPOINT_HSCH6_V)<<(LEDC_HPOINT_HSCH6_S))
+#define LEDC_HPOINT_HSCH6_V  0xFFFFF
+#define LEDC_HPOINT_HSCH6_S  0
+
+#define LEDC_HSCH6_DUTY_REG          (DR_REG_LEDC_BASE + 0x0080)
+/* LEDC_DUTY_HSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel6 has reached reg_lpoint_hsch6 the output signal changes to low. reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4])          (1)  reg_lpoint_hsch6=(reg_hpoint_hsch6[19:0]+reg_duty_hsch6[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH6  0x01FFFFFF
+#define LEDC_DUTY_HSCH6_M  ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
+#define LEDC_DUTY_HSCH6_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH6_S  0
+
+#define LEDC_HSCH6_CONF1_REG          (DR_REG_LEDC_BASE + 0x0084)
+/* LEDC_DUTY_START_HSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH6  (BIT(31))
+#define LEDC_DUTY_START_HSCH6_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH6_V  0x1
+#define LEDC_DUTY_START_HSCH6_S  31
+/* LEDC_DUTY_INC_HSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel6.*/
+#define LEDC_DUTY_INC_HSCH6  (BIT(30))
+#define LEDC_DUTY_INC_HSCH6_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH6_V  0x1
+#define LEDC_DUTY_INC_HSCH6_S  30
+/* LEDC_DUTY_NUM_HSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel6.*/
+#define LEDC_DUTY_NUM_HSCH6  0x000003FF
+#define LEDC_DUTY_NUM_HSCH6_M  ((LEDC_DUTY_NUM_HSCH6_V)<<(LEDC_DUTY_NUM_HSCH6_S))
+#define LEDC_DUTY_NUM_HSCH6_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH6_S  20
+/* LEDC_DUTY_CYCLE_HSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch6 cycles for high speed channel6.*/
+#define LEDC_DUTY_CYCLE_HSCH6  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH6_M  ((LEDC_DUTY_CYCLE_HSCH6_V)<<(LEDC_DUTY_CYCLE_HSCH6_S))
+#define LEDC_DUTY_CYCLE_HSCH6_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH6_S  10
+/* LEDC_DUTY_SCALE_HSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel6.*/
+#define LEDC_DUTY_SCALE_HSCH6  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH6_M  ((LEDC_DUTY_SCALE_HSCH6_V)<<(LEDC_DUTY_SCALE_HSCH6_S))
+#define LEDC_DUTY_SCALE_HSCH6_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH6_S  0
+
+#define LEDC_HSCH6_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0088)
+/* LEDC_DUTY_HSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel6.*/
+#define LEDC_DUTY_HSCH6  0x01FFFFFF
+#define LEDC_DUTY_HSCH6_M  ((LEDC_DUTY_HSCH6_V)<<(LEDC_DUTY_HSCH6_S))
+#define LEDC_DUTY_HSCH6_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH6_S  0
+
+#define LEDC_HSCH7_CONF0_REG          (DR_REG_LEDC_BASE + 0x008C)
+/* LEDC_OVF_CNT_EN_HSCH7 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_HSCH7  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH7_M  (BIT(14))
+#define LEDC_OVF_CNT_EN_HSCH7_V  0x1
+#define LEDC_OVF_CNT_EN_HSCH7_S  14
+/* LEDC_OVF_NUM_HSCH7 : R/W ;bitpos:[13:4] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_HSCH7  0x000003FF
+#define LEDC_OVF_NUM_HSCH7_M  ((LEDC_OVF_NUM_HSCH7_V)<<(LEDC_OVF_NUM_HSCH7_S))
+#define LEDC_OVF_NUM_HSCH7_V  0x3FF
+#define LEDC_OVF_NUM_HSCH7_S  4
+/* LEDC_IDLE_LV_HSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when high speed channel7 is off.*/
+#define LEDC_IDLE_LV_HSCH7  (BIT(3))
+#define LEDC_IDLE_LV_HSCH7_M  (BIT(3))
+#define LEDC_IDLE_LV_HSCH7_V  0x1
+#define LEDC_IDLE_LV_HSCH7_S  3
+/* LEDC_SIG_OUT_EN_HSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for high speed channel7.*/
+#define LEDC_SIG_OUT_EN_HSCH7  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH7_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_HSCH7_V  0x1
+#define LEDC_SIG_OUT_EN_HSCH7_S  2
+/* LEDC_TIMER_SEL_HSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four high speed timers  the two bits are used to select
+ one of them for high speed channel7.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+#define LEDC_TIMER_SEL_HSCH7  0x00000003
+#define LEDC_TIMER_SEL_HSCH7_M  ((LEDC_TIMER_SEL_HSCH7_V)<<(LEDC_TIMER_SEL_HSCH7_S))
+#define LEDC_TIMER_SEL_HSCH7_V  0x3
+#define LEDC_TIMER_SEL_HSCH7_S  0
+
+#define LEDC_HSCH7_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0090)
+/* LEDC_HPOINT_HSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when htimerx(x=[0 3]) selected
+ by high speed channel7 has reached reg_hpoint_hsch7[19:0]*/
+#define LEDC_HPOINT_HSCH7  0x000FFFFF
+#define LEDC_HPOINT_HSCH7_M  ((LEDC_HPOINT_HSCH7_V)<<(LEDC_HPOINT_HSCH7_S))
+#define LEDC_HPOINT_HSCH7_V  0xFFFFF
+#define LEDC_HPOINT_HSCH7_S  0
+
+#define LEDC_HSCH7_DUTY_REG          (DR_REG_LEDC_BASE + 0x0094)
+/* LEDC_DUTY_HSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When hstimerx(x=[0
+ 3]) choosed by high speed channel7 has reached reg_lpoint_hsch7 the output signal changes to low. reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4])          (1)  reg_lpoint_hsch7=(reg_hpoint_hsch7[19:0]+reg_duty_hsch7[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_HSCH7  0x01FFFFFF
+#define LEDC_DUTY_HSCH7_M  ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
+#define LEDC_DUTY_HSCH7_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH7_S  0
+
+#define LEDC_HSCH7_CONF1_REG          (DR_REG_LEDC_BASE + 0x0098)
+/* LEDC_DUTY_START_HSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_HSCH7  (BIT(31))
+#define LEDC_DUTY_START_HSCH7_M  (BIT(31))
+#define LEDC_DUTY_START_HSCH7_V  0x1
+#define LEDC_DUTY_START_HSCH7_S  31
+/* LEDC_DUTY_INC_HSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for high speed channel6.*/
+#define LEDC_DUTY_INC_HSCH7  (BIT(30))
+#define LEDC_DUTY_INC_HSCH7_M  (BIT(30))
+#define LEDC_DUTY_INC_HSCH7_V  0x1
+#define LEDC_DUTY_INC_HSCH7_S  30
+/* LEDC_DUTY_NUM_HSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for high speed channel6.*/
+#define LEDC_DUTY_NUM_HSCH7  0x000003FF
+#define LEDC_DUTY_NUM_HSCH7_M  ((LEDC_DUTY_NUM_HSCH7_V)<<(LEDC_DUTY_NUM_HSCH7_S))
+#define LEDC_DUTY_NUM_HSCH7_V  0x3FF
+#define LEDC_DUTY_NUM_HSCH7_S  20
+/* LEDC_DUTY_CYCLE_HSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_hsch7 cycles for high speed channel7.*/
+#define LEDC_DUTY_CYCLE_HSCH7  0x000003FF
+#define LEDC_DUTY_CYCLE_HSCH7_M  ((LEDC_DUTY_CYCLE_HSCH7_V)<<(LEDC_DUTY_CYCLE_HSCH7_S))
+#define LEDC_DUTY_CYCLE_HSCH7_V  0x3FF
+#define LEDC_DUTY_CYCLE_HSCH7_S  10
+/* LEDC_DUTY_SCALE_HSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ high speed channel7.*/
+#define LEDC_DUTY_SCALE_HSCH7  0x000003FF
+#define LEDC_DUTY_SCALE_HSCH7_M  ((LEDC_DUTY_SCALE_HSCH7_V)<<(LEDC_DUTY_SCALE_HSCH7_S))
+#define LEDC_DUTY_SCALE_HSCH7_V  0x3FF
+#define LEDC_DUTY_SCALE_HSCH7_S  0
+
+#define LEDC_HSCH7_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x009C)
+/* LEDC_DUTY_HSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for high speed channel7.*/
+#define LEDC_DUTY_HSCH7  0x01FFFFFF
+#define LEDC_DUTY_HSCH7_M  ((LEDC_DUTY_HSCH7_V)<<(LEDC_DUTY_HSCH7_S))
+#define LEDC_DUTY_HSCH7_V  0x1FFFFFF
+#define LEDC_DUTY_HSCH7_S  0
+
+#define LEDC_LSCH0_CONF0_REG          (DR_REG_LEDC_BASE + 0x00A0)
+/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH0  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH0_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH0_S  15
+/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH0  0x000003FF
+#define LEDC_OVF_NUM_LSCH0_M  ((LEDC_OVF_NUM_LSCH0_V)<<(LEDC_OVF_NUM_LSCH0_S))
+#define LEDC_OVF_NUM_LSCH0_V  0x3FF
+#define LEDC_OVF_NUM_LSCH0_S  5
+/* LEDC_PARA_UP_LSCH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH0_HPOINT and LEDC_LSCH0_DUTY
+ for low speed channel0.*/
+#define LEDC_PARA_UP_LSCH0  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH0_V  0x1
+#define LEDC_PARA_UP_LSCH0_S  4
+/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel0 is off.*/
+#define LEDC_IDLE_LV_LSCH0  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH0_V  0x1
+#define LEDC_IDLE_LV_LSCH0_S  3
+/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel0.*/
+#define LEDC_SIG_OUT_EN_LSCH0  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH0_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH0_S  2
+/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel0.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH0  0x00000003
+#define LEDC_TIMER_SEL_LSCH0_M  ((LEDC_TIMER_SEL_LSCH0_V)<<(LEDC_TIMER_SEL_LSCH0_S))
+#define LEDC_TIMER_SEL_LSCH0_V  0x3
+#define LEDC_TIMER_SEL_LSCH0_S  0
+
+#define LEDC_LSCH0_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00A4)
+/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel0 has reached reg_hpoint_lsch0[19:0]*/
+#define LEDC_HPOINT_LSCH0  0x000FFFFF
+#define LEDC_HPOINT_LSCH0_M  ((LEDC_HPOINT_LSCH0_V)<<(LEDC_HPOINT_LSCH0_S))
+#define LEDC_HPOINT_LSCH0_V  0xFFFFF
+#define LEDC_HPOINT_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_REG          (DR_REG_LEDC_BASE + 0x00A8)
+/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel0 has reached reg_lpoint_lsch0 the output signal changes to low. reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4])          (1)  reg_lpoint_lsch0=(reg_hpoint_lsch0[19:0]+reg_duty_lsch0[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH0  0x01FFFFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH0_CONF1_REG          (DR_REG_LEDC_BASE + 0x00AC)
+/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH0  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH0_V  0x1
+#define LEDC_DUTY_START_LSCH0_S  31
+/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel6.*/
+#define LEDC_DUTY_INC_LSCH0  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH0_V  0x1
+#define LEDC_DUTY_INC_LSCH0_S  30
+/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel6.*/
+#define LEDC_DUTY_NUM_LSCH0  0x000003FF
+#define LEDC_DUTY_NUM_LSCH0_M  ((LEDC_DUTY_NUM_LSCH0_V)<<(LEDC_DUTY_NUM_LSCH0_S))
+#define LEDC_DUTY_NUM_LSCH0_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH0_S  20
+/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch0 cycles for low speed channel0.*/
+#define LEDC_DUTY_CYCLE_LSCH0  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH0_M  ((LEDC_DUTY_CYCLE_LSCH0_V)<<(LEDC_DUTY_CYCLE_LSCH0_S))
+#define LEDC_DUTY_CYCLE_LSCH0_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH0_S  10
+/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel0.*/
+#define LEDC_DUTY_SCALE_LSCH0  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH0_M  ((LEDC_DUTY_SCALE_LSCH0_V)<<(LEDC_DUTY_SCALE_LSCH0_S))
+#define LEDC_DUTY_SCALE_LSCH0_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH0_S  0
+
+#define LEDC_LSCH0_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00B0)
+/* LEDC_DUTY_LSCH0 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel0.*/
+#define LEDC_DUTY_LSCH0  0x01FFFFFF
+#define LEDC_DUTY_LSCH0_M  ((LEDC_DUTY_LSCH0_V)<<(LEDC_DUTY_LSCH0_S))
+#define LEDC_DUTY_LSCH0_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH0_S  0
+
+#define LEDC_LSCH1_CONF0_REG          (DR_REG_LEDC_BASE + 0x00B4)
+/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH1  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH1_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH1_S  15
+/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH1  0x000003FF
+#define LEDC_OVF_NUM_LSCH1_M  ((LEDC_OVF_NUM_LSCH1_V)<<(LEDC_OVF_NUM_LSCH1_S))
+#define LEDC_OVF_NUM_LSCH1_V  0x3FF
+#define LEDC_OVF_NUM_LSCH1_S  5
+/* LEDC_PARA_UP_LSCH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH1_HPOINT and LEDC_LSCH1_DUTY
+ for low speed channel1.*/
+#define LEDC_PARA_UP_LSCH1  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH1_V  0x1
+#define LEDC_PARA_UP_LSCH1_S  4
+/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel1 is off.*/
+#define LEDC_IDLE_LV_LSCH1  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH1_V  0x1
+#define LEDC_IDLE_LV_LSCH1_S  3
+/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel1.*/
+#define LEDC_SIG_OUT_EN_LSCH1  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH1_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH1_S  2
+/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel1.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH1  0x00000003
+#define LEDC_TIMER_SEL_LSCH1_M  ((LEDC_TIMER_SEL_LSCH1_V)<<(LEDC_TIMER_SEL_LSCH1_S))
+#define LEDC_TIMER_SEL_LSCH1_V  0x3
+#define LEDC_TIMER_SEL_LSCH1_S  0
+
+#define LEDC_LSCH1_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00B8)
+/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel1 has reached reg_hpoint_lsch1[19:0]*/
+#define LEDC_HPOINT_LSCH1  0x000FFFFF
+#define LEDC_HPOINT_LSCH1_M  ((LEDC_HPOINT_LSCH1_V)<<(LEDC_HPOINT_LSCH1_S))
+#define LEDC_HPOINT_LSCH1_V  0xFFFFF
+#define LEDC_HPOINT_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_REG          (DR_REG_LEDC_BASE + 0x00BC)
+/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel1 has reached reg_lpoint_lsch1 the output signal changes to low. reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4])          (1)  reg_lpoint_lsch1=(reg_hpoint_lsch1[19:0]+reg_duty_lsch1[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH1  0x01FFFFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH1_CONF1_REG          (DR_REG_LEDC_BASE + 0x00C0)
+/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch1 reg_duty_cycle_hsch1 and reg_duty_scale_hsch1
+ has been configured. these register won't take effect until set reg_duty_start_hsch1. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH1  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH1_V  0x1
+#define LEDC_DUTY_START_LSCH1_S  31
+/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel1.*/
+#define LEDC_DUTY_INC_LSCH1  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH1_V  0x1
+#define LEDC_DUTY_INC_LSCH1_S  30
+/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel1.*/
+#define LEDC_DUTY_NUM_LSCH1  0x000003FF
+#define LEDC_DUTY_NUM_LSCH1_M  ((LEDC_DUTY_NUM_LSCH1_V)<<(LEDC_DUTY_NUM_LSCH1_S))
+#define LEDC_DUTY_NUM_LSCH1_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH1_S  20
+/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch1 cycles for low speed channel1.*/
+#define LEDC_DUTY_CYCLE_LSCH1  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH1_M  ((LEDC_DUTY_CYCLE_LSCH1_V)<<(LEDC_DUTY_CYCLE_LSCH1_S))
+#define LEDC_DUTY_CYCLE_LSCH1_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH1_S  10
+/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel1.*/
+#define LEDC_DUTY_SCALE_LSCH1  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH1_M  ((LEDC_DUTY_SCALE_LSCH1_V)<<(LEDC_DUTY_SCALE_LSCH1_S))
+#define LEDC_DUTY_SCALE_LSCH1_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH1_S  0
+
+#define LEDC_LSCH1_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00C4)
+/* LEDC_DUTY_LSCH1 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel1.*/
+#define LEDC_DUTY_LSCH1  0x01FFFFFF
+#define LEDC_DUTY_LSCH1_M  ((LEDC_DUTY_LSCH1_V)<<(LEDC_DUTY_LSCH1_S))
+#define LEDC_DUTY_LSCH1_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH1_S  0
+
+#define LEDC_LSCH2_CONF0_REG          (DR_REG_LEDC_BASE + 0x00C8)
+/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH2  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH2_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH2_S  15
+/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH2  0x000003FF
+#define LEDC_OVF_NUM_LSCH2_M  ((LEDC_OVF_NUM_LSCH2_V)<<(LEDC_OVF_NUM_LSCH2_S))
+#define LEDC_OVF_NUM_LSCH2_V  0x3FF
+#define LEDC_OVF_NUM_LSCH2_S  5
+/* LEDC_PARA_UP_LSCH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH2_HPOINT and LEDC_LSCH2_DUTY
+ for low speed channel2.*/
+#define LEDC_PARA_UP_LSCH2  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH2_V  0x1
+#define LEDC_PARA_UP_LSCH2_S  4
+/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel2 is off.*/
+#define LEDC_IDLE_LV_LSCH2  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH2_V  0x1
+#define LEDC_IDLE_LV_LSCH2_S  3
+/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel2.*/
+#define LEDC_SIG_OUT_EN_LSCH2  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH2_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH2_S  2
+/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel2.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH2  0x00000003
+#define LEDC_TIMER_SEL_LSCH2_M  ((LEDC_TIMER_SEL_LSCH2_V)<<(LEDC_TIMER_SEL_LSCH2_S))
+#define LEDC_TIMER_SEL_LSCH2_V  0x3
+#define LEDC_TIMER_SEL_LSCH2_S  0
+
+#define LEDC_LSCH2_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00CC)
+/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel2 has reached reg_hpoint_lsch2[19:0]*/
+#define LEDC_HPOINT_LSCH2  0x000FFFFF
+#define LEDC_HPOINT_LSCH2_M  ((LEDC_HPOINT_LSCH2_V)<<(LEDC_HPOINT_LSCH2_S))
+#define LEDC_HPOINT_LSCH2_V  0xFFFFF
+#define LEDC_HPOINT_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_REG          (DR_REG_LEDC_BASE + 0x00D0)
+/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel2 has reached reg_lpoint_lsch2 the output signal changes to low. reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4])          (1)  reg_lpoint_lsch2=(reg_hpoint_lsch2[19:0]+reg_duty_lsch2[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH2  0x01FFFFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH2_CONF1_REG          (DR_REG_LEDC_BASE + 0x00D4)
+/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch2 reg_duty_cycle_hsch2 and reg_duty_scale_hsch2
+ has been configured. these register won't take effect until set reg_duty_start_hsch2. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH2  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH2_V  0x1
+#define LEDC_DUTY_START_LSCH2_S  31
+/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel2.*/
+#define LEDC_DUTY_INC_LSCH2  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH2_V  0x1
+#define LEDC_DUTY_INC_LSCH2_S  30
+/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel2.*/
+#define LEDC_DUTY_NUM_LSCH2  0x000003FF
+#define LEDC_DUTY_NUM_LSCH2_M  ((LEDC_DUTY_NUM_LSCH2_V)<<(LEDC_DUTY_NUM_LSCH2_S))
+#define LEDC_DUTY_NUM_LSCH2_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH2_S  20
+/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch2 cycles for low speed channel2.*/
+#define LEDC_DUTY_CYCLE_LSCH2  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH2_M  ((LEDC_DUTY_CYCLE_LSCH2_V)<<(LEDC_DUTY_CYCLE_LSCH2_S))
+#define LEDC_DUTY_CYCLE_LSCH2_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH2_S  10
+/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel2.*/
+#define LEDC_DUTY_SCALE_LSCH2  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH2_M  ((LEDC_DUTY_SCALE_LSCH2_V)<<(LEDC_DUTY_SCALE_LSCH2_S))
+#define LEDC_DUTY_SCALE_LSCH2_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH2_S  0
+
+#define LEDC_LSCH2_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00D8)
+/* LEDC_DUTY_LSCH2 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel2.*/
+#define LEDC_DUTY_LSCH2  0x01FFFFFF
+#define LEDC_DUTY_LSCH2_M  ((LEDC_DUTY_LSCH2_V)<<(LEDC_DUTY_LSCH2_S))
+#define LEDC_DUTY_LSCH2_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH2_S  0
+
+#define LEDC_LSCH3_CONF0_REG          (DR_REG_LEDC_BASE + 0x00DC)
+/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH3  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH3_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH3_S  15
+/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH3  0x000003FF
+#define LEDC_OVF_NUM_LSCH3_M  ((LEDC_OVF_NUM_LSCH3_V)<<(LEDC_OVF_NUM_LSCH3_S))
+#define LEDC_OVF_NUM_LSCH3_V  0x3FF
+#define LEDC_OVF_NUM_LSCH3_S  5
+/* LEDC_PARA_UP_LSCH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH3_HPOINT and LEDC_LSCH3_DUTY
+ for low speed channel3.*/
+#define LEDC_PARA_UP_LSCH3  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH3_V  0x1
+#define LEDC_PARA_UP_LSCH3_S  4
+/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel3 is off.*/
+#define LEDC_IDLE_LV_LSCH3  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH3_V  0x1
+#define LEDC_IDLE_LV_LSCH3_S  3
+/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel3.*/
+#define LEDC_SIG_OUT_EN_LSCH3  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH3_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH3_S  2
+/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel3.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH3  0x00000003
+#define LEDC_TIMER_SEL_LSCH3_M  ((LEDC_TIMER_SEL_LSCH3_V)<<(LEDC_TIMER_SEL_LSCH3_S))
+#define LEDC_TIMER_SEL_LSCH3_V  0x3
+#define LEDC_TIMER_SEL_LSCH3_S  0
+
+#define LEDC_LSCH3_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00E0)
+/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel3 has reached reg_hpoint_lsch3[19:0]*/
+#define LEDC_HPOINT_LSCH3  0x000FFFFF
+#define LEDC_HPOINT_LSCH3_M  ((LEDC_HPOINT_LSCH3_V)<<(LEDC_HPOINT_LSCH3_S))
+#define LEDC_HPOINT_LSCH3_V  0xFFFFF
+#define LEDC_HPOINT_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_REG          (DR_REG_LEDC_BASE + 0x00E4)
+/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel3 has reached reg_lpoint_lsch3 the output signal changes to low. reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4])          (1)  reg_lpoint_lsch3=(reg_hpoint_lsch3[19:0]+reg_duty_lsch3[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH3  0x01FFFFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH3_CONF1_REG          (DR_REG_LEDC_BASE + 0x00E8)
+/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch3 reg_duty_cycle_hsch3 and reg_duty_scale_hsch3
+ has been configured. these register won't take effect until set reg_duty_start_hsch3. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH3  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH3_V  0x1
+#define LEDC_DUTY_START_LSCH3_S  31
+/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel3.*/
+#define LEDC_DUTY_INC_LSCH3  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH3_V  0x1
+#define LEDC_DUTY_INC_LSCH3_S  30
+/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel3.*/
+#define LEDC_DUTY_NUM_LSCH3  0x000003FF
+#define LEDC_DUTY_NUM_LSCH3_M  ((LEDC_DUTY_NUM_LSCH3_V)<<(LEDC_DUTY_NUM_LSCH3_S))
+#define LEDC_DUTY_NUM_LSCH3_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH3_S  20
+/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch3 cycles for low speed channel3.*/
+#define LEDC_DUTY_CYCLE_LSCH3  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH3_M  ((LEDC_DUTY_CYCLE_LSCH3_V)<<(LEDC_DUTY_CYCLE_LSCH3_S))
+#define LEDC_DUTY_CYCLE_LSCH3_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH3_S  10
+/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel3.*/
+#define LEDC_DUTY_SCALE_LSCH3  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH3_M  ((LEDC_DUTY_SCALE_LSCH3_V)<<(LEDC_DUTY_SCALE_LSCH3_S))
+#define LEDC_DUTY_SCALE_LSCH3_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH3_S  0
+
+#define LEDC_LSCH3_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x00EC)
+/* LEDC_DUTY_LSCH3 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel3.*/
+#define LEDC_DUTY_LSCH3  0x01FFFFFF
+#define LEDC_DUTY_LSCH3_M  ((LEDC_DUTY_LSCH3_V)<<(LEDC_DUTY_LSCH3_S))
+#define LEDC_DUTY_LSCH3_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH3_S  0
+
+#define LEDC_LSCH4_CONF0_REG          (DR_REG_LEDC_BASE + 0x00F0)
+/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH4  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH4_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH4_S  15
+/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH4  0x000003FF
+#define LEDC_OVF_NUM_LSCH4_M  ((LEDC_OVF_NUM_LSCH4_V)<<(LEDC_OVF_NUM_LSCH4_S))
+#define LEDC_OVF_NUM_LSCH4_V  0x3FF
+#define LEDC_OVF_NUM_LSCH4_S  5
+/* LEDC_PARA_UP_LSCH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH4_HPOINT and LEDC_LSCH4_DUTY
+ for low speed channel4.*/
+#define LEDC_PARA_UP_LSCH4  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH4_V  0x1
+#define LEDC_PARA_UP_LSCH4_S  4
+/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel4 is off.*/
+#define LEDC_IDLE_LV_LSCH4  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH4_V  0x1
+#define LEDC_IDLE_LV_LSCH4_S  3
+/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel4.*/
+#define LEDC_SIG_OUT_EN_LSCH4  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH4_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH4_S  2
+/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel4.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH4  0x00000003
+#define LEDC_TIMER_SEL_LSCH4_M  ((LEDC_TIMER_SEL_LSCH4_V)<<(LEDC_TIMER_SEL_LSCH4_S))
+#define LEDC_TIMER_SEL_LSCH4_V  0x3
+#define LEDC_TIMER_SEL_LSCH4_S  0
+
+#define LEDC_LSCH4_HPOINT_REG          (DR_REG_LEDC_BASE + 0x00F4)
+/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel4 has reached reg_hpoint_lsch4[19:0]*/
+#define LEDC_HPOINT_LSCH4  0x000FFFFF
+#define LEDC_HPOINT_LSCH4_M  ((LEDC_HPOINT_LSCH4_V)<<(LEDC_HPOINT_LSCH4_S))
+#define LEDC_HPOINT_LSCH4_V  0xFFFFF
+#define LEDC_HPOINT_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_REG          (DR_REG_LEDC_BASE + 0x00F8)
+/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel4 has reached reg_lpoint_lsch4 the output signal changes to low. reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4])          (1)  reg_lpoint_lsch4=(reg_hpoint_lsch4[19:0]+reg_duty_lsch4[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH4  0x01FFFFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH4_CONF1_REG          (DR_REG_LEDC_BASE + 0x00FC)
+/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch4  reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH4  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH4_V  0x1
+#define LEDC_DUTY_START_LSCH4_S  31
+/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel4.*/
+#define LEDC_DUTY_INC_LSCH4  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH4_V  0x1
+#define LEDC_DUTY_INC_LSCH4_S  30
+/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel4.*/
+#define LEDC_DUTY_NUM_LSCH4  0x000003FF
+#define LEDC_DUTY_NUM_LSCH4_M  ((LEDC_DUTY_NUM_LSCH4_V)<<(LEDC_DUTY_NUM_LSCH4_S))
+#define LEDC_DUTY_NUM_LSCH4_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH4_S  20
+/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch4 cycles for low speed channel4.*/
+#define LEDC_DUTY_CYCLE_LSCH4  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH4_M  ((LEDC_DUTY_CYCLE_LSCH4_V)<<(LEDC_DUTY_CYCLE_LSCH4_S))
+#define LEDC_DUTY_CYCLE_LSCH4_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH4_S  10
+/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel4.*/
+#define LEDC_DUTY_SCALE_LSCH4  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH4_M  ((LEDC_DUTY_SCALE_LSCH4_V)<<(LEDC_DUTY_SCALE_LSCH4_S))
+#define LEDC_DUTY_SCALE_LSCH4_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH4_S  0
+
+#define LEDC_LSCH4_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0100)
+/* LEDC_DUTY_LSCH4 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel4.*/
+#define LEDC_DUTY_LSCH4  0x01FFFFFF
+#define LEDC_DUTY_LSCH4_M  ((LEDC_DUTY_LSCH4_V)<<(LEDC_DUTY_LSCH4_S))
+#define LEDC_DUTY_LSCH4_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH4_S  0
+
+#define LEDC_LSCH5_CONF0_REG          (DR_REG_LEDC_BASE + 0x0104)
+/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH5  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH5_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH5_S  15
+/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH5  0x000003FF
+#define LEDC_OVF_NUM_LSCH5_M  ((LEDC_OVF_NUM_LSCH5_V)<<(LEDC_OVF_NUM_LSCH5_S))
+#define LEDC_OVF_NUM_LSCH5_V  0x3FF
+#define LEDC_OVF_NUM_LSCH5_S  5
+/* LEDC_PARA_UP_LSCH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH5_HPOINT and LEDC_LSCH5_DUTY
+ for low speed channel5.*/
+#define LEDC_PARA_UP_LSCH5  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH5_V  0x1
+#define LEDC_PARA_UP_LSCH5_S  4
+/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel5 is off.*/
+#define LEDC_IDLE_LV_LSCH5  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH5_V  0x1
+#define LEDC_IDLE_LV_LSCH5_S  3
+/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel5.*/
+#define LEDC_SIG_OUT_EN_LSCH5  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH5_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH5_S  2
+/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel5.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH5  0x00000003
+#define LEDC_TIMER_SEL_LSCH5_M  ((LEDC_TIMER_SEL_LSCH5_V)<<(LEDC_TIMER_SEL_LSCH5_S))
+#define LEDC_TIMER_SEL_LSCH5_V  0x3
+#define LEDC_TIMER_SEL_LSCH5_S  0
+
+#define LEDC_LSCH5_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0108)
+/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel5 has reached reg_hpoint_lsch5[19:0]*/
+#define LEDC_HPOINT_LSCH5  0x000FFFFF
+#define LEDC_HPOINT_LSCH5_M  ((LEDC_HPOINT_LSCH5_V)<<(LEDC_HPOINT_LSCH5_S))
+#define LEDC_HPOINT_LSCH5_V  0xFFFFF
+#define LEDC_HPOINT_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_REG          (DR_REG_LEDC_BASE + 0x010C)
+/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel5 has reached reg_lpoint_lsch5 the output signal changes to low. reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4])          (1)  reg_lpoint_lsch5=(reg_hpoint_lsch5[19:0]+reg_duty_lsch5[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH5  0x01FFFFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSCH5_CONF1_REG          (DR_REG_LEDC_BASE + 0x0110)
+/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch4  reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH5  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH5_V  0x1
+#define LEDC_DUTY_START_LSCH5_S  31
+/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel5.*/
+#define LEDC_DUTY_INC_LSCH5  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH5_V  0x1
+#define LEDC_DUTY_INC_LSCH5_S  30
+/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel5.*/
+#define LEDC_DUTY_NUM_LSCH5  0x000003FF
+#define LEDC_DUTY_NUM_LSCH5_M  ((LEDC_DUTY_NUM_LSCH5_V)<<(LEDC_DUTY_NUM_LSCH5_S))
+#define LEDC_DUTY_NUM_LSCH5_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH5_S  20
+/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch5 cycles for low speed channel4.*/
+#define LEDC_DUTY_CYCLE_LSCH5  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH5_M  ((LEDC_DUTY_CYCLE_LSCH5_V)<<(LEDC_DUTY_CYCLE_LSCH5_S))
+#define LEDC_DUTY_CYCLE_LSCH5_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH5_S  10
+/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel5.*/
+#define LEDC_DUTY_SCALE_LSCH5  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH5_M  ((LEDC_DUTY_SCALE_LSCH5_V)<<(LEDC_DUTY_SCALE_LSCH5_S))
+#define LEDC_DUTY_SCALE_LSCH5_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH5_S  0
+
+#define LEDC_LSCH5_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0114)
+/* LEDC_DUTY_LSCH5 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel5.*/
+#define LEDC_DUTY_LSCH5  0x01FFFFFF
+#define LEDC_DUTY_LSCH5_M  ((LEDC_DUTY_LSCH5_V)<<(LEDC_DUTY_LSCH5_S))
+#define LEDC_DUTY_LSCH5_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH5_S  0
+
+#define LEDC_LSCH6_CONF0_REG          (DR_REG_LEDC_BASE + 0x0118)
+/* LEDC_OVF_CNT_EN_LSCH6 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH6  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH6_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH6_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH6_S  15
+/* LEDC_OVF_NUM_LSCH6 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH6  0x000003FF
+#define LEDC_OVF_NUM_LSCH6_M  ((LEDC_OVF_NUM_LSCH6_V)<<(LEDC_OVF_NUM_LSCH6_S))
+#define LEDC_OVF_NUM_LSCH6_V  0x3FF
+#define LEDC_OVF_NUM_LSCH6_S  5
+/* LEDC_PARA_UP_LSCH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH6_HPOINT and LEDC_LSCH6_DUTY
+ for low speed channel6.*/
+#define LEDC_PARA_UP_LSCH6  (BIT(4))
+#define LEDC_PARA_UP_LSCH6_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH6_V  0x1
+#define LEDC_PARA_UP_LSCH6_S  4
+/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel6 is off.*/
+#define LEDC_IDLE_LV_LSCH6  (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH6_V  0x1
+#define LEDC_IDLE_LV_LSCH6_S  3
+/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel6.*/
+#define LEDC_SIG_OUT_EN_LSCH6  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH6_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH6_S  2
+/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel6.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH6  0x00000003
+#define LEDC_TIMER_SEL_LSCH6_M  ((LEDC_TIMER_SEL_LSCH6_V)<<(LEDC_TIMER_SEL_LSCH6_S))
+#define LEDC_TIMER_SEL_LSCH6_V  0x3
+#define LEDC_TIMER_SEL_LSCH6_S  0
+
+#define LEDC_LSCH6_HPOINT_REG          (DR_REG_LEDC_BASE + 0x011C)
+/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel6 has reached reg_hpoint_lsch6[19:0]*/
+#define LEDC_HPOINT_LSCH6  0x000FFFFF
+#define LEDC_HPOINT_LSCH6_M  ((LEDC_HPOINT_LSCH6_V)<<(LEDC_HPOINT_LSCH6_S))
+#define LEDC_HPOINT_LSCH6_V  0xFFFFF
+#define LEDC_HPOINT_LSCH6_S  0
+
+#define LEDC_LSCH6_DUTY_REG          (DR_REG_LEDC_BASE + 0x0120)
+/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel6 has reached reg_lpoint_lsch6 the output signal changes to low. reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4])          (1)  reg_lpoint_lsch6=(reg_hpoint_lsch6[19:0]+reg_duty_lsch6[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH6  0x01FFFFFF
+#define LEDC_DUTY_LSCH6_M  ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH6_S  0
+
+#define LEDC_LSCH6_CONF1_REG          (DR_REG_LEDC_BASE + 0x0124)
+/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch6  reg_duty_cycle_hsch6 and reg_duty_scale_hsch6
+ has been configured. these register won't take effect until set reg_duty_start_hsch6. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH6  (BIT(31))
+#define LEDC_DUTY_START_LSCH6_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH6_V  0x1
+#define LEDC_DUTY_START_LSCH6_S  31
+/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel6.*/
+#define LEDC_DUTY_INC_LSCH6  (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH6_V  0x1
+#define LEDC_DUTY_INC_LSCH6_S  30
+/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel6.*/
+#define LEDC_DUTY_NUM_LSCH6  0x000003FF
+#define LEDC_DUTY_NUM_LSCH6_M  ((LEDC_DUTY_NUM_LSCH6_V)<<(LEDC_DUTY_NUM_LSCH6_S))
+#define LEDC_DUTY_NUM_LSCH6_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH6_S  20
+/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch6 cycles for low speed channel6.*/
+#define LEDC_DUTY_CYCLE_LSCH6  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH6_M  ((LEDC_DUTY_CYCLE_LSCH6_V)<<(LEDC_DUTY_CYCLE_LSCH6_S))
+#define LEDC_DUTY_CYCLE_LSCH6_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH6_S  10
+/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel6.*/
+#define LEDC_DUTY_SCALE_LSCH6  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH6_M  ((LEDC_DUTY_SCALE_LSCH6_V)<<(LEDC_DUTY_SCALE_LSCH6_S))
+#define LEDC_DUTY_SCALE_LSCH6_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH6_S  0
+
+#define LEDC_LSCH6_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x0128)
+/* LEDC_DUTY_LSCH6 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel6.*/
+#define LEDC_DUTY_LSCH6  0x01FFFFFF
+#define LEDC_DUTY_LSCH6_M  ((LEDC_DUTY_LSCH6_V)<<(LEDC_DUTY_LSCH6_S))
+#define LEDC_DUTY_LSCH6_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH6_S  0
+
+#define LEDC_LSCH7_CONF0_REG          (DR_REG_LEDC_BASE + 0x012C)
+/* LEDC_OVF_CNT_EN_LSCH7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_EN_LSCH7  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH7_M  (BIT(15))
+#define LEDC_OVF_CNT_EN_LSCH7_V  0x1
+#define LEDC_OVF_CNT_EN_LSCH7_S  15
+/* LEDC_OVF_NUM_LSCH7 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */
+/*description: */
+#define LEDC_OVF_NUM_LSCH7  0x000003FF
+#define LEDC_OVF_NUM_LSCH7_M  ((LEDC_OVF_NUM_LSCH7_V)<<(LEDC_OVF_NUM_LSCH7_S))
+#define LEDC_OVF_NUM_LSCH7_V  0x3FF
+#define LEDC_OVF_NUM_LSCH7_S  5
+/* LEDC_PARA_UP_LSCH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This bit is used to update register LEDC_LSCH7_HPOINT and LEDC_LSCH7_DUTY
+ for low speed channel7.*/
+#define LEDC_PARA_UP_LSCH7  (BIT(4))
+#define LEDC_PARA_UP_LSCH7_M  (BIT(4))
+#define LEDC_PARA_UP_LSCH7_V  0x1
+#define LEDC_PARA_UP_LSCH7_S  4
+/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This bit is used to control the output value when low speed channel7 is off.*/
+#define LEDC_IDLE_LV_LSCH7  (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_M  (BIT(3))
+#define LEDC_IDLE_LV_LSCH7_V  0x1
+#define LEDC_IDLE_LV_LSCH7_S  3
+/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for low speed channel7.*/
+#define LEDC_SIG_OUT_EN_LSCH7  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_M  (BIT(2))
+#define LEDC_SIG_OUT_EN_LSCH7_V  0x1
+#define LEDC_SIG_OUT_EN_LSCH7_S  2
+/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: There are four low speed timers  the two bits are used to select
+ one of them for low speed channel7.  2'b00: seletc lstimer0.   2'b01: select lstimer1.  2'b10: select lstimer2.    2'b11: select lstimer3.*/
+#define LEDC_TIMER_SEL_LSCH7  0x00000003
+#define LEDC_TIMER_SEL_LSCH7_M  ((LEDC_TIMER_SEL_LSCH7_V)<<(LEDC_TIMER_SEL_LSCH7_S))
+#define LEDC_TIMER_SEL_LSCH7_V  0x3
+#define LEDC_TIMER_SEL_LSCH7_S  0
+
+#define LEDC_LSCH7_HPOINT_REG          (DR_REG_LEDC_BASE + 0x0130)
+/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The output value changes to high when lstimerx(x=[0 3]) selected
+ by low speed channel7 has reached reg_hpoint_lsch7[19:0]*/
+#define LEDC_HPOINT_LSCH7  0x000FFFFF
+#define LEDC_HPOINT_LSCH7_M  ((LEDC_HPOINT_LSCH7_V)<<(LEDC_HPOINT_LSCH7_S))
+#define LEDC_HPOINT_LSCH7_V  0xFFFFF
+#define LEDC_HPOINT_LSCH7_S  0
+
+#define LEDC_LSCH7_DUTY_REG          (DR_REG_LEDC_BASE + 0x0134)
+/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: The register is used to control output duty. When lstimerx(x=[0
+ 3]) choosed by low speed channel7 has reached reg_lpoint_lsch7 the output signal changes to low. reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4])          (1)  reg_lpoint_lsch7=(reg_hpoint_lsch7[19:0]+reg_duty_lsch7[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+#define LEDC_DUTY_LSCH7  0x01FFFFFF
+#define LEDC_DUTY_LSCH7_M  ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH7_S  0
+
+#define LEDC_LSCH7_CONF1_REG          (DR_REG_LEDC_BASE + 0x0138)
+/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: When reg_duty_num_hsch4  reg_duty_cycle_hsch4 and reg_duty_scale_hsch4
+ has been configured. these register won't take effect until set reg_duty_start_hsch4. this bit is automatically cleared by hardware.*/
+#define LEDC_DUTY_START_LSCH7  (BIT(31))
+#define LEDC_DUTY_START_LSCH7_M  (BIT(31))
+#define LEDC_DUTY_START_LSCH7_V  0x1
+#define LEDC_DUTY_START_LSCH7_S  31
+/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: This register is used to increase the duty of output signal or
+ decrease the duty of output signal for low speed channel4.*/
+#define LEDC_DUTY_INC_LSCH7  (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_M  (BIT(30))
+#define LEDC_DUTY_INC_LSCH7_V  0x1
+#define LEDC_DUTY_INC_LSCH7_S  30
+/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */
+/*description: This register is used to control the num of increased or decreased
+ times for low speed channel4.*/
+#define LEDC_DUTY_NUM_LSCH7  0x000003FF
+#define LEDC_DUTY_NUM_LSCH7_M  ((LEDC_DUTY_NUM_LSCH7_V)<<(LEDC_DUTY_NUM_LSCH7_S))
+#define LEDC_DUTY_NUM_LSCH7_V  0x3FF
+#define LEDC_DUTY_NUM_LSCH7_S  20
+/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */
+/*description: This register is used to increase or decrease the duty every
+ reg_duty_cycle_lsch7 cycles for low speed channel7.*/
+#define LEDC_DUTY_CYCLE_LSCH7  0x000003FF
+#define LEDC_DUTY_CYCLE_LSCH7_M  ((LEDC_DUTY_CYCLE_LSCH7_V)<<(LEDC_DUTY_CYCLE_LSCH7_S))
+#define LEDC_DUTY_CYCLE_LSCH7_V  0x3FF
+#define LEDC_DUTY_CYCLE_LSCH7_S  10
+/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: This register controls the increase or decrease step scale for
+ low speed channel7.*/
+#define LEDC_DUTY_SCALE_LSCH7  0x000003FF
+#define LEDC_DUTY_SCALE_LSCH7_M  ((LEDC_DUTY_SCALE_LSCH7_V)<<(LEDC_DUTY_SCALE_LSCH7_S))
+#define LEDC_DUTY_SCALE_LSCH7_V  0x3FF
+#define LEDC_DUTY_SCALE_LSCH7_S  0
+
+#define LEDC_LSCH7_DUTY_R_REG          (DR_REG_LEDC_BASE + 0x013C)
+/* LEDC_DUTY_LSCH7 : RO ;bitpos:[24:0] ;default: 25'h0 ; */
+/*description: This register represents the current duty of the output signal
+ for low speed channel7.*/
+#define LEDC_DUTY_LSCH7  0x01FFFFFF
+#define LEDC_DUTY_LSCH7_M  ((LEDC_DUTY_LSCH7_V)<<(LEDC_DUTY_LSCH7_S))
+#define LEDC_DUTY_LSCH7_V  0x1FFFFFF
+#define LEDC_DUTY_LSCH7_S  0
+
+#define LEDC_HSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x0140)
+/* LEDC_TICK_SEL_HSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer0. 1'b1:apb_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER0  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER0_M  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER0_V  0x1
+#define LEDC_TICK_SEL_HSTIMER0_S  25
+/* LEDC_HSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer0 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER0_RST  (BIT(24))
+#define LEDC_HSTIMER0_RST_M  (BIT(24))
+#define LEDC_HSTIMER0_RST_V  0x1
+#define LEDC_HSTIMER0_RST_S  24
+/* LEDC_HSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer0*/
+#define LEDC_HSTIMER0_PAUSE  (BIT(23))
+#define LEDC_HSTIMER0_PAUSE_M  (BIT(23))
+#define LEDC_HSTIMER0_PAUSE_V  0x1
+#define LEDC_HSTIMER0_PAUSE_S  23
+/* LEDC_CLK_DIV_HSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_HSTIMER0  0x0003FFFF
+#define LEDC_CLK_DIV_HSTIMER0_M  ((LEDC_CLK_DIV_HSTIMER0_V)<<(LEDC_CLK_DIV_HSTIMER0_S))
+#define LEDC_CLK_DIV_HSTIMER0_V  0x3FFFF
+#define LEDC_CLK_DIV_HSTIMER0_S  5
+/* LEDC_HSTIMER0_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_HSTIMER0_DUTY_RES  0x0000001F
+#define LEDC_HSTIMER0_DUTY_RES_M  ((LEDC_HSTIMER0_DUTY_RES_V)<<(LEDC_HSTIMER0_DUTY_RES_S))
+#define LEDC_HSTIMER0_DUTY_RES_V  0x1F
+#define LEDC_HSTIMER0_DUTY_RES_S  0
+
+#define LEDC_DIV_NUM_HSTIMER0    LEDC_CLK_DIV_HSTIMER0
+#define LEDC_DIV_NUM_HSTIMER0_M  LEDC_CLK_DIV_HSTIMER0_M
+#define LEDC_DIV_NUM_HSTIMER0_V  LEDC_CLK_DIV_HSTIMER0_V
+#define LEDC_DIV_NUM_HSTIMER0_S  LEDC_CLK_DIV_HSTIMER0_S
+
+#define LEDC_HSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x0144)
+/* LEDC_HSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer0*/
+#define LEDC_HSTIMER0_CNT  0x000FFFFF
+#define LEDC_HSTIMER0_CNT_M  ((LEDC_HSTIMER0_CNT_V)<<(LEDC_HSTIMER0_CNT_S))
+#define LEDC_HSTIMER0_CNT_V  0xFFFFF
+#define LEDC_HSTIMER0_CNT_S  0
+
+#define LEDC_HSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x0148)
+/* LEDC_TICK_SEL_HSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer1. 1'b1:apb_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER1  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER1_M  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER1_V  0x1
+#define LEDC_TICK_SEL_HSTIMER1_S  25
+/* LEDC_HSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer1 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER1_RST  (BIT(24))
+#define LEDC_HSTIMER1_RST_M  (BIT(24))
+#define LEDC_HSTIMER1_RST_V  0x1
+#define LEDC_HSTIMER1_RST_S  24
+/* LEDC_HSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer1*/
+#define LEDC_HSTIMER1_PAUSE  (BIT(23))
+#define LEDC_HSTIMER1_PAUSE_M  (BIT(23))
+#define LEDC_HSTIMER1_PAUSE_V  0x1
+#define LEDC_HSTIMER1_PAUSE_S  23
+/* LEDC_CLK_DIV_HSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_HSTIMER1  0x0003FFFF
+#define LEDC_CLK_DIV_HSTIMER1_M  ((LEDC_CLK_DIV_HSTIMER1_V)<<(LEDC_CLK_DIV_HSTIMER1_S))
+#define LEDC_CLK_DIV_HSTIMER1_V  0x3FFFF
+#define LEDC_CLK_DIV_HSTIMER1_S  5
+/* LEDC_HSTIMER1_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_HSTIMER1_DUTY_RES  0x0000001F
+#define LEDC_HSTIMER1_DUTY_RES_M  ((LEDC_HSTIMER1_DUTY_RES_V)<<(LEDC_HSTIMER1_DUTY_RES_S))
+#define LEDC_HSTIMER1_DUTY_RES_V  0x1F
+#define LEDC_HSTIMER1_DUTY_RES_S  0
+
+#define LEDC_HSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x014C)
+/* LEDC_HSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer1.*/
+#define LEDC_HSTIMER1_CNT  0x000FFFFF
+#define LEDC_HSTIMER1_CNT_M  ((LEDC_HSTIMER1_CNT_V)<<(LEDC_HSTIMER1_CNT_S))
+#define LEDC_HSTIMER1_CNT_V  0xFFFFF
+#define LEDC_HSTIMER1_CNT_S  0
+
+#define LEDC_HSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x0150)
+/* LEDC_TICK_SEL_HSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer2. 1'b1:apb_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER2  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER2_M  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER2_V  0x1
+#define LEDC_TICK_SEL_HSTIMER2_S  25
+/* LEDC_HSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer2 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER2_RST  (BIT(24))
+#define LEDC_HSTIMER2_RST_M  (BIT(24))
+#define LEDC_HSTIMER2_RST_V  0x1
+#define LEDC_HSTIMER2_RST_S  24
+/* LEDC_HSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer2*/
+#define LEDC_HSTIMER2_PAUSE  (BIT(23))
+#define LEDC_HSTIMER2_PAUSE_M  (BIT(23))
+#define LEDC_HSTIMER2_PAUSE_V  0x1
+#define LEDC_HSTIMER2_PAUSE_S  23
+/* LEDC_CLK_DIV_HSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_HSTIMER2  0x0003FFFF
+#define LEDC_CLK_DIV_HSTIMER2_M  ((LEDC_CLK_DIV_HSTIMER2_V)<<(LEDC_CLK_DIV_HSTIMER2_S))
+#define LEDC_CLK_DIV_HSTIMER2_V  0x3FFFF
+#define LEDC_CLK_DIV_HSTIMER2_S  5
+/* LEDC_HSTIMER2_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_HSTIMER2_DUTY_RES  0x0000001F
+#define LEDC_HSTIMER2_DUTY_RES_M  ((LEDC_HSTIMER2_DUTY_RES_V)<<(LEDC_HSTIMER2_DUTY_RES_S))
+#define LEDC_HSTIMER2_DUTY_RES_V  0x1F
+#define LEDC_HSTIMER2_DUTY_RES_S  0
+
+#define LEDC_HSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x0154)
+/* LEDC_HSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer2*/
+#define LEDC_HSTIMER2_CNT  0x000FFFFF
+#define LEDC_HSTIMER2_CNT_M  ((LEDC_HSTIMER2_CNT_V)<<(LEDC_HSTIMER2_CNT_S))
+#define LEDC_HSTIMER2_CNT_V  0xFFFFF
+#define LEDC_HSTIMER2_CNT_S  0
+
+#define LEDC_HSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x0158)
+/* LEDC_TICK_SEL_HSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose apb_clk or ref_tick for high speed
+ timer3. 1'b1:apb_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_HSTIMER3  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER3_M  (BIT(25))
+#define LEDC_TICK_SEL_HSTIMER3_V  0x1
+#define LEDC_TICK_SEL_HSTIMER3_S  25
+/* LEDC_HSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset high speed timer3 the counter will be 0 after reset.*/
+#define LEDC_HSTIMER3_RST  (BIT(24))
+#define LEDC_HSTIMER3_RST_M  (BIT(24))
+#define LEDC_HSTIMER3_RST_V  0x1
+#define LEDC_HSTIMER3_RST_S  24
+/* LEDC_HSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in high speed timer3*/
+#define LEDC_HSTIMER3_PAUSE  (BIT(23))
+#define LEDC_HSTIMER3_PAUSE_M  (BIT(23))
+#define LEDC_HSTIMER3_PAUSE_V  0x1
+#define LEDC_HSTIMER3_PAUSE_S  23
+/* LEDC_CLK_DIV_HSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_HSTIMER3  0x0003FFFF
+#define LEDC_CLK_DIV_HSTIMER3_M  ((LEDC_CLK_DIV_HSTIMER3_V)<<(LEDC_CLK_DIV_HSTIMER3_S))
+#define LEDC_CLK_DIV_HSTIMER3_V  0x3FFFF
+#define LEDC_CLK_DIV_HSTIMER3_S  5
+/* LEDC_HSTIMER3_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_HSTIMER3_DUTY_RES  0x0000001F
+#define LEDC_HSTIMER3_DUTY_RES_M  ((LEDC_HSTIMER3_DUTY_RES_V)<<(LEDC_HSTIMER3_DUTY_RES_S))
+#define LEDC_HSTIMER3_DUTY_RES_V  0x1F
+#define LEDC_HSTIMER3_DUTY_RES_S  0
+
+#define LEDC_HSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x015C)
+/* LEDC_HSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in high speed timer3*/
+#define LEDC_HSTIMER3_CNT  0x000FFFFF
+#define LEDC_HSTIMER3_CNT_M  ((LEDC_HSTIMER3_CNT_V)<<(LEDC_HSTIMER3_CNT_S))
+#define LEDC_HSTIMER3_CNT_V  0xFFFFF
+#define LEDC_HSTIMER3_CNT_S  0
+
+#define LEDC_LSTIMER0_CONF_REG          (DR_REG_LEDC_BASE + 0x0160)
+/* LEDC_LSTIMER0_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit  to update  reg_div_num_lstime0 and  reg_lstimer0_lim.*/
+#define LEDC_LSTIMER0_PARA_UP  (BIT(26))
+#define LEDC_LSTIMER0_PARA_UP_M  (BIT(26))
+#define LEDC_LSTIMER0_PARA_UP_V  0x1
+#define LEDC_LSTIMER0_PARA_UP_S  26
+/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer0. 1'b1:slow_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER0  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER0_M  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER0_V  0x1
+#define LEDC_TICK_SEL_LSTIMER0_S  25
+/* LEDC_LSTIMER0_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer0 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER0_RST  (BIT(24))
+#define LEDC_LSTIMER0_RST_M  (BIT(24))
+#define LEDC_LSTIMER0_RST_V  0x1
+#define LEDC_LSTIMER0_RST_S  24
+/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer0.*/
+#define LEDC_LSTIMER0_PAUSE  (BIT(23))
+#define LEDC_LSTIMER0_PAUSE_M  (BIT(23))
+#define LEDC_LSTIMER0_PAUSE_V  0x1
+#define LEDC_LSTIMER0_PAUSE_S  23
+/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER0  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER0_M  ((LEDC_CLK_DIV_LSTIMER0_V)<<(LEDC_CLK_DIV_LSTIMER0_S))
+#define LEDC_CLK_DIV_LSTIMER0_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER0_S  5
+/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_LSTIMER0_DUTY_RES  0x0000001F
+#define LEDC_LSTIMER0_DUTY_RES_M  ((LEDC_LSTIMER0_DUTY_RES_V)<<(LEDC_LSTIMER0_DUTY_RES_S))
+#define LEDC_LSTIMER0_DUTY_RES_V  0x1F
+#define LEDC_LSTIMER0_DUTY_RES_S  0
+
+#define LEDC_LSTIMER0_VALUE_REG          (DR_REG_LEDC_BASE + 0x0164)
+/* LEDC_LSTIMER0_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer0.*/
+#define LEDC_LSTIMER0_CNT  0x000FFFFF
+#define LEDC_LSTIMER0_CNT_M  ((LEDC_LSTIMER0_CNT_V)<<(LEDC_LSTIMER0_CNT_S))
+#define LEDC_LSTIMER0_CNT_V  0xFFFFF
+#define LEDC_LSTIMER0_CNT_S  0
+
+#define LEDC_LSTIMER1_CONF_REG          (DR_REG_LEDC_BASE + 0x0168)
+/* LEDC_LSTIMER1_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit  to update  reg_div_num_lstime1 and  reg_lstimer1_lim.*/
+#define LEDC_LSTIMER1_PARA_UP  (BIT(26))
+#define LEDC_LSTIMER1_PARA_UP_M  (BIT(26))
+#define LEDC_LSTIMER1_PARA_UP_V  0x1
+#define LEDC_LSTIMER1_PARA_UP_S  26
+/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer1. 1'b1:slow_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER1  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER1_M  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER1_V  0x1
+#define LEDC_TICK_SEL_LSTIMER1_S  25
+/* LEDC_LSTIMER1_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer1 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER1_RST  (BIT(24))
+#define LEDC_LSTIMER1_RST_M  (BIT(24))
+#define LEDC_LSTIMER1_RST_V  0x1
+#define LEDC_LSTIMER1_RST_S  24
+/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer1.*/
+#define LEDC_LSTIMER1_PAUSE  (BIT(23))
+#define LEDC_LSTIMER1_PAUSE_M  (BIT(23))
+#define LEDC_LSTIMER1_PAUSE_V  0x1
+#define LEDC_LSTIMER1_PAUSE_S  23
+/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER1  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER1_M  ((LEDC_CLK_DIV_LSTIMER1_V)<<(LEDC_CLK_DIV_LSTIMER1_S))
+#define LEDC_CLK_DIV_LSTIMER1_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER1_S  5
+/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_LSTIMER1_DUTY_RES  0x0000001F
+#define LEDC_LSTIMER1_DUTY_RES_M  ((LEDC_LSTIMER1_DUTY_RES_V)<<(LEDC_LSTIMER1_DUTY_RES_S))
+#define LEDC_LSTIMER1_DUTY_RES_V  0x1F
+#define LEDC_LSTIMER1_DUTY_RES_S  0
+
+#define LEDC_LSTIMER1_VALUE_REG          (DR_REG_LEDC_BASE + 0x016C)
+/* LEDC_LSTIMER1_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer1.*/
+#define LEDC_LSTIMER1_CNT  0x000FFFFF
+#define LEDC_LSTIMER1_CNT_M  ((LEDC_LSTIMER1_CNT_V)<<(LEDC_LSTIMER1_CNT_S))
+#define LEDC_LSTIMER1_CNT_V  0xFFFFF
+#define LEDC_LSTIMER1_CNT_S  0
+
+#define LEDC_LSTIMER2_CONF_REG          (DR_REG_LEDC_BASE + 0x0170)
+/* LEDC_LSTIMER2_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit  to update  reg_div_num_lstime2 and  reg_lstimer2_lim.*/
+#define LEDC_LSTIMER2_PARA_UP  (BIT(26))
+#define LEDC_LSTIMER2_PARA_UP_M  (BIT(26))
+#define LEDC_LSTIMER2_PARA_UP_V  0x1
+#define LEDC_LSTIMER2_PARA_UP_S  26
+/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer2. 1'b1:slow_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER2  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER2_M  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER2_V  0x1
+#define LEDC_TICK_SEL_LSTIMER2_S  25
+/* LEDC_LSTIMER2_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer2 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER2_RST  (BIT(24))
+#define LEDC_LSTIMER2_RST_M  (BIT(24))
+#define LEDC_LSTIMER2_RST_V  0x1
+#define LEDC_LSTIMER2_RST_S  24
+/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer2.*/
+#define LEDC_LSTIMER2_PAUSE  (BIT(23))
+#define LEDC_LSTIMER2_PAUSE_M  (BIT(23))
+#define LEDC_LSTIMER2_PAUSE_V  0x1
+#define LEDC_LSTIMER2_PAUSE_S  23
+/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER2  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER2_M  ((LEDC_CLK_DIV_LSTIMER2_V)<<(LEDC_CLK_DIV_LSTIMER2_S))
+#define LEDC_CLK_DIV_LSTIMER2_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER2_S  5
+/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_LSTIMER2_DUTY_RES  0x0000001F
+#define LEDC_LSTIMER2_DUTY_RES_M  ((LEDC_LSTIMER2_DUTY_RES_V)<<(LEDC_LSTIMER2_DUTY_RES_S))
+#define LEDC_LSTIMER2_DUTY_RES_V  0x1F
+#define LEDC_LSTIMER2_DUTY_RES_S  0
+
+#define LEDC_LSTIMER2_VALUE_REG          (DR_REG_LEDC_BASE + 0x0174)
+/* LEDC_LSTIMER2_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer2.*/
+#define LEDC_LSTIMER2_CNT  0x000FFFFF
+#define LEDC_LSTIMER2_CNT_M  ((LEDC_LSTIMER2_CNT_V)<<(LEDC_LSTIMER2_CNT_S))
+#define LEDC_LSTIMER2_CNT_V  0xFFFFF
+#define LEDC_LSTIMER2_CNT_S  0
+
+#define LEDC_LSTIMER3_CONF_REG          (DR_REG_LEDC_BASE + 0x0178)
+/* LEDC_LSTIMER3_PARA_UP : R/W ;bitpos:[26] ;default: 1'h0 ; */
+/*description: Set this bit  to update  reg_div_num_lstime3 and  reg_lstimer3_lim.*/
+#define LEDC_LSTIMER3_PARA_UP  (BIT(26))
+#define LEDC_LSTIMER3_PARA_UP_M  (BIT(26))
+#define LEDC_LSTIMER3_PARA_UP_V  0x1
+#define LEDC_LSTIMER3_PARA_UP_S  26
+/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: This bit is used to choose slow_clk or ref_tick for low speed
+ timer3. 1'b1:slow_clk  0:ref_tick*/
+#define LEDC_TICK_SEL_LSTIMER3  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER3_M  (BIT(25))
+#define LEDC_TICK_SEL_LSTIMER3_V  0x1
+#define LEDC_TICK_SEL_LSTIMER3_S  25
+/* LEDC_LSTIMER3_RST : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: This bit is used to reset low speed timer3 the counter will be 0 after reset.*/
+#define LEDC_LSTIMER3_RST  (BIT(24))
+#define LEDC_LSTIMER3_RST_M  (BIT(24))
+#define LEDC_LSTIMER3_RST_V  0x1
+#define LEDC_LSTIMER3_RST_S  24
+/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: This bit is used to pause the counter in low speed timer3.*/
+#define LEDC_LSTIMER3_PAUSE  (BIT(23))
+#define LEDC_LSTIMER3_PAUSE_M  (BIT(23))
+#define LEDC_LSTIMER3_PAUSE_V  0x1
+#define LEDC_LSTIMER3_PAUSE_S  23
+/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[22:5] ;default: 18'h0 ; */
+/*description: */
+#define LEDC_CLK_DIV_LSTIMER3  0x0003FFFF
+#define LEDC_CLK_DIV_LSTIMER3_M  ((LEDC_CLK_DIV_LSTIMER3_V)<<(LEDC_CLK_DIV_LSTIMER3_S))
+#define LEDC_CLK_DIV_LSTIMER3_V  0x3FFFF
+#define LEDC_CLK_DIV_LSTIMER3_S  5
+/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[4:0] ;default: 5'h0 ; */
+/*description: */
+#define LEDC_LSTIMER3_DUTY_RES  0x0000001F
+#define LEDC_LSTIMER3_DUTY_RES_M  ((LEDC_LSTIMER3_DUTY_RES_V)<<(LEDC_LSTIMER3_DUTY_RES_S))
+#define LEDC_LSTIMER3_DUTY_RES_V  0x1F
+#define LEDC_LSTIMER3_DUTY_RES_S  0
+
+#define LEDC_LSTIMER3_VALUE_REG          (DR_REG_LEDC_BASE + 0x017C)
+/* LEDC_LSTIMER3_CNT : RO ;bitpos:[19:0] ;default: 20'b0 ; */
+/*description: software can read this register to get the current counter value
+ in low speed timer3.*/
+#define LEDC_LSTIMER3_CNT  0x000FFFFF
+#define LEDC_LSTIMER3_CNT_M  ((LEDC_LSTIMER3_CNT_V)<<(LEDC_LSTIMER3_CNT_S))
+#define LEDC_LSTIMER3_CNT_V  0xFFFFF
+#define LEDC_LSTIMER3_CNT_S  0
+
+#define LEDC_INT_RAW_REG          (DR_REG_LEDC_BASE + 0x0180)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 7 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S  23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 6 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S  22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 5 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S  21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 4 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S  20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 3 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S  19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 2 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S  18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 1 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S  17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel 0 duty change done.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S  16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 7 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_M  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_RAW_S  15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 6 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_M  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_RAW_S  14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 5 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_M  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_RAW_S  13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 4 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_M  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_RAW_S  12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 3 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_M  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_RAW_S  11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 2 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_M  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_RAW_S  10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 1 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_RAW_S  9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel 0 duty change done.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_RAW_S  8
+/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel3  counter overflow.*/
+#define LEDC_LSTIMER3_OVF_INT_RAW  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_RAW_M  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_RAW_S  7
+/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel2  counter overflow.*/
+#define LEDC_LSTIMER2_OVF_INT_RAW  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_RAW_M  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_RAW_S  6
+/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel1  counter overflow.*/
+#define LEDC_LSTIMER1_OVF_INT_RAW  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_RAW_M  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_RAW_S  5
+/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for low speed channel0  counter overflow.*/
+#define LEDC_LSTIMER0_OVF_INT_RAW  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_RAW_M  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_RAW_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_RAW_S  4
+/* LEDC_HSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel3  counter overflow.*/
+#define LEDC_HSTIMER3_OVF_INT_RAW  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_RAW_M  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_RAW_V  0x1
+#define LEDC_HSTIMER3_OVF_INT_RAW_S  3
+/* LEDC_HSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel2  counter overflow.*/
+#define LEDC_HSTIMER2_OVF_INT_RAW  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_RAW_M  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_RAW_V  0x1
+#define LEDC_HSTIMER2_OVF_INT_RAW_S  2
+/* LEDC_HSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel1  counter overflow.*/
+#define LEDC_HSTIMER1_OVF_INT_RAW  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_RAW_M  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_RAW_V  0x1
+#define LEDC_HSTIMER1_OVF_INT_RAW_S  1
+/* LEDC_HSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for high speed channel0  counter overflow.*/
+#define LEDC_HSTIMER0_OVF_INT_RAW  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_RAW_M  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_RAW_V  0x1
+#define LEDC_HSTIMER0_OVF_INT_RAW_S  0
+
+#define LEDC_INT_ST_REG          (DR_REG_LEDC_BASE + 0x0184)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[23] ;default: 1'h0 ; */
+/*description: The interrupt status bit for low speed channel 7 duty change done event*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S  23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 6 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S  22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 5 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S  21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 4 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S  20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 3 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S  19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 2 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S  18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 1 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S  17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel 0 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S  16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 7 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_M  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ST_S  15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 6 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_M  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ST_S  14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 5 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_M  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ST_S  13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 4 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_M  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ST_S  12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 3 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_M  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ST_S  11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 2 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_M  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ST_S  10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 1 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ST_S  9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel 0 duty change done event.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ST_S  8
+/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel3  counter overflow event.*/
+#define LEDC_LSTIMER3_OVF_INT_ST  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ST_M  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ST_S  7
+/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel2  counter overflow event.*/
+#define LEDC_LSTIMER2_OVF_INT_ST  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ST_M  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ST_S  6
+/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel1  counter overflow event.*/
+#define LEDC_LSTIMER1_OVF_INT_ST  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ST_M  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ST_S  5
+/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt status bit for low speed channel0  counter overflow event.*/
+#define LEDC_LSTIMER0_OVF_INT_ST  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ST_M  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ST_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ST_S  4
+/* LEDC_HSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel3  counter overflow event.*/
+#define LEDC_HSTIMER3_OVF_INT_ST  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ST_M  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ST_V  0x1
+#define LEDC_HSTIMER3_OVF_INT_ST_S  3
+/* LEDC_HSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel2  counter overflow event.*/
+#define LEDC_HSTIMER2_OVF_INT_ST  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ST_M  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ST_V  0x1
+#define LEDC_HSTIMER2_OVF_INT_ST_S  2
+/* LEDC_HSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel1  counter overflow event.*/
+#define LEDC_HSTIMER1_OVF_INT_ST  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ST_M  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ST_V  0x1
+#define LEDC_HSTIMER1_OVF_INT_ST_S  1
+/* LEDC_HSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt status bit for high speed channel0  counter overflow event.*/
+#define LEDC_HSTIMER0_OVF_INT_ST  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ST_M  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ST_V  0x1
+#define LEDC_HSTIMER0_OVF_INT_ST_S  0
+
+#define LEDC_INT_ENA_REG          (DR_REG_LEDC_BASE + 0x0188)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S  23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S  22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S  21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S  20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S  19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S  18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S  17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S  16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_M  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_ENA_S  15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_M  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_ENA_S  14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_M  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_ENA_S  13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_M  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_ENA_S  12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_M  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_ENA_S  11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_M  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_ENA_S  10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_ENA_S  9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_ENA_S  8
+/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel3  counter overflow interrupt.*/
+#define LEDC_LSTIMER3_OVF_INT_ENA  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ENA_M  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_ENA_S  7
+/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel2  counter overflow interrupt.*/
+#define LEDC_LSTIMER2_OVF_INT_ENA  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ENA_M  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_ENA_S  6
+/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel1  counter overflow interrupt.*/
+#define LEDC_LSTIMER1_OVF_INT_ENA  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ENA_M  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_ENA_S  5
+/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for low speed channel0  counter overflow interrupt.*/
+#define LEDC_LSTIMER0_OVF_INT_ENA  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ENA_M  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_ENA_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_ENA_S  4
+/* LEDC_HSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel3  counter overflow interrupt.*/
+#define LEDC_HSTIMER3_OVF_INT_ENA  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ENA_M  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_ENA_V  0x1
+#define LEDC_HSTIMER3_OVF_INT_ENA_S  3
+/* LEDC_HSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel2  counter overflow interrupt.*/
+#define LEDC_HSTIMER2_OVF_INT_ENA  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ENA_M  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_ENA_V  0x1
+#define LEDC_HSTIMER2_OVF_INT_ENA_S  2
+/* LEDC_HSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel1  counter overflow interrupt.*/
+#define LEDC_HSTIMER1_OVF_INT_ENA  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ENA_M  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_ENA_V  0x1
+#define LEDC_HSTIMER1_OVF_INT_ENA_S  1
+/* LEDC_HSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt enable bit for high speed channel0  counter overflow interrupt.*/
+#define LEDC_HSTIMER0_OVF_INT_ENA  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ENA_M  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_ENA_V  0x1
+#define LEDC_HSTIMER0_OVF_INT_ENA_S  0
+
+#define LEDC_INT_CLR_REG          (DR_REG_LEDC_BASE + 0x018C)
+/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[23] ;default: 1'h0 ; */
+/*description: Set this  bit to clear  low speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M  (BIT(23))
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S  23
+/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M  (BIT(22))
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S  22
+/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M  (BIT(21))
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S  21
+/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M  (BIT(20))
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S  20
+/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M  (BIT(19))
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S  19
+/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M  (BIT(18))
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S  18
+/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M  (BIT(17))
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S  17
+/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M  (BIT(16))
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S  16
+/* LEDC_DUTY_CHNG_END_HSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 7 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_M  (BIT(15))
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH7_INT_CLR_S  15
+/* LEDC_DUTY_CHNG_END_HSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 6 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_M  (BIT(14))
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH6_INT_CLR_S  14
+/* LEDC_DUTY_CHNG_END_HSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 5 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_M  (BIT(13))
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH5_INT_CLR_S  13
+/* LEDC_DUTY_CHNG_END_HSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 4 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_M  (BIT(12))
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH4_INT_CLR_S  12
+/* LEDC_DUTY_CHNG_END_HSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 3 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_M  (BIT(11))
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH3_INT_CLR_S  11
+/* LEDC_DUTY_CHNG_END_HSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 2 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_M  (BIT(10))
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH2_INT_CLR_S  10
+/* LEDC_DUTY_CHNG_END_HSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 1 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_M  (BIT(9))
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH1_INT_CLR_S  9
+/* LEDC_DUTY_CHNG_END_HSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel 0 duty change done interrupt.*/
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_M  (BIT(8))
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_V  0x1
+#define LEDC_DUTY_CHNG_END_HSCH0_INT_CLR_S  8
+/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel3  counter overflow interrupt.*/
+#define LEDC_LSTIMER3_OVF_INT_CLR  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_CLR_M  (BIT(7))
+#define LEDC_LSTIMER3_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER3_OVF_INT_CLR_S  7
+/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel2  counter overflow interrupt.*/
+#define LEDC_LSTIMER2_OVF_INT_CLR  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_CLR_M  (BIT(6))
+#define LEDC_LSTIMER2_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER2_OVF_INT_CLR_S  6
+/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel1  counter overflow interrupt.*/
+#define LEDC_LSTIMER1_OVF_INT_CLR  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_CLR_M  (BIT(5))
+#define LEDC_LSTIMER1_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER1_OVF_INT_CLR_S  5
+/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  low speed channel0  counter overflow interrupt.*/
+#define LEDC_LSTIMER0_OVF_INT_CLR  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_CLR_M  (BIT(4))
+#define LEDC_LSTIMER0_OVF_INT_CLR_V  0x1
+#define LEDC_LSTIMER0_OVF_INT_CLR_S  4
+/* LEDC_HSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel3  counter overflow interrupt.*/
+#define LEDC_HSTIMER3_OVF_INT_CLR  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_CLR_M  (BIT(3))
+#define LEDC_HSTIMER3_OVF_INT_CLR_V  0x1
+#define LEDC_HSTIMER3_OVF_INT_CLR_S  3
+/* LEDC_HSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel2  counter overflow interrupt.*/
+#define LEDC_HSTIMER2_OVF_INT_CLR  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_CLR_M  (BIT(2))
+#define LEDC_HSTIMER2_OVF_INT_CLR_V  0x1
+#define LEDC_HSTIMER2_OVF_INT_CLR_S  2
+/* LEDC_HSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel1  counter overflow interrupt.*/
+#define LEDC_HSTIMER1_OVF_INT_CLR  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_CLR_M  (BIT(1))
+#define LEDC_HSTIMER1_OVF_INT_CLR_V  0x1
+#define LEDC_HSTIMER1_OVF_INT_CLR_S  1
+/* LEDC_HSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this  bit to clear  high speed channel0  counter overflow interrupt.*/
+#define LEDC_HSTIMER0_OVF_INT_CLR  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_CLR_M  (BIT(0))
+#define LEDC_HSTIMER0_OVF_INT_CLR_V  0x1
+#define LEDC_HSTIMER0_OVF_INT_CLR_S  0
+
+#define LEDC_CONF_REG          (DR_REG_LEDC_BASE + 0x0190)
+/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define LEDC_APB_CLK_SEL  0x00000003
+#define LEDC_APB_CLK_SEL_M  ((LEDC_APB_CLK_SEL_V)<<(LEDC_APB_CLK_SEL_S))
+#define LEDC_APB_CLK_SEL_V  0x3
+#define LEDC_APB_CLK_SEL_S  0
+
+#define LEDC_INT1_RAW_REG          (DR_REG_LEDC_BASE + 0x0194)
+/* LEDC_OVF_CNT_LSCH7_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_RAW  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_RAW_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH7_INT_RAW_S  15
+/* LEDC_OVF_CNT_LSCH6_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_RAW  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_RAW_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH6_INT_RAW_S  14
+/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_RAW  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_RAW_S  13
+/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_RAW  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_RAW_S  12
+/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_RAW  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_RAW_S  11
+/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_RAW  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_RAW_S  10
+/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_RAW  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_M  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_RAW_S  9
+/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_RAW  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_M  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_RAW_S  8
+/* LEDC_OVF_CNT_HSCH7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH7_INT_RAW  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_RAW_M  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH7_INT_RAW_S  7
+/* LEDC_OVF_CNT_HSCH6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH6_INT_RAW  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_RAW_M  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH6_INT_RAW_S  6
+/* LEDC_OVF_CNT_HSCH5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH5_INT_RAW  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_RAW_M  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH5_INT_RAW_S  5
+/* LEDC_OVF_CNT_HSCH4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH4_INT_RAW  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_RAW_M  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH4_INT_RAW_S  4
+/* LEDC_OVF_CNT_HSCH3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH3_INT_RAW  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_RAW_M  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH3_INT_RAW_S  3
+/* LEDC_OVF_CNT_HSCH2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH2_INT_RAW  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_RAW_M  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH2_INT_RAW_S  2
+/* LEDC_OVF_CNT_HSCH1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH1_INT_RAW  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_RAW_M  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH1_INT_RAW_S  1
+/* LEDC_OVF_CNT_HSCH0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH0_INT_RAW  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_RAW_M  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_RAW_V  0x1
+#define LEDC_OVF_CNT_HSCH0_INT_RAW_S  0
+
+#define LEDC_INT1_ST_REG          (DR_REG_LEDC_BASE + 0x0198)
+/* LEDC_OVF_CNT_LSCH7_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_ST  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_ST_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH7_INT_ST_S  15
+/* LEDC_OVF_CNT_LSCH6_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_ST  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_ST_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH6_INT_ST_S  14
+/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ST  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ST_S  13
+/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ST  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ST_S  12
+/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ST  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ST_S  11
+/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ST  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ST_S  10
+/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ST  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_M  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ST_S  9
+/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ST  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_M  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_ST_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ST_S  8
+/* LEDC_OVF_CNT_HSCH7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH7_INT_ST  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_ST_M  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH7_INT_ST_S  7
+/* LEDC_OVF_CNT_HSCH6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH6_INT_ST  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_ST_M  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH6_INT_ST_S  6
+/* LEDC_OVF_CNT_HSCH5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH5_INT_ST  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_ST_M  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH5_INT_ST_S  5
+/* LEDC_OVF_CNT_HSCH4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH4_INT_ST  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_ST_M  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH4_INT_ST_S  4
+/* LEDC_OVF_CNT_HSCH3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH3_INT_ST  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_ST_M  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH3_INT_ST_S  3
+/* LEDC_OVF_CNT_HSCH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH2_INT_ST  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_ST_M  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH2_INT_ST_S  2
+/* LEDC_OVF_CNT_HSCH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH1_INT_ST  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_ST_M  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH1_INT_ST_S  1
+/* LEDC_OVF_CNT_HSCH0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH0_INT_ST  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_ST_M  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_ST_V  0x1
+#define LEDC_OVF_CNT_HSCH0_INT_ST_S  0
+
+#define LEDC_INT1_ENA_REG          (DR_REG_LEDC_BASE + 0x019c)
+/* LEDC_OVF_CNT_LSCH7_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_ENA  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_ENA_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH7_INT_ENA_S  15
+/* LEDC_OVF_CNT_LSCH6_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_ENA  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_ENA_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH6_INT_ENA_S  14
+/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_ENA  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_ENA_S  13
+/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_ENA  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_ENA_S  12
+/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_ENA  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_ENA_S  11
+/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_ENA  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_ENA_S  10
+/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_ENA  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_M  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_ENA_S  9
+/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_ENA  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_M  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_ENA_S  8
+/* LEDC_OVF_CNT_HSCH7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH7_INT_ENA  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_ENA_M  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH7_INT_ENA_S  7
+/* LEDC_OVF_CNT_HSCH6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH6_INT_ENA  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_ENA_M  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH6_INT_ENA_S  6
+/* LEDC_OVF_CNT_HSCH5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH5_INT_ENA  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_ENA_M  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH5_INT_ENA_S  5
+/* LEDC_OVF_CNT_HSCH4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH4_INT_ENA  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_ENA_M  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH4_INT_ENA_S  4
+/* LEDC_OVF_CNT_HSCH3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH3_INT_ENA  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_ENA_M  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH3_INT_ENA_S  3
+/* LEDC_OVF_CNT_HSCH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH2_INT_ENA  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_ENA_M  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH2_INT_ENA_S  2
+/* LEDC_OVF_CNT_HSCH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH1_INT_ENA  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_ENA_M  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH1_INT_ENA_S  1
+/* LEDC_OVF_CNT_HSCH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH0_INT_ENA  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_ENA_M  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_ENA_V  0x1
+#define LEDC_OVF_CNT_HSCH0_INT_ENA_S  0
+
+#define LEDC_INT1_CLR_REG          (DR_REG_LEDC_BASE + 0x01a0)
+/* LEDC_OVF_CNT_LSCH7_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH7_INT_CLR  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_CLR_M  (BIT(15))
+#define LEDC_OVF_CNT_LSCH7_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH7_INT_CLR_S  15
+/* LEDC_OVF_CNT_LSCH6_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH6_INT_CLR  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_CLR_M  (BIT(14))
+#define LEDC_OVF_CNT_LSCH6_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH6_INT_CLR_S  14
+/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH5_INT_CLR  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_M  (BIT(13))
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH5_INT_CLR_S  13
+/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH4_INT_CLR  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_M  (BIT(12))
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH4_INT_CLR_S  12
+/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH3_INT_CLR  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_M  (BIT(11))
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH3_INT_CLR_S  11
+/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH2_INT_CLR  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_M  (BIT(10))
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH2_INT_CLR_S  10
+/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH1_INT_CLR  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_M  (BIT(9))
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH1_INT_CLR_S  9
+/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_LSCH0_INT_CLR  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_M  (BIT(8))
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_LSCH0_INT_CLR_S  8
+/* LEDC_OVF_CNT_HSCH7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH7_INT_CLR  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_CLR_M  (BIT(7))
+#define LEDC_OVF_CNT_HSCH7_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH7_INT_CLR_S  7
+/* LEDC_OVF_CNT_HSCH6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH6_INT_CLR  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_CLR_M  (BIT(6))
+#define LEDC_OVF_CNT_HSCH6_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH6_INT_CLR_S  6
+/* LEDC_OVF_CNT_HSCH5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH5_INT_CLR  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_CLR_M  (BIT(5))
+#define LEDC_OVF_CNT_HSCH5_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH5_INT_CLR_S  5
+/* LEDC_OVF_CNT_HSCH4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH4_INT_CLR  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_CLR_M  (BIT(4))
+#define LEDC_OVF_CNT_HSCH4_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH4_INT_CLR_S  4
+/* LEDC_OVF_CNT_HSCH3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH3_INT_CLR  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_CLR_M  (BIT(3))
+#define LEDC_OVF_CNT_HSCH3_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH3_INT_CLR_S  3
+/* LEDC_OVF_CNT_HSCH2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH2_INT_CLR  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_CLR_M  (BIT(2))
+#define LEDC_OVF_CNT_HSCH2_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH2_INT_CLR_S  2
+/* LEDC_OVF_CNT_HSCH1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH1_INT_CLR  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_CLR_M  (BIT(1))
+#define LEDC_OVF_CNT_HSCH1_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH1_INT_CLR_S  1
+/* LEDC_OVF_CNT_HSCH0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define LEDC_OVF_CNT_HSCH0_INT_CLR  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_CLR_M  (BIT(0))
+#define LEDC_OVF_CNT_HSCH0_INT_CLR_V  0x1
+#define LEDC_OVF_CNT_HSCH0_INT_CLR_S  0
+
+#define LEDC_DATE_REG          (DR_REG_LEDC_BASE + 0x01FC)
+/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18051200 ; */
+/*description: */
+#define LEDC_DATE  0xFFFFFFFF
+#define LEDC_DATE_M  ((LEDC_DATE_V)<<(LEDC_DATE_S))
+#define LEDC_DATE_V  0xFFFFFFFF
+#define LEDC_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_LEDC_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/ledc_struct.h b/components/soc/esp32s2beta/include/soc/ledc_struct.h
new file mode 100644
index 000000000..12e46cb86
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/ledc_struct.h
@@ -0,0 +1,356 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_LEDC_STRUCT_H_
+#define _SOC_LEDC_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t htimer_sel:       2;
+                    uint32_t hsig_out_en:      1;
+                    uint32_t hidle_lv:         1;
+                    uint32_t hovf_num:         10;
+                    uint32_t hovf_cnt_en:       1;
+                    uint32_t reserved15:      16;
+                    uint32_t clk_en:           1;
+                };
+                struct {
+                    uint32_t ltimer_sel:        2;
+                    uint32_t lsig_out_en:       1;
+                    uint32_t lidle_lv:          1;
+                    uint32_t low_speed_update: 1;
+                    uint32_t lovf_num:         10;
+                    uint32_t lovf_cnt_en:       1;
+                    uint32_t reserved16:      16;
+                };
+                struct {
+                    uint32_t timer_sel:  2;              /*There are four high speed timers  the two bits are used to select one of them for high speed channel.  2'b00: seletc hstimer0.   2'b01: select hstimer1.  2'b10: select hstimer2.    2'b11: select hstimer3.*/
+                    uint32_t sig_out_en: 1;              /*This is the output enable control bit for high speed channel*/
+                    uint32_t idle_lv:    1;              /*This bit is used to control the output value when high speed channel is off.*/
+                    uint32_t reserved28:   28;
+                };
+                uint32_t val;
+            } conf0;
+            union {
+                struct {
+                    uint32_t hpoint:     20;             /*The output value changes to high when htimerx(x=[0 3]) selected by high speed channel has reached reg_hpoint_hsch0[19:0]*/
+                    uint32_t reserved20: 12;
+                };
+                uint32_t val;
+            } hpoint;
+            union {
+                struct {
+                    uint32_t duty:      25;              /*The register is used to control output duty. When hstimerx(x=[0 3]) chosen by high speed channel  has reached reg_lpoint_hsch0 the output signal changes to low. reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4])          (1)  reg_lpoint_hsch0=(reg_hpoint_hsch0[19:0]+reg_duty_hsch0[24:4] +1)     (2)  The least four bits in this register represent the decimal part and determines when to choose (1) or (2)*/
+                    uint32_t reserved25: 7;
+                };
+                uint32_t val;
+            } duty;
+            union {
+                struct {
+                    uint32_t duty_scale:10;              /*This register controls the increase or decrease step scale for high speed channel.*/
+                    uint32_t duty_cycle:10;              /*This register is used to increase or decrease the duty every reg_duty_cycle_hsch0 cycles for high speed channel.*/
+                    uint32_t duty_num:  10;              /*This register is used to control the number of increased or decreased times for high speed channel.*/
+                    uint32_t duty_inc:   1;              /*This register is used to increase the duty of output signal or decrease the duty of output signal for high speed channel.*/
+                    uint32_t duty_start: 1;              /*When reg_duty_num_hsch0 reg_duty_cycle_hsch0 and reg_duty_scale_hsch0 has been configured. these register won't take effect until set reg_duty_start_hsch0. this bit is automatically cleared by hardware.*/
+                };
+                uint32_t val;
+            } conf1;
+            union {
+                struct {
+                    uint32_t duty_read: 25;              /*This register represents the current duty of the output signal for high speed channel.*/
+                    uint32_t reserved25: 7;
+                };
+                uint32_t val;
+            } duty_rd;
+        } channel[8];
+    } channel_group[2];                                /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
+    struct {
+        struct {
+            union {
+                struct {
+                    uint32_t duty_resolution:          5;
+                    uint32_t clock_divider:          18;
+                    uint32_t pause:             1;
+                    uint32_t rst:               1;
+                    uint32_t tick_sel:          1;
+                    uint32_t low_speed_update:  1;
+                    uint32_t reserved27:        5;
+                };
+                uint32_t val;
+            } conf;
+            union {
+                struct {
+                    uint32_t timer_cnt:  20;               /*software can read this register to get the current counter value in high speed timer*/
+                    uint32_t reserved20: 12;
+                };
+                uint32_t val;
+            } value;
+        } timer[4];
+    } timer_group[2];                                    /*two channel groups : 0: high-speed channels; 1: low-speed channels*/
+    union {
+        struct {
+            uint32_t hstimer0_ovf:        1;           /*The interrupt raw bit for high speed channel0  counter overflow.*/
+            uint32_t hstimer1_ovf:        1;           /*The interrupt raw bit for high speed channel1  counter overflow.*/
+            uint32_t hstimer2_ovf:        1;           /*The interrupt raw bit for high speed channel2  counter overflow.*/
+            uint32_t hstimer3_ovf:        1;           /*The interrupt raw bit for high speed channel3  counter overflow.*/
+            uint32_t lstimer0_ovf:        1;           /*The interrupt raw bit for low speed channel0  counter overflow.*/
+            uint32_t lstimer1_ovf:        1;           /*The interrupt raw bit for low speed channel1  counter overflow.*/
+            uint32_t lstimer2_ovf:        1;           /*The interrupt raw bit for low speed channel2  counter overflow.*/
+            uint32_t lstimer3_ovf:        1;           /*The interrupt raw bit for low speed channel3  counter overflow.*/
+            uint32_t duty_chng_end_hsch0: 1;           /*The interrupt raw bit for high speed channel 0 duty change done.*/
+            uint32_t duty_chng_end_hsch1: 1;           /*The interrupt raw bit for high speed channel 1 duty change done.*/
+            uint32_t duty_chng_end_hsch2: 1;           /*The interrupt raw bit for high speed channel 2 duty change done.*/
+            uint32_t duty_chng_end_hsch3: 1;           /*The interrupt raw bit for high speed channel 3 duty change done.*/
+            uint32_t duty_chng_end_hsch4: 1;           /*The interrupt raw bit for high speed channel 4 duty change done.*/
+            uint32_t duty_chng_end_hsch5: 1;           /*The interrupt raw bit for high speed channel 5 duty change done.*/
+            uint32_t duty_chng_end_hsch6: 1;           /*The interrupt raw bit for high speed channel 6 duty change done.*/
+            uint32_t duty_chng_end_hsch7: 1;           /*The interrupt raw bit for high speed channel 7 duty change done.*/
+            uint32_t duty_chng_end_lsch0: 1;           /*The interrupt raw bit for low speed channel 0 duty change done.*/
+            uint32_t duty_chng_end_lsch1: 1;           /*The interrupt raw bit for low speed channel 1 duty change done.*/
+            uint32_t duty_chng_end_lsch2: 1;           /*The interrupt raw bit for low speed channel 2 duty change done.*/
+            uint32_t duty_chng_end_lsch3: 1;           /*The interrupt raw bit for low speed channel 3 duty change done.*/
+            uint32_t duty_chng_end_lsch4: 1;           /*The interrupt raw bit for low speed channel 4 duty change done.*/
+            uint32_t duty_chng_end_lsch5: 1;           /*The interrupt raw bit for low speed channel 5 duty change done.*/
+            uint32_t duty_chng_end_lsch6: 1;           /*The interrupt raw bit for low speed channel 6 duty change done.*/
+            uint32_t duty_chng_end_lsch7: 1;           /*The interrupt raw bit for low speed channel 7 duty change done.*/
+            uint32_t reserved24:          8;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t hstimer0_ovf:        1;            /*The interrupt status bit for high speed channel0  counter overflow event.*/
+            uint32_t hstimer1_ovf:        1;            /*The interrupt status bit for high speed channel1  counter overflow event.*/
+            uint32_t hstimer2_ovf:        1;            /*The interrupt status bit for high speed channel2  counter overflow event.*/
+            uint32_t hstimer3_ovf:        1;            /*The interrupt status bit for high speed channel3  counter overflow event.*/
+            uint32_t lstimer0_ovf:        1;            /*The interrupt status bit for low speed channel0  counter overflow event.*/
+            uint32_t lstimer1_ovf:        1;            /*The interrupt status bit for low speed channel1  counter overflow event.*/
+            uint32_t lstimer2_ovf:        1;            /*The interrupt status bit for low speed channel2  counter overflow event.*/
+            uint32_t lstimer3_ovf:        1;            /*The interrupt status bit for low speed channel3  counter overflow event.*/
+            uint32_t duty_chng_end_hsch0: 1;            /*The interrupt enable bit for high speed channel 0 duty change done event.*/
+            uint32_t duty_chng_end_hsch1: 1;            /*The interrupt status bit for high speed channel 1 duty change done event.*/
+            uint32_t duty_chng_end_hsch2: 1;            /*The interrupt status bit for high speed channel 2 duty change done event.*/
+            uint32_t duty_chng_end_hsch3: 1;            /*The interrupt status bit for high speed channel 3 duty change done event.*/
+            uint32_t duty_chng_end_hsch4: 1;            /*The interrupt status bit for high speed channel 4 duty change done event.*/
+            uint32_t duty_chng_end_hsch5: 1;            /*The interrupt status bit for high speed channel 5 duty change done event.*/
+            uint32_t duty_chng_end_hsch6: 1;            /*The interrupt status bit for high speed channel 6 duty change done event.*/
+            uint32_t duty_chng_end_hsch7: 1;            /*The interrupt status bit for high speed channel 7 duty change done event.*/
+            uint32_t duty_chng_end_lsch0: 1;            /*The interrupt status bit for low speed channel 0 duty change done event.*/
+            uint32_t duty_chng_end_lsch1: 1;            /*The interrupt status bit for low speed channel 1 duty change done event.*/
+            uint32_t duty_chng_end_lsch2: 1;            /*The interrupt status bit for low speed channel 2 duty change done event.*/
+            uint32_t duty_chng_end_lsch3: 1;            /*The interrupt status bit for low speed channel 3 duty change done event.*/
+            uint32_t duty_chng_end_lsch4: 1;            /*The interrupt status bit for low speed channel 4 duty change done event.*/
+            uint32_t duty_chng_end_lsch5: 1;            /*The interrupt status bit for low speed channel 5 duty change done event.*/
+            uint32_t duty_chng_end_lsch6: 1;            /*The interrupt status bit for low speed channel 6 duty change done event.*/
+            uint32_t duty_chng_end_lsch7: 1;            /*The interrupt status bit for low speed channel 7 duty change done event*/
+            uint32_t reserved24:          8;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t hstimer0_ovf:        1;           /*The interrupt enable bit for high speed channel0  counter overflow interrupt.*/
+            uint32_t hstimer1_ovf:        1;           /*The interrupt enable bit for high speed channel1  counter overflow interrupt.*/
+            uint32_t hstimer2_ovf:        1;           /*The interrupt enable bit for high speed channel2  counter overflow interrupt.*/
+            uint32_t hstimer3_ovf:        1;           /*The interrupt enable bit for high speed channel3  counter overflow interrupt.*/
+            uint32_t lstimer0_ovf:        1;           /*The interrupt enable bit for low speed channel0  counter overflow interrupt.*/
+            uint32_t lstimer1_ovf:        1;           /*The interrupt enable bit for low speed channel1  counter overflow interrupt.*/
+            uint32_t lstimer2_ovf:        1;           /*The interrupt enable bit for low speed channel2  counter overflow interrupt.*/
+            uint32_t lstimer3_ovf:        1;           /*The interrupt enable bit for low speed channel3  counter overflow interrupt.*/
+            uint32_t duty_chng_end_hsch0: 1;           /*The interrupt enable bit for high speed channel 0 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch1: 1;           /*The interrupt enable bit for high speed channel 1 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch2: 1;           /*The interrupt enable bit for high speed channel 2 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch3: 1;           /*The interrupt enable bit for high speed channel 3 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch4: 1;           /*The interrupt enable bit for high speed channel 4 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch5: 1;           /*The interrupt enable bit for high speed channel 5 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch6: 1;           /*The interrupt enable bit for high speed channel 6 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch7: 1;           /*The interrupt enable bit for high speed channel 7 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch0: 1;           /*The interrupt enable bit for low speed channel 0 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch1: 1;           /*The interrupt enable bit for low speed channel 1 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch2: 1;           /*The interrupt enable bit for low speed channel 2 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch3: 1;           /*The interrupt enable bit for low speed channel 3 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch4: 1;           /*The interrupt enable bit for low speed channel 4 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch5: 1;           /*The interrupt enable bit for low speed channel 5 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch6: 1;           /*The interrupt enable bit for low speed channel 6 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch7: 1;           /*The interrupt enable bit for low speed channel 7 duty change done interrupt.*/
+            uint32_t reserved24:          8;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t hstimer0_ovf:        1;           /*Set this  bit to clear  high speed channel0  counter overflow interrupt.*/
+            uint32_t hstimer1_ovf:        1;           /*Set this  bit to clear  high speed channel1  counter overflow interrupt.*/
+            uint32_t hstimer2_ovf:        1;           /*Set this  bit to clear  high speed channel2  counter overflow interrupt.*/
+            uint32_t hstimer3_ovf:        1;           /*Set this  bit to clear  high speed channel3  counter overflow interrupt.*/
+            uint32_t lstimer0_ovf:        1;           /*Set this  bit to clear  low speed channel0  counter overflow interrupt.*/
+            uint32_t lstimer1_ovf:        1;           /*Set this  bit to clear  low speed channel1  counter overflow interrupt.*/
+            uint32_t lstimer2_ovf:        1;           /*Set this  bit to clear  low speed channel2  counter overflow interrupt.*/
+            uint32_t lstimer3_ovf:        1;           /*Set this  bit to clear  low speed channel3  counter overflow interrupt.*/
+            uint32_t duty_chng_end_hsch0: 1;           /*Set this  bit to clear  high speed channel 0 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch1: 1;           /*Set this  bit to clear  high speed channel 1 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch2: 1;           /*Set this  bit to clear  high speed channel 2 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch3: 1;           /*Set this  bit to clear  high speed channel 3 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch4: 1;           /*Set this  bit to clear  high speed channel 4 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch5: 1;           /*Set this  bit to clear  high speed channel 5 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch6: 1;           /*Set this  bit to clear  high speed channel 6 duty change done interrupt.*/
+            uint32_t duty_chng_end_hsch7: 1;           /*Set this  bit to clear  high speed channel 7 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch0: 1;           /*Set this  bit to clear  low speed channel 0 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch1: 1;           /*Set this  bit to clear  low speed channel 1 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch2: 1;           /*Set this  bit to clear  low speed channel 2 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch3: 1;           /*Set this  bit to clear  low speed channel 3 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch4: 1;           /*Set this  bit to clear  low speed channel 4 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch5: 1;           /*Set this  bit to clear  low speed channel 5 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch6: 1;           /*Set this  bit to clear  low speed channel 6 duty change done interrupt.*/
+            uint32_t duty_chng_end_lsch7: 1;           /*Set this  bit to clear  low speed channel 7 duty change done interrupt.*/
+            uint32_t reserved24:          8;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t apb_clk_sel: 2;
+            uint32_t reserved2:  30;
+        };
+        struct {
+            uint32_t slow_clk_sel: 1;                  /*This bit is used to set the frequency of slow_clk. 1'b1:80mhz  1'b0:8mhz, (only used by LEDC low speed channels/timers)*/
+            uint32_t reserved:  31;
+        };
+        uint32_t val;
+    } conf;
+    union {
+        struct {
+            uint32_t ovf_cnt_hsch0:         1;
+            uint32_t ovf_cnt_hsch1:         1;
+            uint32_t ovf_cnt_hsch2:         1;
+            uint32_t ovf_cnt_hsch3:         1;
+            uint32_t ovf_cnt_hsch4:         1;
+            uint32_t ovf_cnt_hsch5:         1;
+            uint32_t ovf_cnt_hsch6:         1;
+            uint32_t ovf_cnt_hsch7:         1;
+            uint32_t ovf_cnt_lsch0:         1;
+            uint32_t ovf_cnt_lsch1:         1;
+            uint32_t ovf_cnt_lsch2:         1;
+            uint32_t ovf_cnt_lsch3:         1;
+            uint32_t ovf_cnt_lsch4:         1;
+            uint32_t ovf_cnt_lsch5:         1;
+            uint32_t ovf_cnt_lsch6:         1;
+            uint32_t ovf_cnt_lsch7:         1;
+            uint32_t reserved16:           16;
+        };
+        uint32_t val;
+    } int1_raw;
+    union {
+        struct {
+            uint32_t ovf_cnt_hsch0:        1;
+            uint32_t ovf_cnt_hsch1:        1;
+            uint32_t ovf_cnt_hsch2:        1;
+            uint32_t ovf_cnt_hsch3:        1;
+            uint32_t ovf_cnt_hsch4:        1;
+            uint32_t ovf_cnt_hsch5:        1;
+            uint32_t ovf_cnt_hsch6:        1;
+            uint32_t ovf_cnt_hsch7:        1;
+            uint32_t ovf_cnt_lsch0:        1;
+            uint32_t ovf_cnt_lsch1:        1;
+            uint32_t ovf_cnt_lsch2:        1;
+            uint32_t ovf_cnt_lsch3:        1;
+            uint32_t ovf_cnt_lsch4:        1;
+            uint32_t ovf_cnt_lsch5:        1;
+            uint32_t ovf_cnt_lsch6:        1;
+            uint32_t ovf_cnt_lsch7:        1;
+            uint32_t reserved16:          16;
+        };
+        uint32_t val;
+    } int1_st;
+    union {
+        struct {
+            uint32_t ovf_cnt_hsch0:         1;
+            uint32_t ovf_cnt_hsch1:         1;
+            uint32_t ovf_cnt_hsch2:         1;
+            uint32_t ovf_cnt_hsch3:         1;
+            uint32_t ovf_cnt_hsch4:         1;
+            uint32_t ovf_cnt_hsch5:         1;
+            uint32_t ovf_cnt_hsch6:         1;
+            uint32_t ovf_cnt_hsch7:         1;
+            uint32_t ovf_cnt_lsch0:         1;
+            uint32_t ovf_cnt_lsch1:         1;
+            uint32_t ovf_cnt_lsch2:         1;
+            uint32_t ovf_cnt_lsch3:         1;
+            uint32_t ovf_cnt_lsch4:         1;
+            uint32_t ovf_cnt_lsch5:         1;
+            uint32_t ovf_cnt_lsch6:         1;
+            uint32_t ovf_cnt_lsch7:         1;
+            uint32_t reserved16:           16;
+        };
+        uint32_t val;
+    } int1_ena;
+    union {
+        struct {
+            uint32_t ovf_cnt_hsch0:         1;
+            uint32_t ovf_cnt_hsch1:         1;
+            uint32_t ovf_cnt_hsch2:         1;
+            uint32_t ovf_cnt_hsch3:         1;
+            uint32_t ovf_cnt_hsch4:         1;
+            uint32_t ovf_cnt_hsch5:         1;
+            uint32_t ovf_cnt_hsch6:         1;
+            uint32_t ovf_cnt_hsch7:         1;
+            uint32_t ovf_cnt_lsch0:         1;
+            uint32_t ovf_cnt_lsch1:         1;
+            uint32_t ovf_cnt_lsch2:         1;
+            uint32_t ovf_cnt_lsch3:         1;
+            uint32_t ovf_cnt_lsch4:         1;
+            uint32_t ovf_cnt_lsch5:         1;
+            uint32_t ovf_cnt_lsch6:         1;
+            uint32_t ovf_cnt_lsch7:         1;
+            uint32_t reserved16:           16;
+        };
+        uint32_t val;
+    } int1_clr;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t date;                                     /*This register represents the version .*/
+} ledc_dev_t;
+extern ledc_dev_t LEDC;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_LEDC_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/mcpwm_reg.h b/components/soc/esp32s2beta/include/soc/mcpwm_reg.h
new file mode 100644
index 000000000..1dce94d46
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/mcpwm_reg.h
@@ -0,0 +1,3028 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_MCPWM_REG_H_
+#define _SOC_MCPWM_REG_H_
+#include "soc.h"
+
+#define REG_MCPWM_BASE(i)               (DR_REG_PWM_BASE + i * (0xE000))
+#define MCPWM_CLK_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0000)
+/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
+#define MCPWM_CLK_PRESCALE  0x000000FF
+#define MCPWM_CLK_PRESCALE_M  ((MCPWM_CLK_PRESCALE_V)<<(MCPWM_CLK_PRESCALE_S))
+#define MCPWM_CLK_PRESCALE_V  0xFF
+#define MCPWM_CLK_PRESCALE_S  0
+
+#define MCPWM_TIMER0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0004)
+/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer0 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync. TEZ here and below means timer equal zero event*/
+#define MCPWM_TIMER0_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_M  ((MCPWM_TIMER0_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER0_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER0_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer0*/
+#define MCPWM_TIMER0_PERIOD  0x0000FFFF
+#define MCPWM_TIMER0_PERIOD_M  ((MCPWM_TIMER0_PERIOD_V)<<(MCPWM_TIMER0_PERIOD_S))
+#define MCPWM_TIMER0_PERIOD_V  0xFFFF
+#define MCPWM_TIMER0_PERIOD_S  8
+/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
+#define MCPWM_TIMER0_PRESCALE  0x000000FF
+#define MCPWM_TIMER0_PRESCALE_M  ((MCPWM_TIMER0_PRESCALE_V)<<(MCPWM_TIMER0_PRESCALE_S))
+#define MCPWM_TIMER0_PRESCALE_V  0xFF
+#define MCPWM_TIMER0_PRESCALE_S  0
+
+#define MCPWM_TIMER0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0008)
+/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer0 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER0_MOD  0x00000003
+#define MCPWM_TIMER0_MOD_M  ((MCPWM_TIMER0_MOD_V)<<(MCPWM_TIMER0_MOD_S))
+#define MCPWM_TIMER0_MOD_V  0x3
+#define MCPWM_TIMER0_MOD_S  3
+/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
+#define MCPWM_TIMER0_START  0x00000007
+#define MCPWM_TIMER0_START_M  ((MCPWM_TIMER0_START_V)<<(MCPWM_TIMER0_START_S))
+#define MCPWM_TIMER0_START_V  0x7
+#define MCPWM_TIMER0_START_S  0
+
+#define MCPWM_TIMER0_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x000c)
+/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER0_PHASE  0x0001FFFF
+#define MCPWM_TIMER0_PHASE_M  ((MCPWM_TIMER0_PHASE_V)<<(MCPWM_TIMER0_PHASE_S))
+#define MCPWM_TIMER0_PHASE_V  0x1FFFF
+#define MCPWM_TIMER0_PHASE_S  4
+/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER0_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER0_SYNCO_SEL_M  ((MCPWM_TIMER0_SYNCO_SEL_V)<<(MCPWM_TIMER0_SYNCO_SEL_S))
+#define MCPWM_TIMER0_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER0_SYNCO_SEL_S  2
+/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER0_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER0_SYNC_SW_V  0x1
+#define MCPWM_TIMER0_SYNC_SW_S  1
+/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER0_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER0_SYNCI_EN_V  0x1
+#define MCPWM_TIMER0_SYNCI_EN_S  0
+
+#define MCPWM_TIMER0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0010)
+/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer0 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER0_DIRECTION  (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER0_DIRECTION_V  0x1
+#define MCPWM_TIMER0_DIRECTION_S  16
+/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer0 counter value*/
+#define MCPWM_TIMER0_VALUE  0x0000FFFF
+#define MCPWM_TIMER0_VALUE_M  ((MCPWM_TIMER0_VALUE_V)<<(MCPWM_TIMER0_VALUE_S))
+#define MCPWM_TIMER0_VALUE_V  0xFFFF
+#define MCPWM_TIMER0_VALUE_S  0
+
+#define MCPWM_TIMER1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0014)
+/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer1 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync*/
+#define MCPWM_TIMER1_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_M  ((MCPWM_TIMER1_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER1_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER1_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer1*/
+#define MCPWM_TIMER1_PERIOD  0x0000FFFF
+#define MCPWM_TIMER1_PERIOD_M  ((MCPWM_TIMER1_PERIOD_V)<<(MCPWM_TIMER1_PERIOD_S))
+#define MCPWM_TIMER1_PERIOD_V  0xFFFF
+#define MCPWM_TIMER1_PERIOD_S  8
+/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT1_clk = Period of PWM_clk * (PWM_TIMER1_PRESCALE + 1)*/
+#define MCPWM_TIMER1_PRESCALE  0x000000FF
+#define MCPWM_TIMER1_PRESCALE_M  ((MCPWM_TIMER1_PRESCALE_V)<<(MCPWM_TIMER1_PRESCALE_S))
+#define MCPWM_TIMER1_PRESCALE_V  0xFF
+#define MCPWM_TIMER1_PRESCALE_S  0
+
+#define MCPWM_TIMER1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0018)
+/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer1 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER1_MOD  0x00000003
+#define MCPWM_TIMER1_MOD_M  ((MCPWM_TIMER1_MOD_V)<<(MCPWM_TIMER1_MOD_S))
+#define MCPWM_TIMER1_MOD_V  0x3
+#define MCPWM_TIMER1_MOD_S  3
+/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer1 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
+#define MCPWM_TIMER1_START  0x00000007
+#define MCPWM_TIMER1_START_M  ((MCPWM_TIMER1_START_V)<<(MCPWM_TIMER1_START_S))
+#define MCPWM_TIMER1_START_V  0x7
+#define MCPWM_TIMER1_START_S  0
+
+#define MCPWM_TIMER1_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x001c)
+/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER1_PHASE  0x0001FFFF
+#define MCPWM_TIMER1_PHASE_M  ((MCPWM_TIMER1_PHASE_V)<<(MCPWM_TIMER1_PHASE_S))
+#define MCPWM_TIMER1_PHASE_V  0x1FFFF
+#define MCPWM_TIMER1_PHASE_S  4
+/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer1 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER1_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER1_SYNCO_SEL_M  ((MCPWM_TIMER1_SYNCO_SEL_V)<<(MCPWM_TIMER1_SYNCO_SEL_S))
+#define MCPWM_TIMER1_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER1_SYNCO_SEL_S  2
+/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER1_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER1_SYNC_SW_V  0x1
+#define MCPWM_TIMER1_SYNC_SW_S  1
+/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER1_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER1_SYNCI_EN_V  0x1
+#define MCPWM_TIMER1_SYNCI_EN_S  0
+
+#define MCPWM_TIMER1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0020)
+/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer1 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER1_DIRECTION  (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER1_DIRECTION_V  0x1
+#define MCPWM_TIMER1_DIRECTION_S  16
+/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer1 counter value*/
+#define MCPWM_TIMER1_VALUE  0x0000FFFF
+#define MCPWM_TIMER1_VALUE_M  ((MCPWM_TIMER1_VALUE_V)<<(MCPWM_TIMER1_VALUE_S))
+#define MCPWM_TIMER1_VALUE_V  0xFFFF
+#define MCPWM_TIMER1_VALUE_S  0
+
+#define MCPWM_TIMER2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0024)
+/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: Update method for active reg of PWM timer2 period  0: immediate
+  1: TEZ  2: sync  3: TEZ or sync*/
+#define MCPWM_TIMER2_PERIOD_UPMETHOD  0x00000003
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_M  ((MCPWM_TIMER2_PERIOD_UPMETHOD_V)<<(MCPWM_TIMER2_PERIOD_UPMETHOD_S))
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_V  0x3
+#define MCPWM_TIMER2_PERIOD_UPMETHOD_S  24
+/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */
+/*description: Period shadow reg of PWM timer2*/
+#define MCPWM_TIMER2_PERIOD  0x0000FFFF
+#define MCPWM_TIMER2_PERIOD_M  ((MCPWM_TIMER2_PERIOD_V)<<(MCPWM_TIMER2_PERIOD_S))
+#define MCPWM_TIMER2_PERIOD_V  0xFFFF
+#define MCPWM_TIMER2_PERIOD_S  8
+/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: Period of PT2_clk = Period of PWM_clk * (PWM_TIMER2_PRESCALE + 1)*/
+#define MCPWM_TIMER2_PRESCALE  0x000000FF
+#define MCPWM_TIMER2_PRESCALE_M  ((MCPWM_TIMER2_PRESCALE_V)<<(MCPWM_TIMER2_PRESCALE_S))
+#define MCPWM_TIMER2_PRESCALE_V  0xFF
+#define MCPWM_TIMER2_PRESCALE_S  0
+
+#define MCPWM_TIMER2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x0028)
+/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */
+/*description: PWM timer2 working mode  0: freeze  1: increase mod  2: decrease
+ mod  3: up-down mod*/
+#define MCPWM_TIMER2_MOD  0x00000003
+#define MCPWM_TIMER2_MOD_M  ((MCPWM_TIMER2_MOD_V)<<(MCPWM_TIMER2_MOD_S))
+#define MCPWM_TIMER2_MOD_V  0x3
+#define MCPWM_TIMER2_MOD_S  3
+/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: PWM timer2 start and stop control. 0: stop @ TEZ  1: stop @ TEP
+  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP.*/
+#define MCPWM_TIMER2_START  0x00000007
+#define MCPWM_TIMER2_START_M  ((MCPWM_TIMER2_START_V)<<(MCPWM_TIMER2_START_S))
+#define MCPWM_TIMER2_START_V  0x7
+#define MCPWM_TIMER2_START_S  0
+
+#define MCPWM_TIMER2_SYNC_REG(i)          (REG_MCPWM_BASE(i) + 0x002c)
+/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */
+/*description: Phase for timer reload on sync event*/
+#define MCPWM_TIMER2_PHASE  0x0001FFFF
+#define MCPWM_TIMER2_PHASE_M  ((MCPWM_TIMER2_PHASE_V)<<(MCPWM_TIMER2_PHASE_S))
+#define MCPWM_TIMER2_PHASE_V  0x1FFFF
+#define MCPWM_TIMER2_PHASE_S  4
+/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: PWM timer2 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+#define MCPWM_TIMER2_SYNCO_SEL  0x00000003
+#define MCPWM_TIMER2_SYNCO_SEL_M  ((MCPWM_TIMER2_SYNCO_SEL_V)<<(MCPWM_TIMER2_SYNCO_SEL_S))
+#define MCPWM_TIMER2_SYNCO_SEL_V  0x3
+#define MCPWM_TIMER2_SYNCO_SEL_S  2
+/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Toggling this bit will trigger a software sync*/
+#define MCPWM_TIMER2_SYNC_SW  (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_M  (BIT(1))
+#define MCPWM_TIMER2_SYNC_SW_V  0x1
+#define MCPWM_TIMER2_SYNC_SW_S  1
+/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: When set   timer reload with phase on sync input event is enabled*/
+#define MCPWM_TIMER2_SYNCI_EN  (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_M  (BIT(0))
+#define MCPWM_TIMER2_SYNCI_EN_V  0x1
+#define MCPWM_TIMER2_SYNCI_EN_S  0
+
+#define MCPWM_TIMER2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0030)
+/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Current PWM timer2 counter direction  0: increment 1: decrement*/
+#define MCPWM_TIMER2_DIRECTION  (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_M  (BIT(16))
+#define MCPWM_TIMER2_DIRECTION_V  0x1
+#define MCPWM_TIMER2_DIRECTION_S  16
+/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Current PWM timer2 counter value*/
+#define MCPWM_TIMER2_VALUE  0x0000FFFF
+#define MCPWM_TIMER2_VALUE_M  ((MCPWM_TIMER2_VALUE_V)<<(MCPWM_TIMER2_VALUE_S))
+#define MCPWM_TIMER2_VALUE_V  0xFFFF
+#define MCPWM_TIMER2_VALUE_S  0
+
+#define MCPWM_TIMER_SYNCI_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0034)
+/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: Onvert SYNC2 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI2_INVERT  (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_M  (BIT(11))
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI2_INVERT_S  11
+/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Invert SYNC1 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI1_INVERT  (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_M  (BIT(10))
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI1_INVERT_S  10
+/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Invert SYNC0 from GPIO matrix*/
+#define MCPWM_EXTERNAL_SYNCI0_INVERT  (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_M  (BIT(9))
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_V  0x1
+#define MCPWM_EXTERNAL_SYNCI0_INVERT_S  9
+/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer2  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER2_SYNCISEL  0x00000007
+#define MCPWM_TIMER2_SYNCISEL_M  ((MCPWM_TIMER2_SYNCISEL_V)<<(MCPWM_TIMER2_SYNCISEL_S))
+#define MCPWM_TIMER2_SYNCISEL_V  0x7
+#define MCPWM_TIMER2_SYNCISEL_S  6
+/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer1  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER1_SYNCISEL  0x00000007
+#define MCPWM_TIMER1_SYNCISEL_M  ((MCPWM_TIMER1_SYNCISEL_V)<<(MCPWM_TIMER1_SYNCISEL_S))
+#define MCPWM_TIMER1_SYNCISEL_V  0x7
+#define MCPWM_TIMER1_SYNCISEL_S  3
+/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */
+/*description: Select sync input for PWM timer0  1: PWM timer0 synco  2: PWM
+ timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  other values: no sync input selected*/
+#define MCPWM_TIMER0_SYNCISEL  0x00000007
+#define MCPWM_TIMER0_SYNCISEL_M  ((MCPWM_TIMER0_SYNCISEL_V)<<(MCPWM_TIMER0_SYNCISEL_S))
+#define MCPWM_TIMER0_SYNCISEL_V  0x7
+#define MCPWM_TIMER0_SYNCISEL_S  0
+
+#define MCPWM_OPERATOR_TIMERSEL_REG(i)          (REG_MCPWM_BASE(i) + 0x0038)
+/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator2
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR2_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR2_TIMERSEL_M  ((MCPWM_OPERATOR2_TIMERSEL_V)<<(MCPWM_OPERATOR2_TIMERSEL_S))
+#define MCPWM_OPERATOR2_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR2_TIMERSEL_S  4
+/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator1
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR1_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR1_TIMERSEL_M  ((MCPWM_OPERATOR1_TIMERSEL_V)<<(MCPWM_OPERATOR1_TIMERSEL_S))
+#define MCPWM_OPERATOR1_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR1_TIMERSEL_S  2
+/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Select which PWM timer's is the timing reference for PWM operator0
+  0: timer0  1: timer1  2: timer2*/
+#define MCPWM_OPERATOR0_TIMERSEL  0x00000003
+#define MCPWM_OPERATOR0_TIMERSEL_M  ((MCPWM_OPERATOR0_TIMERSEL_V)<<(MCPWM_OPERATOR0_TIMERSEL_S))
+#define MCPWM_OPERATOR0_TIMERSEL_V  0x3
+#define MCPWM_OPERATOR0_TIMERSEL_S  0
+
+#define MCPWM_GEN0_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x003c)
+/* MCPWM_GEN0_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN0_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN0_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN0_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN0_B_SHDW_FULL_S  9
+/* MCPWM_GEN0_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 0 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN0_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN0_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN0_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN0_A_SHDW_FULL_S  8
+/* MCPWM_GEN0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN0_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_B_UPMETHOD_M  ((MCPWM_GEN0_B_UPMETHOD_V)<<(MCPWM_GEN0_B_UPMETHOD_S))
+#define MCPWM_GEN0_B_UPMETHOD_V  0xF
+#define MCPWM_GEN0_B_UPMETHOD_S  4
+/* MCPWM_GEN0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN0_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_A_UPMETHOD_M  ((MCPWM_GEN0_A_UPMETHOD_V)<<(MCPWM_GEN0_A_UPMETHOD_S))
+#define MCPWM_GEN0_A_UPMETHOD_V  0xF
+#define MCPWM_GEN0_A_UPMETHOD_S  0
+
+#define MCPWM_GEN0_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0040)
+/* MCPWM_GEN0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 0 time stamp A's shadow reg*/
+#define MCPWM_GEN0_A  0x0000FFFF
+#define MCPWM_GEN0_A_M  ((MCPWM_GEN0_A_V)<<(MCPWM_GEN0_A_S))
+#define MCPWM_GEN0_A_V  0xFFFF
+#define MCPWM_GEN0_A_S  0
+
+#define MCPWM_GEN0_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0044)
+/* MCPWM_GEN0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 0 time stamp B's shadow reg*/
+#define MCPWM_GEN0_B  0x0000FFFF
+#define MCPWM_GEN0_B_M  ((MCPWM_GEN0_B_V)<<(MCPWM_GEN0_B_S))
+#define MCPWM_GEN0_B_V  0xFFFF
+#define MCPWM_GEN0_B_S  0
+
+#define MCPWM_GEN0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0048)
+/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generator 0 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN0_T1_SEL  0x00000007
+#define MCPWM_GEN0_T1_SEL_M  ((MCPWM_GEN0_T1_SEL_V)<<(MCPWM_GEN0_T1_SEL_S))
+#define MCPWM_GEN0_T1_SEL_V  0x7
+#define MCPWM_GEN0_T1_SEL_S  7
+/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generator 0 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN0_T0_SEL  0x00000007
+#define MCPWM_GEN0_T0_SEL_M  ((MCPWM_GEN0_T0_SEL_V)<<(MCPWM_GEN0_T0_SEL_S))
+#define MCPWM_GEN0_T0_SEL_V  0x7
+#define MCPWM_GEN0_T0_SEL_S  4
+/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 0's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN0_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN0_CFG_UPMETHOD_M  ((MCPWM_GEN0_CFG_UPMETHOD_V)<<(MCPWM_GEN0_CFG_UPMETHOD_S))
+#define MCPWM_GEN0_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN0_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN0_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x004c)
+/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM0B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN0_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN0_B_NCIFORCE_MODE_M  ((MCPWM_GEN0_B_NCIFORCE_MODE_V)<<(MCPWM_GEN0_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN0_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN0_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM0B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN0_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN0_B_NCIFORCE_V  0x1
+#define MCPWM_GEN0_B_NCIFORCE_S  13
+/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM0A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN0_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN0_A_NCIFORCE_MODE_M  ((MCPWM_GEN0_A_NCIFORCE_MODE_V)<<(MCPWM_GEN0_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN0_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN0_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM0A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN0_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN0_A_NCIFORCE_V  0x1
+#define MCPWM_GEN0_A_NCIFORCE_S  10
+/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM0B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN0_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_M  ((MCPWM_GEN0_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN0_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM0A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN0_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_M  ((MCPWM_GEN0_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN0_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN0_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator0.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN0_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN0_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0050)
+/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN0_A_DT1  0x00000003
+#define MCPWM_GEN0_A_DT1_M  ((MCPWM_GEN0_A_DT1_V)<<(MCPWM_GEN0_A_DT1_S))
+#define MCPWM_GEN0_A_DT1_V  0x3
+#define MCPWM_GEN0_A_DT1_S  22
+/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN0_A_DT0  0x00000003
+#define MCPWM_GEN0_A_DT0_M  ((MCPWM_GEN0_A_DT0_V)<<(MCPWM_GEN0_A_DT0_S))
+#define MCPWM_GEN0_A_DT0_V  0x3
+#define MCPWM_GEN0_A_DT0_S  20
+/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN0_A_DTEB  0x00000003
+#define MCPWM_GEN0_A_DTEB_M  ((MCPWM_GEN0_A_DTEB_V)<<(MCPWM_GEN0_A_DTEB_S))
+#define MCPWM_GEN0_A_DTEB_V  0x3
+#define MCPWM_GEN0_A_DTEB_S  18
+/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN0_A_DTEA  0x00000003
+#define MCPWM_GEN0_A_DTEA_M  ((MCPWM_GEN0_A_DTEA_V)<<(MCPWM_GEN0_A_DTEA_S))
+#define MCPWM_GEN0_A_DTEA_V  0x3
+#define MCPWM_GEN0_A_DTEA_S  16
+/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN0_A_DTEP  0x00000003
+#define MCPWM_GEN0_A_DTEP_M  ((MCPWM_GEN0_A_DTEP_V)<<(MCPWM_GEN0_A_DTEP_S))
+#define MCPWM_GEN0_A_DTEP_V  0x3
+#define MCPWM_GEN0_A_DTEP_S  14
+/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN0_A_DTEZ  0x00000003
+#define MCPWM_GEN0_A_DTEZ_M  ((MCPWM_GEN0_A_DTEZ_V)<<(MCPWM_GEN0_A_DTEZ_S))
+#define MCPWM_GEN0_A_DTEZ_V  0x3
+#define MCPWM_GEN0_A_DTEZ_S  12
+/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN0_A_UT1  0x00000003
+#define MCPWM_GEN0_A_UT1_M  ((MCPWM_GEN0_A_UT1_V)<<(MCPWM_GEN0_A_UT1_S))
+#define MCPWM_GEN0_A_UT1_V  0x3
+#define MCPWM_GEN0_A_UT1_S  10
+/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN0_A_UT0  0x00000003
+#define MCPWM_GEN0_A_UT0_M  ((MCPWM_GEN0_A_UT0_V)<<(MCPWM_GEN0_A_UT0_S))
+#define MCPWM_GEN0_A_UT0_V  0x3
+#define MCPWM_GEN0_A_UT0_S  8
+/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN0_A_UTEB  0x00000003
+#define MCPWM_GEN0_A_UTEB_M  ((MCPWM_GEN0_A_UTEB_V)<<(MCPWM_GEN0_A_UTEB_S))
+#define MCPWM_GEN0_A_UTEB_V  0x3
+#define MCPWM_GEN0_A_UTEB_S  6
+/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN0_A_UTEA  0x00000003
+#define MCPWM_GEN0_A_UTEA_M  ((MCPWM_GEN0_A_UTEA_V)<<(MCPWM_GEN0_A_UTEA_S))
+#define MCPWM_GEN0_A_UTEA_V  0x3
+#define MCPWM_GEN0_A_UTEA_S  4
+/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN0_A_UTEP  0x00000003
+#define MCPWM_GEN0_A_UTEP_M  ((MCPWM_GEN0_A_UTEP_V)<<(MCPWM_GEN0_A_UTEP_S))
+#define MCPWM_GEN0_A_UTEP_V  0x3
+#define MCPWM_GEN0_A_UTEP_S  2
+/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM0A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN0_A_UTEZ  0x00000003
+#define MCPWM_GEN0_A_UTEZ_M  ((MCPWM_GEN0_A_UTEZ_V)<<(MCPWM_GEN0_A_UTEZ_S))
+#define MCPWM_GEN0_A_UTEZ_V  0x3
+#define MCPWM_GEN0_A_UTEZ_S  0
+
+#define MCPWM_GEN0_B_REG(i)          (REG_MCPWM_BASE(i) + 0x0054)
+/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN0_B_DT1  0x00000003
+#define MCPWM_GEN0_B_DT1_M  ((MCPWM_GEN0_B_DT1_V)<<(MCPWM_GEN0_B_DT1_S))
+#define MCPWM_GEN0_B_DT1_V  0x3
+#define MCPWM_GEN0_B_DT1_S  22
+/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN0_B_DT0  0x00000003
+#define MCPWM_GEN0_B_DT0_M  ((MCPWM_GEN0_B_DT0_V)<<(MCPWM_GEN0_B_DT0_S))
+#define MCPWM_GEN0_B_DT0_V  0x3
+#define MCPWM_GEN0_B_DT0_S  20
+/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN0_B_DTEB  0x00000003
+#define MCPWM_GEN0_B_DTEB_M  ((MCPWM_GEN0_B_DTEB_V)<<(MCPWM_GEN0_B_DTEB_S))
+#define MCPWM_GEN0_B_DTEB_V  0x3
+#define MCPWM_GEN0_B_DTEB_S  18
+/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN0_B_DTEA  0x00000003
+#define MCPWM_GEN0_B_DTEA_M  ((MCPWM_GEN0_B_DTEA_V)<<(MCPWM_GEN0_B_DTEA_S))
+#define MCPWM_GEN0_B_DTEA_V  0x3
+#define MCPWM_GEN0_B_DTEA_S  16
+/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN0_B_DTEP  0x00000003
+#define MCPWM_GEN0_B_DTEP_M  ((MCPWM_GEN0_B_DTEP_V)<<(MCPWM_GEN0_B_DTEP_S))
+#define MCPWM_GEN0_B_DTEP_V  0x3
+#define MCPWM_GEN0_B_DTEP_S  14
+/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN0_B_DTEZ  0x00000003
+#define MCPWM_GEN0_B_DTEZ_M  ((MCPWM_GEN0_B_DTEZ_V)<<(MCPWM_GEN0_B_DTEZ_S))
+#define MCPWM_GEN0_B_DTEZ_V  0x3
+#define MCPWM_GEN0_B_DTEZ_S  12
+/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN0_B_UT1  0x00000003
+#define MCPWM_GEN0_B_UT1_M  ((MCPWM_GEN0_B_UT1_V)<<(MCPWM_GEN0_B_UT1_S))
+#define MCPWM_GEN0_B_UT1_V  0x3
+#define MCPWM_GEN0_B_UT1_S  10
+/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN0_B_UT0  0x00000003
+#define MCPWM_GEN0_B_UT0_M  ((MCPWM_GEN0_B_UT0_V)<<(MCPWM_GEN0_B_UT0_S))
+#define MCPWM_GEN0_B_UT0_V  0x3
+#define MCPWM_GEN0_B_UT0_S  8
+/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN0_B_UTEB  0x00000003
+#define MCPWM_GEN0_B_UTEB_M  ((MCPWM_GEN0_B_UTEB_V)<<(MCPWM_GEN0_B_UTEB_S))
+#define MCPWM_GEN0_B_UTEB_V  0x3
+#define MCPWM_GEN0_B_UTEB_S  6
+/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN0_B_UTEA  0x00000003
+#define MCPWM_GEN0_B_UTEA_M  ((MCPWM_GEN0_B_UTEA_V)<<(MCPWM_GEN0_B_UTEA_S))
+#define MCPWM_GEN0_B_UTEA_V  0x3
+#define MCPWM_GEN0_B_UTEA_S  4
+/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN0_B_UTEP  0x00000003
+#define MCPWM_GEN0_B_UTEP_M  ((MCPWM_GEN0_B_UTEP_V)<<(MCPWM_GEN0_B_UTEP_S))
+#define MCPWM_GEN0_B_UTEP_V  0x3
+#define MCPWM_GEN0_B_UTEP_S  2
+/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM0B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN0_B_UTEZ  0x00000003
+#define MCPWM_GEN0_B_UTEZ_M  ((MCPWM_GEN0_B_UTEZ_V)<<(MCPWM_GEN0_B_UTEZ_S))
+#define MCPWM_GEN0_B_UTEZ_V  0x3
+#define MCPWM_GEN0_B_UTEZ_S  0
+
+#define MCPWM_DT0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0058)
+/* MCPWM_DT0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 0 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT0_CLK_SEL  (BIT(17))
+#define MCPWM_DT0_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT0_CLK_SEL_V  0x1
+#define MCPWM_DT0_CLK_SEL_S  17
+/* MCPWM_DT0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT0_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT0_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT0_B_OUTBYPASS_V  0x1
+#define MCPWM_DT0_B_OUTBYPASS_S  16
+/* MCPWM_DT0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT0_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT0_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT0_A_OUTBYPASS_V  0x1
+#define MCPWM_DT0_A_OUTBYPASS_S  15
+/* MCPWM_DT0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT0_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT0_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT0_FED_OUTINVERT_V  0x1
+#define MCPWM_DT0_FED_OUTINVERT_S  14
+/* MCPWM_DT0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT0_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT0_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT0_RED_OUTINVERT_V  0x1
+#define MCPWM_DT0_RED_OUTINVERT_S  13
+/* MCPWM_DT0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT0_FED_INSEL  (BIT(12))
+#define MCPWM_DT0_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT0_FED_INSEL_V  0x1
+#define MCPWM_DT0_FED_INSEL_S  12
+/* MCPWM_DT0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT0_RED_INSEL  (BIT(11))
+#define MCPWM_DT0_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT0_RED_INSEL_V  0x1
+#define MCPWM_DT0_RED_INSEL_S  11
+/* MCPWM_DT0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT0_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT0_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT0_B_OUTSWAP_V  0x1
+#define MCPWM_DT0_B_OUTSWAP_S  10
+/* MCPWM_DT0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT0_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT0_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT0_A_OUTSWAP_V  0x1
+#define MCPWM_DT0_A_OUTSWAP_S  9
+/* MCPWM_DT0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT0_DEB_MODE  (BIT(8))
+#define MCPWM_DT0_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT0_DEB_MODE_V  0x1
+#define MCPWM_DT0_DEB_MODE_S  8
+/* MCPWM_DT0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT0_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT0_RED_UPMETHOD_M  ((MCPWM_DT0_RED_UPMETHOD_V)<<(MCPWM_DT0_RED_UPMETHOD_S))
+#define MCPWM_DT0_RED_UPMETHOD_V  0xF
+#define MCPWM_DT0_RED_UPMETHOD_S  4
+/* MCPWM_DT0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT0_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT0_FED_UPMETHOD_M  ((MCPWM_DT0_FED_UPMETHOD_V)<<(MCPWM_DT0_FED_UPMETHOD_S))
+#define MCPWM_DT0_FED_UPMETHOD_V  0xF
+#define MCPWM_DT0_FED_UPMETHOD_S  0
+
+#define MCPWM_DT0_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x005c)
+/* MCPWM_DT0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT0_FED  0x0000FFFF
+#define MCPWM_DT0_FED_M  ((MCPWM_DT0_FED_V)<<(MCPWM_DT0_FED_S))
+#define MCPWM_DT0_FED_V  0xFFFF
+#define MCPWM_DT0_FED_S  0
+
+#define MCPWM_DT0_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0060)
+/* MCPWM_DT0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT0_RED  0x0000FFFF
+#define MCPWM_DT0_RED_M  ((MCPWM_DT0_RED_V)<<(MCPWM_DT0_RED_S))
+#define MCPWM_DT0_RED_V  0xFFFF
+#define MCPWM_DT0_RED_S  0
+
+#define MCPWM_CARRIER0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0064)
+/* MCPWM_CARRIER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM0A and PWM0B for this submodule*/
+#define MCPWM_CARRIER0_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER0_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER0_IN_INVERT_V  0x1
+#define MCPWM_CARRIER0_IN_INVERT_S  13
+/* MCPWM_CARRIER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM0A and PWM0B for this submodule*/
+#define MCPWM_CARRIER0_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER0_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER0_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER0_OUT_INVERT_S  12
+/* MCPWM_CARRIER0_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER0_OSHWTH  0x0000000F
+#define MCPWM_CARRIER0_OSHWTH_M  ((MCPWM_CARRIER0_OSHWTH_V)<<(MCPWM_CARRIER0_OSHWTH_S))
+#define MCPWM_CARRIER0_OSHWTH_V  0xF
+#define MCPWM_CARRIER0_OSHWTH_S  8
+/* MCPWM_CARRIER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
+#define MCPWM_CARRIER0_DUTY  0x00000007
+#define MCPWM_CARRIER0_DUTY_M  ((MCPWM_CARRIER0_DUTY_V)<<(MCPWM_CARRIER0_DUTY_S))
+#define MCPWM_CARRIER0_DUTY_V  0x7
+#define MCPWM_CARRIER0_DUTY_S  5
+/* MCPWM_CARRIER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier0 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
+#define MCPWM_CARRIER0_PRESCALE  0x0000000F
+#define MCPWM_CARRIER0_PRESCALE_M  ((MCPWM_CARRIER0_PRESCALE_V)<<(MCPWM_CARRIER0_PRESCALE_S))
+#define MCPWM_CARRIER0_PRESCALE_V  0xF
+#define MCPWM_CARRIER0_PRESCALE_S  1
+/* MCPWM_CARRIER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier0 function is enabled. When cleared  carrier0 is bypassed*/
+#define MCPWM_CARRIER0_EN  (BIT(0))
+#define MCPWM_CARRIER0_EN_M  (BIT(0))
+#define MCPWM_CARRIER0_EN_V  0x1
+#define MCPWM_CARRIER0_EN_S  0
+
+#define MCPWM_FH0_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0068)
+/* MCPWM_FH0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_OST_U  0x00000003
+#define MCPWM_FH0_B_OST_U_M  ((MCPWM_FH0_B_OST_U_V)<<(MCPWM_FH0_B_OST_U_S))
+#define MCPWM_FH0_B_OST_U_V  0x3
+#define MCPWM_FH0_B_OST_U_S  22
+/* MCPWM_FH0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_OST_D  0x00000003
+#define MCPWM_FH0_B_OST_D_M  ((MCPWM_FH0_B_OST_D_V)<<(MCPWM_FH0_B_OST_D_S))
+#define MCPWM_FH0_B_OST_D_V  0x3
+#define MCPWM_FH0_B_OST_D_S  20
+/* MCPWM_FH0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_CBC_U  0x00000003
+#define MCPWM_FH0_B_CBC_U_M  ((MCPWM_FH0_B_CBC_U_V)<<(MCPWM_FH0_B_CBC_U_S))
+#define MCPWM_FH0_B_CBC_U_V  0x3
+#define MCPWM_FH0_B_CBC_U_S  18
+/* MCPWM_FH0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_B_CBC_D  0x00000003
+#define MCPWM_FH0_B_CBC_D_M  ((MCPWM_FH0_B_CBC_D_V)<<(MCPWM_FH0_B_CBC_D_S))
+#define MCPWM_FH0_B_CBC_D_V  0x3
+#define MCPWM_FH0_B_CBC_D_S  16
+/* MCPWM_FH0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_OST_U  0x00000003
+#define MCPWM_FH0_A_OST_U_M  ((MCPWM_FH0_A_OST_U_V)<<(MCPWM_FH0_A_OST_U_S))
+#define MCPWM_FH0_A_OST_U_V  0x3
+#define MCPWM_FH0_A_OST_U_S  14
+/* MCPWM_FH0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM0A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_OST_D  0x00000003
+#define MCPWM_FH0_A_OST_D_M  ((MCPWM_FH0_A_OST_D_V)<<(MCPWM_FH0_A_OST_D_S))
+#define MCPWM_FH0_A_OST_D_V  0x3
+#define MCPWM_FH0_A_OST_D_S  12
+/* MCPWM_FH0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_CBC_U  0x00000003
+#define MCPWM_FH0_A_CBC_U_M  ((MCPWM_FH0_A_CBC_U_V)<<(MCPWM_FH0_A_CBC_U_S))
+#define MCPWM_FH0_A_CBC_U_V  0x3
+#define MCPWM_FH0_A_CBC_U_S  10
+/* MCPWM_FH0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM0A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH0_A_CBC_D  0x00000003
+#define MCPWM_FH0_A_CBC_D_M  ((MCPWM_FH0_A_CBC_D_V)<<(MCPWM_FH0_A_CBC_D_S))
+#define MCPWM_FH0_A_CBC_D_V  0x3
+#define MCPWM_FH0_A_CBC_D_S  8
+/* MCPWM_FH0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F0_OST  (BIT(7))
+#define MCPWM_FH0_F0_OST_M  (BIT(7))
+#define MCPWM_FH0_F0_OST_V  0x1
+#define MCPWM_FH0_F0_OST_S  7
+/* MCPWM_FH0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F1_OST  (BIT(6))
+#define MCPWM_FH0_F1_OST_M  (BIT(6))
+#define MCPWM_FH0_F1_OST_V  0x1
+#define MCPWM_FH0_F1_OST_S  6
+/* MCPWM_FH0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F2_OST  (BIT(5))
+#define MCPWM_FH0_F2_OST_M  (BIT(5))
+#define MCPWM_FH0_F2_OST_V  0x1
+#define MCPWM_FH0_F2_OST_S  5
+/* MCPWM_FH0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_SW_OST  (BIT(4))
+#define MCPWM_FH0_SW_OST_M  (BIT(4))
+#define MCPWM_FH0_SW_OST_V  0x1
+#define MCPWM_FH0_SW_OST_S  4
+/* MCPWM_FH0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F0_CBC  (BIT(3))
+#define MCPWM_FH0_F0_CBC_M  (BIT(3))
+#define MCPWM_FH0_F0_CBC_V  0x1
+#define MCPWM_FH0_F0_CBC_S  3
+/* MCPWM_FH0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F1_CBC  (BIT(2))
+#define MCPWM_FH0_F1_CBC_M  (BIT(2))
+#define MCPWM_FH0_F1_CBC_V  0x1
+#define MCPWM_FH0_F1_CBC_S  2
+/* MCPWM_FH0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH0_F2_CBC  (BIT(1))
+#define MCPWM_FH0_F2_CBC_M  (BIT(1))
+#define MCPWM_FH0_F2_CBC_V  0x1
+#define MCPWM_FH0_F2_CBC_S  1
+/* MCPWM_FH0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH0_SW_CBC  (BIT(0))
+#define MCPWM_FH0_SW_CBC_M  (BIT(0))
+#define MCPWM_FH0_SW_CBC_V  0x1
+#define MCPWM_FH0_SW_CBC_S  0
+
+#define MCPWM_FH0_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x006c)
+/* MCPWM_FH0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH0_FORCE_OST  (BIT(4))
+#define MCPWM_FH0_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH0_FORCE_OST_V  0x1
+#define MCPWM_FH0_FORCE_OST_S  4
+/* MCPWM_FH0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH0_FORCE_CBC  (BIT(3))
+#define MCPWM_FH0_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH0_FORCE_CBC_V  0x1
+#define MCPWM_FH0_FORCE_CBC_S  3
+/* MCPWM_FH0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH0_CBCPULSE  0x00000003
+#define MCPWM_FH0_CBCPULSE_M  ((MCPWM_FH0_CBCPULSE_V)<<(MCPWM_FH0_CBCPULSE_S))
+#define MCPWM_FH0_CBCPULSE_V  0x3
+#define MCPWM_FH0_CBCPULSE_S  1
+/* MCPWM_FH0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH0_CLR_OST  (BIT(0))
+#define MCPWM_FH0_CLR_OST_M  (BIT(0))
+#define MCPWM_FH0_CLR_OST_V  0x1
+#define MCPWM_FH0_CLR_OST_S  0
+
+#define MCPWM_FH0_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0070)
+/* MCPWM_FH0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH0_OST_ON  (BIT(1))
+#define MCPWM_FH0_OST_ON_M  (BIT(1))
+#define MCPWM_FH0_OST_ON_V  0x1
+#define MCPWM_FH0_OST_ON_S  1
+/* MCPWM_FH0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH0_CBC_ON  (BIT(0))
+#define MCPWM_FH0_CBC_ON_M  (BIT(0))
+#define MCPWM_FH0_CBC_ON_V  0x1
+#define MCPWM_FH0_CBC_ON_S  0
+
+#define MCPWM_GEN1_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0074)
+/* MCPWM_GEN1_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN1_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN1_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN1_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN1_B_SHDW_FULL_S  9
+/* MCPWM_GEN1_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 1 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN1_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN1_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN1_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN1_A_SHDW_FULL_S  8
+/* MCPWM_GEN1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 1 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN1_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_B_UPMETHOD_M  ((MCPWM_GEN1_B_UPMETHOD_V)<<(MCPWM_GEN1_B_UPMETHOD_S))
+#define MCPWM_GEN1_B_UPMETHOD_V  0xF
+#define MCPWM_GEN1_B_UPMETHOD_S  4
+/* MCPWM_GEN1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 1 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN1_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_A_UPMETHOD_M  ((MCPWM_GEN1_A_UPMETHOD_V)<<(MCPWM_GEN1_A_UPMETHOD_S))
+#define MCPWM_GEN1_A_UPMETHOD_V  0xF
+#define MCPWM_GEN1_A_UPMETHOD_S  0
+
+#define MCPWM_GEN1_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0078)
+/* MCPWM_GEN1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 1 time stamp A's shadow reg*/
+#define MCPWM_GEN1_A  0x0000FFFF
+#define MCPWM_GEN1_A_M  ((MCPWM_GEN1_A_V)<<(MCPWM_GEN1_A_S))
+#define MCPWM_GEN1_A_V  0xFFFF
+#define MCPWM_GEN1_A_S  0
+
+#define MCPWM_GEN1_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x007c)
+/* MCPWM_GEN1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 1 time stamp B's shadow reg*/
+#define MCPWM_GEN1_B  0x0000FFFF
+#define MCPWM_GEN1_B_M  ((MCPWM_GEN1_B_V)<<(MCPWM_GEN1_B_S))
+#define MCPWM_GEN1_B_V  0xFFFF
+#define MCPWM_GEN1_B_S  0
+
+#define MCPWM_GEN1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x0080)
+/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate1 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN1_T1_SEL  0x00000007
+#define MCPWM_GEN1_T1_SEL_M  ((MCPWM_GEN1_T1_SEL_V)<<(MCPWM_GEN1_T1_SEL_S))
+#define MCPWM_GEN1_T1_SEL_V  0x7
+#define MCPWM_GEN1_T1_SEL_S  7
+/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate1 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN1_T0_SEL  0x00000007
+#define MCPWM_GEN1_T0_SEL_M  ((MCPWM_GEN1_T0_SEL_V)<<(MCPWM_GEN1_T0_SEL_S))
+#define MCPWM_GEN1_T0_SEL_V  0x7
+#define MCPWM_GEN1_T0_SEL_S  4
+/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generate1's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN1_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN1_CFG_UPMETHOD_M  ((MCPWM_GEN1_CFG_UPMETHOD_V)<<(MCPWM_GEN1_CFG_UPMETHOD_S))
+#define MCPWM_GEN1_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN1_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN1_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x0084)
+/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM1B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN1_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN1_B_NCIFORCE_MODE_M  ((MCPWM_GEN1_B_NCIFORCE_MODE_V)<<(MCPWM_GEN1_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN1_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN1_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM1B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN1_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN1_B_NCIFORCE_V  0x1
+#define MCPWM_GEN1_B_NCIFORCE_S  13
+/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM1A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN1_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN1_A_NCIFORCE_MODE_M  ((MCPWM_GEN1_A_NCIFORCE_MODE_V)<<(MCPWM_GEN1_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN1_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN1_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM1A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN1_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN1_A_NCIFORCE_V  0x1
+#define MCPWM_GEN1_A_NCIFORCE_S  10
+/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM1B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN1_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_M  ((MCPWM_GEN1_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN1_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM1A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN1_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_M  ((MCPWM_GEN1_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN1_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN1_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator1.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN1_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN1_A_REG(i)          (REG_MCPWM_BASE(i) + 0x0088)
+/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN1_A_DT1  0x00000003
+#define MCPWM_GEN1_A_DT1_M  ((MCPWM_GEN1_A_DT1_V)<<(MCPWM_GEN1_A_DT1_S))
+#define MCPWM_GEN1_A_DT1_V  0x3
+#define MCPWM_GEN1_A_DT1_S  22
+/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN1_A_DT0  0x00000003
+#define MCPWM_GEN1_A_DT0_M  ((MCPWM_GEN1_A_DT0_V)<<(MCPWM_GEN1_A_DT0_S))
+#define MCPWM_GEN1_A_DT0_V  0x3
+#define MCPWM_GEN1_A_DT0_S  20
+/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN1_A_DTEB  0x00000003
+#define MCPWM_GEN1_A_DTEB_M  ((MCPWM_GEN1_A_DTEB_V)<<(MCPWM_GEN1_A_DTEB_S))
+#define MCPWM_GEN1_A_DTEB_V  0x3
+#define MCPWM_GEN1_A_DTEB_S  18
+/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN1_A_DTEA  0x00000003
+#define MCPWM_GEN1_A_DTEA_M  ((MCPWM_GEN1_A_DTEA_V)<<(MCPWM_GEN1_A_DTEA_S))
+#define MCPWM_GEN1_A_DTEA_V  0x3
+#define MCPWM_GEN1_A_DTEA_S  16
+/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN1_A_DTEP  0x00000003
+#define MCPWM_GEN1_A_DTEP_M  ((MCPWM_GEN1_A_DTEP_V)<<(MCPWM_GEN1_A_DTEP_S))
+#define MCPWM_GEN1_A_DTEP_V  0x3
+#define MCPWM_GEN1_A_DTEP_S  14
+/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN1_A_DTEZ  0x00000003
+#define MCPWM_GEN1_A_DTEZ_M  ((MCPWM_GEN1_A_DTEZ_V)<<(MCPWM_GEN1_A_DTEZ_S))
+#define MCPWM_GEN1_A_DTEZ_V  0x3
+#define MCPWM_GEN1_A_DTEZ_S  12
+/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN1_A_UT1  0x00000003
+#define MCPWM_GEN1_A_UT1_M  ((MCPWM_GEN1_A_UT1_V)<<(MCPWM_GEN1_A_UT1_S))
+#define MCPWM_GEN1_A_UT1_V  0x3
+#define MCPWM_GEN1_A_UT1_S  10
+/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN1_A_UT0  0x00000003
+#define MCPWM_GEN1_A_UT0_M  ((MCPWM_GEN1_A_UT0_V)<<(MCPWM_GEN1_A_UT0_S))
+#define MCPWM_GEN1_A_UT0_V  0x3
+#define MCPWM_GEN1_A_UT0_S  8
+/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN1_A_UTEB  0x00000003
+#define MCPWM_GEN1_A_UTEB_M  ((MCPWM_GEN1_A_UTEB_V)<<(MCPWM_GEN1_A_UTEB_S))
+#define MCPWM_GEN1_A_UTEB_V  0x3
+#define MCPWM_GEN1_A_UTEB_S  6
+/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN1_A_UTEA  0x00000003
+#define MCPWM_GEN1_A_UTEA_M  ((MCPWM_GEN1_A_UTEA_V)<<(MCPWM_GEN1_A_UTEA_S))
+#define MCPWM_GEN1_A_UTEA_V  0x3
+#define MCPWM_GEN1_A_UTEA_S  4
+/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN1_A_UTEP  0x00000003
+#define MCPWM_GEN1_A_UTEP_M  ((MCPWM_GEN1_A_UTEP_V)<<(MCPWM_GEN1_A_UTEP_S))
+#define MCPWM_GEN1_A_UTEP_V  0x3
+#define MCPWM_GEN1_A_UTEP_S  2
+/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM1A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN1_A_UTEZ  0x00000003
+#define MCPWM_GEN1_A_UTEZ_M  ((MCPWM_GEN1_A_UTEZ_V)<<(MCPWM_GEN1_A_UTEZ_S))
+#define MCPWM_GEN1_A_UTEZ_V  0x3
+#define MCPWM_GEN1_A_UTEZ_S  0
+
+#define MCPWM_GEN1_B_REG(i)          (REG_MCPWM_BASE(i) + 0x008c)
+/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN1_B_DT1  0x00000003
+#define MCPWM_GEN1_B_DT1_M  ((MCPWM_GEN1_B_DT1_V)<<(MCPWM_GEN1_B_DT1_S))
+#define MCPWM_GEN1_B_DT1_V  0x3
+#define MCPWM_GEN1_B_DT1_S  22
+/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN1_B_DT0  0x00000003
+#define MCPWM_GEN1_B_DT0_M  ((MCPWM_GEN1_B_DT0_V)<<(MCPWM_GEN1_B_DT0_S))
+#define MCPWM_GEN1_B_DT0_V  0x3
+#define MCPWM_GEN1_B_DT0_S  20
+/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN1_B_DTEB  0x00000003
+#define MCPWM_GEN1_B_DTEB_M  ((MCPWM_GEN1_B_DTEB_V)<<(MCPWM_GEN1_B_DTEB_S))
+#define MCPWM_GEN1_B_DTEB_V  0x3
+#define MCPWM_GEN1_B_DTEB_S  18
+/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN1_B_DTEA  0x00000003
+#define MCPWM_GEN1_B_DTEA_M  ((MCPWM_GEN1_B_DTEA_V)<<(MCPWM_GEN1_B_DTEA_S))
+#define MCPWM_GEN1_B_DTEA_V  0x3
+#define MCPWM_GEN1_B_DTEA_S  16
+/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN1_B_DTEP  0x00000003
+#define MCPWM_GEN1_B_DTEP_M  ((MCPWM_GEN1_B_DTEP_V)<<(MCPWM_GEN1_B_DTEP_S))
+#define MCPWM_GEN1_B_DTEP_V  0x3
+#define MCPWM_GEN1_B_DTEP_S  14
+/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN1_B_DTEZ  0x00000003
+#define MCPWM_GEN1_B_DTEZ_M  ((MCPWM_GEN1_B_DTEZ_V)<<(MCPWM_GEN1_B_DTEZ_S))
+#define MCPWM_GEN1_B_DTEZ_V  0x3
+#define MCPWM_GEN1_B_DTEZ_S  12
+/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN1_B_UT1  0x00000003
+#define MCPWM_GEN1_B_UT1_M  ((MCPWM_GEN1_B_UT1_V)<<(MCPWM_GEN1_B_UT1_S))
+#define MCPWM_GEN1_B_UT1_V  0x3
+#define MCPWM_GEN1_B_UT1_S  10
+/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN1_B_UT0  0x00000003
+#define MCPWM_GEN1_B_UT0_M  ((MCPWM_GEN1_B_UT0_V)<<(MCPWM_GEN1_B_UT0_S))
+#define MCPWM_GEN1_B_UT0_V  0x3
+#define MCPWM_GEN1_B_UT0_S  8
+/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN1_B_UTEB  0x00000003
+#define MCPWM_GEN1_B_UTEB_M  ((MCPWM_GEN1_B_UTEB_V)<<(MCPWM_GEN1_B_UTEB_S))
+#define MCPWM_GEN1_B_UTEB_V  0x3
+#define MCPWM_GEN1_B_UTEB_S  6
+/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN1_B_UTEA  0x00000003
+#define MCPWM_GEN1_B_UTEA_M  ((MCPWM_GEN1_B_UTEA_V)<<(MCPWM_GEN1_B_UTEA_S))
+#define MCPWM_GEN1_B_UTEA_V  0x3
+#define MCPWM_GEN1_B_UTEA_S  4
+/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN1_B_UTEP  0x00000003
+#define MCPWM_GEN1_B_UTEP_M  ((MCPWM_GEN1_B_UTEP_V)<<(MCPWM_GEN1_B_UTEP_S))
+#define MCPWM_GEN1_B_UTEP_V  0x3
+#define MCPWM_GEN1_B_UTEP_S  2
+/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM1B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN1_B_UTEZ  0x00000003
+#define MCPWM_GEN1_B_UTEZ_M  ((MCPWM_GEN1_B_UTEZ_V)<<(MCPWM_GEN1_B_UTEZ_S))
+#define MCPWM_GEN1_B_UTEZ_V  0x3
+#define MCPWM_GEN1_B_UTEZ_S  0
+
+#define MCPWM_DT1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0090)
+/* MCPWM_DT1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT1_CLK_SEL  (BIT(17))
+#define MCPWM_DT1_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT1_CLK_SEL_V  0x1
+#define MCPWM_DT1_CLK_SEL_S  17
+/* MCPWM_DT1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT1_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT1_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT1_B_OUTBYPASS_V  0x1
+#define MCPWM_DT1_B_OUTBYPASS_S  16
+/* MCPWM_DT1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT1_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT1_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT1_A_OUTBYPASS_V  0x1
+#define MCPWM_DT1_A_OUTBYPASS_S  15
+/* MCPWM_DT1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT1_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT1_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT1_FED_OUTINVERT_V  0x1
+#define MCPWM_DT1_FED_OUTINVERT_S  14
+/* MCPWM_DT1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT1_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT1_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT1_RED_OUTINVERT_V  0x1
+#define MCPWM_DT1_RED_OUTINVERT_S  13
+/* MCPWM_DT1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT1_FED_INSEL  (BIT(12))
+#define MCPWM_DT1_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT1_FED_INSEL_V  0x1
+#define MCPWM_DT1_FED_INSEL_S  12
+/* MCPWM_DT1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT1_RED_INSEL  (BIT(11))
+#define MCPWM_DT1_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT1_RED_INSEL_V  0x1
+#define MCPWM_DT1_RED_INSEL_S  11
+/* MCPWM_DT1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT1_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT1_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT1_B_OUTSWAP_V  0x1
+#define MCPWM_DT1_B_OUTSWAP_S  10
+/* MCPWM_DT1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT1_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT1_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT1_A_OUTSWAP_V  0x1
+#define MCPWM_DT1_A_OUTSWAP_S  9
+/* MCPWM_DT1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT1_DEB_MODE  (BIT(8))
+#define MCPWM_DT1_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT1_DEB_MODE_V  0x1
+#define MCPWM_DT1_DEB_MODE_S  8
+/* MCPWM_DT1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT1_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT1_RED_UPMETHOD_M  ((MCPWM_DT1_RED_UPMETHOD_V)<<(MCPWM_DT1_RED_UPMETHOD_S))
+#define MCPWM_DT1_RED_UPMETHOD_V  0xF
+#define MCPWM_DT1_RED_UPMETHOD_S  4
+/* MCPWM_DT1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT1_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT1_FED_UPMETHOD_M  ((MCPWM_DT1_FED_UPMETHOD_V)<<(MCPWM_DT1_FED_UPMETHOD_S))
+#define MCPWM_DT1_FED_UPMETHOD_V  0xF
+#define MCPWM_DT1_FED_UPMETHOD_S  0
+
+#define MCPWM_DT1_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0094)
+/* MCPWM_DT1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT1_FED  0x0000FFFF
+#define MCPWM_DT1_FED_M  ((MCPWM_DT1_FED_V)<<(MCPWM_DT1_FED_S))
+#define MCPWM_DT1_FED_V  0xFFFF
+#define MCPWM_DT1_FED_S  0
+
+#define MCPWM_DT1_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x0098)
+/* MCPWM_DT1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT1_RED  0x0000FFFF
+#define MCPWM_DT1_RED_M  ((MCPWM_DT1_RED_V)<<(MCPWM_DT1_RED_S))
+#define MCPWM_DT1_RED_V  0xFFFF
+#define MCPWM_DT1_RED_S  0
+
+#define MCPWM_CARRIER1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x009c)
+/* MCPWM_CARRIER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM1A and PWM1B for this submodule*/
+#define MCPWM_CARRIER1_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER1_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER1_IN_INVERT_V  0x1
+#define MCPWM_CARRIER1_IN_INVERT_S  13
+/* MCPWM_CARRIER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM1A and PWM1B for this submodule*/
+#define MCPWM_CARRIER1_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER1_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER1_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER1_OUT_INVERT_S  12
+/* MCPWM_CARRIER1_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER1_OSHWTH  0x0000000F
+#define MCPWM_CARRIER1_OSHWTH_M  ((MCPWM_CARRIER1_OSHWTH_V)<<(MCPWM_CARRIER1_OSHWTH_S))
+#define MCPWM_CARRIER1_OSHWTH_V  0xF
+#define MCPWM_CARRIER1_OSHWTH_S  8
+/* MCPWM_CARRIER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER1_DUTY / 8*/
+#define MCPWM_CARRIER1_DUTY  0x00000007
+#define MCPWM_CARRIER1_DUTY_M  ((MCPWM_CARRIER1_DUTY_V)<<(MCPWM_CARRIER1_DUTY_S))
+#define MCPWM_CARRIER1_DUTY_V  0x7
+#define MCPWM_CARRIER1_DUTY_S  5
+/* MCPWM_CARRIER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier1 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER1_PRESCALE + 1)*/
+#define MCPWM_CARRIER1_PRESCALE  0x0000000F
+#define MCPWM_CARRIER1_PRESCALE_M  ((MCPWM_CARRIER1_PRESCALE_V)<<(MCPWM_CARRIER1_PRESCALE_S))
+#define MCPWM_CARRIER1_PRESCALE_V  0xF
+#define MCPWM_CARRIER1_PRESCALE_S  1
+/* MCPWM_CARRIER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier1 function is enabled. When cleared  carrier1 is bypassed*/
+#define MCPWM_CARRIER1_EN  (BIT(0))
+#define MCPWM_CARRIER1_EN_M  (BIT(0))
+#define MCPWM_CARRIER1_EN_V  0x1
+#define MCPWM_CARRIER1_EN_S  0
+
+#define MCPWM_FH1_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00a0)
+/* MCPWM_FH1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_OST_U  0x00000003
+#define MCPWM_FH1_B_OST_U_M  ((MCPWM_FH1_B_OST_U_V)<<(MCPWM_FH1_B_OST_U_S))
+#define MCPWM_FH1_B_OST_U_V  0x3
+#define MCPWM_FH1_B_OST_U_S  22
+/* MCPWM_FH1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_OST_D  0x00000003
+#define MCPWM_FH1_B_OST_D_M  ((MCPWM_FH1_B_OST_D_V)<<(MCPWM_FH1_B_OST_D_S))
+#define MCPWM_FH1_B_OST_D_V  0x3
+#define MCPWM_FH1_B_OST_D_S  20
+/* MCPWM_FH1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_CBC_U  0x00000003
+#define MCPWM_FH1_B_CBC_U_M  ((MCPWM_FH1_B_CBC_U_V)<<(MCPWM_FH1_B_CBC_U_S))
+#define MCPWM_FH1_B_CBC_U_V  0x3
+#define MCPWM_FH1_B_CBC_U_S  18
+/* MCPWM_FH1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_B_CBC_D  0x00000003
+#define MCPWM_FH1_B_CBC_D_M  ((MCPWM_FH1_B_CBC_D_V)<<(MCPWM_FH1_B_CBC_D_S))
+#define MCPWM_FH1_B_CBC_D_V  0x3
+#define MCPWM_FH1_B_CBC_D_S  16
+/* MCPWM_FH1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_OST_U  0x00000003
+#define MCPWM_FH1_A_OST_U_M  ((MCPWM_FH1_A_OST_U_V)<<(MCPWM_FH1_A_OST_U_S))
+#define MCPWM_FH1_A_OST_U_V  0x3
+#define MCPWM_FH1_A_OST_U_S  14
+/* MCPWM_FH1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM1A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_OST_D  0x00000003
+#define MCPWM_FH1_A_OST_D_M  ((MCPWM_FH1_A_OST_D_V)<<(MCPWM_FH1_A_OST_D_S))
+#define MCPWM_FH1_A_OST_D_V  0x3
+#define MCPWM_FH1_A_OST_D_S  12
+/* MCPWM_FH1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_CBC_U  0x00000003
+#define MCPWM_FH1_A_CBC_U_M  ((MCPWM_FH1_A_CBC_U_V)<<(MCPWM_FH1_A_CBC_U_S))
+#define MCPWM_FH1_A_CBC_U_V  0x3
+#define MCPWM_FH1_A_CBC_U_S  10
+/* MCPWM_FH1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM1A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH1_A_CBC_D  0x00000003
+#define MCPWM_FH1_A_CBC_D_M  ((MCPWM_FH1_A_CBC_D_V)<<(MCPWM_FH1_A_CBC_D_S))
+#define MCPWM_FH1_A_CBC_D_V  0x3
+#define MCPWM_FH1_A_CBC_D_S  8
+/* MCPWM_FH1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F0_OST  (BIT(7))
+#define MCPWM_FH1_F0_OST_M  (BIT(7))
+#define MCPWM_FH1_F0_OST_V  0x1
+#define MCPWM_FH1_F0_OST_S  7
+/* MCPWM_FH1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F1_OST  (BIT(6))
+#define MCPWM_FH1_F1_OST_M  (BIT(6))
+#define MCPWM_FH1_F1_OST_V  0x1
+#define MCPWM_FH1_F1_OST_S  6
+/* MCPWM_FH1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F2_OST  (BIT(5))
+#define MCPWM_FH1_F2_OST_M  (BIT(5))
+#define MCPWM_FH1_F2_OST_V  0x1
+#define MCPWM_FH1_F2_OST_S  5
+/* MCPWM_FH1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_SW_OST  (BIT(4))
+#define MCPWM_FH1_SW_OST_M  (BIT(4))
+#define MCPWM_FH1_SW_OST_V  0x1
+#define MCPWM_FH1_SW_OST_S  4
+/* MCPWM_FH1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F0_CBC  (BIT(3))
+#define MCPWM_FH1_F0_CBC_M  (BIT(3))
+#define MCPWM_FH1_F0_CBC_V  0x1
+#define MCPWM_FH1_F0_CBC_S  3
+/* MCPWM_FH1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F1_CBC  (BIT(2))
+#define MCPWM_FH1_F1_CBC_M  (BIT(2))
+#define MCPWM_FH1_F1_CBC_V  0x1
+#define MCPWM_FH1_F1_CBC_S  2
+/* MCPWM_FH1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH1_F2_CBC  (BIT(1))
+#define MCPWM_FH1_F2_CBC_M  (BIT(1))
+#define MCPWM_FH1_F2_CBC_V  0x1
+#define MCPWM_FH1_F2_CBC_S  1
+/* MCPWM_FH1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH1_SW_CBC  (BIT(0))
+#define MCPWM_FH1_SW_CBC_M  (BIT(0))
+#define MCPWM_FH1_SW_CBC_V  0x1
+#define MCPWM_FH1_SW_CBC_S  0
+
+#define MCPWM_FH1_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00a4)
+/* MCPWM_FH1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH1_FORCE_OST  (BIT(4))
+#define MCPWM_FH1_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH1_FORCE_OST_V  0x1
+#define MCPWM_FH1_FORCE_OST_S  4
+/* MCPWM_FH1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH1_FORCE_CBC  (BIT(3))
+#define MCPWM_FH1_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH1_FORCE_CBC_V  0x1
+#define MCPWM_FH1_FORCE_CBC_S  3
+/* MCPWM_FH1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH1_CBCPULSE  0x00000003
+#define MCPWM_FH1_CBCPULSE_M  ((MCPWM_FH1_CBCPULSE_V)<<(MCPWM_FH1_CBCPULSE_S))
+#define MCPWM_FH1_CBCPULSE_V  0x3
+#define MCPWM_FH1_CBCPULSE_S  1
+/* MCPWM_FH1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH1_CLR_OST  (BIT(0))
+#define MCPWM_FH1_CLR_OST_M  (BIT(0))
+#define MCPWM_FH1_CLR_OST_V  0x1
+#define MCPWM_FH1_CLR_OST_S  0
+
+#define MCPWM_FH1_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00a8)
+/* MCPWM_FH1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH1_OST_ON  (BIT(1))
+#define MCPWM_FH1_OST_ON_M  (BIT(1))
+#define MCPWM_FH1_OST_ON_V  0x1
+#define MCPWM_FH1_OST_ON_S  1
+/* MCPWM_FH1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH1_CBC_ON  (BIT(0))
+#define MCPWM_FH1_CBC_ON_M  (BIT(0))
+#define MCPWM_FH1_CBC_ON_V  0x1
+#define MCPWM_FH1_CBC_ON_S  0
+
+#define MCPWM_GEN2_STMP_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00ac)
+/* MCPWM_GEN2_B_SHDW_FULL : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
+ B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN2_B_SHDW_FULL  (BIT(9))
+#define MCPWM_GEN2_B_SHDW_FULL_M  (BIT(9))
+#define MCPWM_GEN2_B_SHDW_FULL_V  0x1
+#define MCPWM_GEN2_B_SHDW_FULL_S  9
+/* MCPWM_GEN2_A_SHDW_FULL : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  PWM generator 2 time stamp
+ A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+#define MCPWM_GEN2_A_SHDW_FULL  (BIT(8))
+#define MCPWM_GEN2_A_SHDW_FULL_M  (BIT(8))
+#define MCPWM_GEN2_A_SHDW_FULL_V  0x1
+#define MCPWM_GEN2_A_SHDW_FULL_S  8
+/* MCPWM_GEN2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 2 time stamp B's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN2_B_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_B_UPMETHOD_M  ((MCPWM_GEN2_B_UPMETHOD_V)<<(MCPWM_GEN2_B_UPMETHOD_S))
+#define MCPWM_GEN2_B_UPMETHOD_V  0xF
+#define MCPWM_GEN2_B_UPMETHOD_S  4
+/* MCPWM_GEN2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generator 2 time stamp A's active reg.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_GEN2_A_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_A_UPMETHOD_M  ((MCPWM_GEN2_A_UPMETHOD_V)<<(MCPWM_GEN2_A_UPMETHOD_S))
+#define MCPWM_GEN2_A_UPMETHOD_V  0xF
+#define MCPWM_GEN2_A_UPMETHOD_S  0
+
+#define MCPWM_GEN2_TSTMP_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00b0)
+/* MCPWM_GEN2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 2 time stamp A's shadow reg*/
+#define MCPWM_GEN2_A  0x0000FFFF
+#define MCPWM_GEN2_A_M  ((MCPWM_GEN2_A_V)<<(MCPWM_GEN2_A_S))
+#define MCPWM_GEN2_A_V  0xFFFF
+#define MCPWM_GEN2_A_S  0
+
+#define MCPWM_GEN2_TSTMP_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00b4)
+/* MCPWM_GEN2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: PWM generator 2 time stamp B's shadow reg*/
+#define MCPWM_GEN2_B  0x0000FFFF
+#define MCPWM_GEN2_B_M  ((MCPWM_GEN2_B_V)<<(MCPWM_GEN2_B_S))
+#define MCPWM_GEN2_B_V  0xFFFF
+#define MCPWM_GEN2_B_S  0
+
+#define MCPWM_GEN2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00b8)
+/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate2 event_t1  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN2_T1_SEL  0x00000007
+#define MCPWM_GEN2_T1_SEL_M  ((MCPWM_GEN2_T1_SEL_V)<<(MCPWM_GEN2_T1_SEL_S))
+#define MCPWM_GEN2_T1_SEL_V  0x7
+#define MCPWM_GEN2_T1_SEL_S  7
+/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */
+/*description: Source selection for PWM generate2 event_t0  take effect immediately
+  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+#define MCPWM_GEN2_T0_SEL  0x00000007
+#define MCPWM_GEN2_T0_SEL_M  ((MCPWM_GEN2_T0_SEL_V)<<(MCPWM_GEN2_T0_SEL_S))
+#define MCPWM_GEN2_T0_SEL_V  0x7
+#define MCPWM_GEN2_T0_SEL_S  4
+/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for PWM generate2's active reg of configuration.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: disable update*/
+#define MCPWM_GEN2_CFG_UPMETHOD  0x0000000F
+#define MCPWM_GEN2_CFG_UPMETHOD_M  ((MCPWM_GEN2_CFG_UPMETHOD_V)<<(MCPWM_GEN2_CFG_UPMETHOD_S))
+#define MCPWM_GEN2_CFG_UPMETHOD_V  0xF
+#define MCPWM_GEN2_CFG_UPMETHOD_S  0
+
+#define MCPWM_GEN2_FORCE_REG(i)          (REG_MCPWM_BASE(i) + 0x00bc)
+/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM2B  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN2_B_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN2_B_NCIFORCE_MODE_M  ((MCPWM_GEN2_B_NCIFORCE_MODE_V)<<(MCPWM_GEN2_B_NCIFORCE_MODE_S))
+#define MCPWM_GEN2_B_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN2_B_NCIFORCE_MODE_S  14
+/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM2B  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN2_B_NCIFORCE  (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_M  (BIT(13))
+#define MCPWM_GEN2_B_NCIFORCE_V  0x1
+#define MCPWM_GEN2_B_NCIFORCE_S  13
+/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */
+/*description: Non-continuous immediate software force mode for PWM2A  0: disabled
+  1: low  2: high  3: disabled*/
+#define MCPWM_GEN2_A_NCIFORCE_MODE  0x00000003
+#define MCPWM_GEN2_A_NCIFORCE_MODE_M  ((MCPWM_GEN2_A_NCIFORCE_MODE_V)<<(MCPWM_GEN2_A_NCIFORCE_MODE_S))
+#define MCPWM_GEN2_A_NCIFORCE_MODE_V  0x3
+#define MCPWM_GEN2_A_NCIFORCE_MODE_S  11
+/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Non-continuous immediate software force trigger for PWM2A  a
+ toggle will trigger a force event*/
+#define MCPWM_GEN2_A_NCIFORCE  (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_M  (BIT(10))
+#define MCPWM_GEN2_A_NCIFORCE_V  0x1
+#define MCPWM_GEN2_A_NCIFORCE_S  10
+/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM2B. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN2_B_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_M  ((MCPWM_GEN2_B_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_B_CNTUFORCE_MODE_S))
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN2_B_CNTUFORCE_MODE_S  8
+/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Continuous software force mode for PWM2A. 0: disabled  1: low
+  2: high  3: disabled*/
+#define MCPWM_GEN2_A_CNTUFORCE_MODE  0x00000003
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_M  ((MCPWM_GEN2_A_CNTUFORCE_MODE_V)<<(MCPWM_GEN2_A_CNTUFORCE_MODE_S))
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_V  0x3
+#define MCPWM_GEN2_A_CNTUFORCE_MODE_S  6
+/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: Update method for continuous software force of PWM generator2.
+ 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: disable update. (TEA/B here and below means an event generated when timer value equals A/B register)*/
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD  0x0000003F
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M  ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V)<<(MCPWM_GEN2_CNTUFORCE_UPMETHOD_S))
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V  0x3F
+#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S  0
+
+#define MCPWM_GEN2_A_REG(i)          (REG_MCPWM_BASE(i) + 0x00c0)
+/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN2_A_DT1  0x00000003
+#define MCPWM_GEN2_A_DT1_M  ((MCPWM_GEN2_A_DT1_V)<<(MCPWM_GEN2_A_DT1_S))
+#define MCPWM_GEN2_A_DT1_V  0x3
+#define MCPWM_GEN2_A_DT1_S  22
+/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN2_A_DT0  0x00000003
+#define MCPWM_GEN2_A_DT0_M  ((MCPWM_GEN2_A_DT0_V)<<(MCPWM_GEN2_A_DT0_S))
+#define MCPWM_GEN2_A_DT0_V  0x3
+#define MCPWM_GEN2_A_DT0_S  20
+/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN2_A_DTEB  0x00000003
+#define MCPWM_GEN2_A_DTEB_M  ((MCPWM_GEN2_A_DTEB_V)<<(MCPWM_GEN2_A_DTEB_S))
+#define MCPWM_GEN2_A_DTEB_V  0x3
+#define MCPWM_GEN2_A_DTEB_S  18
+/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN2_A_DTEA  0x00000003
+#define MCPWM_GEN2_A_DTEA_M  ((MCPWM_GEN2_A_DTEA_V)<<(MCPWM_GEN2_A_DTEA_S))
+#define MCPWM_GEN2_A_DTEA_V  0x3
+#define MCPWM_GEN2_A_DTEA_S  16
+/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN2_A_DTEP  0x00000003
+#define MCPWM_GEN2_A_DTEP_M  ((MCPWM_GEN2_A_DTEP_V)<<(MCPWM_GEN2_A_DTEP_S))
+#define MCPWM_GEN2_A_DTEP_V  0x3
+#define MCPWM_GEN2_A_DTEP_S  14
+/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN2_A_DTEZ  0x00000003
+#define MCPWM_GEN2_A_DTEZ_M  ((MCPWM_GEN2_A_DTEZ_V)<<(MCPWM_GEN2_A_DTEZ_S))
+#define MCPWM_GEN2_A_DTEZ_V  0x3
+#define MCPWM_GEN2_A_DTEZ_S  12
+/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN2_A_UT1  0x00000003
+#define MCPWM_GEN2_A_UT1_M  ((MCPWM_GEN2_A_UT1_V)<<(MCPWM_GEN2_A_UT1_S))
+#define MCPWM_GEN2_A_UT1_V  0x3
+#define MCPWM_GEN2_A_UT1_S  10
+/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN2_A_UT0  0x00000003
+#define MCPWM_GEN2_A_UT0_M  ((MCPWM_GEN2_A_UT0_V)<<(MCPWM_GEN2_A_UT0_S))
+#define MCPWM_GEN2_A_UT0_V  0x3
+#define MCPWM_GEN2_A_UT0_S  8
+/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEB when timer increasing*/
+#define MCPWM_GEN2_A_UTEB  0x00000003
+#define MCPWM_GEN2_A_UTEB_M  ((MCPWM_GEN2_A_UTEB_V)<<(MCPWM_GEN2_A_UTEB_S))
+#define MCPWM_GEN2_A_UTEB_V  0x3
+#define MCPWM_GEN2_A_UTEB_S  6
+/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEA when timer increasing*/
+#define MCPWM_GEN2_A_UTEA  0x00000003
+#define MCPWM_GEN2_A_UTEA_M  ((MCPWM_GEN2_A_UTEA_V)<<(MCPWM_GEN2_A_UTEA_S))
+#define MCPWM_GEN2_A_UTEA_V  0x3
+#define MCPWM_GEN2_A_UTEA_S  4
+/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEP when timer increasing*/
+#define MCPWM_GEN2_A_UTEP  0x00000003
+#define MCPWM_GEN2_A_UTEP_M  ((MCPWM_GEN2_A_UTEP_V)<<(MCPWM_GEN2_A_UTEP_S))
+#define MCPWM_GEN2_A_UTEP_V  0x3
+#define MCPWM_GEN2_A_UTEP_S  2
+/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM2A triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN2_A_UTEZ  0x00000003
+#define MCPWM_GEN2_A_UTEZ_M  ((MCPWM_GEN2_A_UTEZ_V)<<(MCPWM_GEN2_A_UTEZ_S))
+#define MCPWM_GEN2_A_UTEZ_V  0x3
+#define MCPWM_GEN2_A_UTEZ_S  0
+
+#define MCPWM_GEN2_B_REG(i)          (REG_MCPWM_BASE(i) + 0x00c4)
+/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t1 when timer decreasing.
+ 0: no change  1: low  2: high  3: toggle*/
+#define MCPWM_GEN2_B_DT1  0x00000003
+#define MCPWM_GEN2_B_DT1_M  ((MCPWM_GEN2_B_DT1_V)<<(MCPWM_GEN2_B_DT1_S))
+#define MCPWM_GEN2_B_DT1_V  0x3
+#define MCPWM_GEN2_B_DT1_S  22
+/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t0 when timer decreasing*/
+#define MCPWM_GEN2_B_DT0  0x00000003
+#define MCPWM_GEN2_B_DT0_M  ((MCPWM_GEN2_B_DT0_V)<<(MCPWM_GEN2_B_DT0_S))
+#define MCPWM_GEN2_B_DT0_V  0x3
+#define MCPWM_GEN2_B_DT0_S  20
+/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEB when timer decreasing*/
+#define MCPWM_GEN2_B_DTEB  0x00000003
+#define MCPWM_GEN2_B_DTEB_M  ((MCPWM_GEN2_B_DTEB_V)<<(MCPWM_GEN2_B_DTEB_S))
+#define MCPWM_GEN2_B_DTEB_V  0x3
+#define MCPWM_GEN2_B_DTEB_S  18
+/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEA when timer decreasing*/
+#define MCPWM_GEN2_B_DTEA  0x00000003
+#define MCPWM_GEN2_B_DTEA_M  ((MCPWM_GEN2_B_DTEA_V)<<(MCPWM_GEN2_B_DTEA_S))
+#define MCPWM_GEN2_B_DTEA_V  0x3
+#define MCPWM_GEN2_B_DTEA_S  16
+/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEP when timer decreasing*/
+#define MCPWM_GEN2_B_DTEP  0x00000003
+#define MCPWM_GEN2_B_DTEP_M  ((MCPWM_GEN2_B_DTEP_V)<<(MCPWM_GEN2_B_DTEP_S))
+#define MCPWM_GEN2_B_DTEP_V  0x3
+#define MCPWM_GEN2_B_DTEP_S  14
+/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEZ when timer decreasing*/
+#define MCPWM_GEN2_B_DTEZ  0x00000003
+#define MCPWM_GEN2_B_DTEZ_M  ((MCPWM_GEN2_B_DTEZ_V)<<(MCPWM_GEN2_B_DTEZ_S))
+#define MCPWM_GEN2_B_DTEZ_V  0x3
+#define MCPWM_GEN2_B_DTEZ_S  12
+/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t1 when timer increasing*/
+#define MCPWM_GEN2_B_UT1  0x00000003
+#define MCPWM_GEN2_B_UT1_M  ((MCPWM_GEN2_B_UT1_V)<<(MCPWM_GEN2_B_UT1_S))
+#define MCPWM_GEN2_B_UT1_V  0x3
+#define MCPWM_GEN2_B_UT1_S  10
+/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event_t0 when timer increasing*/
+#define MCPWM_GEN2_B_UT0  0x00000003
+#define MCPWM_GEN2_B_UT0_M  ((MCPWM_GEN2_B_UT0_V)<<(MCPWM_GEN2_B_UT0_S))
+#define MCPWM_GEN2_B_UT0_V  0x3
+#define MCPWM_GEN2_B_UT0_S  8
+/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEB when timer increasing*/
+#define MCPWM_GEN2_B_UTEB  0x00000003
+#define MCPWM_GEN2_B_UTEB_M  ((MCPWM_GEN2_B_UTEB_V)<<(MCPWM_GEN2_B_UTEB_S))
+#define MCPWM_GEN2_B_UTEB_V  0x3
+#define MCPWM_GEN2_B_UTEB_S  6
+/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEA when timer increasing*/
+#define MCPWM_GEN2_B_UTEA  0x00000003
+#define MCPWM_GEN2_B_UTEA_M  ((MCPWM_GEN2_B_UTEA_V)<<(MCPWM_GEN2_B_UTEA_S))
+#define MCPWM_GEN2_B_UTEA_V  0x3
+#define MCPWM_GEN2_B_UTEA_S  4
+/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEP when timer increasing*/
+#define MCPWM_GEN2_B_UTEP  0x00000003
+#define MCPWM_GEN2_B_UTEP_M  ((MCPWM_GEN2_B_UTEP_V)<<(MCPWM_GEN2_B_UTEP_S))
+#define MCPWM_GEN2_B_UTEP_V  0x3
+#define MCPWM_GEN2_B_UTEP_S  2
+/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: Action on PWM2B triggered by event TEZ when timer increasing*/
+#define MCPWM_GEN2_B_UTEZ  0x00000003
+#define MCPWM_GEN2_B_UTEZ_M  ((MCPWM_GEN2_B_UTEZ_V)<<(MCPWM_GEN2_B_UTEZ_S))
+#define MCPWM_GEN2_B_UTEZ_V  0x3
+#define MCPWM_GEN2_B_UTEZ_S  0
+
+#define MCPWM_DT2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00c8)
+/* MCPWM_DT2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Dead time generator 1 clock selection. 0: PWM_clk  1: PT_clk*/
+#define MCPWM_DT2_CLK_SEL  (BIT(17))
+#define MCPWM_DT2_CLK_SEL_M  (BIT(17))
+#define MCPWM_DT2_CLK_SEL_V  0x1
+#define MCPWM_DT2_CLK_SEL_S  17
+/* MCPWM_DT2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: S0 in documentation*/
+#define MCPWM_DT2_B_OUTBYPASS  (BIT(16))
+#define MCPWM_DT2_B_OUTBYPASS_M  (BIT(16))
+#define MCPWM_DT2_B_OUTBYPASS_V  0x1
+#define MCPWM_DT2_B_OUTBYPASS_S  16
+/* MCPWM_DT2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: S1 in documentation*/
+#define MCPWM_DT2_A_OUTBYPASS  (BIT(15))
+#define MCPWM_DT2_A_OUTBYPASS_M  (BIT(15))
+#define MCPWM_DT2_A_OUTBYPASS_V  0x1
+#define MCPWM_DT2_A_OUTBYPASS_S  15
+/* MCPWM_DT2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: S3 in documentation*/
+#define MCPWM_DT2_FED_OUTINVERT  (BIT(14))
+#define MCPWM_DT2_FED_OUTINVERT_M  (BIT(14))
+#define MCPWM_DT2_FED_OUTINVERT_V  0x1
+#define MCPWM_DT2_FED_OUTINVERT_S  14
+/* MCPWM_DT2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: S2 in documentation*/
+#define MCPWM_DT2_RED_OUTINVERT  (BIT(13))
+#define MCPWM_DT2_RED_OUTINVERT_M  (BIT(13))
+#define MCPWM_DT2_RED_OUTINVERT_V  0x1
+#define MCPWM_DT2_RED_OUTINVERT_S  13
+/* MCPWM_DT2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: S5 in documentation*/
+#define MCPWM_DT2_FED_INSEL  (BIT(12))
+#define MCPWM_DT2_FED_INSEL_M  (BIT(12))
+#define MCPWM_DT2_FED_INSEL_V  0x1
+#define MCPWM_DT2_FED_INSEL_S  12
+/* MCPWM_DT2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: S4 in documentation*/
+#define MCPWM_DT2_RED_INSEL  (BIT(11))
+#define MCPWM_DT2_RED_INSEL_M  (BIT(11))
+#define MCPWM_DT2_RED_INSEL_V  0x1
+#define MCPWM_DT2_RED_INSEL_S  11
+/* MCPWM_DT2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: S7 in documentation*/
+#define MCPWM_DT2_B_OUTSWAP  (BIT(10))
+#define MCPWM_DT2_B_OUTSWAP_M  (BIT(10))
+#define MCPWM_DT2_B_OUTSWAP_V  0x1
+#define MCPWM_DT2_B_OUTSWAP_S  10
+/* MCPWM_DT2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: S6 in documentation*/
+#define MCPWM_DT2_A_OUTSWAP  (BIT(9))
+#define MCPWM_DT2_A_OUTSWAP_M  (BIT(9))
+#define MCPWM_DT2_A_OUTSWAP_V  0x1
+#define MCPWM_DT2_A_OUTSWAP_S  9
+/* MCPWM_DT2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: S8 in documentation  dual-edge B mode  0: FED/RED take effect
+ on different path separately  1: FED/RED take effect on B path  A out is in bypass or normal operation mode*/
+#define MCPWM_DT2_DEB_MODE  (BIT(8))
+#define MCPWM_DT2_DEB_MODE_M  (BIT(8))
+#define MCPWM_DT2_DEB_MODE_V  0x1
+#define MCPWM_DT2_DEB_MODE_S  8
+/* MCPWM_DT2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */
+/*description: Update method for RED (rising edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT2_RED_UPMETHOD  0x0000000F
+#define MCPWM_DT2_RED_UPMETHOD_M  ((MCPWM_DT2_RED_UPMETHOD_V)<<(MCPWM_DT2_RED_UPMETHOD_S))
+#define MCPWM_DT2_RED_UPMETHOD_V  0xF
+#define MCPWM_DT2_RED_UPMETHOD_S  4
+/* MCPWM_DT2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */
+/*description: Update method for FED (falling edge delay) active reg. 0: immediate
+  bit0: TEZ  bit1: TEP  bit2: sync  bit3: disable update*/
+#define MCPWM_DT2_FED_UPMETHOD  0x0000000F
+#define MCPWM_DT2_FED_UPMETHOD_M  ((MCPWM_DT2_FED_UPMETHOD_V)<<(MCPWM_DT2_FED_UPMETHOD_S))
+#define MCPWM_DT2_FED_UPMETHOD_V  0xF
+#define MCPWM_DT2_FED_UPMETHOD_S  0
+
+#define MCPWM_DT2_FED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00cc)
+/* MCPWM_DT2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for FED*/
+#define MCPWM_DT2_FED  0x0000FFFF
+#define MCPWM_DT2_FED_M  ((MCPWM_DT2_FED_V)<<(MCPWM_DT2_FED_S))
+#define MCPWM_DT2_FED_V  0xFFFF
+#define MCPWM_DT2_FED_S  0
+
+#define MCPWM_DT2_RED_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d0)
+/* MCPWM_DT2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */
+/*description: Shadow reg for RED*/
+#define MCPWM_DT2_RED  0x0000FFFF
+#define MCPWM_DT2_RED_M  ((MCPWM_DT2_RED_V)<<(MCPWM_DT2_RED_S))
+#define MCPWM_DT2_RED_V  0xFFFF
+#define MCPWM_DT2_RED_S  0
+
+#define MCPWM_CARRIER2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00d4)
+/* MCPWM_CARRIER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: When set  invert the input of PWM2A and PWM2B for this submodule*/
+#define MCPWM_CARRIER2_IN_INVERT  (BIT(13))
+#define MCPWM_CARRIER2_IN_INVERT_M  (BIT(13))
+#define MCPWM_CARRIER2_IN_INVERT_V  0x1
+#define MCPWM_CARRIER2_IN_INVERT_S  13
+/* MCPWM_CARRIER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: When set  invert the output of PWM2A and PWM2B for this submodule*/
+#define MCPWM_CARRIER2_OUT_INVERT  (BIT(12))
+#define MCPWM_CARRIER2_OUT_INVERT_M  (BIT(12))
+#define MCPWM_CARRIER2_OUT_INVERT_V  0x1
+#define MCPWM_CARRIER2_OUT_INVERT_S  12
+/* MCPWM_CARRIER2_OSHWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */
+/*description: Width of the fist pulse in number of periods of the carrier*/
+#define MCPWM_CARRIER2_OSHWTH  0x0000000F
+#define MCPWM_CARRIER2_OSHWTH_M  ((MCPWM_CARRIER2_OSHWTH_V)<<(MCPWM_CARRIER2_OSHWTH_S))
+#define MCPWM_CARRIER2_OSHWTH_V  0xF
+#define MCPWM_CARRIER2_OSHWTH_S  8
+/* MCPWM_CARRIER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */
+/*description: Carrier duty selection. Duty = PWM_CARRIER2_DUTY / 8*/
+#define MCPWM_CARRIER2_DUTY  0x00000007
+#define MCPWM_CARRIER2_DUTY_M  ((MCPWM_CARRIER2_DUTY_V)<<(MCPWM_CARRIER2_DUTY_S))
+#define MCPWM_CARRIER2_DUTY_V  0x7
+#define MCPWM_CARRIER2_DUTY_S  5
+/* MCPWM_CARRIER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: PWM carrier2 clock (PC_clk) prescale value. Period of PC_clk
+ = period of PWM_clk * (PWM_CARRIER2_PRESCALE + 1)*/
+#define MCPWM_CARRIER2_PRESCALE  0x0000000F
+#define MCPWM_CARRIER2_PRESCALE_M  ((MCPWM_CARRIER2_PRESCALE_V)<<(MCPWM_CARRIER2_PRESCALE_S))
+#define MCPWM_CARRIER2_PRESCALE_V  0xF
+#define MCPWM_CARRIER2_PRESCALE_S  1
+/* MCPWM_CARRIER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  carrier2 function is enabled. When cleared  carrier2 is bypassed*/
+#define MCPWM_CARRIER2_EN  (BIT(0))
+#define MCPWM_CARRIER2_EN_M  (BIT(0))
+#define MCPWM_CARRIER2_EN_V  0x1
+#define MCPWM_CARRIER2_EN_S  0
+
+#define MCPWM_FH2_CFG0_REG(i)          (REG_MCPWM_BASE(i) + 0x00d8)
+/* MCPWM_FH2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2B when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_OST_U  0x00000003
+#define MCPWM_FH2_B_OST_U_M  ((MCPWM_FH2_B_OST_U_V)<<(MCPWM_FH2_B_OST_U_S))
+#define MCPWM_FH2_B_OST_U_V  0x3
+#define MCPWM_FH2_B_OST_U_S  22
+/* MCPWM_FH2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2B when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_OST_D  0x00000003
+#define MCPWM_FH2_B_OST_D_M  ((MCPWM_FH2_B_OST_D_V)<<(MCPWM_FH2_B_OST_D_S))
+#define MCPWM_FH2_B_OST_D_V  0x3
+#define MCPWM_FH2_B_OST_D_S  20
+/* MCPWM_FH2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_CBC_U  0x00000003
+#define MCPWM_FH2_B_CBC_U_M  ((MCPWM_FH2_B_CBC_U_V)<<(MCPWM_FH2_B_CBC_U_S))
+#define MCPWM_FH2_B_CBC_U_V  0x3
+#define MCPWM_FH2_B_CBC_U_S  18
+/* MCPWM_FH2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2B when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_B_CBC_D  0x00000003
+#define MCPWM_FH2_B_CBC_D_M  ((MCPWM_FH2_B_CBC_D_V)<<(MCPWM_FH2_B_CBC_D_S))
+#define MCPWM_FH2_B_CBC_D_V  0x3
+#define MCPWM_FH2_B_CBC_D_S  16
+/* MCPWM_FH2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2A when fault event occurs and timer
+ is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_OST_U  0x00000003
+#define MCPWM_FH2_A_OST_U_M  ((MCPWM_FH2_A_OST_U_V)<<(MCPWM_FH2_A_OST_U_S))
+#define MCPWM_FH2_A_OST_U_V  0x3
+#define MCPWM_FH2_A_OST_U_S  14
+/* MCPWM_FH2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */
+/*description: One-shot mode action on PWM2A when fault event occurs and timer
+ is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_OST_D  0x00000003
+#define MCPWM_FH2_A_OST_D_M  ((MCPWM_FH2_A_OST_D_V)<<(MCPWM_FH2_A_OST_D_S))
+#define MCPWM_FH2_A_OST_D_V  0x3
+#define MCPWM_FH2_A_OST_D_S  12
+/* MCPWM_FH2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
+ timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_CBC_U  0x00000003
+#define MCPWM_FH2_A_CBC_U_M  ((MCPWM_FH2_A_CBC_U_V)<<(MCPWM_FH2_A_CBC_U_S))
+#define MCPWM_FH2_A_CBC_U_V  0x3
+#define MCPWM_FH2_A_CBC_U_S  10
+/* MCPWM_FH2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */
+/*description: Cycle-by-cycle mode action on PWM2A when fault event occurs and
+ timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+#define MCPWM_FH2_A_CBC_D  0x00000003
+#define MCPWM_FH2_A_CBC_D_M  ((MCPWM_FH2_A_CBC_D_V)<<(MCPWM_FH2_A_CBC_D_S))
+#define MCPWM_FH2_A_CBC_D_V  0x3
+#define MCPWM_FH2_A_CBC_D_S  8
+/* MCPWM_FH2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: event_f0 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F0_OST  (BIT(7))
+#define MCPWM_FH2_F0_OST_M  (BIT(7))
+#define MCPWM_FH2_F0_OST_V  0x1
+#define MCPWM_FH2_F0_OST_S  7
+/* MCPWM_FH2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: event_f1 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F1_OST  (BIT(6))
+#define MCPWM_FH2_F1_OST_M  (BIT(6))
+#define MCPWM_FH2_F1_OST_V  0x1
+#define MCPWM_FH2_F1_OST_S  6
+/* MCPWM_FH2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: event_f2 will trigger one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F2_OST  (BIT(5))
+#define MCPWM_FH2_F2_OST_M  (BIT(5))
+#define MCPWM_FH2_F2_OST_V  0x1
+#define MCPWM_FH2_F2_OST_S  5
+/* MCPWM_FH2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Enable register for software force one-shot mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_SW_OST  (BIT(4))
+#define MCPWM_FH2_SW_OST_M  (BIT(4))
+#define MCPWM_FH2_SW_OST_V  0x1
+#define MCPWM_FH2_SW_OST_S  4
+/* MCPWM_FH2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: event_f0 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F0_CBC  (BIT(3))
+#define MCPWM_FH2_F0_CBC_M  (BIT(3))
+#define MCPWM_FH2_F0_CBC_V  0x1
+#define MCPWM_FH2_F0_CBC_S  3
+/* MCPWM_FH2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: event_f1 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F1_CBC  (BIT(2))
+#define MCPWM_FH2_F1_CBC_M  (BIT(2))
+#define MCPWM_FH2_F1_CBC_V  0x1
+#define MCPWM_FH2_F1_CBC_S  2
+/* MCPWM_FH2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: event_f2 will trigger cycle-by-cycle mode action. 0: disable  1: enable*/
+#define MCPWM_FH2_F2_CBC  (BIT(1))
+#define MCPWM_FH2_F2_CBC_M  (BIT(1))
+#define MCPWM_FH2_F2_CBC_V  0x1
+#define MCPWM_FH2_F2_CBC_S  1
+/* MCPWM_FH2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Enable register for software force cycle-by-cycle mode action.
+ 0: disable  1: enable*/
+#define MCPWM_FH2_SW_CBC  (BIT(0))
+#define MCPWM_FH2_SW_CBC_M  (BIT(0))
+#define MCPWM_FH2_SW_CBC_V  0x1
+#define MCPWM_FH2_SW_CBC_S  0
+
+#define MCPWM_FH2_CFG1_REG(i)          (REG_MCPWM_BASE(i) + 0x00dc)
+/* MCPWM_FH2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) triggers a
+ one-shot mode action*/
+#define MCPWM_FH2_FORCE_OST  (BIT(4))
+#define MCPWM_FH2_FORCE_OST_M  (BIT(4))
+#define MCPWM_FH2_FORCE_OST_V  0x1
+#define MCPWM_FH2_FORCE_OST_S  4
+/* MCPWM_FH2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle triggers a cycle-by-cycle mode action*/
+#define MCPWM_FH2_FORCE_CBC  (BIT(3))
+#define MCPWM_FH2_FORCE_CBC_M  (BIT(3))
+#define MCPWM_FH2_FORCE_CBC_V  0x1
+#define MCPWM_FH2_FORCE_CBC_S  3
+/* MCPWM_FH2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: The cycle-by-cycle mode action refresh moment selection. Bit0: TEZ  bit1:TEP*/
+#define MCPWM_FH2_CBCPULSE  0x00000003
+#define MCPWM_FH2_CBCPULSE_M  ((MCPWM_FH2_CBCPULSE_V)<<(MCPWM_FH2_CBCPULSE_S))
+#define MCPWM_FH2_CBCPULSE_V  0x3
+#define MCPWM_FH2_CBCPULSE_S  1
+/* MCPWM_FH2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: A toggle will clear on going one-shot mode action*/
+#define MCPWM_FH2_CLR_OST  (BIT(0))
+#define MCPWM_FH2_CLR_OST_M  (BIT(0))
+#define MCPWM_FH2_CLR_OST_V  0x1
+#define MCPWM_FH2_CLR_OST_S  0
+
+#define MCPWM_FH2_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x00e0)
+/* MCPWM_FH2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an one-shot mode action is on going*/
+#define MCPWM_FH2_OST_ON  (BIT(1))
+#define MCPWM_FH2_OST_ON_M  (BIT(1))
+#define MCPWM_FH2_OST_ON_V  0x1
+#define MCPWM_FH2_OST_ON_S  1
+/* MCPWM_FH2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  an cycle-by-cycle mode action is on going*/
+#define MCPWM_FH2_CBC_ON  (BIT(0))
+#define MCPWM_FH2_CBC_ON_M  (BIT(0))
+#define MCPWM_FH2_CBC_ON_V  0x1
+#define MCPWM_FH2_CBC_ON_S  0
+
+#define MCPWM_FAULT_DETECT_REG(i)          (REG_MCPWM_BASE(i) + 0x00e4)
+/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f2 is on going*/
+#define MCPWM_EVENT_F2  (BIT(8))
+#define MCPWM_EVENT_F2_M  (BIT(8))
+#define MCPWM_EVENT_F2_V  0x1
+#define MCPWM_EVENT_F2_S  8
+/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f1 is on going*/
+#define MCPWM_EVENT_F1  (BIT(7))
+#define MCPWM_EVENT_F1_M  (BIT(7))
+#define MCPWM_EVENT_F1_V  0x1
+#define MCPWM_EVENT_F1_S  7
+/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */
+/*description: Set and reset by hardware. If set  event_f0 is on going*/
+#define MCPWM_EVENT_F0  (BIT(6))
+#define MCPWM_EVENT_F0_M  (BIT(6))
+#define MCPWM_EVENT_F0_V  0x1
+#define MCPWM_EVENT_F0_S  6
+/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: Set event_f2 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F2_POLE  (BIT(5))
+#define MCPWM_F2_POLE_M  (BIT(5))
+#define MCPWM_F2_POLE_V  0x1
+#define MCPWM_F2_POLE_S  5
+/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: Set event_f1 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F1_POLE  (BIT(4))
+#define MCPWM_F1_POLE_M  (BIT(4))
+#define MCPWM_F1_POLE_V  0x1
+#define MCPWM_F1_POLE_S  4
+/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: Set event_f0 trigger polarity on FAULT2 source from GPIO matrix.
+ 0: level low  1: level high*/
+#define MCPWM_F0_POLE  (BIT(3))
+#define MCPWM_F0_POLE_M  (BIT(3))
+#define MCPWM_F0_POLE_V  0x1
+#define MCPWM_F0_POLE_S  3
+/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f2*/
+#define MCPWM_F2_EN  (BIT(2))
+#define MCPWM_F2_EN_M  (BIT(2))
+#define MCPWM_F2_EN_V  0x1
+#define MCPWM_F2_EN_S  2
+/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f1*/
+#define MCPWM_F1_EN  (BIT(1))
+#define MCPWM_F1_EN_M  (BIT(1))
+#define MCPWM_F1_EN_V  0x1
+#define MCPWM_F1_EN_S  1
+/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Set to enable generation of event_f0*/
+#define MCPWM_F0_EN  (BIT(0))
+#define MCPWM_F0_EN_M  (BIT(0))
+#define MCPWM_F0_EN_V  0x1
+#define MCPWM_F0_EN_S  0
+
+#define MCPWM_CAP_TIMER_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00e8)
+/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */
+/*description: Set this bit to force a capture timer sync  capture timer is
+ loaded with value in phase register.*/
+#define MCPWM_CAP_SYNC_SW  (BIT(5))
+#define MCPWM_CAP_SYNC_SW_M  (BIT(5))
+#define MCPWM_CAP_SYNC_SW_V  0x1
+#define MCPWM_CAP_SYNC_SW_S  5
+/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */
+/*description: Capture module sync input selection. 0: none  1: timer0 synco
+  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
+#define MCPWM_CAP_SYNCI_SEL  0x00000007
+#define MCPWM_CAP_SYNCI_SEL_M  ((MCPWM_CAP_SYNCI_SEL_V)<<(MCPWM_CAP_SYNCI_SEL_S))
+#define MCPWM_CAP_SYNCI_SEL_V  0x7
+#define MCPWM_CAP_SYNCI_SEL_S  2
+/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: When set  capture timer sync is enabled.*/
+#define MCPWM_CAP_SYNCI_EN  (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_M  (BIT(1))
+#define MCPWM_CAP_SYNCI_EN_V  0x1
+#define MCPWM_CAP_SYNCI_EN_S  1
+/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture timer incrementing under APB_clk is enabled.*/
+#define MCPWM_CAP_TIMER_EN  (BIT(0))
+#define MCPWM_CAP_TIMER_EN_M  (BIT(0))
+#define MCPWM_CAP_TIMER_EN_V  0x1
+#define MCPWM_CAP_TIMER_EN_S  0
+
+#define MCPWM_CAP_TIMER_PHASE_REG(i)          (REG_MCPWM_BASE(i) + 0x00ec)
+/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Phase value for capture timer sync operation.*/
+#define MCPWM_CAP_PHASE  0xFFFFFFFF
+#define MCPWM_CAP_PHASE_M  ((MCPWM_CAP_PHASE_V)<<(MCPWM_CAP_PHASE_S))
+#define MCPWM_CAP_PHASE_V  0xFFFFFFFF
+#define MCPWM_CAP_PHASE_S  0
+
+#define MCPWM_CAP_CH0_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f0)
+/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 0*/
+#define MCPWM_CAP0_SW  (BIT(12))
+#define MCPWM_CAP0_SW_M  (BIT(12))
+#define MCPWM_CAP0_SW_V  0x1
+#define MCPWM_CAP0_SW_S  12
+/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP0 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP0_IN_INVERT  (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP0_IN_INVERT_V  0x1
+#define MCPWM_CAP0_IN_INVERT_S  11
+/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP0. Prescale value =
+ PWM_CAP0_PRESCALE + 1*/
+#define MCPWM_CAP0_PRESCALE  0x000000FF
+#define MCPWM_CAP0_PRESCALE_M  ((MCPWM_CAP0_PRESCALE_V)<<(MCPWM_CAP0_PRESCALE_S))
+#define MCPWM_CAP0_PRESCALE_V  0xFF
+#define MCPWM_CAP0_PRESCALE_S  3
+/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 0 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP0_MODE  0x00000003
+#define MCPWM_CAP0_MODE_M  ((MCPWM_CAP0_MODE_V)<<(MCPWM_CAP0_MODE_S))
+#define MCPWM_CAP0_MODE_V  0x3
+#define MCPWM_CAP0_MODE_S  1
+/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 0 is enabled*/
+#define MCPWM_CAP0_EN  (BIT(0))
+#define MCPWM_CAP0_EN_M  (BIT(0))
+#define MCPWM_CAP0_EN_V  0x1
+#define MCPWM_CAP0_EN_S  0
+
+#define MCPWM_CAP_CH1_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f4)
+/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 1*/
+#define MCPWM_CAP1_SW  (BIT(12))
+#define MCPWM_CAP1_SW_M  (BIT(12))
+#define MCPWM_CAP1_SW_V  0x1
+#define MCPWM_CAP1_SW_S  12
+/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP1 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP1_IN_INVERT  (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP1_IN_INVERT_V  0x1
+#define MCPWM_CAP1_IN_INVERT_S  11
+/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP1. Prescale value =
+ PWM_CAP1_PRESCALE + 1*/
+#define MCPWM_CAP1_PRESCALE  0x000000FF
+#define MCPWM_CAP1_PRESCALE_M  ((MCPWM_CAP1_PRESCALE_V)<<(MCPWM_CAP1_PRESCALE_S))
+#define MCPWM_CAP1_PRESCALE_V  0xFF
+#define MCPWM_CAP1_PRESCALE_S  3
+/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 1 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP1_MODE  0x00000003
+#define MCPWM_CAP1_MODE_M  ((MCPWM_CAP1_MODE_V)<<(MCPWM_CAP1_MODE_S))
+#define MCPWM_CAP1_MODE_V  0x3
+#define MCPWM_CAP1_MODE_S  1
+/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 1 is enabled*/
+#define MCPWM_CAP1_EN  (BIT(0))
+#define MCPWM_CAP1_EN_M  (BIT(0))
+#define MCPWM_CAP1_EN_V  0x1
+#define MCPWM_CAP1_EN_S  0
+
+#define MCPWM_CAP_CH2_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x00f8)
+/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Write 1 will trigger a software forced capture on channel 2*/
+#define MCPWM_CAP2_SW  (BIT(12))
+#define MCPWM_CAP2_SW_M  (BIT(12))
+#define MCPWM_CAP2_SW_V  0x1
+#define MCPWM_CAP2_SW_S  12
+/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: When set  CAP2 form GPIO matrix is inverted before prescale*/
+#define MCPWM_CAP2_IN_INVERT  (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_M  (BIT(11))
+#define MCPWM_CAP2_IN_INVERT_V  0x1
+#define MCPWM_CAP2_IN_INVERT_S  11
+/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: Value of prescale on possitive edge of CAP2. Prescale value =
+ PWM_CAP2_PRESCALE + 1*/
+#define MCPWM_CAP2_PRESCALE  0x000000FF
+#define MCPWM_CAP2_PRESCALE_M  ((MCPWM_CAP2_PRESCALE_V)<<(MCPWM_CAP2_PRESCALE_S))
+#define MCPWM_CAP2_PRESCALE_V  0xFF
+#define MCPWM_CAP2_PRESCALE_S  3
+/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */
+/*description: Edge of capture on channel 2 after prescale.  bit0: negedge cap
+ en  bit1: posedge cap en*/
+#define MCPWM_CAP2_MODE  0x00000003
+#define MCPWM_CAP2_MODE_M  ((MCPWM_CAP2_MODE_V)<<(MCPWM_CAP2_MODE_S))
+#define MCPWM_CAP2_MODE_V  0x3
+#define MCPWM_CAP2_MODE_S  1
+/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: When set  capture on channel 2 is enabled*/
+#define MCPWM_CAP2_EN  (BIT(0))
+#define MCPWM_CAP2_EN_M  (BIT(0))
+#define MCPWM_CAP2_EN_V  0x1
+#define MCPWM_CAP2_EN_S  0
+
+#define MCPWM_CAP_CH0_REG(i)          (REG_MCPWM_BASE(i) + 0x00fc)
+/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 0*/
+#define MCPWM_CAP0_VALUE  0xFFFFFFFF
+#define MCPWM_CAP0_VALUE_M  ((MCPWM_CAP0_VALUE_V)<<(MCPWM_CAP0_VALUE_S))
+#define MCPWM_CAP0_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP0_VALUE_S  0
+
+#define MCPWM_CAP_CH1_REG(i)          (REG_MCPWM_BASE(i) + 0x0100)
+/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 1*/
+#define MCPWM_CAP1_VALUE  0xFFFFFFFF
+#define MCPWM_CAP1_VALUE_M  ((MCPWM_CAP1_VALUE_V)<<(MCPWM_CAP1_VALUE_S))
+#define MCPWM_CAP1_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP1_VALUE_S  0
+
+#define MCPWM_CAP_CH2_REG(i)          (REG_MCPWM_BASE(i) + 0x0104)
+/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: Value of last capture on channel 2*/
+#define MCPWM_CAP2_VALUE  0xFFFFFFFF
+#define MCPWM_CAP2_VALUE_M  ((MCPWM_CAP2_VALUE_V)<<(MCPWM_CAP2_VALUE_S))
+#define MCPWM_CAP2_VALUE_V  0xFFFFFFFF
+#define MCPWM_CAP2_VALUE_S  0
+
+#define MCPWM_CAP_STATUS_REG(i)          (REG_MCPWM_BASE(i) + 0x0108)
+/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
+#define MCPWM_CAP2_EDGE  (BIT(2))
+#define MCPWM_CAP2_EDGE_M  (BIT(2))
+#define MCPWM_CAP2_EDGE_V  0x1
+#define MCPWM_CAP2_EDGE_S  2
+/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
+#define MCPWM_CAP1_EDGE  (BIT(1))
+#define MCPWM_CAP1_EDGE_M  (BIT(1))
+#define MCPWM_CAP1_EDGE_V  0x1
+#define MCPWM_CAP1_EDGE_S  1
+/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
+#define MCPWM_CAP0_EDGE  (BIT(0))
+#define MCPWM_CAP0_EDGE_M  (BIT(0))
+#define MCPWM_CAP0_EDGE_V  0x1
+#define MCPWM_CAP0_EDGE_S  0
+
+#define MCPWM_UPDATE_CFG_REG(i)          (REG_MCPWM_BASE(i) + 0x010c)
+/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 2*/
+#define MCPWM_OP2_FORCE_UP  (BIT(7))
+#define MCPWM_OP2_FORCE_UP_M  (BIT(7))
+#define MCPWM_OP2_FORCE_UP_V  0x1
+#define MCPWM_OP2_FORCE_UP_S  7
+/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 2 are enabled*/
+#define MCPWM_OP2_UP_EN  (BIT(6))
+#define MCPWM_OP2_UP_EN_M  (BIT(6))
+#define MCPWM_OP2_UP_EN_V  0x1
+#define MCPWM_OP2_UP_EN_S  6
+/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 1*/
+#define MCPWM_OP1_FORCE_UP  (BIT(5))
+#define MCPWM_OP1_FORCE_UP_M  (BIT(5))
+#define MCPWM_OP1_FORCE_UP_V  0x1
+#define MCPWM_OP1_FORCE_UP_S  5
+/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 1 are enabled*/
+#define MCPWM_OP1_UP_EN  (BIT(4))
+#define MCPWM_OP1_UP_EN_M  (BIT(4))
+#define MCPWM_OP1_UP_EN_V  0x1
+#define MCPWM_OP1_UP_EN_S  4
+/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of active registers in PWM operator 0*/
+#define MCPWM_OP0_FORCE_UP  (BIT(3))
+#define MCPWM_OP0_FORCE_UP_M  (BIT(3))
+#define MCPWM_OP0_FORCE_UP_V  0x1
+#define MCPWM_OP0_FORCE_UP_S  3
+/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */
+/*description: When set and PWM_GLOBAL_UP_EN is set  update of active registers
+ in PWM operator 0 are enabled*/
+#define MCPWM_OP0_UP_EN  (BIT(2))
+#define MCPWM_OP0_UP_EN_M  (BIT(2))
+#define MCPWM_OP0_UP_EN_V  0x1
+#define MCPWM_OP0_UP_EN_S  2
+/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: A toggle (software negation of value of this bit) will trigger
+ a forced update of all active registers in MCPWM module*/
+#define MCPWM_GLOBAL_FORCE_UP  (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_M  (BIT(1))
+#define MCPWM_GLOBAL_FORCE_UP_V  0x1
+#define MCPWM_GLOBAL_FORCE_UP_S  1
+/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: The global enable of update of all active registers in MCPWM module*/
+#define MCPWM_GLOBAL_UP_EN  (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_M  (BIT(0))
+#define MCPWM_GLOBAL_UP_EN_V  0x1
+#define MCPWM_GLOBAL_UP_EN_S  0
+
+#define MCMCPWM_INT_ENA_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0110)
+/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_ENA  (BIT(29))
+#define MCPWM_CAP2_INT_ENA_M  (BIT(29))
+#define MCPWM_CAP2_INT_ENA_V  0x1
+#define MCPWM_CAP2_INT_ENA_S  29
+/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_ENA  (BIT(28))
+#define MCPWM_CAP1_INT_ENA_M  (BIT(28))
+#define MCPWM_CAP1_INT_ENA_V  0x1
+#define MCPWM_CAP1_INT_ENA_S  28
+/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_ENA  (BIT(27))
+#define MCPWM_CAP0_INT_ENA_M  (BIT(27))
+#define MCPWM_CAP0_INT_ENA_V  0x1
+#define MCPWM_CAP0_INT_ENA_S  27
+/* MCPWM_FH2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_ENA  (BIT(26))
+#define MCPWM_FH2_OST_INT_ENA_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_ENA_V  0x1
+#define MCPWM_FH2_OST_INT_ENA_S  26
+/* MCPWM_FH1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_ENA  (BIT(25))
+#define MCPWM_FH1_OST_INT_ENA_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_ENA_V  0x1
+#define MCPWM_FH1_OST_INT_ENA_S  25
+/* MCPWM_FH0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_ENA  (BIT(24))
+#define MCPWM_FH0_OST_INT_ENA_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_ENA_V  0x1
+#define MCPWM_FH0_OST_INT_ENA_S  24
+/* MCPWM_FH2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_ENA  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ENA_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ENA_V  0x1
+#define MCPWM_FH2_CBC_INT_ENA_S  23
+/* MCPWM_FH1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_ENA  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ENA_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ENA_V  0x1
+#define MCPWM_FH1_CBC_INT_ENA_S  22
+/* MCPWM_FH0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by an cycle-by-cycle mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_ENA  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ENA_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ENA_V  0x1
+#define MCPWM_FH0_CBC_INT_ENA_S  21
+/* MCPWM_OP2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_ENA  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ENA_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ENA_V  0x1
+#define MCPWM_OP2_TEB_INT_ENA_S  20
+/* MCPWM_OP1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_ENA  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ENA_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ENA_V  0x1
+#define MCPWM_OP1_TEB_INT_ENA_S  19
+/* MCPWM_OP0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_ENA  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ENA_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ENA_V  0x1
+#define MCPWM_OP0_TEB_INT_ENA_S  18
+/* MCPWM_OP2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_ENA  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ENA_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ENA_V  0x1
+#define MCPWM_OP2_TEA_INT_ENA_S  17
+/* MCPWM_OP1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_ENA  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ENA_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ENA_V  0x1
+#define MCPWM_OP1_TEA_INT_ENA_S  16
+/* MCPWM_OP0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_ENA  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ENA_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ENA_V  0x1
+#define MCPWM_OP0_TEA_INT_ENA_S  15
+/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_ENA  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT2_CLR_INT_ENA_S  14
+/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_ENA  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT1_CLR_INT_ENA_S  13
+/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_ENA  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ENA_V  0x1
+#define MCPWM_FAULT0_CLR_INT_ENA_S  12
+/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_ENA  (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_M  (BIT(11))
+#define MCPWM_FAULT2_INT_ENA_V  0x1
+#define MCPWM_FAULT2_INT_ENA_S  11
+/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_ENA  (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_M  (BIT(10))
+#define MCPWM_FAULT1_INT_ENA_V  0x1
+#define MCPWM_FAULT1_INT_ENA_S  10
+/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The enable bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_ENA  (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_M  (BIT(9))
+#define MCPWM_FAULT0_INT_ENA_V  0x1
+#define MCPWM_FAULT0_INT_ENA_S  9
+/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_ENA  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER2_TEP_INT_ENA_S  8
+/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_ENA  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER1_TEP_INT_ENA_S  7
+/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_ENA  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ENA_V  0x1
+#define MCPWM_TIMER0_TEP_INT_ENA_S  6
+/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_ENA  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_ENA_S  5
+/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_ENA  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_ENA_S  4
+/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_ENA  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ENA_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_ENA_S  3
+/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_ENA  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER2_STOP_INT_ENA_S  2
+/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_ENA  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER1_STOP_INT_ENA_S  1
+/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The enable bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_ENA  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ENA_V  0x1
+#define MCPWM_TIMER0_STOP_INT_ENA_S  0
+
+#define MCMCPWM_INT_RAW_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0114)
+/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_RAW  (BIT(29))
+#define MCPWM_CAP2_INT_RAW_M  (BIT(29))
+#define MCPWM_CAP2_INT_RAW_V  0x1
+#define MCPWM_CAP2_INT_RAW_S  29
+/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_RAW  (BIT(28))
+#define MCPWM_CAP1_INT_RAW_M  (BIT(28))
+#define MCPWM_CAP1_INT_RAW_V  0x1
+#define MCPWM_CAP1_INT_RAW_S  28
+/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_RAW  (BIT(27))
+#define MCPWM_CAP0_INT_RAW_M  (BIT(27))
+#define MCPWM_CAP0_INT_RAW_V  0x1
+#define MCPWM_CAP0_INT_RAW_S  27
+/* MCPWM_FH2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_RAW  (BIT(26))
+#define MCPWM_FH2_OST_INT_RAW_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_RAW_V  0x1
+#define MCPWM_FH2_OST_INT_RAW_S  26
+/* MCPWM_FH1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_RAW  (BIT(25))
+#define MCPWM_FH1_OST_INT_RAW_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_RAW_V  0x1
+#define MCPWM_FH1_OST_INT_RAW_S  25
+/* MCPWM_FH0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_RAW  (BIT(24))
+#define MCPWM_FH0_OST_INT_RAW_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_RAW_V  0x1
+#define MCPWM_FH0_OST_INT_RAW_S  24
+/* MCPWM_FH2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_RAW  (BIT(23))
+#define MCPWM_FH2_CBC_INT_RAW_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_RAW_V  0x1
+#define MCPWM_FH2_CBC_INT_RAW_S  23
+/* MCPWM_FH1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_RAW  (BIT(22))
+#define MCPWM_FH1_CBC_INT_RAW_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_RAW_V  0x1
+#define MCPWM_FH1_CBC_INT_RAW_S  22
+/* MCPWM_FH0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_RAW  (BIT(21))
+#define MCPWM_FH0_CBC_INT_RAW_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_RAW_V  0x1
+#define MCPWM_FH0_CBC_INT_RAW_S  21
+/* MCPWM_OP2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_RAW  (BIT(20))
+#define MCPWM_OP2_TEB_INT_RAW_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_RAW_V  0x1
+#define MCPWM_OP2_TEB_INT_RAW_S  20
+/* MCPWM_OP1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_RAW  (BIT(19))
+#define MCPWM_OP1_TEB_INT_RAW_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_RAW_V  0x1
+#define MCPWM_OP1_TEB_INT_RAW_S  19
+/* MCPWM_OP0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_RAW  (BIT(18))
+#define MCPWM_OP0_TEB_INT_RAW_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_RAW_V  0x1
+#define MCPWM_OP0_TEB_INT_RAW_S  18
+/* MCPWM_OP2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_RAW  (BIT(17))
+#define MCPWM_OP2_TEA_INT_RAW_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_RAW_V  0x1
+#define MCPWM_OP2_TEA_INT_RAW_S  17
+/* MCPWM_OP1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_RAW  (BIT(16))
+#define MCPWM_OP1_TEA_INT_RAW_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_RAW_V  0x1
+#define MCPWM_OP1_TEA_INT_RAW_S  16
+/* MCPWM_OP0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_RAW  (BIT(15))
+#define MCPWM_OP0_TEA_INT_RAW_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_RAW_V  0x1
+#define MCPWM_OP0_TEA_INT_RAW_S  15
+/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_RAW  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT2_CLR_INT_RAW_S  14
+/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_RAW  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT1_CLR_INT_RAW_S  13
+/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_RAW  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_RAW_V  0x1
+#define MCPWM_FAULT0_CLR_INT_RAW_S  12
+/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_RAW  (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_M  (BIT(11))
+#define MCPWM_FAULT2_INT_RAW_V  0x1
+#define MCPWM_FAULT2_INT_RAW_S  11
+/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_RAW  (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_M  (BIT(10))
+#define MCPWM_FAULT1_INT_RAW_V  0x1
+#define MCPWM_FAULT1_INT_RAW_S  10
+/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The raw status bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_RAW  (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_M  (BIT(9))
+#define MCPWM_FAULT0_INT_RAW_V  0x1
+#define MCPWM_FAULT0_INT_RAW_S  9
+/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_RAW  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER2_TEP_INT_RAW_S  8
+/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_RAW  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER1_TEP_INT_RAW_S  7
+/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_RAW  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_RAW_V  0x1
+#define MCPWM_TIMER0_TEP_INT_RAW_S  6
+/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_RAW  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_RAW_S  5
+/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_RAW  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_RAW_S  4
+/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_RAW  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_RAW_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_RAW_S  3
+/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_RAW  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER2_STOP_INT_RAW_S  2
+/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_RAW  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER1_STOP_INT_RAW_S  1
+/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The raw status bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_RAW  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_RAW_V  0x1
+#define MCPWM_TIMER0_STOP_INT_RAW_S  0
+
+#define MCMCPWM_INT_ST_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x0118)
+/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_ST  (BIT(29))
+#define MCPWM_CAP2_INT_ST_M  (BIT(29))
+#define MCPWM_CAP2_INT_ST_V  0x1
+#define MCPWM_CAP2_INT_ST_S  29
+/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_ST  (BIT(28))
+#define MCPWM_CAP1_INT_ST_M  (BIT(28))
+#define MCPWM_CAP1_INT_ST_V  0x1
+#define MCPWM_CAP1_INT_ST_S  28
+/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_ST  (BIT(27))
+#define MCPWM_CAP0_INT_ST_M  (BIT(27))
+#define MCPWM_CAP0_INT_ST_V  0x1
+#define MCPWM_CAP0_INT_ST_S  27
+/* MCPWM_FH2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_ST  (BIT(26))
+#define MCPWM_FH2_OST_INT_ST_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_ST_V  0x1
+#define MCPWM_FH2_OST_INT_ST_S  26
+/* MCPWM_FH1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_ST  (BIT(25))
+#define MCPWM_FH1_OST_INT_ST_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_ST_V  0x1
+#define MCPWM_FH1_OST_INT_ST_S  25
+/* MCPWM_FH0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_ST  (BIT(24))
+#define MCPWM_FH0_OST_INT_ST_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_ST_V  0x1
+#define MCPWM_FH0_OST_INT_ST_S  24
+/* MCPWM_FH2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_ST  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ST_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_ST_V  0x1
+#define MCPWM_FH2_CBC_INT_ST_S  23
+/* MCPWM_FH1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_ST  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ST_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_ST_V  0x1
+#define MCPWM_FH1_CBC_INT_ST_S  22
+/* MCPWM_FH0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_ST  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ST_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_ST_V  0x1
+#define MCPWM_FH0_CBC_INT_ST_S  21
+/* MCPWM_OP2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_ST  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ST_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_ST_V  0x1
+#define MCPWM_OP2_TEB_INT_ST_S  20
+/* MCPWM_OP1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_ST  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ST_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_ST_V  0x1
+#define MCPWM_OP1_TEB_INT_ST_S  19
+/* MCPWM_OP0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_ST  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ST_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_ST_V  0x1
+#define MCPWM_OP0_TEB_INT_ST_S  18
+/* MCPWM_OP2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_ST  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ST_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_ST_V  0x1
+#define MCPWM_OP2_TEA_INT_ST_S  17
+/* MCPWM_OP1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_ST  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ST_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_ST_V  0x1
+#define MCPWM_OP1_TEA_INT_ST_S  16
+/* MCPWM_OP0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_ST  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ST_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_ST_V  0x1
+#define MCPWM_OP0_TEA_INT_ST_S  15
+/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_ST  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT2_CLR_INT_ST_S  14
+/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_ST  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT1_CLR_INT_ST_S  13
+/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_ST  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_ST_V  0x1
+#define MCPWM_FAULT0_CLR_INT_ST_S  12
+/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_ST  (BIT(11))
+#define MCPWM_FAULT2_INT_ST_M  (BIT(11))
+#define MCPWM_FAULT2_INT_ST_V  0x1
+#define MCPWM_FAULT2_INT_ST_S  11
+/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_ST  (BIT(10))
+#define MCPWM_FAULT1_INT_ST_M  (BIT(10))
+#define MCPWM_FAULT1_INT_ST_V  0x1
+#define MCPWM_FAULT1_INT_ST_S  10
+/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: The masked status bit for interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_ST  (BIT(9))
+#define MCPWM_FAULT0_INT_ST_M  (BIT(9))
+#define MCPWM_FAULT0_INT_ST_V  0x1
+#define MCPWM_FAULT0_INT_ST_S  9
+/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_ST  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER2_TEP_INT_ST_S  8
+/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_ST  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER1_TEP_INT_ST_S  7
+/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_ST  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_ST_V  0x1
+#define MCPWM_TIMER0_TEP_INT_ST_S  6
+/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_ST  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_ST_S  5
+/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_ST  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_ST_S  4
+/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_ST  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_ST_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_ST_S  3
+/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_ST  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER2_STOP_INT_ST_S  2
+/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_ST  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER1_STOP_INT_ST_S  1
+/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The masked status bit for interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_ST  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_ST_V  0x1
+#define MCPWM_TIMER0_STOP_INT_ST_S  0
+
+#define MCMCPWM_INT_CLR_MCPWM_REG(i)          (REG_MCPWM_BASE(i) + 0x011c)
+/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 2*/
+#define MCPWM_CAP2_INT_CLR  (BIT(29))
+#define MCPWM_CAP2_INT_CLR_M  (BIT(29))
+#define MCPWM_CAP2_INT_CLR_V  0x1
+#define MCPWM_CAP2_INT_CLR_S  29
+/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 1*/
+#define MCPWM_CAP1_INT_CLR  (BIT(28))
+#define MCPWM_CAP1_INT_CLR_M  (BIT(28))
+#define MCPWM_CAP1_INT_CLR_V  0x1
+#define MCPWM_CAP1_INT_CLR_S  28
+/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by captureon channel 0*/
+#define MCPWM_CAP0_INT_CLR  (BIT(27))
+#define MCPWM_CAP0_INT_CLR_M  (BIT(27))
+#define MCPWM_CAP0_INT_CLR_V  0x1
+#define MCPWM_CAP0_INT_CLR_S  27
+/* MCPWM_FH2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM2*/
+#define MCPWM_FH2_OST_INT_CLR  (BIT(26))
+#define MCPWM_FH2_OST_INT_CLR_M  (BIT(26))
+#define MCPWM_FH2_OST_INT_CLR_V  0x1
+#define MCPWM_FH2_OST_INT_CLR_S  26
+/* MCPWM_FH1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH1_OST_INT_CLR  (BIT(25))
+#define MCPWM_FH1_OST_INT_CLR_M  (BIT(25))
+#define MCPWM_FH1_OST_INT_CLR_V  0x1
+#define MCPWM_FH1_OST_INT_CLR_S  25
+/* MCPWM_FH0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an one-shot mode action on PWM0*/
+#define MCPWM_FH0_OST_INT_CLR  (BIT(24))
+#define MCPWM_FH0_OST_INT_CLR_M  (BIT(24))
+#define MCPWM_FH0_OST_INT_CLR_V  0x1
+#define MCPWM_FH0_OST_INT_CLR_S  24
+/* MCPWM_FH2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM2*/
+#define MCPWM_FH2_CBC_INT_CLR  (BIT(23))
+#define MCPWM_FH2_CBC_INT_CLR_M  (BIT(23))
+#define MCPWM_FH2_CBC_INT_CLR_V  0x1
+#define MCPWM_FH2_CBC_INT_CLR_S  23
+/* MCPWM_FH1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM1*/
+#define MCPWM_FH1_CBC_INT_CLR  (BIT(22))
+#define MCPWM_FH1_CBC_INT_CLR_M  (BIT(22))
+#define MCPWM_FH1_CBC_INT_CLR_V  0x1
+#define MCPWM_FH1_CBC_INT_CLR_S  22
+/* MCPWM_FH0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by an cycle-by-cycle
+ mode action on PWM0*/
+#define MCPWM_FH0_CBC_INT_CLR  (BIT(21))
+#define MCPWM_FH0_CBC_INT_CLR_M  (BIT(21))
+#define MCPWM_FH0_CBC_INT_CLR_V  0x1
+#define MCPWM_FH0_CBC_INT_CLR_S  21
+/* MCPWM_OP2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEB event*/
+#define MCPWM_OP2_TEB_INT_CLR  (BIT(20))
+#define MCPWM_OP2_TEB_INT_CLR_M  (BIT(20))
+#define MCPWM_OP2_TEB_INT_CLR_V  0x1
+#define MCPWM_OP2_TEB_INT_CLR_S  20
+/* MCPWM_OP1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEB event*/
+#define MCPWM_OP1_TEB_INT_CLR  (BIT(19))
+#define MCPWM_OP1_TEB_INT_CLR_M  (BIT(19))
+#define MCPWM_OP1_TEB_INT_CLR_V  0x1
+#define MCPWM_OP1_TEB_INT_CLR_S  19
+/* MCPWM_OP0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEB event*/
+#define MCPWM_OP0_TEB_INT_CLR  (BIT(18))
+#define MCPWM_OP0_TEB_INT_CLR_M  (BIT(18))
+#define MCPWM_OP0_TEB_INT_CLR_V  0x1
+#define MCPWM_OP0_TEB_INT_CLR_S  18
+/* MCPWM_OP2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 2 TEA event*/
+#define MCPWM_OP2_TEA_INT_CLR  (BIT(17))
+#define MCPWM_OP2_TEA_INT_CLR_M  (BIT(17))
+#define MCPWM_OP2_TEA_INT_CLR_V  0x1
+#define MCPWM_OP2_TEA_INT_CLR_S  17
+/* MCPWM_OP1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 1 TEA event*/
+#define MCPWM_OP1_TEA_INT_CLR  (BIT(16))
+#define MCPWM_OP1_TEA_INT_CLR_M  (BIT(16))
+#define MCPWM_OP1_TEA_INT_CLR_V  0x1
+#define MCPWM_OP1_TEA_INT_CLR_S  16
+/* MCPWM_OP0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM operator 0 TEA event*/
+#define MCPWM_OP0_TEA_INT_CLR  (BIT(15))
+#define MCPWM_OP0_TEA_INT_CLR_M  (BIT(15))
+#define MCPWM_OP0_TEA_INT_CLR_V  0x1
+#define MCPWM_OP0_TEA_INT_CLR_S  15
+/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f2 ends*/
+#define MCPWM_FAULT2_CLR_INT_CLR  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_M  (BIT(14))
+#define MCPWM_FAULT2_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT2_CLR_INT_CLR_S  14
+/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f1 ends*/
+#define MCPWM_FAULT1_CLR_INT_CLR  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_M  (BIT(13))
+#define MCPWM_FAULT1_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT1_CLR_INT_CLR_S  13
+/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f0 ends*/
+#define MCPWM_FAULT0_CLR_INT_CLR  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_M  (BIT(12))
+#define MCPWM_FAULT0_CLR_INT_CLR_V  0x1
+#define MCPWM_FAULT0_CLR_INT_CLR_S  12
+/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f2 starts*/
+#define MCPWM_FAULT2_INT_CLR  (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_M  (BIT(11))
+#define MCPWM_FAULT2_INT_CLR_V  0x1
+#define MCPWM_FAULT2_INT_CLR_S  11
+/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f1 starts*/
+#define MCPWM_FAULT1_INT_CLR  (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_M  (BIT(10))
+#define MCPWM_FAULT1_INT_CLR_V  0x1
+#define MCPWM_FAULT1_INT_CLR_S  10
+/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: Set this bit to clear interrupt triggered when event_f0 starts*/
+#define MCPWM_FAULT0_INT_CLR  (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_M  (BIT(9))
+#define MCPWM_FAULT0_INT_CLR_V  0x1
+#define MCPWM_FAULT0_INT_CLR_S  9
+/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEP event*/
+#define MCPWM_TIMER2_TEP_INT_CLR  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_M  (BIT(8))
+#define MCPWM_TIMER2_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER2_TEP_INT_CLR_S  8
+/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEP event*/
+#define MCPWM_TIMER1_TEP_INT_CLR  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_M  (BIT(7))
+#define MCPWM_TIMER1_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER1_TEP_INT_CLR_S  7
+/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEP event*/
+#define MCPWM_TIMER0_TEP_INT_CLR  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_M  (BIT(6))
+#define MCPWM_TIMER0_TEP_INT_CLR_V  0x1
+#define MCPWM_TIMER0_TEP_INT_CLR_S  6
+/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 2 TEZ event*/
+#define MCPWM_TIMER2_TEZ_INT_CLR  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_M  (BIT(5))
+#define MCPWM_TIMER2_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER2_TEZ_INT_CLR_S  5
+/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 1 TEZ event*/
+#define MCPWM_TIMER1_TEZ_INT_CLR  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_M  (BIT(4))
+#define MCPWM_TIMER1_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER1_TEZ_INT_CLR_S  4
+/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered by a PWM timer 0 TEZ event*/
+#define MCPWM_TIMER0_TEZ_INT_CLR  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_M  (BIT(3))
+#define MCPWM_TIMER0_TEZ_INT_CLR_V  0x1
+#define MCPWM_TIMER0_TEZ_INT_CLR_S  3
+/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 2 stops*/
+#define MCPWM_TIMER2_STOP_INT_CLR  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_M  (BIT(2))
+#define MCPWM_TIMER2_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER2_STOP_INT_CLR_S  2
+/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 1 stops*/
+#define MCPWM_TIMER1_STOP_INT_CLR  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_M  (BIT(1))
+#define MCPWM_TIMER1_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER1_STOP_INT_CLR_S  1
+/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to clear interrupt triggered when timer 0 stops*/
+#define MCPWM_TIMER0_STOP_INT_CLR  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_M  (BIT(0))
+#define MCPWM_TIMER0_STOP_INT_CLR_V  0x1
+#define MCPWM_TIMER0_STOP_INT_CLR_S  0
+
+#define MCPWM_CLK_REG(i)          (REG_MCPWM_BASE(i) + 0x0120)
+/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: Force clock on for this reg file*/
+#define MCPWM_CLK_EN  (BIT(0))
+#define MCPWM_CLK_EN_M  (BIT(0))
+#define MCPWM_CLK_EN_V  0x1
+#define MCPWM_CLK_EN_S  0
+
+#define MCPWM_VERSION_REG(i)          (REG_MCPWM_BASE(i) + 0x0124)
+/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */
+/*description: Version of this reg file*/
+#define MCPWM_DATE  0x0FFFFFFF
+#define MCPWM_DATE_M  ((MCPWM_DATE_V)<<(MCPWM_DATE_S))
+#define MCPWM_DATE_V  0xFFFFFFF
+#define MCPWM_DATE_S  0
+
+
+
+
+#endif /*_SOC_MCPWM_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/mcpwm_struct.h b/components/soc/esp32s2beta/include/soc/mcpwm_struct.h
new file mode 100644
index 000000000..f41d40c64
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/mcpwm_struct.h
@@ -0,0 +1,462 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_MCPWM_STRUCT_H__
+#define _SOC_MCPWM_STRUCT_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t prescale: 8;                  /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    }clk_cfg;
+    struct {
+        union {
+            struct {
+                uint32_t prescale:        8;        /*period of PT0_clk = Period of PWM_clk * (PWM_TIMER0_PRESCALE + 1)*/
+                uint32_t period:         16;        /*period shadow reg of PWM timer0*/
+                uint32_t upmethod: 2;        /*Update method for active reg of PWM timer0 period  0: immediate  1: TEZ  2: sync  3: TEZ | sync. TEZ here and below means timer equal zero event*/
+                uint32_t reserved26:      6;
+            };
+            uint32_t val;
+        }period;
+        union {
+            struct {
+                uint32_t start: 3;                  /*PWM timer0 start and stop control. 0: stop @ TEZ  1: stop @ TEP  2: free run  3: start and stop @ next TEZ  4: start and stop @ next TEP. TEP here and below means timer equal period event*/
+                uint32_t mode:   2;                  /*PWM timer0 working mode  0: freeze  1: increase mod  2: decrease mod  3: up-down mod*/
+                uint32_t reserved5:   27;
+            };
+            uint32_t val;
+        }mode;
+        union {
+            struct {
+                uint32_t in_en:     1;              /*when set   timer reload with phase on sync input event is enabled*/
+                uint32_t sync_sw:   1;              /*write the negate value will trigger a software sync*/
+                uint32_t out_sel: 2;              /*PWM timer0 synco selection  0: synci  1: TEZ  2: TEP  else 0*/
+                uint32_t timer_phase:    17;              /*phase for timer reload on sync event*/
+                uint32_t reserved21:      11;
+            };
+            uint32_t val;
+        }sync;
+        union {
+            struct {
+                uint32_t value:    16;              /*current PWM timer0 counter value*/
+                uint32_t direction: 1;              /*current PWM timer0 counter direction  0: increment 1: decrement*/
+                uint32_t reserved17:      15;
+            };
+            uint32_t val;
+        }status;
+    }timer[3];
+
+
+    union {
+        struct {
+            uint32_t t0_in_sel:   3;        /*select sync input for PWM timer0  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t t1_in_sel:   3;        /*select sync input for PWM timer1  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t t2_in_sel:   3;        /*select sync input for PWM timer2  1: PWM timer0 synco  2: PWM timer1 synco  3: PWM timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix  else: none*/
+            uint32_t ext_in0_inv: 1;        /*invert SYNC0 from GPIO matrix*/
+            uint32_t ext_in1_inv: 1;        /*invert SYNC1 from GPIO matrix*/
+            uint32_t ext_in2_inv: 1;        /*invert SYNC2 from GPIO matrix*/
+            uint32_t reserved12:            20;
+        };
+        uint32_t val;
+    }timer_synci_cfg;
+    union {
+        struct {
+            uint32_t operator0_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator0  0: timer0  1: timer1  2: timer2*/
+            uint32_t operator1_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator1  0: timer0  1: timer1  2: timer2*/
+            uint32_t operator2_sel: 2;            /*Select which PWM timer's is the timing reference for PWM operator2  0: timer0  1: timer1  2: timer2*/
+            uint32_t reserved6:         26;
+        };
+        uint32_t val;
+    }timer_sel;
+
+
+    struct {
+        union {
+            struct {
+                uint32_t a_upmethod:  4;             /*Update method for PWM compare0 A's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
+                uint32_t b_upmethod:  4;             /*Update method for PWM compare0 B's active reg. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync  bit3: freeze*/
+                uint32_t a_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 A's shadow reg is filled and waiting to be transferred to A's active reg. If cleared  A's active reg has been updated with shadow reg latest value*/
+                uint32_t b_shdw_full: 1;             /*Set and reset by hardware. If set  PWM compare0 B's shadow reg is filled and waiting to be transferred to B's active reg. If cleared  B's active reg has been updated with shadow reg latest value*/
+                uint32_t reserved10:       22;
+            };
+            uint32_t val;
+        }cmpr_cfg;
+        union {
+            struct {
+                uint32_t cmpr_val:       16;                    /*PWM compare0 A's shadow reg*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }cmpr_value[2];
+        union {
+            struct {
+                uint32_t upmethod: 4;             /*Update method for PWM generate0's active reg of configuration. 0: immediate  bit0: TEZ  bit1: TEP  bit2: sync. bit3: freeze*/
+                uint32_t t0_sel:       3;             /*Source selection for PWM generate0 event_t0  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+                uint32_t t1_sel:       3;             /*Source selection for PWM generate0 event_t1  take effect immediately  0: fault_event0  1: fault_event1  2: fault_event2  3: sync_taken  4: none*/
+                uint32_t reserved10:       22;
+            };
+            uint32_t val;
+        }gen_cfg0;
+        union {
+            struct {
+                uint32_t cntu_force_upmethod: 6;       /*Update method for continuous software force of PWM generate0. 0: immediate  bit0: TEZ  bit1: TEP  bit2: TEA  bit3: TEB  bit4: sync  bit5: freeze. (TEA/B here and below means timer equals A/B event)*/
+                uint32_t a_cntuforce_mode:   2;       /*Continuous software force mode for PWM0A. 0: disabled  1: low  2: high  3: disabled*/
+                uint32_t b_cntuforce_mode:   2;       /*Continuous software force mode for PWM0B. 0: disabled  1: low  2: high  3: disabled*/
+                uint32_t a_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0A  a toggle will trigger a force event*/
+                uint32_t a_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0A  0: disabled  1: low  2: high  3: disabled*/
+                uint32_t b_nciforce:         1;       /*non-continuous immediate software force trigger for PWM0B  a toggle will trigger a force event*/
+                uint32_t b_nciforce_mode:    2;       /*non-continuous immediate software force mode for PWM0B  0: disabled  1: low  2: high  3: disabled*/
+                uint32_t reserved16:             16;
+            };
+            uint32_t val;
+        }gen_force;
+        union {
+            struct {
+                uint32_t utez: 2;                   /*Action on PWM0A triggered by event TEZ when timer increasing*/
+                uint32_t utep: 2;                   /*Action on PWM0A triggered by event TEP when timer increasing*/
+                uint32_t utea: 2;                   /*Action on PWM0A triggered by event TEA when timer increasing*/
+                uint32_t uteb: 2;                   /*Action on PWM0A triggered by event TEB when timer increasing*/
+                uint32_t ut0:  2;                   /*Action on PWM0A triggered by event_t0 when timer increasing*/
+                uint32_t ut1:  2;                   /*Action on PWM0A triggered by event_t1 when timer increasing*/
+                uint32_t dtez: 2;                   /*Action on PWM0A triggered by event TEZ when timer decreasing*/
+                uint32_t dtep: 2;                   /*Action on PWM0A triggered by event TEP when timer decreasing*/
+                uint32_t dtea: 2;                   /*Action on PWM0A triggered by event TEA when timer decreasing*/
+                uint32_t dteb: 2;                   /*Action on PWM0A triggered by event TEB when timer decreasing*/
+                uint32_t dt0:  2;                   /*Action on PWM0A triggered by event_t0 when timer decreasing*/
+                uint32_t dt1:  2;                   /*Action on PWM0A triggered by event_t1 when timer decreasing. 0: no change  1: low  2: high  3: toggle*/
+                uint32_t reserved24:  8;
+            };
+            uint32_t val;
+        }generator[2];
+        union {
+            struct {
+                uint32_t fed_upmethod:  4;             /*Update method for FED (falling edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
+                uint32_t red_upmethod:  4;             /*Update method for RED (rising edge delay) active reg. 0: immediate  bit0: tez  bit1: tep  bit2: sync  bit3: freeze*/
+                uint32_t deb_mode:      1;             /*S8 in documentation  dual-edge B mode  0: fed/red take effect on different path separately  1: fed/red take effect on B path  A out is in bypass or dulpB mode*/
+                uint32_t a_outswap:     1;             /*S6 in documentation*/
+                uint32_t b_outswap:     1;             /*S7 in documentation*/
+                uint32_t red_insel:     1;             /*S4 in documentation*/
+                uint32_t fed_insel:     1;             /*S5 in documentation*/
+                uint32_t red_outinvert: 1;             /*S2 in documentation*/
+                uint32_t fed_outinvert: 1;             /*S3 in documentation*/
+                uint32_t a_outbypass:   1;             /*S1 in documentation*/
+                uint32_t b_outbypass:   1;             /*S0 in documentation*/
+                uint32_t clk_sel:       1;             /*Dead band0 clock selection. 0: PWM_clk  1: PT_clk*/
+                uint32_t reserved18:   14;
+            };
+            uint32_t val;
+        }db_cfg;
+        union {
+            struct {
+                uint32_t fed:   16;                    /*Shadow reg for FED*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }db_fed_cfg;
+        union {
+            struct {
+                uint32_t red:   16;                    /*Shadow reg for RED*/
+                uint32_t reserved16:16;
+            };
+            uint32_t val;
+        }db_red_cfg;
+        union {
+            struct {
+                uint32_t en:         1;           /*When set  carrier0 function is enabled. When reset  carrier0 is bypassed*/
+                uint32_t prescale:   4;           /*carrier0 clk (CP_clk) prescale value. Period of CP_clk = period of PWM_clk * (PWM_CARRIER0_PRESCALE + 1)*/
+                uint32_t duty:       3;           /*carrier duty selection. Duty = PWM_CARRIER0_DUTY / 8*/
+                uint32_t oshtwth:    4;           /*width of the fist pulse in number of periods of the carrier*/
+                uint32_t out_invert: 1;           /*when set  invert the output of PWM0A and PWM0B for this submodule*/
+                uint32_t in_invert:  1;           /*when set  invert the input of PWM0A and PWM0B for this submodule*/
+                uint32_t reserved14:         18;
+            };
+            uint32_t val;
+        }carrier_cfg;
+        union {
+            struct {
+                uint32_t sw_cbc:  1;                   /*Cycle-by-cycle tripping software force event will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f2_cbc:  1;                   /*event_f2 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f1_cbc:  1;                   /*event_f1 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t f0_cbc:  1;                   /*event_f0 will trigger cycle-by-cycle trip event. 0: disable  1: enable*/
+                uint32_t sw_ost:  1;                   /*one-shot tripping software force event will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f2_ost:  1;                   /*event_f2 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f1_ost:  1;                   /*event_f1 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t f0_ost:  1;                   /*event_f0 will trigger one-shot trip event. 0: disable  1: enable*/
+                uint32_t a_cbc_d: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_cbc_u: 2;                   /*Action on PWM0A when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_ost_d: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t a_ost_u: 2;                   /*Action on PWM0A when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_cbc_d: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_cbc_u: 2;                   /*Action on PWM0B when cycle-by-cycle trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_ost_d: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is decreasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t b_ost_u: 2;                   /*Action on PWM0B when one-shot trip event occurs and timer is increasing. 0: do nothing  1: force lo  2: force hi  3: toggle*/
+                uint32_t reserved24:  8;
+            };
+            uint32_t val;
+        }tz_cfg0;
+        union {
+            struct {
+                uint32_t clr_ost:   1;                 /*a toggle will clear on going one-shot tripping*/
+                uint32_t cbcpulse:  2;                 /*cycle-by-cycle tripping refresh moment selection. Bit0: TEZ  bit1:TEP*/
+                uint32_t force_cbc: 1;                 /*a toggle trigger a cycle-by-cycle tripping software force event*/
+                uint32_t force_ost: 1;                 /*a toggle (software negate its value) trigger a one-shot tripping software force event*/
+                uint32_t reserved5:    27;
+            };
+            uint32_t val;
+        }tz_cfg1;
+        union {
+            struct {
+                uint32_t cbc_on: 1;                    /*Set and reset by hardware. If set  an cycle-by-cycle trip event is on going*/
+                uint32_t ost_on: 1;                    /*Set and reset by hardware. If set  an one-shot trip event is on going*/
+                uint32_t reserved2: 30;
+            };
+            uint32_t val;
+        }tz_status;
+    }channel[3];
+
+    union {
+        struct {
+            uint32_t f0_en:      1;                    /*When set  event_f0 generation is enabled*/
+            uint32_t f1_en:      1;                    /*When set  event_f1 generation is enabled*/
+            uint32_t f2_en:      1;                    /*When set  event_f2 generation is enabled*/
+            uint32_t f0_pole:    1;                    /*Set event_f0 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t f1_pole:    1;                    /*Set event_f1 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t f2_pole:    1;                    /*Set event_f2 trigger polarity on FAULT2 source from GPIO matrix. 0: level low  1: level high*/
+            uint32_t event_f0:   1;                    /*Set and reset by hardware. If set  event_f0 is on going*/
+            uint32_t event_f1:   1;                    /*Set and reset by hardware. If set  event_f1 is on going*/
+            uint32_t event_f2:   1;                    /*Set and reset by hardware. If set  event_f2 is on going*/
+            uint32_t reserved9: 23;
+        };
+        uint32_t val;
+    }fault_detect;
+    union {
+        struct {
+            uint32_t timer_en:  1;                 /*When set  capture timer incrementing under APB_clk is enabled.*/
+            uint32_t synci_en:  1;                 /*When set  capture timer sync is enabled.*/
+            uint32_t synci_sel: 3;                 /*capture module sync input selection. 0: none  1: timer0 synco  2: timer1 synco  3: timer2 synco  4: SYNC0 from GPIO matrix  5: SYNC1 from GPIO matrix  6: SYNC2 from GPIO matrix*/
+            uint32_t sync_sw:   1;                 /*Write 1 will force a capture timer sync  capture timer is loaded with value in phase register.*/
+            uint32_t reserved6:    26;
+        };
+        uint32_t val;
+    }cap_timer_cfg;
+    uint32_t cap_timer_phase;                      /*Phase value for capture timer sync operation.*/
+    union {
+        struct {
+            uint32_t en:        1;                /*When set  capture on channel 0 is enabled*/
+            uint32_t mode:      2;                /*Edge of capture on channel 0 after prescale.  bit0: negedge cap en  bit1: posedge cap en*/
+            uint32_t prescale:  8;                /*Value of prescale on possitive edge of CAP0. Prescale value = PWM_CAP0_PRESCALE + 1*/
+            uint32_t in_invert: 1;                /*when set  CAP0 form GPIO matrix is inverted before prescale*/
+            uint32_t sw:        1;                /*Write 1 will trigger a software forced capture on channel 0*/
+            uint32_t reserved13:    19;
+        };
+        uint32_t val;
+    }cap_cfg_ch[3];
+    uint32_t cap_val_ch[3];                              /*Value of last capture on channel 0*/
+    union {
+        struct {
+            uint32_t cap0_edge:  1;                    /*Edge of last capture trigger on channel 0  0: posedge  1: negedge*/
+            uint32_t cap1_edge:  1;                    /*Edge of last capture trigger on channel 1  0: posedge  1: negedge*/
+            uint32_t cap2_edge:  1;                    /*Edge of last capture trigger on channel 2  0: posedge  1: negedge*/
+            uint32_t reserved3: 29;
+        };
+        uint32_t val;
+    }cap_status;
+    union {
+        struct {
+            uint32_t global_up_en:    1;               /*The global enable of update of all active registers in MCPWM module*/
+            uint32_t global_force_up: 1;               /*a toggle (software invert its value) will trigger a forced update of all active registers in MCPWM module*/
+            uint32_t op0_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 0 are enabled*/
+            uint32_t op0_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 0*/
+            uint32_t op1_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 1 are enabled*/
+            uint32_t op1_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 1*/
+            uint32_t op2_up_en:       1;               /*When set and PWM_GLOBAL_UP_EN is set  update of active registers in PWM operator 2 are enabled*/
+            uint32_t op2_force_up:    1;               /*a toggle (software invert its value) will trigger a forced update of active registers in PWM operator 2*/
+            uint32_t reserved8:      24;
+        };
+        uint32_t val;
+    }update_cfg;
+    union {
+        struct {
+            uint32_t timer0_stop_int_ena: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_ena: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_ena: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_ena:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_ena:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_ena:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_ena:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_ena:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_ena:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_ena:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_ena:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_ena:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_ena:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_ena:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_ena:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_ena:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_ena:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_ena:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_ena:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_ena:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_ena:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_ena:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_ena:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_ena:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_ena:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_ena:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_ena:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_ena:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_ena;
+    union {
+        struct {
+            uint32_t timer0_stop_int_raw: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_raw: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_raw: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_raw:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_raw:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_raw:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_raw:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_raw:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_raw:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_raw:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_raw:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_raw:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_raw:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_raw:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_raw:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_raw:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_raw:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_raw:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_raw:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_raw:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_raw:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_raw:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_raw:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_raw:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_raw:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_raw:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_raw:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_raw:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_raw;
+    union {
+        struct {
+            uint32_t timer0_stop_int_st: 1;            /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_st: 1;            /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_st: 1;            /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_st:  1;            /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_st:  1;            /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_st:  1;            /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_st:  1;            /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_st:  1;            /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_st:  1;            /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_st:      1;            /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_st:      1;            /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_st:      1;            /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_st:  1;            /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_st:  1;            /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_st:  1;            /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_st:   1;            /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_st:   1;            /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_st:   1;            /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_st:   1;            /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_st:   1;            /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_st:   1;            /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_st:     1;            /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_st:     1;            /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_st:     1;            /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_st:     1;            /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_st:        1;            /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_st:        1;            /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_st:        1;            /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:         2;
+        };
+        uint32_t val;
+    }int_st;
+    union {
+        struct {
+            uint32_t timer0_stop_int_clr: 1;           /*Interrupt when timer 0 stops*/
+            uint32_t timer1_stop_int_clr: 1;           /*Interrupt when timer 1 stops*/
+            uint32_t timer2_stop_int_clr: 1;           /*Interrupt when timer 2 stops*/
+            uint32_t timer0_tez_int_clr:  1;           /*A PWM timer 0 TEZ event will trigger this interrupt*/
+            uint32_t timer1_tez_int_clr:  1;           /*A PWM timer 1 TEZ event will trigger this interrupt*/
+            uint32_t timer2_tez_int_clr:  1;           /*A PWM timer 2 TEZ event will trigger this interrupt*/
+            uint32_t timer0_tep_int_clr:  1;           /*A PWM timer 0 TEP event will trigger this interrupt*/
+            uint32_t timer1_tep_int_clr:  1;           /*A PWM timer 1 TEP event will trigger this interrupt*/
+            uint32_t timer2_tep_int_clr:  1;           /*A PWM timer 2 TEP event will trigger this interrupt*/
+            uint32_t fault0_int_clr:      1;           /*Interrupt when event_f0 starts*/
+            uint32_t fault1_int_clr:      1;           /*Interrupt when event_f1 starts*/
+            uint32_t fault2_int_clr:      1;           /*Interrupt when event_f2 starts*/
+            uint32_t fault0_clr_int_clr:  1;           /*Interrupt when event_f0 ends*/
+            uint32_t fault1_clr_int_clr:  1;           /*Interrupt when event_f1 ends*/
+            uint32_t fault2_clr_int_clr:  1;           /*Interrupt when event_f2 ends*/
+            uint32_t cmpr0_tea_int_clr:   1;           /*A PWM operator 0 TEA event will trigger this interrupt*/
+            uint32_t cmpr1_tea_int_clr:   1;           /*A PWM operator 1 TEA event will trigger this interrupt*/
+            uint32_t cmpr2_tea_int_clr:   1;           /*A PWM operator 2 TEA event will trigger this interrupt*/
+            uint32_t cmpr0_teb_int_clr:   1;           /*A PWM operator 0 TEB event will trigger this interrupt*/
+            uint32_t cmpr1_teb_int_clr:   1;           /*A PWM operator 1 TEB event will trigger this interrupt*/
+            uint32_t cmpr2_teb_int_clr:   1;           /*A PWM operator 2 TEB event will trigger this interrupt*/
+            uint32_t tz0_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_cbc_int_clr:     1;           /*An cycle-by-cycle trip event on PWM2 will trigger this interrupt*/
+            uint32_t tz0_ost_int_clr:     1;           /*An one-shot trip event on PWM0 will trigger this interrupt*/
+            uint32_t tz1_ost_int_clr:     1;           /*An one-shot trip event on PWM1 will trigger this interrupt*/
+            uint32_t tz2_ost_int_clr:     1;           /*An one-shot trip event on PWM2 will trigger this interrupt*/
+            uint32_t cap0_int_clr:        1;           /*A capture on channel 0 will trigger this interrupt*/
+            uint32_t cap1_int_clr:        1;           /*A capture on channel 1 will trigger this interrupt*/
+            uint32_t cap2_int_clr:        1;           /*A capture on channel 2 will trigger this interrupt*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    }int_clr;
+    union {
+        struct {
+            uint32_t clk_en:     1;                    /*Force clock on for this reg file*/
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    }reg_clk;
+    union {
+        struct {
+            uint32_t date:      28;                    /*Version of this reg file*/
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    }version;
+} mcpwm_dev_t;
+extern mcpwm_dev_t MCPWM0;
+extern mcpwm_dev_t MCPWM1;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_MCPWM_STRUCT_H__ */
diff --git a/components/soc/esp32s2beta/include/soc/nrx_reg.h b/components/soc/esp32s2beta/include/soc/nrx_reg.h
new file mode 100644
index 000000000..ca338b89a
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/nrx_reg.h
@@ -0,0 +1,55 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc/soc.h"
+
+/* Some of the WiFi RX control registers.
+ * PU/PD fields defined here are used in sleep related functions.
+ */
+
+#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
+#define NRX_CHAN_EST_FORCE_PU (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
+#define NRX_CHAN_EST_FORCE_PU_V 1
+#define NRX_CHAN_EST_FORCE_PU_S 7
+#define NRX_CHAN_EST_FORCE_PD (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
+#define NRX_CHAN_EST_FORCE_PD_V 1
+#define NRX_CHAN_EST_FORCE_PD_S 6
+#define NRX_RX_ROT_FORCE_PU (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
+#define NRX_RX_ROT_FORCE_PU_V 1
+#define NRX_RX_ROT_FORCE_PU_S 5
+#define NRX_RX_ROT_FORCE_PD (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
+#define NRX_RX_ROT_FORCE_PD_V 1
+#define NRX_RX_ROT_FORCE_PD_S 4
+#define NRX_VIT_FORCE_PU (BIT(3))
+#define NRX_VIT_FORCE_PU_M (BIT(3))
+#define NRX_VIT_FORCE_PU_V 1
+#define NRX_VIT_FORCE_PU_S 3
+#define NRX_VIT_FORCE_PD (BIT(2))
+#define NRX_VIT_FORCE_PD_M (BIT(2))
+#define NRX_VIT_FORCE_PD_V 1
+#define NRX_VIT_FORCE_PD_S 2
+#define NRX_DEMAP_FORCE_PU (BIT(1))
+#define NRX_DEMAP_FORCE_PU_M (BIT(1))
+#define NRX_DEMAP_FORCE_PU_V 1
+#define NRX_DEMAP_FORCE_PU_S 1
+#define NRX_DEMAP_FORCE_PD (BIT(0))
+#define NRX_DEMAP_FORCE_PD_M (BIT(0))
+#define NRX_DEMAP_FORCE_PD_V 1
+#define NRX_DEMAP_FORCE_PD_S 0
diff --git a/components/soc/esp32s2beta/include/soc/pcnt_reg.h b/components/soc/esp32s2beta/include/soc/pcnt_reg.h
new file mode 100644
index 000000000..38b1dd721
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/pcnt_reg.h
@@ -0,0 +1,1742 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_PCNT_REG_H_
+#define _SOC_PCNT_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define PCNT_U0_CONF0_REG          (DR_REG_PCNT_BASE + 0x0000)
+/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U0  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U0_M  ((PCNT_CH1_LCTRL_MODE_U0_V)<<(PCNT_CH1_LCTRL_MODE_U0_S))
+#define PCNT_CH1_LCTRL_MODE_U0_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U0_S  30
+/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U0  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U0_M  ((PCNT_CH1_HCTRL_MODE_U0_V)<<(PCNT_CH1_HCTRL_MODE_U0_S))
+#define PCNT_CH1_HCTRL_MODE_U0_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U0_S  28
+/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit0. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U0  0x00000003
+#define PCNT_CH1_POS_MODE_U0_M  ((PCNT_CH1_POS_MODE_U0_V)<<(PCNT_CH1_POS_MODE_U0_S))
+#define PCNT_CH1_POS_MODE_U0_V  0x3
+#define PCNT_CH1_POS_MODE_U0_S  26
+/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit0. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U0  0x00000003
+#define PCNT_CH1_NEG_MODE_U0_M  ((PCNT_CH1_NEG_MODE_U0_V)<<(PCNT_CH1_NEG_MODE_U0_S))
+#define PCNT_CH1_NEG_MODE_U0_V  0x3
+#define PCNT_CH1_NEG_MODE_U0_S  24
+/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U0  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U0_M  ((PCNT_CH0_LCTRL_MODE_U0_V)<<(PCNT_CH0_LCTRL_MODE_U0_S))
+#define PCNT_CH0_LCTRL_MODE_U0_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U0_S  22
+/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit0. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U0  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U0_M  ((PCNT_CH0_HCTRL_MODE_U0_V)<<(PCNT_CH0_HCTRL_MODE_U0_S))
+#define PCNT_CH0_HCTRL_MODE_U0_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U0_S  20
+/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit0. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U0  0x00000003
+#define PCNT_CH0_POS_MODE_U0_M  ((PCNT_CH0_POS_MODE_U0_V)<<(PCNT_CH0_POS_MODE_U0_S))
+#define PCNT_CH0_POS_MODE_U0_V  0x3
+#define PCNT_CH0_POS_MODE_U0_S  18
+/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit0. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U0  0x00000003
+#define PCNT_CH0_NEG_MODE_U0_M  ((PCNT_CH0_NEG_MODE_U0_V)<<(PCNT_CH0_NEG_MODE_U0_S))
+#define PCNT_CH0_NEG_MODE_U0_V  0x3
+#define PCNT_CH0_NEG_MODE_U0_S  16
+/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit0's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U0  (BIT(15))
+#define PCNT_THR_THRES1_EN_U0_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U0_V  0x1
+#define PCNT_THR_THRES1_EN_U0_S  15
+/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit0's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U0  (BIT(14))
+#define PCNT_THR_THRES0_EN_U0_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U0_V  0x1
+#define PCNT_THR_THRES0_EN_U0_S  14
+/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit0's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U0  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U0_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U0_V  0x1
+#define PCNT_THR_L_LIM_EN_U0_S  13
+/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit0's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U0  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U0_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U0_V  0x1
+#define PCNT_THR_H_LIM_EN_U0_S  12
+/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit0's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U0  (BIT(11))
+#define PCNT_THR_ZERO_EN_U0_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U0_V  0x1
+#define PCNT_THR_ZERO_EN_U0_S  11
+/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit0.*/
+#define PCNT_FILTER_EN_U0  (BIT(10))
+#define PCNT_FILTER_EN_U0_M  (BIT(10))
+#define PCNT_FILTER_EN_U0_V  0x1
+#define PCNT_FILTER_EN_U0_S  10
+/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit0.*/
+#define PCNT_FILTER_THRES_U0  0x000003FF
+#define PCNT_FILTER_THRES_U0_M  ((PCNT_FILTER_THRES_U0_V)<<(PCNT_FILTER_THRES_U0_S))
+#define PCNT_FILTER_THRES_U0_V  0x3FF
+#define PCNT_FILTER_THRES_U0_S  0
+
+#define PCNT_U0_CONF1_REG          (DR_REG_PCNT_BASE + 0x0004)
+/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit0.*/
+#define PCNT_CNT_THRES1_U0  0x0000FFFF
+#define PCNT_CNT_THRES1_U0_M  ((PCNT_CNT_THRES1_U0_V)<<(PCNT_CNT_THRES1_U0_S))
+#define PCNT_CNT_THRES1_U0_V  0xFFFF
+#define PCNT_CNT_THRES1_U0_S  16
+/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit0.*/
+#define PCNT_CNT_THRES0_U0  0x0000FFFF
+#define PCNT_CNT_THRES0_U0_M  ((PCNT_CNT_THRES0_U0_V)<<(PCNT_CNT_THRES0_U0_S))
+#define PCNT_CNT_THRES0_U0_V  0xFFFF
+#define PCNT_CNT_THRES0_U0_S  0
+
+#define PCNT_U0_CONF2_REG          (DR_REG_PCNT_BASE + 0x0008)
+/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit0.*/
+#define PCNT_CNT_L_LIM_U0  0x0000FFFF
+#define PCNT_CNT_L_LIM_U0_M  ((PCNT_CNT_L_LIM_U0_V)<<(PCNT_CNT_L_LIM_U0_S))
+#define PCNT_CNT_L_LIM_U0_V  0xFFFF
+#define PCNT_CNT_L_LIM_U0_S  16
+/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit0.*/
+#define PCNT_CNT_H_LIM_U0  0x0000FFFF
+#define PCNT_CNT_H_LIM_U0_M  ((PCNT_CNT_H_LIM_U0_V)<<(PCNT_CNT_H_LIM_U0_S))
+#define PCNT_CNT_H_LIM_U0_V  0xFFFF
+#define PCNT_CNT_H_LIM_U0_S  0
+
+#define PCNT_U1_CONF0_REG          (DR_REG_PCNT_BASE + 0x000c)
+/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U1  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U1_M  ((PCNT_CH1_LCTRL_MODE_U1_V)<<(PCNT_CH1_LCTRL_MODE_U1_S))
+#define PCNT_CH1_LCTRL_MODE_U1_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U1_S  30
+/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U1  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U1_M  ((PCNT_CH1_HCTRL_MODE_U1_V)<<(PCNT_CH1_HCTRL_MODE_U1_S))
+#define PCNT_CH1_HCTRL_MODE_U1_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U1_S  28
+/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit1. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U1  0x00000003
+#define PCNT_CH1_POS_MODE_U1_M  ((PCNT_CH1_POS_MODE_U1_V)<<(PCNT_CH1_POS_MODE_U1_S))
+#define PCNT_CH1_POS_MODE_U1_V  0x3
+#define PCNT_CH1_POS_MODE_U1_S  26
+/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit1. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U1  0x00000003
+#define PCNT_CH1_NEG_MODE_U1_M  ((PCNT_CH1_NEG_MODE_U1_V)<<(PCNT_CH1_NEG_MODE_U1_S))
+#define PCNT_CH1_NEG_MODE_U1_V  0x3
+#define PCNT_CH1_NEG_MODE_U1_S  24
+/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U1  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U1_M  ((PCNT_CH0_LCTRL_MODE_U1_V)<<(PCNT_CH0_LCTRL_MODE_U1_S))
+#define PCNT_CH0_LCTRL_MODE_U1_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U1_S  22
+/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit1. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U1  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U1_M  ((PCNT_CH0_HCTRL_MODE_U1_V)<<(PCNT_CH0_HCTRL_MODE_U1_S))
+#define PCNT_CH0_HCTRL_MODE_U1_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U1_S  20
+/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit1. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U1  0x00000003
+#define PCNT_CH0_POS_MODE_U1_M  ((PCNT_CH0_POS_MODE_U1_V)<<(PCNT_CH0_POS_MODE_U1_S))
+#define PCNT_CH0_POS_MODE_U1_V  0x3
+#define PCNT_CH0_POS_MODE_U1_S  18
+/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit1. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U1  0x00000003
+#define PCNT_CH0_NEG_MODE_U1_M  ((PCNT_CH0_NEG_MODE_U1_V)<<(PCNT_CH0_NEG_MODE_U1_S))
+#define PCNT_CH0_NEG_MODE_U1_V  0x3
+#define PCNT_CH0_NEG_MODE_U1_S  16
+/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit1's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U1  (BIT(15))
+#define PCNT_THR_THRES1_EN_U1_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U1_V  0x1
+#define PCNT_THR_THRES1_EN_U1_S  15
+/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit1's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U1  (BIT(14))
+#define PCNT_THR_THRES0_EN_U1_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U1_V  0x1
+#define PCNT_THR_THRES0_EN_U1_S  14
+/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit1's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U1  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U1_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U1_V  0x1
+#define PCNT_THR_L_LIM_EN_U1_S  13
+/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit1's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U1  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U1_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U1_V  0x1
+#define PCNT_THR_H_LIM_EN_U1_S  12
+/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit1's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U1  (BIT(11))
+#define PCNT_THR_ZERO_EN_U1_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U1_V  0x1
+#define PCNT_THR_ZERO_EN_U1_S  11
+/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit1.*/
+#define PCNT_FILTER_EN_U1  (BIT(10))
+#define PCNT_FILTER_EN_U1_M  (BIT(10))
+#define PCNT_FILTER_EN_U1_V  0x1
+#define PCNT_FILTER_EN_U1_S  10
+/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit1.*/
+#define PCNT_FILTER_THRES_U1  0x000003FF
+#define PCNT_FILTER_THRES_U1_M  ((PCNT_FILTER_THRES_U1_V)<<(PCNT_FILTER_THRES_U1_S))
+#define PCNT_FILTER_THRES_U1_V  0x3FF
+#define PCNT_FILTER_THRES_U1_S  0
+
+#define PCNT_U1_CONF1_REG          (DR_REG_PCNT_BASE + 0x0010)
+/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit1.*/
+#define PCNT_CNT_THRES1_U1  0x0000FFFF
+#define PCNT_CNT_THRES1_U1_M  ((PCNT_CNT_THRES1_U1_V)<<(PCNT_CNT_THRES1_U1_S))
+#define PCNT_CNT_THRES1_U1_V  0xFFFF
+#define PCNT_CNT_THRES1_U1_S  16
+/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit1.*/
+#define PCNT_CNT_THRES0_U1  0x0000FFFF
+#define PCNT_CNT_THRES0_U1_M  ((PCNT_CNT_THRES0_U1_V)<<(PCNT_CNT_THRES0_U1_S))
+#define PCNT_CNT_THRES0_U1_V  0xFFFF
+#define PCNT_CNT_THRES0_U1_S  0
+
+#define PCNT_U1_CONF2_REG          (DR_REG_PCNT_BASE + 0x0014)
+/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit1.*/
+#define PCNT_CNT_L_LIM_U1  0x0000FFFF
+#define PCNT_CNT_L_LIM_U1_M  ((PCNT_CNT_L_LIM_U1_V)<<(PCNT_CNT_L_LIM_U1_S))
+#define PCNT_CNT_L_LIM_U1_V  0xFFFF
+#define PCNT_CNT_L_LIM_U1_S  16
+/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit1.*/
+#define PCNT_CNT_H_LIM_U1  0x0000FFFF
+#define PCNT_CNT_H_LIM_U1_M  ((PCNT_CNT_H_LIM_U1_V)<<(PCNT_CNT_H_LIM_U1_S))
+#define PCNT_CNT_H_LIM_U1_V  0xFFFF
+#define PCNT_CNT_H_LIM_U1_S  0
+
+#define PCNT_U2_CONF0_REG          (DR_REG_PCNT_BASE + 0x0018)
+/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U2  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U2_M  ((PCNT_CH1_LCTRL_MODE_U2_V)<<(PCNT_CH1_LCTRL_MODE_U2_S))
+#define PCNT_CH1_LCTRL_MODE_U2_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U2_S  30
+/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U2  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U2_M  ((PCNT_CH1_HCTRL_MODE_U2_V)<<(PCNT_CH1_HCTRL_MODE_U2_S))
+#define PCNT_CH1_HCTRL_MODE_U2_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U2_S  28
+/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit2. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U2  0x00000003
+#define PCNT_CH1_POS_MODE_U2_M  ((PCNT_CH1_POS_MODE_U2_V)<<(PCNT_CH1_POS_MODE_U2_S))
+#define PCNT_CH1_POS_MODE_U2_V  0x3
+#define PCNT_CH1_POS_MODE_U2_S  26
+/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit2. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U2  0x00000003
+#define PCNT_CH1_NEG_MODE_U2_M  ((PCNT_CH1_NEG_MODE_U2_V)<<(PCNT_CH1_NEG_MODE_U2_S))
+#define PCNT_CH1_NEG_MODE_U2_V  0x3
+#define PCNT_CH1_NEG_MODE_U2_S  24
+/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U2  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U2_M  ((PCNT_CH0_LCTRL_MODE_U2_V)<<(PCNT_CH0_LCTRL_MODE_U2_S))
+#define PCNT_CH0_LCTRL_MODE_U2_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U2_S  22
+/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit2. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U2  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U2_M  ((PCNT_CH0_HCTRL_MODE_U2_V)<<(PCNT_CH0_HCTRL_MODE_U2_S))
+#define PCNT_CH0_HCTRL_MODE_U2_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U2_S  20
+/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit2. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U2  0x00000003
+#define PCNT_CH0_POS_MODE_U2_M  ((PCNT_CH0_POS_MODE_U2_V)<<(PCNT_CH0_POS_MODE_U2_S))
+#define PCNT_CH0_POS_MODE_U2_V  0x3
+#define PCNT_CH0_POS_MODE_U2_S  18
+/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit2. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U2  0x00000003
+#define PCNT_CH0_NEG_MODE_U2_M  ((PCNT_CH0_NEG_MODE_U2_V)<<(PCNT_CH0_NEG_MODE_U2_S))
+#define PCNT_CH0_NEG_MODE_U2_V  0x3
+#define PCNT_CH0_NEG_MODE_U2_S  16
+/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit2's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U2  (BIT(15))
+#define PCNT_THR_THRES1_EN_U2_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U2_V  0x1
+#define PCNT_THR_THRES1_EN_U2_S  15
+/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit2's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U2  (BIT(14))
+#define PCNT_THR_THRES0_EN_U2_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U2_V  0x1
+#define PCNT_THR_THRES0_EN_U2_S  14
+/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit2's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U2  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U2_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U2_V  0x1
+#define PCNT_THR_L_LIM_EN_U2_S  13
+/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit2's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U2  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U2_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U2_V  0x1
+#define PCNT_THR_H_LIM_EN_U2_S  12
+/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit2's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U2  (BIT(11))
+#define PCNT_THR_ZERO_EN_U2_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U2_V  0x1
+#define PCNT_THR_ZERO_EN_U2_S  11
+/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit2.*/
+#define PCNT_FILTER_EN_U2  (BIT(10))
+#define PCNT_FILTER_EN_U2_M  (BIT(10))
+#define PCNT_FILTER_EN_U2_V  0x1
+#define PCNT_FILTER_EN_U2_S  10
+/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit2.*/
+#define PCNT_FILTER_THRES_U2  0x000003FF
+#define PCNT_FILTER_THRES_U2_M  ((PCNT_FILTER_THRES_U2_V)<<(PCNT_FILTER_THRES_U2_S))
+#define PCNT_FILTER_THRES_U2_V  0x3FF
+#define PCNT_FILTER_THRES_U2_S  0
+
+#define PCNT_U2_CONF1_REG          (DR_REG_PCNT_BASE + 0x001c)
+/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit2.*/
+#define PCNT_CNT_THRES1_U2  0x0000FFFF
+#define PCNT_CNT_THRES1_U2_M  ((PCNT_CNT_THRES1_U2_V)<<(PCNT_CNT_THRES1_U2_S))
+#define PCNT_CNT_THRES1_U2_V  0xFFFF
+#define PCNT_CNT_THRES1_U2_S  16
+/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit2.*/
+#define PCNT_CNT_THRES0_U2  0x0000FFFF
+#define PCNT_CNT_THRES0_U2_M  ((PCNT_CNT_THRES0_U2_V)<<(PCNT_CNT_THRES0_U2_S))
+#define PCNT_CNT_THRES0_U2_V  0xFFFF
+#define PCNT_CNT_THRES0_U2_S  0
+
+#define PCNT_U2_CONF2_REG          (DR_REG_PCNT_BASE + 0x0020)
+/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit2.*/
+#define PCNT_CNT_L_LIM_U2  0x0000FFFF
+#define PCNT_CNT_L_LIM_U2_M  ((PCNT_CNT_L_LIM_U2_V)<<(PCNT_CNT_L_LIM_U2_S))
+#define PCNT_CNT_L_LIM_U2_V  0xFFFF
+#define PCNT_CNT_L_LIM_U2_S  16
+/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit2.*/
+#define PCNT_CNT_H_LIM_U2  0x0000FFFF
+#define PCNT_CNT_H_LIM_U2_M  ((PCNT_CNT_H_LIM_U2_V)<<(PCNT_CNT_H_LIM_U2_S))
+#define PCNT_CNT_H_LIM_U2_V  0xFFFF
+#define PCNT_CNT_H_LIM_U2_S  0
+
+#define PCNT_U3_CONF0_REG          (DR_REG_PCNT_BASE + 0x0024)
+/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U3  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U3_M  ((PCNT_CH1_LCTRL_MODE_U3_V)<<(PCNT_CH1_LCTRL_MODE_U3_S))
+#define PCNT_CH1_LCTRL_MODE_U3_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U3_S  30
+/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U3  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U3_M  ((PCNT_CH1_HCTRL_MODE_U3_V)<<(PCNT_CH1_HCTRL_MODE_U3_S))
+#define PCNT_CH1_HCTRL_MODE_U3_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U3_S  28
+/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit3. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U3  0x00000003
+#define PCNT_CH1_POS_MODE_U3_M  ((PCNT_CH1_POS_MODE_U3_V)<<(PCNT_CH1_POS_MODE_U3_S))
+#define PCNT_CH1_POS_MODE_U3_V  0x3
+#define PCNT_CH1_POS_MODE_U3_S  26
+/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit3. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U3  0x00000003
+#define PCNT_CH1_NEG_MODE_U3_M  ((PCNT_CH1_NEG_MODE_U3_V)<<(PCNT_CH1_NEG_MODE_U3_S))
+#define PCNT_CH1_NEG_MODE_U3_V  0x3
+#define PCNT_CH1_NEG_MODE_U3_S  24
+/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U3  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U3_M  ((PCNT_CH0_LCTRL_MODE_U3_V)<<(PCNT_CH0_LCTRL_MODE_U3_S))
+#define PCNT_CH0_LCTRL_MODE_U3_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U3_S  22
+/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit3. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U3  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U3_M  ((PCNT_CH0_HCTRL_MODE_U3_V)<<(PCNT_CH0_HCTRL_MODE_U3_S))
+#define PCNT_CH0_HCTRL_MODE_U3_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U3_S  20
+/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit3. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U3  0x00000003
+#define PCNT_CH0_POS_MODE_U3_M  ((PCNT_CH0_POS_MODE_U3_V)<<(PCNT_CH0_POS_MODE_U3_S))
+#define PCNT_CH0_POS_MODE_U3_V  0x3
+#define PCNT_CH0_POS_MODE_U3_S  18
+/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit3. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U3  0x00000003
+#define PCNT_CH0_NEG_MODE_U3_M  ((PCNT_CH0_NEG_MODE_U3_V)<<(PCNT_CH0_NEG_MODE_U3_S))
+#define PCNT_CH0_NEG_MODE_U3_V  0x3
+#define PCNT_CH0_NEG_MODE_U3_S  16
+/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit3's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U3  (BIT(15))
+#define PCNT_THR_THRES1_EN_U3_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U3_V  0x1
+#define PCNT_THR_THRES1_EN_U3_S  15
+/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit3's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U3  (BIT(14))
+#define PCNT_THR_THRES0_EN_U3_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U3_V  0x1
+#define PCNT_THR_THRES0_EN_U3_S  14
+/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit3's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U3  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U3_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U3_V  0x1
+#define PCNT_THR_L_LIM_EN_U3_S  13
+/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit3's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U3  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U3_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U3_V  0x1
+#define PCNT_THR_H_LIM_EN_U3_S  12
+/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit3's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U3  (BIT(11))
+#define PCNT_THR_ZERO_EN_U3_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U3_V  0x1
+#define PCNT_THR_ZERO_EN_U3_S  11
+/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit3.*/
+#define PCNT_FILTER_EN_U3  (BIT(10))
+#define PCNT_FILTER_EN_U3_M  (BIT(10))
+#define PCNT_FILTER_EN_U3_V  0x1
+#define PCNT_FILTER_EN_U3_S  10
+/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit3.*/
+#define PCNT_FILTER_THRES_U3  0x000003FF
+#define PCNT_FILTER_THRES_U3_M  ((PCNT_FILTER_THRES_U3_V)<<(PCNT_FILTER_THRES_U3_S))
+#define PCNT_FILTER_THRES_U3_V  0x3FF
+#define PCNT_FILTER_THRES_U3_S  0
+
+#define PCNT_U3_CONF1_REG          (DR_REG_PCNT_BASE + 0x0028)
+/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit3.*/
+#define PCNT_CNT_THRES1_U3  0x0000FFFF
+#define PCNT_CNT_THRES1_U3_M  ((PCNT_CNT_THRES1_U3_V)<<(PCNT_CNT_THRES1_U3_S))
+#define PCNT_CNT_THRES1_U3_V  0xFFFF
+#define PCNT_CNT_THRES1_U3_S  16
+/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit3.*/
+#define PCNT_CNT_THRES0_U3  0x0000FFFF
+#define PCNT_CNT_THRES0_U3_M  ((PCNT_CNT_THRES0_U3_V)<<(PCNT_CNT_THRES0_U3_S))
+#define PCNT_CNT_THRES0_U3_V  0xFFFF
+#define PCNT_CNT_THRES0_U3_S  0
+
+#define PCNT_U3_CONF2_REG          (DR_REG_PCNT_BASE + 0x002c)
+/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit3.*/
+#define PCNT_CNT_L_LIM_U3  0x0000FFFF
+#define PCNT_CNT_L_LIM_U3_M  ((PCNT_CNT_L_LIM_U3_V)<<(PCNT_CNT_L_LIM_U3_S))
+#define PCNT_CNT_L_LIM_U3_V  0xFFFF
+#define PCNT_CNT_L_LIM_U3_S  16
+/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit3.*/
+#define PCNT_CNT_H_LIM_U3  0x0000FFFF
+#define PCNT_CNT_H_LIM_U3_M  ((PCNT_CNT_H_LIM_U3_V)<<(PCNT_CNT_H_LIM_U3_S))
+#define PCNT_CNT_H_LIM_U3_V  0xFFFF
+#define PCNT_CNT_H_LIM_U3_S  0
+
+#define PCNT_U4_CONF0_REG          (DR_REG_PCNT_BASE + 0x0030)
+/* PCNT_CH1_LCTRL_MODE_U4 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U4  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U4_M  ((PCNT_CH1_LCTRL_MODE_U4_V)<<(PCNT_CH1_LCTRL_MODE_U4_S))
+#define PCNT_CH1_LCTRL_MODE_U4_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U4_S  30
+/* PCNT_CH1_HCTRL_MODE_U4 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U4  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U4_M  ((PCNT_CH1_HCTRL_MODE_U4_V)<<(PCNT_CH1_HCTRL_MODE_U4_S))
+#define PCNT_CH1_HCTRL_MODE_U4_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U4_S  28
+/* PCNT_CH1_POS_MODE_U4 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit4. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U4  0x00000003
+#define PCNT_CH1_POS_MODE_U4_M  ((PCNT_CH1_POS_MODE_U4_V)<<(PCNT_CH1_POS_MODE_U4_S))
+#define PCNT_CH1_POS_MODE_U4_V  0x3
+#define PCNT_CH1_POS_MODE_U4_S  26
+/* PCNT_CH1_NEG_MODE_U4 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit4. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U4  0x00000003
+#define PCNT_CH1_NEG_MODE_U4_M  ((PCNT_CH1_NEG_MODE_U4_V)<<(PCNT_CH1_NEG_MODE_U4_S))
+#define PCNT_CH1_NEG_MODE_U4_V  0x3
+#define PCNT_CH1_NEG_MODE_U4_S  24
+/* PCNT_CH0_LCTRL_MODE_U4 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U4  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U4_M  ((PCNT_CH0_LCTRL_MODE_U4_V)<<(PCNT_CH0_LCTRL_MODE_U4_S))
+#define PCNT_CH0_LCTRL_MODE_U4_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U4_S  22
+/* PCNT_CH0_HCTRL_MODE_U4 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit4. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U4  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U4_M  ((PCNT_CH0_HCTRL_MODE_U4_V)<<(PCNT_CH0_HCTRL_MODE_U4_S))
+#define PCNT_CH0_HCTRL_MODE_U4_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U4_S  20
+/* PCNT_CH0_POS_MODE_U4 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit4. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U4  0x00000003
+#define PCNT_CH0_POS_MODE_U4_M  ((PCNT_CH0_POS_MODE_U4_V)<<(PCNT_CH0_POS_MODE_U4_S))
+#define PCNT_CH0_POS_MODE_U4_V  0x3
+#define PCNT_CH0_POS_MODE_U4_S  18
+/* PCNT_CH0_NEG_MODE_U4 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit4. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U4  0x00000003
+#define PCNT_CH0_NEG_MODE_U4_M  ((PCNT_CH0_NEG_MODE_U4_V)<<(PCNT_CH0_NEG_MODE_U4_S))
+#define PCNT_CH0_NEG_MODE_U4_V  0x3
+#define PCNT_CH0_NEG_MODE_U4_S  16
+/* PCNT_THR_THRES1_EN_U4 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit4's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U4  (BIT(15))
+#define PCNT_THR_THRES1_EN_U4_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U4_V  0x1
+#define PCNT_THR_THRES1_EN_U4_S  15
+/* PCNT_THR_THRES0_EN_U4 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit4's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U4  (BIT(14))
+#define PCNT_THR_THRES0_EN_U4_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U4_V  0x1
+#define PCNT_THR_THRES0_EN_U4_S  14
+/* PCNT_THR_L_LIM_EN_U4 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit4's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U4  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U4_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U4_V  0x1
+#define PCNT_THR_L_LIM_EN_U4_S  13
+/* PCNT_THR_H_LIM_EN_U4 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit4's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U4  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U4_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U4_V  0x1
+#define PCNT_THR_H_LIM_EN_U4_S  12
+/* PCNT_THR_ZERO_EN_U4 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit4's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U4  (BIT(11))
+#define PCNT_THR_ZERO_EN_U4_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U4_V  0x1
+#define PCNT_THR_ZERO_EN_U4_S  11
+/* PCNT_FILTER_EN_U4 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit4.*/
+#define PCNT_FILTER_EN_U4  (BIT(10))
+#define PCNT_FILTER_EN_U4_M  (BIT(10))
+#define PCNT_FILTER_EN_U4_V  0x1
+#define PCNT_FILTER_EN_U4_S  10
+/* PCNT_FILTER_THRES_U4 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit4.*/
+#define PCNT_FILTER_THRES_U4  0x000003FF
+#define PCNT_FILTER_THRES_U4_M  ((PCNT_FILTER_THRES_U4_V)<<(PCNT_FILTER_THRES_U4_S))
+#define PCNT_FILTER_THRES_U4_V  0x3FF
+#define PCNT_FILTER_THRES_U4_S  0
+
+#define PCNT_U4_CONF1_REG          (DR_REG_PCNT_BASE + 0x0034)
+/* PCNT_CNT_THRES1_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit4.*/
+#define PCNT_CNT_THRES1_U4  0x0000FFFF
+#define PCNT_CNT_THRES1_U4_M  ((PCNT_CNT_THRES1_U4_V)<<(PCNT_CNT_THRES1_U4_S))
+#define PCNT_CNT_THRES1_U4_V  0xFFFF
+#define PCNT_CNT_THRES1_U4_S  16
+/* PCNT_CNT_THRES0_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit4.*/
+#define PCNT_CNT_THRES0_U4  0x0000FFFF
+#define PCNT_CNT_THRES0_U4_M  ((PCNT_CNT_THRES0_U4_V)<<(PCNT_CNT_THRES0_U4_S))
+#define PCNT_CNT_THRES0_U4_V  0xFFFF
+#define PCNT_CNT_THRES0_U4_S  0
+
+#define PCNT_U4_CONF2_REG          (DR_REG_PCNT_BASE + 0x0038)
+/* PCNT_CNT_L_LIM_U4 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit4.*/
+#define PCNT_CNT_L_LIM_U4  0x0000FFFF
+#define PCNT_CNT_L_LIM_U4_M  ((PCNT_CNT_L_LIM_U4_V)<<(PCNT_CNT_L_LIM_U4_S))
+#define PCNT_CNT_L_LIM_U4_V  0xFFFF
+#define PCNT_CNT_L_LIM_U4_S  16
+/* PCNT_CNT_H_LIM_U4 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit4.*/
+#define PCNT_CNT_H_LIM_U4  0x0000FFFF
+#define PCNT_CNT_H_LIM_U4_M  ((PCNT_CNT_H_LIM_U4_V)<<(PCNT_CNT_H_LIM_U4_S))
+#define PCNT_CNT_H_LIM_U4_V  0xFFFF
+#define PCNT_CNT_H_LIM_U4_S  0
+
+#define PCNT_U5_CONF0_REG          (DR_REG_PCNT_BASE + 0x003c)
+/* PCNT_CH1_LCTRL_MODE_U5 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U5  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U5_M  ((PCNT_CH1_LCTRL_MODE_U5_V)<<(PCNT_CH1_LCTRL_MODE_U5_S))
+#define PCNT_CH1_LCTRL_MODE_U5_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U5_S  30
+/* PCNT_CH1_HCTRL_MODE_U5 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U5  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U5_M  ((PCNT_CH1_HCTRL_MODE_U5_V)<<(PCNT_CH1_HCTRL_MODE_U5_S))
+#define PCNT_CH1_HCTRL_MODE_U5_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U5_S  28
+/* PCNT_CH1_POS_MODE_U5 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit5. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U5  0x00000003
+#define PCNT_CH1_POS_MODE_U5_M  ((PCNT_CH1_POS_MODE_U5_V)<<(PCNT_CH1_POS_MODE_U5_S))
+#define PCNT_CH1_POS_MODE_U5_V  0x3
+#define PCNT_CH1_POS_MODE_U5_S  26
+/* PCNT_CH1_NEG_MODE_U5 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit5. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U5  0x00000003
+#define PCNT_CH1_NEG_MODE_U5_M  ((PCNT_CH1_NEG_MODE_U5_V)<<(PCNT_CH1_NEG_MODE_U5_S))
+#define PCNT_CH1_NEG_MODE_U5_V  0x3
+#define PCNT_CH1_NEG_MODE_U5_S  24
+/* PCNT_CH0_LCTRL_MODE_U5 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U5  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U5_M  ((PCNT_CH0_LCTRL_MODE_U5_V)<<(PCNT_CH0_LCTRL_MODE_U5_S))
+#define PCNT_CH0_LCTRL_MODE_U5_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U5_S  22
+/* PCNT_CH0_HCTRL_MODE_U5 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit5. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U5  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U5_M  ((PCNT_CH0_HCTRL_MODE_U5_V)<<(PCNT_CH0_HCTRL_MODE_U5_S))
+#define PCNT_CH0_HCTRL_MODE_U5_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U5_S  20
+/* PCNT_CH0_POS_MODE_U5 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit5. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U5  0x00000003
+#define PCNT_CH0_POS_MODE_U5_M  ((PCNT_CH0_POS_MODE_U5_V)<<(PCNT_CH0_POS_MODE_U5_S))
+#define PCNT_CH0_POS_MODE_U5_V  0x3
+#define PCNT_CH0_POS_MODE_U5_S  18
+/* PCNT_CH0_NEG_MODE_U5 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit5. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U5  0x00000003
+#define PCNT_CH0_NEG_MODE_U5_M  ((PCNT_CH0_NEG_MODE_U5_V)<<(PCNT_CH0_NEG_MODE_U5_S))
+#define PCNT_CH0_NEG_MODE_U5_V  0x3
+#define PCNT_CH0_NEG_MODE_U5_S  16
+/* PCNT_THR_THRES1_EN_U5 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit5's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U5  (BIT(15))
+#define PCNT_THR_THRES1_EN_U5_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U5_V  0x1
+#define PCNT_THR_THRES1_EN_U5_S  15
+/* PCNT_THR_THRES0_EN_U5 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit5's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U5  (BIT(14))
+#define PCNT_THR_THRES0_EN_U5_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U5_V  0x1
+#define PCNT_THR_THRES0_EN_U5_S  14
+/* PCNT_THR_L_LIM_EN_U5 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit5's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U5  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U5_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U5_V  0x1
+#define PCNT_THR_L_LIM_EN_U5_S  13
+/* PCNT_THR_H_LIM_EN_U5 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit5's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U5  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U5_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U5_V  0x1
+#define PCNT_THR_H_LIM_EN_U5_S  12
+/* PCNT_THR_ZERO_EN_U5 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit5's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U5  (BIT(11))
+#define PCNT_THR_ZERO_EN_U5_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U5_V  0x1
+#define PCNT_THR_ZERO_EN_U5_S  11
+/* PCNT_FILTER_EN_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit5.*/
+#define PCNT_FILTER_EN_U5  (BIT(10))
+#define PCNT_FILTER_EN_U5_M  (BIT(10))
+#define PCNT_FILTER_EN_U5_V  0x1
+#define PCNT_FILTER_EN_U5_S  10
+/* PCNT_FILTER_THRES_U5 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit5.*/
+#define PCNT_FILTER_THRES_U5  0x000003FF
+#define PCNT_FILTER_THRES_U5_M  ((PCNT_FILTER_THRES_U5_V)<<(PCNT_FILTER_THRES_U5_S))
+#define PCNT_FILTER_THRES_U5_V  0x3FF
+#define PCNT_FILTER_THRES_U5_S  0
+
+#define PCNT_U5_CONF1_REG          (DR_REG_PCNT_BASE + 0x0040)
+/* PCNT_CNT_THRES1_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit5.*/
+#define PCNT_CNT_THRES1_U5  0x0000FFFF
+#define PCNT_CNT_THRES1_U5_M  ((PCNT_CNT_THRES1_U5_V)<<(PCNT_CNT_THRES1_U5_S))
+#define PCNT_CNT_THRES1_U5_V  0xFFFF
+#define PCNT_CNT_THRES1_U5_S  16
+/* PCNT_CNT_THRES0_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit5.*/
+#define PCNT_CNT_THRES0_U5  0x0000FFFF
+#define PCNT_CNT_THRES0_U5_M  ((PCNT_CNT_THRES0_U5_V)<<(PCNT_CNT_THRES0_U5_S))
+#define PCNT_CNT_THRES0_U5_V  0xFFFF
+#define PCNT_CNT_THRES0_U5_S  0
+
+#define PCNT_U5_CONF2_REG          (DR_REG_PCNT_BASE + 0x0044)
+/* PCNT_CNT_L_LIM_U5 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit5.*/
+#define PCNT_CNT_L_LIM_U5  0x0000FFFF
+#define PCNT_CNT_L_LIM_U5_M  ((PCNT_CNT_L_LIM_U5_V)<<(PCNT_CNT_L_LIM_U5_S))
+#define PCNT_CNT_L_LIM_U5_V  0xFFFF
+#define PCNT_CNT_L_LIM_U5_S  16
+/* PCNT_CNT_H_LIM_U5 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit5.*/
+#define PCNT_CNT_H_LIM_U5  0x0000FFFF
+#define PCNT_CNT_H_LIM_U5_M  ((PCNT_CNT_H_LIM_U5_V)<<(PCNT_CNT_H_LIM_U5_S))
+#define PCNT_CNT_H_LIM_U5_V  0xFFFF
+#define PCNT_CNT_H_LIM_U5_S  0
+
+#define PCNT_U6_CONF0_REG          (DR_REG_PCNT_BASE + 0x0048)
+/* PCNT_CH1_LCTRL_MODE_U6 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U6  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U6_M  ((PCNT_CH1_LCTRL_MODE_U6_V)<<(PCNT_CH1_LCTRL_MODE_U6_S))
+#define PCNT_CH1_LCTRL_MODE_U6_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U6_S  30
+/* PCNT_CH1_HCTRL_MODE_U6 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U6  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U6_M  ((PCNT_CH1_HCTRL_MODE_U6_V)<<(PCNT_CH1_HCTRL_MODE_U6_S))
+#define PCNT_CH1_HCTRL_MODE_U6_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U6_S  28
+/* PCNT_CH1_POS_MODE_U6 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit6. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U6  0x00000003
+#define PCNT_CH1_POS_MODE_U6_M  ((PCNT_CH1_POS_MODE_U6_V)<<(PCNT_CH1_POS_MODE_U6_S))
+#define PCNT_CH1_POS_MODE_U6_V  0x3
+#define PCNT_CH1_POS_MODE_U6_S  26
+/* PCNT_CH1_NEG_MODE_U6 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit6. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U6  0x00000003
+#define PCNT_CH1_NEG_MODE_U6_M  ((PCNT_CH1_NEG_MODE_U6_V)<<(PCNT_CH1_NEG_MODE_U6_S))
+#define PCNT_CH1_NEG_MODE_U6_V  0x3
+#define PCNT_CH1_NEG_MODE_U6_S  24
+/* PCNT_CH0_LCTRL_MODE_U6 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U6  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U6_M  ((PCNT_CH0_LCTRL_MODE_U6_V)<<(PCNT_CH0_LCTRL_MODE_U6_S))
+#define PCNT_CH0_LCTRL_MODE_U6_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U6_S  22
+/* PCNT_CH0_HCTRL_MODE_U6 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit6. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U6  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U6_M  ((PCNT_CH0_HCTRL_MODE_U6_V)<<(PCNT_CH0_HCTRL_MODE_U6_S))
+#define PCNT_CH0_HCTRL_MODE_U6_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U6_S  20
+/* PCNT_CH0_POS_MODE_U6 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit6. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U6  0x00000003
+#define PCNT_CH0_POS_MODE_U6_M  ((PCNT_CH0_POS_MODE_U6_V)<<(PCNT_CH0_POS_MODE_U6_S))
+#define PCNT_CH0_POS_MODE_U6_V  0x3
+#define PCNT_CH0_POS_MODE_U6_S  18
+/* PCNT_CH0_NEG_MODE_U6 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit6. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U6  0x00000003
+#define PCNT_CH0_NEG_MODE_U6_M  ((PCNT_CH0_NEG_MODE_U6_V)<<(PCNT_CH0_NEG_MODE_U6_S))
+#define PCNT_CH0_NEG_MODE_U6_V  0x3
+#define PCNT_CH0_NEG_MODE_U6_S  16
+/* PCNT_THR_THRES1_EN_U6 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit6's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U6  (BIT(15))
+#define PCNT_THR_THRES1_EN_U6_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U6_V  0x1
+#define PCNT_THR_THRES1_EN_U6_S  15
+/* PCNT_THR_THRES0_EN_U6 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit6's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U6  (BIT(14))
+#define PCNT_THR_THRES0_EN_U6_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U6_V  0x1
+#define PCNT_THR_THRES0_EN_U6_S  14
+/* PCNT_THR_L_LIM_EN_U6 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit6's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U6  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U6_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U6_V  0x1
+#define PCNT_THR_L_LIM_EN_U6_S  13
+/* PCNT_THR_H_LIM_EN_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit6's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U6  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U6_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U6_V  0x1
+#define PCNT_THR_H_LIM_EN_U6_S  12
+/* PCNT_THR_ZERO_EN_U6 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit6's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U6  (BIT(11))
+#define PCNT_THR_ZERO_EN_U6_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U6_V  0x1
+#define PCNT_THR_ZERO_EN_U6_S  11
+/* PCNT_FILTER_EN_U6 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit6.*/
+#define PCNT_FILTER_EN_U6  (BIT(10))
+#define PCNT_FILTER_EN_U6_M  (BIT(10))
+#define PCNT_FILTER_EN_U6_V  0x1
+#define PCNT_FILTER_EN_U6_S  10
+/* PCNT_FILTER_THRES_U6 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit6.*/
+#define PCNT_FILTER_THRES_U6  0x000003FF
+#define PCNT_FILTER_THRES_U6_M  ((PCNT_FILTER_THRES_U6_V)<<(PCNT_FILTER_THRES_U6_S))
+#define PCNT_FILTER_THRES_U6_V  0x3FF
+#define PCNT_FILTER_THRES_U6_S  0
+
+#define PCNT_U6_CONF1_REG          (DR_REG_PCNT_BASE + 0x004c)
+/* PCNT_CNT_THRES1_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit6.*/
+#define PCNT_CNT_THRES1_U6  0x0000FFFF
+#define PCNT_CNT_THRES1_U6_M  ((PCNT_CNT_THRES1_U6_V)<<(PCNT_CNT_THRES1_U6_S))
+#define PCNT_CNT_THRES1_U6_V  0xFFFF
+#define PCNT_CNT_THRES1_U6_S  16
+/* PCNT_CNT_THRES0_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit6.*/
+#define PCNT_CNT_THRES0_U6  0x0000FFFF
+#define PCNT_CNT_THRES0_U6_M  ((PCNT_CNT_THRES0_U6_V)<<(PCNT_CNT_THRES0_U6_S))
+#define PCNT_CNT_THRES0_U6_V  0xFFFF
+#define PCNT_CNT_THRES0_U6_S  0
+
+#define PCNT_U6_CONF2_REG          (DR_REG_PCNT_BASE + 0x0050)
+/* PCNT_CNT_L_LIM_U6 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit6.*/
+#define PCNT_CNT_L_LIM_U6  0x0000FFFF
+#define PCNT_CNT_L_LIM_U6_M  ((PCNT_CNT_L_LIM_U6_V)<<(PCNT_CNT_L_LIM_U6_S))
+#define PCNT_CNT_L_LIM_U6_V  0xFFFF
+#define PCNT_CNT_L_LIM_U6_S  16
+/* PCNT_CNT_H_LIM_U6 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit6.*/
+#define PCNT_CNT_H_LIM_U6  0x0000FFFF
+#define PCNT_CNT_H_LIM_U6_M  ((PCNT_CNT_H_LIM_U6_V)<<(PCNT_CNT_H_LIM_U6_S))
+#define PCNT_CNT_H_LIM_U6_V  0xFFFF
+#define PCNT_CNT_H_LIM_U6_S  0
+
+#define PCNT_U7_CONF0_REG          (DR_REG_PCNT_BASE + 0x0054)
+/* PCNT_CH1_LCTRL_MODE_U7 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's low control
+ signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_LCTRL_MODE_U7  0x00000003
+#define PCNT_CH1_LCTRL_MODE_U7_M  ((PCNT_CH1_LCTRL_MODE_U7_V)<<(PCNT_CH1_LCTRL_MODE_U7_S))
+#define PCNT_CH1_LCTRL_MODE_U7_V  0x3
+#define PCNT_CH1_LCTRL_MODE_U7_S  30
+/* PCNT_CH1_HCTRL_MODE_U7 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's high
+ control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH1_HCTRL_MODE_U7  0x00000003
+#define PCNT_CH1_HCTRL_MODE_U7_M  ((PCNT_CH1_HCTRL_MODE_U7_V)<<(PCNT_CH1_HCTRL_MODE_U7_S))
+#define PCNT_CH1_HCTRL_MODE_U7_V  0x3
+#define PCNT_CH1_HCTRL_MODE_U7_S  28
+/* PCNT_CH1_POS_MODE_U7 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ posedge signal for unit7. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH1_POS_MODE_U7  0x00000003
+#define PCNT_CH1_POS_MODE_U7_M  ((PCNT_CH1_POS_MODE_U7_V)<<(PCNT_CH1_POS_MODE_U7_S))
+#define PCNT_CH1_POS_MODE_U7_V  0x3
+#define PCNT_CH1_POS_MODE_U7_S  26
+/* PCNT_CH1_NEG_MODE_U7 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel1's input
+ negedge signal for unit7. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH1_NEG_MODE_U7  0x00000003
+#define PCNT_CH1_NEG_MODE_U7_M  ((PCNT_CH1_NEG_MODE_U7_V)<<(PCNT_CH1_NEG_MODE_U7_S))
+#define PCNT_CH1_NEG_MODE_U7_V  0x3
+#define PCNT_CH1_NEG_MODE_U7_S  24
+/* PCNT_CH0_LCTRL_MODE_U7 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's low control
+ signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_LCTRL_MODE_U7  0x00000003
+#define PCNT_CH0_LCTRL_MODE_U7_M  ((PCNT_CH0_LCTRL_MODE_U7_V)<<(PCNT_CH0_LCTRL_MODE_U7_S))
+#define PCNT_CH0_LCTRL_MODE_U7_V  0x3
+#define PCNT_CH0_LCTRL_MODE_U7_S  22
+/* PCNT_CH0_HCTRL_MODE_U7 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's high
+ control signal for unit7. 2'd0:increase when control signal is low   2'd1: decrease when control signal is high   others:forbidden*/
+#define PCNT_CH0_HCTRL_MODE_U7  0x00000003
+#define PCNT_CH0_HCTRL_MODE_U7_M  ((PCNT_CH0_HCTRL_MODE_U7_V)<<(PCNT_CH0_HCTRL_MODE_U7_S))
+#define PCNT_CH0_HCTRL_MODE_U7_V  0x3
+#define PCNT_CH0_HCTRL_MODE_U7_S  20
+/* PCNT_CH0_POS_MODE_U7 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ posedge signal for unit7. 2'd1: increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+#define PCNT_CH0_POS_MODE_U7  0x00000003
+#define PCNT_CH0_POS_MODE_U7_M  ((PCNT_CH0_POS_MODE_U7_V)<<(PCNT_CH0_POS_MODE_U7_S))
+#define PCNT_CH0_POS_MODE_U7_V  0x3
+#define PCNT_CH0_POS_MODE_U7_S  18
+/* PCNT_CH0_NEG_MODE_U7 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: This register is used to control the mode of channel0's input
+ negedge signal for unit7. 2'd1: increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+#define PCNT_CH0_NEG_MODE_U7  0x00000003
+#define PCNT_CH0_NEG_MODE_U7_M  ((PCNT_CH0_NEG_MODE_U7_V)<<(PCNT_CH0_NEG_MODE_U7_S))
+#define PCNT_CH0_NEG_MODE_U7_V  0x3
+#define PCNT_CH0_NEG_MODE_U7_S  16
+/* PCNT_THR_THRES1_EN_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: This is the enable bit for  comparing  unit7's count with thres1 value .*/
+#define PCNT_THR_THRES1_EN_U7  (BIT(15))
+#define PCNT_THR_THRES1_EN_U7_M  (BIT(15))
+#define PCNT_THR_THRES1_EN_U7_V  0x1
+#define PCNT_THR_THRES1_EN_U7_S  15
+/* PCNT_THR_THRES0_EN_U7 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: This is the enable bit for comparing unit7's count with  thres0 value.*/
+#define PCNT_THR_THRES0_EN_U7  (BIT(14))
+#define PCNT_THR_THRES0_EN_U7_M  (BIT(14))
+#define PCNT_THR_THRES0_EN_U7_V  0x1
+#define PCNT_THR_THRES0_EN_U7_S  14
+/* PCNT_THR_L_LIM_EN_U7 : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit7's count with thr_l_lim  value.*/
+#define PCNT_THR_L_LIM_EN_U7  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U7_M  (BIT(13))
+#define PCNT_THR_L_LIM_EN_U7_V  0x1
+#define PCNT_THR_L_LIM_EN_U7_S  13
+/* PCNT_THR_H_LIM_EN_U7 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: This is the enable bit for  comparing unit7's count with thr_h_lim value.*/
+#define PCNT_THR_H_LIM_EN_U7  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U7_M  (BIT(12))
+#define PCNT_THR_H_LIM_EN_U7_V  0x1
+#define PCNT_THR_H_LIM_EN_U7_S  12
+/* PCNT_THR_ZERO_EN_U7 : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: This is the enable bit for comparing unit7's count with 0 value.*/
+#define PCNT_THR_ZERO_EN_U7  (BIT(11))
+#define PCNT_THR_ZERO_EN_U7_M  (BIT(11))
+#define PCNT_THR_ZERO_EN_U7_V  0x1
+#define PCNT_THR_ZERO_EN_U7_S  11
+/* PCNT_FILTER_EN_U7 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: This is the enable bit for filtering input signals for unit7.*/
+#define PCNT_FILTER_EN_U7  (BIT(10))
+#define PCNT_FILTER_EN_U7_M  (BIT(10))
+#define PCNT_FILTER_EN_U7_V  0x1
+#define PCNT_FILTER_EN_U7_S  10
+/* PCNT_FILTER_THRES_U7 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
+/*description: This register is used to filter pluse whose width is smaller
+ than this value for unit7.*/
+#define PCNT_FILTER_THRES_U7  0x000003FF
+#define PCNT_FILTER_THRES_U7_M  ((PCNT_FILTER_THRES_U7_V)<<(PCNT_FILTER_THRES_U7_S))
+#define PCNT_FILTER_THRES_U7_V  0x3FF
+#define PCNT_FILTER_THRES_U7_S  0
+
+#define PCNT_U7_CONF1_REG          (DR_REG_PCNT_BASE + 0x0058)
+/* PCNT_CNT_THRES1_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to configure  thres1 value for unit7.*/
+#define PCNT_CNT_THRES1_U7  0x0000FFFF
+#define PCNT_CNT_THRES1_U7_M  ((PCNT_CNT_THRES1_U7_V)<<(PCNT_CNT_THRES1_U7_S))
+#define PCNT_CNT_THRES1_U7_V  0xFFFF
+#define PCNT_CNT_THRES1_U7_S  16
+/* PCNT_CNT_THRES0_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thres0 value for unit7.*/
+#define PCNT_CNT_THRES0_U7  0x0000FFFF
+#define PCNT_CNT_THRES0_U7_M  ((PCNT_CNT_THRES0_U7_V)<<(PCNT_CNT_THRES0_U7_S))
+#define PCNT_CNT_THRES0_U7_V  0xFFFF
+#define PCNT_CNT_THRES0_U7_S  0
+
+#define PCNT_U7_CONF2_REG          (DR_REG_PCNT_BASE + 0x005c)
+/* PCNT_CNT_L_LIM_U7 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
+/*description: This register is used to confiugre thr_l_lim value for unit7.*/
+#define PCNT_CNT_L_LIM_U7  0x0000FFFF
+#define PCNT_CNT_L_LIM_U7_M  ((PCNT_CNT_L_LIM_U7_V)<<(PCNT_CNT_L_LIM_U7_S))
+#define PCNT_CNT_L_LIM_U7_V  0xFFFF
+#define PCNT_CNT_L_LIM_U7_S  16
+/* PCNT_CNT_H_LIM_U7 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
+/*description: This register is used to configure thr_h_lim value for unit7.*/
+#define PCNT_CNT_H_LIM_U7  0x0000FFFF
+#define PCNT_CNT_H_LIM_U7_M  ((PCNT_CNT_H_LIM_U7_V)<<(PCNT_CNT_H_LIM_U7_S))
+#define PCNT_CNT_H_LIM_U7_V  0xFFFF
+#define PCNT_CNT_H_LIM_U7_S  0
+
+#define PCNT_U0_CNT_REG          (DR_REG_PCNT_BASE + 0x0060)
+/* PCNT_PULSE_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U0  0x0000FFFF
+#define PCNT_PULSE_CNT_U0_M  ((PCNT_PULSE_CNT_U0_V)<<(PCNT_PULSE_CNT_U0_S))
+#define PCNT_PULSE_CNT_U0_V  0xFFFF
+#define PCNT_PULSE_CNT_U0_S  0
+
+#define PCNT_U1_CNT_REG          (DR_REG_PCNT_BASE + 0x0064)
+/* PCNT_PULSE_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U1  0x0000FFFF
+#define PCNT_PULSE_CNT_U1_M  ((PCNT_PULSE_CNT_U1_V)<<(PCNT_PULSE_CNT_U1_S))
+#define PCNT_PULSE_CNT_U1_V  0xFFFF
+#define PCNT_PULSE_CNT_U1_S  0
+
+#define PCNT_U2_CNT_REG          (DR_REG_PCNT_BASE + 0x0068)
+/* PCNT_PULSE_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U2  0x0000FFFF
+#define PCNT_PULSE_CNT_U2_M  ((PCNT_PULSE_CNT_U2_V)<<(PCNT_PULSE_CNT_U2_S))
+#define PCNT_PULSE_CNT_U2_V  0xFFFF
+#define PCNT_PULSE_CNT_U2_S  0
+
+#define PCNT_U3_CNT_REG          (DR_REG_PCNT_BASE + 0x006c)
+/* PCNT_PULSE_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U3  0x0000FFFF
+#define PCNT_PULSE_CNT_U3_M  ((PCNT_PULSE_CNT_U3_V)<<(PCNT_PULSE_CNT_U3_S))
+#define PCNT_PULSE_CNT_U3_V  0xFFFF
+#define PCNT_PULSE_CNT_U3_S  0
+
+#define PCNT_U4_CNT_REG          (DR_REG_PCNT_BASE + 0x0070)
+/* PCNT_PULSE_CNT_U4 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U4  0x0000FFFF
+#define PCNT_PULSE_CNT_U4_M  ((PCNT_PULSE_CNT_U4_V)<<(PCNT_PULSE_CNT_U4_S))
+#define PCNT_PULSE_CNT_U4_V  0xFFFF
+#define PCNT_PULSE_CNT_U4_S  0
+
+#define PCNT_U5_CNT_REG          (DR_REG_PCNT_BASE + 0x0074)
+/* PCNT_PULSE_CNT_U5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U5  0x0000FFFF
+#define PCNT_PULSE_CNT_U5_M  ((PCNT_PULSE_CNT_U5_V)<<(PCNT_PULSE_CNT_U5_S))
+#define PCNT_PULSE_CNT_U5_V  0xFFFF
+#define PCNT_PULSE_CNT_U5_S  0
+
+#define PCNT_U6_CNT_REG          (DR_REG_PCNT_BASE + 0x0078)
+/* PCNT_PULSE_CNT_U6 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U6  0x0000FFFF
+#define PCNT_PULSE_CNT_U6_M  ((PCNT_PULSE_CNT_U6_V)<<(PCNT_PULSE_CNT_U6_S))
+#define PCNT_PULSE_CNT_U6_V  0xFFFF
+#define PCNT_PULSE_CNT_U6_S  0
+
+#define PCNT_U7_CNT_REG          (DR_REG_PCNT_BASE + 0x007c)
+/* PCNT_PULSE_CNT_U7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: */
+#define PCNT_PULSE_CNT_U7  0x0000FFFF
+#define PCNT_PULSE_CNT_U7_M  ((PCNT_PULSE_CNT_U7_V)<<(PCNT_PULSE_CNT_U7_S))
+#define PCNT_PULSE_CNT_U7_V  0xFFFF
+#define PCNT_PULSE_CNT_U7_S  0
+
+#define PCNT_INT_RAW_REG          (DR_REG_PCNT_BASE + 0x0080)
+/* PCNT_CNT_THR_EVENT_U7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel7 event.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_M  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_RAW_S  7
+/* PCNT_CNT_THR_EVENT_U6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel6 event.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_M  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_RAW_S  6
+/* PCNT_CNT_THR_EVENT_U5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel5 event.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_M  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_RAW_S  5
+/* PCNT_CNT_THR_EVENT_U4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel4 event.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_M  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_RAW_S  4
+/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel3 event.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S  3
+/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel2 event.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S  2
+/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel1 event.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S  1
+/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the interrupt raw bit for channel0 event.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S  0
+
+#define PCNT_INT_ST_REG          (DR_REG_PCNT_BASE + 0x0084)
+/* PCNT_CNT_THR_EVENT_U7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel7 event.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_ST  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_M  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_ST_S  7
+/* PCNT_CNT_THR_EVENT_U6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel6 event.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_ST  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_M  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_ST_S  6
+/* PCNT_CNT_THR_EVENT_U5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel5 event.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_ST  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_M  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_ST_S  5
+/* PCNT_CNT_THR_EVENT_U4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel4 event.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_ST  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_M  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_ST_S  4
+/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel3 event.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_ST  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_M  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_ST_S  3
+/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel2 event.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_ST  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_M  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_ST_S  2
+/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel1 event.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_ST  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_M  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_ST_S  1
+/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the  interrupt status bit for channel0 event.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_ST  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_M  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_ST_S  0
+
+#define PCNT_INT_ENA_REG          (DR_REG_PCNT_BASE + 0x0088)
+/* PCNT_CNT_THR_EVENT_U7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel7 event.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_M  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_ENA_S  7
+/* PCNT_CNT_THR_EVENT_U6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel6 event.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_M  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_ENA_S  6
+/* PCNT_CNT_THR_EVENT_U5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel5 event.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_M  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_ENA_S  5
+/* PCNT_CNT_THR_EVENT_U4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel4 event.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_M  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_ENA_S  4
+/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel3 event.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S  3
+/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel2 event.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S  2
+/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel1 event.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S  1
+/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: This is the  interrupt enable bit for channel0 event.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S  0
+
+#define PCNT_INT_CLR_REG          (DR_REG_PCNT_BASE + 0x008c)
+/* PCNT_CNT_THR_EVENT_U7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel7 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_M  (BIT(7))
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U7_INT_CLR_S  7
+/* PCNT_CNT_THR_EVENT_U6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel6 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_M  (BIT(6))
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U6_INT_CLR_S  6
+/* PCNT_CNT_THR_EVENT_U5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel5 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_M  (BIT(5))
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U5_INT_CLR_S  5
+/* PCNT_CNT_THR_EVENT_U4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel4 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_M  (BIT(4))
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U4_INT_CLR_S  4
+/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel3 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M  (BIT(3))
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S  3
+/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel2 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M  (BIT(2))
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S  2
+/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel1 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M  (BIT(1))
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S  1
+/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear channel0 event interrupt.*/
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M  (BIT(0))
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V  0x1
+#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S  0
+
+#define PCNT_U0_STATUS_REG          (DR_REG_PCNT_BASE + 0x0090)
+/* PCNT_CORE_STATUS_U0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U0  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U0_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U0_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U0_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U0 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U0  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U0_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U0_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U0_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U0 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U0  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U0_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U0_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U0_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U0 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U0  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U0_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U0_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U0_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U0 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U0  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U0_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U0_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U0_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U0 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U0  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U0_M  ((PCNT_CNT_THR_ZERO_MODE_U0_V)<<(PCNT_CNT_THR_ZERO_MODE_U0_S))
+#define PCNT_CNT_THR_ZERO_MODE_U0_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U0_S  0
+
+#define PCNT_U1_STATUS_REG          (DR_REG_PCNT_BASE + 0x0094)
+/* PCNT_CNT_THR_ZERO_LAT_U1 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U1  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U1_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U1_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U1_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U1 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U1  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U1_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U1_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U1_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U1 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U1  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U1_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U1_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U1_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U1 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U1  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U1_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U1_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U1_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U1 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U1  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U1_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U1_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U1_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U1 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U1  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U1_M  ((PCNT_CNT_THR_ZERO_MODE_U1_V)<<(PCNT_CNT_THR_ZERO_MODE_U1_S))
+#define PCNT_CNT_THR_ZERO_MODE_U1_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U1_S  0
+
+#define PCNT_U2_STATUS_REG          (DR_REG_PCNT_BASE + 0x0098)
+/* PCNT_CNT_THR_ZERO_LAT_U2 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U2  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U2_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U2_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U2_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U2 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U2  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U2_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U2_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U2_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U2 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U2  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U2_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U2_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U2_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U2 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U2  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U2_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U2_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U2_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U2 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U2  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U2_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U2_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U2_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U2 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U2  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U2_M  ((PCNT_CNT_THR_ZERO_MODE_U2_V)<<(PCNT_CNT_THR_ZERO_MODE_U2_S))
+#define PCNT_CNT_THR_ZERO_MODE_U2_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U2_S  0
+
+#define PCNT_U3_STATUS_REG          (DR_REG_PCNT_BASE + 0x009c)
+/* PCNT_CNT_THR_ZERO_LAT_U3 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U3  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U3_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U3_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U3_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U3 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U3  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U3_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U3_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U3_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U3 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U3  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U3_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U3_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U3_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U3 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U3  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U3_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U3_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U3_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U3 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U3  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U3_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U3_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U3_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U3 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U3  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U3_M  ((PCNT_CNT_THR_ZERO_MODE_U3_V)<<(PCNT_CNT_THR_ZERO_MODE_U3_S))
+#define PCNT_CNT_THR_ZERO_MODE_U3_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U3_S  0
+
+#define PCNT_U4_STATUS_REG          (DR_REG_PCNT_BASE + 0x00a0)
+/* PCNT_CNT_THR_ZERO_LAT_U4 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U4  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U4_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U4_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U4_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U4 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U4  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U4_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U4_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U4_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U4 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U4  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U4_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U4_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U4_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U4 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U4  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U4_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U4_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U4_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U4 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U4  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U4_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U4_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U4_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U4 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U4  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U4_M  ((PCNT_CNT_THR_ZERO_MODE_U4_V)<<(PCNT_CNT_THR_ZERO_MODE_U4_S))
+#define PCNT_CNT_THR_ZERO_MODE_U4_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U4_S  0
+
+#define PCNT_U5_STATUS_REG          (DR_REG_PCNT_BASE + 0x00a4)
+/* PCNT_CNT_THR_ZERO_LAT_U5 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U5  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U5_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U5_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U5_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U5 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U5  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U5_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U5_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U5_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U5 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U5  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U5_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U5_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U5_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U5 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U5  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U5_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U5_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U5_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U5 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U5  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U5_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U5_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U5_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U5 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U5  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U5_M  ((PCNT_CNT_THR_ZERO_MODE_U5_V)<<(PCNT_CNT_THR_ZERO_MODE_U5_S))
+#define PCNT_CNT_THR_ZERO_MODE_U5_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U5_S  0
+
+#define PCNT_U6_STATUS_REG          (DR_REG_PCNT_BASE + 0x00a8)
+/* PCNT_CNT_THR_ZERO_LAT_U6 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U6  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U6_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U6_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U6_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U6 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U6  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U6_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U6_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U6_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U6 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U6  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U6_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U6_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U6_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U6 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U6  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U6_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U6_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U6_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U6 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U6  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U6_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U6_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U6_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U6 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U6  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U6_M  ((PCNT_CNT_THR_ZERO_MODE_U6_V)<<(PCNT_CNT_THR_ZERO_MODE_U6_S))
+#define PCNT_CNT_THR_ZERO_MODE_U6_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U6_S  0
+
+#define PCNT_U7_STATUS_REG          (DR_REG_PCNT_BASE + 0x00ac)
+/* PCNT_CNT_THR_ZERO_LAT_U7 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_LAT_U7  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U7_M  (BIT(6))
+#define PCNT_CNT_THR_ZERO_LAT_U7_V  0x1
+#define PCNT_CNT_THR_ZERO_LAT_U7_S  6
+/* PCNT_CNT_THR_H_LIM_LAT_U7 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_H_LIM_LAT_U7  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U7_M  (BIT(5))
+#define PCNT_CNT_THR_H_LIM_LAT_U7_V  0x1
+#define PCNT_CNT_THR_H_LIM_LAT_U7_S  5
+/* PCNT_CNT_THR_L_LIM_LAT_U7 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_L_LIM_LAT_U7  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U7_M  (BIT(4))
+#define PCNT_CNT_THR_L_LIM_LAT_U7_V  0x1
+#define PCNT_CNT_THR_L_LIM_LAT_U7_S  4
+/* PCNT_CNT_THR_THRES0_LAT_U7 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES0_LAT_U7  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U7_M  (BIT(3))
+#define PCNT_CNT_THR_THRES0_LAT_U7_V  0x1
+#define PCNT_CNT_THR_THRES0_LAT_U7_S  3
+/* PCNT_CNT_THR_THRES1_LAT_U7 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_THRES1_LAT_U7  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U7_M  (BIT(2))
+#define PCNT_CNT_THR_THRES1_LAT_U7_V  0x1
+#define PCNT_CNT_THR_THRES1_LAT_U7_S  2
+/* PCNT_CNT_THR_ZERO_MODE_U7 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define PCNT_CNT_THR_ZERO_MODE_U7  0x00000003
+#define PCNT_CNT_THR_ZERO_MODE_U7_M  ((PCNT_CNT_THR_ZERO_MODE_U7_V)<<(PCNT_CNT_THR_ZERO_MODE_U7_S))
+#define PCNT_CNT_THR_ZERO_MODE_U7_V  0x3
+#define PCNT_CNT_THR_ZERO_MODE_U7_S  0
+
+#define PCNT_CTRL_REG          (DR_REG_PCNT_BASE + 0x00b0)
+/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define PCNT_CLK_EN  (BIT(16))
+#define PCNT_CLK_EN_M  (BIT(16))
+#define PCNT_CLK_EN_V  0x1
+#define PCNT_CLK_EN_S  16
+/* PCNT_CNT_PAUSE_U7 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit7's counter.*/
+#define PCNT_CNT_PAUSE_U7  (BIT(15))
+#define PCNT_CNT_PAUSE_U7_M  (BIT(15))
+#define PCNT_CNT_PAUSE_U7_V  0x1
+#define PCNT_CNT_PAUSE_U7_S  15
+/* PCNT_PULSE_CNT_RST_U7 : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U7  (BIT(14))
+#define PCNT_PULSE_CNT_RST_U7_M  (BIT(14))
+#define PCNT_PULSE_CNT_RST_U7_V  0x1
+#define PCNT_PULSE_CNT_RST_U7_S  14
+/* PCNT_CNT_PAUSE_U6 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit6's counter.*/
+#define PCNT_CNT_PAUSE_U6  (BIT(13))
+#define PCNT_CNT_PAUSE_U6_M  (BIT(13))
+#define PCNT_CNT_PAUSE_U6_V  0x1
+#define PCNT_CNT_PAUSE_U6_S  13
+/* PCNT_PULSE_CNT_RST_U6 : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U6  (BIT(12))
+#define PCNT_PULSE_CNT_RST_U6_M  (BIT(12))
+#define PCNT_PULSE_CNT_RST_U6_V  0x1
+#define PCNT_PULSE_CNT_RST_U6_S  12
+/* PCNT_CNT_PAUSE_U5 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit5's counter.*/
+#define PCNT_CNT_PAUSE_U5  (BIT(11))
+#define PCNT_CNT_PAUSE_U5_M  (BIT(11))
+#define PCNT_CNT_PAUSE_U5_V  0x1
+#define PCNT_CNT_PAUSE_U5_S  11
+/* PCNT_PULSE_CNT_RST_U5 : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U5  (BIT(10))
+#define PCNT_PULSE_CNT_RST_U5_M  (BIT(10))
+#define PCNT_PULSE_CNT_RST_U5_V  0x1
+#define PCNT_PULSE_CNT_RST_U5_S  10
+/* PCNT_CNT_PAUSE_U4 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit4's counter.*/
+#define PCNT_CNT_PAUSE_U4  (BIT(9))
+#define PCNT_CNT_PAUSE_U4_M  (BIT(9))
+#define PCNT_CNT_PAUSE_U4_V  0x1
+#define PCNT_CNT_PAUSE_U4_S  9
+/* PCNT_PULSE_CNT_RST_U4 : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U4  (BIT(8))
+#define PCNT_PULSE_CNT_RST_U4_M  (BIT(8))
+#define PCNT_PULSE_CNT_RST_U4_V  0x1
+#define PCNT_PULSE_CNT_RST_U4_S  8
+/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit3's counter.*/
+#define PCNT_CNT_PAUSE_U3  (BIT(7))
+#define PCNT_CNT_PAUSE_U3_M  (BIT(7))
+#define PCNT_CNT_PAUSE_U3_V  0x1
+#define PCNT_CNT_PAUSE_U3_S  7
+/* PCNT_PULSE_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U3  (BIT(6))
+#define PCNT_PULSE_CNT_RST_U3_M  (BIT(6))
+#define PCNT_PULSE_CNT_RST_U3_V  0x1
+#define PCNT_PULSE_CNT_RST_U3_S  6
+/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit2's counter.*/
+#define PCNT_CNT_PAUSE_U2  (BIT(5))
+#define PCNT_CNT_PAUSE_U2_M  (BIT(5))
+#define PCNT_CNT_PAUSE_U2_V  0x1
+#define PCNT_CNT_PAUSE_U2_S  5
+/* PCNT_PULSE_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U2  (BIT(4))
+#define PCNT_PULSE_CNT_RST_U2_M  (BIT(4))
+#define PCNT_PULSE_CNT_RST_U2_V  0x1
+#define PCNT_PULSE_CNT_RST_U2_S  4
+/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit1's counter.*/
+#define PCNT_CNT_PAUSE_U1  (BIT(3))
+#define PCNT_CNT_PAUSE_U1_M  (BIT(3))
+#define PCNT_CNT_PAUSE_U1_V  0x1
+#define PCNT_CNT_PAUSE_U1_S  3
+/* PCNT_PULSE_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U1  (BIT(2))
+#define PCNT_PULSE_CNT_RST_U1_M  (BIT(2))
+#define PCNT_PULSE_CNT_RST_U1_V  0x1
+#define PCNT_PULSE_CNT_RST_U1_S  2
+/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to pause unit0's counter.*/
+#define PCNT_CNT_PAUSE_U0  (BIT(1))
+#define PCNT_CNT_PAUSE_U0_M  (BIT(1))
+#define PCNT_CNT_PAUSE_U0_V  0x1
+#define PCNT_CNT_PAUSE_U0_S  1
+/* PCNT_PULSE_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define PCNT_PULSE_CNT_RST_U0  (BIT(0))
+#define PCNT_PULSE_CNT_RST_U0_M  (BIT(0))
+#define PCNT_PULSE_CNT_RST_U0_V  0x1
+#define PCNT_PULSE_CNT_RST_U0_S  0
+
+#define PCNT_DATE_REG          (DR_REG_PCNT_BASE + 0x00fc)
+/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h14122600 ; */
+/*description: */
+#define PCNT_DATE  0xFFFFFFFF
+#define PCNT_DATE_M  ((PCNT_DATE_V)<<(PCNT_DATE_S))
+#define PCNT_DATE_V  0xFFFFFFFF
+#define PCNT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_PCNT_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/pcnt_struct.h b/components/soc/esp32s2beta/include/soc/pcnt_struct.h
new file mode 100644
index 000000000..3ed0e163c
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/pcnt_struct.h
@@ -0,0 +1,180 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_PCNT_STRUCT_H_
+#define _SOC_PCNT_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    struct{
+        union {
+            struct {
+                uint32_t filter_thres:  10;         /*This register is used to filter pulse whose width is smaller than this value for unit0.*/
+                uint32_t filter_en:      1;         /*This is the enable bit for filtering input signals for unit0.*/
+                uint32_t thr_zero_en:    1;         /*This is the enable bit for comparing unit0's count with 0 value.*/
+                uint32_t thr_h_lim_en:   1;         /*This is the enable bit for  comparing unit0's count with thr_h_lim value.*/
+                uint32_t thr_l_lim_en:   1;         /*This is the enable bit for comparing unit0's count with thr_l_lim  value.*/
+                uint32_t thr_thres0_en:  1;         /*This is the enable bit for comparing unit0's count with  thres0 value.*/
+                uint32_t thr_thres1_en:  1;         /*This is the enable bit for  comparing  unit0's count with thres1 value .*/
+                uint32_t ch0_neg_mode:   2;         /*This register is used to control the mode of channel0's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+                uint32_t ch0_pos_mode:   2;         /*This register is used to control the mode of channel0's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+                uint32_t ch0_hctrl_mode: 2;         /*This register is used to control the mode of channel0's high control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
+                uint32_t ch0_lctrl_mode: 2;         /*This register is used to control the mode of channel0's low control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
+                uint32_t ch1_neg_mode:   2;         /*This register is used to control the mode of channel1's input neg-edge signal for unit0. 2'd1：increase at the negedge of input signal    2'd2:decrease at the negedge of input signal    others:forbidden*/
+                uint32_t ch1_pos_mode:   2;         /*This register is used to control the mode of channel1's input pos-edge signal for unit0. 2'd1：increase at the posedge of input signal    2'd2:decrease at the posedge of input signal    others:forbidden*/
+                uint32_t ch1_hctrl_mode: 2;         /*This register is used to control the mode of channel1's high control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
+                uint32_t ch1_lctrl_mode: 2;         /*This register is used to control the mode of channel1's low control signal for unit0. 2'd0:increase when control signal is low   2'd1：decrease when control signal is high   others:forbidden*/
+            };
+            uint32_t val;
+        } conf0;
+        union {
+            struct {
+                uint32_t cnt_thres0:16;             /*This register is used to configure thres0 value for unit0.*/
+                uint32_t cnt_thres1:16;             /*This register is used to configure thres1 value for unit0.*/
+            };
+            uint32_t val;
+        } conf1;
+        union {
+            struct {
+                uint32_t cnt_h_lim:16;              /*This register is used to configure thr_h_lim value for unit0.*/
+                uint32_t cnt_l_lim:16;              /*This register is used to configure thr_l_lim value for unit0.*/
+            };
+            uint32_t val;
+        } conf2;
+    } conf_unit[8];
+    union {
+        struct {
+            uint32_t cnt_val   : 16;                /*This register stores the current pulse count value for unit0.*/
+            uint32_t reserved16: 16;
+        };
+        uint32_t val;
+    } cnt_unit[8];
+    union {
+        struct {
+            uint32_t cnt_thr_event_u0: 1;           /*This is the interrupt raw bit for channel0 event.*/
+            uint32_t cnt_thr_event_u1: 1;           /*This is the interrupt raw bit for channel1 event.*/
+            uint32_t cnt_thr_event_u2: 1;           /*This is the interrupt raw bit for channel2 event.*/
+            uint32_t cnt_thr_event_u3: 1;           /*This is the interrupt raw bit for channel3 event.*/
+            uint32_t cnt_thr_event_u4: 1;           /*This is the interrupt raw bit for channel4 event.*/
+            uint32_t cnt_thr_event_u5: 1;           /*This is the interrupt raw bit for channel5 event.*/
+            uint32_t cnt_thr_event_u6: 1;           /*This is the interrupt raw bit for channel6 event.*/
+            uint32_t cnt_thr_event_u7: 1;           /*This is the interrupt raw bit for channel7 event.*/
+            uint32_t reserved8:       24;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t cnt_thr_event_u0: 1;            /*This is the  interrupt status bit for channel0 event.*/
+            uint32_t cnt_thr_event_u1: 1;            /*This is the  interrupt status bit for channel1 event.*/
+            uint32_t cnt_thr_event_u2: 1;            /*This is the  interrupt status bit for channel2 event.*/
+            uint32_t cnt_thr_event_u3: 1;            /*This is the  interrupt status bit for channel3 event.*/
+            uint32_t cnt_thr_event_u4: 1;            /*This is the  interrupt status bit for channel4 event.*/
+            uint32_t cnt_thr_event_u5: 1;            /*This is the  interrupt status bit for channel5 event.*/
+            uint32_t cnt_thr_event_u6: 1;            /*This is the  interrupt status bit for channel6 event.*/
+            uint32_t cnt_thr_event_u7: 1;            /*This is the  interrupt status bit for channel7 event.*/
+            uint32_t reserved8:       24;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t cnt_thr_event_u0: 1;           /*This is the  interrupt enable bit for channel0 event.*/
+            uint32_t cnt_thr_event_u1: 1;           /*This is the  interrupt enable bit for channel1 event.*/
+            uint32_t cnt_thr_event_u2: 1;           /*This is the  interrupt enable bit for channel2 event.*/
+            uint32_t cnt_thr_event_u3: 1;           /*This is the  interrupt enable bit for channel3 event.*/
+            uint32_t cnt_thr_event_u4: 1;           /*This is the  interrupt enable bit for channel4 event.*/
+            uint32_t cnt_thr_event_u5: 1;           /*This is the  interrupt enable bit for channel5 event.*/
+            uint32_t cnt_thr_event_u6: 1;           /*This is the  interrupt enable bit for channel6 event.*/
+            uint32_t cnt_thr_event_u7: 1;           /*This is the  interrupt enable bit for channel7 event.*/
+            uint32_t reserved8:       24;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t cnt_thr_event_u0: 1;           /*Set this bit to clear channel0 event interrupt.*/
+            uint32_t cnt_thr_event_u1: 1;           /*Set this bit to clear channel1 event interrupt.*/
+            uint32_t cnt_thr_event_u2: 1;           /*Set this bit to clear channel2 event interrupt.*/
+            uint32_t cnt_thr_event_u3: 1;           /*Set this bit to clear channel3 event interrupt.*/
+            uint32_t cnt_thr_event_u4: 1;           /*Set this bit to clear channel4 event interrupt.*/
+            uint32_t cnt_thr_event_u5: 1;           /*Set this bit to clear channel5 event interrupt.*/
+            uint32_t cnt_thr_event_u6: 1;           /*Set this bit to clear channel6 event interrupt.*/
+            uint32_t cnt_thr_event_u7: 1;           /*Set this bit to clear channel7 event interrupt.*/
+            uint32_t reserved8:       24;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t cnt_mode:2;                    /*0: positive value to zero; 1: negative value to zero; 2: counter value negative ; 3: counter value positive*/
+            uint32_t thres1_lat:1;                  /* counter value equals to thresh1*/
+            uint32_t thres0_lat:1;                  /* counter value equals to thresh0*/
+            uint32_t l_lim_lat:1;                   /* counter value reaches h_lim*/
+            uint32_t h_lim_lat:1;                   /* counter value reaches l_lim*/
+            uint32_t zero_lat:1;                    /* counter value equals zero*/
+            uint32_t reserved7:25;
+        };
+        uint32_t val;
+    } status_unit[8];
+    union {
+        struct {
+            uint32_t cnt_rst_u0:   1;               /*Set this bit to clear unit0's counter.*/
+            uint32_t cnt_pause_u0: 1;               /*Set this bit to pause unit0's counter.*/
+            uint32_t cnt_rst_u1:   1;               /*Set this bit to clear unit1's counter.*/
+            uint32_t cnt_pause_u1: 1;               /*Set this bit to pause unit1's counter.*/
+            uint32_t cnt_rst_u2:   1;               /*Set this bit to clear unit2's counter.*/
+            uint32_t cnt_pause_u2: 1;               /*Set this bit to pause unit2's counter.*/
+            uint32_t cnt_rst_u3:   1;               /*Set this bit to clear unit3's counter.*/
+            uint32_t cnt_pause_u3: 1;               /*Set this bit to pause unit3's counter.*/
+            uint32_t cnt_rst_u4:   1;               /*Set this bit to clear unit4's counter.*/
+            uint32_t cnt_pause_u4: 1;               /*Set this bit to pause unit4's counter.*/
+            uint32_t cnt_rst_u5:   1;               /*Set this bit to clear unit5's counter.*/
+            uint32_t cnt_pause_u5: 1;               /*Set this bit to pause unit5's counter.*/
+            uint32_t cnt_rst_u6:   1;               /*Set this bit to clear unit6's counter.*/
+            uint32_t cnt_pause_u6: 1;               /*Set this bit to pause unit6's counter.*/
+            uint32_t cnt_rst_u7:   1;               /*Set this bit to clear unit7's counter.*/
+            uint32_t cnt_pause_u7: 1;               /*Set this bit to pause unit7's counter.*/
+            uint32_t clk_en:       1;
+            uint32_t reserved17:  15;
+        };
+        uint32_t val;
+    } ctrl;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t date;                                  /**/
+} pcnt_dev_t;
+extern pcnt_dev_t PCNT;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_PCNT_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/periph_defs.h b/components/soc/esp32s2beta/include/soc/periph_defs.h
new file mode 100644
index 000000000..85c8274cf
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/periph_defs.h
@@ -0,0 +1,165 @@
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_PERIPH_DEFS_H_
+#define _SOC_PERIPH_DEFS_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PERIPH_LEDC_MODULE = 0,
+    PERIPH_UART0_MODULE,
+    PERIPH_UART1_MODULE,
+#ifdef CONFIG_CHIP_IS_ESP32
+    PERIPH_UART2_MODULE,
+#else
+    PERIPH_USB_MODULE,
+#endif
+    PERIPH_I2C0_MODULE,
+    PERIPH_I2C1_MODULE,
+    PERIPH_I2S0_MODULE,
+    PERIPH_I2S1_MODULE,
+    PERIPH_TIMG0_MODULE,
+    PERIPH_TIMG1_MODULE,
+    PERIPH_PWM0_MODULE,
+    PERIPH_PWM1_MODULE,
+    PERIPH_PWM2_MODULE,
+    PERIPH_PWM3_MODULE,
+    PERIPH_UHCI0_MODULE,
+    PERIPH_UHCI1_MODULE,
+    PERIPH_RMT_MODULE,
+    PERIPH_PCNT_MODULE,
+    PERIPH_SPI_MODULE,  //SPI1
+    PERIPH_FSPI_MODULE, //SPI2
+    PERIPH_HSPI_MODULE, //SPI3
+    PERIPH_VSPI_MODULE, //SPI4
+    PERIPH_SPI2_DMA_MODULE,
+    PERIPH_SPI3_DMA_MODULE,
+    PERIPH_SPI_SHARED_DMA_MODULE,   //this DMA is shared by SPI1 and SPI4
+    PERIPH_SDMMC_MODULE,
+    PERIPH_SDIO_SLAVE_MODULE,
+    PERIPH_CAN_MODULE,
+    PERIPH_EMAC_MODULE,
+    PERIPH_RNG_MODULE,
+    PERIPH_WIFI_MODULE,
+    PERIPH_BT_MODULE,
+    PERIPH_WIFI_BT_COMMON_MODULE,
+    PERIPH_BT_BASEBAND_MODULE,
+    PERIPH_BT_LC_MODULE,
+} periph_module_t;
+
+typedef enum {
+    ETS_WIFI_MAC_INTR_SOURCE = 0,               /**< interrupt of WiFi MAC, level*/
+    ETS_WIFI_MAC_NMI_SOURCE,                    /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
+    ETS_WIFI_PWR_INTR_SOURCE,                   /**< */
+    ETS_WIFI_BB_INTR_SOURCE,                    /**< interrupt of WiFi BB, level, we can do some calibartion*/
+    ETS_BT_MAC_INTR_SOURCE,                     /**< will be cancelled*/
+    ETS_BT_BB_INTR_SOURCE,                      /**< interrupt of BT BB, level*/
+    ETS_BT_BB_NMI_SOURCE,                       /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
+    ETS_RWBT_INTR_SOURCE,                       /**< interrupt of RWBT, level*/
+    ETS_RWBLE_INTR_SOURCE,                      /**< interrupt of RWBLE, level*/
+    ETS_RWBT_NMI_SOURCE,                        /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
+    ETS_RWBLE_NMI_SOURCE,                       /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
+    ETS_SLC0_INTR_SOURCE,                       /**< interrupt of SLC0, level*/
+    ETS_SLC1_INTR_SOURCE,                       /**< interrupt of SLC1, level*/
+    ETS_UHCI0_INTR_SOURCE,                      /**< interrupt of UHCI0, level*/
+    ETS_UHCI1_INTR_SOURCE,                      /**< interrupt of UHCI1, level*/
+    ETS_TG0_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
+
+    ETS_TG0_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
+    ETS_TG0_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
+    ETS_TG0_LACT_LEVEL_INTR_SOURCE,             /**< interrupt of TIMER_GROUP0, LACT, level*/
+    ETS_TG1_T0_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
+    ETS_TG1_T1_LEVEL_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
+    ETS_TG1_WDT_LEVEL_INTR_SOURCE,              /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
+    ETS_TG1_LACT_LEVEL_INTR_SOURCE,             /**< interrupt of TIMER_GROUP1, LACT, level*/
+    ETS_GPIO_INTR_SOURCE,                       /**< interrupt of GPIO, level*/
+    ETS_GPIO_NMI_SOURCE,                        /**< interrupt of GPIO, NMI*/
+    ETS_GPIO_INTR_SOURCE2,                      /**< interrupt of GPIO, level*/
+    ETS_GPIO_NMI_SOURCE2,                       /**< interrupt of GPIO, NMI*/
+    ETS_DEDICATED_GPIO_INTR_SOURCE,                 /**< interrupt of dedicated GPIO, level*/
+    ETS_FROM_CPU_INTR0_SOURCE,                  /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
+    ETS_FROM_CPU_INTR1_SOURCE,                  /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
+    ETS_FROM_CPU_INTR2_SOURCE,                  /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
+    ETS_FROM_CPU_INTR3_SOURCE,                  /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
+
+    ETS_SPI1_INTR_SOURCE = 32,                       /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
+    ETS_SPI2_INTR_SOURCE,                       /**< interrupt of SPI2, level*/
+    ETS_SPI3_INTR_SOURCE,                       /**< interrupt of SPI3, level*/
+    ETS_I2S0_INTR_SOURCE,                       /**< interrupt of I2S0, level*/
+    ETS_I2S1_INTR_SOURCE,                       /**< interrupt of I2S1, level*/
+    ETS_UART0_INTR_SOURCE,                      /**< interrupt of UART0, level*/
+    ETS_UART1_INTR_SOURCE,                      /**< interrupt of UART1, level*/
+    ETS_UART2_INTR_SOURCE,                      /**< interrupt of UART2, level*/
+    ETS_SDIO_HOST_INTR_SOURCE,                  /**< interrupt of SD/SDIO/MMC HOST, level*/
+    ETS_PWM0_INTR_SOURCE,                       /**< interrupt of PWM0, level, Reserved*/
+    ETS_PWM1_INTR_SOURCE,                       /**< interrupt of PWM1, level, Reserved*/
+    ETS_PWM2_INTR_SOURCE,                       /**< interrupt of PWM2, level*/
+    ETS_PWM3_INTR_SOURCE,                       /**< interruot of PWM3, level*/
+    ETS_LEDC_INTR_SOURCE,                       /**< interrupt of LED PWM, level*/
+    ETS_EFUSE_INTR_SOURCE,                      /**< interrupt of efuse, level, not likely to use*/
+    ETS_CAN_INTR_SOURCE ,                       /**< interrupt of can, level*/
+
+    ETS_USB_INTR_SOURCE = 48,                   /**< interrupt of USB, level*/
+    ETS_RTC_CORE_INTR_SOURCE,                   /**< interrupt of rtc core, level, include rtc watchdog*/
+    ETS_RMT_INTR_SOURCE,                        /**< interrupt of remote controller, level*/
+    ETS_PCNT_INTR_SOURCE,                       /**< interrupt of pluse count, level*/
+    ETS_I2C_EXT0_INTR_SOURCE,                   /**< interrupt of I2C controller1, level*/
+    ETS_I2C_EXT1_INTR_SOURCE,                   /**< interrupt of I2C controller0, level*/
+    ETS_RSA_INTR_SOURCE,                        /**< interrupt of RSA accelerator, level*/
+    ETS_SPI1_DMA_INTR_SOURCE,                   /**< interrupt of SPI1 DMA, SPI1 is for flash read/write, do not use this*/
+    ETS_SPI2_DMA_INTR_SOURCE,                   /**< interrupt of SPI2 DMA, level*/
+    ETS_SPI3_DMA_INTR_SOURCE,                   /**< interrupt of SPI3 DMA, level*/
+    ETS_WDT_INTR_SOURCE,                        /**< will be cancelled*/
+    ETS_TIMER1_INTR_SOURCE,                     /**< will be cancelled*/
+    ETS_TIMER2_INTR_SOURCE,                     /**< will be cancelled*/
+    ETS_TG0_T0_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
+    ETS_TG0_T1_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
+    ETS_TG0_WDT_EDGE_INTR_SOURCE,               /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
+
+    ETS_TG0_LACT_EDGE_INTR_SOURCE = 64,         /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
+    ETS_TG1_T0_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
+    ETS_TG1_T1_EDGE_INTR_SOURCE,                /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
+    ETS_TG1_WDT_EDGE_INTR_SOURCE,               /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
+    ETS_TG1_LACT_EDGE_INTR_SOURCE,              /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
+    ETS_CACHE_IA_INTR_SOURCE,                   /**< interrupt of Cache Invalied Access, LEVEL*/
+    ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE,      /**< interrupt of system timer 0, EDGE*/
+    ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE,      /**< interrupt of system timer 1, EDGE*/
+    ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE,      /**< interrupt of system timer 2, EDGE*/
+    ETS_ASSIST_DEBUG_INTR_SOURCE,               /**< interrupt of Assist debug module, LEVEL*/
+    ETS_PMS_PRO_IRAM0_ILG_INTR_SOURCE,          /**< interrupt of illegal IRAM1 access, LEVEL*/
+    ETS_PMS_PRO_DRAM0_ILG_INTR_SOURCE,          /**< interrupt of illegal DRAM0 access, LEVEL*/
+    ETS_PMS_PRO_DPORT_ILG_INTR_SOURCE,          /**< interrupt of illegal DPORT access, LEVEL*/
+    ETS_PMS_PRO_AHB_ILG_INTR_SOURCE,            /**< interrupt of illegal AHB access, LEVEL*/
+    ETS_PMS_PRO_CACHE_ILG_INTR_SOURCE,          /**< interrupt of illegal CACHE access, LEVEL*/
+    ETS_PMS_DMA_APB_I_ILG_INTR_SOURCE,          /**< interrupt of illegal APB access, LEVEL*/
+
+    ETS_PMS_DMA_RX_I_ILG_INTR_SOURCE = 80,      /**< interrupt of illegal DMA RX access, LEVEL*/
+    ETS_PMS_DMA_TX_I_ILG_INTR_SOURCE,           /**< interrupt of illegal DMA TX access, LEVEL*/
+    ETS_SPI0_REJECT_CACHE_INTR_SOURCE,          /**< interrupt of SPI0 Cache access rejected, LEVEL*/
+    ETS_SPI1_REJECT_CPU_INTR_SOURCE,            /**< interrupt of SPI1 access rejected, LEVEL*/
+    ETS_DMA_COPY_INTR_SOURCE,                   /**< interrupt of DMA copy, LEVEL*/
+    ETS_SPI4_DMA_INTR_SOURCE,                   /**< interrupt of SPI4 DMA, LEVEL*/
+    ETS_SPI4_INTR_SOURCE,                       /**< interrupt of SPI4, LEVEL*/
+    ETS_MAX_INTR_SOURCE,                        /**< number of interrupt sources */
+
+} periph_interrput_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SOC_PERIPH_DEFS_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/rmt_reg.h b/components/soc/esp32s2beta/include/soc/rmt_reg.h
new file mode 100644
index 000000000..d216d54d1
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rmt_reg.h
@@ -0,0 +1,2964 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RMT_REG_H_
+#define _SOC_RMT_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RMT_CH0DATA_REG          (DR_REG_RMT_BASE + 0x0000)
+
+#define RMT_CH1DATA_REG          (DR_REG_RMT_BASE + 0x0004)
+
+#define RMT_CH2DATA_REG          (DR_REG_RMT_BASE + 0x0008)
+
+#define RMT_CH3DATA_REG          (DR_REG_RMT_BASE + 0x000c)
+
+#define RMT_CH4DATA_REG          (DR_REG_RMT_BASE + 0x0010)
+
+#define RMT_CH5DATA_REG          (DR_REG_RMT_BASE + 0x0014)
+
+#define RMT_CH6DATA_REG          (DR_REG_RMT_BASE + 0x0018)
+
+#define RMT_CH7DATA_REG          (DR_REG_RMT_BASE + 0x001c)
+
+#define RMT_CH0CONF0_REG          (DR_REG_RMT_BASE + 0x0020)
+/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: This bit  is used  to control clock.when software config RMT
+ internal registers  it controls the register clock.*/
+#define RMT_CLK_EN  (BIT(31))
+#define RMT_CLK_EN_M  (BIT(31))
+#define RMT_CLK_EN_V  0x1
+#define RMT_CLK_EN_S  31
+/* RMT_MEM_PD : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit is used to reduce power consumed by mem. 1:mem is in low power state.*/
+#define RMT_MEM_PD  (BIT(30))
+#define RMT_MEM_PD_M  (BIT(30))
+#define RMT_MEM_PD_V  0x1
+#define RMT_MEM_PD_S  30
+/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure the way carrier wave is modulated
+ for  channel0.1'b1:transmit on low output level  1'b0:transmit  on high output level.*/
+#define RMT_CARRIER_OUT_LV_CH0  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH0_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH0_V  0x1
+#define RMT_CARRIER_OUT_LV_CH0_S  29
+/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel0.*/
+#define RMT_CARRIER_EN_CH0  (BIT(28))
+#define RMT_CARRIER_EN_CH0_M  (BIT(28))
+#define RMT_CARRIER_EN_CH0_V  0x1
+#define RMT_CARRIER_EN_CH0_S  28
+/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel0.*/
+#define RMT_MEM_SIZE_CH0  0x0000000F
+#define RMT_MEM_SIZE_CH0_M  ((RMT_MEM_SIZE_CH0_V)<<(RMT_MEM_SIZE_CH0_S))
+#define RMT_MEM_SIZE_CH0_V  0xF
+#define RMT_MEM_SIZE_CH0_S  24
+/* RMT_IDLE_THRES_CH0 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when no edge is detected on the input signal
+ for longer than reg_idle_thres_ch0 then the receive process is done.*/
+#define RMT_IDLE_THRES_CH0  0x0000FFFF
+#define RMT_IDLE_THRES_CH0_M  ((RMT_IDLE_THRES_CH0_V)<<(RMT_IDLE_THRES_CH0_S))
+#define RMT_IDLE_THRES_CH0_V  0xFFFF
+#define RMT_IDLE_THRES_CH0_S  8
+/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel0.*/
+#define RMT_DIV_CNT_CH0  0x000000FF
+#define RMT_DIV_CNT_CH0_M  ((RMT_DIV_CNT_CH0_V)<<(RMT_DIV_CNT_CH0_S))
+#define RMT_DIV_CNT_CH0_V  0xFF
+#define RMT_DIV_CNT_CH0_S  0
+
+#define RMT_CH0CONF1_REG          (DR_REG_RMT_BASE + 0x0024)
+/* RMT_TX_STOP_CH0 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH0  (BIT(20))
+#define RMT_TX_STOP_CH0_M  (BIT(20))
+#define RMT_TX_STOP_CH0_V  0x1
+#define RMT_TX_STOP_CH0_S  20
+/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel0 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH0  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH0_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH0_V  0x1
+#define RMT_IDLE_OUT_EN_CH0_S  19
+/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel0 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH0  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH0_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH0_V  0x1
+#define RMT_IDLE_OUT_LV_CH0_S  18
+/* RMT_REF_ALWAYS_ON_CH0 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH0  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH0_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH0_V  0x1
+#define RMT_REF_ALWAYS_ON_CH0_S  17
+/* RMT_RX_FILTER_THRES_CH0 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel0 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH0  0x000000FF
+#define RMT_RX_FILTER_THRES_CH0_M  ((RMT_RX_FILTER_THRES_CH0_V)<<(RMT_RX_FILTER_THRES_CH0_S))
+#define RMT_RX_FILTER_THRES_CH0_V  0xFF
+#define RMT_RX_FILTER_THRES_CH0_S  8
+/* RMT_RX_FILTER_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel0.*/
+#define RMT_RX_FILTER_EN_CH0  (BIT(7))
+#define RMT_RX_FILTER_EN_CH0_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH0_V  0x1
+#define RMT_RX_FILTER_EN_CH0_S  7
+/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel0 again and again.*/
+#define RMT_TX_CONTI_MODE_CH0  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH0_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH0_V  0x1
+#define RMT_TX_CONTI_MODE_CH0_S  6
+/* RMT_MEM_OWNER_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel0's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH0  (BIT(5))
+#define RMT_MEM_OWNER_CH0_M  (BIT(5))
+#define RMT_MEM_OWNER_CH0_V  0x1
+#define RMT_MEM_OWNER_CH0_S  5
+/* RMT_APB_MEM_RST_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel0 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH0  (BIT(4))
+#define RMT_APB_MEM_RST_CH0_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH0_V  0x1
+#define RMT_APB_MEM_RST_CH0_S  4
+/* RMT_MEM_RD_RST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel0 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH0  (BIT(3))
+#define RMT_MEM_RD_RST_CH0_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH0_V  0x1
+#define RMT_MEM_RD_RST_CH0_S  3
+/* RMT_MEM_WR_RST_CH0 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel0 by receiver access.*/
+#define RMT_MEM_WR_RST_CH0  (BIT(2))
+#define RMT_MEM_WR_RST_CH0_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH0_V  0x1
+#define RMT_MEM_WR_RST_CH0_S  2
+/* RMT_RX_EN_CH0 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel0.*/
+#define RMT_RX_EN_CH0  (BIT(1))
+#define RMT_RX_EN_CH0_M  (BIT(1))
+#define RMT_RX_EN_CH0_V  0x1
+#define RMT_RX_EN_CH0_S  1
+/* RMT_TX_START_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel0.*/
+#define RMT_TX_START_CH0  (BIT(0))
+#define RMT_TX_START_CH0_M  (BIT(0))
+#define RMT_TX_START_CH0_V  0x1
+#define RMT_TX_START_CH0_S  0
+
+#define RMT_CH1CONF0_REG          (DR_REG_RMT_BASE + 0x0028)
+/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure the way carrier wave is modulated
+ for  channel1.1'b1:transmit on low output level  1'b0:transmit  on high output level.*/
+#define RMT_CARRIER_OUT_LV_CH1  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH1_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH1_V  0x1
+#define RMT_CARRIER_OUT_LV_CH1_S  29
+/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel1.*/
+#define RMT_CARRIER_EN_CH1  (BIT(28))
+#define RMT_CARRIER_EN_CH1_M  (BIT(28))
+#define RMT_CARRIER_EN_CH1_V  0x1
+#define RMT_CARRIER_EN_CH1_S  28
+/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel1.*/
+#define RMT_MEM_SIZE_CH1  0x0000000F
+#define RMT_MEM_SIZE_CH1_M  ((RMT_MEM_SIZE_CH1_V)<<(RMT_MEM_SIZE_CH1_S))
+#define RMT_MEM_SIZE_CH1_V  0xF
+#define RMT_MEM_SIZE_CH1_S  24
+/* RMT_IDLE_THRES_CH1 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel1.*/
+#define RMT_IDLE_THRES_CH1  0x0000FFFF
+#define RMT_IDLE_THRES_CH1_M  ((RMT_IDLE_THRES_CH1_V)<<(RMT_IDLE_THRES_CH1_S))
+#define RMT_IDLE_THRES_CH1_V  0xFFFF
+#define RMT_IDLE_THRES_CH1_S  8
+/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel1.*/
+#define RMT_DIV_CNT_CH1  0x000000FF
+#define RMT_DIV_CNT_CH1_M  ((RMT_DIV_CNT_CH1_V)<<(RMT_DIV_CNT_CH1_S))
+#define RMT_DIV_CNT_CH1_V  0xFF
+#define RMT_DIV_CNT_CH1_S  0
+
+#define RMT_CH1CONF1_REG          (DR_REG_RMT_BASE + 0x002c)
+/* RMT_TX_STOP_CH1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH1  (BIT(20))
+#define RMT_TX_STOP_CH1_M  (BIT(20))
+#define RMT_TX_STOP_CH1_V  0x1
+#define RMT_TX_STOP_CH1_S  20
+/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel1 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH1  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH1_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH1_V  0x1
+#define RMT_IDLE_OUT_EN_CH1_S  19
+/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel1 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH1  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH1_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH1_V  0x1
+#define RMT_IDLE_OUT_LV_CH1_S  18
+/* RMT_REF_ALWAYS_ON_CH1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH1  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH1_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH1_V  0x1
+#define RMT_REF_ALWAYS_ON_CH1_S  17
+/* RMT_RX_FILTER_THRES_CH1 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel1 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH1  0x000000FF
+#define RMT_RX_FILTER_THRES_CH1_M  ((RMT_RX_FILTER_THRES_CH1_V)<<(RMT_RX_FILTER_THRES_CH1_S))
+#define RMT_RX_FILTER_THRES_CH1_V  0xFF
+#define RMT_RX_FILTER_THRES_CH1_S  8
+/* RMT_RX_FILTER_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel1.*/
+#define RMT_RX_FILTER_EN_CH1  (BIT(7))
+#define RMT_RX_FILTER_EN_CH1_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH1_V  0x1
+#define RMT_RX_FILTER_EN_CH1_S  7
+/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel1 again and again.*/
+#define RMT_TX_CONTI_MODE_CH1  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH1_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH1_V  0x1
+#define RMT_TX_CONTI_MODE_CH1_S  6
+/* RMT_MEM_OWNER_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel1's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH1  (BIT(5))
+#define RMT_MEM_OWNER_CH1_M  (BIT(5))
+#define RMT_MEM_OWNER_CH1_V  0x1
+#define RMT_MEM_OWNER_CH1_S  5
+/* RMT_APB_MEM_RST_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel1 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH1  (BIT(4))
+#define RMT_APB_MEM_RST_CH1_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH1_V  0x1
+#define RMT_APB_MEM_RST_CH1_S  4
+/* RMT_MEM_RD_RST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel1 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH1  (BIT(3))
+#define RMT_MEM_RD_RST_CH1_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH1_V  0x1
+#define RMT_MEM_RD_RST_CH1_S  3
+/* RMT_MEM_WR_RST_CH1 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel1 by receiver access.*/
+#define RMT_MEM_WR_RST_CH1  (BIT(2))
+#define RMT_MEM_WR_RST_CH1_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH1_V  0x1
+#define RMT_MEM_WR_RST_CH1_S  2
+/* RMT_RX_EN_CH1 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel1.*/
+#define RMT_RX_EN_CH1  (BIT(1))
+#define RMT_RX_EN_CH1_M  (BIT(1))
+#define RMT_RX_EN_CH1_V  0x1
+#define RMT_RX_EN_CH1_S  1
+/* RMT_TX_START_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel1.*/
+#define RMT_TX_START_CH1  (BIT(0))
+#define RMT_TX_START_CH1_M  (BIT(0))
+#define RMT_TX_START_CH1_V  0x1
+#define RMT_TX_START_CH1_S  0
+
+#define RMT_CH2CONF0_REG          (DR_REG_RMT_BASE + 0x0030)
+/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel2.1'b1:add
+ on low level  1'b0:add  on high level.*/
+#define RMT_CARRIER_OUT_LV_CH2  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH2_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH2_V  0x1
+#define RMT_CARRIER_OUT_LV_CH2_S  29
+/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel2.*/
+#define RMT_CARRIER_EN_CH2  (BIT(28))
+#define RMT_CARRIER_EN_CH2_M  (BIT(28))
+#define RMT_CARRIER_EN_CH2_V  0x1
+#define RMT_CARRIER_EN_CH2_S  28
+/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel2.*/
+#define RMT_MEM_SIZE_CH2  0x0000000F
+#define RMT_MEM_SIZE_CH2_M  ((RMT_MEM_SIZE_CH2_V)<<(RMT_MEM_SIZE_CH2_S))
+#define RMT_MEM_SIZE_CH2_V  0xF
+#define RMT_MEM_SIZE_CH2_S  24
+/* RMT_IDLE_THRES_CH2 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch2
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH2  0x0000FFFF
+#define RMT_IDLE_THRES_CH2_M  ((RMT_IDLE_THRES_CH2_V)<<(RMT_IDLE_THRES_CH2_S))
+#define RMT_IDLE_THRES_CH2_V  0xFFFF
+#define RMT_IDLE_THRES_CH2_S  8
+/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel2.*/
+#define RMT_DIV_CNT_CH2  0x000000FF
+#define RMT_DIV_CNT_CH2_M  ((RMT_DIV_CNT_CH2_V)<<(RMT_DIV_CNT_CH2_S))
+#define RMT_DIV_CNT_CH2_V  0xFF
+#define RMT_DIV_CNT_CH2_S  0
+
+#define RMT_CH2CONF1_REG          (DR_REG_RMT_BASE + 0x0034)
+/* RMT_TX_STOP_CH2 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH2  (BIT(20))
+#define RMT_TX_STOP_CH2_M  (BIT(20))
+#define RMT_TX_STOP_CH2_V  0x1
+#define RMT_TX_STOP_CH2_S  20
+/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel2 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH2  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH2_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH2_V  0x1
+#define RMT_IDLE_OUT_EN_CH2_S  19
+/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel2 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH2  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH2_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH2_V  0x1
+#define RMT_IDLE_OUT_LV_CH2_S  18
+/* RMT_REF_ALWAYS_ON_CH2 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH2  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH2_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH2_V  0x1
+#define RMT_REF_ALWAYS_ON_CH2_S  17
+/* RMT_RX_FILTER_THRES_CH2 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel2 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH2  0x000000FF
+#define RMT_RX_FILTER_THRES_CH2_M  ((RMT_RX_FILTER_THRES_CH2_V)<<(RMT_RX_FILTER_THRES_CH2_S))
+#define RMT_RX_FILTER_THRES_CH2_V  0xFF
+#define RMT_RX_FILTER_THRES_CH2_S  8
+/* RMT_RX_FILTER_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel2.*/
+#define RMT_RX_FILTER_EN_CH2  (BIT(7))
+#define RMT_RX_FILTER_EN_CH2_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH2_V  0x1
+#define RMT_RX_FILTER_EN_CH2_S  7
+/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel2.*/
+#define RMT_TX_CONTI_MODE_CH2  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH2_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH2_V  0x1
+#define RMT_TX_CONTI_MODE_CH2_S  6
+/* RMT_MEM_OWNER_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel2's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH2  (BIT(5))
+#define RMT_MEM_OWNER_CH2_M  (BIT(5))
+#define RMT_MEM_OWNER_CH2_V  0x1
+#define RMT_MEM_OWNER_CH2_S  5
+/* RMT_APB_MEM_RST_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel2 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH2  (BIT(4))
+#define RMT_APB_MEM_RST_CH2_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH2_V  0x1
+#define RMT_APB_MEM_RST_CH2_S  4
+/* RMT_MEM_RD_RST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel2 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH2  (BIT(3))
+#define RMT_MEM_RD_RST_CH2_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH2_V  0x1
+#define RMT_MEM_RD_RST_CH2_S  3
+/* RMT_MEM_WR_RST_CH2 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel2 by receiver access.*/
+#define RMT_MEM_WR_RST_CH2  (BIT(2))
+#define RMT_MEM_WR_RST_CH2_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH2_V  0x1
+#define RMT_MEM_WR_RST_CH2_S  2
+/* RMT_RX_EN_CH2 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel2.*/
+#define RMT_RX_EN_CH2  (BIT(1))
+#define RMT_RX_EN_CH2_M  (BIT(1))
+#define RMT_RX_EN_CH2_V  0x1
+#define RMT_RX_EN_CH2_S  1
+/* RMT_TX_START_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel2.*/
+#define RMT_TX_START_CH2  (BIT(0))
+#define RMT_TX_START_CH2_M  (BIT(0))
+#define RMT_TX_START_CH2_V  0x1
+#define RMT_TX_START_CH2_S  0
+
+#define RMT_CH3CONF0_REG          (DR_REG_RMT_BASE + 0x0038)
+/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel3.1'b1:add
+ on low level  1'b0:add  on high level.*/
+#define RMT_CARRIER_OUT_LV_CH3  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH3_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH3_V  0x1
+#define RMT_CARRIER_OUT_LV_CH3_S  29
+/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel3.*/
+#define RMT_CARRIER_EN_CH3  (BIT(28))
+#define RMT_CARRIER_EN_CH3_M  (BIT(28))
+#define RMT_CARRIER_EN_CH3_V  0x1
+#define RMT_CARRIER_EN_CH3_S  28
+/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel3.*/
+#define RMT_MEM_SIZE_CH3  0x0000000F
+#define RMT_MEM_SIZE_CH3_M  ((RMT_MEM_SIZE_CH3_V)<<(RMT_MEM_SIZE_CH3_S))
+#define RMT_MEM_SIZE_CH3_V  0xF
+#define RMT_MEM_SIZE_CH3_S  24
+/* RMT_IDLE_THRES_CH3 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch3
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH3  0x0000FFFF
+#define RMT_IDLE_THRES_CH3_M  ((RMT_IDLE_THRES_CH3_V)<<(RMT_IDLE_THRES_CH3_S))
+#define RMT_IDLE_THRES_CH3_V  0xFFFF
+#define RMT_IDLE_THRES_CH3_S  8
+/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel3.*/
+#define RMT_DIV_CNT_CH3  0x000000FF
+#define RMT_DIV_CNT_CH3_M  ((RMT_DIV_CNT_CH3_V)<<(RMT_DIV_CNT_CH3_S))
+#define RMT_DIV_CNT_CH3_V  0xFF
+#define RMT_DIV_CNT_CH3_S  0
+
+#define RMT_CH3CONF1_REG          (DR_REG_RMT_BASE + 0x003c)
+/* RMT_TX_STOP_CH3 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH3  (BIT(20))
+#define RMT_TX_STOP_CH3_M  (BIT(20))
+#define RMT_TX_STOP_CH3_V  0x1
+#define RMT_TX_STOP_CH3_S  20
+/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel3 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH3  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH3_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH3_V  0x1
+#define RMT_IDLE_OUT_EN_CH3_S  19
+/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel3 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH3  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH3_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH3_V  0x1
+#define RMT_IDLE_OUT_LV_CH3_S  18
+/* RMT_REF_ALWAYS_ON_CH3 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH3  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH3_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH3_V  0x1
+#define RMT_REF_ALWAYS_ON_CH3_S  17
+/* RMT_RX_FILTER_THRES_CH3 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel3 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH3  0x000000FF
+#define RMT_RX_FILTER_THRES_CH3_M  ((RMT_RX_FILTER_THRES_CH3_V)<<(RMT_RX_FILTER_THRES_CH3_S))
+#define RMT_RX_FILTER_THRES_CH3_V  0xFF
+#define RMT_RX_FILTER_THRES_CH3_S  8
+/* RMT_RX_FILTER_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel3.*/
+#define RMT_RX_FILTER_EN_CH3  (BIT(7))
+#define RMT_RX_FILTER_EN_CH3_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH3_V  0x1
+#define RMT_RX_FILTER_EN_CH3_S  7
+/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel3.*/
+#define RMT_TX_CONTI_MODE_CH3  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH3_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH3_V  0x1
+#define RMT_TX_CONTI_MODE_CH3_S  6
+/* RMT_MEM_OWNER_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel3's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH3  (BIT(5))
+#define RMT_MEM_OWNER_CH3_M  (BIT(5))
+#define RMT_MEM_OWNER_CH3_V  0x1
+#define RMT_MEM_OWNER_CH3_S  5
+/* RMT_APB_MEM_RST_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel3 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH3  (BIT(4))
+#define RMT_APB_MEM_RST_CH3_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH3_V  0x1
+#define RMT_APB_MEM_RST_CH3_S  4
+/* RMT_MEM_RD_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel3 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH3  (BIT(3))
+#define RMT_MEM_RD_RST_CH3_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH3_V  0x1
+#define RMT_MEM_RD_RST_CH3_S  3
+/* RMT_MEM_WR_RST_CH3 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel3 by receiver access.*/
+#define RMT_MEM_WR_RST_CH3  (BIT(2))
+#define RMT_MEM_WR_RST_CH3_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH3_V  0x1
+#define RMT_MEM_WR_RST_CH3_S  2
+/* RMT_RX_EN_CH3 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel3.*/
+#define RMT_RX_EN_CH3  (BIT(1))
+#define RMT_RX_EN_CH3_M  (BIT(1))
+#define RMT_RX_EN_CH3_V  0x1
+#define RMT_RX_EN_CH3_S  1
+/* RMT_TX_START_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel3.*/
+#define RMT_TX_START_CH3  (BIT(0))
+#define RMT_TX_START_CH3_M  (BIT(0))
+#define RMT_TX_START_CH3_V  0x1
+#define RMT_TX_START_CH3_S  0
+
+#define RMT_CH4CONF0_REG          (DR_REG_RMT_BASE + 0x0040)
+/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel4.1'b1:add
+ on low level  1'b0:add  on high level.*/
+#define RMT_CARRIER_OUT_LV_CH4  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH4_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH4_V  0x1
+#define RMT_CARRIER_OUT_LV_CH4_S  29
+/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel4.*/
+#define RMT_CARRIER_EN_CH4  (BIT(28))
+#define RMT_CARRIER_EN_CH4_M  (BIT(28))
+#define RMT_CARRIER_EN_CH4_V  0x1
+#define RMT_CARRIER_EN_CH4_S  28
+/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel4.*/
+#define RMT_MEM_SIZE_CH4  0x0000000F
+#define RMT_MEM_SIZE_CH4_M  ((RMT_MEM_SIZE_CH4_V)<<(RMT_MEM_SIZE_CH4_S))
+#define RMT_MEM_SIZE_CH4_V  0xF
+#define RMT_MEM_SIZE_CH4_S  24
+/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch4
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH4  0x0000FFFF
+#define RMT_IDLE_THRES_CH4_M  ((RMT_IDLE_THRES_CH4_V)<<(RMT_IDLE_THRES_CH4_S))
+#define RMT_IDLE_THRES_CH4_V  0xFFFF
+#define RMT_IDLE_THRES_CH4_S  8
+/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel4.*/
+#define RMT_DIV_CNT_CH4  0x000000FF
+#define RMT_DIV_CNT_CH4_M  ((RMT_DIV_CNT_CH4_V)<<(RMT_DIV_CNT_CH4_S))
+#define RMT_DIV_CNT_CH4_V  0xFF
+#define RMT_DIV_CNT_CH4_S  0
+
+#define RMT_CH4CONF1_REG          (DR_REG_RMT_BASE + 0x0044)
+/* RMT_TX_STOP_CH4 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH4  (BIT(20))
+#define RMT_TX_STOP_CH4_M  (BIT(20))
+#define RMT_TX_STOP_CH4_V  0x1
+#define RMT_TX_STOP_CH4_S  20
+/* RMT_IDLE_OUT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel4 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH4  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH4_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH4_V  0x1
+#define RMT_IDLE_OUT_EN_CH4_S  19
+/* RMT_IDLE_OUT_LV_CH4 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel4 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH4  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH4_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH4_V  0x1
+#define RMT_IDLE_OUT_LV_CH4_S  18
+/* RMT_REF_ALWAYS_ON_CH4 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH4  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH4_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH4_V  0x1
+#define RMT_REF_ALWAYS_ON_CH4_S  17
+/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel4 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH4  0x000000FF
+#define RMT_RX_FILTER_THRES_CH4_M  ((RMT_RX_FILTER_THRES_CH4_V)<<(RMT_RX_FILTER_THRES_CH4_S))
+#define RMT_RX_FILTER_THRES_CH4_V  0xFF
+#define RMT_RX_FILTER_THRES_CH4_S  8
+/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel4.*/
+#define RMT_RX_FILTER_EN_CH4  (BIT(7))
+#define RMT_RX_FILTER_EN_CH4_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH4_V  0x1
+#define RMT_RX_FILTER_EN_CH4_S  7
+/* RMT_TX_CONTI_MODE_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel4.*/
+#define RMT_TX_CONTI_MODE_CH4  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH4_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH4_V  0x1
+#define RMT_TX_CONTI_MODE_CH4_S  6
+/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel4's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH4  (BIT(5))
+#define RMT_MEM_OWNER_CH4_M  (BIT(5))
+#define RMT_MEM_OWNER_CH4_V  0x1
+#define RMT_MEM_OWNER_CH4_S  5
+/* RMT_APB_MEM_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel4 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH4  (BIT(4))
+#define RMT_APB_MEM_RST_CH4_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH4_V  0x1
+#define RMT_APB_MEM_RST_CH4_S  4
+/* RMT_MEM_RD_RST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel4 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH4  (BIT(3))
+#define RMT_MEM_RD_RST_CH4_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH4_V  0x1
+#define RMT_MEM_RD_RST_CH4_S  3
+/* RMT_MEM_WR_RST_CH4 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel4 by receiver access.*/
+#define RMT_MEM_WR_RST_CH4  (BIT(2))
+#define RMT_MEM_WR_RST_CH4_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH4_V  0x1
+#define RMT_MEM_WR_RST_CH4_S  2
+/* RMT_RX_EN_CH4 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel4.*/
+#define RMT_RX_EN_CH4  (BIT(1))
+#define RMT_RX_EN_CH4_M  (BIT(1))
+#define RMT_RX_EN_CH4_V  0x1
+#define RMT_RX_EN_CH4_S  1
+/* RMT_TX_START_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel4.*/
+#define RMT_TX_START_CH4  (BIT(0))
+#define RMT_TX_START_CH4_M  (BIT(0))
+#define RMT_TX_START_CH4_V  0x1
+#define RMT_TX_START_CH4_S  0
+
+#define RMT_CH5CONF0_REG          (DR_REG_RMT_BASE + 0x0048)
+/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel5.1'b1:add
+ on low level  1'b0:add  on high level.*/
+#define RMT_CARRIER_OUT_LV_CH5  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH5_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH5_V  0x1
+#define RMT_CARRIER_OUT_LV_CH5_S  29
+/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel5.*/
+#define RMT_CARRIER_EN_CH5  (BIT(28))
+#define RMT_CARRIER_EN_CH5_M  (BIT(28))
+#define RMT_CARRIER_EN_CH5_V  0x1
+#define RMT_CARRIER_EN_CH5_S  28
+/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel5.*/
+#define RMT_MEM_SIZE_CH5  0x0000000F
+#define RMT_MEM_SIZE_CH5_M  ((RMT_MEM_SIZE_CH5_V)<<(RMT_MEM_SIZE_CH5_S))
+#define RMT_MEM_SIZE_CH5_V  0xF
+#define RMT_MEM_SIZE_CH5_S  24
+/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch5
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH5  0x0000FFFF
+#define RMT_IDLE_THRES_CH5_M  ((RMT_IDLE_THRES_CH5_V)<<(RMT_IDLE_THRES_CH5_S))
+#define RMT_IDLE_THRES_CH5_V  0xFFFF
+#define RMT_IDLE_THRES_CH5_S  8
+/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel5.*/
+#define RMT_DIV_CNT_CH5  0x000000FF
+#define RMT_DIV_CNT_CH5_M  ((RMT_DIV_CNT_CH5_V)<<(RMT_DIV_CNT_CH5_S))
+#define RMT_DIV_CNT_CH5_V  0xFF
+#define RMT_DIV_CNT_CH5_S  0
+
+#define RMT_CH5CONF1_REG          (DR_REG_RMT_BASE + 0x004c)
+/* RMT_TX_STOP_CH5 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH5  (BIT(20))
+#define RMT_TX_STOP_CH5_M  (BIT(20))
+#define RMT_TX_STOP_CH5_V  0x1
+#define RMT_TX_STOP_CH5_S  20
+/* RMT_IDLE_OUT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel5 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH5  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH5_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH5_V  0x1
+#define RMT_IDLE_OUT_EN_CH5_S  19
+/* RMT_IDLE_OUT_LV_CH5 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel5 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH5  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH5_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH5_V  0x1
+#define RMT_IDLE_OUT_LV_CH5_S  18
+/* RMT_REF_ALWAYS_ON_CH5 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH5  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH5_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH5_V  0x1
+#define RMT_REF_ALWAYS_ON_CH5_S  17
+/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel5 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH5  0x000000FF
+#define RMT_RX_FILTER_THRES_CH5_M  ((RMT_RX_FILTER_THRES_CH5_V)<<(RMT_RX_FILTER_THRES_CH5_S))
+#define RMT_RX_FILTER_THRES_CH5_V  0xFF
+#define RMT_RX_FILTER_THRES_CH5_S  8
+/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel5.*/
+#define RMT_RX_FILTER_EN_CH5  (BIT(7))
+#define RMT_RX_FILTER_EN_CH5_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH5_V  0x1
+#define RMT_RX_FILTER_EN_CH5_S  7
+/* RMT_TX_CONTI_MODE_CH5 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel5.*/
+#define RMT_TX_CONTI_MODE_CH5  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH5_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH5_V  0x1
+#define RMT_TX_CONTI_MODE_CH5_S  6
+/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel5's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH5  (BIT(5))
+#define RMT_MEM_OWNER_CH5_M  (BIT(5))
+#define RMT_MEM_OWNER_CH5_V  0x1
+#define RMT_MEM_OWNER_CH5_S  5
+/* RMT_APB_MEM_RST_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel5 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH5  (BIT(4))
+#define RMT_APB_MEM_RST_CH5_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH5_V  0x1
+#define RMT_APB_MEM_RST_CH5_S  4
+/* RMT_MEM_RD_RST_CH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel5 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH5  (BIT(3))
+#define RMT_MEM_RD_RST_CH5_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH5_V  0x1
+#define RMT_MEM_RD_RST_CH5_S  3
+/* RMT_MEM_WR_RST_CH5 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel5 by receiver access.*/
+#define RMT_MEM_WR_RST_CH5  (BIT(2))
+#define RMT_MEM_WR_RST_CH5_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH5_V  0x1
+#define RMT_MEM_WR_RST_CH5_S  2
+/* RMT_RX_EN_CH5 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel5.*/
+#define RMT_RX_EN_CH5  (BIT(1))
+#define RMT_RX_EN_CH5_M  (BIT(1))
+#define RMT_RX_EN_CH5_V  0x1
+#define RMT_RX_EN_CH5_S  1
+/* RMT_TX_START_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel5.*/
+#define RMT_TX_START_CH5  (BIT(0))
+#define RMT_TX_START_CH5_M  (BIT(0))
+#define RMT_TX_START_CH5_V  0x1
+#define RMT_TX_START_CH5_S  0
+
+#define RMT_CH6CONF0_REG          (DR_REG_RMT_BASE + 0x0050)
+/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel6.1'b1:add
+ on low level  1'b0:add  on high level.*/
+#define RMT_CARRIER_OUT_LV_CH6  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH6_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH6_V  0x1
+#define RMT_CARRIER_OUT_LV_CH6_S  29
+/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel6.*/
+#define RMT_CARRIER_EN_CH6  (BIT(28))
+#define RMT_CARRIER_EN_CH6_M  (BIT(28))
+#define RMT_CARRIER_EN_CH6_V  0x1
+#define RMT_CARRIER_EN_CH6_S  28
+/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel6.*/
+#define RMT_MEM_SIZE_CH6  0x0000000F
+#define RMT_MEM_SIZE_CH6_M  ((RMT_MEM_SIZE_CH6_V)<<(RMT_MEM_SIZE_CH6_S))
+#define RMT_MEM_SIZE_CH6_V  0xF
+#define RMT_MEM_SIZE_CH6_S  24
+/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch6
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH6  0x0000FFFF
+#define RMT_IDLE_THRES_CH6_M  ((RMT_IDLE_THRES_CH6_V)<<(RMT_IDLE_THRES_CH6_S))
+#define RMT_IDLE_THRES_CH6_V  0xFFFF
+#define RMT_IDLE_THRES_CH6_S  8
+/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel6.*/
+#define RMT_DIV_CNT_CH6  0x000000FF
+#define RMT_DIV_CNT_CH6_M  ((RMT_DIV_CNT_CH6_V)<<(RMT_DIV_CNT_CH6_S))
+#define RMT_DIV_CNT_CH6_V  0xFF
+#define RMT_DIV_CNT_CH6_S  0
+
+#define RMT_CH6CONF1_REG          (DR_REG_RMT_BASE + 0x0054)
+/* RMT_TX_STOP_CH6 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH6  (BIT(20))
+#define RMT_TX_STOP_CH6_M  (BIT(20))
+#define RMT_TX_STOP_CH6_V  0x1
+#define RMT_TX_STOP_CH6_S  20
+/* RMT_IDLE_OUT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel6 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH6  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH6_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH6_V  0x1
+#define RMT_IDLE_OUT_EN_CH6_S  19
+/* RMT_IDLE_OUT_LV_CH6 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel6 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH6  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH6_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH6_V  0x1
+#define RMT_IDLE_OUT_LV_CH6_S  18
+/* RMT_REF_ALWAYS_ON_CH6 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH6  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH6_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH6_V  0x1
+#define RMT_REF_ALWAYS_ON_CH6_S  17
+/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel6 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH6  0x000000FF
+#define RMT_RX_FILTER_THRES_CH6_M  ((RMT_RX_FILTER_THRES_CH6_V)<<(RMT_RX_FILTER_THRES_CH6_S))
+#define RMT_RX_FILTER_THRES_CH6_V  0xFF
+#define RMT_RX_FILTER_THRES_CH6_S  8
+/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel6.*/
+#define RMT_RX_FILTER_EN_CH6  (BIT(7))
+#define RMT_RX_FILTER_EN_CH6_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH6_V  0x1
+#define RMT_RX_FILTER_EN_CH6_S  7
+/* RMT_TX_CONTI_MODE_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel6.*/
+#define RMT_TX_CONTI_MODE_CH6  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH6_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH6_V  0x1
+#define RMT_TX_CONTI_MODE_CH6_S  6
+/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel6's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH6  (BIT(5))
+#define RMT_MEM_OWNER_CH6_M  (BIT(5))
+#define RMT_MEM_OWNER_CH6_V  0x1
+#define RMT_MEM_OWNER_CH6_S  5
+/* RMT_APB_MEM_RST_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel6 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH6  (BIT(4))
+#define RMT_APB_MEM_RST_CH6_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH6_V  0x1
+#define RMT_APB_MEM_RST_CH6_S  4
+/* RMT_MEM_RD_RST_CH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel6 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH6  (BIT(3))
+#define RMT_MEM_RD_RST_CH6_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH6_V  0x1
+#define RMT_MEM_RD_RST_CH6_S  3
+/* RMT_MEM_WR_RST_CH6 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel6 by receiver access.*/
+#define RMT_MEM_WR_RST_CH6  (BIT(2))
+#define RMT_MEM_WR_RST_CH6_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH6_V  0x1
+#define RMT_MEM_WR_RST_CH6_S  2
+/* RMT_RX_EN_CH6 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel6.*/
+#define RMT_RX_EN_CH6  (BIT(1))
+#define RMT_RX_EN_CH6_M  (BIT(1))
+#define RMT_RX_EN_CH6_V  0x1
+#define RMT_RX_EN_CH6_S  1
+/* RMT_TX_START_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel6.*/
+#define RMT_TX_START_CH6  (BIT(0))
+#define RMT_TX_START_CH6_M  (BIT(0))
+#define RMT_TX_START_CH6_V  0x1
+#define RMT_TX_START_CH6_S  0
+
+#define RMT_CH7CONF0_REG          (DR_REG_RMT_BASE + 0x0058)
+/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: This bit is used to configure carrier wave's position for channel7.1'b1:add
+ on low level  1'b0:add  on high level.*/
+#define RMT_CARRIER_OUT_LV_CH7  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH7_M  (BIT(29))
+#define RMT_CARRIER_OUT_LV_CH7_V  0x1
+#define RMT_CARRIER_OUT_LV_CH7_S  29
+/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: This is the carrier modulation enable control bit for channel7.*/
+#define RMT_CARRIER_EN_CH7  (BIT(28))
+#define RMT_CARRIER_EN_CH7_M  (BIT(28))
+#define RMT_CARRIER_EN_CH7_V  0x1
+#define RMT_CARRIER_EN_CH7_S  28
+/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */
+/*description: This register is used to configure the the amount of memory blocks
+ allocated to channel7.*/
+#define RMT_MEM_SIZE_CH7  0x0000000F
+#define RMT_MEM_SIZE_CH7_M  ((RMT_MEM_SIZE_CH7_V)<<(RMT_MEM_SIZE_CH7_S))
+#define RMT_MEM_SIZE_CH7_V  0xF
+#define RMT_MEM_SIZE_CH7_S  24
+/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[23:8] ;default: 16'h1000 ; */
+/*description: In receive mode when the counter's value is bigger than reg_idle_thres_ch7
+ then the receive process is done.*/
+#define RMT_IDLE_THRES_CH7  0x0000FFFF
+#define RMT_IDLE_THRES_CH7_M  ((RMT_IDLE_THRES_CH7_V)<<(RMT_IDLE_THRES_CH7_S))
+#define RMT_IDLE_THRES_CH7_V  0xFFFF
+#define RMT_IDLE_THRES_CH7_S  8
+/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */
+/*description: This register is used to configure the  frequency divider's factor in channel7.*/
+#define RMT_DIV_CNT_CH7  0x000000FF
+#define RMT_DIV_CNT_CH7_M  ((RMT_DIV_CNT_CH7_V)<<(RMT_DIV_CNT_CH7_S))
+#define RMT_DIV_CNT_CH7_V  0xFF
+#define RMT_DIV_CNT_CH7_S  0
+
+#define RMT_CH7CONF1_REG          (DR_REG_RMT_BASE + 0x005c)
+/* RMT_TX_STOP_CH7 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_STOP_CH7  (BIT(20))
+#define RMT_TX_STOP_CH7_M  (BIT(20))
+#define RMT_TX_STOP_CH7_V  0x1
+#define RMT_TX_STOP_CH7_S  20
+/* RMT_IDLE_OUT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: This is the output enable control bit for channel6 in IDLE state.*/
+#define RMT_IDLE_OUT_EN_CH7  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH7_M  (BIT(19))
+#define RMT_IDLE_OUT_EN_CH7_V  0x1
+#define RMT_IDLE_OUT_EN_CH7_S  19
+/* RMT_IDLE_OUT_LV_CH7 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: This bit configures the output signal's level for channel7 in IDLE state.*/
+#define RMT_IDLE_OUT_LV_CH7  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH7_M  (BIT(18))
+#define RMT_IDLE_OUT_LV_CH7_V  0x1
+#define RMT_IDLE_OUT_LV_CH7_S  18
+/* RMT_REF_ALWAYS_ON_CH7 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+#define RMT_REF_ALWAYS_ON_CH7  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH7_M  (BIT(17))
+#define RMT_REF_ALWAYS_ON_CH7_V  0x1
+#define RMT_REF_ALWAYS_ON_CH7_S  17
+/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[15:8] ;default: 8'hf ; */
+/*description: in receive mode  channel7 ignore input pulse when the pulse width
+ is smaller then this value.*/
+#define RMT_RX_FILTER_THRES_CH7  0x000000FF
+#define RMT_RX_FILTER_THRES_CH7_M  ((RMT_RX_FILTER_THRES_CH7_V)<<(RMT_RX_FILTER_THRES_CH7_S))
+#define RMT_RX_FILTER_THRES_CH7_V  0xFF
+#define RMT_RX_FILTER_THRES_CH7_S  8
+/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: This is the receive filter enable bit for channel7.*/
+#define RMT_RX_FILTER_EN_CH7  (BIT(7))
+#define RMT_RX_FILTER_EN_CH7_M  (BIT(7))
+#define RMT_RX_FILTER_EN_CH7_V  0x1
+#define RMT_RX_FILTER_EN_CH7_S  7
+/* RMT_TX_CONTI_MODE_CH7 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to continue sending  from the first data to the
+ last data in channel7.*/
+#define RMT_TX_CONTI_MODE_CH7  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH7_M  (BIT(6))
+#define RMT_TX_CONTI_MODE_CH7_V  0x1
+#define RMT_TX_CONTI_MODE_CH7_S  6
+/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: This is the mark of channel7's ram usage right.1'b1：receiver
+ uses the ram  0：transmitter uses the ram*/
+#define RMT_MEM_OWNER_CH7  (BIT(5))
+#define RMT_MEM_OWNER_CH7_M  (BIT(5))
+#define RMT_MEM_OWNER_CH7_V  0x1
+#define RMT_MEM_OWNER_CH7_S  5
+/* RMT_APB_MEM_RST_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to reset W/R ram address for channel7 by apb fifo access*/
+#define RMT_APB_MEM_RST_CH7  (BIT(4))
+#define RMT_APB_MEM_RST_CH7_M  (BIT(4))
+#define RMT_APB_MEM_RST_CH7_V  0x1
+#define RMT_APB_MEM_RST_CH7_S  4
+/* RMT_MEM_RD_RST_CH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to reset read ram address for channel7 by transmitter access.*/
+#define RMT_MEM_RD_RST_CH7  (BIT(3))
+#define RMT_MEM_RD_RST_CH7_M  (BIT(3))
+#define RMT_MEM_RD_RST_CH7_V  0x1
+#define RMT_MEM_RD_RST_CH7_S  3
+/* RMT_MEM_WR_RST_CH7 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: Set this bit to reset write ram address for channel7 by receiver access.*/
+#define RMT_MEM_WR_RST_CH7  (BIT(2))
+#define RMT_MEM_WR_RST_CH7_M  (BIT(2))
+#define RMT_MEM_WR_RST_CH7_V  0x1
+#define RMT_MEM_WR_RST_CH7_S  2
+/* RMT_RX_EN_CH7 : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: Set this bit to enbale receving data for channel7.*/
+#define RMT_RX_EN_CH7  (BIT(1))
+#define RMT_RX_EN_CH7_M  (BIT(1))
+#define RMT_RX_EN_CH7_V  0x1
+#define RMT_RX_EN_CH7_S  1
+/* RMT_TX_START_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to start sending data for channel7.*/
+#define RMT_TX_START_CH7  (BIT(0))
+#define RMT_TX_START_CH7_M  (BIT(0))
+#define RMT_TX_START_CH7_V  0x1
+#define RMT_TX_START_CH7_S  0
+
+#define RMT_CH0STATUS_REG          (DR_REG_RMT_BASE + 0x0060)
+/* RMT_APB_MEM_RD_ERR_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH0  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH0_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH0_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH0_S  27
+/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH0  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH0_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH0_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH0_S  26
+/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH0  (BIT(25))
+#define RMT_MEM_EMPTY_CH0_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH0_V  0x1
+#define RMT_MEM_EMPTY_CH0_S  25
+/* RMT_MEM_FULL_CH0 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH0  (BIT(24))
+#define RMT_MEM_FULL_CH0_M  (BIT(24))
+#define RMT_MEM_FULL_CH0_V  0x1
+#define RMT_MEM_FULL_CH0_S  24
+/* RMT_MEM_OWNER_ERR_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH0  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH0_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH0_V  0x1
+#define RMT_MEM_OWNER_ERR_CH0_S  23
+/* RMT_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH0  0x00000007
+#define RMT_STATE_CH0_M  ((RMT_STATE_CH0_V)<<(RMT_STATE_CH0_S))
+#define RMT_STATE_CH0_V  0x7
+#define RMT_STATE_CH0_S  20
+/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH0  0x000003FF
+#define RMT_MEM_RADDR_EX_CH0_M  ((RMT_MEM_RADDR_EX_CH0_V)<<(RMT_MEM_RADDR_EX_CH0_S))
+#define RMT_MEM_RADDR_EX_CH0_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH0_S  10
+/* RMT_MEM_WADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH0  0x000003FF
+#define RMT_MEM_WADDR_EX_CH0_M  ((RMT_MEM_WADDR_EX_CH0_V)<<(RMT_MEM_WADDR_EX_CH0_S))
+#define RMT_MEM_WADDR_EX_CH0_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH0_S  0
+
+#define RMT_CH1STATUS_REG          (DR_REG_RMT_BASE + 0x0064)
+/* RMT_APB_MEM_RD_ERR_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH1  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH1_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH1_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH1_S  27
+/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH1  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH1_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH1_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH1_S  26
+/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH1  (BIT(25))
+#define RMT_MEM_EMPTY_CH1_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH1_V  0x1
+#define RMT_MEM_EMPTY_CH1_S  25
+/* RMT_MEM_FULL_CH1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH1  (BIT(24))
+#define RMT_MEM_FULL_CH1_M  (BIT(24))
+#define RMT_MEM_FULL_CH1_V  0x1
+#define RMT_MEM_FULL_CH1_S  24
+/* RMT_MEM_OWNER_ERR_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH1  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH1_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH1_V  0x1
+#define RMT_MEM_OWNER_ERR_CH1_S  23
+/* RMT_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH1  0x00000007
+#define RMT_STATE_CH1_M  ((RMT_STATE_CH1_V)<<(RMT_STATE_CH1_S))
+#define RMT_STATE_CH1_V  0x7
+#define RMT_STATE_CH1_S  20
+/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH1  0x000003FF
+#define RMT_MEM_RADDR_EX_CH1_M  ((RMT_MEM_RADDR_EX_CH1_V)<<(RMT_MEM_RADDR_EX_CH1_S))
+#define RMT_MEM_RADDR_EX_CH1_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH1_S  10
+/* RMT_MEM_WADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH1  0x000003FF
+#define RMT_MEM_WADDR_EX_CH1_M  ((RMT_MEM_WADDR_EX_CH1_V)<<(RMT_MEM_WADDR_EX_CH1_S))
+#define RMT_MEM_WADDR_EX_CH1_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH1_S  0
+
+#define RMT_CH2STATUS_REG          (DR_REG_RMT_BASE + 0x0068)
+/* RMT_APB_MEM_RD_ERR_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH2  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH2_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH2_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH2_S  27
+/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH2  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH2_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH2_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH2_S  26
+/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH2  (BIT(25))
+#define RMT_MEM_EMPTY_CH2_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH2_V  0x1
+#define RMT_MEM_EMPTY_CH2_S  25
+/* RMT_MEM_FULL_CH2 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH2  (BIT(24))
+#define RMT_MEM_FULL_CH2_M  (BIT(24))
+#define RMT_MEM_FULL_CH2_V  0x1
+#define RMT_MEM_FULL_CH2_S  24
+/* RMT_MEM_OWNER_ERR_CH2 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH2  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH2_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH2_V  0x1
+#define RMT_MEM_OWNER_ERR_CH2_S  23
+/* RMT_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH2  0x00000007
+#define RMT_STATE_CH2_M  ((RMT_STATE_CH2_V)<<(RMT_STATE_CH2_S))
+#define RMT_STATE_CH2_V  0x7
+#define RMT_STATE_CH2_S  20
+/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH2  0x000003FF
+#define RMT_MEM_RADDR_EX_CH2_M  ((RMT_MEM_RADDR_EX_CH2_V)<<(RMT_MEM_RADDR_EX_CH2_S))
+#define RMT_MEM_RADDR_EX_CH2_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH2_S  10
+/* RMT_MEM_WADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH2  0x000003FF
+#define RMT_MEM_WADDR_EX_CH2_M  ((RMT_MEM_WADDR_EX_CH2_V)<<(RMT_MEM_WADDR_EX_CH2_S))
+#define RMT_MEM_WADDR_EX_CH2_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH2_S  0
+
+#define RMT_CH3STATUS_REG          (DR_REG_RMT_BASE + 0x006c)
+/* RMT_APB_MEM_RD_ERR_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH3  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH3_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH3_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH3_S  27
+/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH3  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH3_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH3_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH3_S  26
+/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH3  (BIT(25))
+#define RMT_MEM_EMPTY_CH3_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH3_V  0x1
+#define RMT_MEM_EMPTY_CH3_S  25
+/* RMT_MEM_FULL_CH3 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH3  (BIT(24))
+#define RMT_MEM_FULL_CH3_M  (BIT(24))
+#define RMT_MEM_FULL_CH3_V  0x1
+#define RMT_MEM_FULL_CH3_S  24
+/* RMT_MEM_OWNER_ERR_CH3 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH3  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH3_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH3_V  0x1
+#define RMT_MEM_OWNER_ERR_CH3_S  23
+/* RMT_STATE_CH3 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH3  0x00000007
+#define RMT_STATE_CH3_M  ((RMT_STATE_CH3_V)<<(RMT_STATE_CH3_S))
+#define RMT_STATE_CH3_V  0x7
+#define RMT_STATE_CH3_S  20
+/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH3  0x000003FF
+#define RMT_MEM_RADDR_EX_CH3_M  ((RMT_MEM_RADDR_EX_CH3_V)<<(RMT_MEM_RADDR_EX_CH3_S))
+#define RMT_MEM_RADDR_EX_CH3_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH3_S  10
+/* RMT_MEM_WADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH3  0x000003FF
+#define RMT_MEM_WADDR_EX_CH3_M  ((RMT_MEM_WADDR_EX_CH3_V)<<(RMT_MEM_WADDR_EX_CH3_S))
+#define RMT_MEM_WADDR_EX_CH3_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH3_S  0
+
+#define RMT_CH4STATUS_REG          (DR_REG_RMT_BASE + 0x0070)
+/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH4  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH4_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH4_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH4_S  27
+/* RMT_APB_MEM_WR_ERR_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH4  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH4_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH4_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH4_S  26
+/* RMT_MEM_EMPTY_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH4  (BIT(25))
+#define RMT_MEM_EMPTY_CH4_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH4_V  0x1
+#define RMT_MEM_EMPTY_CH4_S  25
+/* RMT_MEM_FULL_CH4 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH4  (BIT(24))
+#define RMT_MEM_FULL_CH4_M  (BIT(24))
+#define RMT_MEM_FULL_CH4_V  0x1
+#define RMT_MEM_FULL_CH4_S  24
+/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH4  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH4_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH4_V  0x1
+#define RMT_MEM_OWNER_ERR_CH4_S  23
+/* RMT_STATE_CH4 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH4  0x00000007
+#define RMT_STATE_CH4_M  ((RMT_STATE_CH4_V)<<(RMT_STATE_CH4_S))
+#define RMT_STATE_CH4_V  0x7
+#define RMT_STATE_CH4_S  20
+/* RMT_MEM_RADDR_EX_CH4 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH4  0x000003FF
+#define RMT_MEM_RADDR_EX_CH4_M  ((RMT_MEM_RADDR_EX_CH4_V)<<(RMT_MEM_RADDR_EX_CH4_S))
+#define RMT_MEM_RADDR_EX_CH4_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH4_S  10
+/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH4  0x000003FF
+#define RMT_MEM_WADDR_EX_CH4_M  ((RMT_MEM_WADDR_EX_CH4_V)<<(RMT_MEM_WADDR_EX_CH4_S))
+#define RMT_MEM_WADDR_EX_CH4_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH4_S  0
+
+#define RMT_CH5STATUS_REG          (DR_REG_RMT_BASE + 0x0074)
+/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH5  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH5_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH5_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH5_S  27
+/* RMT_APB_MEM_WR_ERR_CH5 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH5  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH5_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH5_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH5_S  26
+/* RMT_MEM_EMPTY_CH5 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH5  (BIT(25))
+#define RMT_MEM_EMPTY_CH5_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH5_V  0x1
+#define RMT_MEM_EMPTY_CH5_S  25
+/* RMT_MEM_FULL_CH5 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH5  (BIT(24))
+#define RMT_MEM_FULL_CH5_M  (BIT(24))
+#define RMT_MEM_FULL_CH5_V  0x1
+#define RMT_MEM_FULL_CH5_S  24
+/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH5  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH5_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH5_V  0x1
+#define RMT_MEM_OWNER_ERR_CH5_S  23
+/* RMT_STATE_CH5 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH5  0x00000007
+#define RMT_STATE_CH5_M  ((RMT_STATE_CH5_V)<<(RMT_STATE_CH5_S))
+#define RMT_STATE_CH5_V  0x7
+#define RMT_STATE_CH5_S  20
+/* RMT_MEM_RADDR_EX_CH5 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH5  0x000003FF
+#define RMT_MEM_RADDR_EX_CH5_M  ((RMT_MEM_RADDR_EX_CH5_V)<<(RMT_MEM_RADDR_EX_CH5_S))
+#define RMT_MEM_RADDR_EX_CH5_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH5_S  10
+/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH5  0x000003FF
+#define RMT_MEM_WADDR_EX_CH5_M  ((RMT_MEM_WADDR_EX_CH5_V)<<(RMT_MEM_WADDR_EX_CH5_S))
+#define RMT_MEM_WADDR_EX_CH5_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH5_S  0
+
+#define RMT_CH6STATUS_REG          (DR_REG_RMT_BASE + 0x0078)
+/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH6  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH6_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH6_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH6_S  27
+/* RMT_APB_MEM_WR_ERR_CH6 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH6  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH6_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH6_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH6_S  26
+/* RMT_MEM_EMPTY_CH6 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH6  (BIT(25))
+#define RMT_MEM_EMPTY_CH6_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH6_V  0x1
+#define RMT_MEM_EMPTY_CH6_S  25
+/* RMT_MEM_FULL_CH6 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH6  (BIT(24))
+#define RMT_MEM_FULL_CH6_M  (BIT(24))
+#define RMT_MEM_FULL_CH6_V  0x1
+#define RMT_MEM_FULL_CH6_S  24
+/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH6  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH6_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH6_V  0x1
+#define RMT_MEM_OWNER_ERR_CH6_S  23
+/* RMT_STATE_CH6 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH6  0x00000007
+#define RMT_STATE_CH6_M  ((RMT_STATE_CH6_V)<<(RMT_STATE_CH6_S))
+#define RMT_STATE_CH6_V  0x7
+#define RMT_STATE_CH6_S  20
+/* RMT_MEM_RADDR_EX_CH6 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH6  0x000003FF
+#define RMT_MEM_RADDR_EX_CH6_M  ((RMT_MEM_RADDR_EX_CH6_V)<<(RMT_MEM_RADDR_EX_CH6_S))
+#define RMT_MEM_RADDR_EX_CH6_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH6_S  10
+/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH6  0x000003FF
+#define RMT_MEM_WADDR_EX_CH6_M  ((RMT_MEM_WADDR_EX_CH6_V)<<(RMT_MEM_WADDR_EX_CH6_S))
+#define RMT_MEM_WADDR_EX_CH6_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH6_S  0
+
+#define RMT_CH7STATUS_REG          (DR_REG_RMT_BASE + 0x007c)
+/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RD_ERR_CH7  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH7_M  (BIT(27))
+#define RMT_APB_MEM_RD_ERR_CH7_V  0x1
+#define RMT_APB_MEM_RD_ERR_CH7_S  27
+/* RMT_APB_MEM_WR_ERR_CH7 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WR_ERR_CH7  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH7_M  (BIT(26))
+#define RMT_APB_MEM_WR_ERR_CH7_V  0x1
+#define RMT_APB_MEM_WR_ERR_CH7_S  26
+/* RMT_MEM_EMPTY_CH7 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_EMPTY_CH7  (BIT(25))
+#define RMT_MEM_EMPTY_CH7_M  (BIT(25))
+#define RMT_MEM_EMPTY_CH7_V  0x1
+#define RMT_MEM_EMPTY_CH7_S  25
+/* RMT_MEM_FULL_CH7 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_FULL_CH7  (BIT(24))
+#define RMT_MEM_FULL_CH7_M  (BIT(24))
+#define RMT_MEM_FULL_CH7_V  0x1
+#define RMT_MEM_FULL_CH7_S  24
+/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define RMT_MEM_OWNER_ERR_CH7  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH7_M  (BIT(23))
+#define RMT_MEM_OWNER_ERR_CH7_V  0x1
+#define RMT_MEM_OWNER_ERR_CH7_S  23
+/* RMT_STATE_CH7 : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define RMT_STATE_CH7  0x00000007
+#define RMT_STATE_CH7_M  ((RMT_STATE_CH7_V)<<(RMT_STATE_CH7_S))
+#define RMT_STATE_CH7_V  0x7
+#define RMT_STATE_CH7_S  20
+/* RMT_MEM_RADDR_EX_CH7 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_RADDR_EX_CH7  0x000003FF
+#define RMT_MEM_RADDR_EX_CH7_M  ((RMT_MEM_RADDR_EX_CH7_V)<<(RMT_MEM_RADDR_EX_CH7_S))
+#define RMT_MEM_RADDR_EX_CH7_V  0x3FF
+#define RMT_MEM_RADDR_EX_CH7_S  10
+/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_MEM_WADDR_EX_CH7  0x000003FF
+#define RMT_MEM_WADDR_EX_CH7_M  ((RMT_MEM_WADDR_EX_CH7_V)<<(RMT_MEM_WADDR_EX_CH7_S))
+#define RMT_MEM_WADDR_EX_CH7_V  0x3FF
+#define RMT_MEM_WADDR_EX_CH7_S  0
+
+#define RMT_CH0ADDR_REG          (DR_REG_RMT_BASE + 0x0080)
+/* RMT_APB_MEM_RADDR_CH0 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH0  0x000003FF
+#define RMT_APB_MEM_RADDR_CH0_M  ((RMT_APB_MEM_RADDR_CH0_V)<<(RMT_APB_MEM_RADDR_CH0_S))
+#define RMT_APB_MEM_RADDR_CH0_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH0_S  10
+/* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH0  0x000003FF
+#define RMT_APB_MEM_WADDR_CH0_M  ((RMT_APB_MEM_WADDR_CH0_V)<<(RMT_APB_MEM_WADDR_CH0_S))
+#define RMT_APB_MEM_WADDR_CH0_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH0_S  0
+
+#define RMT_CH1ADDR_REG          (DR_REG_RMT_BASE + 0x0084)
+/* RMT_APB_MEM_RADDR_CH1 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH1  0x000003FF
+#define RMT_APB_MEM_RADDR_CH1_M  ((RMT_APB_MEM_RADDR_CH1_V)<<(RMT_APB_MEM_RADDR_CH1_S))
+#define RMT_APB_MEM_RADDR_CH1_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH1_S  10
+/* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH1  0x000003FF
+#define RMT_APB_MEM_WADDR_CH1_M  ((RMT_APB_MEM_WADDR_CH1_V)<<(RMT_APB_MEM_WADDR_CH1_S))
+#define RMT_APB_MEM_WADDR_CH1_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH1_S  0
+
+#define RMT_CH2ADDR_REG          (DR_REG_RMT_BASE + 0x0088)
+/* RMT_APB_MEM_RADDR_CH2 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH2  0x000003FF
+#define RMT_APB_MEM_RADDR_CH2_M  ((RMT_APB_MEM_RADDR_CH2_V)<<(RMT_APB_MEM_RADDR_CH2_S))
+#define RMT_APB_MEM_RADDR_CH2_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH2_S  10
+/* RMT_APB_MEM_WADDR_CH2 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH2  0x000003FF
+#define RMT_APB_MEM_WADDR_CH2_M  ((RMT_APB_MEM_WADDR_CH2_V)<<(RMT_APB_MEM_WADDR_CH2_S))
+#define RMT_APB_MEM_WADDR_CH2_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH2_S  0
+
+#define RMT_CH3ADDR_REG          (DR_REG_RMT_BASE + 0x008c)
+/* RMT_APB_MEM_RADDR_CH3 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH3  0x000003FF
+#define RMT_APB_MEM_RADDR_CH3_M  ((RMT_APB_MEM_RADDR_CH3_V)<<(RMT_APB_MEM_RADDR_CH3_S))
+#define RMT_APB_MEM_RADDR_CH3_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH3_S  10
+/* RMT_APB_MEM_WADDR_CH3 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH3  0x000003FF
+#define RMT_APB_MEM_WADDR_CH3_M  ((RMT_APB_MEM_WADDR_CH3_V)<<(RMT_APB_MEM_WADDR_CH3_S))
+#define RMT_APB_MEM_WADDR_CH3_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH3_S  0
+
+#define RMT_CH4ADDR_REG          (DR_REG_RMT_BASE + 0x0090)
+/* RMT_APB_MEM_RADDR_CH4 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH4  0x000003FF
+#define RMT_APB_MEM_RADDR_CH4_M  ((RMT_APB_MEM_RADDR_CH4_V)<<(RMT_APB_MEM_RADDR_CH4_S))
+#define RMT_APB_MEM_RADDR_CH4_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH4_S  10
+/* RMT_APB_MEM_WADDR_CH4 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH4  0x000003FF
+#define RMT_APB_MEM_WADDR_CH4_M  ((RMT_APB_MEM_WADDR_CH4_V)<<(RMT_APB_MEM_WADDR_CH4_S))
+#define RMT_APB_MEM_WADDR_CH4_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH4_S  0
+
+#define RMT_CH5ADDR_REG          (DR_REG_RMT_BASE + 0x0094)
+/* RMT_APB_MEM_RADDR_CH5 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH5  0x000003FF
+#define RMT_APB_MEM_RADDR_CH5_M  ((RMT_APB_MEM_RADDR_CH5_V)<<(RMT_APB_MEM_RADDR_CH5_S))
+#define RMT_APB_MEM_RADDR_CH5_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH5_S  10
+/* RMT_APB_MEM_WADDR_CH5 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH5  0x000003FF
+#define RMT_APB_MEM_WADDR_CH5_M  ((RMT_APB_MEM_WADDR_CH5_V)<<(RMT_APB_MEM_WADDR_CH5_S))
+#define RMT_APB_MEM_WADDR_CH5_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH5_S  0
+
+#define RMT_CH6ADDR_REG          (DR_REG_RMT_BASE + 0x0098)
+/* RMT_APB_MEM_RADDR_CH6 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH6  0x000003FF
+#define RMT_APB_MEM_RADDR_CH6_M  ((RMT_APB_MEM_RADDR_CH6_V)<<(RMT_APB_MEM_RADDR_CH6_S))
+#define RMT_APB_MEM_RADDR_CH6_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH6_S  10
+/* RMT_APB_MEM_WADDR_CH6 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH6  0x000003FF
+#define RMT_APB_MEM_WADDR_CH6_M  ((RMT_APB_MEM_WADDR_CH6_V)<<(RMT_APB_MEM_WADDR_CH6_S))
+#define RMT_APB_MEM_WADDR_CH6_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH6_S  0
+
+#define RMT_CH7ADDR_REG          (DR_REG_RMT_BASE + 0x009c)
+/* RMT_APB_MEM_RADDR_CH7 : RO ;bitpos:[19:10] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_RADDR_CH7  0x000003FF
+#define RMT_APB_MEM_RADDR_CH7_M  ((RMT_APB_MEM_RADDR_CH7_V)<<(RMT_APB_MEM_RADDR_CH7_S))
+#define RMT_APB_MEM_RADDR_CH7_V  0x3FF
+#define RMT_APB_MEM_RADDR_CH7_S  10
+/* RMT_APB_MEM_WADDR_CH7 : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define RMT_APB_MEM_WADDR_CH7  0x000003FF
+#define RMT_APB_MEM_WADDR_CH7_M  ((RMT_APB_MEM_WADDR_CH7_V)<<(RMT_APB_MEM_WADDR_CH7_S))
+#define RMT_APB_MEM_WADDR_CH7_V  0x3FF
+#define RMT_APB_MEM_WADDR_CH7_S  0
+
+#define RMT_INT_RAW_REG          (DR_REG_RMT_BASE + 0x00a0)
+/* RMT_CH7_TX_THR_EVENT_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ transmitter in channle7  have send datas more than  reg_rmt_tx_lim_ch7  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH7_TX_THR_EVENT_INT_RAW  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_M  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH7_TX_THR_EVENT_INT_RAW_S  31
+/* RMT_CH6_TX_THR_EVENT_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ transmitter in channle6  have send datas more than  reg_rmt_tx_lim_ch6  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH6_TX_THR_EVENT_INT_RAW  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_M  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH6_TX_THR_EVENT_INT_RAW_S  30
+/* RMT_CH5_TX_THR_EVENT_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ transmitter in channle5  have send datas more than  reg_rmt_tx_lim_ch5  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH5_TX_THR_EVENT_INT_RAW  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_M  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH5_TX_THR_EVENT_INT_RAW_S  29
+/* RMT_CH4_TX_THR_EVENT_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ transmitter in channle4  have send datas more than  reg_rmt_tx_lim_ch4  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH4_TX_THR_EVENT_INT_RAW  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_M  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH4_TX_THR_EVENT_INT_RAW_S  28
+/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ transmitter in channle3  have send datas more than  reg_rmt_tx_lim_ch3  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH3_TX_THR_EVENT_INT_RAW  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_M  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH3_TX_THR_EVENT_INT_RAW_S  27
+/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ transmitter in channle2  have send datas more than  reg_rmt_tx_lim_ch2  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH2_TX_THR_EVENT_INT_RAW  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_M  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH2_TX_THR_EVENT_INT_RAW_S  26
+/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ transmitter in channle1  have send datas more than  reg_rmt_tx_lim_ch1  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH1_TX_THR_EVENT_INT_RAW  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_M  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_RAW_S  25
+/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ transmitter in channle0  have send datas more than  reg_rmt_tx_lim_ch0  after detecting this interrupt  software can updata the old datas with new datas.*/
+#define RMT_CH0_TX_THR_EVENT_INT_RAW  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_M  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_RAW_S  24
+/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ channle 7 detects some errors.*/
+#define RMT_CH7_ERR_INT_RAW  (BIT(23))
+#define RMT_CH7_ERR_INT_RAW_M  (BIT(23))
+#define RMT_CH7_ERR_INT_RAW_V  0x1
+#define RMT_CH7_ERR_INT_RAW_S  23
+/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ the receive process is done.*/
+#define RMT_CH7_RX_END_INT_RAW  (BIT(22))
+#define RMT_CH7_RX_END_INT_RAW_M  (BIT(22))
+#define RMT_CH7_RX_END_INT_RAW_V  0x1
+#define RMT_CH7_RX_END_INT_RAW_S  22
+/* RMT_CH7_TX_END_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 7 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH7_TX_END_INT_RAW  (BIT(21))
+#define RMT_CH7_TX_END_INT_RAW_M  (BIT(21))
+#define RMT_CH7_TX_END_INT_RAW_V  0x1
+#define RMT_CH7_TX_END_INT_RAW_S  21
+/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ channle 6 detects some errors.*/
+#define RMT_CH6_ERR_INT_RAW  (BIT(20))
+#define RMT_CH6_ERR_INT_RAW_M  (BIT(20))
+#define RMT_CH6_ERR_INT_RAW_V  0x1
+#define RMT_CH6_ERR_INT_RAW_S  20
+/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ the receive process is done.*/
+#define RMT_CH6_RX_END_INT_RAW  (BIT(19))
+#define RMT_CH6_RX_END_INT_RAW_M  (BIT(19))
+#define RMT_CH6_RX_END_INT_RAW_V  0x1
+#define RMT_CH6_RX_END_INT_RAW_S  19
+/* RMT_CH6_TX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 6 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH6_TX_END_INT_RAW  (BIT(18))
+#define RMT_CH6_TX_END_INT_RAW_M  (BIT(18))
+#define RMT_CH6_TX_END_INT_RAW_V  0x1
+#define RMT_CH6_TX_END_INT_RAW_S  18
+/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ channle 5 detects some errors.*/
+#define RMT_CH5_ERR_INT_RAW  (BIT(17))
+#define RMT_CH5_ERR_INT_RAW_M  (BIT(17))
+#define RMT_CH5_ERR_INT_RAW_V  0x1
+#define RMT_CH5_ERR_INT_RAW_S  17
+/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ the receive process is done.*/
+#define RMT_CH5_RX_END_INT_RAW  (BIT(16))
+#define RMT_CH5_RX_END_INT_RAW_M  (BIT(16))
+#define RMT_CH5_RX_END_INT_RAW_V  0x1
+#define RMT_CH5_RX_END_INT_RAW_S  16
+/* RMT_CH5_TX_END_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 5 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH5_TX_END_INT_RAW  (BIT(15))
+#define RMT_CH5_TX_END_INT_RAW_M  (BIT(15))
+#define RMT_CH5_TX_END_INT_RAW_V  0x1
+#define RMT_CH5_TX_END_INT_RAW_S  15
+/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ channle 4 detects some errors.*/
+#define RMT_CH4_ERR_INT_RAW  (BIT(14))
+#define RMT_CH4_ERR_INT_RAW_M  (BIT(14))
+#define RMT_CH4_ERR_INT_RAW_V  0x1
+#define RMT_CH4_ERR_INT_RAW_S  14
+/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ the receive process is done.*/
+#define RMT_CH4_RX_END_INT_RAW  (BIT(13))
+#define RMT_CH4_RX_END_INT_RAW_M  (BIT(13))
+#define RMT_CH4_RX_END_INT_RAW_V  0x1
+#define RMT_CH4_RX_END_INT_RAW_S  13
+/* RMT_CH4_TX_END_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 4 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH4_TX_END_INT_RAW  (BIT(12))
+#define RMT_CH4_TX_END_INT_RAW_M  (BIT(12))
+#define RMT_CH4_TX_END_INT_RAW_V  0x1
+#define RMT_CH4_TX_END_INT_RAW_S  12
+/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ channle 3 detects some errors.*/
+#define RMT_CH3_ERR_INT_RAW  (BIT(11))
+#define RMT_CH3_ERR_INT_RAW_M  (BIT(11))
+#define RMT_CH3_ERR_INT_RAW_V  0x1
+#define RMT_CH3_ERR_INT_RAW_S  11
+/* RMT_CH3_RX_END_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ the receive process is done.*/
+#define RMT_CH3_RX_END_INT_RAW  (BIT(10))
+#define RMT_CH3_RX_END_INT_RAW_M  (BIT(10))
+#define RMT_CH3_RX_END_INT_RAW_V  0x1
+#define RMT_CH3_RX_END_INT_RAW_S  10
+/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 3 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH3_TX_END_INT_RAW  (BIT(9))
+#define RMT_CH3_TX_END_INT_RAW_M  (BIT(9))
+#define RMT_CH3_TX_END_INT_RAW_V  0x1
+#define RMT_CH3_TX_END_INT_RAW_S  9
+/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ channle 2 detects some errors.*/
+#define RMT_CH2_ERR_INT_RAW  (BIT(8))
+#define RMT_CH2_ERR_INT_RAW_M  (BIT(8))
+#define RMT_CH2_ERR_INT_RAW_V  0x1
+#define RMT_CH2_ERR_INT_RAW_S  8
+/* RMT_CH2_RX_END_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ the receive process is done.*/
+#define RMT_CH2_RX_END_INT_RAW  (BIT(7))
+#define RMT_CH2_RX_END_INT_RAW_M  (BIT(7))
+#define RMT_CH2_RX_END_INT_RAW_V  0x1
+#define RMT_CH2_RX_END_INT_RAW_S  7
+/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 2 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH2_TX_END_INT_RAW  (BIT(6))
+#define RMT_CH2_TX_END_INT_RAW_M  (BIT(6))
+#define RMT_CH2_TX_END_INT_RAW_V  0x1
+#define RMT_CH2_TX_END_INT_RAW_S  6
+/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ channle 1 detects some errors.*/
+#define RMT_CH1_ERR_INT_RAW  (BIT(5))
+#define RMT_CH1_ERR_INT_RAW_M  (BIT(5))
+#define RMT_CH1_ERR_INT_RAW_V  0x1
+#define RMT_CH1_ERR_INT_RAW_S  5
+/* RMT_CH1_RX_END_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ the receive process is done.*/
+#define RMT_CH1_RX_END_INT_RAW  (BIT(4))
+#define RMT_CH1_RX_END_INT_RAW_M  (BIT(4))
+#define RMT_CH1_RX_END_INT_RAW_V  0x1
+#define RMT_CH1_RX_END_INT_RAW_S  4
+/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 1 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH1_TX_END_INT_RAW  (BIT(3))
+#define RMT_CH1_TX_END_INT_RAW_M  (BIT(3))
+#define RMT_CH1_TX_END_INT_RAW_V  0x1
+#define RMT_CH1_TX_END_INT_RAW_S  3
+/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ channle 0 detects some errors.*/
+#define RMT_CH0_ERR_INT_RAW  (BIT(2))
+#define RMT_CH0_ERR_INT_RAW_M  (BIT(2))
+#define RMT_CH0_ERR_INT_RAW_V  0x1
+#define RMT_CH0_ERR_INT_RAW_S  2
+/* RMT_CH0_RX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ the receive process is done.*/
+#define RMT_CH0_RX_END_INT_RAW  (BIT(1))
+#define RMT_CH0_RX_END_INT_RAW_M  (BIT(1))
+#define RMT_CH0_RX_END_INT_RAW_V  0x1
+#define RMT_CH0_RX_END_INT_RAW_S  1
+/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for channel 0 turns to high level when
+ the transmit process is done.*/
+#define RMT_CH0_TX_END_INT_RAW  (BIT(0))
+#define RMT_CH0_TX_END_INT_RAW_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_RAW_V  0x1
+#define RMT_CH0_TX_END_INT_RAW_S  0
+
+#define RMT_INT_ST_REG          (DR_REG_RMT_BASE + 0x00a4)
+/* RMT_CH7_TX_THR_EVENT_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 7's rmt_ch7_tx_thr_event_int_raw
+ when mt_ch7_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH7_TX_THR_EVENT_INT_ST  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ST_M  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH7_TX_THR_EVENT_INT_ST_S  31
+/* RMT_CH6_TX_THR_EVENT_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 6's rmt_ch6_tx_thr_event_int_raw
+ when mt_ch6_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH6_TX_THR_EVENT_INT_ST  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ST_M  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH6_TX_THR_EVENT_INT_ST_S  30
+/* RMT_CH5_TX_THR_EVENT_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 5's rmt_ch5_tx_thr_event_int_raw
+ when mt_ch5_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH5_TX_THR_EVENT_INT_ST  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ST_M  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH5_TX_THR_EVENT_INT_ST_S  29
+/* RMT_CH4_TX_THR_EVENT_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 4's rmt_ch4_tx_thr_event_int_raw
+ when mt_ch4_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH4_TX_THR_EVENT_INT_ST  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ST_M  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH4_TX_THR_EVENT_INT_ST_S  28
+/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 3's rmt_ch3_tx_thr_event_int_raw
+ when mt_ch3_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH3_TX_THR_EVENT_INT_ST  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ST_M  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH3_TX_THR_EVENT_INT_ST_S  27
+/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 2's rmt_ch2_tx_thr_event_int_raw
+ when mt_ch2_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH2_TX_THR_EVENT_INT_ST  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ST_M  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH2_TX_THR_EVENT_INT_ST_S  26
+/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 1's rmt_ch1_tx_thr_event_int_raw
+ when mt_ch1_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH1_TX_THR_EVENT_INT_ST  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ST_M  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_ST_S  25
+/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The interrupt state bit  for channel 0's rmt_ch0_tx_thr_event_int_raw
+ when mt_ch0_tx_thr_event_int_ena is set to 1.*/
+#define RMT_CH0_TX_THR_EVENT_INT_ST  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ST_M  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ST_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_ST_S  24
+/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 7's rmt_ch7_err_int_raw
+ when  rmt_ch7_err_int_ena is set to 1.*/
+#define RMT_CH7_ERR_INT_ST  (BIT(23))
+#define RMT_CH7_ERR_INT_ST_M  (BIT(23))
+#define RMT_CH7_ERR_INT_ST_V  0x1
+#define RMT_CH7_ERR_INT_ST_S  23
+/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 7's rmt_ch7_rx_end_int_raw
+ when  rmt_ch7_rx_end_int_ena is set to 1.*/
+#define RMT_CH7_RX_END_INT_ST  (BIT(22))
+#define RMT_CH7_RX_END_INT_ST_M  (BIT(22))
+#define RMT_CH7_RX_END_INT_ST_V  0x1
+#define RMT_CH7_RX_END_INT_ST_S  22
+/* RMT_CH7_TX_END_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 7's mt_ch7_tx_end_int_raw
+ when mt_ch7_tx_end_int_ena is set to 1.*/
+#define RMT_CH7_TX_END_INT_ST  (BIT(21))
+#define RMT_CH7_TX_END_INT_ST_M  (BIT(21))
+#define RMT_CH7_TX_END_INT_ST_V  0x1
+#define RMT_CH7_TX_END_INT_ST_S  21
+/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 6's rmt_ch6_err_int_raw
+ when  rmt_ch6_err_int_ena is set to 1.*/
+#define RMT_CH6_ERR_INT_ST  (BIT(20))
+#define RMT_CH6_ERR_INT_ST_M  (BIT(20))
+#define RMT_CH6_ERR_INT_ST_V  0x1
+#define RMT_CH6_ERR_INT_ST_S  20
+/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 6's rmt_ch6_rx_end_int_raw
+ when  rmt_ch6_rx_end_int_ena is set to 1.*/
+#define RMT_CH6_RX_END_INT_ST  (BIT(19))
+#define RMT_CH6_RX_END_INT_ST_M  (BIT(19))
+#define RMT_CH6_RX_END_INT_ST_V  0x1
+#define RMT_CH6_RX_END_INT_ST_S  19
+/* RMT_CH6_TX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 6's mt_ch6_tx_end_int_raw
+ when mt_ch6_tx_end_int_ena is set to 1.*/
+#define RMT_CH6_TX_END_INT_ST  (BIT(18))
+#define RMT_CH6_TX_END_INT_ST_M  (BIT(18))
+#define RMT_CH6_TX_END_INT_ST_V  0x1
+#define RMT_CH6_TX_END_INT_ST_S  18
+/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 5's rmt_ch5_err_int_raw
+ when  rmt_ch5_err_int_ena is set to 1.*/
+#define RMT_CH5_ERR_INT_ST  (BIT(17))
+#define RMT_CH5_ERR_INT_ST_M  (BIT(17))
+#define RMT_CH5_ERR_INT_ST_V  0x1
+#define RMT_CH5_ERR_INT_ST_S  17
+/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 5's rmt_ch5_rx_end_int_raw
+ when  rmt_ch5_rx_end_int_ena is set to 1.*/
+#define RMT_CH5_RX_END_INT_ST  (BIT(16))
+#define RMT_CH5_RX_END_INT_ST_M  (BIT(16))
+#define RMT_CH5_RX_END_INT_ST_V  0x1
+#define RMT_CH5_RX_END_INT_ST_S  16
+/* RMT_CH5_TX_END_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 5's mt_ch5_tx_end_int_raw
+ when mt_ch5_tx_end_int_ena is set to 1.*/
+#define RMT_CH5_TX_END_INT_ST  (BIT(15))
+#define RMT_CH5_TX_END_INT_ST_M  (BIT(15))
+#define RMT_CH5_TX_END_INT_ST_V  0x1
+#define RMT_CH5_TX_END_INT_ST_S  15
+/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 4's rmt_ch4_err_int_raw
+ when  rmt_ch4_err_int_ena is set to 1.*/
+#define RMT_CH4_ERR_INT_ST  (BIT(14))
+#define RMT_CH4_ERR_INT_ST_M  (BIT(14))
+#define RMT_CH4_ERR_INT_ST_V  0x1
+#define RMT_CH4_ERR_INT_ST_S  14
+/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 4's rmt_ch4_rx_end_int_raw
+ when  rmt_ch4_rx_end_int_ena is set to 1.*/
+#define RMT_CH4_RX_END_INT_ST  (BIT(13))
+#define RMT_CH4_RX_END_INT_ST_M  (BIT(13))
+#define RMT_CH4_RX_END_INT_ST_V  0x1
+#define RMT_CH4_RX_END_INT_ST_S  13
+/* RMT_CH4_TX_END_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 4's mt_ch4_tx_end_int_raw
+ when mt_ch4_tx_end_int_ena is set to 1.*/
+#define RMT_CH4_TX_END_INT_ST  (BIT(12))
+#define RMT_CH4_TX_END_INT_ST_M  (BIT(12))
+#define RMT_CH4_TX_END_INT_ST_V  0x1
+#define RMT_CH4_TX_END_INT_ST_S  12
+/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 3's rmt_ch3_err_int_raw
+ when  rmt_ch3_err_int_ena is set to 1.*/
+#define RMT_CH3_ERR_INT_ST  (BIT(11))
+#define RMT_CH3_ERR_INT_ST_M  (BIT(11))
+#define RMT_CH3_ERR_INT_ST_V  0x1
+#define RMT_CH3_ERR_INT_ST_S  11
+/* RMT_CH3_RX_END_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 3's rmt_ch3_rx_end_int_raw
+ when  rmt_ch3_rx_end_int_ena is set to 1.*/
+#define RMT_CH3_RX_END_INT_ST  (BIT(10))
+#define RMT_CH3_RX_END_INT_ST_M  (BIT(10))
+#define RMT_CH3_RX_END_INT_ST_V  0x1
+#define RMT_CH3_RX_END_INT_ST_S  10
+/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 3's mt_ch3_tx_end_int_raw
+ when mt_ch3_tx_end_int_ena is set to 1.*/
+#define RMT_CH3_TX_END_INT_ST  (BIT(9))
+#define RMT_CH3_TX_END_INT_ST_M  (BIT(9))
+#define RMT_CH3_TX_END_INT_ST_V  0x1
+#define RMT_CH3_TX_END_INT_ST_S  9
+/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 2's rmt_ch2_err_int_raw
+ when  rmt_ch2_err_int_ena is set to 1.*/
+#define RMT_CH2_ERR_INT_ST  (BIT(8))
+#define RMT_CH2_ERR_INT_ST_M  (BIT(8))
+#define RMT_CH2_ERR_INT_ST_V  0x1
+#define RMT_CH2_ERR_INT_ST_S  8
+/* RMT_CH2_RX_END_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 2's rmt_ch2_rx_end_int_raw
+ when  rmt_ch2_rx_end_int_ena is set to 1.*/
+#define RMT_CH2_RX_END_INT_ST  (BIT(7))
+#define RMT_CH2_RX_END_INT_ST_M  (BIT(7))
+#define RMT_CH2_RX_END_INT_ST_V  0x1
+#define RMT_CH2_RX_END_INT_ST_S  7
+/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 2's mt_ch2_tx_end_int_raw
+ when mt_ch2_tx_end_int_ena is set to 1.*/
+#define RMT_CH2_TX_END_INT_ST  (BIT(6))
+#define RMT_CH2_TX_END_INT_ST_M  (BIT(6))
+#define RMT_CH2_TX_END_INT_ST_V  0x1
+#define RMT_CH2_TX_END_INT_ST_S  6
+/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 1's rmt_ch1_err_int_raw
+ when  rmt_ch1_err_int_ena is set to 1.*/
+#define RMT_CH1_ERR_INT_ST  (BIT(5))
+#define RMT_CH1_ERR_INT_ST_M  (BIT(5))
+#define RMT_CH1_ERR_INT_ST_V  0x1
+#define RMT_CH1_ERR_INT_ST_S  5
+/* RMT_CH1_RX_END_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 1's rmt_ch1_rx_end_int_raw
+ when  rmt_ch1_rx_end_int_ena is set to 1.*/
+#define RMT_CH1_RX_END_INT_ST  (BIT(4))
+#define RMT_CH1_RX_END_INT_ST_M  (BIT(4))
+#define RMT_CH1_RX_END_INT_ST_V  0x1
+#define RMT_CH1_RX_END_INT_ST_S  4
+/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 1's mt_ch1_tx_end_int_raw
+ when mt_ch1_tx_end_int_ena is set to 1.*/
+#define RMT_CH1_TX_END_INT_ST  (BIT(3))
+#define RMT_CH1_TX_END_INT_ST_M  (BIT(3))
+#define RMT_CH1_TX_END_INT_ST_V  0x1
+#define RMT_CH1_TX_END_INT_ST_S  3
+/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 0's rmt_ch0_err_int_raw
+ when  rmt_ch0_err_int_ena is set to 0.*/
+#define RMT_CH0_ERR_INT_ST  (BIT(2))
+#define RMT_CH0_ERR_INT_ST_M  (BIT(2))
+#define RMT_CH0_ERR_INT_ST_V  0x1
+#define RMT_CH0_ERR_INT_ST_S  2
+/* RMT_CH0_RX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 0's rmt_ch0_rx_end_int_raw
+ when  rmt_ch0_rx_end_int_ena is set to 0.*/
+#define RMT_CH0_RX_END_INT_ST  (BIT(1))
+#define RMT_CH0_RX_END_INT_ST_M  (BIT(1))
+#define RMT_CH0_RX_END_INT_ST_V  0x1
+#define RMT_CH0_RX_END_INT_ST_S  1
+/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The interrupt  state bit for channel 0's mt_ch0_tx_end_int_raw
+ when mt_ch0_tx_end_int_ena is set to 0.*/
+#define RMT_CH0_TX_END_INT_ST  (BIT(0))
+#define RMT_CH0_TX_END_INT_ST_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_ST_V  0x1
+#define RMT_CH0_TX_END_INT_ST_S  0
+
+#define RMT_INT_ENA_REG          (DR_REG_RMT_BASE + 0x00a8)
+/* RMT_CH7_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
+#define RMT_CH7_TX_THR_EVENT_INT_ENA  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_M  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH7_TX_THR_EVENT_INT_ENA_S  31
+/* RMT_CH6_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
+#define RMT_CH6_TX_THR_EVENT_INT_ENA  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_M  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH6_TX_THR_EVENT_INT_ENA_S  30
+/* RMT_CH5_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
+#define RMT_CH5_TX_THR_EVENT_INT_ENA  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_M  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH5_TX_THR_EVENT_INT_ENA_S  29
+/* RMT_CH4_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
+#define RMT_CH4_TX_THR_EVENT_INT_ENA  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_M  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH4_TX_THR_EVENT_INT_ENA_S  28
+/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
+#define RMT_CH3_TX_THR_EVENT_INT_ENA  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_M  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH3_TX_THR_EVENT_INT_ENA_S  27
+/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
+#define RMT_CH2_TX_THR_EVENT_INT_ENA  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_M  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH2_TX_THR_EVENT_INT_ENA_S  26
+/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
+#define RMT_CH1_TX_THR_EVENT_INT_ENA  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_M  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_ENA_S  25
+/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
+#define RMT_CH0_TX_THR_EVENT_INT_ENA  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_M  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_ENA_S  24
+/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_err_int_st.*/
+#define RMT_CH7_ERR_INT_ENA  (BIT(23))
+#define RMT_CH7_ERR_INT_ENA_M  (BIT(23))
+#define RMT_CH7_ERR_INT_ENA_V  0x1
+#define RMT_CH7_ERR_INT_ENA_S  23
+/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_rx_end_int_st.*/
+#define RMT_CH7_RX_END_INT_ENA  (BIT(22))
+#define RMT_CH7_RX_END_INT_ENA_M  (BIT(22))
+#define RMT_CH7_RX_END_INT_ENA_V  0x1
+#define RMT_CH7_RX_END_INT_ENA_S  22
+/* RMT_CH7_TX_END_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch7_tx_end_int_st.*/
+#define RMT_CH7_TX_END_INT_ENA  (BIT(21))
+#define RMT_CH7_TX_END_INT_ENA_M  (BIT(21))
+#define RMT_CH7_TX_END_INT_ENA_V  0x1
+#define RMT_CH7_TX_END_INT_ENA_S  21
+/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_err_int_st.*/
+#define RMT_CH6_ERR_INT_ENA  (BIT(20))
+#define RMT_CH6_ERR_INT_ENA_M  (BIT(20))
+#define RMT_CH6_ERR_INT_ENA_V  0x1
+#define RMT_CH6_ERR_INT_ENA_S  20
+/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_rx_end_int_st.*/
+#define RMT_CH6_RX_END_INT_ENA  (BIT(19))
+#define RMT_CH6_RX_END_INT_ENA_M  (BIT(19))
+#define RMT_CH6_RX_END_INT_ENA_V  0x1
+#define RMT_CH6_RX_END_INT_ENA_S  19
+/* RMT_CH6_TX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch6_tx_end_int_st.*/
+#define RMT_CH6_TX_END_INT_ENA  (BIT(18))
+#define RMT_CH6_TX_END_INT_ENA_M  (BIT(18))
+#define RMT_CH6_TX_END_INT_ENA_V  0x1
+#define RMT_CH6_TX_END_INT_ENA_S  18
+/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_err_int_st.*/
+#define RMT_CH5_ERR_INT_ENA  (BIT(17))
+#define RMT_CH5_ERR_INT_ENA_M  (BIT(17))
+#define RMT_CH5_ERR_INT_ENA_V  0x1
+#define RMT_CH5_ERR_INT_ENA_S  17
+/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_rx_end_int_st.*/
+#define RMT_CH5_RX_END_INT_ENA  (BIT(16))
+#define RMT_CH5_RX_END_INT_ENA_M  (BIT(16))
+#define RMT_CH5_RX_END_INT_ENA_V  0x1
+#define RMT_CH5_RX_END_INT_ENA_S  16
+/* RMT_CH5_TX_END_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch5_tx_end_int_st.*/
+#define RMT_CH5_TX_END_INT_ENA  (BIT(15))
+#define RMT_CH5_TX_END_INT_ENA_M  (BIT(15))
+#define RMT_CH5_TX_END_INT_ENA_V  0x1
+#define RMT_CH5_TX_END_INT_ENA_S  15
+/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_err_int_st.*/
+#define RMT_CH4_ERR_INT_ENA  (BIT(14))
+#define RMT_CH4_ERR_INT_ENA_M  (BIT(14))
+#define RMT_CH4_ERR_INT_ENA_V  0x1
+#define RMT_CH4_ERR_INT_ENA_S  14
+/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_rx_end_int_st.*/
+#define RMT_CH4_RX_END_INT_ENA  (BIT(13))
+#define RMT_CH4_RX_END_INT_ENA_M  (BIT(13))
+#define RMT_CH4_RX_END_INT_ENA_V  0x1
+#define RMT_CH4_RX_END_INT_ENA_S  13
+/* RMT_CH4_TX_END_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch4_tx_end_int_st.*/
+#define RMT_CH4_TX_END_INT_ENA  (BIT(12))
+#define RMT_CH4_TX_END_INT_ENA_M  (BIT(12))
+#define RMT_CH4_TX_END_INT_ENA_V  0x1
+#define RMT_CH4_TX_END_INT_ENA_S  12
+/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_err_int_st.*/
+#define RMT_CH3_ERR_INT_ENA  (BIT(11))
+#define RMT_CH3_ERR_INT_ENA_M  (BIT(11))
+#define RMT_CH3_ERR_INT_ENA_V  0x1
+#define RMT_CH3_ERR_INT_ENA_S  11
+/* RMT_CH3_RX_END_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_rx_end_int_st.*/
+#define RMT_CH3_RX_END_INT_ENA  (BIT(10))
+#define RMT_CH3_RX_END_INT_ENA_M  (BIT(10))
+#define RMT_CH3_RX_END_INT_ENA_V  0x1
+#define RMT_CH3_RX_END_INT_ENA_S  10
+/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch3_tx_end_int_st.*/
+#define RMT_CH3_TX_END_INT_ENA  (BIT(9))
+#define RMT_CH3_TX_END_INT_ENA_M  (BIT(9))
+#define RMT_CH3_TX_END_INT_ENA_V  0x1
+#define RMT_CH3_TX_END_INT_ENA_S  9
+/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_err_int_st.*/
+#define RMT_CH2_ERR_INT_ENA  (BIT(8))
+#define RMT_CH2_ERR_INT_ENA_M  (BIT(8))
+#define RMT_CH2_ERR_INT_ENA_V  0x1
+#define RMT_CH2_ERR_INT_ENA_S  8
+/* RMT_CH2_RX_END_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_rx_end_int_st.*/
+#define RMT_CH2_RX_END_INT_ENA  (BIT(7))
+#define RMT_CH2_RX_END_INT_ENA_M  (BIT(7))
+#define RMT_CH2_RX_END_INT_ENA_V  0x1
+#define RMT_CH2_RX_END_INT_ENA_S  7
+/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch2_tx_end_int_st.*/
+#define RMT_CH2_TX_END_INT_ENA  (BIT(6))
+#define RMT_CH2_TX_END_INT_ENA_M  (BIT(6))
+#define RMT_CH2_TX_END_INT_ENA_V  0x1
+#define RMT_CH2_TX_END_INT_ENA_S  6
+/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_err_int_st.*/
+#define RMT_CH1_ERR_INT_ENA  (BIT(5))
+#define RMT_CH1_ERR_INT_ENA_M  (BIT(5))
+#define RMT_CH1_ERR_INT_ENA_V  0x1
+#define RMT_CH1_ERR_INT_ENA_S  5
+/* RMT_CH1_RX_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_rx_end_int_st.*/
+#define RMT_CH1_RX_END_INT_ENA  (BIT(4))
+#define RMT_CH1_RX_END_INT_ENA_M  (BIT(4))
+#define RMT_CH1_RX_END_INT_ENA_V  0x1
+#define RMT_CH1_RX_END_INT_ENA_S  4
+/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch1_tx_end_int_st.*/
+#define RMT_CH1_TX_END_INT_ENA  (BIT(3))
+#define RMT_CH1_TX_END_INT_ENA_M  (BIT(3))
+#define RMT_CH1_TX_END_INT_ENA_V  0x1
+#define RMT_CH1_TX_END_INT_ENA_S  3
+/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_err_int_st.*/
+#define RMT_CH0_ERR_INT_ENA  (BIT(2))
+#define RMT_CH0_ERR_INT_ENA_M  (BIT(2))
+#define RMT_CH0_ERR_INT_ENA_V  0x1
+#define RMT_CH0_ERR_INT_ENA_S  2
+/* RMT_CH0_RX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_rx_end_int_st.*/
+#define RMT_CH0_RX_END_INT_ENA  (BIT(1))
+#define RMT_CH0_RX_END_INT_ENA_M  (BIT(1))
+#define RMT_CH0_RX_END_INT_ENA_V  0x1
+#define RMT_CH0_RX_END_INT_ENA_S  1
+/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to enable rmt_ch0_tx_end_int_st.*/
+#define RMT_CH0_TX_END_INT_ENA  (BIT(0))
+#define RMT_CH0_TX_END_INT_ENA_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_ENA_V  0x1
+#define RMT_CH0_TX_END_INT_ENA_S  0
+
+#define RMT_INT_CLR_REG          (DR_REG_RMT_BASE + 0x00ac)
+/* RMT_CH7_TX_THR_EVENT_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch7_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH7_TX_THR_EVENT_INT_CLR  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_M  (BIT(31))
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH7_TX_THR_EVENT_INT_CLR_S  31
+/* RMT_CH6_TX_THR_EVENT_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch6_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH6_TX_THR_EVENT_INT_CLR  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_M  (BIT(30))
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH6_TX_THR_EVENT_INT_CLR_S  30
+/* RMT_CH5_TX_THR_EVENT_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch5_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH5_TX_THR_EVENT_INT_CLR  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_M  (BIT(29))
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH5_TX_THR_EVENT_INT_CLR_S  29
+/* RMT_CH4_TX_THR_EVENT_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch4_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH4_TX_THR_EVENT_INT_CLR  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_M  (BIT(28))
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH4_TX_THR_EVENT_INT_CLR_S  28
+/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch3_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH3_TX_THR_EVENT_INT_CLR  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_M  (BIT(27))
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH3_TX_THR_EVENT_INT_CLR_S  27
+/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch2_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH2_TX_THR_EVENT_INT_CLR  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_M  (BIT(26))
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH2_TX_THR_EVENT_INT_CLR_S  26
+/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch1_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH1_TX_THR_EVENT_INT_CLR  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_M  (BIT(25))
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH1_TX_THR_EVENT_INT_CLR_S  25
+/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch0_tx_thr_event_int_raw interrupt.*/
+#define RMT_CH0_TX_THR_EVENT_INT_CLR  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_M  (BIT(24))
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_V  0x1
+#define RMT_CH0_TX_THR_EVENT_INT_CLR_S  24
+/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch7_err_int_raw.*/
+#define RMT_CH7_ERR_INT_CLR  (BIT(23))
+#define RMT_CH7_ERR_INT_CLR_M  (BIT(23))
+#define RMT_CH7_ERR_INT_CLR_V  0x1
+#define RMT_CH7_ERR_INT_CLR_S  23
+/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
+#define RMT_CH7_RX_END_INT_CLR  (BIT(22))
+#define RMT_CH7_RX_END_INT_CLR_M  (BIT(22))
+#define RMT_CH7_RX_END_INT_CLR_V  0x1
+#define RMT_CH7_RX_END_INT_CLR_S  22
+/* RMT_CH7_TX_END_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
+#define RMT_CH7_TX_END_INT_CLR  (BIT(21))
+#define RMT_CH7_TX_END_INT_CLR_M  (BIT(21))
+#define RMT_CH7_TX_END_INT_CLR_V  0x1
+#define RMT_CH7_TX_END_INT_CLR_S  21
+/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch6_err_int_raw.*/
+#define RMT_CH6_ERR_INT_CLR  (BIT(20))
+#define RMT_CH6_ERR_INT_CLR_M  (BIT(20))
+#define RMT_CH6_ERR_INT_CLR_V  0x1
+#define RMT_CH6_ERR_INT_CLR_S  20
+/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
+#define RMT_CH6_RX_END_INT_CLR  (BIT(19))
+#define RMT_CH6_RX_END_INT_CLR_M  (BIT(19))
+#define RMT_CH6_RX_END_INT_CLR_V  0x1
+#define RMT_CH6_RX_END_INT_CLR_S  19
+/* RMT_CH6_TX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
+#define RMT_CH6_TX_END_INT_CLR  (BIT(18))
+#define RMT_CH6_TX_END_INT_CLR_M  (BIT(18))
+#define RMT_CH6_TX_END_INT_CLR_V  0x1
+#define RMT_CH6_TX_END_INT_CLR_S  18
+/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch5_err_int_raw.*/
+#define RMT_CH5_ERR_INT_CLR  (BIT(17))
+#define RMT_CH5_ERR_INT_CLR_M  (BIT(17))
+#define RMT_CH5_ERR_INT_CLR_V  0x1
+#define RMT_CH5_ERR_INT_CLR_S  17
+/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
+#define RMT_CH5_RX_END_INT_CLR  (BIT(16))
+#define RMT_CH5_RX_END_INT_CLR_M  (BIT(16))
+#define RMT_CH5_RX_END_INT_CLR_V  0x1
+#define RMT_CH5_RX_END_INT_CLR_S  16
+/* RMT_CH5_TX_END_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
+#define RMT_CH5_TX_END_INT_CLR  (BIT(15))
+#define RMT_CH5_TX_END_INT_CLR_M  (BIT(15))
+#define RMT_CH5_TX_END_INT_CLR_V  0x1
+#define RMT_CH5_TX_END_INT_CLR_S  15
+/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch4_err_int_raw.*/
+#define RMT_CH4_ERR_INT_CLR  (BIT(14))
+#define RMT_CH4_ERR_INT_CLR_M  (BIT(14))
+#define RMT_CH4_ERR_INT_CLR_V  0x1
+#define RMT_CH4_ERR_INT_CLR_S  14
+/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
+#define RMT_CH4_RX_END_INT_CLR  (BIT(13))
+#define RMT_CH4_RX_END_INT_CLR_M  (BIT(13))
+#define RMT_CH4_RX_END_INT_CLR_V  0x1
+#define RMT_CH4_RX_END_INT_CLR_S  13
+/* RMT_CH4_TX_END_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
+#define RMT_CH4_TX_END_INT_CLR  (BIT(12))
+#define RMT_CH4_TX_END_INT_CLR_M  (BIT(12))
+#define RMT_CH4_TX_END_INT_CLR_V  0x1
+#define RMT_CH4_TX_END_INT_CLR_S  12
+/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch3_err_int_raw.*/
+#define RMT_CH3_ERR_INT_CLR  (BIT(11))
+#define RMT_CH3_ERR_INT_CLR_M  (BIT(11))
+#define RMT_CH3_ERR_INT_CLR_V  0x1
+#define RMT_CH3_ERR_INT_CLR_S  11
+/* RMT_CH3_RX_END_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
+#define RMT_CH3_RX_END_INT_CLR  (BIT(10))
+#define RMT_CH3_RX_END_INT_CLR_M  (BIT(10))
+#define RMT_CH3_RX_END_INT_CLR_V  0x1
+#define RMT_CH3_RX_END_INT_CLR_S  10
+/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
+#define RMT_CH3_TX_END_INT_CLR  (BIT(9))
+#define RMT_CH3_TX_END_INT_CLR_M  (BIT(9))
+#define RMT_CH3_TX_END_INT_CLR_V  0x1
+#define RMT_CH3_TX_END_INT_CLR_S  9
+/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch2_err_int_raw.*/
+#define RMT_CH2_ERR_INT_CLR  (BIT(8))
+#define RMT_CH2_ERR_INT_CLR_M  (BIT(8))
+#define RMT_CH2_ERR_INT_CLR_V  0x1
+#define RMT_CH2_ERR_INT_CLR_S  8
+/* RMT_CH2_RX_END_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
+#define RMT_CH2_RX_END_INT_CLR  (BIT(7))
+#define RMT_CH2_RX_END_INT_CLR_M  (BIT(7))
+#define RMT_CH2_RX_END_INT_CLR_V  0x1
+#define RMT_CH2_RX_END_INT_CLR_S  7
+/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
+#define RMT_CH2_TX_END_INT_CLR  (BIT(6))
+#define RMT_CH2_TX_END_INT_CLR_M  (BIT(6))
+#define RMT_CH2_TX_END_INT_CLR_V  0x1
+#define RMT_CH2_TX_END_INT_CLR_S  6
+/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch1_err_int_raw.*/
+#define RMT_CH1_ERR_INT_CLR  (BIT(5))
+#define RMT_CH1_ERR_INT_CLR_M  (BIT(5))
+#define RMT_CH1_ERR_INT_CLR_V  0x1
+#define RMT_CH1_ERR_INT_CLR_S  5
+/* RMT_CH1_RX_END_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
+#define RMT_CH1_RX_END_INT_CLR  (BIT(4))
+#define RMT_CH1_RX_END_INT_CLR_M  (BIT(4))
+#define RMT_CH1_RX_END_INT_CLR_V  0x1
+#define RMT_CH1_RX_END_INT_CLR_S  4
+/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
+#define RMT_CH1_TX_END_INT_CLR  (BIT(3))
+#define RMT_CH1_TX_END_INT_CLR_M  (BIT(3))
+#define RMT_CH1_TX_END_INT_CLR_V  0x1
+#define RMT_CH1_TX_END_INT_CLR_S  3
+/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set this bit to clear the  rmt_ch0_err_int_raw.*/
+#define RMT_CH0_ERR_INT_CLR  (BIT(2))
+#define RMT_CH0_ERR_INT_CLR_M  (BIT(2))
+#define RMT_CH0_ERR_INT_CLR_V  0x1
+#define RMT_CH0_ERR_INT_CLR_S  2
+/* RMT_CH0_RX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
+#define RMT_CH0_RX_END_INT_CLR  (BIT(1))
+#define RMT_CH0_RX_END_INT_CLR_M  (BIT(1))
+#define RMT_CH0_RX_END_INT_CLR_V  0x1
+#define RMT_CH0_RX_END_INT_CLR_S  1
+/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
+#define RMT_CH0_TX_END_INT_CLR  (BIT(0))
+#define RMT_CH0_TX_END_INT_CLR_M  (BIT(0))
+#define RMT_CH0_TX_END_INT_CLR_V  0x1
+#define RMT_CH0_TX_END_INT_CLR_S  0
+
+#define RMT_CH0CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00b0)
+/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel0.*/
+#define RMT_CARRIER_HIGH_CH0  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH0_M  ((RMT_CARRIER_HIGH_CH0_V)<<(RMT_CARRIER_HIGH_CH0_S))
+#define RMT_CARRIER_HIGH_CH0_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH0_S  16
+/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel0.*/
+#define RMT_CARRIER_LOW_CH0  0x0000FFFF
+#define RMT_CARRIER_LOW_CH0_M  ((RMT_CARRIER_LOW_CH0_V)<<(RMT_CARRIER_LOW_CH0_S))
+#define RMT_CARRIER_LOW_CH0_V  0xFFFF
+#define RMT_CARRIER_LOW_CH0_S  0
+
+#define RMT_CH1CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00b4)
+/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel1.*/
+#define RMT_CARRIER_HIGH_CH1  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH1_M  ((RMT_CARRIER_HIGH_CH1_V)<<(RMT_CARRIER_HIGH_CH1_S))
+#define RMT_CARRIER_HIGH_CH1_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH1_S  16
+/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel1.*/
+#define RMT_CARRIER_LOW_CH1  0x0000FFFF
+#define RMT_CARRIER_LOW_CH1_M  ((RMT_CARRIER_LOW_CH1_V)<<(RMT_CARRIER_LOW_CH1_S))
+#define RMT_CARRIER_LOW_CH1_V  0xFFFF
+#define RMT_CARRIER_LOW_CH1_S  0
+
+#define RMT_CH2CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00b8)
+/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel2.*/
+#define RMT_CARRIER_HIGH_CH2  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH2_M  ((RMT_CARRIER_HIGH_CH2_V)<<(RMT_CARRIER_HIGH_CH2_S))
+#define RMT_CARRIER_HIGH_CH2_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH2_S  16
+/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel2.*/
+#define RMT_CARRIER_LOW_CH2  0x0000FFFF
+#define RMT_CARRIER_LOW_CH2_M  ((RMT_CARRIER_LOW_CH2_V)<<(RMT_CARRIER_LOW_CH2_S))
+#define RMT_CARRIER_LOW_CH2_V  0xFFFF
+#define RMT_CARRIER_LOW_CH2_S  0
+
+#define RMT_CH3CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00bc)
+/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel3.*/
+#define RMT_CARRIER_HIGH_CH3  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH3_M  ((RMT_CARRIER_HIGH_CH3_V)<<(RMT_CARRIER_HIGH_CH3_S))
+#define RMT_CARRIER_HIGH_CH3_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH3_S  16
+/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel3.*/
+#define RMT_CARRIER_LOW_CH3  0x0000FFFF
+#define RMT_CARRIER_LOW_CH3_M  ((RMT_CARRIER_LOW_CH3_V)<<(RMT_CARRIER_LOW_CH3_S))
+#define RMT_CARRIER_LOW_CH3_V  0xFFFF
+#define RMT_CARRIER_LOW_CH3_S  0
+
+#define RMT_CH4CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00c0)
+/* RMT_CARRIER_HIGH_CH4 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel4.*/
+#define RMT_CARRIER_HIGH_CH4  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH4_M  ((RMT_CARRIER_HIGH_CH4_V)<<(RMT_CARRIER_HIGH_CH4_S))
+#define RMT_CARRIER_HIGH_CH4_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH4_S  16
+/* RMT_CARRIER_LOW_CH4 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel4.*/
+#define RMT_CARRIER_LOW_CH4  0x0000FFFF
+#define RMT_CARRIER_LOW_CH4_M  ((RMT_CARRIER_LOW_CH4_V)<<(RMT_CARRIER_LOW_CH4_S))
+#define RMT_CARRIER_LOW_CH4_V  0xFFFF
+#define RMT_CARRIER_LOW_CH4_S  0
+
+#define RMT_CH5CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00c4)
+/* RMT_CARRIER_HIGH_CH5 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel5.*/
+#define RMT_CARRIER_HIGH_CH5  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH5_M  ((RMT_CARRIER_HIGH_CH5_V)<<(RMT_CARRIER_HIGH_CH5_S))
+#define RMT_CARRIER_HIGH_CH5_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH5_S  16
+/* RMT_CARRIER_LOW_CH5 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel5.*/
+#define RMT_CARRIER_LOW_CH5  0x0000FFFF
+#define RMT_CARRIER_LOW_CH5_M  ((RMT_CARRIER_LOW_CH5_V)<<(RMT_CARRIER_LOW_CH5_S))
+#define RMT_CARRIER_LOW_CH5_V  0xFFFF
+#define RMT_CARRIER_LOW_CH5_S  0
+
+#define RMT_CH6CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00c8)
+/* RMT_CARRIER_HIGH_CH6 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel6.*/
+#define RMT_CARRIER_HIGH_CH6  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH6_M  ((RMT_CARRIER_HIGH_CH6_V)<<(RMT_CARRIER_HIGH_CH6_S))
+#define RMT_CARRIER_HIGH_CH6_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH6_S  16
+/* RMT_CARRIER_LOW_CH6 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel6.*/
+#define RMT_CARRIER_LOW_CH6  0x0000FFFF
+#define RMT_CARRIER_LOW_CH6_M  ((RMT_CARRIER_LOW_CH6_V)<<(RMT_CARRIER_LOW_CH6_S))
+#define RMT_CARRIER_LOW_CH6_V  0xFFFF
+#define RMT_CARRIER_LOW_CH6_S  0
+
+#define RMT_CH7CARRIER_DUTY_REG          (DR_REG_RMT_BASE + 0x00cc)
+/* RMT_CARRIER_HIGH_CH7 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's high level value for channel7.*/
+#define RMT_CARRIER_HIGH_CH7  0x0000FFFF
+#define RMT_CARRIER_HIGH_CH7_M  ((RMT_CARRIER_HIGH_CH7_V)<<(RMT_CARRIER_HIGH_CH7_S))
+#define RMT_CARRIER_HIGH_CH7_V  0xFFFF
+#define RMT_CARRIER_HIGH_CH7_S  16
+/* RMT_CARRIER_LOW_CH7 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */
+/*description: This register is used to configure carrier wave's low level value for channel7.*/
+#define RMT_CARRIER_LOW_CH7  0x0000FFFF
+#define RMT_CARRIER_LOW_CH7_M  ((RMT_CARRIER_LOW_CH7_V)<<(RMT_CARRIER_LOW_CH7_S))
+#define RMT_CARRIER_LOW_CH7_V  0xFFFF
+#define RMT_CARRIER_LOW_CH7_S  0
+
+#define RMT_CH0_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00d0)
+/* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH0  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH0_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH0_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH0_S  19
+/* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH0  0x000003FF
+#define RMT_TX_LOOP_NUM_CH0_M  ((RMT_TX_LOOP_NUM_CH0_V)<<(RMT_TX_LOOP_NUM_CH0_S))
+#define RMT_TX_LOOP_NUM_CH0_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH0_S  9
+/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel0 sends more than reg_rmt_tx_lim_ch0 datas then channel0
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH0  0x000001FF
+#define RMT_TX_LIM_CH0_M  ((RMT_TX_LIM_CH0_V)<<(RMT_TX_LIM_CH0_S))
+#define RMT_TX_LIM_CH0_V  0x1FF
+#define RMT_TX_LIM_CH0_S  0
+
+#define RMT_CH1_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00d4)
+/* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH1  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH1_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH1_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH1_S  19
+/* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH1  0x000003FF
+#define RMT_TX_LOOP_NUM_CH1_M  ((RMT_TX_LOOP_NUM_CH1_V)<<(RMT_TX_LOOP_NUM_CH1_S))
+#define RMT_TX_LOOP_NUM_CH1_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH1_S  9
+/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel1 sends more than reg_rmt_tx_lim_ch1 datas then channel1
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH1  0x000001FF
+#define RMT_TX_LIM_CH1_M  ((RMT_TX_LIM_CH1_V)<<(RMT_TX_LIM_CH1_S))
+#define RMT_TX_LIM_CH1_V  0x1FF
+#define RMT_TX_LIM_CH1_S  0
+
+#define RMT_CH2_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00d8)
+/* RMT_TX_LOOP_CNT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH2  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH2_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH2_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH2_S  19
+/* RMT_TX_LOOP_NUM_CH2 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH2  0x000003FF
+#define RMT_TX_LOOP_NUM_CH2_M  ((RMT_TX_LOOP_NUM_CH2_V)<<(RMT_TX_LOOP_NUM_CH2_S))
+#define RMT_TX_LOOP_NUM_CH2_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH2_S  9
+/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel2 sends more than reg_rmt_tx_lim_ch2 datas then channel2
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH2  0x000001FF
+#define RMT_TX_LIM_CH2_M  ((RMT_TX_LIM_CH2_V)<<(RMT_TX_LIM_CH2_S))
+#define RMT_TX_LIM_CH2_V  0x1FF
+#define RMT_TX_LIM_CH2_S  0
+
+#define RMT_CH3_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00dc)
+/* RMT_TX_LOOP_CNT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH3  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH3_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH3_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH3_S  19
+/* RMT_TX_LOOP_NUM_CH3 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH3  0x000003FF
+#define RMT_TX_LOOP_NUM_CH3_M  ((RMT_TX_LOOP_NUM_CH3_V)<<(RMT_TX_LOOP_NUM_CH3_S))
+#define RMT_TX_LOOP_NUM_CH3_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH3_S  9
+/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel3 sends more than reg_rmt_tx_lim_ch3 datas then channel3
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH3  0x000001FF
+#define RMT_TX_LIM_CH3_M  ((RMT_TX_LIM_CH3_V)<<(RMT_TX_LIM_CH3_S))
+#define RMT_TX_LIM_CH3_V  0x1FF
+#define RMT_TX_LIM_CH3_S  0
+
+#define RMT_CH4_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00e0)
+/* RMT_TX_LOOP_CNT_EN_CH4 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH4  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH4_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH4_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH4_S  19
+/* RMT_TX_LOOP_NUM_CH4 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH4  0x000003FF
+#define RMT_TX_LOOP_NUM_CH4_M  ((RMT_TX_LOOP_NUM_CH4_V)<<(RMT_TX_LOOP_NUM_CH4_S))
+#define RMT_TX_LOOP_NUM_CH4_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH4_S  9
+/* RMT_TX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel4 sends more than reg_rmt_tx_lim_ch4 datas then channel4
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH4  0x000001FF
+#define RMT_TX_LIM_CH4_M  ((RMT_TX_LIM_CH4_V)<<(RMT_TX_LIM_CH4_S))
+#define RMT_TX_LIM_CH4_V  0x1FF
+#define RMT_TX_LIM_CH4_S  0
+
+#define RMT_CH5_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00e4)
+/* RMT_TX_LOOP_CNT_EN_CH5 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH5  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH5_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH5_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH5_S  19
+/* RMT_TX_LOOP_NUM_CH5 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH5  0x000003FF
+#define RMT_TX_LOOP_NUM_CH5_M  ((RMT_TX_LOOP_NUM_CH5_V)<<(RMT_TX_LOOP_NUM_CH5_S))
+#define RMT_TX_LOOP_NUM_CH5_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH5_S  9
+/* RMT_TX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel5 sends more than reg_rmt_tx_lim_ch5 datas then channel5
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH5  0x000001FF
+#define RMT_TX_LIM_CH5_M  ((RMT_TX_LIM_CH5_V)<<(RMT_TX_LIM_CH5_S))
+#define RMT_TX_LIM_CH5_V  0x1FF
+#define RMT_TX_LIM_CH5_S  0
+
+#define RMT_CH6_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00e8)
+/* RMT_TX_LOOP_CNT_EN_CH6 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH6  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH6_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH6_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH6_S  19
+/* RMT_TX_LOOP_NUM_CH6 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH6  0x000003FF
+#define RMT_TX_LOOP_NUM_CH6_M  ((RMT_TX_LOOP_NUM_CH6_V)<<(RMT_TX_LOOP_NUM_CH6_S))
+#define RMT_TX_LOOP_NUM_CH6_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH6_S  9
+/* RMT_TX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel6 sends more than reg_rmt_tx_lim_ch6 datas then channel6
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH6  0x000001FF
+#define RMT_TX_LIM_CH6_M  ((RMT_TX_LIM_CH6_V)<<(RMT_TX_LIM_CH6_S))
+#define RMT_TX_LIM_CH6_V  0x1FF
+#define RMT_TX_LIM_CH6_S  0
+
+#define RMT_CH7_TX_LIM_REG          (DR_REG_RMT_BASE + 0x00ec)
+/* RMT_TX_LOOP_CNT_EN_CH7 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_CNT_EN_CH7  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH7_M  (BIT(19))
+#define RMT_TX_LOOP_CNT_EN_CH7_V  0x1
+#define RMT_TX_LOOP_CNT_EN_CH7_S  19
+/* RMT_TX_LOOP_NUM_CH7 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */
+/*description: */
+#define RMT_TX_LOOP_NUM_CH7  0x000003FF
+#define RMT_TX_LOOP_NUM_CH7_M  ((RMT_TX_LOOP_NUM_CH7_V)<<(RMT_TX_LOOP_NUM_CH7_S))
+#define RMT_TX_LOOP_NUM_CH7_V  0x3FF
+#define RMT_TX_LOOP_NUM_CH7_S  9
+/* RMT_TX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */
+/*description: When channel7 sends more than reg_rmt_tx_lim_ch7 datas then channel7
+ produce the relative interrupt.*/
+#define RMT_TX_LIM_CH7  0x000001FF
+#define RMT_TX_LIM_CH7_M  ((RMT_TX_LIM_CH7_V)<<(RMT_TX_LIM_CH7_S))
+#define RMT_TX_LIM_CH7_V  0x1FF
+#define RMT_TX_LIM_CH7_S  0
+
+#define RMT_APB_CONF_REG          (DR_REG_RMT_BASE + 0x00f0)
+/* RMT_MEM_TX_WRAP_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: when datas need to be send is more than channel's mem can store
+  then set this bit to enable reusage of mem this bit is used together with reg_rmt_tx_lim_chn.*/
+#define RMT_MEM_TX_WRAP_EN  (BIT(1))
+#define RMT_MEM_TX_WRAP_EN_M  (BIT(1))
+#define RMT_MEM_TX_WRAP_EN_V  0x1
+#define RMT_MEM_TX_WRAP_EN_S  1
+/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: Set this bit to disable apb fifo access*/
+#define RMT_APB_FIFO_MASK  (BIT(0))
+#define RMT_APB_FIFO_MASK_M  (BIT(0))
+#define RMT_APB_FIFO_MASK_V  0x1
+#define RMT_APB_FIFO_MASK_S  0
+
+#define RMT_TX_SIM_REG          (DR_REG_RMT_BASE + 0x00f4)
+/* RMT_TX_SIM_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_EN  (BIT(8))
+#define RMT_TX_SIM_EN_M  (BIT(8))
+#define RMT_TX_SIM_EN_V  0x1
+#define RMT_TX_SIM_EN_S  8
+/* RMT_TX_SIM_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH7  (BIT(7))
+#define RMT_TX_SIM_CH7_M  (BIT(7))
+#define RMT_TX_SIM_CH7_V  0x1
+#define RMT_TX_SIM_CH7_S  7
+/* RMT_TX_SIM_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH6  (BIT(6))
+#define RMT_TX_SIM_CH6_M  (BIT(6))
+#define RMT_TX_SIM_CH6_V  0x1
+#define RMT_TX_SIM_CH6_S  6
+/* RMT_TX_SIM_CH5 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH5  (BIT(5))
+#define RMT_TX_SIM_CH5_M  (BIT(5))
+#define RMT_TX_SIM_CH5_V  0x1
+#define RMT_TX_SIM_CH5_S  5
+/* RMT_TX_SIM_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH4  (BIT(4))
+#define RMT_TX_SIM_CH4_M  (BIT(4))
+#define RMT_TX_SIM_CH4_V  0x1
+#define RMT_TX_SIM_CH4_S  4
+/* RMT_TX_SIM_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH3  (BIT(3))
+#define RMT_TX_SIM_CH3_M  (BIT(3))
+#define RMT_TX_SIM_CH3_V  0x1
+#define RMT_TX_SIM_CH3_S  3
+/* RMT_TX_SIM_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH2  (BIT(2))
+#define RMT_TX_SIM_CH2_M  (BIT(2))
+#define RMT_TX_SIM_CH2_V  0x1
+#define RMT_TX_SIM_CH2_S  2
+/* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH1  (BIT(1))
+#define RMT_TX_SIM_CH1_M  (BIT(1))
+#define RMT_TX_SIM_CH1_V  0x1
+#define RMT_TX_SIM_CH1_S  1
+/* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_TX_SIM_CH0  (BIT(0))
+#define RMT_TX_SIM_CH0_M  (BIT(0))
+#define RMT_TX_SIM_CH0_V  0x1
+#define RMT_TX_SIM_CH0_S  0
+
+#define RMT_REF_CNT_RST_REG          (DR_REG_RMT_BASE + 0x00f8)
+/* RMT_REF_CNT_RST_CH7 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH7  (BIT(7))
+#define RMT_REF_CNT_RST_CH7_M  (BIT(7))
+#define RMT_REF_CNT_RST_CH7_V  0x1
+#define RMT_REF_CNT_RST_CH7_S  7
+/* RMT_REF_CNT_RST_CH6 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH6  (BIT(6))
+#define RMT_REF_CNT_RST_CH6_M  (BIT(6))
+#define RMT_REF_CNT_RST_CH6_V  0x1
+#define RMT_REF_CNT_RST_CH6_S  6
+/* RMT_REF_CNT_RST_CH5 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH5  (BIT(5))
+#define RMT_REF_CNT_RST_CH5_M  (BIT(5))
+#define RMT_REF_CNT_RST_CH5_V  0x1
+#define RMT_REF_CNT_RST_CH5_S  5
+/* RMT_REF_CNT_RST_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH4  (BIT(4))
+#define RMT_REF_CNT_RST_CH4_M  (BIT(4))
+#define RMT_REF_CNT_RST_CH4_V  0x1
+#define RMT_REF_CNT_RST_CH4_S  4
+/* RMT_REF_CNT_RST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH3  (BIT(3))
+#define RMT_REF_CNT_RST_CH3_M  (BIT(3))
+#define RMT_REF_CNT_RST_CH3_V  0x1
+#define RMT_REF_CNT_RST_CH3_S  3
+/* RMT_REF_CNT_RST_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH2  (BIT(2))
+#define RMT_REF_CNT_RST_CH2_M  (BIT(2))
+#define RMT_REF_CNT_RST_CH2_V  0x1
+#define RMT_REF_CNT_RST_CH2_S  2
+/* RMT_REF_CNT_RST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH1  (BIT(1))
+#define RMT_REF_CNT_RST_CH1_M  (BIT(1))
+#define RMT_REF_CNT_RST_CH1_V  0x1
+#define RMT_REF_CNT_RST_CH1_S  1
+/* RMT_REF_CNT_RST_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_REF_CNT_RST_CH0  (BIT(0))
+#define RMT_REF_CNT_RST_CH0_M  (BIT(0))
+#define RMT_REF_CNT_RST_CH0_V  0x1
+#define RMT_REF_CNT_RST_CH0_S  0
+
+#define RMT_INT1_RAW_REG          (DR_REG_RMT_BASE + 0x00fc)
+/* RMT_CH7_TX_LOOP_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH7_TX_LOOP_INT_RAW  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_RAW_M  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH7_TX_LOOP_INT_RAW_S  7
+/* RMT_CH6_TX_LOOP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH6_TX_LOOP_INT_RAW  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_RAW_M  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH6_TX_LOOP_INT_RAW_S  6
+/* RMT_CH5_TX_LOOP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH5_TX_LOOP_INT_RAW  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_RAW_M  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH5_TX_LOOP_INT_RAW_S  5
+/* RMT_CH4_TX_LOOP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH4_TX_LOOP_INT_RAW  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_RAW_M  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH4_TX_LOOP_INT_RAW_S  4
+/* RMT_CH3_TX_LOOP_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_TX_LOOP_INT_RAW  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_RAW_M  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH3_TX_LOOP_INT_RAW_S  3
+/* RMT_CH2_TX_LOOP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_TX_LOOP_INT_RAW  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_RAW_M  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH2_TX_LOOP_INT_RAW_S  2
+/* RMT_CH1_TX_LOOP_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_RAW  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_RAW_M  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH1_TX_LOOP_INT_RAW_S  1
+/* RMT_CH0_TX_LOOP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_RAW  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_RAW_M  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_RAW_V  0x1
+#define RMT_CH0_TX_LOOP_INT_RAW_S  0
+
+#define RMT_INT1_ST_REG          (DR_REG_RMT_BASE + 0x0100)
+/* RMT_CH7_TX_LOOP_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH7_TX_LOOP_INT_ST  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_ST_M  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH7_TX_LOOP_INT_ST_S  7
+/* RMT_CH6_TX_LOOP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH6_TX_LOOP_INT_ST  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_ST_M  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH6_TX_LOOP_INT_ST_S  6
+/* RMT_CH5_TX_LOOP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH5_TX_LOOP_INT_ST  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_ST_M  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH5_TX_LOOP_INT_ST_S  5
+/* RMT_CH4_TX_LOOP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH4_TX_LOOP_INT_ST  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_ST_M  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH4_TX_LOOP_INT_ST_S  4
+/* RMT_CH3_TX_LOOP_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_TX_LOOP_INT_ST  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_ST_M  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH3_TX_LOOP_INT_ST_S  3
+/* RMT_CH2_TX_LOOP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_TX_LOOP_INT_ST  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_ST_M  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH2_TX_LOOP_INT_ST_S  2
+/* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_ST  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_ST_M  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH1_TX_LOOP_INT_ST_S  1
+/* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_ST  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_ST_M  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_ST_V  0x1
+#define RMT_CH0_TX_LOOP_INT_ST_S  0
+
+#define RMT_INT1_ENA_REG          (DR_REG_RMT_BASE + 0x0104)
+/* RMT_CH7_TX_LOOP_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH7_TX_LOOP_INT_ENA  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_ENA_M  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH7_TX_LOOP_INT_ENA_S  7
+/* RMT_CH6_TX_LOOP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH6_TX_LOOP_INT_ENA  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_ENA_M  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH6_TX_LOOP_INT_ENA_S  6
+/* RMT_CH5_TX_LOOP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH5_TX_LOOP_INT_ENA  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_ENA_M  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH5_TX_LOOP_INT_ENA_S  5
+/* RMT_CH4_TX_LOOP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH4_TX_LOOP_INT_ENA  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_ENA_M  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH4_TX_LOOP_INT_ENA_S  4
+/* RMT_CH3_TX_LOOP_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_TX_LOOP_INT_ENA  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_ENA_M  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH3_TX_LOOP_INT_ENA_S  3
+/* RMT_CH2_TX_LOOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_TX_LOOP_INT_ENA  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_ENA_M  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH2_TX_LOOP_INT_ENA_S  2
+/* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_ENA  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_ENA_M  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH1_TX_LOOP_INT_ENA_S  1
+/* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_ENA  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_ENA_M  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_ENA_V  0x1
+#define RMT_CH0_TX_LOOP_INT_ENA_S  0
+
+#define RMT_INT1_CLR_REG          (DR_REG_RMT_BASE + 0x0108)
+/* RMT_CH7_TX_LOOP_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH7_TX_LOOP_INT_CLR  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_CLR_M  (BIT(7))
+#define RMT_CH7_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH7_TX_LOOP_INT_CLR_S  7
+/* RMT_CH6_TX_LOOP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH6_TX_LOOP_INT_CLR  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_CLR_M  (BIT(6))
+#define RMT_CH6_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH6_TX_LOOP_INT_CLR_S  6
+/* RMT_CH5_TX_LOOP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH5_TX_LOOP_INT_CLR  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_CLR_M  (BIT(5))
+#define RMT_CH5_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH5_TX_LOOP_INT_CLR_S  5
+/* RMT_CH4_TX_LOOP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH4_TX_LOOP_INT_CLR  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_CLR_M  (BIT(4))
+#define RMT_CH4_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH4_TX_LOOP_INT_CLR_S  4
+/* RMT_CH3_TX_LOOP_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH3_TX_LOOP_INT_CLR  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_CLR_M  (BIT(3))
+#define RMT_CH3_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH3_TX_LOOP_INT_CLR_S  3
+/* RMT_CH2_TX_LOOP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH2_TX_LOOP_INT_CLR  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_CLR_M  (BIT(2))
+#define RMT_CH2_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH2_TX_LOOP_INT_CLR_S  2
+/* RMT_CH1_TX_LOOP_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH1_TX_LOOP_INT_CLR  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_CLR_M  (BIT(1))
+#define RMT_CH1_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH1_TX_LOOP_INT_CLR_S  1
+/* RMT_CH0_TX_LOOP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RMT_CH0_TX_LOOP_INT_CLR  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_CLR_M  (BIT(0))
+#define RMT_CH0_TX_LOOP_INT_CLR_V  0x1
+#define RMT_CH0_TX_LOOP_INT_CLR_S  0
+
+#define RMT_DATE_REG          (DR_REG_RMT_BASE + 0x010c)
+/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18051400 ; */
+/*description: */
+#define RMT_DATE  0xFFFFFFFF
+#define RMT_DATE_M  ((RMT_DATE_V)<<(RMT_DATE_S))
+#define RMT_DATE_V  0xFFFFFFFF
+#define RMT_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+#define RMT_CHANNEL_MEM(i)  (DR_REG_RMT_BASE + 0x800 + 64 * 4 * (i))
+
+
+#endif /*_SOC_RMT_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/rmt_struct.h b/components/soc/esp32s2beta/include/soc/rmt_struct.h
new file mode 100644
index 000000000..52793676f
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rmt_struct.h
@@ -0,0 +1,376 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RMT_STRUCT_H_
+#define _SOC_RMT_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    uint32_t data_ch[8];                                /*The R/W ram address for channel0-7 by apb fifo access.*/
+    struct{
+        union {
+            struct {
+                uint32_t div_cnt:        8;             /*This register is used to configure the  frequency divider's factor in channel0-7.*/
+                uint32_t idle_thres:    16;             /*In receive mode when no edge is detected on the input signal for longer than reg_idle_thres_ch0 then the receive process is done.*/
+                uint32_t mem_size:       4;             /*This register is used to configure the the amount of memory blocks allocated to channel0-7.*/
+                uint32_t carrier_en:     1;             /*This is the carrier modulation enable control bit for channel0-7.*/
+                uint32_t carrier_out_lv: 1;             /*This bit is used to configure the way carrier wave is modulated for  channel0-7.1'b1:transmit on low output level  1'b0:transmit  on high output level.*/
+                uint32_t mem_pd:         1;             /*This bit is used to reduce power consumed by memory. 1:memory is in low power state.*/
+                uint32_t clk_en:         1;             /*This bit  is used  to control clock.when software configure RMT internal registers  it controls the register clock.*/
+            };
+            uint32_t val;
+        } conf0;
+        union {
+            struct {
+                uint32_t tx_start:        1;            /*Set this bit to start sending data for channel0-7.*/
+                uint32_t rx_en:           1;            /*Set this bit to enable receiving data for channel0-7.*/
+                uint32_t mem_wr_rst:      1;            /*Set this bit to reset write ram address for channel0-7 by receiver access.*/
+                uint32_t mem_rd_rst:      1;            /*Set this bit to reset read ram address for channel0-7 by transmitter access.*/
+                uint32_t apb_mem_rst:     1;            /*Set this bit to reset W/R ram address for channel0-7 by apb fifo access*/
+                uint32_t mem_owner:       1;            /*This is the mark of channel0-7's ram usage right.1'b1：receiver uses the ram  0：transmitter uses the ram*/
+                uint32_t tx_conti_mode:   1;            /*Set this bit to continue sending  from the first data to the last data in channel0-7 again and again.*/
+                uint32_t rx_filter_en:    1;            /*This is the receive filter enable bit for channel0-7.*/
+                uint32_t rx_filter_thres: 8;            /*in receive mode  channel0-7 ignore input pulse when the pulse width is smaller then this value.*/
+                uint32_t reserved16:          1;
+                uint32_t ref_always_on:   1;            /*This bit is used to select base clock. 1'b1:clk_apb  1'b0:clk_ref*/
+                uint32_t idle_out_lv:     1;            /*This bit configures the output signal's level for channel0-7 in IDLE state.*/
+                uint32_t idle_out_en:     1;            /*This is the output enable control bit for channel0-7 in IDLE state.*/
+                uint32_t tx_stop:             1;
+                uint32_t reserved21:         11;
+            };
+            uint32_t val;
+        } conf1;
+    } conf_ch[8];
+    union {
+        struct {
+            uint32_t mem_waddr_ex:      10;
+            uint32_t mem_raddr_ex:      10;
+            uint32_t state:              3;
+            uint32_t mem_owner_err:      1;
+            uint32_t mem_full:           1;
+            uint32_t mem_empty:          1;
+            uint32_t apb_mem_wr_err:     1;
+            uint32_t apb_mem_rd_err:     1;
+            uint32_t reserved28:         4;
+        };
+        uint32_t val;
+    } status_ch[8];
+    union {
+        struct {
+            uint32_t waddr:            10;
+            uint32_t raddr:            10;
+            uint32_t reserved20:       12;
+        };
+        uint32_t val;
+    } apb_mem_addr_ch[8];
+    union {
+        struct {
+            uint32_t ch0_tx_end:       1;               /*The interrupt raw bit for channel 0 turns to high level when the transmit process is done.*/
+            uint32_t ch0_rx_end:       1;               /*The interrupt raw bit for channel 0 turns to high level when the receive process is done.*/
+            uint32_t ch0_err:          1;               /*The interrupt raw bit for channel 0 turns to high level when channel 0 detects some errors.*/
+            uint32_t ch1_tx_end:       1;               /*The interrupt raw bit for channel 1 turns to high level when the transmit process is done.*/
+            uint32_t ch1_rx_end:       1;               /*The interrupt raw bit for channel 1 turns to high level when the receive process is done.*/
+            uint32_t ch1_err:          1;               /*The interrupt raw bit for channel 1 turns to high level when channel 1 detects some errors.*/
+            uint32_t ch2_tx_end:       1;               /*The interrupt raw bit for channel 2 turns to high level when the transmit process is done.*/
+            uint32_t ch2_rx_end:       1;               /*The interrupt raw bit for channel 2 turns to high level when the receive process is done.*/
+            uint32_t ch2_err:          1;               /*The interrupt raw bit for channel 2 turns to high level when channel 2 detects some errors.*/
+            uint32_t ch3_tx_end:       1;               /*The interrupt raw bit for channel 3 turns to high level when the transmit process is done.*/
+            uint32_t ch3_rx_end:       1;               /*The interrupt raw bit for channel 3 turns to high level when the receive process is done.*/
+            uint32_t ch3_err:          1;               /*The interrupt raw bit for channel 3 turns to high level when channel 3 detects some errors.*/
+            uint32_t ch4_tx_end:       1;               /*The interrupt raw bit for channel 4 turns to high level when the transmit process is done.*/
+            uint32_t ch4_rx_end:       1;               /*The interrupt raw bit for channel 4 turns to high level when the receive process is done.*/
+            uint32_t ch4_err:          1;               /*The interrupt raw bit for channel 4 turns to high level when channel 4 detects some errors.*/
+            uint32_t ch5_tx_end:       1;               /*The interrupt raw bit for channel 5 turns to high level when the transmit process is done.*/
+            uint32_t ch5_rx_end:       1;               /*The interrupt raw bit for channel 5 turns to high level when the receive process is done.*/
+            uint32_t ch5_err:          1;               /*The interrupt raw bit for channel 5 turns to high level when channel 5 detects some errors.*/
+            uint32_t ch6_tx_end:       1;               /*The interrupt raw bit for channel 6 turns to high level when the transmit process is done.*/
+            uint32_t ch6_rx_end:       1;               /*The interrupt raw bit for channel 6 turns to high level when the receive process is done.*/
+            uint32_t ch6_err:          1;               /*The interrupt raw bit for channel 6 turns to high level when channel 6 detects some errors.*/
+            uint32_t ch7_tx_end:       1;               /*The interrupt raw bit for channel 7 turns to high level when the transmit process is done.*/
+            uint32_t ch7_rx_end:       1;               /*The interrupt raw bit for channel 7 turns to high level when the receive process is done.*/
+            uint32_t ch7_err:          1;               /*The interrupt raw bit for channel 7 turns to high level when channel 7 detects some errors.*/
+            uint32_t ch0_tx_thr_event: 1;               /*The interrupt raw bit for channel 0 turns to high level when transmitter in channel0  have send data more than  reg_rmt_tx_lim_ch0  after detecting this interrupt  software can updata the old data with new data.*/
+            uint32_t ch1_tx_thr_event: 1;               /*The interrupt raw bit for channel 1 turns to high level when transmitter in channel1  have send data more than  reg_rmt_tx_lim_ch1  after detecting this interrupt  software can updata the old data with new data.*/
+            uint32_t ch2_tx_thr_event: 1;               /*The interrupt raw bit for channel 2 turns to high level when transmitter in channel2  have send data more than  reg_rmt_tx_lim_ch2  after detecting this interrupt  software can updata the old data with new data.*/
+            uint32_t ch3_tx_thr_event: 1;               /*The interrupt raw bit for channel 3 turns to high level when transmitter in channel3  have send data more than  reg_rmt_tx_lim_ch3  after detecting this interrupt  software can updata the old data with new data.*/
+            uint32_t ch4_tx_thr_event: 1;               /*The interrupt raw bit for channel 4 turns to high level when transmitter in channel4  have send data more than  reg_rmt_tx_lim_ch4  after detecting this interrupt  software can updata the old data with new data.*/
+            uint32_t ch5_tx_thr_event: 1;               /*The interrupt raw bit for channel 5 turns to high level when transmitter in channel5  have send data more than  reg_rmt_tx_lim_ch5  after detecting this interrupt  software can updata the old data with new data.*/
+            uint32_t ch6_tx_thr_event: 1;               /*The interrupt raw bit for channel 6 turns to high level when transmitter in channel6  have send data more than  reg_rmt_tx_lim_ch6  after detecting this interrupt  software can updata the old data with new data.*/
+            uint32_t ch7_tx_thr_event: 1;               /*The interrupt raw bit for channel 7 turns to high level when transmitter in channel7  have send data more than  reg_rmt_tx_lim_ch7  after detecting this interrupt  software can updata the old data with new data.*/
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t ch0_tx_end:       1;                /*The interrupt  state bit for channel 0's mt_ch0_tx_end_int_raw when mt_ch0_tx_end_int_ena is set to 0.*/
+            uint32_t ch0_rx_end:       1;                /*The interrupt  state bit for channel 0's rmt_ch0_rx_end_int_raw when  rmt_ch0_rx_end_int_ena is set to 0.*/
+            uint32_t ch0_err:          1;                /*The interrupt  state bit for channel 0's rmt_ch0_err_int_raw when  rmt_ch0_err_int_ena is set to 0.*/
+            uint32_t ch1_tx_end:       1;                /*The interrupt  state bit for channel 1's mt_ch1_tx_end_int_raw when mt_ch1_tx_end_int_ena is set to 1.*/
+            uint32_t ch1_rx_end:       1;                /*The interrupt  state bit for channel 1's rmt_ch1_rx_end_int_raw when  rmt_ch1_rx_end_int_ena is set to 1.*/
+            uint32_t ch1_err:          1;                /*The interrupt  state bit for channel 1's rmt_ch1_err_int_raw when  rmt_ch1_err_int_ena is set to 1.*/
+            uint32_t ch2_tx_end:       1;                /*The interrupt  state bit for channel 2's mt_ch2_tx_end_int_raw when mt_ch2_tx_end_int_ena is set to 1.*/
+            uint32_t ch2_rx_end:       1;                /*The interrupt  state bit for channel 2's rmt_ch2_rx_end_int_raw when  rmt_ch2_rx_end_int_ena is set to 1.*/
+            uint32_t ch2_err:          1;                /*The interrupt  state bit for channel 2's rmt_ch2_err_int_raw when  rmt_ch2_err_int_ena is set to 1.*/
+            uint32_t ch3_tx_end:       1;                /*The interrupt  state bit for channel 3's mt_ch3_tx_end_int_raw when mt_ch3_tx_end_int_ena is set to 1.*/
+            uint32_t ch3_rx_end:       1;                /*The interrupt  state bit for channel 3's rmt_ch3_rx_end_int_raw when  rmt_ch3_rx_end_int_ena is set to 1.*/
+            uint32_t ch3_err:          1;                /*The interrupt  state bit for channel 3's rmt_ch3_err_int_raw when  rmt_ch3_err_int_ena is set to 1.*/
+            uint32_t ch4_tx_end:       1;                /*The interrupt  state bit for channel 4's mt_ch4_tx_end_int_raw when mt_ch4_tx_end_int_ena is set to 1.*/
+            uint32_t ch4_rx_end:       1;                /*The interrupt  state bit for channel 4's rmt_ch4_rx_end_int_raw when  rmt_ch4_rx_end_int_ena is set to 1.*/
+            uint32_t ch4_err:          1;                /*The interrupt  state bit for channel 4's rmt_ch4_err_int_raw when  rmt_ch4_err_int_ena is set to 1.*/
+            uint32_t ch5_tx_end:       1;                /*The interrupt  state bit for channel 5's mt_ch5_tx_end_int_raw when mt_ch5_tx_end_int_ena is set to 1.*/
+            uint32_t ch5_rx_end:       1;                /*The interrupt  state bit for channel 5's rmt_ch5_rx_end_int_raw when  rmt_ch5_rx_end_int_ena is set to 1.*/
+            uint32_t ch5_err:          1;                /*The interrupt  state bit for channel 5's rmt_ch5_err_int_raw when  rmt_ch5_err_int_ena is set to 1.*/
+            uint32_t ch6_tx_end:       1;                /*The interrupt  state bit for channel 6's mt_ch6_tx_end_int_raw when mt_ch6_tx_end_int_ena is set to 1.*/
+            uint32_t ch6_rx_end:       1;                /*The interrupt  state bit for channel 6's rmt_ch6_rx_end_int_raw when  rmt_ch6_rx_end_int_ena is set to 1.*/
+            uint32_t ch6_err:          1;                /*The interrupt  state bit for channel 6's rmt_ch6_err_int_raw when  rmt_ch6_err_int_ena is set to 1.*/
+            uint32_t ch7_tx_end:       1;                /*The interrupt  state bit for channel 7's mt_ch7_tx_end_int_raw when mt_ch7_tx_end_int_ena is set to 1.*/
+            uint32_t ch7_rx_end:       1;                /*The interrupt  state bit for channel 7's rmt_ch7_rx_end_int_raw when  rmt_ch7_rx_end_int_ena is set to 1.*/
+            uint32_t ch7_err:          1;                /*The interrupt  state bit for channel 7's rmt_ch7_err_int_raw when  rmt_ch7_err_int_ena is set to 1.*/
+            uint32_t ch0_tx_thr_event: 1;                /*The interrupt state bit  for channel 0's rmt_ch0_tx_thr_event_int_raw when mt_ch0_tx_thr_event_int_ena is set to 1.*/
+            uint32_t ch1_tx_thr_event: 1;                /*The interrupt state bit  for channel 1's rmt_ch1_tx_thr_event_int_raw when mt_ch1_tx_thr_event_int_ena is set to 1.*/
+            uint32_t ch2_tx_thr_event: 1;                /*The interrupt state bit  for channel 2's rmt_ch2_tx_thr_event_int_raw when mt_ch2_tx_thr_event_int_ena is set to 1.*/
+            uint32_t ch3_tx_thr_event: 1;                /*The interrupt state bit  for channel 3's rmt_ch3_tx_thr_event_int_raw when mt_ch3_tx_thr_event_int_ena is set to 1.*/
+            uint32_t ch4_tx_thr_event: 1;                /*The interrupt state bit  for channel 4's rmt_ch4_tx_thr_event_int_raw when mt_ch4_tx_thr_event_int_ena is set to 1.*/
+            uint32_t ch5_tx_thr_event: 1;                /*The interrupt state bit  for channel 5's rmt_ch5_tx_thr_event_int_raw when mt_ch5_tx_thr_event_int_ena is set to 1.*/
+            uint32_t ch6_tx_thr_event: 1;                /*The interrupt state bit  for channel 6's rmt_ch6_tx_thr_event_int_raw when mt_ch6_tx_thr_event_int_ena is set to 1.*/
+            uint32_t ch7_tx_thr_event: 1;                /*The interrupt state bit  for channel 7's rmt_ch7_tx_thr_event_int_raw when mt_ch7_tx_thr_event_int_ena is set to 1.*/
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t ch0_tx_end:       1;               /*Set this bit to enable rmt_ch0_tx_end_int_st.*/
+            uint32_t ch0_rx_end:       1;               /*Set this bit to enable rmt_ch0_rx_end_int_st.*/
+            uint32_t ch0_err:          1;               /*Set this bit to enable rmt_ch0_err_int_st.*/
+            uint32_t ch1_tx_end:       1;               /*Set this bit to enable rmt_ch1_tx_end_int_st.*/
+            uint32_t ch1_rx_end:       1;               /*Set this bit to enable rmt_ch1_rx_end_int_st.*/
+            uint32_t ch1_err:          1;               /*Set this bit to enable rmt_ch1_err_int_st.*/
+            uint32_t ch2_tx_end:       1;               /*Set this bit to enable rmt_ch2_tx_end_int_st.*/
+            uint32_t ch2_rx_end:       1;               /*Set this bit to enable rmt_ch2_rx_end_int_st.*/
+            uint32_t ch2_err:          1;               /*Set this bit to enable rmt_ch2_err_int_st.*/
+            uint32_t ch3_tx_end:       1;               /*Set this bit to enable rmt_ch3_tx_end_int_st.*/
+            uint32_t ch3_rx_end:       1;               /*Set this bit to enable rmt_ch3_rx_end_int_st.*/
+            uint32_t ch3_err:          1;               /*Set this bit to enable rmt_ch3_err_int_st.*/
+            uint32_t ch4_tx_end:       1;               /*Set this bit to enable rmt_ch4_tx_end_int_st.*/
+            uint32_t ch4_rx_end:       1;               /*Set this bit to enable rmt_ch4_rx_end_int_st.*/
+            uint32_t ch4_err:          1;               /*Set this bit to enable rmt_ch4_err_int_st.*/
+            uint32_t ch5_tx_end:       1;               /*Set this bit to enable rmt_ch5_tx_end_int_st.*/
+            uint32_t ch5_rx_end:       1;               /*Set this bit to enable rmt_ch5_rx_end_int_st.*/
+            uint32_t ch5_err:          1;               /*Set this bit to enable rmt_ch5_err_int_st.*/
+            uint32_t ch6_tx_end:       1;               /*Set this bit to enable rmt_ch6_tx_end_int_st.*/
+            uint32_t ch6_rx_end:       1;               /*Set this bit to enable rmt_ch6_rx_end_int_st.*/
+            uint32_t ch6_err:          1;               /*Set this bit to enable rmt_ch6_err_int_st.*/
+            uint32_t ch7_tx_end:       1;               /*Set this bit to enable rmt_ch7_tx_end_int_st.*/
+            uint32_t ch7_rx_end:       1;               /*Set this bit to enable rmt_ch7_rx_end_int_st.*/
+            uint32_t ch7_err:          1;               /*Set this bit to enable rmt_ch7_err_int_st.*/
+            uint32_t ch0_tx_thr_event: 1;               /*Set this bit to enable rmt_ch0_tx_thr_event_int_st.*/
+            uint32_t ch1_tx_thr_event: 1;               /*Set this bit to enable rmt_ch1_tx_thr_event_int_st.*/
+            uint32_t ch2_tx_thr_event: 1;               /*Set this bit to enable rmt_ch2_tx_thr_event_int_st.*/
+            uint32_t ch3_tx_thr_event: 1;               /*Set this bit to enable rmt_ch3_tx_thr_event_int_st.*/
+            uint32_t ch4_tx_thr_event: 1;               /*Set this bit to enable rmt_ch4_tx_thr_event_int_st.*/
+            uint32_t ch5_tx_thr_event: 1;               /*Set this bit to enable rmt_ch5_tx_thr_event_int_st.*/
+            uint32_t ch6_tx_thr_event: 1;               /*Set this bit to enable rmt_ch6_tx_thr_event_int_st.*/
+            uint32_t ch7_tx_thr_event: 1;               /*Set this bit to enable rmt_ch7_tx_thr_event_int_st.*/
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t ch0_tx_end:       1;               /*Set this bit to clear the rmt_ch0_rx_end_int_raw..*/
+            uint32_t ch0_rx_end:       1;               /*Set this bit to clear the rmt_ch0_tx_end_int_raw.*/
+            uint32_t ch0_err:          1;               /*Set this bit to clear the  rmt_ch0_err_int_raw.*/
+            uint32_t ch1_tx_end:       1;               /*Set this bit to clear the rmt_ch1_rx_end_int_raw..*/
+            uint32_t ch1_rx_end:       1;               /*Set this bit to clear the rmt_ch1_tx_end_int_raw.*/
+            uint32_t ch1_err:          1;               /*Set this bit to clear the  rmt_ch1_err_int_raw.*/
+            uint32_t ch2_tx_end:       1;               /*Set this bit to clear the rmt_ch2_rx_end_int_raw..*/
+            uint32_t ch2_rx_end:       1;               /*Set this bit to clear the rmt_ch2_tx_end_int_raw.*/
+            uint32_t ch2_err:          1;               /*Set this bit to clear the  rmt_ch2_err_int_raw.*/
+            uint32_t ch3_tx_end:       1;               /*Set this bit to clear the rmt_ch3_rx_end_int_raw..*/
+            uint32_t ch3_rx_end:       1;               /*Set this bit to clear the rmt_ch3_tx_end_int_raw.*/
+            uint32_t ch3_err:          1;               /*Set this bit to clear the  rmt_ch3_err_int_raw.*/
+            uint32_t ch4_tx_end:       1;               /*Set this bit to clear the rmt_ch4_rx_end_int_raw..*/
+            uint32_t ch4_rx_end:       1;               /*Set this bit to clear the rmt_ch4_tx_end_int_raw.*/
+            uint32_t ch4_err:          1;               /*Set this bit to clear the  rmt_ch4_err_int_raw.*/
+            uint32_t ch5_tx_end:       1;               /*Set this bit to clear the rmt_ch5_rx_end_int_raw..*/
+            uint32_t ch5_rx_end:       1;               /*Set this bit to clear the rmt_ch5_tx_end_int_raw.*/
+            uint32_t ch5_err:          1;               /*Set this bit to clear the  rmt_ch5_err_int_raw.*/
+            uint32_t ch6_tx_end:       1;               /*Set this bit to clear the rmt_ch6_rx_end_int_raw..*/
+            uint32_t ch6_rx_end:       1;               /*Set this bit to clear the rmt_ch6_tx_end_int_raw.*/
+            uint32_t ch6_err:          1;               /*Set this bit to clear the  rmt_ch6_err_int_raw.*/
+            uint32_t ch7_tx_end:       1;               /*Set this bit to clear the rmt_ch7_rx_end_int_raw..*/
+            uint32_t ch7_rx_end:       1;               /*Set this bit to clear the rmt_ch7_tx_end_int_raw.*/
+            uint32_t ch7_err:          1;               /*Set this bit to clear the  rmt_ch7_err_int_raw.*/
+            uint32_t ch0_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch0_tx_thr_event_int_raw interrupt.*/
+            uint32_t ch1_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch1_tx_thr_event_int_raw interrupt.*/
+            uint32_t ch2_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch2_tx_thr_event_int_raw interrupt.*/
+            uint32_t ch3_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch3_tx_thr_event_int_raw interrupt.*/
+            uint32_t ch4_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch4_tx_thr_event_int_raw interrupt.*/
+            uint32_t ch5_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch5_tx_thr_event_int_raw interrupt.*/
+            uint32_t ch6_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch6_tx_thr_event_int_raw interrupt.*/
+            uint32_t ch7_tx_thr_event: 1;               /*Set this bit to clear the  rmt_ch7_tx_thr_event_int_raw interrupt.*/
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t low: 16;                           /*This register is used to configure carrier wave's low level value for channel0-7.*/
+            uint32_t high:16;                           /*This register is used to configure carrier wave's high level value for channel0-7.*/
+        };
+        uint32_t val;
+    } carrier_duty_ch[8];
+    union {
+        struct {
+            uint32_t limit:              9;
+            uint32_t tx_loop_num:       10;
+            uint32_t tx_loop_cnt_en:     1;
+            uint32_t reserved20:        12;
+        };
+        uint32_t val;
+    } tx_lim_ch[8];
+    union {
+        struct {
+            uint32_t fifo_mask:  1;                     /*Set this bit to disable apb fifo access*/
+            uint32_t mem_tx_wrap_en: 1;                 /*when data need to be send is more than channel's mem can store  then set this bit to enable reuse of mem this bit is used together with reg_rmt_tx_lim_chn.*/
+            uint32_t reserved2:     30;
+        };
+        uint32_t val;
+    } apb_conf;
+    union {
+        struct {
+            uint32_t ch0:        1;
+            uint32_t ch1:        1;
+            uint32_t ch2:        1;
+            uint32_t ch3:        1;
+            uint32_t ch4:        1;
+            uint32_t ch5:        1;
+            uint32_t ch6:        1;
+            uint32_t ch7:        1;
+            uint32_t en:         1;
+            uint32_t reserved9: 23;
+        };
+        uint32_t val;
+    } tx_sim;
+    union {
+        struct {
+            uint32_t ch0:             1;
+            uint32_t ch1:             1;
+            uint32_t ch2:             1;
+            uint32_t ch3:             1;
+            uint32_t ch4:             1;
+            uint32_t ch5:             1;
+            uint32_t ch6:             1;
+            uint32_t ch7:             1;
+            uint32_t reserved8:      24;
+        };
+        uint32_t val;
+    } ref_cnt_rst;
+    union {
+        struct {
+            uint32_t ch0_tx_loop:         1;
+            uint32_t ch1_tx_loop:         1;
+            uint32_t ch2_tx_loop:         1;
+            uint32_t ch3_tx_loop:         1;
+            uint32_t ch4_tx_loop:         1;
+            uint32_t ch5_tx_loop:         1;
+            uint32_t ch6_tx_loop:         1;
+            uint32_t ch7_tx_loop:         1;
+            uint32_t reserved8:          24;
+        };
+        uint32_t val;
+    } int1_raw;
+    union {
+        struct {
+            uint32_t ch0_tx_loop:        1;
+            uint32_t ch1_tx_loop:        1;
+            uint32_t ch2_tx_loop:        1;
+            uint32_t ch3_tx_loop:        1;
+            uint32_t ch4_tx_loop:        1;
+            uint32_t ch5_tx_loop:        1;
+            uint32_t ch6_tx_loop:        1;
+            uint32_t ch7_tx_loop:        1;
+            uint32_t reserved8:         24;
+        };
+        uint32_t val;
+    } int1_st;
+    union {
+        struct {
+            uint32_t ch0_tx_loop:         1;
+            uint32_t ch1_tx_loop:         1;
+            uint32_t ch2_tx_loop:         1;
+            uint32_t ch3_tx_loop:         1;
+            uint32_t ch4_tx_loop:         1;
+            uint32_t ch5_tx_loop:         1;
+            uint32_t ch6_tx_loop:         1;
+            uint32_t ch7_tx_loop:         1;
+            uint32_t reserved8:          24;
+        };
+        uint32_t val;
+    } int1_ena;
+    union {
+        struct {
+            uint32_t ch0_tx_loop:         1;
+            uint32_t ch1_tx_loop:         1;
+            uint32_t ch2_tx_loop:         1;
+            uint32_t ch3_tx_loop:         1;
+            uint32_t ch4_tx_loop:         1;
+            uint32_t ch5_tx_loop:         1;
+            uint32_t ch6_tx_loop:         1;
+            uint32_t ch7_tx_loop:         1;
+            uint32_t reserved8:          24;
+        };
+        uint32_t val;
+    } int1_clr;
+    uint32_t date;                                      /**/
+} rmt_dev_t;
+extern rmt_dev_t RMT;
+
+typedef struct {
+    union {
+        struct {
+            uint32_t duration0 :15;
+            uint32_t level0 :1;
+            uint32_t duration1 :15;
+            uint32_t level1 :1;
+        };
+        uint32_t val;
+    };
+} rmt_item32_t;
+
+typedef struct {
+    union {
+        struct {
+            uint16_t duration :15;
+            uint16_t level :1;
+        };
+        uint16_t val;
+    };
+} rmt_item16_t;
+
+//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
+typedef volatile struct {
+    struct {
+        union {
+            rmt_item32_t data32[64];
+            rmt_item16_t data16[128];
+        };
+    } chan[8];
+} rmt_mem_t;
+extern rmt_mem_t RMTMEM;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RMT_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/rtc.h b/components/soc/esp32s2beta/include/soc/rtc.h
new file mode 100644
index 000000000..eef096260
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc.h
@@ -0,0 +1,662 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+#include <stdbool.h>
+#include <stddef.h>
+#include <stdint.h>
+#include "soc/soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @file rtc.h
+ * @brief Low-level RTC power, clock, and sleep functions.
+ *
+ * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
+ * RTC_CNTL peripheral handles many functions:
+ * - enables/disables clocks and power to various parts of the chip; this is
+ *   done using direct register access (forcing power up or power down) or by
+ *   allowing state machines to control power and clocks automatically
+ * - handles sleep and wakeup functions
+ * - maintains a 48-bit counter which can be used for timekeeping
+ *
+ * These functions are not thread safe, and should not be viewed as high level
+ * APIs. For example, while this file provides a function which can switch
+ * CPU frequency, this function is on its own is not sufficient to implement
+ * frequency switching in ESP-IDF context: some coordination with RTOS,
+ * peripheral drivers, and WiFi/BT stacks is also required.
+ *
+ * These functions will normally not be used in applications directly.
+ * ESP-IDF provides, or will provide, drivers and other facilities to use
+ * RTC subsystem functionality.
+ *
+ * The functions are loosely split into the following groups:
+ * - rtc_clk: clock switching, calibration
+ * - rtc_time: reading RTC counter, conversion between counter values and time
+ * - rtc_sleep: entry into sleep modes
+ * - rtc_init: initialization
+ */
+
+
+/**
+ * @brief Possible main XTAL frequency values.
+ *
+ * Enum values should be equal to frequency in MHz.
+ */
+typedef enum {
+    RTC_XTAL_FREQ_AUTO = 0,     //!< Automatic XTAL frequency detection
+    RTC_XTAL_FREQ_40M = 40,     //!< 40 MHz XTAL
+    RTC_XTAL_FREQ_26M = 26,     //!< 26 MHz XTAL
+    RTC_XTAL_FREQ_24M = 24,     //!< 24 MHz XTAL
+} rtc_xtal_freq_t;
+
+/**
+ * @brief CPU frequency values
+ */
+typedef enum {
+    RTC_CPU_FREQ_XTAL = 0,      //!< Main XTAL frequency
+    RTC_CPU_FREQ_80M = 1,       //!< 80 MHz
+    RTC_CPU_FREQ_160M = 2,      //!< 160 MHz
+    RTC_CPU_FREQ_240M = 3,      //!< 240 MHz
+    RTC_CPU_FREQ_2M = 4,        //!< 2 MHz
+    RTC_CPU_320M_80M = 5,       //!< for test
+    RTC_CPU_320M_160M = 6,      //!< for test
+} rtc_cpu_freq_t;
+
+/**
+ * @brief RTC SLOW_CLK frequency values
+ */
+typedef enum {
+    RTC_SLOW_FREQ_RTC = 0,      //!< Internal 150 kHz RC oscillator
+    RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
+    RTC_SLOW_FREQ_8MD256 = 2,   //!< Internal 8 MHz RC oscillator, divided by 256
+} rtc_slow_freq_t;
+
+/**
+ * @brief RTC FAST_CLK frequency values
+ */
+typedef enum {
+    RTC_FAST_FREQ_XTALD4 = 0,   //!< Main XTAL, divided by 4
+    RTC_FAST_FREQ_8M = 1,       //!< Internal 8 MHz RC oscillator
+} rtc_fast_freq_t;
+
+/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
+#define RTC_FAST_CLK_FREQ_APPROX 8500000
+
+/**
+ * @brief Clock source to be calibrated using rtc_clk_cal function
+ */
+typedef enum {
+    RTC_CAL_RTC_MUX = 0,       //!< Currently selected RTC SLOW_CLK
+    RTC_CAL_8MD256 = 1,        //!< Internal 8 MHz RC oscillator, divided by 256
+    RTC_CAL_32K_XTAL = 2       //!< External 32 kHz XTAL
+} rtc_cal_sel_t;
+
+/**
+ * Initialization parameters for rtc_clk_init
+ */
+typedef struct {
+    rtc_xtal_freq_t xtal_freq : 8;  //!< Main XTAL frequency
+    rtc_cpu_freq_t cpu_freq : 3;    //!< CPU frequency to set
+    rtc_fast_freq_t fast_freq : 1;  //!< RTC_FAST_CLK frequency to set
+    rtc_slow_freq_t slow_freq : 2;  //!< RTC_SLOW_CLK frequency to set
+    uint32_t clk_rtc_clk_div : 8;
+    uint32_t clk_8m_clk_div : 3;        //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
+    uint32_t slow_clk_dcap : 8;     //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
+    uint32_t clk_8m_dfreq : 8;      //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
+} rtc_clk_config_t;
+
+/**
+ * Default initializer for rtc_clk_config_t
+ */
+#define RTC_CLK_CONFIG_DEFAULT() { \
+    .xtal_freq = RTC_XTAL_FREQ_AUTO, \
+    .cpu_freq = RTC_CPU_FREQ_80M, \
+    .fast_freq = RTC_FAST_FREQ_8M, \
+    .slow_freq = RTC_SLOW_FREQ_RTC, \
+    .clk_rtc_clk_div = 0, \
+    .clk_8m_clk_div = 0, \
+    .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
+    .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
+}
+
+void rtc_clk_divider_set(uint32_t div);
+
+void rtc_clk_8m_divider_set(uint32_t div);
+
+/**
+ * Initialize clocks and set CPU frequency
+ *
+ * If cfg.xtal_freq is set to RTC_XTAL_FREQ_AUTO, this function will attempt
+ * to auto detect XTAL frequency. Auto detection is performed by comparing
+ * XTAL frequency with the frequency of internal 8MHz oscillator. Note that at
+ * high temperatures the frequency of the internal 8MHz oscillator may drift
+ * enough for auto detection to be unreliable.
+ * Auto detection code will attempt to distinguish between 26MHz and 40MHz
+ * crystals. 24 MHz crystals are not supported by auto detection code.
+ * If XTAL frequency can not be auto detected, this 26MHz frequency will be used.
+ *
+ * @param cfg clock configuration as rtc_clk_config_t
+ */
+void rtc_clk_init(rtc_clk_config_t cfg);
+
+/**
+ * @brief Get main XTAL frequency
+ *
+ * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
+ * rtc_clk_init function, or if the value was RTC_XTAL_FREQ_AUTO, the detected
+ * XTAL frequency.
+ *
+ * @return XTAL frequency, one of rtc_xtal_freq_t
+ */
+rtc_xtal_freq_t rtc_clk_xtal_freq_get();
+
+/**
+ * @brief Update XTAL frequency
+ *
+ * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
+ * after startup.
+ *
+ * @param xtal_freq New frequency value
+ */
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
+
+/**
+ * @brief Enable or disable 32 kHz XTAL oscillator
+ * @param en  true to enable, false to disable
+ */
+void rtc_clk_32k_enable(bool en);
+
+/**
+ * @brief Get the state of 32k XTAL oscillator
+ * @return true if 32k XTAL oscillator has been enabled
+ */
+bool rtc_clk_32k_enabled();
+
+/**
+ * @brief Enable 32k oscillator, configuring it for fast startup time.
+ * Note: to achieve higher frequency stability, rtc_clk_32k_enable function
+ * must be called one the 32k XTAL oscillator has started up. This function
+ * will initially disable the 32k XTAL oscillator, so it should not be called
+ * when the system is using 32k XTAL as RTC_SLOW_CLK.
+ *
+ * @param cycle Number of 32kHz cycles to bootstrap external crystal.
+ *              If 0, no square wave will be used to bootstrap crystal oscillation.
+ */
+void rtc_clk_32k_bootstrap(uint32_t cycle);
+
+/**
+ * @brief Enable or disable 8 MHz internal oscillator
+ *
+ * Output from 8 MHz internal oscillator is passed into a configurable
+ * divider, which by default divides the input clock frequency by 256.
+ * Output of the divider may be used as RTC_SLOW_CLK source.
+ * Output of the divider is referred to in register descriptions and code as
+ * 8md256 or simply d256. Divider values other than 256 may be configured, but
+ * this facility is not currently needed, so is not exposed in the code.
+ *
+ * When 8MHz/256 divided output is not needed, the divider should be disabled
+ * to reduce power consumption.
+ *
+ * @param clk_8m_en true to enable 8MHz generator
+ * @param d256_en true to enable /256 divider
+ */
+void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
+
+/**
+ * @brief Get the state of 8 MHz internal oscillator
+ * @return true if the oscillator is enabled
+ */
+bool rtc_clk_8m_enabled();
+
+/**
+ * @brief Get the state of /256 divider which is applied to 8MHz clock
+ * @return true if the divided output is enabled
+ */
+bool rtc_clk_8md256_enabled();
+
+/**
+ * @brief Enable or disable APLL
+ *
+ * Output frequency is given by the formula:
+ * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
+ *
+ * The dividend in this expression should be in the range of 240 - 600 MHz.
+ *
+ * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
+ *
+ * @param enable  true to enable, false to disable
+ * @param sdm0  frequency adjustment parameter, 0..255
+ * @param sdm1  frequency adjustment parameter, 0..255
+ * @param sdm2  frequency adjustment parameter, 0..63
+ * @param o_div  frequency divider, 0..31
+ */
+void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
+
+/**
+ * @brief Select source for RTC_SLOW_CLK
+ * @param slow_freq clock source (one of rtc_slow_freq_t values)
+ */
+void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
+
+/**
+ * @brief Get the RTC_SLOW_CLK source
+ * @return currently selected clock source (one of rtc_slow_freq_t values)
+ */
+rtc_slow_freq_t rtc_clk_slow_freq_get();
+
+/**
+ * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
+ *
+ * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
+ * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
+ * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
+ *
+ * rtc_clk_cal function can be used to get more precise value by comparing
+ * RTC_SLOW_CLK frequency to the frequency of main XTAL.
+ *
+ * @return RTC_SLOW_CLK frequency, in Hz
+ */
+uint32_t rtc_clk_slow_freq_get_hz();
+
+/**
+ * @brief Select source for RTC_FAST_CLK
+ * @param fast_freq clock source (one of rtc_fast_freq_t values)
+ */
+void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
+
+/**
+ * @brief Get the RTC_FAST_CLK source
+ * @return currently selected clock source (one of rtc_fast_freq_t values)
+ */
+rtc_fast_freq_t rtc_clk_fast_freq_get();
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * If a PLL-derived frequency is requested (80, 160, 240 MHz), this function
+ * will enable the PLL. Otherwise, PLL will be disabled.
+ * Note: this function is not optimized for switching speed. It may take several
+ * hundred microseconds to perform frequency switch.
+ *
+ * @param cpu_freq  new CPU frequency
+ */
+void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq);
+
+/**
+ * @brief Switch CPU frequency
+ *
+ * This is a faster version of rtc_clk_cpu_freq_set, which can handle some of
+ * the frequency switch paths (XTAL -> PLL, PLL -> XTAL).
+ * When switching from PLL to XTAL, PLL is not disabled (unlike rtc_clk_cpu_freq_set).
+ * When switching back from XTAL to PLL, only the same PLL can be used.
+ * Therefore it is not possible to switch 240 -> XTAL -> (80 or 160) using this
+ * function.
+ *
+ * For unsupported cases, this function falls back to rtc_clk_cpu_freq_set.
+ *
+ * Unlike rtc_clk_cpu_freq_set, this function relies on static data, so it is
+ * less safe to use it e.g. from a panic handler (when memory might be corrupted).
+ *
+ * @param cpu_freq  new CPU frequency
+ */
+void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq);
+
+/**
+ * @brief Get the currently selected CPU frequency
+ *
+ * Although CPU can be clocked by APLL and RTC 8M sources, such support is not
+ * exposed through this library. As such, this function will not return
+ * meaningful values when these clock sources are configured (e.g. using direct
+ * access to clock selection registers). In debug builds, it will assert; in
+ * release builds, it will return RTC_CPU_FREQ_XTAL.
+ *
+ * @return CPU frequency (one of rtc_cpu_freq_t values)
+ */
+rtc_cpu_freq_t rtc_clk_cpu_freq_get();
+
+/**
+ * @brief Get corresponding frequency value for rtc_cpu_freq_t enum value
+ * @param cpu_freq  CPU frequency, on of rtc_cpu_freq_t values
+ * @return CPU frequency, in HZ
+ */
+uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq);
+
+/**
+ * @brief Get rtc_cpu_freq_t enum value for given CPU frequency
+ * @param cpu_freq_mhz  CPU frequency, one of 80, 160, 240, 2, and XTAL frequency
+ * @param[out] out_val output, rtc_cpu_freq_t value corresponding to the frequency
+ * @return true if the given frequency value matches one of enum values
+ */
+ bool rtc_clk_cpu_freq_from_mhz(int cpu_freq_mhz, rtc_cpu_freq_t* out_val);
+
+/**
+ * @brief Store new APB frequency value into RTC_APB_FREQ_REG
+ *
+ * This function doesn't change any hardware clocks.
+ *
+ * Functions which perform frequency switching and change APB frequency call
+ * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
+ * (one of RTC general purpose retention registers). This should not normally
+ * be called from application code.
+ *
+ * @param apb_freq  new APB frequency, in Hz
+ */
+void rtc_clk_apb_freq_update(uint32_t apb_freq);
+
+/**
+ * @brief Get the current stored APB frequency.
+ * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
+ */
+uint32_t rtc_clk_apb_freq_get();
+
+#define RTC_CLK_CAL_FRACT  19  //!< Number of fractional bits in values returned by rtc_clk_cal
+
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
+
+/**
+ * @brief Measure RTC slow clock's period, based on main XTAL frequency
+ *
+ * This function will time out and return 0 if the time for the given number
+ * of cycles to be counted exceeds the expected time twice. This may happen if
+ * 32k XTAL is being calibrated, but the oscillator has not started up (due to
+ * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
+ *
+ * @param cal_clk  clock to be measured
+ * @param slow_clk_cycles  number of slow clock cycles to average
+ * @return average slow clock period in microseconds, Q13.19 fixed point format,
+ *         or 0 if calibration has timed out
+ */
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Measure ratio between XTAL frequency and RTC slow clock frequency
+ * @param cal_clk slow clock to be measured
+ * @param slow_clk_cycles number of slow clock cycles to average
+ * @return average ratio between XTAL frequency and slow clock frequency,
+ *         Q13.19 fixed point format, or 0 if calibration has timed out.
+ */
+uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
+
+/**
+ * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
+ * @param time_in_us Time interval in microseconds
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return number of slow clock cycles
+ */
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
+
+/**
+ * @brief Convert time interval from RTC_SLOW_CLK to microseconds
+ * @param time_in_us Time interval in RTC_SLOW_CLK cycles
+ * @param slow_clk_period  Period of slow clock in microseconds, Q13.19
+ *                         fixed point format (as returned by rtc_slowck_cali).
+ * @return time interval in microseconds
+ */
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
+
+/**
+ * @brief Get current value of RTC counter
+ *
+ * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
+ * cycles. Counter value is not writable by software. The value is not adjusted
+ * when switching to a different RTC_SLOW_CLK source.
+ *
+ * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
+ *
+ * @return current value of RTC counter
+ */
+uint64_t rtc_time_get();
+
+uint64_t rtc_light_slp_time_get();
+
+uint64_t rtc_deep_slp_time_get();
+
+/**
+ * @brief Busy loop until next RTC_SLOW_CLK cycle
+ *
+ * This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
+ * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
+ * one RTC_SLOW_CLK cycle later.
+ */
+void rtc_clk_wait_for_slow_cycle();
+
+/**
+ * @brief Power down flags for rtc_sleep_pd function
+ */
+typedef struct {
+    uint32_t dig_fpu : 1;    //!< Set to 1 to power down digital part in sleep
+    uint32_t rtc_fpu : 1;    //!< Set to 1 to power down RTC memories in sleep
+    uint32_t cpu_fpu : 1;    //!< Set to 1 to power down digital memories and CPU in sleep
+    uint32_t i2s_fpu : 1;    //!< Set to 1 to power down I2S in sleep
+    uint32_t bb_fpu : 1;     //!< Set to 1 to power down WiFi in sleep
+    uint32_t nrx_fpu : 1;    //!< Set to 1 to power down WiFi in sleep
+    uint32_t fe_fpu : 1;     //!< Set to 1 to power down WiFi in sleep
+} rtc_sleep_pd_config_t;
+
+/**
+ * Initializer for rtc_sleep_pd_config_t which sets all flags to the same value
+ */
+#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
+    .dig_fpu = (val), \
+    .rtc_fpu = (val), \
+    .cpu_fpu = (val), \
+    .i2s_fpu = (val), \
+    .bb_fpu = (val), \
+    .nrx_fpu = (val), \
+    .fe_fpu = (val), \
+}
+
+void rtc_sleep_pd(rtc_sleep_pd_config_t cfg);
+
+/**
+ * @brief sleep configuration for rtc_sleep_init function
+ */
+typedef struct {
+    uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
+    uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
+    uint32_t rtc_fastmem_pd_en : 1;     //!< power down RTC fast memory
+    uint32_t rtc_slowmem_pd_en : 1;     //!< power down RTC slow memory
+    uint32_t rtc_peri_pd_en : 1;        //!< power down RTC peripherals
+    uint32_t wifi_pd_en : 1;            //!< power down WiFi
+    uint32_t deep_slp : 1;              //!< power down digital domain
+    uint32_t wdt_flashboot_mod_en : 1;  //!< enable WDT flashboot mode
+    uint32_t dig_dbias_wak : 3;         //!< set bias for digital domain, in active mode
+    uint32_t dig_dbias_slp : 3;         //!< set bias for digital domain, in sleep mode
+    uint32_t rtc_dbias_wak : 3;         //!< set bias for RTC domain, in active mode
+    uint32_t rtc_dbias_slp : 3;         //!< set bias for RTC domain, in sleep mode
+    uint32_t vddsdio_pd_en : 1;         //!< power down VDDSDIO regulator
+    uint32_t deep_slp_reject : 1;
+    uint32_t light_slp_reject : 1;
+} rtc_sleep_config_t;
+
+/**
+ * Default initializer for rtc_sleep_config_t
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use) based on a combination of RTC_SLEEP_PD_x flags.
+ *
+ * @param RTC_SLEEP_PD_x flags combined using bitwise OR
+ */
+#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
+    .lslp_mem_inf_fpu = 0, \
+    .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
+    .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
+    .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
+    .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
+    .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
+    .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
+    .wdt_flashboot_mod_en = 0, \
+    .dig_dbias_wak = RTC_CNTL_DBIAS_1V10, \
+    .dig_dbias_slp = RTC_CNTL_DBIAS_0V90, \
+    .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
+    .rtc_dbias_slp = RTC_CNTL_DBIAS_0V90, \
+    .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
+    .deep_slp_reject = 1, \
+    .light_slp_reject = 1 \
+};
+
+#define RTC_SLEEP_PD_DIG                BIT(0)  //!< Deep sleep (power down digital domain)
+#define RTC_SLEEP_PD_RTC_PERIPH         BIT(1)  //!< Power down RTC peripherals
+#define RTC_SLEEP_PD_RTC_SLOW_MEM       BIT(2)  //!< Power down RTC SLOW memory
+#define RTC_SLEEP_PD_RTC_FAST_MEM       BIT(3)  //!< Power down RTC FAST memory
+#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4)  //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
+#define RTC_SLEEP_PD_VDDSDIO            BIT(5)  //!< Power down VDDSDIO regulator
+#define RTC_SLEEP_PD_WIFI               BIT(6)
+
+/**
+ * @brief Prepare the chip to enter sleep mode
+ *
+ * This function configures various power control state machines to handle
+ * entry into light sleep or deep sleep mode, switches APB and CPU clock source
+ * (usually to XTAL), and sets bias voltages for digital and RTC power domains.
+ *
+ * This function does not actually enter sleep mode; this is done using
+ * rtc_sleep_start function. Software may do some other actions between
+ * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
+ * wakeup sources.
+ * @param cfg sleep mode configuration
+ */
+void rtc_sleep_init(rtc_sleep_config_t cfg);
+
+
+/**
+ * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
+ * @param t value of RTC counter at which wakeup from sleep will happen;
+ *          only the lower 48 bits are used
+ */
+void rtc_sleep_set_wakeup_time(uint64_t t);
+
+
+#define RTC_EXT0_TRIG_EN    BIT(0)  //!< EXT0 GPIO wakeup
+#define RTC_EXT1_TRIG_EN    BIT(1)  //!< EXT1 GPIO wakeup
+#define RTC_GPIO_TRIG_EN    BIT(2)  //!< GPIO wakeup (light sleep only)
+#define RTC_TIMER_TRIG_EN   BIT(3)  //!< Timer wakeup
+#define RTC_SDIO_TRIG_EN    BIT(4)  //!< SDIO wakeup (light sleep only)
+#define RTC_MAC_TRIG_EN     BIT(5)  //!< MAC wakeup (light sleep only)
+#define RTC_UART0_TRIG_EN   BIT(6)  //!< UART0 wakeup (light sleep only)
+#define RTC_UART1_TRIG_EN   BIT(7)  //!< UART1 wakeup (light sleep only)
+#define RTC_TOUCH_TRIG_EN   BIT(8)  //!< Touch wakeup
+#define RTC_ULP_TRIG_EN     BIT(9)  //!< ULP wakeup
+#define RTC_BT_TRIG_EN      BIT(10) //!< BT wakeup (light sleep only)
+#define RTC_COCPU_TRIG_EN   BIT(11)
+#define RTC_XTAL32K_DEAD_TRIG_EN    BIT(12)
+#define RTC_COCPU_TRAP_TRIG_EN      BIT(13)
+#define RTC_USB_TRIG_EN             BIT(14)
+
+/**
+ * @brief Enter deep or light sleep mode
+ *
+ * This function enters the sleep mode previously configured using rtc_sleep_init
+ * function. Before entering sleep, software should configure wake up sources
+ * appropriately (set up GPIO wakeup registers, timer wakeup registers,
+ * and so on).
+ *
+ * If deep sleep mode was configured using rtc_sleep_init, and sleep is not
+ * rejected by hardware (based on reject_opt flags), this function never returns.
+ * When the chip wakes up from deep sleep, CPU is reset and execution starts
+ * from ROM bootloader.
+ *
+ * If light sleep mode was configured using rtc_sleep_init, this function
+ * returns on wakeup, or if sleep is rejected by hardware.
+ *
+ * @param wakeup_opt  bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
+ *                    combined with OR)
+ * @param reject_opt  bit mask of sleep reject reasons:
+ *                      - RTC_CNTL_GPIO_REJECT_EN
+ *                      - RTC_CNTL_SDIO_REJECT_EN
+ *                    These flags are used to prevent entering sleep when e.g.
+ *                    an external host is communicating via SDIO slave
+ * @return non-zero if sleep was rejected by hardware
+ */
+uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
+
+/**
+ * RTC power and clock control initialization settings
+ */
+typedef struct {
+    uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
+    uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
+    uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
+    uint32_t clkctl_init : 1;       //!< Perform clock control related initialization
+    uint32_t pwrctl_init : 1;       //!< Perform power control related initialization
+    uint32_t rtc_dboost_fpd : 1;    //!< Force power down RTC_DBOOST
+    uint32_t xtal_fpu : 1;
+    uint32_t bbpll_fpu : 1;
+} rtc_config_t;
+
+/**
+ * Default initializer of rtc_config_t.
+ *
+ * This initializer sets all fields to "reasonable" values (e.g. suggested for
+ * production use).
+ */
+#define RTC_CONFIG_DEFAULT() {\
+    .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
+    .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
+    .pll_wait  = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
+    .clkctl_init = 1, \
+    .pwrctl_init = 1, \
+    .rtc_dboost_fpd = 1, \
+    .xtal_fpu = 0, \
+    .bbpll_fpu = 0 \
+}
+
+/**
+ * Initialize RTC clock and power control related functions
+ * @param cfg configuration options as rtc_config_t
+ */
+void rtc_init(rtc_config_t cfg);
+
+#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
+#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
+
+/**
+ * Structure describing vddsdio configuration
+ */
+typedef struct {
+    uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
+    uint32_t enable : 1;    //!< Enable VDDSDIO regulator
+    uint32_t tieh  : 1;     //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
+    uint32_t drefh : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefm : 2;     //!< Tuning parameter for VDDSDIO regulator
+    uint32_t drefl : 2;     //!< Tuning parameter for VDDSDIO regulator
+} rtc_vddsdio_config_t;
+
+/**
+ * Get current VDDSDIO configuration
+ * If VDDSDIO configuration is overridden by RTC, get values from RTC
+ * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
+ * Otherwise, use default values and the level of MTDI bootstrapping pin.
+ * @return currently used VDDSDIO configuration
+ */
+rtc_vddsdio_config_t rtc_vddsdio_get_config();
+
+/**
+ * Set new VDDSDIO configuration using RTC registers.
+ * If config.force == 1, this overrides configuration done using bootstrapping
+ * pins and EFUSE.
+ *
+ * @param config new VDDSDIO configuration
+ */
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
+
+#ifdef __cplusplus
+}
+#endif
+
diff --git a/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h
new file mode 100644
index 000000000..9eacfc6b4
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc_cntl_reg.h
@@ -0,0 +1,3182 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_CNTL_REG_H_
+#define _SOC_RTC_CNTL_REG_H_
+
+/* The value that needs to be written to RTC_CNTL_WDT_WKEY to write-enable the wdt registers */
+#define RTC_CNTL_WDT_WKEY_VALUE 0x50D83AA1
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RTC_CNTL_TIME0_REG		RTC_CNTL_TIME_LOW0_REG
+#define RTC_CNTL_TIME1_REG		RTC_CNTL_TIME_HIGH0_REG
+
+#define RTC_CNTL_OPTIONS0_REG          (DR_REG_RTCCNTL_BASE + 0x0000)
+/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: SW system reset*/
+#define RTC_CNTL_SW_SYS_RST  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_M  (BIT(31))
+#define RTC_CNTL_SW_SYS_RST_V  0x1
+#define RTC_CNTL_SW_SYS_RST_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force no reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_NORST  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NORST_S  30
+/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: digital wrap force reset in deep sleep*/
+#define RTC_CNTL_DG_WRAP_FORCE_RST  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_M  (BIT(29))
+#define RTC_CNTL_DG_WRAP_FORCE_RST_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_RST_S  29
+/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_NOISO  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_M  (BIT(28))
+#define RTC_CNTL_ANALOG_FORCE_NOISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_NOISO_S  28
+/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_NOISO  (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_PLL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_NOISO_S  27
+/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_NOISO  (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_M  (BIT(26))
+#define RTC_CNTL_XTL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_NOISO_S  26
+/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_ANALOG_FORCE_ISO  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_M  (BIT(25))
+#define RTC_CNTL_ANALOG_FORCE_ISO_V  0x1
+#define RTC_CNTL_ANALOG_FORCE_ISO_S  25
+/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_PLL_FORCE_ISO  (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_PLL_FORCE_ISO_V  0x1
+#define RTC_CNTL_PLL_FORCE_ISO_S  24
+/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_XTL_FORCE_ISO  (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_M  (BIT(23))
+#define RTC_CNTL_XTL_FORCE_ISO_V  0x1
+#define RTC_CNTL_XTL_FORCE_ISO_S  23
+/* RTC_CNTL_BIAS_CORE_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
+/*description: BIAS_CORE force power up*/
+#define RTC_CNTL_BIAS_CORE_FORCE_PU  (BIT(22))
+#define RTC_CNTL_BIAS_CORE_FORCE_PU_M  (BIT(22))
+#define RTC_CNTL_BIAS_CORE_FORCE_PU_V  0x1
+#define RTC_CNTL_BIAS_CORE_FORCE_PU_S  22
+/* RTC_CNTL_BIAS_CORE_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: BIAS_CORE force power down*/
+#define RTC_CNTL_BIAS_CORE_FORCE_PD  (BIT(21))
+#define RTC_CNTL_BIAS_CORE_FORCE_PD_M  (BIT(21))
+#define RTC_CNTL_BIAS_CORE_FORCE_PD_V  0x1
+#define RTC_CNTL_BIAS_CORE_FORCE_PD_S  21
+/* RTC_CNTL_BIAS_CORE_FOLW_8M : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: BIAS_CORE follow CK8M*/
+#define RTC_CNTL_BIAS_CORE_FOLW_8M  (BIT(20))
+#define RTC_CNTL_BIAS_CORE_FOLW_8M_M  (BIT(20))
+#define RTC_CNTL_BIAS_CORE_FOLW_8M_V  0x1
+#define RTC_CNTL_BIAS_CORE_FOLW_8M_S  20
+/* RTC_CNTL_BIAS_I2C_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd1 ; */
+/*description: BIAS_I2C force power up*/
+#define RTC_CNTL_BIAS_I2C_FORCE_PU  (BIT(19))
+#define RTC_CNTL_BIAS_I2C_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_BIAS_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BIAS_I2C_FORCE_PU_S  19
+/* RTC_CNTL_BIAS_I2C_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: BIAS_I2C force power down*/
+#define RTC_CNTL_BIAS_I2C_FORCE_PD  (BIT(18))
+#define RTC_CNTL_BIAS_I2C_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_BIAS_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BIAS_I2C_FORCE_PD_S  18
+/* RTC_CNTL_BIAS_I2C_FOLW_8M : R/W ;bitpos:[17] ;default: 1'd0 ; */
+/*description: BIAS_I2C follow CK8M*/
+#define RTC_CNTL_BIAS_I2C_FOLW_8M  (BIT(17))
+#define RTC_CNTL_BIAS_I2C_FOLW_8M_M  (BIT(17))
+#define RTC_CNTL_BIAS_I2C_FOLW_8M_V  0x1
+#define RTC_CNTL_BIAS_I2C_FOLW_8M_S  17
+/* RTC_CNTL_BIAS_FORCE_NOSLEEP : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: BIAS_SLEEP force no sleep*/
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP  (BIT(16))
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP_M  (BIT(16))
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP_V  0x1
+#define RTC_CNTL_BIAS_FORCE_NOSLEEP_S  16
+/* RTC_CNTL_BIAS_FORCE_SLEEP : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: BIAS_SLEEP force sleep*/
+#define RTC_CNTL_BIAS_FORCE_SLEEP  (BIT(15))
+#define RTC_CNTL_BIAS_FORCE_SLEEP_M  (BIT(15))
+#define RTC_CNTL_BIAS_FORCE_SLEEP_V  0x1
+#define RTC_CNTL_BIAS_FORCE_SLEEP_S  15
+/* RTC_CNTL_BIAS_SLEEP_FOLW_8M : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: BIAS_SLEEP follow CK8M*/
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M  (BIT(14))
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_M  (BIT(14))
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_V  0x1
+#define RTC_CNTL_BIAS_SLEEP_FOLW_8M_S  14
+/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */
+/*description: crystall force power up*/
+#define RTC_CNTL_XTL_FORCE_PU  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_M  (BIT(13))
+#define RTC_CNTL_XTL_FORCE_PU_V  0x1
+#define RTC_CNTL_XTL_FORCE_PU_S  13
+/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: crystall force power down*/
+#define RTC_CNTL_XTL_FORCE_PD  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_M  (BIT(12))
+#define RTC_CNTL_XTL_FORCE_PD_V  0x1
+#define RTC_CNTL_XTL_FORCE_PD_S  12
+/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: BB_PLL force power up*/
+#define RTC_CNTL_BBPLL_FORCE_PU  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_M  (BIT(11))
+#define RTC_CNTL_BBPLL_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PU_S  11
+/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: BB_PLL force power down*/
+#define RTC_CNTL_BBPLL_FORCE_PD  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_M  (BIT(10))
+#define RTC_CNTL_BBPLL_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_FORCE_PD_S  10
+/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: BB_PLL_I2C force power up*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M  (BIT(9))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S  9
+/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: BB_PLL _I2C force power down*/
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M  (BIT(8))
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S  8
+/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: BB_I2C force power up*/
+#define RTC_CNTL_BB_I2C_FORCE_PU  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_M  (BIT(7))
+#define RTC_CNTL_BB_I2C_FORCE_PU_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PU_S  7
+/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: BB_I2C force power down*/
+#define RTC_CNTL_BB_I2C_FORCE_PD  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_M  (BIT(6))
+#define RTC_CNTL_BB_I2C_FORCE_PD_V  0x1
+#define RTC_CNTL_BB_I2C_FORCE_PD_S  6
+/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: PRO CPU SW reset*/
+#define RTC_CNTL_SW_PROCPU_RST  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_M  (BIT(5))
+#define RTC_CNTL_SW_PROCPU_RST_V  0x1
+#define RTC_CNTL_SW_PROCPU_RST_S  5
+/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: APP CPU SW reset*/
+#define RTC_CNTL_SW_APPCPU_RST  (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_M  (BIT(4))
+#define RTC_CNTL_SW_APPCPU_RST_V  0x1
+#define RTC_CNTL_SW_APPCPU_RST_S  4
+/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} ==
+ 0x86 will stall PRO CPU*/
+#define RTC_CNTL_SW_STALL_PROCPU_C0  0x00000003
+#define RTC_CNTL_SW_STALL_PROCPU_C0_M  ((RTC_CNTL_SW_STALL_PROCPU_C0_V)<<(RTC_CNTL_SW_STALL_PROCPU_C0_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_PROCPU_C0_S  2
+/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
+ 0x86 will stall APP CPU*/
+#define RTC_CNTL_SW_STALL_APPCPU_C0  0x00000003
+#define RTC_CNTL_SW_STALL_APPCPU_C0_M  ((RTC_CNTL_SW_STALL_APPCPU_C0_V)<<(RTC_CNTL_SW_STALL_APPCPU_C0_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C0_V  0x3
+#define RTC_CNTL_SW_STALL_APPCPU_C0_S  0
+
+#define RTC_CNTL_SLP_TIMER0_REG          (DR_REG_RTCCNTL_BASE + 0x0004)
+/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC sleep timer low 32 bits*/
+#define RTC_CNTL_SLP_VAL_LO  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_M  ((RTC_CNTL_SLP_VAL_LO_V)<<(RTC_CNTL_SLP_VAL_LO_S))
+#define RTC_CNTL_SLP_VAL_LO_V  0xFFFFFFFF
+#define RTC_CNTL_SLP_VAL_LO_S  0
+
+#define RTC_CNTL_SLP_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x0008)
+/* RTC_CNTL_MAIN_TIMER_ALARM_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: timer alarm enable bit*/
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M  (BIT(16))
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V  0x1
+#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S  16
+/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC sleep timer high 16 bits*/
+#define RTC_CNTL_SLP_VAL_HI  0x0000FFFF
+#define RTC_CNTL_SLP_VAL_HI_M  ((RTC_CNTL_SLP_VAL_HI_V)<<(RTC_CNTL_SLP_VAL_HI_S))
+#define RTC_CNTL_SLP_VAL_HI_V  0xFFFF
+#define RTC_CNTL_SLP_VAL_HI_S  0
+
+#define RTC_CNTL_TIME_UPDATE_REG          (DR_REG_RTCCNTL_BASE + 0x000c)
+/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: Set 1: to update register with RTC timer*/
+#define RTC_CNTL_TIME_UPDATE  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_M  (BIT(31))
+#define RTC_CNTL_TIME_UPDATE_V  0x1
+#define RTC_CNTL_TIME_UPDATE_S  31
+/* RTC_CNTL_TIME_VALID : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: To indicate the register is updated*/
+#define RTC_CNTL_TIME_VALID  (BIT(30))
+#define RTC_CNTL_TIME_VALID_M  (BIT(30))
+#define RTC_CNTL_TIME_VALID_V  0x1
+#define RTC_CNTL_TIME_VALID_S  30
+/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: enable to record system reset time*/
+#define RTC_CNTL_TIMER_SYS_RST  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_M  (BIT(29))
+#define RTC_CNTL_TIMER_SYS_RST_V  0x1
+#define RTC_CNTL_TIMER_SYS_RST_S  29
+/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Enable to record 40M XTAL OFF time*/
+#define RTC_CNTL_TIMER_XTL_OFF  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_M  (BIT(28))
+#define RTC_CNTL_TIMER_XTL_OFF_V  0x1
+#define RTC_CNTL_TIMER_XTL_OFF_S  28
+/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Enable to record system stall time*/
+#define RTC_CNTL_TIMER_SYS_STALL  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_M  (BIT(27))
+#define RTC_CNTL_TIMER_SYS_STALL_V  0x1
+#define RTC_CNTL_TIMER_SYS_STALL_S  27
+
+#define RTC_CNTL_TIME_LOW0_REG          (DR_REG_RTCCNTL_BASE + 0x0010)
+/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits*/
+#define RTC_CNTL_TIMER_VALUE0_LOW  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_M  ((RTC_CNTL_TIMER_VALUE0_LOW_V)<<(RTC_CNTL_TIMER_VALUE0_LOW_S))
+#define RTC_CNTL_TIMER_VALUE0_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE0_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH0_REG          (DR_REG_RTCCNTL_BASE + 0x0014)
+/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits*/
+#define RTC_CNTL_TIMER_VALUE0_HIGH  0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_M  ((RTC_CNTL_TIMER_VALUE0_HIGH_V)<<(RTC_CNTL_TIMER_VALUE0_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE0_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE0_HIGH_S  0
+
+#define RTC_CNTL_STATE0_REG          (DR_REG_RTCCNTL_BASE + 0x0018)
+/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: sleep enable bit*/
+#define RTC_CNTL_SLEEP_EN  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_M  (BIT(31))
+#define RTC_CNTL_SLEEP_EN_V  0x1
+#define RTC_CNTL_SLEEP_EN_S  31
+/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: leep reject bit*/
+#define RTC_CNTL_SLP_REJECT  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_M  (BIT(30))
+#define RTC_CNTL_SLP_REJECT_V  0x1
+#define RTC_CNTL_SLP_REJECT_S  30
+/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: leep wakeup bit*/
+#define RTC_CNTL_SLP_WAKEUP  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_M  (BIT(29))
+#define RTC_CNTL_SLP_WAKEUP_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_S  29
+/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */
+/*description: SDIO active indication*/
+#define RTC_CNTL_SDIO_ACTIVE_IND  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_M  (BIT(28))
+#define RTC_CNTL_SDIO_ACTIVE_IND_V  0x1
+#define RTC_CNTL_SDIO_ACTIVE_IND_S  28
+/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: APB to RTC using bridge   0: APB to RTC using sync*/
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M  (BIT(22))
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V  0x1
+#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S  22
+/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear rtc sleep reject cause*/
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S  1
+/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rtc software interrupt to main cpu*/
+#define RTC_CNTL_SW_CPU_INT  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_M  (BIT(0))
+#define RTC_CNTL_SW_CPU_INT_V  0x1
+#define RTC_CNTL_SW_CPU_INT_S  0
+
+#define RTC_CNTL_TIMER1_REG          (DR_REG_RTCCNTL_BASE + 0x001c)
+/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */
+/*description: PLL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_PLL_BUF_WAIT  0x000000FF
+#define RTC_CNTL_PLL_BUF_WAIT_M  ((RTC_CNTL_PLL_BUF_WAIT_V)<<(RTC_CNTL_PLL_BUF_WAIT_S))
+#define RTC_CNTL_PLL_BUF_WAIT_V  0xFF
+#define RTC_CNTL_PLL_BUF_WAIT_S  24
+#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT  20
+/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */
+/*description: XTAL wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_XTL_BUF_WAIT  0x000003FF
+#define RTC_CNTL_XTL_BUF_WAIT_M  ((RTC_CNTL_XTL_BUF_WAIT_V)<<(RTC_CNTL_XTL_BUF_WAIT_S))
+#define RTC_CNTL_XTL_BUF_WAIT_V  0x3FF
+#define RTC_CNTL_XTL_BUF_WAIT_S  14
+#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT  20
+/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */
+/*description: CK8M wait cycles in slow_clk_rtc*/
+#define RTC_CNTL_CK8M_WAIT  0x000000FF
+#define RTC_CNTL_CK8M_WAIT_M  ((RTC_CNTL_CK8M_WAIT_V)<<(RTC_CNTL_CK8M_WAIT_S))
+#define RTC_CNTL_CK8M_WAIT_V  0xFF
+#define RTC_CNTL_CK8M_WAIT_S  6
+#define RTC_CNTL_CK8M_WAIT_DEFAULT  20
+/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */
+/*description: CPU stall wait cycles in fast_clk_rtc*/
+#define RTC_CNTL_CPU_STALL_WAIT  0x0000001F
+#define RTC_CNTL_CPU_STALL_WAIT_M  ((RTC_CNTL_CPU_STALL_WAIT_V)<<(RTC_CNTL_CPU_STALL_WAIT_S))
+#define RTC_CNTL_CPU_STALL_WAIT_V  0x1F
+#define RTC_CNTL_CPU_STALL_WAIT_S  1
+/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */
+/*description: CPU stall enable bit*/
+#define RTC_CNTL_CPU_STALL_EN  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_M  (BIT(0))
+#define RTC_CNTL_CPU_STALL_EN_V  0x1
+#define RTC_CNTL_CPU_STALL_EN_S  0
+
+#define RTC_CNTL_TIMER2_REG          (DR_REG_RTCCNTL_BASE + 0x0020)
+/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */
+/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/
+#define RTC_CNTL_MIN_TIME_CK8M_OFF  0x000000FF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_M  ((RTC_CNTL_MIN_TIME_CK8M_OFF_V)<<(RTC_CNTL_MIN_TIME_CK8M_OFF_S))
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_V  0xFF
+#define RTC_CNTL_MIN_TIME_CK8M_OFF_S  24
+/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */
+/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller
+ start to work*/
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT  0x000001FF
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M  ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V)<<(RTC_CNTL_ULPCP_TOUCH_START_WAIT_S))
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V  0x1FF
+#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S  15
+
+#define RTC_CNTL_TIMER3_REG          (DR_REG_RTCCNTL_BASE + 0x0024)
+/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */
+/*description: */
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M  ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V)<<(RTC_CNTL_ROM_RAM_POWERUP_TIMER_S))
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S  25
+/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */
+/*description: */
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M  ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V)<<(RTC_CNTL_ROM_RAM_WAIT_TIMER_S))
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S  16
+/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_WIFI_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_M  ((RTC_CNTL_WIFI_POWERUP_TIMER_V)<<(RTC_CNTL_WIFI_POWERUP_TIMER_S))
+#define RTC_CNTL_WIFI_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_WIFI_POWERUP_TIMER_S  9
+/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_WIFI_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_M  ((RTC_CNTL_WIFI_WAIT_TIMER_V)<<(RTC_CNTL_WIFI_WAIT_TIMER_S))
+#define RTC_CNTL_WIFI_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_WIFI_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER4_REG          (DR_REG_RTCCNTL_BASE + 0x0028)
+/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M  ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V)<<(RTC_CNTL_DG_WRAP_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M  ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V)<<(RTC_CNTL_DG_WRAP_WAIT_TIMER_S))
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S  16
+/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */
+/*description: */
+#define RTC_CNTL_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_POWERUP_TIMER_M  ((RTC_CNTL_POWERUP_TIMER_V)<<(RTC_CNTL_POWERUP_TIMER_S))
+#define RTC_CNTL_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_POWERUP_TIMER_S  9
+/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */
+/*description: */
+#define RTC_CNTL_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_WAIT_TIMER_M  ((RTC_CNTL_WAIT_TIMER_V)<<(RTC_CNTL_WAIT_TIMER_S))
+#define RTC_CNTL_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_WAIT_TIMER_S  0
+
+#define RTC_CNTL_TIMER5_REG          (DR_REG_RTCCNTL_BASE + 0x002c)
+/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */
+/*description: */
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M  ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V)<<(RTC_CNTL_RTCMEM_POWERUP_TIMER_S))
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S  25
+/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */
+/*description: */
+#define RTC_CNTL_RTCMEM_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_RTCMEM_WAIT_TIMER_M  ((RTC_CNTL_RTCMEM_WAIT_TIMER_V)<<(RTC_CNTL_RTCMEM_WAIT_TIMER_S))
+#define RTC_CNTL_RTCMEM_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_RTCMEM_WAIT_TIMER_S  16
+/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */
+/*description: minimal sleep cycles in slow_clk_rtc*/
+#define RTC_CNTL_MIN_SLP_VAL  0x000000FF
+#define RTC_CNTL_MIN_SLP_VAL_M  ((RTC_CNTL_MIN_SLP_VAL_V)<<(RTC_CNTL_MIN_SLP_VAL_S))
+#define RTC_CNTL_MIN_SLP_VAL_V  0xFF
+#define RTC_CNTL_MIN_SLP_VAL_S  8
+#define RTC_CNTL_MIN_SLP_VAL_MIN 2
+
+#define RTC_CNTL_TIMER6_REG          (DR_REG_RTCCNTL_BASE + 0x0030)
+/* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */
+/*description: */
+#define RTC_CNTL_DG_DCDC_POWERUP_TIMER  0x0000007F
+#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M  ((RTC_CNTL_DG_DCDC_POWERUP_TIMER_V)<<(RTC_CNTL_DG_DCDC_POWERUP_TIMER_S))
+#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V  0x7F
+#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S  25
+/* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */
+/*description: */
+#define RTC_CNTL_DG_DCDC_WAIT_TIMER  0x000001FF
+#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M  ((RTC_CNTL_DG_DCDC_WAIT_TIMER_V)<<(RTC_CNTL_DG_DCDC_WAIT_TIMER_S))
+#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V  0x1FF
+#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S  16
+
+#define RTC_CNTL_ANA_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0034)
+/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_PLL_I2C_PU  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_M  (BIT(31))
+#define RTC_CNTL_PLL_I2C_PU_V  0x1
+#define RTC_CNTL_PLL_I2C_PU_S  31
+/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: CKGEN_I2C power up   otherwise power down*/
+#define RTC_CNTL_CKGEN_I2C_PU  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_M  (BIT(30))
+#define RTC_CNTL_CKGEN_I2C_PU_V  0x1
+#define RTC_CNTL_CKGEN_I2C_PU_S  30
+/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: 1: RFRX_PBUS power up   otherwise power down*/
+#define RTC_CNTL_RFRX_PBUS_PU  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_M  (BIT(28))
+#define RTC_CNTL_RFRX_PBUS_PU_V  0x1
+#define RTC_CNTL_RFRX_PBUS_PU_S  28
+/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: TXRF_I2C power up   otherwise power down*/
+#define RTC_CNTL_TXRF_I2C_PU  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_M  (BIT(27))
+#define RTC_CNTL_TXRF_I2C_PU_V  0x1
+#define RTC_CNTL_TXRF_I2C_PU_S  27
+/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: PVTMON power up   otherwise power down*/
+#define RTC_CNTL_PVTMON_PU  (BIT(26))
+#define RTC_CNTL_PVTMON_PU_M  (BIT(26))
+#define RTC_CNTL_PVTMON_PU_V  0x1
+#define RTC_CNTL_PVTMON_PU_S  26
+/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: start BBPLL calibration during sleep*/
+#define RTC_CNTL_BBPLL_CAL_SLP_START  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_M  (BIT(25))
+#define RTC_CNTL_BBPLL_CAL_SLP_START_V  0x1
+#define RTC_CNTL_BBPLL_CAL_SLP_START_S  25
+/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: PLLA force power up*/
+#define RTC_CNTL_PLLA_FORCE_PU  (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_M  (BIT(24))
+#define RTC_CNTL_PLLA_FORCE_PU_V  0x1
+#define RTC_CNTL_PLLA_FORCE_PU_S  24
+/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: PLLA force power down*/
+#define RTC_CNTL_PLLA_FORCE_PD  (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_M  (BIT(23))
+#define RTC_CNTL_PLLA_FORCE_PD_V  0x1
+#define RTC_CNTL_PLLA_FORCE_PD_S  23
+
+#define RTC_CNTL_RESET_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x0038)
+/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: PRO CPU state vector sel*/
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL  (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M  (BIT(13))
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V  0x1
+#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S  13
+/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: APP CPU state vector sel*/
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL  (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M  (BIT(12))
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V  0x1
+#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S  12
+/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */
+/*description: reset cause of APP CPU*/
+#define RTC_CNTL_RESET_CAUSE_APPCPU  0x0000003F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_M  ((RTC_CNTL_RESET_CAUSE_APPCPU_V)<<(RTC_CNTL_RESET_CAUSE_APPCPU_S))
+#define RTC_CNTL_RESET_CAUSE_APPCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_APPCPU_S  6
+/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */
+/*description: reset cause of PRO CPU*/
+#define RTC_CNTL_RESET_CAUSE_PROCPU  0x0000003F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_M  ((RTC_CNTL_RESET_CAUSE_PROCPU_V)<<(RTC_CNTL_RESET_CAUSE_PROCPU_S))
+#define RTC_CNTL_RESET_CAUSE_PROCPU_V  0x3F
+#define RTC_CNTL_RESET_CAUSE_PROCPU_S  0
+
+#define RTC_CNTL_WAKEUP_STATE_REG          (DR_REG_RTCCNTL_BASE + 0x003c)
+/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: enable filter for gpio wakeup event*/
+#define RTC_CNTL_GPIO_WAKEUP_FILTER  (BIT(30))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_M  (BIT(30))
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_V  0x1
+#define RTC_CNTL_GPIO_WAKEUP_FILTER_S  30
+/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[29:15] ;default: 15'b1100 ; */
+/*description: wakeup enable bitmap*/
+#define RTC_CNTL_WAKEUP_ENA  0x00007FFF
+#define RTC_CNTL_WAKEUP_ENA_M  ((RTC_CNTL_WAKEUP_ENA_V)<<(RTC_CNTL_WAKEUP_ENA_S))
+#define RTC_CNTL_WAKEUP_ENA_V  0x7FFF
+#define RTC_CNTL_WAKEUP_ENA_S  15
+/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[14:0] ;default: 15'h0 ; */
+/*description: wakeup cause*/
+#define RTC_CNTL_WAKEUP_CAUSE  0x00007FFF
+#define RTC_CNTL_WAKEUP_CAUSE_M  ((RTC_CNTL_WAKEUP_CAUSE_V)<<(RTC_CNTL_WAKEUP_CAUSE_S))
+#define RTC_CNTL_WAKEUP_CAUSE_V  0x7FFF
+#define RTC_CNTL_WAKEUP_CAUSE_S  0
+
+#define RTC_CNTL_INT_ENA_REG          (DR_REG_RTCCNTL_BASE + 0x0040)
+/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_COCPU_TRAP_INT_ENA  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_ENA_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: enable cocpu trap interrupt*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S  16
+/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable super watch dog interrupt*/
+#define RTC_CNTL_SWD_INT_ENA  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ENA_V  0x1
+#define RTC_CNTL_SWD_INT_ENA_S  15
+/* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable saradc2 interrupt*/
+#define RTC_CNTL_SARADC2_INT_ENA  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ENA_V  0x1
+#define RTC_CNTL_SARADC2_INT_ENA_S  14
+/* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: enable riscV cocpu interrupt*/
+#define RTC_CNTL_COCPU_INT_ENA  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ENA_V  0x1
+#define RTC_CNTL_COCPU_INT_ENA_S  13
+/* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: enable tsens interrupt*/
+#define RTC_CNTL_TSENS_INT_ENA  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ENA_V  0x1
+#define RTC_CNTL_TSENS_INT_ENA_S  12
+/* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: enable saradc1 interrupt*/
+#define RTC_CNTL_SARADC1_INT_ENA  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ENA_V  0x1
+#define RTC_CNTL_SARADC1_INT_ENA_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: enable RTC main timer interrupt*/
+#define RTC_CNTL_MAIN_TIMER_INT_ENA  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ENA_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: enable brown out interrupt*/
+#define RTC_CNTL_BROWN_OUT_INT_ENA  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ENA_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable touch inactive interrupt*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable touch active interrupt*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable touch done interrupt*/
+#define RTC_CNTL_TOUCH_DONE_INT_ENA  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_ENA_S  6
+/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable ULP-coprocessor interrupt*/
+#define RTC_CNTL_ULP_CP_INT_ENA  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ENA_V  0x1
+#define RTC_CNTL_ULP_CP_INT_ENA_S  5
+/* RTC_CNTL_TIME_VALID_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable RTC time valid interrupt*/
+#define RTC_CNTL_TIME_VALID_INT_ENA  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ENA_M  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ENA_V  0x1
+#define RTC_CNTL_TIME_VALID_INT_ENA_S  4
+/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable RTC WDT interrupt*/
+#define RTC_CNTL_WDT_INT_ENA  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ENA_V  0x1
+#define RTC_CNTL_WDT_INT_ENA_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable SDIO idle interrupt*/
+#define RTC_CNTL_SDIO_IDLE_INT_ENA  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ENA_S  2
+/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable sleep reject interrupt*/
+#define RTC_CNTL_SLP_REJECT_INT_ENA  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ENA_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable sleep wakeup interrupt*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S  0
+
+#define RTC_CNTL_INT_RAW_REG          (DR_REG_RTCCNTL_BASE + 0x0044)
+/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: cocpu trap interrupt raw*/
+#define RTC_CNTL_COCPU_TRAP_INT_RAW  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_RAW_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_RAW_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_RAW_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt raw*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S  16
+/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt raw*/
+#define RTC_CNTL_SWD_INT_RAW  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_RAW_V  0x1
+#define RTC_CNTL_SWD_INT_RAW_S  15
+/* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: saradc2 interrupt raw*/
+#define RTC_CNTL_SARADC2_INT_RAW  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_RAW_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_RAW_V  0x1
+#define RTC_CNTL_SARADC2_INT_RAW_S  14
+/* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: riscV cocpu interrupt raw*/
+#define RTC_CNTL_COCPU_INT_RAW  (BIT(13))
+#define RTC_CNTL_COCPU_INT_RAW_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_RAW_V  0x1
+#define RTC_CNTL_COCPU_INT_RAW_S  13
+/* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: tsens interrupt raw*/
+#define RTC_CNTL_TSENS_INT_RAW  (BIT(12))
+#define RTC_CNTL_TSENS_INT_RAW_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_RAW_V  0x1
+#define RTC_CNTL_TSENS_INT_RAW_S  12
+/* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: saradc1 interrupt raw*/
+#define RTC_CNTL_SARADC1_INT_RAW  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_RAW_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_RAW_V  0x1
+#define RTC_CNTL_SARADC1_INT_RAW_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt raw*/
+#define RTC_CNTL_MAIN_TIMER_INT_RAW  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_RAW_S  10
+/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt raw*/
+#define RTC_CNTL_BROWN_OUT_INT_RAW  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_RAW_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_RAW_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: touch inactive interrupt raw*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: touch active interrupt raw*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: touch interrupt raw*/
+#define RTC_CNTL_TOUCH_DONE_INT_RAW  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_RAW_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_RAW_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_RAW_S  6
+/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ULP-coprocessor interrupt raw*/
+#define RTC_CNTL_ULP_CP_INT_RAW  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_RAW_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_RAW_V  0x1
+#define RTC_CNTL_ULP_CP_INT_RAW_S  5
+/* RTC_CNTL_TIME_VALID_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: RTC time valid interrupt raw*/
+#define RTC_CNTL_TIME_VALID_INT_RAW  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_RAW_M  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_RAW_V  0x1
+#define RTC_CNTL_TIME_VALID_INT_RAW_S  4
+/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt raw*/
+#define RTC_CNTL_WDT_INT_RAW  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_RAW_V  0x1
+#define RTC_CNTL_WDT_INT_RAW_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SDIO idle interrupt raw*/
+#define RTC_CNTL_SDIO_IDLE_INT_RAW  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_RAW_S  2
+/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt raw*/
+#define RTC_CNTL_SLP_REJECT_INT_RAW  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_RAW_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt raw*/
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S  0
+
+#define RTC_CNTL_INT_ST_REG          (DR_REG_RTCCNTL_BASE + 0x0048)
+/* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: cocpu trap interrupt state*/
+#define RTC_CNTL_COCPU_TRAP_INT_ST  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ST_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_ST_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_ST_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: xtal32k dead detection interrupt state*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S  16
+/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: super watch dog interrupt state*/
+#define RTC_CNTL_SWD_INT_ST  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_ST_V  0x1
+#define RTC_CNTL_SWD_INT_ST_S  15
+/* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: saradc2 interrupt state*/
+#define RTC_CNTL_SARADC2_INT_ST  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ST_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_ST_V  0x1
+#define RTC_CNTL_SARADC2_INT_ST_S  14
+/* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: riscV cocpu interrupt state*/
+#define RTC_CNTL_COCPU_INT_ST  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ST_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_ST_V  0x1
+#define RTC_CNTL_COCPU_INT_ST_S  13
+/* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: tsens interrupt state*/
+#define RTC_CNTL_TSENS_INT_ST  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ST_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_ST_V  0x1
+#define RTC_CNTL_TSENS_INT_ST_S  12
+/* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: saradc1 interrupt state*/
+#define RTC_CNTL_SARADC1_INT_ST  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ST_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_ST_V  0x1
+#define RTC_CNTL_SARADC1_INT_ST_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_ST  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_ST_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_ST_S  10
+/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_ST  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_ST_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_ST_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: touch inactive interrupt state*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: touch active interrupt state*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: touch done interrupt state*/
+#define RTC_CNTL_TOUCH_DONE_INT_ST  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ST_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_ST_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_ST_S  6
+/* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ULP-coprocessor interrupt state*/
+#define RTC_CNTL_ULP_CP_INT_ST  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ST_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_ST_V  0x1
+#define RTC_CNTL_ULP_CP_INT_ST_S  5
+/* RTC_CNTL_TIME_VALID_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: RTC time valid interrupt state*/
+#define RTC_CNTL_TIME_VALID_INT_ST  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ST_M  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_ST_V  0x1
+#define RTC_CNTL_TIME_VALID_INT_ST_S  4
+/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_ST  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_ST_V  0x1
+#define RTC_CNTL_WDT_INT_ST_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: SDIO idle interrupt state*/
+#define RTC_CNTL_SDIO_IDLE_INT_ST  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_ST_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_ST_S  2
+/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_ST  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_ST_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_ST_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_ST  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_ST_S  0
+
+#define RTC_CNTL_INT_CLR_REG          (DR_REG_RTCCNTL_BASE + 0x004c)
+/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: Clear cocpu trap interrupt state*/
+#define RTC_CNTL_COCPU_TRAP_INT_CLR  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_CLR_M  (BIT(17))
+#define RTC_CNTL_COCPU_TRAP_INT_CLR_V  0x1
+#define RTC_CNTL_COCPU_TRAP_INT_CLR_S  17
+/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state*/
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M  (BIT(16))
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V  0x1
+#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S  16
+/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: Clear super watch dog interrupt state*/
+#define RTC_CNTL_SWD_INT_CLR  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_M  (BIT(15))
+#define RTC_CNTL_SWD_INT_CLR_V  0x1
+#define RTC_CNTL_SWD_INT_CLR_S  15
+/* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: Clear saradc2 interrupt state*/
+#define RTC_CNTL_SARADC2_INT_CLR  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_CLR_M  (BIT(14))
+#define RTC_CNTL_SARADC2_INT_CLR_V  0x1
+#define RTC_CNTL_SARADC2_INT_CLR_S  14
+/* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Clear riscV cocpu interrupt state*/
+#define RTC_CNTL_COCPU_INT_CLR  (BIT(13))
+#define RTC_CNTL_COCPU_INT_CLR_M  (BIT(13))
+#define RTC_CNTL_COCPU_INT_CLR_V  0x1
+#define RTC_CNTL_COCPU_INT_CLR_S  13
+/* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Clear tsens interrupt state*/
+#define RTC_CNTL_TSENS_INT_CLR  (BIT(12))
+#define RTC_CNTL_TSENS_INT_CLR_M  (BIT(12))
+#define RTC_CNTL_TSENS_INT_CLR_V  0x1
+#define RTC_CNTL_TSENS_INT_CLR_S  12
+/* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: Clear saradc1 interrupt state*/
+#define RTC_CNTL_SARADC1_INT_CLR  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_CLR_M  (BIT(11))
+#define RTC_CNTL_SARADC1_INT_CLR_V  0x1
+#define RTC_CNTL_SARADC1_INT_CLR_S  11
+/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: Clear RTC main timer interrupt state*/
+#define RTC_CNTL_MAIN_TIMER_INT_CLR  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_M  (BIT(10))
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_V  0x1
+#define RTC_CNTL_MAIN_TIMER_INT_CLR_S  10
+/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Clear brown out interrupt state*/
+#define RTC_CNTL_BROWN_OUT_INT_CLR  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_M  (BIT(9))
+#define RTC_CNTL_BROWN_OUT_INT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_INT_CLR_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Clear touch inactive interrupt state*/
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S  8
+/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Clear touch active interrupt state*/
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M  (BIT(7))
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S  7
+/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Clear touch done interrupt state*/
+#define RTC_CNTL_TOUCH_DONE_INT_CLR  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_CLR_M  (BIT(6))
+#define RTC_CNTL_TOUCH_DONE_INT_CLR_V  0x1
+#define RTC_CNTL_TOUCH_DONE_INT_CLR_S  6
+/* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Clear ULP-coprocessor interrupt state*/
+#define RTC_CNTL_ULP_CP_INT_CLR  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_CLR_M  (BIT(5))
+#define RTC_CNTL_ULP_CP_INT_CLR_V  0x1
+#define RTC_CNTL_ULP_CP_INT_CLR_S  5
+/* RTC_CNTL_TIME_VALID_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Clear RTC time valid interrupt state*/
+#define RTC_CNTL_TIME_VALID_INT_CLR  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_CLR_M  (BIT(4))
+#define RTC_CNTL_TIME_VALID_INT_CLR_V  0x1
+#define RTC_CNTL_TIME_VALID_INT_CLR_S  4
+/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Clear RTC WDT interrupt state*/
+#define RTC_CNTL_WDT_INT_CLR  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_M  (BIT(3))
+#define RTC_CNTL_WDT_INT_CLR_V  0x1
+#define RTC_CNTL_WDT_INT_CLR_S  3
+/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Clear SDIO idle interrupt state*/
+#define RTC_CNTL_SDIO_IDLE_INT_CLR  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_M  (BIT(2))
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_V  0x1
+#define RTC_CNTL_SDIO_IDLE_INT_CLR_S  2
+/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Clear sleep reject interrupt state*/
+#define RTC_CNTL_SLP_REJECT_INT_CLR  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_M  (BIT(1))
+#define RTC_CNTL_SLP_REJECT_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_REJECT_INT_CLR_S  1
+/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Clear sleep wakeup interrupt state*/
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M  (BIT(0))
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V  0x1
+#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S  0
+
+#define RTC_CNTL_STORE0_REG          (DR_REG_RTCCNTL_BASE + 0x0050)
+/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH0  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_M  ((RTC_CNTL_SCRATCH0_V)<<(RTC_CNTL_SCRATCH0_S))
+#define RTC_CNTL_SCRATCH0_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH0_S  0
+
+#define RTC_CNTL_STORE1_REG          (DR_REG_RTCCNTL_BASE + 0x0054)
+/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH1  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_M  ((RTC_CNTL_SCRATCH1_V)<<(RTC_CNTL_SCRATCH1_S))
+#define RTC_CNTL_SCRATCH1_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH1_S  0
+
+#define RTC_CNTL_STORE2_REG          (DR_REG_RTCCNTL_BASE + 0x0058)
+/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH2  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_M  ((RTC_CNTL_SCRATCH2_V)<<(RTC_CNTL_SCRATCH2_S))
+#define RTC_CNTL_SCRATCH2_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH2_S  0
+
+#define RTC_CNTL_STORE3_REG          (DR_REG_RTCCNTL_BASE + 0x005c)
+/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH3  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_M  ((RTC_CNTL_SCRATCH3_V)<<(RTC_CNTL_SCRATCH3_S))
+#define RTC_CNTL_SCRATCH3_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH3_S  0
+
+#define RTC_CNTL_EXT_XTL_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0060)
+/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_XTL_EXT_CTR_EN  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_M  (BIT(31))
+#define RTC_CNTL_XTL_EXT_CTR_EN_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_EN_S  31
+/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: power down XTAL at high level  1: power down XTAL at low level*/
+#define RTC_CNTL_XTL_EXT_CTR_LV  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_M  (BIT(30))
+#define RTC_CNTL_XTL_EXT_CTR_LV_V  0x1
+#define RTC_CNTL_XTL_EXT_CTR_LV_S  30
+/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: XTAL_32K sel. 0: external XTAL_32K  1: CLK from RTC pad X32P_C*/
+#define RTC_CNTL_XTAL32K_GPIO_SEL  (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_M  (BIT(23))
+#define RTC_CNTL_XTAL32K_GPIO_SEL_V  0x1
+#define RTC_CNTL_XTAL32K_GPIO_SEL_S  23
+/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[22:17] ;default: 6'd3 ; */
+/*description: DAC_XTAL_32K*/
+#define RTC_CNTL_DAC_XTAL_32K  0x0000003F
+#define RTC_CNTL_DAC_XTAL_32K_M  ((RTC_CNTL_DAC_XTAL_32K_V)<<(RTC_CNTL_DAC_XTAL_32K_S))
+#define RTC_CNTL_DAC_XTAL_32K_V  0x3F
+#define RTC_CNTL_DAC_XTAL_32K_S  17
+/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: XPD_XTAL_32K*/
+#define RTC_CNTL_XPD_XTAL_32K  (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_M  (BIT(16))
+#define RTC_CNTL_XPD_XTAL_32K_V  0x1
+#define RTC_CNTL_XPD_XTAL_32K_S  16
+/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */
+/*description: DRES_XTAL_32K*/
+#define RTC_CNTL_DRES_XTAL_32K  0x00000007
+#define RTC_CNTL_DRES_XTAL_32K_M  ((RTC_CNTL_DRES_XTAL_32K_V)<<(RTC_CNTL_DRES_XTAL_32K_S))
+#define RTC_CNTL_DRES_XTAL_32K_V  0x7
+#define RTC_CNTL_DRES_XTAL_32K_S  13
+/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */
+/*description: xtal_32k gm control*/
+#define RTC_CNTL_DGM_XTAL_32K  0x00000007
+#define RTC_CNTL_DGM_XTAL_32K_M  ((RTC_CNTL_DGM_XTAL_32K_V)<<(RTC_CNTL_DGM_XTAL_32K_S))
+#define RTC_CNTL_DGM_XTAL_32K_V  0x7
+#define RTC_CNTL_DGM_XTAL_32K_S  10
+/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 0: single-end buffer 1: differential buffer*/
+#define RTC_CNTL_DBUF_XTAL_32K  (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_M  (BIT(9))
+#define RTC_CNTL_DBUF_XTAL_32K_V  0x1
+#define RTC_CNTL_DBUF_XTAL_32K_S  9
+/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: apply an internal clock to help xtal 32k to start*/
+#define RTC_CNTL_ENCKINIT_XTAL_32K  (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_M  (BIT(8))
+#define RTC_CNTL_ENCKINIT_XTAL_32K_V  0x1
+#define RTC_CNTL_ENCKINIT_XTAL_32K_S  8
+/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: Xtal 32k xpd control by sw or fsm*/
+#define RTC_CNTL_XTAL32K_XPD_FORCE  (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_M  (BIT(7))
+#define RTC_CNTL_XTAL32K_XPD_FORCE_V  0x1
+#define RTC_CNTL_XTAL32K_XPD_FORCE_S  7
+/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: xtal 32k switch back xtal when xtal is restarted*/
+#define RTC_CNTL_XTAL32K_AUTO_RETURN  (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_M  (BIT(6))
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RETURN_S  6
+/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: xtal 32k restart xtal when xtal is dead*/
+#define RTC_CNTL_XTAL32K_AUTO_RESTART  (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_M  (BIT(5))
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_RESTART_S  5
+/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: xtal 32k switch to back up clock when xtal is dead*/
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP  (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M  (BIT(4))
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V  0x1
+#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S  4
+/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: xtal 32k external xtal clock force on*/
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO  (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M  (BIT(3))
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S  3
+/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog sw reset*/
+#define RTC_CNTL_XTAL32K_WDT_RESET  (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_M  (BIT(2))
+#define RTC_CNTL_XTAL32K_WDT_RESET_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_RESET_S  2
+/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog clock force on*/
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO  (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M  (BIT(1))
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S  1
+/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: xtal 32k watch dog enable*/
+#define RTC_CNTL_XTAL32K_WDT_EN  (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_M  (BIT(0))
+#define RTC_CNTL_XTAL32K_WDT_EN_V  0x1
+#define RTC_CNTL_XTAL32K_WDT_EN_S  0
+
+#define RTC_CNTL_EXT_WAKEUP_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0064)
+/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_EXT_WAKEUP1_LV  (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_M  (BIT(31))
+#define RTC_CNTL_EXT_WAKEUP1_LV_V  0x1
+#define RTC_CNTL_EXT_WAKEUP1_LV_S  31
+/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: 0: external wakeup at low level  1: external wakeup at high level*/
+#define RTC_CNTL_EXT_WAKEUP0_LV  (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_M  (BIT(30))
+#define RTC_CNTL_EXT_WAKEUP0_LV_V  0x1
+#define RTC_CNTL_EXT_WAKEUP0_LV_S  30
+
+#define RTC_CNTL_SLP_REJECT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0068)
+/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: enable reject for deep sleep*/
+#define RTC_CNTL_DEEP_SLP_REJECT_EN  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_M  (BIT(31))
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_DEEP_SLP_REJECT_EN_S  31
+/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable reject for light sleep*/
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M  (BIT(30))
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V  0x1
+#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S  30
+/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:15] ;default: 15'd0 ; */
+/*description: sleep reject enable*/
+#define RTC_CNTL_SLEEP_REJECT_ENA  0x00007FFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_M  ((RTC_CNTL_SLEEP_REJECT_ENA_V)<<(RTC_CNTL_SLEEP_REJECT_ENA_S))
+#define RTC_CNTL_SLEEP_REJECT_ENA_V  0x7FFF
+#define RTC_CNTL_SLEEP_REJECT_ENA_S  15
+/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[14:0] ;default: 15'd0 ; */
+/*description: sleep reject cause*/
+#define RTC_CNTL_REJECT_CAUSE  0x00007FFF
+#define RTC_CNTL_REJECT_CAUSE_M  ((RTC_CNTL_REJECT_CAUSE_V)<<(RTC_CNTL_REJECT_CAUSE_S))
+#define RTC_CNTL_REJECT_CAUSE_V  0x7FFF
+#define RTC_CNTL_REJECT_CAUSE_S  0
+
+#define RTC_CNTL_CPU_PERIOD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x006c)
+/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */
+/*description: */
+#define RTC_CNTL_CPUPERIOD_SEL  0x00000003
+#define RTC_CNTL_CPUPERIOD_SEL_M  ((RTC_CNTL_CPUPERIOD_SEL_V)<<(RTC_CNTL_CPUPERIOD_SEL_S))
+#define RTC_CNTL_CPUPERIOD_SEL_V  0x3
+#define RTC_CNTL_CPUPERIOD_SEL_S  30
+/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: CPU sel option*/
+#define RTC_CNTL_CPUSEL_CONF  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_M  (BIT(29))
+#define RTC_CNTL_CPUSEL_CONF_V  0x1
+#define RTC_CNTL_CPUSEL_CONF_S  29
+
+#define RTC_CNTL_SDIO_ACT_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0070)
+/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */
+/*description: */
+#define RTC_CNTL_SDIO_ACT_DNUM  0x000003FF
+#define RTC_CNTL_SDIO_ACT_DNUM_M  ((RTC_CNTL_SDIO_ACT_DNUM_V)<<(RTC_CNTL_SDIO_ACT_DNUM_S))
+#define RTC_CNTL_SDIO_ACT_DNUM_V  0x3FF
+#define RTC_CNTL_SDIO_ACT_DNUM_S  22
+
+#define RTC_CNTL_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0074)
+/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: */
+#define RTC_CNTL_ANA_CLK_RTC_SEL  0x00000003
+#define RTC_CNTL_ANA_CLK_RTC_SEL_M  ((RTC_CNTL_ANA_CLK_RTC_SEL_V)<<(RTC_CNTL_ANA_CLK_RTC_SEL_S))
+#define RTC_CNTL_ANA_CLK_RTC_SEL_V  0x3
+#define RTC_CNTL_ANA_CLK_RTC_SEL_S  30
+/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: fast_clk_rtc sel. 0: XTAL div 4  1: CK8M*/
+#define RTC_CNTL_FAST_CLK_RTC_SEL  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_M  (BIT(29))
+#define RTC_CNTL_FAST_CLK_RTC_SEL_V  0x1
+#define RTC_CNTL_FAST_CLK_RTC_SEL_S  29
+/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: CK8M force power up*/
+#define RTC_CNTL_CK8M_FORCE_PU  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_M  (BIT(26))
+#define RTC_CNTL_CK8M_FORCE_PU_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PU_S  26
+/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: CK8M force power down*/
+#define RTC_CNTL_CK8M_FORCE_PD  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_M  (BIT(25))
+#define RTC_CNTL_CK8M_FORCE_PD_V  0x1
+#define RTC_CNTL_CK8M_FORCE_PD_S  25
+/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */
+/*description: CK8M_DFREQ*/
+#define RTC_CNTL_CK8M_DFREQ  0x000000FF
+#define RTC_CNTL_CK8M_DFREQ_M  ((RTC_CNTL_CK8M_DFREQ_V)<<(RTC_CNTL_CK8M_DFREQ_S))
+#define RTC_CNTL_CK8M_DFREQ_V  0xFF
+#define RTC_CNTL_CK8M_DFREQ_S  17
+#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 //TODO, may change in chip7.2.2
+/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: CK8M force no gating during sleep*/
+#define RTC_CNTL_CK8M_FORCE_NOGATING  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_M  (BIT(16))
+#define RTC_CNTL_CK8M_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_CK8M_FORCE_NOGATING_S  16
+/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: XTAL force no gating during sleep*/
+#define RTC_CNTL_XTAL_FORCE_NOGATING  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_M  (BIT(15))
+#define RTC_CNTL_XTAL_FORCE_NOGATING_V  0x1
+#define RTC_CNTL_XTAL_FORCE_NOGATING_S  15
+/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */
+/*description: divider = reg_ck8m_div_sel + 1*/
+#define RTC_CNTL_CK8M_DIV_SEL  0x00000007
+#define RTC_CNTL_CK8M_DIV_SEL_M  ((RTC_CNTL_CK8M_DIV_SEL_V)<<(RTC_CNTL_CK8M_DIV_SEL_S))
+#define RTC_CNTL_CK8M_DIV_SEL_V  0x7
+#define RTC_CNTL_CK8M_DIV_SEL_S  12
+/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable CK8M for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_EN  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_M  (BIT(10))
+#define RTC_CNTL_DIG_CLK8M_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_EN_S  10
+/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_CLK8M_D256_EN  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_M  (BIT(9))
+#define RTC_CNTL_DIG_CLK8M_D256_EN_V  0x1
+#define RTC_CNTL_DIG_CLK8M_D256_EN_S  9
+/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+#define RTC_CNTL_DIG_XTAL32K_EN  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_M  (BIT(8))
+#define RTC_CNTL_DIG_XTAL32K_EN_V  0x1
+#define RTC_CNTL_DIG_XTAL32K_EN_S  8
+/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: 1: CK8M_D256_OUT is actually CK8M  0: CK8M_D256_OUT is CK8M divided by 256*/
+#define RTC_CNTL_ENB_CK8M_DIV  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_M  (BIT(7))
+#define RTC_CNTL_ENB_CK8M_DIV_V  0x1
+#define RTC_CNTL_ENB_CK8M_DIV_S  7
+/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: disable CK8M and CK8M_D256_OUT*/
+#define RTC_CNTL_ENB_CK8M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_M  (BIT(6))
+#define RTC_CNTL_ENB_CK8M_V  0x1
+#define RTC_CNTL_ENB_CK8M_S  6
+/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */
+/*description: CK8M_D256_OUT divider. 00: div128  01: div256  10: div512  11: div1024.*/
+#define RTC_CNTL_CK8M_DIV  0x00000003
+#define RTC_CNTL_CK8M_DIV_M  ((RTC_CNTL_CK8M_DIV_V)<<(RTC_CNTL_CK8M_DIV_S))
+#define RTC_CNTL_CK8M_DIV_V  0x3
+#define RTC_CNTL_CK8M_DIV_S  4
+/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
+  then set vld to actually switch the clk*/
+#define RTC_CNTL_CK8M_DIV_SEL_VLD  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_M  (BIT(3))
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_V  0x1
+#define RTC_CNTL_CK8M_DIV_SEL_VLD_S  3
+
+#define RTC_CNTL_SLOW_CLK_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0078)
+/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M  (BIT(31))
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V  0x1
+#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S  31
+/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */
+/*description: */
+#define RTC_CNTL_ANA_CLK_DIV  0x000000FF
+#define RTC_CNTL_ANA_CLK_DIV_M  ((RTC_CNTL_ANA_CLK_DIV_V)<<(RTC_CNTL_ANA_CLK_DIV_S))
+#define RTC_CNTL_ANA_CLK_DIV_V  0xFF
+#define RTC_CNTL_ANA_CLK_DIV_S  23
+/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div
+  then set vld to actually switch the clk*/
+#define RTC_CNTL_ANA_CLK_DIV_VLD  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_M  (BIT(22))
+#define RTC_CNTL_ANA_CLK_DIV_VLD_V  0x1
+#define RTC_CNTL_ANA_CLK_DIV_VLD_S  22
+
+#define RTC_CNTL_SDIO_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x007c)
+/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_XPD_SDIO_REG  (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_M  (BIT(31))
+#define RTC_CNTL_XPD_SDIO_REG_V  0x1
+#define RTC_CNTL_XPD_SDIO_REG_S  31
+/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */
+/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFH_SDIO  0x00000003
+#define RTC_CNTL_DREFH_SDIO_M  ((RTC_CNTL_DREFH_SDIO_V)<<(RTC_CNTL_DREFH_SDIO_S))
+#define RTC_CNTL_DREFH_SDIO_V  0x3
+#define RTC_CNTL_DREFH_SDIO_S  29
+/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b00 ; */
+/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFM_SDIO  0x00000003
+#define RTC_CNTL_DREFM_SDIO_M  ((RTC_CNTL_DREFM_SDIO_V)<<(RTC_CNTL_DREFM_SDIO_S))
+#define RTC_CNTL_DREFM_SDIO_V  0x3
+#define RTC_CNTL_DREFM_SDIO_S  27
+/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */
+/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_DREFL_SDIO  0x00000003
+#define RTC_CNTL_DREFL_SDIO_M  ((RTC_CNTL_DREFL_SDIO_V)<<(RTC_CNTL_DREFL_SDIO_S))
+#define RTC_CNTL_DREFL_SDIO_V  0x3
+#define RTC_CNTL_DREFL_SDIO_S  25
+/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */
+/*description: read only register for REG1P8_READY*/
+#define RTC_CNTL_REG1P8_READY  (BIT(24))
+#define RTC_CNTL_REG1P8_READY_M  (BIT(24))
+#define RTC_CNTL_REG1P8_READY_V  0x1
+#define RTC_CNTL_REG1P8_READY_S  24
+/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+#define RTC_CNTL_SDIO_TIEH  (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_M  (BIT(23))
+#define RTC_CNTL_SDIO_TIEH_V  0x1
+#define RTC_CNTL_SDIO_TIEH_S  23
+/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: 1: use SW option to control SDIO_REG  0: use state machine*/
+#define RTC_CNTL_SDIO_FORCE  (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_M  (BIT(22))
+#define RTC_CNTL_SDIO_FORCE_V  0x1
+#define RTC_CNTL_SDIO_FORCE_S  22
+/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+#define RTC_CNTL_SDIO_PD_EN  (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_M  (BIT(21))
+#define RTC_CNTL_SDIO_PD_EN_V  0x1
+#define RTC_CNTL_SDIO_PD_EN_S  21
+/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: enable current limit*/
+#define RTC_CNTL_SDIO_ENCURLIM  (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_M  (BIT(20))
+#define RTC_CNTL_SDIO_ENCURLIM_V  0x1
+#define RTC_CNTL_SDIO_ENCURLIM_S  20
+/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: select current limit mode*/
+#define RTC_CNTL_SDIO_MODECURLIM  (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_M  (BIT(19))
+#define RTC_CNTL_SDIO_MODECURLIM_V  0x1
+#define RTC_CNTL_SDIO_MODECURLIM_S  19
+/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */
+/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
+#define RTC_CNTL_SDIO_DCURLIM  0x00000007
+#define RTC_CNTL_SDIO_DCURLIM_M  ((RTC_CNTL_SDIO_DCURLIM_V)<<(RTC_CNTL_SDIO_DCURLIM_S))
+#define RTC_CNTL_SDIO_DCURLIM_V  0x7
+#define RTC_CNTL_SDIO_DCURLIM_S  16
+/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */
+/*description: 0 to set init[1:0]=0*/
+#define RTC_CNTL_SDIO_EN_INITI  (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_M  (BIT(15))
+#define RTC_CNTL_SDIO_EN_INITI_V  0x1
+#define RTC_CNTL_SDIO_EN_INITI_S  15
+/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */
+/*description: add resistor from ldo output to ground. 0: no res  1: 6k  2: 4k  3: 2k*/
+#define RTC_CNTL_SDIO_INITI  0x00000003
+#define RTC_CNTL_SDIO_INITI_M  ((RTC_CNTL_SDIO_INITI_V)<<(RTC_CNTL_SDIO_INITI_S))
+#define RTC_CNTL_SDIO_INITI_V  0x3
+#define RTC_CNTL_SDIO_INITI_S  13
+/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */
+/*description: ability to prevent LDO from overshoot*/
+#define RTC_CNTL_SDIO_DCAP  0x00000003
+#define RTC_CNTL_SDIO_DCAP_M  ((RTC_CNTL_SDIO_DCAP_V)<<(RTC_CNTL_SDIO_DCAP_S))
+#define RTC_CNTL_SDIO_DCAP_V  0x3
+#define RTC_CNTL_SDIO_DCAP_S  11
+/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */
+/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge
+ current  set to 3 after several us.*/
+#define RTC_CNTL_SDIO_DTHDRV  0x00000003
+#define RTC_CNTL_SDIO_DTHDRV_M  ((RTC_CNTL_SDIO_DTHDRV_V)<<(RTC_CNTL_SDIO_DTHDRV_S))
+#define RTC_CNTL_SDIO_DTHDRV_V  0x3
+#define RTC_CNTL_SDIO_DTHDRV_S  9
+/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */
+/*description: timer count to apply reg_sdio_dcap after sdio power on*/
+#define RTC_CNTL_SDIO_TIMER_TARGET  0x000000FF
+#define RTC_CNTL_SDIO_TIMER_TARGET_M  ((RTC_CNTL_SDIO_TIMER_TARGET_V)<<(RTC_CNTL_SDIO_TIMER_TARGET_S))
+#define RTC_CNTL_SDIO_TIMER_TARGET_V  0xFF
+#define RTC_CNTL_SDIO_TIMER_TARGET_S  0
+
+#define RTC_CNTL_BIAS_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0080)
+/* RTC_CNTL_RST_BIAS_I2C : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_RST_BIAS_I2C  (BIT(31))
+#define RTC_CNTL_RST_BIAS_I2C_M  (BIT(31))
+#define RTC_CNTL_RST_BIAS_I2C_V  0x1
+#define RTC_CNTL_RST_BIAS_I2C_S  31
+/* RTC_CNTL_DEC_HEARTBEAT_WIDTH : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: DEC_HEARTBEAT_WIDTH*/
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH  (BIT(30))
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_M  (BIT(30))
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_V  0x1
+#define RTC_CNTL_DEC_HEARTBEAT_WIDTH_S  30
+/* RTC_CNTL_INC_HEARTBEAT_PERIOD : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: INC_HEARTBEAT_PERIOD*/
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD  (BIT(29))
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD_M  (BIT(29))
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD_V  0x1
+#define RTC_CNTL_INC_HEARTBEAT_PERIOD_S  29
+/* RTC_CNTL_DEC_HEARTBEAT_PERIOD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: DEC_HEARTBEAT_PERIOD*/
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD  (BIT(28))
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_M  (BIT(28))
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_V  0x1
+#define RTC_CNTL_DEC_HEARTBEAT_PERIOD_S  28
+/* RTC_CNTL_INC_HEARTBEAT_REFRESH : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: INC_HEARTBEAT_REFRESH*/
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH  (BIT(27))
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH_M  (BIT(27))
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH_V  0x1
+#define RTC_CNTL_INC_HEARTBEAT_REFRESH_S  27
+/* RTC_CNTL_ENB_SCK_XTAL : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: ENB_SCK_XTAL*/
+#define RTC_CNTL_ENB_SCK_XTAL  (BIT(26))
+#define RTC_CNTL_ENB_SCK_XTAL_M  (BIT(26))
+#define RTC_CNTL_ENB_SCK_XTAL_V  0x1
+#define RTC_CNTL_ENB_SCK_XTAL_S  26
+/* RTC_CNTL_DBG_ATTEN : R/W ;bitpos:[25:22] ;default: 4'd0 ; */
+/*description: DBG_ATTEN*/
+#define RTC_CNTL_DBG_ATTEN  0x0000000F
+#define RTC_CNTL_DBG_ATTEN_M  ((RTC_CNTL_DBG_ATTEN_V)<<(RTC_CNTL_DBG_ATTEN_S))
+#define RTC_CNTL_DBG_ATTEN_V  0xF
+#define RTC_CNTL_DBG_ATTEN_S  22
+/* reserved for driver to check */
+#define RTC_CNTL_DBG_ATTEN_DEFAULT  3
+
+#define RTC_CNTL_REG          (DR_REG_RTCCNTL_BASE + 0x0084)
+/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_REGULATOR_FORCE_PU  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_M  (BIT(31))
+#define RTC_CNTL_REGULATOR_FORCE_PU_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PU_S  31
+/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: RTC_REG force power down (for RTC_REG power down means decrease
+ the voltage to 0.8v or lower )*/
+#define RTC_CNTL_REGULATOR_FORCE_PD  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_M  (BIT(30))
+#define RTC_CNTL_REGULATOR_FORCE_PD_V  0x1
+#define RTC_CNTL_REGULATOR_FORCE_PD_S  30
+/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: RTC_DBOOST force power up*/
+#define RTC_CNTL_DBOOST_FORCE_PU  (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_M  (BIT(29))
+#define RTC_CNTL_DBOOST_FORCE_PU_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PU_S  29
+/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RTC_DBOOST force power down*/
+#define RTC_CNTL_DBOOST_FORCE_PD  (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_M  (BIT(28))
+#define RTC_CNTL_DBOOST_FORCE_PD_V  0x1
+#define RTC_CNTL_DBOOST_FORCE_PD_S  28
+/* RTC_CNTL_DBIAS_WAK : R/W ;bitpos:[27:25] ;default: 3'd4 ; */
+/*description: RTC_DBIAS during wakeup*/
+#define RTC_CNTL_DBIAS_WAK  0x00000007
+#define RTC_CNTL_DBIAS_WAK_M  ((RTC_CNTL_DBIAS_WAK_V)<<(RTC_CNTL_DBIAS_WAK_S))
+#define RTC_CNTL_DBIAS_WAK_V  0x7
+#define RTC_CNTL_DBIAS_WAK_S  25
+/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
+ * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
+ * Valid if RTC_CNTL_DBG_ATTEN is 0.
+ */
+#define RTC_CNTL_DBIAS_0V90 0
+#define RTC_CNTL_DBIAS_0V95 1
+#define RTC_CNTL_DBIAS_1V00 2
+#define RTC_CNTL_DBIAS_1V05 3
+#define RTC_CNTL_DBIAS_1V10 4
+#define RTC_CNTL_DBIAS_1V15 5
+#define RTC_CNTL_DBIAS_1V20 6
+#define RTC_CNTL_DBIAS_1V25 7
+
+/* RTC_CNTL_DBIAS_SLP : R/W ;bitpos:[24:22] ;default: 3'd4 ; */
+/*description: RTC_DBIAS during sleep*/
+#define RTC_CNTL_DBIAS_SLP  0x00000007
+#define RTC_CNTL_DBIAS_SLP_M  ((RTC_CNTL_DBIAS_SLP_V)<<(RTC_CNTL_DBIAS_SLP_S))
+#define RTC_CNTL_DBIAS_SLP_V  0x7
+#define RTC_CNTL_DBIAS_SLP_S  22
+/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */
+/*description: SCK_DCAP*/
+#define RTC_CNTL_SCK_DCAP  0x000000FF
+#define RTC_CNTL_SCK_DCAP_M  ((RTC_CNTL_SCK_DCAP_V)<<(RTC_CNTL_SCK_DCAP_S))
+#define RTC_CNTL_SCK_DCAP_V  0xFF
+#define RTC_CNTL_SCK_DCAP_S  14
+#define RTC_CNTL_SCK_DCAP_DEFAULT   255
+/* RTC_CNTL_DIG_DBIAS_WAK : R/W ;bitpos:[13:11] ;default: 3'd4 ; */
+/*description: DIG_REG_DBIAS during wakeup*/
+#define RTC_CNTL_DIG_DBIAS_WAK  0x00000007
+#define RTC_CNTL_DIG_DBIAS_WAK_M  ((RTC_CNTL_DIG_DBIAS_WAK_V)<<(RTC_CNTL_DIG_DBIAS_WAK_S))
+#define RTC_CNTL_DIG_DBIAS_WAK_V  0x7
+#define RTC_CNTL_DIG_DBIAS_WAK_S  11
+/* RTC_CNTL_DIG_DBIAS_SLP : R/W ;bitpos:[10:8] ;default: 3'd4 ; */
+/*description: DIG_REG_DBIAS during sleep*/
+#define RTC_CNTL_DIG_DBIAS_SLP  0x00000007
+#define RTC_CNTL_DIG_DBIAS_SLP_M  ((RTC_CNTL_DIG_DBIAS_SLP_V)<<(RTC_CNTL_DIG_DBIAS_SLP_S))
+#define RTC_CNTL_DIG_DBIAS_SLP_V  0x7
+#define RTC_CNTL_DIG_DBIAS_SLP_S  8
+
+#define RTC_CNTL_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x0088)
+/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: rtc pad force hold*/
+#define RTC_CNTL_PAD_FORCE_HOLD  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_PAD_FORCE_HOLD_S  21
+/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: enable power down rtc_peri in sleep*/
+#define RTC_CNTL_PD_EN  (BIT(20))
+#define RTC_CNTL_PD_EN_M  (BIT(20))
+#define RTC_CNTL_PD_EN_V  0x1
+#define RTC_CNTL_PD_EN_S  20
+/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: rtc_peri force power up*/
+#define RTC_CNTL_PWC_FORCE_PU  (BIT(19))
+#define RTC_CNTL_PWC_FORCE_PU_M  (BIT(19))
+#define RTC_CNTL_PWC_FORCE_PU_V  0x1
+#define RTC_CNTL_PWC_FORCE_PU_S  19
+/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc_peri force power down*/
+#define RTC_CNTL_PWC_FORCE_PD  (BIT(18))
+#define RTC_CNTL_PWC_FORCE_PD_M  (BIT(18))
+#define RTC_CNTL_PWC_FORCE_PD_V  0x1
+#define RTC_CNTL_PWC_FORCE_PD_S  18
+/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: enable power down RTC memory in sleep*/
+#define RTC_CNTL_SLOWMEM_PD_EN  (BIT(17))
+#define RTC_CNTL_SLOWMEM_PD_EN_M  (BIT(17))
+#define RTC_CNTL_SLOWMEM_PD_EN_V  0x1
+#define RTC_CNTL_SLOWMEM_PD_EN_S  17
+/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: RTC memory force power up*/
+#define RTC_CNTL_SLOWMEM_FORCE_PU  (BIT(16))
+#define RTC_CNTL_SLOWMEM_FORCE_PU_M  (BIT(16))
+#define RTC_CNTL_SLOWMEM_FORCE_PU_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_PU_S  16
+/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: RTC memory force power down*/
+#define RTC_CNTL_SLOWMEM_FORCE_PD  (BIT(15))
+#define RTC_CNTL_SLOWMEM_FORCE_PD_M  (BIT(15))
+#define RTC_CNTL_SLOWMEM_FORCE_PD_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_PD_S  15
+/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable power down fast RTC memory in sleep*/
+#define RTC_CNTL_FASTMEM_PD_EN  (BIT(14))
+#define RTC_CNTL_FASTMEM_PD_EN_M  (BIT(14))
+#define RTC_CNTL_FASTMEM_PD_EN_V  0x1
+#define RTC_CNTL_FASTMEM_PD_EN_S  14
+/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: Fast RTC memory force power up*/
+#define RTC_CNTL_FASTMEM_FORCE_PU  (BIT(13))
+#define RTC_CNTL_FASTMEM_FORCE_PU_M  (BIT(13))
+#define RTC_CNTL_FASTMEM_FORCE_PU_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_PU_S  13
+/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: Fast RTC memory force power down*/
+#define RTC_CNTL_FASTMEM_FORCE_PD  (BIT(12))
+#define RTC_CNTL_FASTMEM_FORCE_PD_M  (BIT(12))
+#define RTC_CNTL_FASTMEM_FORCE_PD_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_PD_S  12
+/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: RTC memory force no PD*/
+#define RTC_CNTL_SLOWMEM_FORCE_LPU  (BIT(11))
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_M  (BIT(11))
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_LPU_S  11
+/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: RTC memory force PD*/
+#define RTC_CNTL_SLOWMEM_FORCE_LPD  (BIT(10))
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_M  (BIT(10))
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_LPD_S  10
+/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: RTC memory  PD following CPU  0: RTC memory PD following RTC state machine*/
+#define RTC_CNTL_SLOWMEM_FOLW_CPU  (BIT(9))
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_M  (BIT(9))
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_V  0x1
+#define RTC_CNTL_SLOWMEM_FOLW_CPU_S  9
+/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: Fast RTC memory force no PD*/
+#define RTC_CNTL_FASTMEM_FORCE_LPU  (BIT(8))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_M  (BIT(8))
+#define RTC_CNTL_FASTMEM_FORCE_LPU_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPU_S  8
+/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Fast RTC memory force PD*/
+#define RTC_CNTL_FASTMEM_FORCE_LPD  (BIT(7))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_M  (BIT(7))
+#define RTC_CNTL_FASTMEM_FORCE_LPD_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_LPD_S  7
+/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: 1: Fast RTC memory PD following CPU  0: fast RTC memory PD following
+ RTC state machine*/
+#define RTC_CNTL_FASTMEM_FOLW_CPU  (BIT(6))
+#define RTC_CNTL_FASTMEM_FOLW_CPU_M  (BIT(6))
+#define RTC_CNTL_FASTMEM_FOLW_CPU_V  0x1
+#define RTC_CNTL_FASTMEM_FOLW_CPU_S  6
+/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */
+/*description: rtc_peri force no ISO*/
+#define RTC_CNTL_FORCE_NOISO  (BIT(5))
+#define RTC_CNTL_FORCE_NOISO_M  (BIT(5))
+#define RTC_CNTL_FORCE_NOISO_V  0x1
+#define RTC_CNTL_FORCE_NOISO_S  5
+/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: rtc_peri force ISO*/
+#define RTC_CNTL_FORCE_ISO  (BIT(4))
+#define RTC_CNTL_FORCE_ISO_M  (BIT(4))
+#define RTC_CNTL_FORCE_ISO_V  0x1
+#define RTC_CNTL_FORCE_ISO_S  4
+/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: RTC memory force ISO*/
+#define RTC_CNTL_SLOWMEM_FORCE_ISO  (BIT(3))
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_M  (BIT(3))
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_ISO_S  3
+/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: RTC memory force no ISO*/
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO  (BIT(2))
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M  (BIT(2))
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V  0x1
+#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S  2
+/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: Fast RTC memory force ISO*/
+#define RTC_CNTL_FASTMEM_FORCE_ISO  (BIT(1))
+#define RTC_CNTL_FASTMEM_FORCE_ISO_M  (BIT(1))
+#define RTC_CNTL_FASTMEM_FORCE_ISO_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_ISO_S  1
+/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: Fast RTC memory force no ISO*/
+#define RTC_CNTL_FASTMEM_FORCE_NOISO  (BIT(0))
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_M  (BIT(0))
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_V  0x1
+#define RTC_CNTL_FASTMEM_FORCE_NOISO_S  0
+/* Useful groups of RTC_CNTL_PWC_REG bits */
+#define RTC_CNTL_MEM_FORCE_ISO    \
+    (RTC_CNTL_SLOWMEM_FORCE_ISO | RTC_CNTL_FASTMEM_FORCE_ISO)
+#define RTC_CNTL_MEM_FORCE_NOISO  \
+    (RTC_CNTL_SLOWMEM_FORCE_NOISO | RTC_CNTL_FASTMEM_FORCE_NOISO)
+#define RTC_CNTL_MEM_PD_EN        \
+    (RTC_CNTL_SLOWMEM_PD_EN | RTC_CNTL_FASTMEM_PD_EN)
+#define RTC_CNTL_MEM_FORCE_PU     \
+    (RTC_CNTL_SLOWMEM_FORCE_PU | RTC_CNTL_FASTMEM_FORCE_PU)
+#define RTC_CNTL_MEM_FORCE_PD     \
+    (RTC_CNTL_SLOWMEM_FORCE_PD | RTC_CNTL_FASTMEM_FORCE_PD)
+#define RTC_CNTL_MEM_FOLW_CPU     \
+    (RTC_CNTL_SLOWMEM_FOLW_CPU | RTC_CNTL_FASTMEM_FOLW_CPU)
+#define RTC_CNTL_MEM_FORCE_LPU    \
+    (RTC_CNTL_SLOWMEM_FORCE_LPU | RTC_CNTL_FASTMEM_FORCE_LPU)
+#define RTC_CNTL_MEM_FORCE_LPD    \
+    (RTC_CNTL_SLOWMEM_FORCE_LPD | RTC_CNTL_FASTMEM_FORCE_LPD)
+
+#define RTC_CNTL_DIG_PWC_REG          (DR_REG_RTCCNTL_BASE + 0x008c)
+/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_PD_EN  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_PD_EN_V  0x1
+#define RTC_CNTL_DG_WRAP_PD_EN_S  31
+/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */
+/*description: enable power down wifi in sleep*/
+#define RTC_CNTL_WIFI_PD_EN  (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_M  (BIT(30))
+#define RTC_CNTL_WIFI_PD_EN_V  0x1
+#define RTC_CNTL_WIFI_PD_EN_S  30
+/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */
+/*description: enable power down internal SRAM 4 in sleep*/
+#define RTC_CNTL_INTER_RAM4_PD_EN  (BIT(29))
+#define RTC_CNTL_INTER_RAM4_PD_EN_M  (BIT(29))
+#define RTC_CNTL_INTER_RAM4_PD_EN_V  0x1
+#define RTC_CNTL_INTER_RAM4_PD_EN_S  29
+/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */
+/*description: enable power down internal SRAM 3 in sleep*/
+#define RTC_CNTL_INTER_RAM3_PD_EN  (BIT(28))
+#define RTC_CNTL_INTER_RAM3_PD_EN_M  (BIT(28))
+#define RTC_CNTL_INTER_RAM3_PD_EN_V  0x1
+#define RTC_CNTL_INTER_RAM3_PD_EN_S  28
+/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */
+/*description: enable power down internal SRAM 2 in sleep*/
+#define RTC_CNTL_INTER_RAM2_PD_EN  (BIT(27))
+#define RTC_CNTL_INTER_RAM2_PD_EN_M  (BIT(27))
+#define RTC_CNTL_INTER_RAM2_PD_EN_V  0x1
+#define RTC_CNTL_INTER_RAM2_PD_EN_S  27
+/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */
+/*description: enable power down internal SRAM 1 in sleep*/
+#define RTC_CNTL_INTER_RAM1_PD_EN  (BIT(26))
+#define RTC_CNTL_INTER_RAM1_PD_EN_M  (BIT(26))
+#define RTC_CNTL_INTER_RAM1_PD_EN_V  0x1
+#define RTC_CNTL_INTER_RAM1_PD_EN_S  26
+/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */
+/*description: enable power down internal SRAM 0 in sleep*/
+#define RTC_CNTL_INTER_RAM0_PD_EN  (BIT(25))
+#define RTC_CNTL_INTER_RAM0_PD_EN_M  (BIT(25))
+#define RTC_CNTL_INTER_RAM0_PD_EN_V  0x1
+#define RTC_CNTL_INTER_RAM0_PD_EN_S  25
+/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */
+/*description: enable power down ROM in sleep*/
+#define RTC_CNTL_ROM0_PD_EN  (BIT(24))
+#define RTC_CNTL_ROM0_PD_EN_M  (BIT(24))
+#define RTC_CNTL_ROM0_PD_EN_V  0x1
+#define RTC_CNTL_ROM0_PD_EN_S  24
+/* RTC_CNTL_DG_DCDC_PD_EN : R/W ;bitpos:[23] ;default: 0 ; */
+/*description: enable power down digital dcdc in sleep*/
+#define RTC_CNTL_DG_DCDC_PD_EN  (BIT(23))
+#define RTC_CNTL_DG_DCDC_PD_EN_M  (BIT(23))
+#define RTC_CNTL_DG_DCDC_PD_EN_V  0x1
+#define RTC_CNTL_DG_DCDC_PD_EN_S  23
+/* RTC_CNTL_DG_DCDC_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */
+/*description: digital dcdc force power up*/
+#define RTC_CNTL_DG_DCDC_FORCE_PU  (BIT(22))
+#define RTC_CNTL_DG_DCDC_FORCE_PU_M  (BIT(22))
+#define RTC_CNTL_DG_DCDC_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_DCDC_FORCE_PU_S  22
+/* RTC_CNTL_DG_DCDC_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: digital dcdc force power down*/
+#define RTC_CNTL_DG_DCDC_FORCE_PD  (BIT(21))
+#define RTC_CNTL_DG_DCDC_FORCE_PD_M  (BIT(21))
+#define RTC_CNTL_DG_DCDC_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_DCDC_FORCE_PD_S  21
+/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */
+/*description: digital core force power up*/
+#define RTC_CNTL_DG_WRAP_FORCE_PU  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_M  (BIT(20))
+#define RTC_CNTL_DG_WRAP_FORCE_PU_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PU_S  20
+/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: digital core force power down*/
+#define RTC_CNTL_DG_WRAP_FORCE_PD  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_M  (BIT(19))
+#define RTC_CNTL_DG_WRAP_FORCE_PD_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_PD_S  19
+/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */
+/*description: wifi force power up*/
+#define RTC_CNTL_WIFI_FORCE_PU  (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_M  (BIT(18))
+#define RTC_CNTL_WIFI_FORCE_PU_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PU_S  18
+/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: wifi force power down*/
+#define RTC_CNTL_WIFI_FORCE_PD  (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_M  (BIT(17))
+#define RTC_CNTL_WIFI_FORCE_PD_V  0x1
+#define RTC_CNTL_WIFI_FORCE_PD_S  17
+/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: internal SRAM 4 force power up*/
+#define RTC_CNTL_INTER_RAM4_FORCE_PU  (BIT(16))
+#define RTC_CNTL_INTER_RAM4_FORCE_PU_M  (BIT(16))
+#define RTC_CNTL_INTER_RAM4_FORCE_PU_V  0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_PU_S  16
+/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: internal SRAM 4 force power down*/
+#define RTC_CNTL_INTER_RAM4_FORCE_PD  (BIT(15))
+#define RTC_CNTL_INTER_RAM4_FORCE_PD_M  (BIT(15))
+#define RTC_CNTL_INTER_RAM4_FORCE_PD_V  0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_PD_S  15
+/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: internal SRAM 3 force power up*/
+#define RTC_CNTL_INTER_RAM3_FORCE_PU  (BIT(14))
+#define RTC_CNTL_INTER_RAM3_FORCE_PU_M  (BIT(14))
+#define RTC_CNTL_INTER_RAM3_FORCE_PU_V  0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_PU_S  14
+/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: internal SRAM 3 force power down*/
+#define RTC_CNTL_INTER_RAM3_FORCE_PD  (BIT(13))
+#define RTC_CNTL_INTER_RAM3_FORCE_PD_M  (BIT(13))
+#define RTC_CNTL_INTER_RAM3_FORCE_PD_V  0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_PD_S  13
+/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: internal SRAM 2 force power up*/
+#define RTC_CNTL_INTER_RAM2_FORCE_PU  (BIT(12))
+#define RTC_CNTL_INTER_RAM2_FORCE_PU_M  (BIT(12))
+#define RTC_CNTL_INTER_RAM2_FORCE_PU_V  0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_PU_S  12
+/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: internal SRAM 2 force power down*/
+#define RTC_CNTL_INTER_RAM2_FORCE_PD  (BIT(11))
+#define RTC_CNTL_INTER_RAM2_FORCE_PD_M  (BIT(11))
+#define RTC_CNTL_INTER_RAM2_FORCE_PD_V  0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_PD_S  11
+/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */
+/*description: internal SRAM 1 force power up*/
+#define RTC_CNTL_INTER_RAM1_FORCE_PU  (BIT(10))
+#define RTC_CNTL_INTER_RAM1_FORCE_PU_M  (BIT(10))
+#define RTC_CNTL_INTER_RAM1_FORCE_PU_V  0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_PU_S  10
+/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: internal SRAM 1 force power down*/
+#define RTC_CNTL_INTER_RAM1_FORCE_PD  (BIT(9))
+#define RTC_CNTL_INTER_RAM1_FORCE_PD_M  (BIT(9))
+#define RTC_CNTL_INTER_RAM1_FORCE_PD_V  0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_PD_S  9
+/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */
+/*description: internal SRAM 0 force power up*/
+#define RTC_CNTL_INTER_RAM0_FORCE_PU  (BIT(8))
+#define RTC_CNTL_INTER_RAM0_FORCE_PU_M  (BIT(8))
+#define RTC_CNTL_INTER_RAM0_FORCE_PU_V  0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_PU_S  8
+/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: internal SRAM 0 force power down*/
+#define RTC_CNTL_INTER_RAM0_FORCE_PD  (BIT(7))
+#define RTC_CNTL_INTER_RAM0_FORCE_PD_M  (BIT(7))
+#define RTC_CNTL_INTER_RAM0_FORCE_PD_V  0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_PD_S  7
+/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */
+/*description: ROM force power up*/
+#define RTC_CNTL_ROM0_FORCE_PU  (BIT(6))
+#define RTC_CNTL_ROM0_FORCE_PU_M  (BIT(6))
+#define RTC_CNTL_ROM0_FORCE_PU_V  0x1
+#define RTC_CNTL_ROM0_FORCE_PU_S  6
+/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ROM force power down*/
+#define RTC_CNTL_ROM0_FORCE_PD  (BIT(5))
+#define RTC_CNTL_ROM0_FORCE_PD_M  (BIT(5))
+#define RTC_CNTL_ROM0_FORCE_PD_V  0x1
+#define RTC_CNTL_ROM0_FORCE_PD_S  5
+/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: memories in digital core force no PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PU  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_M  (BIT(4))
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PU_S  4
+/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: memories in digital core force PD in sleep*/
+#define RTC_CNTL_LSLP_MEM_FORCE_PD  (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_M  (BIT(3))
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_V  0x1
+#define RTC_CNTL_LSLP_MEM_FORCE_PD_S  3
+
+#define RTC_CNTL_DIG_ISO_REG          (DR_REG_RTCCNTL_BASE + 0x0090)
+/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */
+/*description: */
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M  (BIT(31))
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S  31
+/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: digital core force ISO*/
+#define RTC_CNTL_DG_WRAP_FORCE_ISO  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_M  (BIT(30))
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_WRAP_FORCE_ISO_S  30
+/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */
+/*description: wifi force no ISO*/
+#define RTC_CNTL_WIFI_FORCE_NOISO  (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_M  (BIT(29))
+#define RTC_CNTL_WIFI_FORCE_NOISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_NOISO_S  29
+/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: wifi force ISO*/
+#define RTC_CNTL_WIFI_FORCE_ISO  (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_M  (BIT(28))
+#define RTC_CNTL_WIFI_FORCE_ISO_V  0x1
+#define RTC_CNTL_WIFI_FORCE_ISO_S  28
+/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: internal SRAM 4 force no ISO*/
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO  (BIT(27))
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M  (BIT(27))
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V  0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S  27
+/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */
+/*description: internal SRAM 4 force ISO*/
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO  (BIT(26))
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M  (BIT(26))
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V  0x1
+#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S  26
+/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */
+/*description: internal SRAM 3 force no ISO*/
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO  (BIT(25))
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M  (BIT(25))
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V  0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S  25
+/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: internal SRAM 3 force ISO*/
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO  (BIT(24))
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M  (BIT(24))
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V  0x1
+#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S  24
+/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */
+/*description: internal SRAM 2 force no ISO*/
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO  (BIT(23))
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M  (BIT(23))
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V  0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S  23
+/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: internal SRAM 2 force ISO*/
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO  (BIT(22))
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M  (BIT(22))
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V  0x1
+#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S  22
+/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */
+/*description: internal SRAM 1 force no ISO*/
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO  (BIT(21))
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M  (BIT(21))
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V  0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S  21
+/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: internal SRAM 1 force ISO*/
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO  (BIT(20))
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M  (BIT(20))
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V  0x1
+#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S  20
+/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */
+/*description: internal SRAM 0 force no ISO*/
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO  (BIT(19))
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M  (BIT(19))
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V  0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S  19
+/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */
+/*description: internal SRAM 0 force ISO*/
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO  (BIT(18))
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M  (BIT(18))
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V  0x1
+#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S  18
+/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */
+/*description: ROM force no ISO*/
+#define RTC_CNTL_ROM0_FORCE_NOISO  (BIT(17))
+#define RTC_CNTL_ROM0_FORCE_NOISO_M  (BIT(17))
+#define RTC_CNTL_ROM0_FORCE_NOISO_V  0x1
+#define RTC_CNTL_ROM0_FORCE_NOISO_S  17
+/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: ROM force ISO*/
+#define RTC_CNTL_ROM0_FORCE_ISO  (BIT(16))
+#define RTC_CNTL_ROM0_FORCE_ISO_M  (BIT(16))
+#define RTC_CNTL_ROM0_FORCE_ISO_V  0x1
+#define RTC_CNTL_ROM0_FORCE_ISO_S  16
+/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: digital pad force hold*/
+#define RTC_CNTL_DG_PAD_FORCE_HOLD  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_M  (BIT(15))
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_HOLD_S  15
+/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */
+/*description: digital pad force un-hold*/
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M  (BIT(14))
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S  14
+/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: digital pad force ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_ISO  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_M  (BIT(13))
+#define RTC_CNTL_DG_PAD_FORCE_ISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_ISO_S  13
+/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: digital pad force no ISO*/
+#define RTC_CNTL_DG_PAD_FORCE_NOISO  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_M  (BIT(12))
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_V  0x1
+#define RTC_CNTL_DG_PAD_FORCE_NOISO_S  12
+/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: digital pad enable auto-hold*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M  (BIT(11))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S  11
+/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */
+/*description: wtite only register to clear digital pad auto-hold*/
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M  (BIT(10))
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S  10
+/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */
+/*description: read only register to indicate digital pad auto-hold status*/
+#define RTC_CNTL_DG_PAD_AUTOHOLD  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_M  (BIT(9))
+#define RTC_CNTL_DG_PAD_AUTOHOLD_V  0x1
+#define RTC_CNTL_DG_PAD_AUTOHOLD_S  9
+/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_ON  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_M  (BIT(8))
+#define RTC_CNTL_DIG_ISO_FORCE_ON_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_ON_S  8
+/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_DIG_ISO_FORCE_OFF  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_V  0x1
+#define RTC_CNTL_DIG_ISO_FORCE_OFF_S  7
+
+#define RTC_CNTL_WDTCONFIG0_REG          (DR_REG_RTCCNTL_BASE + 0x0094)
+/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define RTC_CNTL_WDT_EN  (BIT(31))
+#define RTC_CNTL_WDT_EN_M  (BIT(31))
+#define RTC_CNTL_WDT_EN_V  0x1
+#define RTC_CNTL_WDT_EN_S  31
+/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
+ stage en  4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG0  0x00000007
+#define RTC_CNTL_WDT_STG0_M  ((RTC_CNTL_WDT_STG0_V)<<(RTC_CNTL_WDT_STG0_S))
+#define RTC_CNTL_WDT_STG0_V  0x7
+#define RTC_CNTL_WDT_STG0_S  28
+/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
+ stage en  4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG1  0x00000007
+#define RTC_CNTL_WDT_STG1_M  ((RTC_CNTL_WDT_STG1_V)<<(RTC_CNTL_WDT_STG1_S))
+#define RTC_CNTL_WDT_STG1_V  0x7
+#define RTC_CNTL_WDT_STG1_S  25
+/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
+ stage en  4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG2  0x00000007
+#define RTC_CNTL_WDT_STG2_M  ((RTC_CNTL_WDT_STG2_V)<<(RTC_CNTL_WDT_STG2_S))
+#define RTC_CNTL_WDT_STG2_V  0x7
+#define RTC_CNTL_WDT_STG2_S  22
+/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */
+/*description: 1: interrupt stage en  2: CPU reset stage en  3: system reset
+ stage en  4: RTC reset stage en*/
+#define RTC_CNTL_WDT_STG3  0x00000007
+#define RTC_CNTL_WDT_STG3_M  ((RTC_CNTL_WDT_STG3_V)<<(RTC_CNTL_WDT_STG3_S))
+#define RTC_CNTL_WDT_STG3_V  0x7
+#define RTC_CNTL_WDT_STG3_S  19
+/* RTC_CNTL_WDT_STGX : */
+/*description: stage action selection values */
+#define RTC_WDT_STG_SEL_OFF             0
+#define RTC_WDT_STG_SEL_INT             1
+#define RTC_WDT_STG_SEL_RESET_CPU       2
+#define RTC_WDT_STG_SEL_RESET_SYSTEM    3
+#define RTC_WDT_STG_SEL_RESET_RTC       4
+
+/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */
+/*description: CPU reset counter length*/
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH  0x00000007
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M  ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V)<<(RTC_CNTL_WDT_CPU_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S  16
+/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */
+/*description: system reset counter length*/
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH  0x00000007
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M  ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V)<<(RTC_CNTL_WDT_SYS_RESET_LENGTH_S))
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V  0x7
+#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S  13
+/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: enable WDT in flash boot*/
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M  (BIT(12))
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S  12
+/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: enable WDT reset PRO CPU*/
+#define RTC_CNTL_WDT_PROCPU_RESET_EN  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_M  (BIT(11))
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_PROCPU_RESET_EN_S  11
+/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: enable WDT reset APP CPU*/
+#define RTC_CNTL_WDT_APPCPU_RESET_EN  (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_M  (BIT(10))
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_APPCPU_RESET_EN_S  10
+/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */
+/*description: pause WDT in sleep*/
+#define RTC_CNTL_WDT_PAUSE_IN_SLP  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_M  (BIT(9))
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_V  0x1
+#define RTC_CNTL_WDT_PAUSE_IN_SLP_S  9
+/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: wdt reset whole chip enable*/
+#define RTC_CNTL_WDT_CHIP_RESET_EN  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_M  (BIT(8))
+#define RTC_CNTL_WDT_CHIP_RESET_EN_V  0x1
+#define RTC_CNTL_WDT_CHIP_RESET_EN_S  8
+/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */
+/*description: chip reset siginal pulse width*/
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH  0x000000FF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M  ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V)<<(RTC_CNTL_WDT_CHIP_RESET_WIDTH_S))
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V  0xFF
+#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S  0
+
+#define RTC_CNTL_WDTCONFIG1_REG          (DR_REG_RTCCNTL_BASE + 0x0098)
+/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG0_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_M  ((RTC_CNTL_WDT_STG0_HOLD_V)<<(RTC_CNTL_WDT_STG0_HOLD_S))
+#define RTC_CNTL_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG0_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG2_REG          (DR_REG_RTCCNTL_BASE + 0x009c)
+/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */
+/*description: */
+#define RTC_CNTL_WDT_STG1_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_M  ((RTC_CNTL_WDT_STG1_HOLD_V)<<(RTC_CNTL_WDT_STG1_HOLD_S))
+#define RTC_CNTL_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG1_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG3_REG          (DR_REG_RTCCNTL_BASE + 0x00a0)
+/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG2_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_M  ((RTC_CNTL_WDT_STG2_HOLD_V)<<(RTC_CNTL_WDT_STG2_HOLD_S))
+#define RTC_CNTL_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG2_HOLD_S  0
+
+#define RTC_CNTL_WDTCONFIG4_REG          (DR_REG_RTCCNTL_BASE + 0x00a4)
+/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */
+/*description: */
+#define RTC_CNTL_WDT_STG3_HOLD  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_M  ((RTC_CNTL_WDT_STG3_HOLD_V)<<(RTC_CNTL_WDT_STG3_HOLD_S))
+#define RTC_CNTL_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_STG3_HOLD_S  0
+
+#define RTC_CNTL_WDTFEED_REG          (DR_REG_RTCCNTL_BASE + 0x00a8)
+/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_WDT_FEED  (BIT(31))
+#define RTC_CNTL_WDT_FEED_M  (BIT(31))
+#define RTC_CNTL_WDT_FEED_V  0x1
+#define RTC_CNTL_WDT_FEED_S  31
+
+#define RTC_CNTL_WDTWPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00ac)
+/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: */
+#define RTC_CNTL_WDT_WKEY  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_M  ((RTC_CNTL_WDT_WKEY_V)<<(RTC_CNTL_WDT_WKEY_S))
+#define RTC_CNTL_WDT_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_WDT_WKEY_S  0
+
+#define RTC_CNTL_SWD_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00b0)
+/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: automatically feed swd when int comes*/
+#define RTC_CNTL_SWD_AUTO_FEED_EN  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_M  (BIT(31))
+#define RTC_CNTL_SWD_AUTO_FEED_EN_V  0x1
+#define RTC_CNTL_SWD_AUTO_FEED_EN_S  31
+/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: disabel SWD*/
+#define RTC_CNTL_SWD_DISABLE  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_M  (BIT(30))
+#define RTC_CNTL_SWD_DISABLE_V  0x1
+#define RTC_CNTL_SWD_DISABLE_S  30
+/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Sw feed swd*/
+#define RTC_CNTL_SWD_FEED  (BIT(29))
+#define RTC_CNTL_SWD_FEED_M  (BIT(29))
+#define RTC_CNTL_SWD_FEED_V  0x1
+#define RTC_CNTL_SWD_FEED_S  29
+/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: reset swd reset flag*/
+#define RTC_CNTL_SWD_RST_FLAG_CLR  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_M  (BIT(28))
+#define RTC_CNTL_SWD_RST_FLAG_CLR_V  0x1
+#define RTC_CNTL_SWD_RST_FLAG_CLR_S  28
+/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */
+/*description: adjust signal width send to swd*/
+#define RTC_CNTL_SWD_SIGNAL_WIDTH  0x000003FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_M  ((RTC_CNTL_SWD_SIGNAL_WIDTH_V)<<(RTC_CNTL_SWD_SIGNAL_WIDTH_S))
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_V  0x3FF
+#define RTC_CNTL_SWD_SIGNAL_WIDTH_S  18
+/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: swd interrupt for feeding*/
+#define RTC_CNTL_SWD_FEED_INT  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_M  (BIT(1))
+#define RTC_CNTL_SWD_FEED_INT_V  0x1
+#define RTC_CNTL_SWD_FEED_INT_S  1
+/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: swd reset flag*/
+#define RTC_CNTL_SWD_RESET_FLAG  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_M  (BIT(0))
+#define RTC_CNTL_SWD_RESET_FLAG_V  0x1
+#define RTC_CNTL_SWD_RESET_FLAG_S  0
+
+#define RTC_CNTL_SWD_WPROTECT_REG          (DR_REG_RTCCNTL_BASE + 0x00b4)
+/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */
+/*description: swd write protect*/
+#define RTC_CNTL_SWD_WKEY  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_M  ((RTC_CNTL_SWD_WKEY_V)<<(RTC_CNTL_SWD_WKEY_S))
+#define RTC_CNTL_SWD_WKEY_V  0xFFFFFFFF
+#define RTC_CNTL_SWD_WKEY_S  0
+
+#define RTC_CNTL_TEST_MUX_REG          (DR_REG_RTCCNTL_BASE + 0x00b8)
+/* RTC_CNTL_DTEST_RTC : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: */
+#define RTC_CNTL_DTEST_RTC  0x00000003
+#define RTC_CNTL_DTEST_RTC_M  ((RTC_CNTL_DTEST_RTC_V)<<(RTC_CNTL_DTEST_RTC_S))
+#define RTC_CNTL_DTEST_RTC_V  0x3
+#define RTC_CNTL_DTEST_RTC_S  30
+/* RTC_CNTL_ENT_RTC : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: ENT_RTC*/
+#define RTC_CNTL_ENT_RTC  (BIT(29))
+#define RTC_CNTL_ENT_RTC_M  (BIT(29))
+#define RTC_CNTL_ENT_RTC_V  0x1
+#define RTC_CNTL_ENT_RTC_S  29
+/* RTC_CNTL_ENT_TSENS : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: ENT_TSENS*/
+#define RTC_CNTL_ENT_TSENS  (BIT(28))
+#define RTC_CNTL_ENT_TSENS_M  (BIT(28))
+#define RTC_CNTL_ENT_TSENS_V  0x1
+#define RTC_CNTL_ENT_TSENS_S  28
+
+#define RTC_CNTL_SW_CPU_STALL_REG          (DR_REG_RTCCNTL_BASE + 0x00bc)
+/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */
+/*description: */
+#define RTC_CNTL_SW_STALL_PROCPU_C1  0x0000003F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_M  ((RTC_CNTL_SW_STALL_PROCPU_C1_V)<<(RTC_CNTL_SW_STALL_PROCPU_C1_S))
+#define RTC_CNTL_SW_STALL_PROCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_PROCPU_C1_S  26
+/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */
+/*description: {reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} ==
+ 0x86 will stall APP CPU*/
+#define RTC_CNTL_SW_STALL_APPCPU_C1  0x0000003F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_M  ((RTC_CNTL_SW_STALL_APPCPU_C1_V)<<(RTC_CNTL_SW_STALL_APPCPU_C1_S))
+#define RTC_CNTL_SW_STALL_APPCPU_C1_V  0x3F
+#define RTC_CNTL_SW_STALL_APPCPU_C1_S  20
+
+#define RTC_CNTL_STORE4_REG          (DR_REG_RTCCNTL_BASE + 0x00c0)
+/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH4  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_M  ((RTC_CNTL_SCRATCH4_V)<<(RTC_CNTL_SCRATCH4_S))
+#define RTC_CNTL_SCRATCH4_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH4_S  0
+
+#define RTC_CNTL_STORE5_REG          (DR_REG_RTCCNTL_BASE + 0x00c4)
+/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH5  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_M  ((RTC_CNTL_SCRATCH5_V)<<(RTC_CNTL_SCRATCH5_S))
+#define RTC_CNTL_SCRATCH5_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH5_S  0
+
+#define RTC_CNTL_STORE6_REG          (DR_REG_RTCCNTL_BASE + 0x00c8)
+/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH6  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_M  ((RTC_CNTL_SCRATCH6_V)<<(RTC_CNTL_SCRATCH6_S))
+#define RTC_CNTL_SCRATCH6_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH6_S  0
+
+#define RTC_CNTL_STORE7_REG          (DR_REG_RTCCNTL_BASE + 0x00cc)
+/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_SCRATCH7  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_M  ((RTC_CNTL_SCRATCH7_V)<<(RTC_CNTL_SCRATCH7_S))
+#define RTC_CNTL_SCRATCH7_V  0xFFFFFFFF
+#define RTC_CNTL_SCRATCH7_S  0
+
+#define RTC_CNTL_LOW_POWER_ST_REG          (DR_REG_RTCCNTL_BASE + 0x00d0)
+/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */
+/*description: rtc main state machine status*/
+#define RTC_CNTL_MAIN_STATE  0x0000000F
+#define RTC_CNTL_MAIN_STATE_M  ((RTC_CNTL_MAIN_STATE_V)<<(RTC_CNTL_MAIN_STATE_S))
+#define RTC_CNTL_MAIN_STATE_V  0xF
+#define RTC_CNTL_MAIN_STATE_S  28
+/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: rtc main state machine is in idle state*/
+#define RTC_CNTL_MAIN_STATE_IN_IDLE  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_M  (BIT(27))
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_IDLE_S  27
+/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: rtc main state machine is in sleep state*/
+#define RTC_CNTL_MAIN_STATE_IN_SLP  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_M  (BIT(26))
+#define RTC_CNTL_MAIN_STATE_IN_SLP_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_SLP_S  26
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait xtal state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M  (BIT(25))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S  25
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait pll state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M  (BIT(24))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S  24
+/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: rtc main state machine is in wait 8m state*/
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M  (BIT(23))
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V  0x1
+#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S  23
+/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of low power*/
+#define RTC_CNTL_IN_LOW_POWER_STATE  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_M  (BIT(22))
+#define RTC_CNTL_IN_LOW_POWER_STATE_V  0x1
+#define RTC_CNTL_IN_LOW_POWER_STATE_S  22
+/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: rtc main state machine is in the states of wakeup process*/
+#define RTC_CNTL_IN_WAKEUP_STATE  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_M  (BIT(21))
+#define RTC_CNTL_IN_WAKEUP_STATE_V  0x1
+#define RTC_CNTL_IN_WAKEUP_STATE_S  21
+/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: rtc main state machine has been waited for some cycles*/
+#define RTC_CNTL_MAIN_STATE_WAIT_END  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_M  (BIT(20))
+#define RTC_CNTL_MAIN_STATE_WAIT_END_V  0x1
+#define RTC_CNTL_MAIN_STATE_WAIT_END_S  20
+/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: rtc is ready to receive wake up trigger from wake up source*/
+#define RTC_CNTL_RDY_FOR_WAKEUP  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_M  (BIT(19))
+#define RTC_CNTL_RDY_FOR_WAKEUP_V  0x1
+#define RTC_CNTL_RDY_FOR_WAKEUP_S  19
+/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: rtc main state machine is in states that pll should be running*/
+#define RTC_CNTL_MAIN_STATE_PLL_ON  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_M  (BIT(18))
+#define RTC_CNTL_MAIN_STATE_PLL_ON_V  0x1
+#define RTC_CNTL_MAIN_STATE_PLL_ON_S  18
+/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: no use any more*/
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M  (BIT(17))
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V  0x1
+#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S  17
+/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: ulp/cocpu is done*/
+#define RTC_CNTL_COCPU_STATE_DONE  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_M  (BIT(16))
+#define RTC_CNTL_COCPU_STATE_DONE_V  0x1
+#define RTC_CNTL_COCPU_STATE_DONE_S  16
+/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: ulp/cocpu is in sleep state*/
+#define RTC_CNTL_COCPU_STATE_SLP  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_M  (BIT(15))
+#define RTC_CNTL_COCPU_STATE_SLP_V  0x1
+#define RTC_CNTL_COCPU_STATE_SLP_S  15
+/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: ulp/cocpu is about to working. Switch rtc main state*/
+#define RTC_CNTL_COCPU_STATE_SWITCH  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_M  (BIT(14))
+#define RTC_CNTL_COCPU_STATE_SWITCH_V  0x1
+#define RTC_CNTL_COCPU_STATE_SWITCH_S  14
+/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: ulp/cocpu should start to work*/
+#define RTC_CNTL_COCPU_STATE_START  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_M  (BIT(13))
+#define RTC_CNTL_COCPU_STATE_START_V  0x1
+#define RTC_CNTL_COCPU_STATE_START_S  13
+/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: touch is done*/
+#define RTC_CNTL_TOUCH_STATE_DONE  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_M  (BIT(12))
+#define RTC_CNTL_TOUCH_STATE_DONE_V  0x1
+#define RTC_CNTL_TOUCH_STATE_DONE_S  12
+/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: touch is in sleep state*/
+#define RTC_CNTL_TOUCH_STATE_SLP  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_M  (BIT(11))
+#define RTC_CNTL_TOUCH_STATE_SLP_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SLP_S  11
+/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: touch is about to working. Switch rtc main state*/
+#define RTC_CNTL_TOUCH_STATE_SWITCH  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_M  (BIT(10))
+#define RTC_CNTL_TOUCH_STATE_SWITCH_V  0x1
+#define RTC_CNTL_TOUCH_STATE_SWITCH_S  10
+/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch should start to work*/
+#define RTC_CNTL_TOUCH_STATE_START  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_M  (BIT(9))
+#define RTC_CNTL_TOUCH_STATE_START_V  0x1
+#define RTC_CNTL_TOUCH_STATE_START_S  9
+/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: digital wrap power down*/
+#define RTC_CNTL_XPD_DIG  (BIT(8))
+#define RTC_CNTL_XPD_DIG_M  (BIT(8))
+#define RTC_CNTL_XPD_DIG_V  0x1
+#define RTC_CNTL_XPD_DIG_S  8
+/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: digital wrap iso*/
+#define RTC_CNTL_DIG_ISO  (BIT(7))
+#define RTC_CNTL_DIG_ISO_M  (BIT(7))
+#define RTC_CNTL_DIG_ISO_V  0x1
+#define RTC_CNTL_DIG_ISO_S  7
+/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: wifi wrap power down*/
+#define RTC_CNTL_XPD_WIFI  (BIT(6))
+#define RTC_CNTL_XPD_WIFI_M  (BIT(6))
+#define RTC_CNTL_XPD_WIFI_V  0x1
+#define RTC_CNTL_XPD_WIFI_S  6
+/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: wifi iso*/
+#define RTC_CNTL_WIFI_ISO  (BIT(5))
+#define RTC_CNTL_WIFI_ISO_M  (BIT(5))
+#define RTC_CNTL_WIFI_ISO_V  0x1
+#define RTC_CNTL_WIFI_ISO_S  5
+/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: rtc peripheral power down*/
+#define RTC_CNTL_XPD_RTC_PERI  (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_M  (BIT(4))
+#define RTC_CNTL_XPD_RTC_PERI_V  0x1
+#define RTC_CNTL_XPD_RTC_PERI_S  4
+/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: rtc peripheral iso*/
+#define RTC_CNTL_PERI_ISO  (BIT(3))
+#define RTC_CNTL_PERI_ISO_M  (BIT(3))
+#define RTC_CNTL_PERI_ISO_V  0x1
+#define RTC_CNTL_PERI_ISO_S  3
+/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: External DCDC power down*/
+#define RTC_CNTL_XPD_DIG_DCDC  (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_M  (BIT(2))
+#define RTC_CNTL_XPD_DIG_DCDC_V  0x1
+#define RTC_CNTL_XPD_DIG_DCDC_S  2
+/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: rom0 power down*/
+#define RTC_CNTL_XPD_ROM0  (BIT(0))
+#define RTC_CNTL_XPD_ROM0_M  (BIT(0))
+#define RTC_CNTL_XPD_ROM0_V  0x1
+#define RTC_CNTL_XPD_ROM0_S  0
+
+#define RTC_CNTL_DIAG0_REG          (DR_REG_RTCCNTL_BASE + 0x00d4)
+/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */
+/*description: */
+#define RTC_CNTL_LOW_POWER_DIAG1  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_M  ((RTC_CNTL_LOW_POWER_DIAG1_V)<<(RTC_CNTL_LOW_POWER_DIAG1_S))
+#define RTC_CNTL_LOW_POWER_DIAG1_V  0xFFFFFFFF
+#define RTC_CNTL_LOW_POWER_DIAG1_S  0
+
+#define RTC_CNTL_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00d8)
+/* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_PAD21_HOLD  (BIT(21))
+#define RTC_CNTL_PAD21_HOLD_M  (BIT(21))
+#define RTC_CNTL_PAD21_HOLD_V  0x1
+#define RTC_CNTL_PAD21_HOLD_S  21
+/* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_PAD20_HOLD  (BIT(20))
+#define RTC_CNTL_PAD20_HOLD_M  (BIT(20))
+#define RTC_CNTL_PAD20_HOLD_V  0x1
+#define RTC_CNTL_PAD20_HOLD_S  20
+/* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_PAD19_HOLD  (BIT(19))
+#define RTC_CNTL_PAD19_HOLD_M  (BIT(19))
+#define RTC_CNTL_PAD19_HOLD_V  0x1
+#define RTC_CNTL_PAD19_HOLD_S  19
+/* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_PDAC2_HOLD  (BIT(18))
+#define RTC_CNTL_PDAC2_HOLD_M  (BIT(18))
+#define RTC_CNTL_PDAC2_HOLD_V  0x1
+#define RTC_CNTL_PDAC2_HOLD_S  18
+/* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_PDAC1_HOLD  (BIT(17))
+#define RTC_CNTL_PDAC1_HOLD_M  (BIT(17))
+#define RTC_CNTL_PDAC1_HOLD_V  0x1
+#define RTC_CNTL_PDAC1_HOLD_S  17
+/* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_X32N_HOLD  (BIT(16))
+#define RTC_CNTL_X32N_HOLD_M  (BIT(16))
+#define RTC_CNTL_X32N_HOLD_V  0x1
+#define RTC_CNTL_X32N_HOLD_S  16
+/* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_X32P_HOLD  (BIT(15))
+#define RTC_CNTL_X32P_HOLD_M  (BIT(15))
+#define RTC_CNTL_X32P_HOLD_V  0x1
+#define RTC_CNTL_X32P_HOLD_S  15
+/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD14_HOLD  (BIT(14))
+#define RTC_CNTL_TOUCH_PAD14_HOLD_M  (BIT(14))
+#define RTC_CNTL_TOUCH_PAD14_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD14_HOLD_S  14
+/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD13_HOLD  (BIT(13))
+#define RTC_CNTL_TOUCH_PAD13_HOLD_M  (BIT(13))
+#define RTC_CNTL_TOUCH_PAD13_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD13_HOLD_S  13
+/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD12_HOLD  (BIT(12))
+#define RTC_CNTL_TOUCH_PAD12_HOLD_M  (BIT(12))
+#define RTC_CNTL_TOUCH_PAD12_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD12_HOLD_S  12
+/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD11_HOLD  (BIT(11))
+#define RTC_CNTL_TOUCH_PAD11_HOLD_M  (BIT(11))
+#define RTC_CNTL_TOUCH_PAD11_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD11_HOLD_S  11
+/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD10_HOLD  (BIT(10))
+#define RTC_CNTL_TOUCH_PAD10_HOLD_M  (BIT(10))
+#define RTC_CNTL_TOUCH_PAD10_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD10_HOLD_S  10
+/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD9_HOLD  (BIT(9))
+#define RTC_CNTL_TOUCH_PAD9_HOLD_M  (BIT(9))
+#define RTC_CNTL_TOUCH_PAD9_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD9_HOLD_S  9
+/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD8_HOLD  (BIT(8))
+#define RTC_CNTL_TOUCH_PAD8_HOLD_M  (BIT(8))
+#define RTC_CNTL_TOUCH_PAD8_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD8_HOLD_S  8
+/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD7_HOLD  (BIT(7))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_M  (BIT(7))
+#define RTC_CNTL_TOUCH_PAD7_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD7_HOLD_S  7
+/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD6_HOLD  (BIT(6))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_M  (BIT(6))
+#define RTC_CNTL_TOUCH_PAD6_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD6_HOLD_S  6
+/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD5_HOLD  (BIT(5))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_M  (BIT(5))
+#define RTC_CNTL_TOUCH_PAD5_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD5_HOLD_S  5
+/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD4_HOLD  (BIT(4))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_M  (BIT(4))
+#define RTC_CNTL_TOUCH_PAD4_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD4_HOLD_S  4
+/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD3_HOLD  (BIT(3))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_M  (BIT(3))
+#define RTC_CNTL_TOUCH_PAD3_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD3_HOLD_S  3
+/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD2_HOLD  (BIT(2))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_M  (BIT(2))
+#define RTC_CNTL_TOUCH_PAD2_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD2_HOLD_S  2
+/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD1_HOLD  (BIT(1))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_M  (BIT(1))
+#define RTC_CNTL_TOUCH_PAD1_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD1_HOLD_S  1
+/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_PAD0_HOLD  (BIT(0))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_M  (BIT(0))
+#define RTC_CNTL_TOUCH_PAD0_HOLD_V  0x1
+#define RTC_CNTL_TOUCH_PAD0_HOLD_S  0
+
+#define RTC_CNTL_DIG_PAD_HOLD_REG          (DR_REG_RTCCNTL_BASE + 0x00dc)
+/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define RTC_CNTL_DIG_PAD_HOLD  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_M  ((RTC_CNTL_DIG_PAD_HOLD_V)<<(RTC_CNTL_DIG_PAD_HOLD_S))
+#define RTC_CNTL_DIG_PAD_HOLD_V  0xFFFFFFFF
+#define RTC_CNTL_DIG_PAD_HOLD_S  0
+
+#define RTC_CNTL_EXT_WAKEUP1_REG          (DR_REG_RTCCNTL_BASE + 0x00e0)
+/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: clear ext wakeup1 status*/
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR  (BIT(22))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M  (BIT(22))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V  0x1
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S  22
+/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */
+/*description: Bitmap to select RTC pads for ext wakeup1*/
+#define RTC_CNTL_EXT_WAKEUP1_SEL  0x003FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_SEL_M  ((RTC_CNTL_EXT_WAKEUP1_SEL_V)<<(RTC_CNTL_EXT_WAKEUP1_SEL_S))
+#define RTC_CNTL_EXT_WAKEUP1_SEL_V  0x3FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_SEL_S  0
+
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG          (DR_REG_RTCCNTL_BASE + 0x00e4)
+/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */
+/*description: ext wakeup1 status*/
+#define RTC_CNTL_EXT_WAKEUP1_STATUS  0x003FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_M  ((RTC_CNTL_EXT_WAKEUP1_STATUS_V)<<(RTC_CNTL_EXT_WAKEUP1_STATUS_S))
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_V  0x3FFFFF
+#define RTC_CNTL_EXT_WAKEUP1_STATUS_S  0
+
+#define RTC_CNTL_BROWN_OUT_REG          (DR_REG_RTCCNTL_BASE + 0x00e8)
+/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define RTC_CNTL_BROWN_OUT_DET  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_M  (BIT(31))
+#define RTC_CNTL_BROWN_OUT_DET_V  0x1
+#define RTC_CNTL_BROWN_OUT_DET_S  31
+/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: enable brown out*/
+#define RTC_CNTL_BROWN_OUT_ENA  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_M  (BIT(30))
+#define RTC_CNTL_BROWN_OUT_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_ENA_S  30
+/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: clear brown out counter*/
+#define RTC_CNTL_BROWN_OUT_CNT_CLR  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_M  (BIT(29))
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_V  0x1
+#define RTC_CNTL_BROWN_OUT_CNT_CLR_S  29
+/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: enable brown out reset*/
+#define RTC_CNTL_BROWN_OUT_RST_ENA  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_M  (BIT(26))
+#define RTC_CNTL_BROWN_OUT_RST_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_RST_ENA_S  26
+/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */
+/*description: brown out reset wait cycles*/
+#define RTC_CNTL_BROWN_OUT_RST_WAIT  0x000003FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_M  ((RTC_CNTL_BROWN_OUT_RST_WAIT_V)<<(RTC_CNTL_BROWN_OUT_RST_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_RST_WAIT_S  16
+/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: enable power down RF when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M  (BIT(15))
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S  15
+/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: enable close flash when brown out happens*/
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M  (BIT(14))
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V  0x1
+#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S  14
+/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h2ff ; */
+/*description: brown out interrupt wait cycles*/
+#define RTC_CNTL_BROWN_OUT_INT_WAIT  0x000003FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_M  ((RTC_CNTL_BROWN_OUT_INT_WAIT_V)<<(RTC_CNTL_BROWN_OUT_INT_WAIT_S))
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_V  0x3FF
+#define RTC_CNTL_BROWN_OUT_INT_WAIT_S  4
+
+#define RTC_CNTL_TIME_LOW1_REG          (DR_REG_RTCCNTL_BASE + 0x00ec)
+/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: RTC timer low 32 bits*/
+#define RTC_CNTL_TIMER_VALUE1_LOW  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_M  ((RTC_CNTL_TIMER_VALUE1_LOW_V)<<(RTC_CNTL_TIMER_VALUE1_LOW_S))
+#define RTC_CNTL_TIMER_VALUE1_LOW_V  0xFFFFFFFF
+#define RTC_CNTL_TIMER_VALUE1_LOW_S  0
+
+#define RTC_CNTL_TIME_HIGH1_REG          (DR_REG_RTCCNTL_BASE + 0x00f0)
+/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: RTC timer high 16 bits*/
+#define RTC_CNTL_TIMER_VALUE1_HIGH  0x0000FFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_M  ((RTC_CNTL_TIMER_VALUE1_HIGH_V)<<(RTC_CNTL_TIMER_VALUE1_HIGH_S))
+#define RTC_CNTL_TIMER_VALUE1_HIGH_V  0xFFFF
+#define RTC_CNTL_TIMER_VALUE1_HIGH_S  0
+
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG          (DR_REG_RTCCNTL_BASE + 0x00f4)
+/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: xtal 32k watch dog backup clock factor*/
+#define RTC_CNTL_XTAL32K_CLK_FACTOR  0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_M  ((RTC_CNTL_XTAL32K_CLK_FACTOR_V)<<(RTC_CNTL_XTAL32K_CLK_FACTOR_S))
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_V  0xFFFFFFFF
+#define RTC_CNTL_XTAL32K_CLK_FACTOR_S  0
+
+#define RTC_CNTL_XTAL32K_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x00f8)
+/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: if restarted xtal32k period is smaller than this  it is regarded as stable*/
+#define RTC_CNTL_XTAL32K_STABLE_THRES  0x0000000F
+#define RTC_CNTL_XTAL32K_STABLE_THRES_M  ((RTC_CNTL_XTAL32K_STABLE_THRES_V)<<(RTC_CNTL_XTAL32K_STABLE_THRES_S))
+#define RTC_CNTL_XTAL32K_STABLE_THRES_V  0xF
+#define RTC_CNTL_XTAL32K_STABLE_THRES_S  28
+/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */
+/*description: If no clock detected for this amount of time  32k is regarded as dead*/
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT  0x000000FF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M  ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V)<<(RTC_CNTL_XTAL32K_WDT_TIMEOUT_S))
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V  0xFF
+#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S  20
+/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */
+/*description: cycles to wait to repower on xtal 32k*/
+#define RTC_CNTL_XTAL32K_RESTART_WAIT  0x0000FFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_M  ((RTC_CNTL_XTAL32K_RESTART_WAIT_V)<<(RTC_CNTL_XTAL32K_RESTART_WAIT_S))
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_V  0xFFFF
+#define RTC_CNTL_XTAL32K_RESTART_WAIT_S  4
+/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: cycles to wait to return noral xtal 32k*/
+#define RTC_CNTL_XTAL32K_RETURN_WAIT  0x0000000F
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_M  ((RTC_CNTL_XTAL32K_RETURN_WAIT_V)<<(RTC_CNTL_XTAL32K_RETURN_WAIT_S))
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_V  0xF
+#define RTC_CNTL_XTAL32K_RETURN_WAIT_S  0
+
+#define RTC_CNTL_ULP_CP_TIMER_REG          (DR_REG_RTCCNTL_BASE + 0x00fc)
+/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: ULP-coprocessor timer enable bit*/
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN  (BIT(31))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M  (BIT(31))
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V  0x1
+#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S  31
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */
+/*description: ULP-coprocessor wakeup by GPIO state clear*/
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR  (BIT(30))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M  (BIT(30))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V  0x1
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S  30
+/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: ULP-coprocessor wakeup by GPIO enable*/
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA  (BIT(29))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M  (BIT(29))
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V  0x1
+#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S  29
+/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[27:12] ;default: 16'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer*/
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE  0x0000FFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M  ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V)<<(RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S))
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V  0xFFFF
+#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S  12
+/* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
+/*description: ULP-coprocessor PC initial address*/
+#define RTC_CNTL_ULP_CP_PC_INIT  0x000007FF
+#define RTC_CNTL_ULP_CP_PC_INIT_M  ((RTC_CNTL_ULP_CP_PC_INIT_V)<<(RTC_CNTL_ULP_CP_PC_INIT_S))
+#define RTC_CNTL_ULP_CP_PC_INIT_V  0x7FF
+#define RTC_CNTL_ULP_CP_PC_INIT_S  0
+
+#define RTC_CNTL_ULP_CP_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0100)
+/* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */
+/*description: Write 1 to start ULP-coprocessor*/
+#define RTC_CNTL_ULP_CP_START_TOP  (BIT(31))
+#define RTC_CNTL_ULP_CP_START_TOP_M  (BIT(31))
+#define RTC_CNTL_ULP_CP_START_TOP_V  0x1
+#define RTC_CNTL_ULP_CP_START_TOP_S  31
+/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */
+/*description: 1: ULP-coprocessor is started by SW*/
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP  (BIT(30))
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M  (BIT(30))
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V  0x1
+#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S  30
+/* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */
+/*description: ulp coprocessor clk software reset*/
+#define RTC_CNTL_ULP_CP_RESET  (BIT(29))
+#define RTC_CNTL_ULP_CP_RESET_M  (BIT(29))
+#define RTC_CNTL_ULP_CP_RESET_V  0x1
+#define RTC_CNTL_ULP_CP_RESET_S  29
+/* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: ulp coprocessor clk force on*/
+#define RTC_CNTL_ULP_CP_CLK_FO  (BIT(28))
+#define RTC_CNTL_ULP_CP_CLK_FO_M  (BIT(28))
+#define RTC_CNTL_ULP_CP_CLK_FO_V  0x1
+#define RTC_CNTL_ULP_CP_CLK_FO_S  28
+/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR  (BIT(22))
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M  (BIT(22))
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V  0x1
+#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S  22
+/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */
+/*description: */
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE  0x000007FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M  ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S))
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V  0x7FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S  11
+/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */
+/*description: */
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT  0x000007FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M  ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V)<<(RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S))
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V  0x7FF
+#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S  0
+
+#define RTC_CNTL_COCPU_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0104)
+/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: trigger cocpu register interrupt*/
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER  (BIT(24))
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M  (BIT(24))
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V  0x1
+#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S  24
+/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: done signal used by riscv to control timer.*/
+#define RTC_CNTL_COCPU_DONE  (BIT(23))
+#define RTC_CNTL_COCPU_DONE_M  (BIT(23))
+#define RTC_CNTL_COCPU_DONE_V  0x1
+#define RTC_CNTL_COCPU_DONE_S  23
+/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: select riscv done 0: select ulp done*/
+#define RTC_CNTL_COCPU_DONE_FORCE  (BIT(22))
+#define RTC_CNTL_COCPU_DONE_FORCE_M  (BIT(22))
+#define RTC_CNTL_COCPU_DONE_FORCE_V  0x1
+#define RTC_CNTL_COCPU_DONE_FORCE_S  22
+/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: 1: old ULP 0: new riscV*/
+#define RTC_CNTL_COCPU_SEL  (BIT(21))
+#define RTC_CNTL_COCPU_SEL_M  (BIT(21))
+#define RTC_CNTL_COCPU_SEL_V  0x1
+#define RTC_CNTL_COCPU_SEL_S  21
+/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: to reset cocpu*/
+#define RTC_CNTL_COCPU_SHUT_RESET_EN  (BIT(20))
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_M  (BIT(20))
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_V  0x1
+#define RTC_CNTL_COCPU_SHUT_RESET_EN_S  20
+/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[19:14] ;default: 6'd24 ; */
+/*description: time from shut cocpu to disable clk*/
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS  0x0000003F
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M  ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V)<<(RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S))
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V  0x3F
+#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S  14
+/* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: to shut cocpu*/
+#define RTC_CNTL_COCPU_SHUT  (BIT(13))
+#define RTC_CNTL_COCPU_SHUT_M  (BIT(13))
+#define RTC_CNTL_COCPU_SHUT_V  0x1
+#define RTC_CNTL_COCPU_SHUT_S  13
+/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */
+/*description: time from start cocpu to give start interrupt*/
+#define RTC_CNTL_COCPU_START_2_INTR_EN  0x0000003F
+#define RTC_CNTL_COCPU_START_2_INTR_EN_M  ((RTC_CNTL_COCPU_START_2_INTR_EN_V)<<(RTC_CNTL_COCPU_START_2_INTR_EN_S))
+#define RTC_CNTL_COCPU_START_2_INTR_EN_V  0x3F
+#define RTC_CNTL_COCPU_START_2_INTR_EN_S  7
+/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */
+/*description: time from start cocpu to pull down reset*/
+#define RTC_CNTL_COCPU_START_2_RESET_DIS  0x0000003F
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_M  ((RTC_CNTL_COCPU_START_2_RESET_DIS_V)<<(RTC_CNTL_COCPU_START_2_RESET_DIS_S))
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_V  0x3F
+#define RTC_CNTL_COCPU_START_2_RESET_DIS_S  1
+/* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: cocpu clk force on*/
+#define RTC_CNTL_COCPU_CLK_FO  (BIT(0))
+#define RTC_CNTL_COCPU_CLK_FO_M  (BIT(0))
+#define RTC_CNTL_COCPU_CLK_FO_V  0x1
+#define RTC_CNTL_COCPU_CLK_FO_S  0
+
+#define RTC_CNTL_TOUCH_CTRL1_REG          (DR_REG_RTCCNTL_BASE + 0x0108)
+/* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */
+/*description: the meas length (in 8MHz)*/
+#define RTC_CNTL_TOUCH_MEAS_NUM  0x0000FFFF
+#define RTC_CNTL_TOUCH_MEAS_NUM_M  ((RTC_CNTL_TOUCH_MEAS_NUM_V)<<(RTC_CNTL_TOUCH_MEAS_NUM_S))
+#define RTC_CNTL_TOUCH_MEAS_NUM_V  0xFFFF
+#define RTC_CNTL_TOUCH_MEAS_NUM_S  16
+/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */
+/*description: sleep cycles for timer*/
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES  0x0000FFFF
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M  ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V)<<(RTC_CNTL_TOUCH_SLEEP_CYCLES_S))
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V  0xFFFF
+#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S  0
+
+#define RTC_CNTL_TOUCH_CTRL2_REG          (DR_REG_RTCCNTL_BASE + 0x010c)
+/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: touch clock enable*/
+#define RTC_CNTL_TOUCH_CLKGATE_EN  (BIT(31))
+#define RTC_CNTL_TOUCH_CLKGATE_EN_M  (BIT(31))
+#define RTC_CNTL_TOUCH_CLKGATE_EN_V  0x1
+#define RTC_CNTL_TOUCH_CLKGATE_EN_S  31
+/* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: touch clock force on*/
+#define RTC_CNTL_TOUCH_CLK_FO  (BIT(30))
+#define RTC_CNTL_TOUCH_CLK_FO_M  (BIT(30))
+#define RTC_CNTL_TOUCH_CLK_FO_V  0x1
+#define RTC_CNTL_TOUCH_CLK_FO_S  30
+/* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: reset upgrade touch*/
+#define RTC_CNTL_TOUCH_RESET  (BIT(29))
+#define RTC_CNTL_TOUCH_RESET_M  (BIT(29))
+#define RTC_CNTL_TOUCH_RESET_V  0x1
+#define RTC_CNTL_TOUCH_RESET_S  29
+/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */
+/*description: when a touch pad is active  sleep cycle could be divided by this number*/
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV  0x00000003
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M  ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V)<<(RTC_CNTL_TOUCH_SLP_CYC_DIV_S))
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V  0x3
+#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S  25
+/* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */
+/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
+#define RTC_CNTL_TOUCH_XPD_WAIT  0x000000FF
+#define RTC_CNTL_TOUCH_XPD_WAIT_M  ((RTC_CNTL_TOUCH_XPD_WAIT_V)<<(RTC_CNTL_TOUCH_XPD_WAIT_S))
+#define RTC_CNTL_TOUCH_XPD_WAIT_V  0xFF
+#define RTC_CNTL_TOUCH_XPD_WAIT_S  17
+/* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: to start touch fsm by SW*/
+#define RTC_CNTL_TOUCH_START_FORCE  (BIT(16))
+#define RTC_CNTL_TOUCH_START_FORCE_M  (BIT(16))
+#define RTC_CNTL_TOUCH_START_FORCE_V  0x1
+#define RTC_CNTL_TOUCH_START_FORCE_S  16
+/* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: 1: start touch fsm*/
+#define RTC_CNTL_TOUCH_START_EN  (BIT(15))
+#define RTC_CNTL_TOUCH_START_EN_M  (BIT(15))
+#define RTC_CNTL_TOUCH_START_EN_V  0x1
+#define RTC_CNTL_TOUCH_START_EN_S  15
+/* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/
+#define RTC_CNTL_TOUCH_START_FSM_EN  (BIT(14))
+#define RTC_CNTL_TOUCH_START_FSM_EN_M  (BIT(14))
+#define RTC_CNTL_TOUCH_START_FSM_EN_V  0x1
+#define RTC_CNTL_TOUCH_START_FSM_EN_S  14
+/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: touch timer enable bit*/
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN  (BIT(13))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M  (BIT(13))
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V  0x1
+#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S  13
+/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h4 ; */
+/*description: TOUCH pad0 reference cap*/
+#define RTC_CNTL_TOUCH_REFC  0x00000007
+#define RTC_CNTL_TOUCH_REFC_M  ((RTC_CNTL_TOUCH_REFC_V)<<(RTC_CNTL_TOUCH_REFC_S))
+#define RTC_CNTL_TOUCH_REFC_V  0x7
+#define RTC_CNTL_TOUCH_REFC_S  9
+/* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: TOUCH_XPD_BIAS*/
+#define RTC_CNTL_TOUCH_XPD_BIAS  (BIT(8))
+#define RTC_CNTL_TOUCH_XPD_BIAS_M  (BIT(8))
+#define RTC_CNTL_TOUCH_XPD_BIAS_V  0x1
+#define RTC_CNTL_TOUCH_XPD_BIAS_S  8
+/* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */
+/*description: TOUCH_DREFH*/
+#define RTC_CNTL_TOUCH_DREFH  0x00000003
+#define RTC_CNTL_TOUCH_DREFH_M  ((RTC_CNTL_TOUCH_DREFH_V)<<(RTC_CNTL_TOUCH_DREFH_S))
+#define RTC_CNTL_TOUCH_DREFH_V  0x3
+#define RTC_CNTL_TOUCH_DREFH_S  6
+/* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */
+/*description: TOUCH_DREFL*/
+#define RTC_CNTL_TOUCH_DREFL  0x00000003
+#define RTC_CNTL_TOUCH_DREFL_M  ((RTC_CNTL_TOUCH_DREFL_V)<<(RTC_CNTL_TOUCH_DREFL_S))
+#define RTC_CNTL_TOUCH_DREFL_V  0x3
+#define RTC_CNTL_TOUCH_DREFL_S  4
+/* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: TOUCH_DRANGE*/
+#define RTC_CNTL_TOUCH_DRANGE  0x00000003
+#define RTC_CNTL_TOUCH_DRANGE_M  ((RTC_CNTL_TOUCH_DRANGE_V)<<(RTC_CNTL_TOUCH_DRANGE_S))
+#define RTC_CNTL_TOUCH_DRANGE_V  0x3
+#define RTC_CNTL_TOUCH_DRANGE_S  2
+
+#define RTC_CNTL_TOUCH_SCAN_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x0110)
+/* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */
+/*description: select out ring pad*/
+#define RTC_CNTL_TOUCH_OUT_RING  0x0000000F
+#define RTC_CNTL_TOUCH_OUT_RING_M  ((RTC_CNTL_TOUCH_OUT_RING_V)<<(RTC_CNTL_TOUCH_OUT_RING_S))
+#define RTC_CNTL_TOUCH_OUT_RING_V  0xF
+#define RTC_CNTL_TOUCH_OUT_RING_S  28
+/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h4 ; */
+/*description: touch7 buffer driver strength*/
+#define RTC_CNTL_TOUCH_BUFDRV  0x00000007
+#define RTC_CNTL_TOUCH_BUFDRV_M  ((RTC_CNTL_TOUCH_BUFDRV_V)<<(RTC_CNTL_TOUCH_BUFDRV_S))
+#define RTC_CNTL_TOUCH_BUFDRV_V  0x7
+#define RTC_CNTL_TOUCH_BUFDRV_S  25
+/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */
+/*description: touch scan mode pad enable map*/
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP  0x00007FFF
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M  ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V)<<(RTC_CNTL_TOUCH_SCAN_PAD_MAP_S))
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V  0x7FFF
+#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S  10
+/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: touch pad14 will be used as shield*/
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN  (BIT(9))
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M  (BIT(9))
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V  0x1
+#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S  9
+/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: inactive touch pads connect to 1: gnd 0: HighZ*/
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M  (BIT(8))
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V  0x1
+#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S  8
+/* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: touch pad0 will be used to de-noise*/
+#define RTC_CNTL_TOUCH_DENOISE_EN  (BIT(2))
+#define RTC_CNTL_TOUCH_DENOISE_EN_M  (BIT(2))
+#define RTC_CNTL_TOUCH_DENOISE_EN_V  0x1
+#define RTC_CNTL_TOUCH_DENOISE_EN_S  2
+/* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */
+/*description: De-noise resolution: 12/10/8/4 bit*/
+#define RTC_CNTL_TOUCH_DENOISE_RES  0x00000003
+#define RTC_CNTL_TOUCH_DENOISE_RES_M  ((RTC_CNTL_TOUCH_DENOISE_RES_V)<<(RTC_CNTL_TOUCH_DENOISE_RES_S))
+#define RTC_CNTL_TOUCH_DENOISE_RES_V  0x3
+#define RTC_CNTL_TOUCH_DENOISE_RES_S  0
+
+#define RTC_CNTL_TOUCH_SLP_THRES_REG          (DR_REG_RTCCNTL_BASE + 0x0114)
+/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */
+/*description: */
+#define RTC_CNTL_TOUCH_SLP_PAD  0x0000001F
+#define RTC_CNTL_TOUCH_SLP_PAD_M  ((RTC_CNTL_TOUCH_SLP_PAD_V)<<(RTC_CNTL_TOUCH_SLP_PAD_S))
+#define RTC_CNTL_TOUCH_SLP_PAD_V  0x1F
+#define RTC_CNTL_TOUCH_SLP_PAD_S  27
+/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: sleep pad approach function enable*/
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN  (BIT(26))
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M  (BIT(26))
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V  0x1
+#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S  26
+/* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */
+/*description: the threshold for sleep touch pad*/
+#define RTC_CNTL_TOUCH_SLP_TH  0x003FFFFF
+#define RTC_CNTL_TOUCH_SLP_TH_M  ((RTC_CNTL_TOUCH_SLP_TH_V)<<(RTC_CNTL_TOUCH_SLP_TH_S))
+#define RTC_CNTL_TOUCH_SLP_TH_V  0x3FFFFF
+#define RTC_CNTL_TOUCH_SLP_TH_S  0
+
+#define RTC_CNTL_TOUCH_APPROACH_REG          (DR_REG_RTCCNTL_BASE + 0x0118)
+/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */
+/*description: approach pads total meas times*/
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME  0x000000FF
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M  ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V)<<(RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S))
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V  0xFF
+#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S  24
+/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear touch slp channel*/
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR  (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M  (BIT(23))
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V  0x1
+#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S  23
+
+#define RTC_CNTL_TOUCH_FILTER_CTRL_REG          (DR_REG_RTCCNTL_BASE + 0x011c)
+/* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: touch filter enable*/
+#define RTC_CNTL_TOUCH_FILTER_EN  (BIT(31))
+#define RTC_CNTL_TOUCH_FILTER_EN_M  (BIT(31))
+#define RTC_CNTL_TOUCH_FILTER_EN_V  0x1
+#define RTC_CNTL_TOUCH_FILTER_EN_S  31
+/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:29] ;default: 2'd1 ; */
+/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/
+#define RTC_CNTL_TOUCH_FILTER_MODE  0x00000003
+#define RTC_CNTL_TOUCH_FILTER_MODE_M  ((RTC_CNTL_TOUCH_FILTER_MODE_V)<<(RTC_CNTL_TOUCH_FILTER_MODE_S))
+#define RTC_CNTL_TOUCH_FILTER_MODE_V  0x3
+#define RTC_CNTL_TOUCH_FILTER_MODE_S  29
+/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[28:26] ;default: 3'd3 ; */
+/*description: debounce counter*/
+#define RTC_CNTL_TOUCH_DEBOUNCE  0x00000007
+#define RTC_CNTL_TOUCH_DEBOUNCE_M  ((RTC_CNTL_TOUCH_DEBOUNCE_V)<<(RTC_CNTL_TOUCH_DEBOUNCE_S))
+#define RTC_CNTL_TOUCH_DEBOUNCE_V  0x7
+#define RTC_CNTL_TOUCH_DEBOUNCE_S  26
+/* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[25:24] ;default: 2'd1 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_HYSTERESIS  0x00000003
+#define RTC_CNTL_TOUCH_HYSTERESIS_M  ((RTC_CNTL_TOUCH_HYSTERESIS_V)<<(RTC_CNTL_TOUCH_HYSTERESIS_S))
+#define RTC_CNTL_TOUCH_HYSTERESIS_V  0x3
+#define RTC_CNTL_TOUCH_HYSTERESIS_S  24
+/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[23:22] ;default: 2'd1 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_NOISE_THRES  0x00000003
+#define RTC_CNTL_TOUCH_NOISE_THRES_M  ((RTC_CNTL_TOUCH_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NOISE_THRES_S))
+#define RTC_CNTL_TOUCH_NOISE_THRES_V  0x3
+#define RTC_CNTL_TOUCH_NOISE_THRES_S  22
+/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[21:20] ;default: 2'd1 ; */
+/*description: */
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES  0x00000003
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M  ((RTC_CNTL_TOUCH_NEG_NOISE_THRES_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_THRES_S))
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V  0x3
+#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S  20
+/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[19:16] ;default: 4'd5 ; */
+/*description: negative threshold counter limit*/
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT  0x0000000F
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M  ((RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V)<<(RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S))
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V  0xF
+#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S  16
+/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[15:12] ;default: 4'd1 ; */
+/*description: touch jitter step*/
+#define RTC_CNTL_TOUCH_JITTER_STEP  0x0000000F
+#define RTC_CNTL_TOUCH_JITTER_STEP_M  ((RTC_CNTL_TOUCH_JITTER_STEP_V)<<(RTC_CNTL_TOUCH_JITTER_STEP_S))
+#define RTC_CNTL_TOUCH_JITTER_STEP_V  0xF
+#define RTC_CNTL_TOUCH_JITTER_STEP_S  12
+
+#define RTC_CNTL_USB_CONF_REG          (DR_REG_RTCCNTL_BASE + 0x0120)
+/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_TX_EN_OVERRIDE  (BIT(16))
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_M  (BIT(16))
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_TX_EN_OVERRIDE_S  16
+/* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_TX_EN  (BIT(15))
+#define RTC_CNTL_USB_TX_EN_M  (BIT(15))
+#define RTC_CNTL_USB_TX_EN_V  0x1
+#define RTC_CNTL_USB_TX_EN_S  15
+/* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_TXP  (BIT(14))
+#define RTC_CNTL_USB_TXP_M  (BIT(14))
+#define RTC_CNTL_USB_TXP_V  0x1
+#define RTC_CNTL_USB_TXP_S  14
+/* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_TXM  (BIT(13))
+#define RTC_CNTL_USB_TXM_M  (BIT(13))
+#define RTC_CNTL_USB_TXM_V  0x1
+#define RTC_CNTL_USB_TXM_S  13
+/* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_PAD_ENABLE  (BIT(12))
+#define RTC_CNTL_USB_PAD_ENABLE_M  (BIT(12))
+#define RTC_CNTL_USB_PAD_ENABLE_V  0x1
+#define RTC_CNTL_USB_PAD_ENABLE_S  12
+/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE  (BIT(11))
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M  (BIT(11))
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S  11
+/* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_PULLUP_VALUE  (BIT(10))
+#define RTC_CNTL_USB_PULLUP_VALUE_M  (BIT(10))
+#define RTC_CNTL_USB_PULLUP_VALUE_V  0x1
+#define RTC_CNTL_USB_PULLUP_VALUE_S  10
+/* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_DM_PULLDOWN  (BIT(9))
+#define RTC_CNTL_USB_DM_PULLDOWN_M  (BIT(9))
+#define RTC_CNTL_USB_DM_PULLDOWN_V  0x1
+#define RTC_CNTL_USB_DM_PULLDOWN_S  9
+/* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_DM_PULLUP  (BIT(8))
+#define RTC_CNTL_USB_DM_PULLUP_M  (BIT(8))
+#define RTC_CNTL_USB_DM_PULLUP_V  0x1
+#define RTC_CNTL_USB_DM_PULLUP_S  8
+/* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_DP_PULLDOWN  (BIT(7))
+#define RTC_CNTL_USB_DP_PULLDOWN_M  (BIT(7))
+#define RTC_CNTL_USB_DP_PULLDOWN_V  0x1
+#define RTC_CNTL_USB_DP_PULLDOWN_S  7
+/* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_DP_PULLUP  (BIT(6))
+#define RTC_CNTL_USB_DP_PULLUP_M  (BIT(6))
+#define RTC_CNTL_USB_DP_PULLUP_V  0x1
+#define RTC_CNTL_USB_DP_PULLUP_S  6
+/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE  (BIT(5))
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M  (BIT(5))
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S  5
+/* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_VREF_OVERRIDE  (BIT(4))
+#define RTC_CNTL_USB_VREF_OVERRIDE_M  (BIT(4))
+#define RTC_CNTL_USB_VREF_OVERRIDE_V  0x1
+#define RTC_CNTL_USB_VREF_OVERRIDE_S  4
+/* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_VREFL  0x00000003
+#define RTC_CNTL_USB_VREFL_M  ((RTC_CNTL_USB_VREFL_V)<<(RTC_CNTL_USB_VREFL_S))
+#define RTC_CNTL_USB_VREFL_V  0x3
+#define RTC_CNTL_USB_VREFL_S  2
+/* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: */
+#define RTC_CNTL_USB_VREFH  0x00000003
+#define RTC_CNTL_USB_VREFH_M  ((RTC_CNTL_USB_VREFH_V)<<(RTC_CNTL_USB_VREFH_S))
+#define RTC_CNTL_USB_VREFH_V  0x3
+#define RTC_CNTL_USB_VREFH_S  0
+
+#define RTC_CNTL_DATE_REG          (DR_REG_RTCCNTL_BASE + 0x0124)
+/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810310 ; */
+/*description: */
+#define RTC_CNTL_CNTL_DATE  0x0FFFFFFF
+#define RTC_CNTL_CNTL_DATE_M  ((RTC_CNTL_CNTL_DATE_V)<<(RTC_CNTL_CNTL_DATE_S))
+#define RTC_CNTL_CNTL_DATE_V  0xFFFFFFF
+#define RTC_CNTL_CNTL_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_CNTL_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h b/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h
new file mode 100644
index 000000000..44ce11113
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc_cntl_struct.h
@@ -0,0 +1,645 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_CNTL_STRUCT_H_
+#define _SOC_RTC_CNTL_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t sw_stall_appcpu_c0:  2;             /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
+            uint32_t sw_stall_procpu_c0:  2;             /*{reg_sw_stall_procpu_c1[5:0]   reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
+            uint32_t sw_appcpu_rst:       1;             /*APP CPU SW reset*/
+            uint32_t sw_procpu_rst:       1;             /*PRO CPU SW reset*/
+            uint32_t bb_i2c_force_pd:     1;             /*BB_I2C force power down*/
+            uint32_t bb_i2c_force_pu:     1;             /*BB_I2C force power up*/
+            uint32_t bbpll_i2c_force_pd:  1;             /*BB_PLL _I2C force power down*/
+            uint32_t bbpll_i2c_force_pu:  1;             /*BB_PLL_I2C force power up*/
+            uint32_t bbpll_force_pd:      1;             /*BB_PLL force power down*/
+            uint32_t bbpll_force_pu:      1;             /*BB_PLL force power up*/
+            uint32_t xtl_force_pd:        1;             /*crystall force power down*/
+            uint32_t xtl_force_pu:        1;             /*crystall force power up*/
+            uint32_t bias_sleep_folw_8m:  1;             /*BIAS_SLEEP follow CK8M*/
+            uint32_t bias_force_sleep:    1;             /*BIAS_SLEEP force sleep*/
+            uint32_t bias_force_nosleep:  1;             /*BIAS_SLEEP force no sleep*/
+            uint32_t bias_i2c_folw_8m:    1;             /*BIAS_I2C follow CK8M*/
+            uint32_t bias_i2c_force_pd:   1;             /*BIAS_I2C force power down*/
+            uint32_t bias_i2c_force_pu:   1;             /*BIAS_I2C force power up*/
+            uint32_t bias_core_folw_8m:   1;             /*BIAS_CORE follow CK8M*/
+            uint32_t bias_core_force_pd:  1;             /*BIAS_CORE force power down*/
+            uint32_t bias_core_force_pu:  1;             /*BIAS_CORE force power up*/
+            uint32_t xtl_force_iso:       1;
+            uint32_t pll_force_iso:       1;
+            uint32_t analog_force_iso:    1;
+            uint32_t xtl_force_noiso:     1;
+            uint32_t pll_force_noiso:     1;
+            uint32_t analog_force_noiso:  1;
+            uint32_t dg_wrap_force_rst:   1;             /*digital wrap force reset in deep sleep*/
+            uint32_t dg_wrap_force_norst: 1;             /*digital core force no reset in deep sleep*/
+            uint32_t sw_sys_rst:          1;             /*SW system reset*/
+        };
+        uint32_t val;
+    } options0;
+    uint32_t slp_timer0;                             /*RTC sleep timer low 32 bits*/
+    union {
+        struct {
+            uint32_t slp_val_hi:             16;         /*RTC sleep timer high 16 bits*/
+            uint32_t main_timer_alarm_en:     1;         /*timer alarm enable bit*/
+            uint32_t reserved17:             15;
+        };
+        uint32_t val;
+    } slp_timer1;
+    union {
+        struct {
+            uint32_t reserved0:      30;
+            uint32_t valid:           1;                 /*To indicate the register is updated*/
+            uint32_t update:          1;                 /*Set 1: to update register with RTC timer*/
+        };
+        uint32_t val;
+    } time_update;
+    uint32_t time0;                                  /*RTC timer low 32 bits*/
+    union {
+        struct {
+            uint32_t time_hi:    16;                     /*RTC timer high 16 bits*/
+            uint32_t reserved16: 16;
+        };
+        uint32_t val;
+    } time1;
+    union {
+        struct {
+            uint32_t reserved0:             18;
+            uint32_t cocpu_wakeup:           1;          /*riscV cocpu wake up register*/
+            uint32_t cocpu_wakeup_force_en:  1;          /*riscV cocpu force wake up*/
+            uint32_t touch_wakeup_force_en:  1;          /*touch controller force wake up*/
+            uint32_t ulp_cp_wakeup_force_en: 1;          /*ULP-coprocessor force wake up*/
+            uint32_t apb2rtc_bridge_sel:     1;          /*1: APB to RTC using bridge   0: APB to RTC using sync*/
+            uint32_t touch_slp_timer_en:     1;          /*touch timer enable bit*/
+            uint32_t ulp_cp_slp_timer_en:    1;          /*ULP-coprocessor timer enable bit*/
+            uint32_t ulp_cp_gpio_wakeup_ena: 1;          /*ULP-coprocessor wakeup by GPIO enable*/
+            uint32_t ulp_cp_gpio_wakeup_clr: 1;          /*ULP-coprocessor wakeup by GPIO state clear*/
+            uint32_t reserved27:             1;
+            uint32_t sdio_active_ind:        1;          /*SDIO active indication*/
+            uint32_t slp_wakeup:             1;          /*leep wakeup bit*/
+            uint32_t slp_reject:             1;          /*leep reject bit*/
+            uint32_t sleep_en:               1;          /*sleep enable bit*/
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t cpu_stall_en:   1;                  /*CPU stall enable bit*/
+            uint32_t cpu_stall_wait: 5;                  /*CPU stall wait cycles in fast_clk_rtc*/
+            uint32_t ck8m_wait:      8;                  /*CK8M wait cycles in slow_clk_rtc*/
+            uint32_t xtl_buf_wait:  10;                  /*XTAL wait cycles in slow_clk_rtc*/
+            uint32_t pll_buf_wait:   8;                  /*PLL wait cycles in slow_clk_rtc*/
+        };
+        uint32_t val;
+    } timer1;
+    union {
+        struct {
+            uint32_t reserved0:             15;
+            uint32_t ulpcp_touch_start_wait: 9;          /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/
+            uint32_t min_time_ck8m_off:      8;          /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
+        };
+        uint32_t val;
+    } timer2;
+    union {
+        struct {
+            uint32_t wifi_wait_timer:       9;
+            uint32_t wifi_powerup_timer:    7;
+            uint32_t rom_ram_wait_timer:    9;
+            uint32_t rom_ram_powerup_timer: 7;
+        };
+        uint32_t val;
+    } timer3;
+    union {
+        struct {
+            uint32_t rtc_wait_timer:        9;
+            uint32_t rtc_powerup_timer:     7;
+            uint32_t dg_wrap_wait_timer:    9;
+            uint32_t dg_wrap_powerup_timer: 7;
+        };
+        uint32_t val;
+    } timer4;
+    union {
+        struct {
+            uint32_t ulp_cp_subtimer_prediv: 8;
+            uint32_t min_slp_val:            8;          /*minimal sleep cycles in slow_clk_rtc*/
+            uint32_t rtcmem_wait_timer:      9;
+            uint32_t rtcmem_powerup_timer:   7;
+        };
+        uint32_t val;
+    } timer5;
+    union {
+        struct {
+            uint32_t reserved0:            16;
+            uint32_t dg_dcdc_wait_timer:    9;
+            uint32_t dg_dcdc_powerup_timer: 7;
+        };
+        uint32_t val;
+    } timer6;
+    union {
+        struct {
+            uint32_t reserved0:          19;
+            uint32_t pkdet_cal_force_en:  2;             /*pkdet force option*/
+            uint32_t pwdet_cal_force_en:  2;             /*pwdet force option*/
+            uint32_t plla_force_pd:       1;             /*PLLA force power down*/
+            uint32_t plla_force_pu:       1;             /*PLLA force power up*/
+            uint32_t bbpll_cal_slp_start: 1;             /*start BBPLL calibration during sleep*/
+            uint32_t pvtmon_pu:           1;             /*1: PVTMON power up   otherwise power down*/
+            uint32_t txrf_i2c_pu:         1;             /*1: TXRF_I2C power up   otherwise power down*/
+            uint32_t rfrx_pbus_pu:        1;             /*1: RFRX_PBUS power up   otherwise power down*/
+            uint32_t reserved29:          1;
+            uint32_t ckgen_i2c_pu:        1;             /*1: CKGEN_I2C power up   otherwise power down*/
+            uint32_t pll_i2c_pu:          1;
+        };
+        uint32_t val;
+    } ana_conf;
+    union {
+        struct {
+            uint32_t reset_cause_procpu:     6;          /*reset cause of PRO CPU*/
+            uint32_t reset_cause_appcpu:     6;          /*reset cause of APP CPU*/
+            uint32_t appcpu_stat_vector_sel: 1;          /*APP CPU state vector sel*/
+            uint32_t procpu_stat_vector_sel: 1;          /*PRO CPU state vector sel*/
+            uint32_t reserved14:            18;
+        };
+        uint32_t val;
+    } reset_state;
+    union {
+        struct {
+            uint32_t wakeup_cause:      12;              /*wakeup cause*/
+            uint32_t rtc_wakeup_ena:    12;              /*wakeup enable bitmap*/
+            uint32_t gpio_wakeup_filter: 1;              /*enable filter for gpio wakeup event*/
+            uint32_t reserved25:         7;
+        };
+        uint32_t val;
+    } wakeup_state;
+    union {
+        struct {
+            uint32_t slp_wakeup:             1;          /*enable sleep wakeup interrupt*/
+            uint32_t slp_reject:             1;          /*enable sleep reject interrupt*/
+            uint32_t sdio_idle:              1;          /*enable SDIO idle interrupt*/
+            uint32_t rtc_wdt:                1;          /*enable RTC WDT interrupt*/
+            uint32_t rtc_time_valid:         1;          /*enable RTC time valid interrupt*/
+            uint32_t rtc_ulp_cp:             1;          /*enable ULP-coprocessor interrupt*/
+            uint32_t rtc_touch:              1;          /*enable touch interrupt*/
+            uint32_t rtc_brown_out:          1;          /*enable brown out interrupt*/
+            uint32_t rtc_main_timer:         1;          /*enable RTC main timer interrupt*/
+            uint32_t rtc_saradc1:            1;          /*enable saradc1 interrupt*/
+            uint32_t rtc_tsens:              1;          /*enable tsens interrupt*/
+            uint32_t rtc_cocpu:              1;          /*enable riscV cocpu interrupt*/
+            uint32_t rtc_saradc2:            1;          /*enable saradc2 interrupt*/
+            uint32_t reserved13:            19;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t slp_wakeup:             1;          /*sleep wakeup interrupt raw*/
+            uint32_t slp_reject:             1;          /*sleep reject interrupt raw*/
+            uint32_t sdio_idle:              1;          /*SDIO idle interrupt raw*/
+            uint32_t rtc_wdt:                1;          /*RTC WDT interrupt raw*/
+            uint32_t rtc_time_valid:         1;          /*RTC time valid interrupt raw*/
+            uint32_t rtc_ulp_cp:             1;          /*ULP-coprocessor interrupt raw*/
+            uint32_t rtc_touch:              1;          /*touch interrupt raw*/
+            uint32_t rtc_brown_out:          1;          /*brown out interrupt raw*/
+            uint32_t rtc_main_timer:         1;          /*RTC main timer interrupt raw*/
+            uint32_t rtc_saradc1:            1;          /*saradc1 interrupt raw*/
+            uint32_t rtc_tsens:              1;          /*tsens interrupt raw*/
+            uint32_t rtc_cocpu:              1;          /*riscV cocpu interrupt raw*/
+            uint32_t rtc_saradc2:            1;          /*saradc2 interrupt raw*/
+            uint32_t reserved13:            19;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slp_wakeup:            1;           /*sleep wakeup interrupt state*/
+            uint32_t slp_reject:            1;           /*sleep reject interrupt state*/
+            uint32_t sdio_idle:             1;           /*SDIO idle interrupt state*/
+            uint32_t rtc_wdt:               1;           /*RTC WDT interrupt state*/
+            uint32_t rtc_time_valid:        1;           /*RTC time valid interrupt state*/
+            uint32_t rtc_ulp_cp:            1;           /*ULP-coprocessor interrupt state*/
+            uint32_t rtc_touch:             1;           /*touch interrupt state*/
+            uint32_t rtc_brown_out:         1;           /*brown out interrupt state*/
+            uint32_t rtc_main_timer:        1;           /*RTC main timer interrupt state*/
+            uint32_t rtc_saradc1:           1;           /*saradc1 interrupt state*/
+            uint32_t rtc_tsens:             1;           /*tsens interrupt state*/
+            uint32_t rtc_cocpu:             1;           /*riscV cocpu interrupt state*/
+            uint32_t rtc_saradc2:           1;           /*saradc2 interrupt state*/
+            uint32_t reserved13:           19;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slp_wakeup:             1;          /*Clear sleep wakeup interrupt state*/
+            uint32_t slp_reject:             1;          /*Clear sleep reject interrupt state*/
+            uint32_t sdio_idle:              1;          /*Clear SDIO idle interrupt state*/
+            uint32_t rtc_wdt:                1;          /*Clear RTC WDT interrupt state*/
+            uint32_t rtc_time_valid:         1;          /*Clear RTC time valid interrupt state*/
+            uint32_t rtc_ulp_cp:             1;          /*Clear ULP-coprocessor interrupt state*/
+            uint32_t rtc_touch:              1;          /*Clear touch interrupt state*/
+            uint32_t rtc_brown_out:          1;          /*Clear brown out interrupt state*/
+            uint32_t rtc_main_timer:         1;          /*Clear RTC main timer interrupt state*/
+            uint32_t rtc_saradc1:            1;          /*Clear saradc1 interrupt state*/
+            uint32_t rtc_tsens:              1;          /*Clear tsens interrupt state*/
+            uint32_t rtc_cocpu:              1;          /*Clear riscV cocpu interrupt state*/
+            uint32_t rtc_saradc2:            1;          /*Clear saradc2 interrupt state*/
+            uint32_t reserved13:            19;
+        };
+        uint32_t val;
+    } int_clr;
+    uint32_t store[4];                                 /**/
+    union {
+        struct {
+            uint32_t reserved0:     30;
+            uint32_t ctr_lv:         1;                  /*0: power down XTAL at high level  1: power down XTAL at low level*/
+            uint32_t ctr_en:         1;
+        };
+        uint32_t val;
+    } ext_xtl_conf;
+    union {
+        struct {
+            uint32_t reserved0:     30;
+            uint32_t wakeup0_lv:     1;                  /*0: external wakeup at low level  1: external wakeup at high level*/
+            uint32_t wakeup1_lv:     1;
+        };
+        uint32_t val;
+    } ext_wakeup_conf;
+    union {
+        struct {
+            uint32_t reserved0:          24;
+            uint32_t gpio_reject_en:      1;             /*enable GPIO reject*/
+            uint32_t sdio_reject_en:      1;             /*enable SDIO reject*/
+            uint32_t light_slp_reject_en: 1;             /*enable reject for light sleep*/
+            uint32_t deep_slp_reject_en:  1;             /*enable reject for deep sleep*/
+            uint32_t reject_cause:        4;
+        };
+        uint32_t val;
+    } slp_reject_conf;
+    union {
+        struct {
+            uint32_t reserved0:        29;
+            uint32_t cpusel_conf:       1;               /*CPU sel option*/
+            uint32_t cpuperiod_sel:     2;
+        };
+        uint32_t val;
+    } cpu_period_conf;
+    union {
+        struct {
+            uint32_t reserved0:    22;
+            uint32_t sdio_act_dnum:10;
+        };
+        uint32_t val;
+    } sdio_act_conf;
+    union {
+        struct {
+            uint32_t reserved0:           3;
+            uint32_t ck8m_div_sel_vld:    1;             /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel  then set vld to actually switch the clk*/
+            uint32_t ck8m_div:            2;             /*CK8M_D256_OUT divider. 00: div128  01: div256  10: div512  11: div1024.*/
+            uint32_t enb_ck8m:            1;             /*disable CK8M and CK8M_D256_OUT*/
+            uint32_t enb_ck8m_div:        1;             /*1: CK8M_D256_OUT is actually CK8M  0: CK8M_D256_OUT is CK8M divided by 256*/
+            uint32_t dig_xtal32k_en:      1;             /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_d256_en:   1;             /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
+            uint32_t dig_clk8m_en:        1;             /*enable CK8M for digital core (no relationship with RTC core)*/
+            uint32_t reserved11:          1;
+            uint32_t ck8m_div_sel:        3;             /*divider = reg_ck8m_div_sel + 1*/
+            uint32_t xtal_force_nogating: 1;             /*XTAL force no gating during sleep*/
+            uint32_t ck8m_force_nogating: 1;             /*CK8M force no gating during sleep*/
+            uint32_t ck8m_dfreq:          8;             /*CK8M_DFREQ*/
+            uint32_t ck8m_force_pd:       1;             /*CK8M force power down*/
+            uint32_t ck8m_force_pu:       1;             /*CK8M force power up*/
+            uint32_t reserved27:          2;
+            uint32_t fast_clk_rtc_sel:    1;             /*fast_clk_rtc sel. 0: XTAL div 4  1: CK8M*/
+            uint32_t ana_clk_rtc_sel:     2;
+        };
+        uint32_t val;
+    } clk_conf;
+    union {
+        struct {
+            uint32_t reserved0:             14;
+            uint32_t dbias_xtal_32k:         2;          /*DBIAS_XTAL_32K*/
+            uint32_t dres_xtal_32k:          2;          /*DRES_XTAL_32K*/
+            uint32_t xpd_xtal_32k:           1;          /*XPD_XTAL_32K*/
+            uint32_t dac_xtal_32k:           2;          /*DAC_XTAL_32K*/
+            uint32_t rtc_xtal32k_gpio_sel:   1;          /*XTAL_32K sel. 0: external XTAL_32K  1: CLK from RTC pad X32P_C*/
+            uint32_t rtc_ana_clk_div_vld:    1;          /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div  then set vld to actually switch the clk*/
+            uint32_t rtc_ana_clk_div:        8;
+            uint32_t slow_clk_next_edge:     1;
+        };
+        uint32_t val;
+    } slow_clk_conf;
+    union {
+        struct {
+            uint32_t reserved0:   21;
+            uint32_t sdio_pd_en:   1;                    /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
+            uint32_t sdio_force:   1;                    /*1: use SW option to control SDIO_REG  0: use state machine*/
+            uint32_t sdio_tieh:    1;                    /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
+            uint32_t reg1p8_ready: 1;                    /*read only register for REG1P8_READY*/
+            uint32_t drefl_sdio:   2;                    /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefm_sdio:   2;                    /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t drefh_sdio:   2;                    /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
+            uint32_t xpd_sdio:     1;
+        };
+        uint32_t val;
+    } sdio_conf;
+    union {
+        struct {
+            uint32_t reserved0:            24;
+            uint32_t dbg_atten:             2;           /*DBG_ATTEN*/
+            uint32_t enb_sck_xtal:          1;           /*ENB_SCK_XTAL*/
+            uint32_t inc_heartbeat_refresh: 1;           /*INC_HEARTBEAT_REFRESH*/
+            uint32_t dec_heartbeat_period:  1;           /*DEC_HEARTBEAT_PERIOD*/
+            uint32_t inc_heartbeat_period:  1;           /*INC_HEARTBEAT_PERIOD*/
+            uint32_t dec_heartbeat_width:   1;           /*DEC_HEARTBEAT_WIDTH*/
+            uint32_t rst_bias_i2c:          1;
+        };
+        uint32_t val;
+    } bias_conf;
+    union {
+        struct {
+            uint32_t reserved0:           8;
+            uint32_t dig_dbias_slp:       3;             /*DIG_REG_DBIAS during sleep*/
+            uint32_t dig_dbias_wak:       3;             /*DIG_REG_DBIAS during wakeup*/
+            uint32_t sck_dcap:            8;             /*SCK_DCAP*/
+            uint32_t rtc_dbias_slp:       3;             /*RTC_DBIAS during sleep*/
+            uint32_t rtc_dbias_wak:       3;             /*RTC_DBIAS during wakeup*/
+            uint32_t rtc_dboost_force_pd: 1;             /*RTC_DBOOST force power down*/
+            uint32_t rtc_dboost_force_pu: 1;             /*RTC_DBOOST force power up*/
+            uint32_t rtculator_force_pd:  1;             /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
+            uint32_t rtculator_force_pu:  1;
+        };
+        uint32_t val;
+    } rtc;
+    union {
+        struct {
+            uint32_t fastmem_force_noiso:     1;         /*Fast RTC memory force no ISO*/
+            uint32_t fastmem_force_iso:       1;         /*Fast RTC memory force ISO*/
+            uint32_t slowmem_force_noiso:     1;         /*RTC memory force no ISO*/
+            uint32_t slowmem_force_iso:       1;         /*RTC memory force ISO*/
+            uint32_t rtc_force_iso:           1;         /*rtc_peri force ISO*/
+            uint32_t rtc_force_noiso:         1;         /*rtc_peri force no ISO*/
+            uint32_t fastmem_folw_cpu:        1;         /*1: Fast RTC memory PD following CPU  0: fast RTC memory PD following RTC state machine*/
+            uint32_t fastmem_force_lpd:       1;         /*Fast RTC memory force PD*/
+            uint32_t fastmem_force_lpu:       1;         /*Fast RTC memory force no PD*/
+            uint32_t slowmem_folw_cpu:        1;         /*1: RTC memory  PD following CPU  0: RTC memory PD following RTC state machine*/
+            uint32_t slowmem_force_lpd:       1;         /*RTC memory force PD*/
+            uint32_t slowmem_force_lpu:       1;         /*RTC memory force no PD*/
+            uint32_t fastmem_force_pd:        1;         /*Fast RTC memory force power down*/
+            uint32_t fastmem_force_pu:        1;         /*Fast RTC memory force power up*/
+            uint32_t fastmem_pd_en:           1;         /*enable power down fast RTC memory in sleep*/
+            uint32_t slowmem_force_pd:        1;         /*RTC memory force power down*/
+            uint32_t slowmem_force_pu:        1;         /*RTC memory force power up*/
+            uint32_t slowmem_pd_en:           1;         /*enable power down RTC memory in sleep*/
+            uint32_t rtc_force_pd:            1;         /*rtc_peri force power down*/
+            uint32_t rtc_force_pu:            1;         /*rtc_peri force power up*/
+            uint32_t rtc_pd_en:               1;         /*enable power down rtc_peri in sleep*/
+            uint32_t rtc_pad_autohold:        1;         /*read only register to indicate rtc pad auto-hold status*/
+            uint32_t clr_rtc_pad_autohold:    1;         /*wtite only register to clear rtc pad auto-hold*/
+            uint32_t rtc_pad_autohold_en:     1;         /*rtc pad enable auto-hold*/
+            uint32_t rtc_pad_force_noiso:     1;         /*rtc pad force no ISO*/
+            uint32_t rtc_pad_force_iso:       1;         /*rtc pad force ISO*/
+            uint32_t rtc_pad_force_unhold:    1;         /*rtc pad force un-hold*/
+            uint32_t rtc_pad_force_hold:      1;         /*rtc pad force hold*/
+            uint32_t reserved28:              4;
+        };
+        uint32_t val;
+    } rtc_pwc;
+    union {
+        struct {
+            uint32_t reserved0:           3;
+            uint32_t lslp_mem_force_pd:   1;             /*memories in digital core force PD in sleep*/
+            uint32_t lslp_mem_force_pu:   1;             /*memories in digital core force no PD in sleep*/
+            uint32_t rom0_force_pd:       1;             /*ROM force power down*/
+            uint32_t rom0_force_pu:       1;             /*ROM force power up*/
+            uint32_t inter_ram0_force_pd: 1;             /*internal SRAM 0 force power down*/
+            uint32_t inter_ram0_force_pu: 1;             /*internal SRAM 0 force power up*/
+            uint32_t inter_ram1_force_pd: 1;             /*internal SRAM 1 force power down*/
+            uint32_t inter_ram1_force_pu: 1;             /*internal SRAM 1 force power up*/
+            uint32_t inter_ram2_force_pd: 1;             /*internal SRAM 2 force power down*/
+            uint32_t inter_ram2_force_pu: 1;             /*internal SRAM 2 force power up*/
+            uint32_t inter_ram3_force_pd: 1;             /*internal SRAM 3 force power down*/
+            uint32_t inter_ram3_force_pu: 1;             /*internal SRAM 3 force power up*/
+            uint32_t inter_ram4_force_pd: 1;             /*internal SRAM 4 force power down*/
+            uint32_t inter_ram4_force_pu: 1;             /*internal SRAM 4 force power up*/
+            uint32_t wifi_force_pd:       1;             /*wifi force power down*/
+            uint32_t wifi_force_pu:       1;             /*wifi force power up*/
+            uint32_t dg_wrap_force_pd:    1;             /*digital core force power down*/
+            uint32_t dg_wrap_force_pu:    1;             /*digital core force power up*/
+            uint32_t dg_dcdc_force_pd:    1;             /*digital dcdc force power down*/
+            uint32_t dg_dcdc_force_pu:    1;             /*digital dcdc force power up*/
+            uint32_t dg_dcdc_pd_en:       1;             /*enable power down digital dcdc in sleep*/
+            uint32_t rom0_pd_en:          1;             /*enable power down ROM in sleep*/
+            uint32_t inter_ram0_pd_en:    1;             /*enable power down internal SRAM 0 in sleep*/
+            uint32_t inter_ram1_pd_en:    1;             /*enable power down internal SRAM 1 in sleep*/
+            uint32_t inter_ram2_pd_en:    1;             /*enable power down internal SRAM 2 in sleep*/
+            uint32_t inter_ram3_pd_en:    1;             /*enable power down internal SRAM 3 in sleep*/
+            uint32_t inter_ram4_pd_en:    1;             /*enable power down internal SRAM 4 in sleep*/
+            uint32_t wifi_pd_en:          1;             /*enable power down wifi in sleep*/
+            uint32_t dg_wrap_pd_en:       1;
+        };
+        uint32_t val;
+    } dig_pwc;
+    union {
+        struct {
+            uint32_t reserved0:              7;
+            uint32_t dig_iso_force_off:      1;
+            uint32_t dig_iso_force_on:       1;
+            uint32_t dg_pad_autohold:        1;          /*read only register to indicate digital pad auto-hold status*/
+            uint32_t clr_dg_pad_autohold:    1;          /*wtite only register to clear digital pad auto-hold*/
+            uint32_t dg_pad_autohold_en:     1;          /*digital pad enable auto-hold*/
+            uint32_t dg_pad_force_noiso:     1;          /*digital pad force no ISO*/
+            uint32_t dg_pad_force_iso:       1;          /*digital pad force ISO*/
+            uint32_t dg_pad_force_unhold:    1;          /*digital pad force un-hold*/
+            uint32_t dg_pad_force_hold:      1;          /*digital pad force hold*/
+            uint32_t rom0_force_iso:         1;          /*ROM force ISO*/
+            uint32_t rom0_force_noiso:       1;          /*ROM force no ISO*/
+            uint32_t inter_ram0_force_iso:   1;          /*internal SRAM 0 force ISO*/
+            uint32_t inter_ram0_force_noiso: 1;          /*internal SRAM 0 force no ISO*/
+            uint32_t inter_ram1_force_iso:   1;          /*internal SRAM 1 force ISO*/
+            uint32_t inter_ram1_force_noiso: 1;          /*internal SRAM 1 force no ISO*/
+            uint32_t inter_ram2_force_iso:   1;          /*internal SRAM 2 force ISO*/
+            uint32_t inter_ram2_force_noiso: 1;          /*internal SRAM 2 force no ISO*/
+            uint32_t inter_ram3_force_iso:   1;          /*internal SRAM 3 force ISO*/
+            uint32_t inter_ram3_force_noiso: 1;          /*internal SRAM 3 force no ISO*/
+            uint32_t inter_ram4_force_iso:   1;          /*internal SRAM 4 force ISO*/
+            uint32_t inter_ram4_force_noiso: 1;          /*internal SRAM 4 force no ISO*/
+            uint32_t wifi_force_iso:         1;          /*wifi force ISO*/
+            uint32_t wifi_force_noiso:       1;          /*wifi force no ISO*/
+            uint32_t dg_wrap_force_iso:      1;          /*digital core force ISO*/
+            uint32_t dg_wrap_force_noiso:    1;
+        };
+        uint32_t val;
+    } dig_iso;
+    union {
+        struct {
+            uint32_t reserved0:            7;
+            uint32_t pause_in_slp:         1;            /*pause WDT in sleep*/
+            uint32_t appcpu_reset_en:      1;            /*enable WDT reset APP CPU*/
+            uint32_t procpu_reset_en:      1;            /*enable WDT reset PRO CPU*/
+            uint32_t flashboot_mod_en:     1;            /*enable WDT in flash boot*/
+            uint32_t sys_reset_length:     3;            /*system reset counter length*/
+            uint32_t cpu_reset_length:     3;            /*CPU reset counter length*/
+            uint32_t level_int_en:         1;            /*N/A*/
+            uint32_t edge_int_en:          1;            /*N/A*/
+            uint32_t stg3:                 3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
+            uint32_t stg2:                 3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
+            uint32_t stg1:                 3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
+            uint32_t stg0:                 3;            /*1: interrupt stage en  2: CPU reset stage en  3: system reset stage en  4: RTC reset stage en*/
+            uint32_t en:                   1;
+        };
+        uint32_t val;
+    } wdt_config0;
+    uint32_t wdt_config1;                             /**/
+    uint32_t wdt_config2;                             /**/
+    uint32_t wdt_config3;                             /**/
+    uint32_t wdt_config4;                             /**/
+    union {
+        struct {
+            uint32_t reserved0:   31;
+            uint32_t feed:         1;
+        };
+        uint32_t val;
+    } wdt_feed;
+    uint32_t wdt_wprotect;                            /**/
+    union {
+        struct {
+            uint32_t reserved0: 29;
+            uint32_t ent_rtc:    1;                      /*ENT_RTC*/
+            uint32_t dtest_rtc:  2;
+        };
+        uint32_t val;
+    } test_mux;
+    union {
+        struct {
+            uint32_t reserved0:         20;
+            uint32_t appcpu_c1:          6;              /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
+            uint32_t procpu_c1:          6;
+        };
+        uint32_t val;
+    } sw_cpu_stall;
+    uint32_t store4;                                 /**/
+    uint32_t store5;                                 /**/
+    uint32_t store6;                                 /**/
+    uint32_t store7;                                 /**/
+    union {
+        struct {
+            uint32_t xpd_rom0:                   1;      /*rom0 power down*/
+            uint32_t reserved1:                  1;
+            uint32_t xpd_dig_dcdc:               1;      /*External DCDC power down*/
+            uint32_t rtc_peri_iso:               1;      /*rtc peripheral iso*/
+            uint32_t xpd_rtc_peri:               1;      /*rtc peripheral power down*/
+            uint32_t wifi_iso:                   1;      /*wifi iso*/
+            uint32_t xpd_wifi:                   1;      /*wifi wrap power down*/
+            uint32_t dig_iso:                    1;      /*digital wrap iso*/
+            uint32_t xpd_dig:                    1;      /*digital wrap power down*/
+            uint32_t rtc_touch_start:            1;      /*touch should start to work*/
+            uint32_t rtc_touch_state_switch:     1;      /*touch is about to working. Switch rtc main state*/
+            uint32_t rtc_touch_slp:              1;      /*touch is in sleep state*/
+            uint32_t rtc_touch_done:             1;      /*touch is done*/
+            uint32_t rtc_cocpu_start:            1;      /*ulp/cocpu should start to work*/
+            uint32_t rtc_cocpu_state_switch:     1;      /*ulp/cocpu is about to working. Switch rtc main state*/
+            uint32_t rtc_cocpu_slp:              1;      /*ulp/cocpu is in sleep state*/
+            uint32_t rtc_cocpu_done:             1;      /*ulp/cocpu is done*/
+            uint32_t rtc_main_state_xtal_iso:    1;      /*no use any more*/
+            uint32_t rtc_main_state_pll_on:      1;      /*rtc main state machine is in states that pll should be running*/
+            uint32_t rtc_rdy_for_wakeup:         1;      /*rtc is ready to receive wake up trigger from wake up source*/
+            uint32_t rtc_main_state_wait_end:    1;      /*rtc main state machine has been waited for some cycles*/
+            uint32_t rtc_in_wakeup_state:        1;      /*rtc main state machine is in the states of wakeup process*/
+            uint32_t rtc_in_low_power_state:     1;      /*rtc main state machine is in the states of low power*/
+            uint32_t rtc_main_state_in_wait_8m:  1;      /*rtc main state machine is in wait 8m state*/
+            uint32_t rtc_main_state_in_wait_pll: 1;      /*rtc main state machine is in wait pll state*/
+            uint32_t rtc_main_state_in_wait_xtl: 1;      /*rtc main state machine is in wait xtal state*/
+            uint32_t rtc_main_state_in_slp:      1;      /*rtc main state machine is in sleep state*/
+            uint32_t rtc_main_state_in_idle:     1;      /*rtc main state machine is in idle state*/
+            uint32_t rtc_main_state:             4;      /*rtc main state machine status*/
+        };
+        uint32_t val;
+    } low_power_st;
+    uint32_t diag0;                                  /**/
+    union {
+        struct {
+            uint32_t adc1_hold_force:       1;
+            uint32_t adc2_hold_force:       1;
+            uint32_t pdac1_hold_force:      1;
+            uint32_t pdac2_hold_force:      1;
+            uint32_t sense1_hold_force:     1;
+            uint32_t sense2_hold_force:     1;
+            uint32_t sense3_hold_force:     1;
+            uint32_t sense4_hold_force:     1;
+            uint32_t touch_pad0_hold_force: 1;
+            uint32_t touch_pad1_hold_force: 1;
+            uint32_t touch_pad2_hold_force: 1;
+            uint32_t touch_pad3_hold_force: 1;
+            uint32_t touch_pad4_hold_force: 1;
+            uint32_t touch_pad5_hold_force: 1;
+            uint32_t touch_pad6_hold_force: 1;
+            uint32_t touch_pad7_hold_force: 1;
+            uint32_t x32p_hold_force:       1;
+            uint32_t x32n_hold_force:       1;
+            uint32_t reserved18:           14;
+        };
+        uint32_t val;
+    } hold_force;
+    uint32_t dig_pad_hold;                               /**/
+    union {
+        struct {
+            uint32_t sel:                   18;          /*Bitmap to select RTC pads for ext wakeup1*/
+            uint32_t status_clr:             1;          /*clear ext wakeup1 status*/
+            uint32_t reserved19:            13;
+        };
+        uint32_t val;
+    } ext_wakeup1;
+    union {
+        struct {
+            uint32_t status:            18;              /*ext wakeup1 status*/
+            uint32_t reserved18:        14;
+        };
+        uint32_t val;
+    } ext_wakeup1_status;
+    union {
+        struct {
+            uint32_t reserved0:                14;
+            uint32_t close_flash_ena:           1;       /*enable close flash when brown out happens*/
+            uint32_t pd_rf_ena:                 1;       /*enable power down RF when brown out happens*/
+            uint32_t rst_wait:                 10;       /*brown out reset wait cycles*/
+            uint32_t rst_ena:                   1;       /*enable brown out reset*/
+            uint32_t thres:                     3;       /*brown out threshold*/
+            uint32_t ena:                       1;       /*enable brown out*/
+            uint32_t det:                       1;
+        };
+        uint32_t val;
+    } brown_out;
+    uint32_t reserved_3c;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_cntl_dev_t;
+extern rtc_cntl_dev_t RTCCNTL;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RTC_CNTL_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h b/components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h
new file mode 100644
index 000000000..c5107a0fb
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc_gpio_channel.h
@@ -0,0 +1,73 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_RTC_GPIO_CHANNEL_H
+#define _SOC_RTC_GPIO_CHANNEL_H
+
+//RTC GPIO channels
+#define RTCIO_GPIO36_CHANNEL        0   //RTCIO_CHANNEL_0
+#define RTCIO_CHANNEL_0_GPIO_NUM    36
+
+#define RTCIO_GPIO37_CHANNEL        1   //RTCIO_CHANNEL_1
+#define RTCIO_CHANNEL_1_GPIO_NUM    37
+
+#define RTCIO_GPIO38_CHANNEL        2   //RTCIO_CHANNEL_2
+#define RTCIO_CHANNEL_2_GPIO_NUM    38
+
+#define RTCIO_GPIO39_CHANNEL        3   //RTCIO_CHANNEL_3
+#define RTCIO_CHANNEL_3_GPIO_NUM    39
+
+#define RTCIO_GPIO34_CHANNEL        4   //RTCIO_CHANNEL_4
+#define RTCIO_CHANNEL_4_GPIO_NUM    34
+
+#define RTCIO_GPIO35_CHANNEL        5   //RTCIO_CHANNEL_5
+#define RTCIO_CHANNEL_5_GPIO_NUM    35
+
+#define RTCIO_GPIO25_CHANNEL        6   //RTCIO_CHANNEL_6
+#define RTCIO_CHANNEL_6_GPIO_NUM    25
+
+#define RTCIO_GPIO26_CHANNEL        7   //RTCIO_CHANNEL_7
+#define RTCIO_CHANNEL_7_GPIO_NUM    26
+
+#define RTCIO_GPIO33_CHANNEL        8   //RTCIO_CHANNEL_8
+#define RTCIO_CHANNEL_8_GPIO_NUM    33
+
+#define RTCIO_GPIO32_CHANNEL        9   //RTCIO_CHANNEL_9
+#define RTCIO_CHANNEL_9_GPIO_NUM    32
+
+#define RTCIO_GPIO4_CHANNEL         10   //RTCIO_CHANNEL_10
+#define RTCIO_CHANNEL_10_GPIO_NUM   4
+
+#define RTCIO_GPIO0_CHANNEL         11   //RTCIO_CHANNEL_11
+#define RTCIO_CHANNEL_11_GPIO_NUM   0
+
+#define RTCIO_GPIO2_CHANNEL         12   //RTCIO_CHANNEL_12
+#define RTCIO_CHANNEL_12_GPIO_NUM   2
+
+#define RTCIO_GPIO15_CHANNEL        13   //RTCIO_CHANNEL_13
+#define RTCIO_CHANNEL_13_GPIO_NUM   15
+
+#define RTCIO_GPIO13_CHANNEL        14   //RTCIO_CHANNEL_14
+#define RTCIO_CHANNEL_14_GPIO_NUM   13
+
+#define RTCIO_GPIO12_CHANNEL        15   //RTCIO_CHANNEL_15
+#define RTCIO_CHANNEL_15_GPIO_NUM   12
+
+#define RTCIO_GPIO14_CHANNEL        16   //RTCIO_CHANNEL_16
+#define RTCIO_CHANNEL_16_GPIO_NUM   14
+
+#define RTCIO_GPIO27_CHANNEL        17   //RTCIO_CHANNEL_17
+#define RTCIO_CHANNEL_17_GPIO_NUM   27
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h b/components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h
new file mode 100644
index 000000000..2a05740c0
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc_i2c_reg.h
@@ -0,0 +1,690 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_I2C_REG_H_
+#define _SOC_RTC_I2C_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+/**
+ * This file lists peripheral registers of an I2C controller which is part of the RTC.
+ * ULP coprocessor uses this controller to implement I2C_RD and I2C_WR instructions.
+ *
+ * Part of the functionality of this controller (such as slave mode, and multi-byte
+ * transfers) is not wired to the ULP, and is such, is not available to the
+ * ULP programs.
+ */
+
+#define RTC_I2C_SCL_LOW_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0000)
+/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 0*/
+#define RTC_I2C_SCL_LOW_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_M  ((RTC_I2C_SCL_LOW_PERIOD_V)<<(RTC_I2C_SCL_LOW_PERIOD_S))
+#define RTC_I2C_SCL_LOW_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_LOW_PERIOD_S  0
+
+#define RTC_I2C_CTRL_REG          (DR_REG_RTC_I2C_BASE + 0x0004)
+/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: rtc i2c reg clk gating*/
+#define RTC_I2C_CLK_EN  (BIT(31))
+#define RTC_I2C_CLK_EN_M  (BIT(31))
+#define RTC_I2C_CLK_EN_V  0x1
+#define RTC_I2C_CLK_EN_S  31
+/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: rtc i2c sw reset*/
+#define RTC_I2C_RESET  (BIT(30))
+#define RTC_I2C_RESET_M  (BIT(30))
+#define RTC_I2C_RESET_V  0x1
+#define RTC_I2C_RESET_S  30
+/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: receive lsb first*/
+#define RTC_I2C_RX_LSB_FIRST  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_M  (BIT(5))
+#define RTC_I2C_RX_LSB_FIRST_V  0x1
+#define RTC_I2C_RX_LSB_FIRST_S  5
+/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: transit lsb first*/
+#define RTC_I2C_TX_LSB_FIRST  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_M  (BIT(4))
+#define RTC_I2C_TX_LSB_FIRST_V  0x1
+#define RTC_I2C_TX_LSB_FIRST_S  4
+/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: force start*/
+#define RTC_I2C_TRANS_START  (BIT(3))
+#define RTC_I2C_TRANS_START_M  (BIT(3))
+#define RTC_I2C_TRANS_START_V  0x1
+#define RTC_I2C_TRANS_START_S  3
+/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: 1=master  0=slave*/
+#define RTC_I2C_MS_MODE  (BIT(2))
+#define RTC_I2C_MS_MODE_M  (BIT(2))
+#define RTC_I2C_MS_MODE_V  0x1
+#define RTC_I2C_MS_MODE_S  2
+/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SCL_FORCE_OUT  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_M  (BIT(1))
+#define RTC_I2C_SCL_FORCE_OUT_V  0x1
+#define RTC_I2C_SCL_FORCE_OUT_S  1
+/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: 1=push pull  0=open drain*/
+#define RTC_I2C_SDA_FORCE_OUT  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_M  (BIT(0))
+#define RTC_I2C_SDA_FORCE_OUT_V  0x1
+#define RTC_I2C_SDA_FORCE_OUT_S  0
+
+#define RTC_I2C_STATUS_REG          (DR_REG_RTC_I2C_BASE + 0x0008)
+/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: scl last status*/
+#define RTC_I2C_SCL_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_STATE_LAST_M  ((RTC_I2C_SCL_STATE_LAST_V)<<(RTC_I2C_SCL_STATE_LAST_S))
+#define RTC_I2C_SCL_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_STATE_LAST_S  28
+/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
+/*description: i2c last main status*/
+#define RTC_I2C_SCL_MAIN_STATE_LAST  0x00000007
+#define RTC_I2C_SCL_MAIN_STATE_LAST_M  ((RTC_I2C_SCL_MAIN_STATE_LAST_V)<<(RTC_I2C_SCL_MAIN_STATE_LAST_S))
+#define RTC_I2C_SCL_MAIN_STATE_LAST_V  0x7
+#define RTC_I2C_SCL_MAIN_STATE_LAST_S  24
+/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
+/*description: shifter content*/
+#define RTC_I2C_SHIFT  0x000000FF
+#define RTC_I2C_SHIFT_M  ((RTC_I2C_SHIFT_V)<<(RTC_I2C_SHIFT_S))
+#define RTC_I2C_SHIFT_V  0xFF
+#define RTC_I2C_SHIFT_S  16
+/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
+/*description: which operation is working*/
+#define RTC_I2C_OP_CNT  0x00000003
+#define RTC_I2C_OP_CNT_M  ((RTC_I2C_OP_CNT_V)<<(RTC_I2C_OP_CNT_S))
+#define RTC_I2C_OP_CNT_V  0x3
+#define RTC_I2C_OP_CNT_S  6
+/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: One byte transit done*/
+#define RTC_I2C_BYTE_TRANS  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_M  (BIT(5))
+#define RTC_I2C_BYTE_TRANS_V  0x1
+#define RTC_I2C_BYTE_TRANS_S  5
+/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: slave reg sub address*/
+#define RTC_I2C_SLAVE_ADDRESSED  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_M  (BIT(4))
+#define RTC_I2C_SLAVE_ADDRESSED_V  0x1
+#define RTC_I2C_SLAVE_ADDRESSED_S  4
+/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: bus is busy*/
+#define RTC_I2C_BUS_BUSY  (BIT(3))
+#define RTC_I2C_BUS_BUSY_M  (BIT(3))
+#define RTC_I2C_BUS_BUSY_V  0x1
+#define RTC_I2C_BUS_BUSY_S  3
+/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: arbitration is lost*/
+#define RTC_I2C_ARB_LOST  (BIT(2))
+#define RTC_I2C_ARB_LOST_M  (BIT(2))
+#define RTC_I2C_ARB_LOST_V  0x1
+#define RTC_I2C_ARB_LOST_S  2
+/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: slave read or write*/
+#define RTC_I2C_SLAVE_RW  (BIT(1))
+#define RTC_I2C_SLAVE_RW_M  (BIT(1))
+#define RTC_I2C_SLAVE_RW_V  0x1
+#define RTC_I2C_SLAVE_RW_S  1
+/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: ack response*/
+#define RTC_I2C_ACK_REC  (BIT(0))
+#define RTC_I2C_ACK_REC_M  (BIT(0))
+#define RTC_I2C_ACK_REC_V  0x1
+#define RTC_I2C_ACK_REC_S  0
+
+#define RTC_I2C_TIMEOUT_REG          (DR_REG_RTC_I2C_BASE + 0x000c)
+/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
+/*description: time out threshold*/
+#define RTC_I2C_TIMEOUT  0x000FFFFF
+#define RTC_I2C_TIMEOUT_M  ((RTC_I2C_TIMEOUT_V)<<(RTC_I2C_TIMEOUT_S))
+#define RTC_I2C_TIMEOUT_V  0xFFFFF
+#define RTC_I2C_TIMEOUT_S  0
+
+#define RTC_I2C_SLAVE_ADDR_REG          (DR_REG_RTC_I2C_BASE + 0x0010)
+/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c 10bit mode enable*/
+#define RTC_I2C_ADDR_10BIT_EN  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_M  (BIT(31))
+#define RTC_I2C_ADDR_10BIT_EN_V  0x1
+#define RTC_I2C_ADDR_10BIT_EN_S  31
+/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
+/*description: slave address*/
+#define RTC_I2C_SLAVE_ADDR  0x00007FFF
+#define RTC_I2C_SLAVE_ADDR_M  ((RTC_I2C_SLAVE_ADDR_V)<<(RTC_I2C_SLAVE_ADDR_S))
+#define RTC_I2C_SLAVE_ADDR_V  0x7FFF
+#define RTC_I2C_SLAVE_ADDR_S  0
+
+#define RTC_I2C_SCL_HIGH_REG          (DR_REG_RTC_I2C_BASE + 0x0014)
+/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
+/*description: time period that scl = 1*/
+#define RTC_I2C_SCL_HIGH_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_M  ((RTC_I2C_SCL_HIGH_PERIOD_V)<<(RTC_I2C_SCL_HIGH_PERIOD_S))
+#define RTC_I2C_SCL_HIGH_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_HIGH_PERIOD_S  0
+
+#define RTC_I2C_SDA_DUTY_REG          (DR_REG_RTC_I2C_BASE + 0x0018)
+/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
+/*description: time period for SDA to toggle after SCL goes low*/
+#define RTC_I2C_SDA_DUTY_NUM  0x000FFFFF
+#define RTC_I2C_SDA_DUTY_NUM_M  ((RTC_I2C_SDA_DUTY_NUM_V)<<(RTC_I2C_SDA_DUTY_NUM_S))
+#define RTC_I2C_SDA_DUTY_NUM_V  0xFFFFF
+#define RTC_I2C_SDA_DUTY_NUM_S  0
+
+#define RTC_I2C_SCL_START_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x001c)
+/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to toggle after I2C start is triggered*/
+#define RTC_I2C_SCL_START_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_START_PERIOD_M  ((RTC_I2C_SCL_START_PERIOD_V)<<(RTC_I2C_SCL_START_PERIOD_S))
+#define RTC_I2C_SCL_START_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_START_PERIOD_S  0
+
+#define RTC_I2C_SCL_STOP_PERIOD_REG          (DR_REG_RTC_I2C_BASE + 0x0020)
+/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
+/*description: time period for SCL to stop after I2C end is triggered*/
+#define RTC_I2C_SCL_STOP_PERIOD  0x000FFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_M  ((RTC_I2C_SCL_STOP_PERIOD_V)<<(RTC_I2C_SCL_STOP_PERIOD_S))
+#define RTC_I2C_SCL_STOP_PERIOD_V  0xFFFFF
+#define RTC_I2C_SCL_STOP_PERIOD_S  0
+
+#define RTC_I2C_INT_CLR_REG          (DR_REG_RTC_I2C_BASE + 0x0024)
+/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: clear detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_CLR  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_CLR_V  0x1
+#define RTC_I2C_DETECT_START_INT_CLR_S  8
+/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: clear transit load data complete interrupt*/
+#define RTC_I2C_TX_DATA_INT_CLR  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_TX_DATA_INT_CLR_S  7
+/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: clear receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_CLR  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_CLR_V  0x1
+#define RTC_I2C_RX_DATA_INT_CLR_S  6
+/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: clear ack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_CLR  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_CLR_V  0x1
+#define RTC_I2C_ACK_ERR_INT_CLR_S  5
+/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: clear time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_CLR  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_CLR_V  0x1
+#define RTC_I2C_TIMEOUT_INT_CLR_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: clear transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: clear master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: clear arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: clear slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S  0
+
+#define RTC_I2C_INT_RAW_REG          (DR_REG_RTC_I2C_BASE + 0x0028)
+/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt raw*/
+#define RTC_I2C_DETECT_START_INT_RAW  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_RAW_V  0x1
+#define RTC_I2C_DETECT_START_INT_RAW_S  8
+/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt raw*/
+#define RTC_I2C_TX_DATA_INT_RAW  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_TX_DATA_INT_RAW_S  7
+/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt raw*/
+#define RTC_I2C_RX_DATA_INT_RAW  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_RAW_V  0x1
+#define RTC_I2C_RX_DATA_INT_RAW_S  6
+/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt raw*/
+#define RTC_I2C_ACK_ERR_INT_RAW  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_RAW_V  0x1
+#define RTC_I2C_ACK_ERR_INT_RAW_S  5
+/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt raw*/
+#define RTC_I2C_TIMEOUT_INT_RAW  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_RAW_V  0x1
+#define RTC_I2C_TIMEOUT_INT_RAW_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt raw*/
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt raw*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt raw*/
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt raw*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S  0
+
+#define RTC_I2C_INT_ST_REG          (DR_REG_RTC_I2C_BASE + 0x002c)
+/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: detect start interrupt state*/
+#define RTC_I2C_DETECT_START_INT_ST  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ST_V  0x1
+#define RTC_I2C_DETECT_START_INT_ST_S  8
+/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: transit data interrupt state*/
+#define RTC_I2C_TX_DATA_INT_ST  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ST_V  0x1
+#define RTC_I2C_TX_DATA_INT_ST_S  7
+/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: receive data interrupt state*/
+#define RTC_I2C_RX_DATA_INT_ST  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ST_V  0x1
+#define RTC_I2C_RX_DATA_INT_ST_S  6
+/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: ack error interrupt state*/
+#define RTC_I2C_ACK_ERR_INT_ST  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ST_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ST_S  5
+/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: time out interrupt state*/
+#define RTC_I2C_TIMEOUT_INT_ST  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ST_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ST_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: transit complete interrupt state*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ST  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ST_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: master transit complete interrupt state*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: arbitration lost interrupt state*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ST  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ST_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: slave transit complete interrupt state*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S  0
+
+#define RTC_I2C_INT_ENA_REG          (DR_REG_RTC_I2C_BASE + 0x0030)
+/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: enable detect start interrupt*/
+#define RTC_I2C_DETECT_START_INT_ENA  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_M  (BIT(8))
+#define RTC_I2C_DETECT_START_INT_ENA_V  0x1
+#define RTC_I2C_DETECT_START_INT_ENA_S  8
+/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: enable transit data interrupt*/
+#define RTC_I2C_TX_DATA_INT_ENA  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_M  (BIT(7))
+#define RTC_I2C_TX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_TX_DATA_INT_ENA_S  7
+/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: enable receive data interrupt*/
+#define RTC_I2C_RX_DATA_INT_ENA  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_M  (BIT(6))
+#define RTC_I2C_RX_DATA_INT_ENA_V  0x1
+#define RTC_I2C_RX_DATA_INT_ENA_S  6
+/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: enable eack error interrupt*/
+#define RTC_I2C_ACK_ERR_INT_ENA  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_M  (BIT(5))
+#define RTC_I2C_ACK_ERR_INT_ENA_V  0x1
+#define RTC_I2C_ACK_ERR_INT_ENA_S  5
+/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: enable time out interrupt*/
+#define RTC_I2C_TIMEOUT_INT_ENA  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_M  (BIT(4))
+#define RTC_I2C_TIMEOUT_INT_ENA_V  0x1
+#define RTC_I2C_TIMEOUT_INT_ENA_S  4
+/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: enable transit complete interrupt*/
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M  (BIT(3))
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V  0x1
+#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S  3
+/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: enable master transit complete interrupt*/
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M  (BIT(2))
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S  2
+/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: enable arbitration lost interrupt*/
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M  (BIT(1))
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V  0x1
+#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S  1
+/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: enable slave transit complete interrupt*/
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M  (BIT(0))
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V  0x1
+#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S  0
+
+#define RTC_I2C_DATA_REG          (DR_REG_RTC_I2C_BASE + 0x0034)
+/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: i2c done*/
+#define RTC_I2C_DONE  (BIT(31))
+#define RTC_I2C_DONE_M  (BIT(31))
+#define RTC_I2C_DONE_V  0x1
+#define RTC_I2C_DONE_S  31
+/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: data sent by slave*/
+#define RTC_I2C_SLAVE_TX_DATA  0x000000FF
+#define RTC_I2C_SLAVE_TX_DATA_M  ((RTC_I2C_SLAVE_TX_DATA_V)<<(RTC_I2C_SLAVE_TX_DATA_S))
+#define RTC_I2C_SLAVE_TX_DATA_V  0xFF
+#define RTC_I2C_SLAVE_TX_DATA_S  8
+/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: data received*/
+#define RTC_I2C_RDATA  0x000000FF
+#define RTC_I2C_RDATA_M  ((RTC_I2C_RDATA_V)<<(RTC_I2C_RDATA_S))
+#define RTC_I2C_RDATA_V  0xFF
+#define RTC_I2C_RDATA_S  0
+
+#define RTC_I2C_CMD0_REG          (DR_REG_RTC_I2C_BASE + 0x0038)
+/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command0_done*/
+#define RTC_I2C_COMMAND0_DONE  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND0_DONE_V  0x1
+#define RTC_I2C_COMMAND0_DONE_S  31
+/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command0*/
+#define RTC_I2C_COMMAND0  0x00003FFF
+#define RTC_I2C_COMMAND0_M  ((RTC_I2C_COMMAND0_V)<<(RTC_I2C_COMMAND0_S))
+#define RTC_I2C_COMMAND0_V  0x3FFF
+#define RTC_I2C_COMMAND0_S  0
+
+#define RTC_I2C_CMD1_REG          (DR_REG_RTC_I2C_BASE + 0x003c)
+/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command1_done*/
+#define RTC_I2C_COMMAND1_DONE  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND1_DONE_V  0x1
+#define RTC_I2C_COMMAND1_DONE_S  31
+/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command1*/
+#define RTC_I2C_COMMAND1  0x00003FFF
+#define RTC_I2C_COMMAND1_M  ((RTC_I2C_COMMAND1_V)<<(RTC_I2C_COMMAND1_S))
+#define RTC_I2C_COMMAND1_V  0x3FFF
+#define RTC_I2C_COMMAND1_S  0
+
+#define RTC_I2C_CMD2_REG          (DR_REG_RTC_I2C_BASE + 0x0040)
+/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command2_done*/
+#define RTC_I2C_COMMAND2_DONE  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND2_DONE_V  0x1
+#define RTC_I2C_COMMAND2_DONE_S  31
+/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
+/*description: command2*/
+#define RTC_I2C_COMMAND2  0x00003FFF
+#define RTC_I2C_COMMAND2_M  ((RTC_I2C_COMMAND2_V)<<(RTC_I2C_COMMAND2_S))
+#define RTC_I2C_COMMAND2_V  0x3FFF
+#define RTC_I2C_COMMAND2_S  0
+
+#define RTC_I2C_CMD3_REG          (DR_REG_RTC_I2C_BASE + 0x0044)
+/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command3_done*/
+#define RTC_I2C_COMMAND3_DONE  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND3_DONE_V  0x1
+#define RTC_I2C_COMMAND3_DONE_S  31
+/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command3*/
+#define RTC_I2C_COMMAND3  0x00003FFF
+#define RTC_I2C_COMMAND3_M  ((RTC_I2C_COMMAND3_V)<<(RTC_I2C_COMMAND3_S))
+#define RTC_I2C_COMMAND3_V  0x3FFF
+#define RTC_I2C_COMMAND3_S  0
+
+#define RTC_I2C_CMD4_REG          (DR_REG_RTC_I2C_BASE + 0x0048)
+/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command4_done*/
+#define RTC_I2C_COMMAND4_DONE  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND4_DONE_V  0x1
+#define RTC_I2C_COMMAND4_DONE_S  31
+/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command4*/
+#define RTC_I2C_COMMAND4  0x00003FFF
+#define RTC_I2C_COMMAND4_M  ((RTC_I2C_COMMAND4_V)<<(RTC_I2C_COMMAND4_S))
+#define RTC_I2C_COMMAND4_V  0x3FFF
+#define RTC_I2C_COMMAND4_S  0
+
+#define RTC_I2C_CMD5_REG          (DR_REG_RTC_I2C_BASE + 0x004c)
+/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command5_done*/
+#define RTC_I2C_COMMAND5_DONE  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND5_DONE_V  0x1
+#define RTC_I2C_COMMAND5_DONE_S  31
+/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command5*/
+#define RTC_I2C_COMMAND5  0x00003FFF
+#define RTC_I2C_COMMAND5_M  ((RTC_I2C_COMMAND5_V)<<(RTC_I2C_COMMAND5_S))
+#define RTC_I2C_COMMAND5_V  0x3FFF
+#define RTC_I2C_COMMAND5_S  0
+
+#define RTC_I2C_CMD6_REG          (DR_REG_RTC_I2C_BASE + 0x0050)
+/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command6_done*/
+#define RTC_I2C_COMMAND6_DONE  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND6_DONE_V  0x1
+#define RTC_I2C_COMMAND6_DONE_S  31
+/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command6*/
+#define RTC_I2C_COMMAND6  0x00003FFF
+#define RTC_I2C_COMMAND6_M  ((RTC_I2C_COMMAND6_V)<<(RTC_I2C_COMMAND6_S))
+#define RTC_I2C_COMMAND6_V  0x3FFF
+#define RTC_I2C_COMMAND6_S  0
+
+#define RTC_I2C_CMD7_REG          (DR_REG_RTC_I2C_BASE + 0x0054)
+/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command7_done*/
+#define RTC_I2C_COMMAND7_DONE  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND7_DONE_V  0x1
+#define RTC_I2C_COMMAND7_DONE_S  31
+/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
+/*description: command7*/
+#define RTC_I2C_COMMAND7  0x00003FFF
+#define RTC_I2C_COMMAND7_M  ((RTC_I2C_COMMAND7_V)<<(RTC_I2C_COMMAND7_S))
+#define RTC_I2C_COMMAND7_V  0x3FFF
+#define RTC_I2C_COMMAND7_S  0
+
+#define RTC_I2C_CMD8_REG          (DR_REG_RTC_I2C_BASE + 0x0058)
+/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command8_done*/
+#define RTC_I2C_COMMAND8_DONE  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND8_DONE_V  0x1
+#define RTC_I2C_COMMAND8_DONE_S  31
+/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command8*/
+#define RTC_I2C_COMMAND8  0x00003FFF
+#define RTC_I2C_COMMAND8_M  ((RTC_I2C_COMMAND8_V)<<(RTC_I2C_COMMAND8_S))
+#define RTC_I2C_COMMAND8_V  0x3FFF
+#define RTC_I2C_COMMAND8_S  0
+
+#define RTC_I2C_CMD9_REG          (DR_REG_RTC_I2C_BASE + 0x005c)
+/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command9_done*/
+#define RTC_I2C_COMMAND9_DONE  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND9_DONE_V  0x1
+#define RTC_I2C_COMMAND9_DONE_S  31
+/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
+/*description: command9*/
+#define RTC_I2C_COMMAND9  0x00003FFF
+#define RTC_I2C_COMMAND9_M  ((RTC_I2C_COMMAND9_V)<<(RTC_I2C_COMMAND9_S))
+#define RTC_I2C_COMMAND9_V  0x3FFF
+#define RTC_I2C_COMMAND9_S  0
+
+#define RTC_I2C_CMD10_REG          (DR_REG_RTC_I2C_BASE + 0x0060)
+/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command10_done*/
+#define RTC_I2C_COMMAND10_DONE  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND10_DONE_V  0x1
+#define RTC_I2C_COMMAND10_DONE_S  31
+/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
+/*description: command10*/
+#define RTC_I2C_COMMAND10  0x00003FFF
+#define RTC_I2C_COMMAND10_M  ((RTC_I2C_COMMAND10_V)<<(RTC_I2C_COMMAND10_S))
+#define RTC_I2C_COMMAND10_V  0x3FFF
+#define RTC_I2C_COMMAND10_S  0
+
+#define RTC_I2C_CMD11_REG          (DR_REG_RTC_I2C_BASE + 0x0064)
+/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command11_done*/
+#define RTC_I2C_COMMAND11_DONE  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND11_DONE_V  0x1
+#define RTC_I2C_COMMAND11_DONE_S  31
+/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
+/*description: command11*/
+#define RTC_I2C_COMMAND11  0x00003FFF
+#define RTC_I2C_COMMAND11_M  ((RTC_I2C_COMMAND11_V)<<(RTC_I2C_COMMAND11_S))
+#define RTC_I2C_COMMAND11_V  0x3FFF
+#define RTC_I2C_COMMAND11_S  0
+
+#define RTC_I2C_CMD12_REG          (DR_REG_RTC_I2C_BASE + 0x0068)
+/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command12_done*/
+#define RTC_I2C_COMMAND12_DONE  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND12_DONE_V  0x1
+#define RTC_I2C_COMMAND12_DONE_S  31
+/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
+/*description: command12*/
+#define RTC_I2C_COMMAND12  0x00003FFF
+#define RTC_I2C_COMMAND12_M  ((RTC_I2C_COMMAND12_V)<<(RTC_I2C_COMMAND12_S))
+#define RTC_I2C_COMMAND12_V  0x3FFF
+#define RTC_I2C_COMMAND12_S  0
+
+#define RTC_I2C_CMD13_REG          (DR_REG_RTC_I2C_BASE + 0x006c)
+/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command13_done*/
+#define RTC_I2C_COMMAND13_DONE  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND13_DONE_V  0x1
+#define RTC_I2C_COMMAND13_DONE_S  31
+/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
+/*description: command13*/
+#define RTC_I2C_COMMAND13  0x00003FFF
+#define RTC_I2C_COMMAND13_M  ((RTC_I2C_COMMAND13_V)<<(RTC_I2C_COMMAND13_S))
+#define RTC_I2C_COMMAND13_V  0x3FFF
+#define RTC_I2C_COMMAND13_S  0
+
+#define RTC_I2C_CMD14_REG          (DR_REG_RTC_I2C_BASE + 0x0070)
+/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command14_done*/
+#define RTC_I2C_COMMAND14_DONE  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND14_DONE_V  0x1
+#define RTC_I2C_COMMAND14_DONE_S  31
+/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command14*/
+#define RTC_I2C_COMMAND14  0x00003FFF
+#define RTC_I2C_COMMAND14_M  ((RTC_I2C_COMMAND14_V)<<(RTC_I2C_COMMAND14_S))
+#define RTC_I2C_COMMAND14_V  0x3FFF
+#define RTC_I2C_COMMAND14_S  0
+
+#define RTC_I2C_CMD15_REG          (DR_REG_RTC_I2C_BASE + 0x0074)
+/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: command15_done*/
+#define RTC_I2C_COMMAND15_DONE  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_M  (BIT(31))
+#define RTC_I2C_COMMAND15_DONE_V  0x1
+#define RTC_I2C_COMMAND15_DONE_S  31
+/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
+/*description: command15*/
+#define RTC_I2C_COMMAND15  0x00003FFF
+#define RTC_I2C_COMMAND15_M  ((RTC_I2C_COMMAND15_V)<<(RTC_I2C_COMMAND15_S))
+#define RTC_I2C_COMMAND15_V  0x3FFF
+#define RTC_I2C_COMMAND15_S  0
+
+#define RTC_I2C_DATE_REG          (DR_REG_RTC_I2C_BASE + 0x00FC)
+/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1711170 ; */
+/*description: */
+#define RTC_I2C_DATE  0x0FFFFFFF
+#define RTC_I2C_DATE_M  ((RTC_I2C_DATE_V)<<(RTC_I2C_DATE_S))
+#define RTC_I2C_DATE_V  0xFFFFFFF
+#define RTC_I2C_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_I2C_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h b/components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h
new file mode 100644
index 000000000..938df0c58
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc_i2c_struct.h
@@ -0,0 +1,230 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_I2C_STRUCT_H_
+#define _SOC_RTC_I2C_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t period:        20;             /*time period that scl = 0*/
+            uint32_t reserved20:    12;
+        };
+        uint32_t val;
+    } scl_low;
+    union {
+        struct {
+            uint32_t sda_force_out: 1;              /*1=push pull  0=open drain*/
+            uint32_t scl_force_out: 1;              /*1=push pull  0=open drain*/
+            uint32_t ms_mode:       1;              /*1=master  0=slave*/
+            uint32_t trans_start:   1;              /*force start*/
+            uint32_t tx_lsb_first:  1;              /*transit lsb first*/
+            uint32_t rx_lsb_first:  1;              /*receive lsb first*/
+            uint32_t reserved6:    24;
+            uint32_t i2c_reset:     1;              /*rtc i2c sw reset*/
+            uint32_t i2cclk_en:     1;              /*rtc i2c reg clk gating*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t ack_rec:             1;        /*ack response*/
+            uint32_t slave_rw:            1;        /*slave read or write*/
+            uint32_t arb_lost:            1;        /*arbitration is lost*/
+            uint32_t bus_busy:            1;        /*bus is busy*/
+            uint32_t slave_addressed:     1;        /*slave reg sub address*/
+            uint32_t byte_trans:          1;        /*One byte transit done*/
+            uint32_t op_cnt:              2;        /*which operation is working*/
+            uint32_t reserved8:           8;
+            uint32_t shift:               8;        /*shifter content*/
+            uint32_t scl_main_state_last: 3;        /*i2c last main status*/
+            uint32_t reserved27:          1;
+            uint32_t scl_state_last:      3;        /*scl last status*/
+            uint32_t reserved31:          1;
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t time_out:  20;                 /*time out threshold*/
+            uint32_t reserved20:12;
+        };
+        uint32_t val;
+    } timeout;
+    union {
+        struct {
+            uint32_t addr:         15;              /*slave address*/
+            uint32_t reserved15:   16;
+            uint32_t en_10bit:      1;              /*i2c 10bit mode enable*/
+        };
+        uint32_t val;
+    } slave_addr;
+    union {
+        struct {
+            uint32_t period:         20;            /*time period that scl = 1*/
+            uint32_t reserved20:     12;
+        };
+        uint32_t val;
+    } scl_high;
+    union {
+        struct {
+            uint32_t sda_duty_num:20;               /*time period for SDA to toggle after SCL goes low*/
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } sda_duty;
+    union {
+        struct {
+            uint32_t scl_start_period:20;           /*time period for SCL to toggle after I2C start is triggered*/
+            uint32_t reserved20:      12;
+        };
+        uint32_t val;
+    } scl_start_period;
+    union {
+        struct {
+            uint32_t scl_stop_period:20;            /*time period for SCL to stop after I2C end is triggered*/
+            uint32_t reserved20:     12;
+        };
+        uint32_t val;
+    } scl_stop_period;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*clear slave transit complete interrupt*/
+            uint32_t arbitration_lost:         1;   /*clear arbitration lost interrupt*/
+            uint32_t master_tran_comp:         1;   /*clear master transit complete interrupt*/
+            uint32_t trans_complete:           1;   /*clear transit complete interrupt*/
+            uint32_t time_out:                 1;   /*clear time out interrupt*/
+            uint32_t ack_err:                  1;   /*clear ack error interrupt*/
+            uint32_t rx_data:                  1;   /*clear receive data interrupt*/
+            uint32_t tx_data:                  1;   /*clear transit load data complete interrupt*/
+            uint32_t detect_start:             1;   /*clear detect start interrupt*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*slave transit complete interrupt raw*/
+            uint32_t arbitration_lost:         1;   /*arbitration lost interrupt raw*/
+            uint32_t master_tran_comp:         1;   /*master transit complete interrupt raw*/
+            uint32_t trans_complete:           1;   /*transit complete interrupt raw*/
+            uint32_t time_out:                 1;   /*time out interrupt raw*/
+            uint32_t ack_err:                  1;   /*ack error interrupt raw*/
+            uint32_t rx_data:                  1;   /*receive data interrupt raw*/
+            uint32_t tx_data:                  1;   /*transit data interrupt raw*/
+            uint32_t detect_start:             1;   /*detect start interrupt raw*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t slave_tran_comp:         1;    /*slave transit complete interrupt state*/
+            uint32_t arbitration_lost:        1;    /*arbitration lost interrupt state*/
+            uint32_t master_tran_comp:        1;    /*master transit complete interrupt state*/
+            uint32_t trans_complete:          1;    /*transit complete interrupt state*/
+            uint32_t time_out:                1;    /*time out interrupt state*/
+            uint32_t ack_err:                 1;    /*ack error interrupt state*/
+            uint32_t rx_data:                 1;    /*receive data interrupt state*/
+            uint32_t tx_data:                 1;    /*transit data interrupt state*/
+            uint32_t detect_start:            1;    /*detect start interrupt state*/
+            uint32_t reserved9:              23;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t slave_tran_comp:          1;   /*enable slave transit complete interrupt*/
+            uint32_t arbitration_lost:         1;   /*enable arbitration lost interrupt*/
+            uint32_t master_tran_comp:         1;   /*enable master transit complete interrupt*/
+            uint32_t trans_complete:           1;   /*enable transit complete interrupt*/
+            uint32_t time_out:                 1;   /*enable time out interrupt*/
+            uint32_t ack_err:                  1;   /*enable eack error interrupt*/
+            uint32_t rx_data:                  1;   /*enable receive data interrupt*/
+            uint32_t tx_data:                  1;   /*enable transit data interrupt*/
+            uint32_t detect_start:             1;   /*enable detect start interrupt*/
+            uint32_t reserved9:               23;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t i2c_rdata:     8;              /*data received*/
+            uint32_t slave_tx_data: 8;              /*data sent by slave*/
+            uint32_t reserved16:   15;
+            uint32_t i2c_done:      1;              /*i2c done*/
+        };
+        uint32_t val;
+    } fifo_data;
+    union {
+        struct {
+            uint32_t byte_num:      8;              /*Byte_num represent the number of data need to be send or data need to be received.*/
+            uint32_t ack_en:        1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+            uint32_t ack_exp:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+            uint32_t ack_val:       1;              /*ack_check_en  ack_exp and ack value are used to control  the ack bit.*/
+            uint32_t op_code:       3;              /*op_code is the command  0：RSTART   1：WRITE  2：READ  3：STOP . 4:END.*/
+            uint32_t reserved14:   17;
+            uint32_t done:          1;              /*command0_done*/
+        };
+        uint32_t val;
+    } command[16];
+    uint32_t reserved_78;
+    uint32_t reserved_7c;
+    uint32_t reserved_80;
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    uint32_t reserved_90;
+    uint32_t reserved_94;
+    uint32_t reserved_98;
+    uint32_t reserved_9c;
+    uint32_t reserved_a0;
+    uint32_t reserved_a4;
+    uint32_t reserved_a8;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    union {
+        struct {
+            uint32_t i2c_date:  28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_i2c_dev_t;
+extern rtc_i2c_dev_t RTC_I2C;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RTC_I2C_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/rtc_io_reg.h b/components/soc/esp32s2beta/include/soc/rtc_io_reg.h
new file mode 100644
index 000000000..c9d9b63be
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc_io_reg.h
@@ -0,0 +1,2284 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_IO_REG_H_
+#define _SOC_RTC_IO_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define RTC_GPIO_OUT_REG          (DR_REG_RTCIO_BASE + 0x0)
+/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 output data*/
+#define RTC_GPIO_OUT_DATA  0x003FFFFF
+#define RTC_GPIO_OUT_DATA_M  ((RTC_GPIO_OUT_DATA_V)<<(RTC_GPIO_OUT_DATA_S))
+#define RTC_GPIO_OUT_DATA_V  0x3FFFFF
+#define RTC_GPIO_OUT_DATA_S  10
+
+#define RTC_GPIO_OUT_W1TS_REG          (DR_REG_RTCIO_BASE + 0x10)
+/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 output data write 1 to set*/
+#define RTC_GPIO_OUT_DATA_W1TS  0x003FFFFF
+#define RTC_GPIO_OUT_DATA_W1TS_M  ((RTC_GPIO_OUT_DATA_W1TS_V)<<(RTC_GPIO_OUT_DATA_W1TS_S))
+#define RTC_GPIO_OUT_DATA_W1TS_V  0x3FFFFF
+#define RTC_GPIO_OUT_DATA_W1TS_S  10
+
+#define RTC_GPIO_OUT_W1TC_REG          (DR_REG_RTCIO_BASE + 0x20)
+/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 output data write 1 to clear*/
+#define RTC_GPIO_OUT_DATA_W1TC  0x003FFFFF
+#define RTC_GPIO_OUT_DATA_W1TC_M  ((RTC_GPIO_OUT_DATA_W1TC_V)<<(RTC_GPIO_OUT_DATA_W1TC_S))
+#define RTC_GPIO_OUT_DATA_W1TC_V  0x3FFFFF
+#define RTC_GPIO_OUT_DATA_W1TC_S  10
+
+#define RTC_GPIO_ENABLE_REG          (DR_REG_RTCIO_BASE + 0x30)
+/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 enable*/
+#define RTC_GPIO_ENABLE  0x003FFFFF
+#define RTC_GPIO_ENABLE_M  ((RTC_GPIO_ENABLE_V)<<(RTC_GPIO_ENABLE_S))
+#define RTC_GPIO_ENABLE_V  0x3FFFFF
+#define RTC_GPIO_ENABLE_S  10
+
+#define RTC_GPIO_ENABLE_W1TS_REG          (DR_REG_RTCIO_BASE + 0x40)
+/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 enable write 1 to set*/
+#define RTC_GPIO_ENABLE_W1TS  0x003FFFFF
+#define RTC_GPIO_ENABLE_W1TS_M  ((RTC_GPIO_ENABLE_W1TS_V)<<(RTC_GPIO_ENABLE_W1TS_S))
+#define RTC_GPIO_ENABLE_W1TS_V  0x3FFFFF
+#define RTC_GPIO_ENABLE_W1TS_S  10
+
+#define RTC_GPIO_ENABLE_W1TC_REG          (DR_REG_RTCIO_BASE + 0x50)
+/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 enable write 1 to clear*/
+#define RTC_GPIO_ENABLE_W1TC  0x003FFFFF
+#define RTC_GPIO_ENABLE_W1TC_M  ((RTC_GPIO_ENABLE_W1TC_V)<<(RTC_GPIO_ENABLE_W1TC_S))
+#define RTC_GPIO_ENABLE_W1TC_V  0x3FFFFF
+#define RTC_GPIO_ENABLE_W1TC_S  10
+
+#define RTC_GPIO_STATUS_REG          (DR_REG_RTCIO_BASE + 0x60)
+/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 interrupt status*/
+#define RTC_GPIO_STATUS_INT  0x003FFFFF
+#define RTC_GPIO_STATUS_INT_M  ((RTC_GPIO_STATUS_INT_V)<<(RTC_GPIO_STATUS_INT_S))
+#define RTC_GPIO_STATUS_INT_V  0x3FFFFF
+#define RTC_GPIO_STATUS_INT_S  10
+
+#define RTC_GPIO_STATUS_W1TS_REG          (DR_REG_RTCIO_BASE + 0x70)
+/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
+#define RTC_GPIO_STATUS_INT_W1TS  0x003FFFFF
+#define RTC_GPIO_STATUS_INT_W1TS_M  ((RTC_GPIO_STATUS_INT_W1TS_V)<<(RTC_GPIO_STATUS_INT_W1TS_S))
+#define RTC_GPIO_STATUS_INT_W1TS_V  0x3FFFFF
+#define RTC_GPIO_STATUS_INT_W1TS_S  10
+
+#define RTC_GPIO_STATUS_W1TC_REG          (DR_REG_RTCIO_BASE + 0x80)
+/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */
+/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
+#define RTC_GPIO_STATUS_INT_W1TC  0x003FFFFF
+#define RTC_GPIO_STATUS_INT_W1TC_M  ((RTC_GPIO_STATUS_INT_W1TC_V)<<(RTC_GPIO_STATUS_INT_W1TC_S))
+#define RTC_GPIO_STATUS_INT_W1TC_V  0x3FFFFF
+#define RTC_GPIO_STATUS_INT_W1TC_S  10
+
+#define RTC_GPIO_IN_REG          (DR_REG_RTCIO_BASE + 0x90)
+/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:10] ;default:  ; */
+/*description: RTC GPIO input data*/
+#define RTC_GPIO_IN_NEXT  0x003FFFFF
+#define RTC_GPIO_IN_NEXT_M  ((RTC_GPIO_IN_NEXT_V)<<(RTC_GPIO_IN_NEXT_S))
+#define RTC_GPIO_IN_NEXT_V  0x3FFFFF
+#define RTC_GPIO_IN_NEXT_S  10
+
+#define RTC_GPIO_PIN0_REG          (DR_REG_RTCIO_BASE + 0xa0)
+/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN0_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN0_INT_TYPE_M  ((RTC_GPIO_PIN0_INT_TYPE_V)<<(RTC_GPIO_PIN0_INT_TYPE_S))
+#define RTC_GPIO_PIN0_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN0_INT_TYPE_S  7
+/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN0_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN0_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN0_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN0_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN1_REG          (DR_REG_RTCIO_BASE + 0xb0)
+/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN1_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN1_INT_TYPE_M  ((RTC_GPIO_PIN1_INT_TYPE_V)<<(RTC_GPIO_PIN1_INT_TYPE_S))
+#define RTC_GPIO_PIN1_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN1_INT_TYPE_S  7
+/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN1_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN1_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN1_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN1_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN2_REG          (DR_REG_RTCIO_BASE + 0xc0)
+/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN2_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN2_INT_TYPE_M  ((RTC_GPIO_PIN2_INT_TYPE_V)<<(RTC_GPIO_PIN2_INT_TYPE_S))
+#define RTC_GPIO_PIN2_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN2_INT_TYPE_S  7
+/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN2_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN2_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN2_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN2_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN3_REG          (DR_REG_RTCIO_BASE + 0xd0)
+/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN3_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN3_INT_TYPE_M  ((RTC_GPIO_PIN3_INT_TYPE_V)<<(RTC_GPIO_PIN3_INT_TYPE_S))
+#define RTC_GPIO_PIN3_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN3_INT_TYPE_S  7
+/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN3_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN3_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN3_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN3_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN4_REG          (DR_REG_RTCIO_BASE + 0xe0)
+/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN4_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN4_INT_TYPE_M  ((RTC_GPIO_PIN4_INT_TYPE_V)<<(RTC_GPIO_PIN4_INT_TYPE_S))
+#define RTC_GPIO_PIN4_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN4_INT_TYPE_S  7
+/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN4_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN4_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN4_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN4_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN5_REG          (DR_REG_RTCIO_BASE + 0xf0)
+/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN5_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN5_INT_TYPE_M  ((RTC_GPIO_PIN5_INT_TYPE_V)<<(RTC_GPIO_PIN5_INT_TYPE_S))
+#define RTC_GPIO_PIN5_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN5_INT_TYPE_S  7
+/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN5_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN5_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN5_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN5_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN6_REG          (DR_REG_RTCIO_BASE + 0x100)
+/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN6_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN6_INT_TYPE_M  ((RTC_GPIO_PIN6_INT_TYPE_V)<<(RTC_GPIO_PIN6_INT_TYPE_S))
+#define RTC_GPIO_PIN6_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN6_INT_TYPE_S  7
+/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN6_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN6_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN6_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN6_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN7_REG          (DR_REG_RTCIO_BASE + 0x110)
+/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN7_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN7_INT_TYPE_M  ((RTC_GPIO_PIN7_INT_TYPE_V)<<(RTC_GPIO_PIN7_INT_TYPE_S))
+#define RTC_GPIO_PIN7_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN7_INT_TYPE_S  7
+/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN7_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN7_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN7_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN7_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN8_REG          (DR_REG_RTCIO_BASE + 0x120)
+/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN8_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN8_INT_TYPE_M  ((RTC_GPIO_PIN8_INT_TYPE_V)<<(RTC_GPIO_PIN8_INT_TYPE_S))
+#define RTC_GPIO_PIN8_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN8_INT_TYPE_S  7
+/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN8_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN8_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN8_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN8_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN9_REG          (DR_REG_RTCIO_BASE + 0x130)
+/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN9_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN9_INT_TYPE_M  ((RTC_GPIO_PIN9_INT_TYPE_V)<<(RTC_GPIO_PIN9_INT_TYPE_S))
+#define RTC_GPIO_PIN9_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN9_INT_TYPE_S  7
+/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN9_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN9_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN9_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN9_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN10_REG          (DR_REG_RTCIO_BASE + 0x140)
+/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN10_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN10_INT_TYPE_M  ((RTC_GPIO_PIN10_INT_TYPE_V)<<(RTC_GPIO_PIN10_INT_TYPE_S))
+#define RTC_GPIO_PIN10_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN10_INT_TYPE_S  7
+/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN10_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN10_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN10_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN10_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN11_REG          (DR_REG_RTCIO_BASE + 0x150)
+/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN11_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN11_INT_TYPE_M  ((RTC_GPIO_PIN11_INT_TYPE_V)<<(RTC_GPIO_PIN11_INT_TYPE_S))
+#define RTC_GPIO_PIN11_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN11_INT_TYPE_S  7
+/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN11_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN11_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN11_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN11_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN12_REG          (DR_REG_RTCIO_BASE + 0x160)
+/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN12_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN12_INT_TYPE_M  ((RTC_GPIO_PIN12_INT_TYPE_V)<<(RTC_GPIO_PIN12_INT_TYPE_S))
+#define RTC_GPIO_PIN12_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN12_INT_TYPE_S  7
+/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN12_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN12_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN12_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN12_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN13_REG          (DR_REG_RTCIO_BASE + 0x170)
+/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN13_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN13_INT_TYPE_M  ((RTC_GPIO_PIN13_INT_TYPE_V)<<(RTC_GPIO_PIN13_INT_TYPE_S))
+#define RTC_GPIO_PIN13_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN13_INT_TYPE_S  7
+/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN13_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN13_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN13_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN13_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN14_REG          (DR_REG_RTCIO_BASE + 0x180)
+/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN14_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN14_INT_TYPE_M  ((RTC_GPIO_PIN14_INT_TYPE_V)<<(RTC_GPIO_PIN14_INT_TYPE_S))
+#define RTC_GPIO_PIN14_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN14_INT_TYPE_S  7
+/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN14_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN14_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN14_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN14_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN15_REG          (DR_REG_RTCIO_BASE + 0x190)
+/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN15_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN15_INT_TYPE_M  ((RTC_GPIO_PIN15_INT_TYPE_V)<<(RTC_GPIO_PIN15_INT_TYPE_S))
+#define RTC_GPIO_PIN15_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN15_INT_TYPE_S  7
+/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN15_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN15_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN15_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN15_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN16_REG          (DR_REG_RTCIO_BASE + 0x1a0)
+/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN16_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN16_INT_TYPE_M  ((RTC_GPIO_PIN16_INT_TYPE_V)<<(RTC_GPIO_PIN16_INT_TYPE_S))
+#define RTC_GPIO_PIN16_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN16_INT_TYPE_S  7
+/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN16_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN16_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN16_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN16_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN17_REG          (DR_REG_RTCIO_BASE + 0x1b0)
+/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN17_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN17_INT_TYPE_M  ((RTC_GPIO_PIN17_INT_TYPE_V)<<(RTC_GPIO_PIN17_INT_TYPE_S))
+#define RTC_GPIO_PIN17_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN17_INT_TYPE_S  7
+/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN17_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN17_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN17_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN17_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN18_REG          (DR_REG_RTCIO_BASE + 0x1c0)
+/* RTC_GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN18_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN18_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN18_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN18_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN18_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN18_INT_TYPE_M  ((RTC_GPIO_PIN18_INT_TYPE_V)<<(RTC_GPIO_PIN18_INT_TYPE_S))
+#define RTC_GPIO_PIN18_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN18_INT_TYPE_S  7
+/* RTC_GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN18_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN18_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN18_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN18_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN19_REG          (DR_REG_RTCIO_BASE + 0x1d0)
+/* RTC_GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN19_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN19_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN19_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN19_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN19_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN19_INT_TYPE_M  ((RTC_GPIO_PIN19_INT_TYPE_V)<<(RTC_GPIO_PIN19_INT_TYPE_S))
+#define RTC_GPIO_PIN19_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN19_INT_TYPE_S  7
+/* RTC_GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN19_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN19_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN19_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN19_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN20_REG          (DR_REG_RTCIO_BASE + 0x1e0)
+/* RTC_GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN20_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN20_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN20_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN20_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN20_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN20_INT_TYPE_M  ((RTC_GPIO_PIN20_INT_TYPE_V)<<(RTC_GPIO_PIN20_INT_TYPE_S))
+#define RTC_GPIO_PIN20_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN20_INT_TYPE_S  7
+/* RTC_GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN20_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN20_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN20_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN20_PAD_DRIVER_S  2
+
+#define RTC_GPIO_PIN21_REG          (DR_REG_RTCIO_BASE + 0x1f0)
+/* RTC_GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */
+/*description: RTC GPIO wakeup enable bit*/
+#define RTC_GPIO_PIN21_WAKEUP_ENABLE  (BIT(10))
+#define RTC_GPIO_PIN21_WAKEUP_ENABLE_M  (BIT(10))
+#define RTC_GPIO_PIN21_WAKEUP_ENABLE_V  0x1
+#define RTC_GPIO_PIN21_WAKEUP_ENABLE_S  10
+/* RTC_GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */
+/*description: if set to 0: GPIO interrupt disable   if set to 1: rising edge
+ trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+#define RTC_GPIO_PIN21_INT_TYPE  0x00000007
+#define RTC_GPIO_PIN21_INT_TYPE_M  ((RTC_GPIO_PIN21_INT_TYPE_V)<<(RTC_GPIO_PIN21_INT_TYPE_S))
+#define RTC_GPIO_PIN21_INT_TYPE_V  0x7
+#define RTC_GPIO_PIN21_INT_TYPE_S  7
+/* RTC_GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */
+/*description: if set to 0: normal output  if set to 1: open drain*/
+#define RTC_GPIO_PIN21_PAD_DRIVER  (BIT(2))
+#define RTC_GPIO_PIN21_PAD_DRIVER_M  (BIT(2))
+#define RTC_GPIO_PIN21_PAD_DRIVER_V  0x1
+#define RTC_GPIO_PIN21_PAD_DRIVER_S  2
+
+#define RTC_IO_RTC_DEBUG_SEL_REG          (DR_REG_RTCIO_BASE + 0x200)
+/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_12M_NO_GATING  (BIT(25))
+#define RTC_IO_DEBUG_12M_NO_GATING_M  (BIT(25))
+#define RTC_IO_DEBUG_12M_NO_GATING_V  0x1
+#define RTC_IO_DEBUG_12M_NO_GATING_S  25
+/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL4  0x0000001F
+#define RTC_IO_DEBUG_SEL4_M  ((RTC_IO_DEBUG_SEL4_V)<<(RTC_IO_DEBUG_SEL4_S))
+#define RTC_IO_DEBUG_SEL4_V  0x1F
+#define RTC_IO_DEBUG_SEL4_S  20
+/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL3  0x0000001F
+#define RTC_IO_DEBUG_SEL3_M  ((RTC_IO_DEBUG_SEL3_V)<<(RTC_IO_DEBUG_SEL3_S))
+#define RTC_IO_DEBUG_SEL3_V  0x1F
+#define RTC_IO_DEBUG_SEL3_S  15
+/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL2  0x0000001F
+#define RTC_IO_DEBUG_SEL2_M  ((RTC_IO_DEBUG_SEL2_V)<<(RTC_IO_DEBUG_SEL2_S))
+#define RTC_IO_DEBUG_SEL2_V  0x1F
+#define RTC_IO_DEBUG_SEL2_S  10
+/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL1  0x0000001F
+#define RTC_IO_DEBUG_SEL1_M  ((RTC_IO_DEBUG_SEL1_V)<<(RTC_IO_DEBUG_SEL1_S))
+#define RTC_IO_DEBUG_SEL1_V  0x1F
+#define RTC_IO_DEBUG_SEL1_S  5
+/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_DEBUG_SEL0  0x0000001F
+#define RTC_IO_DEBUG_SEL0_M  ((RTC_IO_DEBUG_SEL0_V)<<(RTC_IO_DEBUG_SEL0_S))
+#define RTC_IO_DEBUG_SEL0_V  0x1F
+#define RTC_IO_DEBUG_SEL0_S  0
+
+#define RTC_IO_TOUCH_PAD0_REG          (DR_REG_RTCIO_BASE + 0x210)
+/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD0_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD0_DRV_M  ((RTC_IO_TOUCH_PAD0_DRV_V)<<(RTC_IO_TOUCH_PAD0_DRV_S))
+#define RTC_IO_TOUCH_PAD0_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD0_DRV_S  29
+/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD0_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD0_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD0_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD0_RDE_S  28
+/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD0_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD0_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD0_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD0_RUE_S  27
+/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD0_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD0_DAC_M  ((RTC_IO_TOUCH_PAD0_DAC_V)<<(RTC_IO_TOUCH_PAD0_DAC_S))
+#define RTC_IO_TOUCH_PAD0_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD0_DAC_S  23
+/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD0_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD0_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD0_START_V  0x1
+#define RTC_IO_TOUCH_PAD0_START_S  22
+/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD0_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD0_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD0_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD0_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD0_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD0_XPD_S  20
+/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD0_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD0_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD0_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_M  ((RTC_IO_TOUCH_PAD0_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD0_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD0_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD0_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD0_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD0_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD0_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD0_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD0_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD0_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD0_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD0_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD0_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD0_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD0_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD0_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD0_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD1_REG          (DR_REG_RTCIO_BASE + 0x220)
+/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD1_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD1_DRV_M  ((RTC_IO_TOUCH_PAD1_DRV_V)<<(RTC_IO_TOUCH_PAD1_DRV_S))
+#define RTC_IO_TOUCH_PAD1_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD1_DRV_S  29
+/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD1_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD1_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD1_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD1_RDE_S  28
+/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD1_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD1_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD1_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD1_RUE_S  27
+/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD1_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD1_DAC_M  ((RTC_IO_TOUCH_PAD1_DAC_V)<<(RTC_IO_TOUCH_PAD1_DAC_S))
+#define RTC_IO_TOUCH_PAD1_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD1_DAC_S  23
+/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD1_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD1_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD1_START_V  0x1
+#define RTC_IO_TOUCH_PAD1_START_S  22
+/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD1_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD1_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD1_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD1_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD1_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD1_XPD_S  20
+/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD1_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD1_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD1_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_M  ((RTC_IO_TOUCH_PAD1_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD1_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD1_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD1_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD1_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD1_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD1_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD1_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD1_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD1_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD1_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD1_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD1_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD1_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD1_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD1_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD1_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD2_REG          (DR_REG_RTCIO_BASE + 0x230)
+/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD2_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD2_DRV_M  ((RTC_IO_TOUCH_PAD2_DRV_V)<<(RTC_IO_TOUCH_PAD2_DRV_S))
+#define RTC_IO_TOUCH_PAD2_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD2_DRV_S  29
+/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD2_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD2_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD2_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD2_RDE_S  28
+/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD2_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD2_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD2_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD2_RUE_S  27
+/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD2_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD2_DAC_M  ((RTC_IO_TOUCH_PAD2_DAC_V)<<(RTC_IO_TOUCH_PAD2_DAC_S))
+#define RTC_IO_TOUCH_PAD2_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD2_DAC_S  23
+/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD2_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD2_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD2_START_V  0x1
+#define RTC_IO_TOUCH_PAD2_START_S  22
+/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD2_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD2_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD2_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD2_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD2_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD2_XPD_S  20
+/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD2_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD2_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD2_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_M  ((RTC_IO_TOUCH_PAD2_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD2_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD2_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD2_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD2_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD2_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD2_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD2_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD2_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD2_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD2_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD2_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD2_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD2_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD2_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD2_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD2_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD3_REG          (DR_REG_RTCIO_BASE + 0x240)
+/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD3_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD3_DRV_M  ((RTC_IO_TOUCH_PAD3_DRV_V)<<(RTC_IO_TOUCH_PAD3_DRV_S))
+#define RTC_IO_TOUCH_PAD3_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD3_DRV_S  29
+/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD3_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD3_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD3_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD3_RDE_S  28
+/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD3_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD3_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD3_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD3_RUE_S  27
+/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD3_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD3_DAC_M  ((RTC_IO_TOUCH_PAD3_DAC_V)<<(RTC_IO_TOUCH_PAD3_DAC_S))
+#define RTC_IO_TOUCH_PAD3_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD3_DAC_S  23
+/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD3_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD3_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD3_START_V  0x1
+#define RTC_IO_TOUCH_PAD3_START_S  22
+/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD3_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD3_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD3_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD3_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD3_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD3_XPD_S  20
+/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD3_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD3_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD3_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_M  ((RTC_IO_TOUCH_PAD3_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD3_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD3_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD3_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD3_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD3_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD3_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD3_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD3_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD3_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD3_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD3_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD3_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD3_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD3_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD3_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD3_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD4_REG          (DR_REG_RTCIO_BASE + 0x250)
+/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD4_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD4_DRV_M  ((RTC_IO_TOUCH_PAD4_DRV_V)<<(RTC_IO_TOUCH_PAD4_DRV_S))
+#define RTC_IO_TOUCH_PAD4_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD4_DRV_S  29
+/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD4_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD4_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD4_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD4_RDE_S  28
+/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD4_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD4_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD4_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD4_RUE_S  27
+/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD4_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD4_DAC_M  ((RTC_IO_TOUCH_PAD4_DAC_V)<<(RTC_IO_TOUCH_PAD4_DAC_S))
+#define RTC_IO_TOUCH_PAD4_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD4_DAC_S  23
+/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD4_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD4_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD4_START_V  0x1
+#define RTC_IO_TOUCH_PAD4_START_S  22
+/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD4_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD4_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD4_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD4_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD4_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD4_XPD_S  20
+/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD4_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD4_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD4_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_M  ((RTC_IO_TOUCH_PAD4_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD4_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD4_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD4_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD4_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD4_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD4_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD4_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD4_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD4_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD4_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD4_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD4_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD4_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD4_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD4_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD4_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD5_REG          (DR_REG_RTCIO_BASE + 0x260)
+/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD5_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD5_DRV_M  ((RTC_IO_TOUCH_PAD5_DRV_V)<<(RTC_IO_TOUCH_PAD5_DRV_S))
+#define RTC_IO_TOUCH_PAD5_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD5_DRV_S  29
+/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD5_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD5_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD5_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD5_RDE_S  28
+/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD5_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD5_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD5_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD5_RUE_S  27
+/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD5_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD5_DAC_M  ((RTC_IO_TOUCH_PAD5_DAC_V)<<(RTC_IO_TOUCH_PAD5_DAC_S))
+#define RTC_IO_TOUCH_PAD5_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD5_DAC_S  23
+/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD5_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD5_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD5_START_V  0x1
+#define RTC_IO_TOUCH_PAD5_START_S  22
+/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD5_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD5_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD5_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD5_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD5_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD5_XPD_S  20
+/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD5_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD5_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD5_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_M  ((RTC_IO_TOUCH_PAD5_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD5_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD5_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD5_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD5_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD5_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD5_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD5_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD5_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD5_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD5_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD5_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD5_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD5_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD5_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD5_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD5_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD6_REG          (DR_REG_RTCIO_BASE + 0x270)
+/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD6_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD6_DRV_M  ((RTC_IO_TOUCH_PAD6_DRV_V)<<(RTC_IO_TOUCH_PAD6_DRV_S))
+#define RTC_IO_TOUCH_PAD6_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD6_DRV_S  29
+/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD6_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD6_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD6_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD6_RDE_S  28
+/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD6_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD6_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD6_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD6_RUE_S  27
+/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD6_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD6_DAC_M  ((RTC_IO_TOUCH_PAD6_DAC_V)<<(RTC_IO_TOUCH_PAD6_DAC_S))
+#define RTC_IO_TOUCH_PAD6_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD6_DAC_S  23
+/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD6_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD6_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD6_START_V  0x1
+#define RTC_IO_TOUCH_PAD6_START_S  22
+/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD6_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD6_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD6_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD6_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD6_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD6_XPD_S  20
+/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD6_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD6_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD6_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_M  ((RTC_IO_TOUCH_PAD6_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD6_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD6_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD6_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD6_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD6_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD6_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD6_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD6_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD6_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD6_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD6_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD6_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD6_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD6_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD6_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD6_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD7_REG          (DR_REG_RTCIO_BASE + 0x280)
+/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD7_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD7_DRV_M  ((RTC_IO_TOUCH_PAD7_DRV_V)<<(RTC_IO_TOUCH_PAD7_DRV_S))
+#define RTC_IO_TOUCH_PAD7_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD7_DRV_S  29
+/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD7_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD7_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD7_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD7_RDE_S  28
+/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD7_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD7_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD7_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD7_RUE_S  27
+/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD7_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD7_DAC_M  ((RTC_IO_TOUCH_PAD7_DAC_V)<<(RTC_IO_TOUCH_PAD7_DAC_S))
+#define RTC_IO_TOUCH_PAD7_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD7_DAC_S  23
+/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD7_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD7_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD7_START_V  0x1
+#define RTC_IO_TOUCH_PAD7_START_S  22
+/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD7_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD7_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD7_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD7_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD7_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD7_XPD_S  20
+/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD7_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD7_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD7_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_M  ((RTC_IO_TOUCH_PAD7_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD7_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD7_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD7_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD7_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD7_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD7_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD7_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD7_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD7_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD7_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD7_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD7_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD7_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD7_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD7_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD7_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD8_REG          (DR_REG_RTCIO_BASE + 0x290)
+/* RTC_IO_TOUCH_PAD8_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD8_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD8_DRV_M  ((RTC_IO_TOUCH_PAD8_DRV_V)<<(RTC_IO_TOUCH_PAD8_DRV_S))
+#define RTC_IO_TOUCH_PAD8_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD8_DRV_S  29
+/* RTC_IO_TOUCH_PAD8_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD8_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD8_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD8_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD8_RDE_S  28
+/* RTC_IO_TOUCH_PAD8_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD8_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD8_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD8_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD8_RUE_S  27
+/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD8_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD8_DAC_M  ((RTC_IO_TOUCH_PAD8_DAC_V)<<(RTC_IO_TOUCH_PAD8_DAC_S))
+#define RTC_IO_TOUCH_PAD8_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD8_DAC_S  23
+/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD8_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD8_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD8_START_V  0x1
+#define RTC_IO_TOUCH_PAD8_START_S  22
+/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD8_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD8_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD8_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD8_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD8_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD8_XPD_S  20
+/* RTC_IO_TOUCH_PAD8_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD8_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD8_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD8_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD8_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD8_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD8_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD8_FUN_SEL_M  ((RTC_IO_TOUCH_PAD8_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD8_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD8_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD8_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD8_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD8_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD8_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD8_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD8_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD8_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD8_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD8_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD8_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD8_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD8_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD8_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD8_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD8_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD8_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD8_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD8_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD8_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD8_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD8_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD9_REG          (DR_REG_RTCIO_BASE + 0x2a0)
+/* RTC_IO_TOUCH_PAD9_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD9_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD9_DRV_M  ((RTC_IO_TOUCH_PAD9_DRV_V)<<(RTC_IO_TOUCH_PAD9_DRV_S))
+#define RTC_IO_TOUCH_PAD9_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD9_DRV_S  29
+/* RTC_IO_TOUCH_PAD9_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD9_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD9_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD9_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD9_RDE_S  28
+/* RTC_IO_TOUCH_PAD9_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD9_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD9_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD9_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD9_RUE_S  27
+/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD9_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD9_DAC_M  ((RTC_IO_TOUCH_PAD9_DAC_V)<<(RTC_IO_TOUCH_PAD9_DAC_S))
+#define RTC_IO_TOUCH_PAD9_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD9_DAC_S  23
+/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD9_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD9_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD9_START_V  0x1
+#define RTC_IO_TOUCH_PAD9_START_S  22
+/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD9_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD9_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD9_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD9_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD9_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD9_XPD_S  20
+/* RTC_IO_TOUCH_PAD9_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD9_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD9_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD9_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD9_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD9_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD9_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD9_FUN_SEL_M  ((RTC_IO_TOUCH_PAD9_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD9_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD9_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD9_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD9_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD9_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD9_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD9_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD9_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD9_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD9_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD9_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD9_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD9_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD9_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD9_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD9_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD9_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD9_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD9_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD9_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD9_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD9_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD9_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD10_REG          (DR_REG_RTCIO_BASE + 0x2b0)
+/* RTC_IO_TOUCH_PAD10_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD10_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD10_DRV_M  ((RTC_IO_TOUCH_PAD10_DRV_V)<<(RTC_IO_TOUCH_PAD10_DRV_S))
+#define RTC_IO_TOUCH_PAD10_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD10_DRV_S  29
+/* RTC_IO_TOUCH_PAD10_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD10_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD10_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD10_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD10_RDE_S  28
+/* RTC_IO_TOUCH_PAD10_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD10_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD10_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD10_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD10_RUE_S  27
+/* RTC_IO_TOUCH_PAD10_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD10_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD10_DAC_M  ((RTC_IO_TOUCH_PAD10_DAC_V)<<(RTC_IO_TOUCH_PAD10_DAC_S))
+#define RTC_IO_TOUCH_PAD10_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD10_DAC_S  23
+/* RTC_IO_TOUCH_PAD10_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD10_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD10_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD10_START_V  0x1
+#define RTC_IO_TOUCH_PAD10_START_S  22
+/* RTC_IO_TOUCH_PAD10_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD10_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD10_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD10_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD10_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD10_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD10_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD10_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD10_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD10_XPD_S  20
+/* RTC_IO_TOUCH_PAD10_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD10_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD10_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD10_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD10_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD10_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD10_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD10_FUN_SEL_M  ((RTC_IO_TOUCH_PAD10_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD10_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD10_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD10_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD10_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD10_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD10_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD10_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD10_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD10_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD10_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD10_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD10_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD10_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD10_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD10_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD10_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD10_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD10_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD10_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD10_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD10_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD10_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD10_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD11_REG          (DR_REG_RTCIO_BASE + 0x2c0)
+/* RTC_IO_TOUCH_PAD11_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD11_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD11_DRV_M  ((RTC_IO_TOUCH_PAD11_DRV_V)<<(RTC_IO_TOUCH_PAD11_DRV_S))
+#define RTC_IO_TOUCH_PAD11_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD11_DRV_S  29
+/* RTC_IO_TOUCH_PAD11_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD11_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD11_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD11_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD11_RDE_S  28
+/* RTC_IO_TOUCH_PAD11_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD11_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD11_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD11_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD11_RUE_S  27
+/* RTC_IO_TOUCH_PAD11_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD11_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD11_DAC_M  ((RTC_IO_TOUCH_PAD11_DAC_V)<<(RTC_IO_TOUCH_PAD11_DAC_S))
+#define RTC_IO_TOUCH_PAD11_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD11_DAC_S  23
+/* RTC_IO_TOUCH_PAD11_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD11_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD11_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD11_START_V  0x1
+#define RTC_IO_TOUCH_PAD11_START_S  22
+/* RTC_IO_TOUCH_PAD11_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD11_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD11_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD11_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD11_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD11_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD11_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD11_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD11_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD11_XPD_S  20
+/* RTC_IO_TOUCH_PAD11_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD11_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD11_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD11_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD11_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD11_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD11_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD11_FUN_SEL_M  ((RTC_IO_TOUCH_PAD11_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD11_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD11_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD11_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD11_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD11_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD11_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD11_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD11_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD11_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD11_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD11_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD11_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD11_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD11_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD11_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD11_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD11_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD11_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD11_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD11_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD11_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD11_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD11_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD12_REG          (DR_REG_RTCIO_BASE + 0x2d0)
+/* RTC_IO_TOUCH_PAD12_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD12_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD12_DRV_M  ((RTC_IO_TOUCH_PAD12_DRV_V)<<(RTC_IO_TOUCH_PAD12_DRV_S))
+#define RTC_IO_TOUCH_PAD12_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD12_DRV_S  29
+/* RTC_IO_TOUCH_PAD12_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD12_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD12_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD12_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD12_RDE_S  28
+/* RTC_IO_TOUCH_PAD12_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD12_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD12_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD12_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD12_RUE_S  27
+/* RTC_IO_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD12_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD12_DAC_M  ((RTC_IO_TOUCH_PAD12_DAC_V)<<(RTC_IO_TOUCH_PAD12_DAC_S))
+#define RTC_IO_TOUCH_PAD12_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD12_DAC_S  23
+/* RTC_IO_TOUCH_PAD12_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD12_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD12_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD12_START_V  0x1
+#define RTC_IO_TOUCH_PAD12_START_S  22
+/* RTC_IO_TOUCH_PAD12_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD12_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD12_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD12_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD12_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD12_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD12_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD12_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD12_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD12_XPD_S  20
+/* RTC_IO_TOUCH_PAD12_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD12_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD12_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD12_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD12_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD12_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD12_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD12_FUN_SEL_M  ((RTC_IO_TOUCH_PAD12_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD12_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD12_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD12_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD12_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD12_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD12_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD12_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD12_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD12_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD12_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD12_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD12_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD12_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD12_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD12_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD12_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD12_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD12_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD12_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD12_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD12_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD12_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD12_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD13_REG          (DR_REG_RTCIO_BASE + 0x2e0)
+/* RTC_IO_TOUCH_PAD13_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD13_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD13_DRV_M  ((RTC_IO_TOUCH_PAD13_DRV_V)<<(RTC_IO_TOUCH_PAD13_DRV_S))
+#define RTC_IO_TOUCH_PAD13_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD13_DRV_S  29
+/* RTC_IO_TOUCH_PAD13_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD13_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD13_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD13_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD13_RDE_S  28
+/* RTC_IO_TOUCH_PAD13_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD13_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD13_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD13_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD13_RUE_S  27
+/* RTC_IO_TOUCH_PAD13_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD13_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD13_DAC_M  ((RTC_IO_TOUCH_PAD13_DAC_V)<<(RTC_IO_TOUCH_PAD13_DAC_S))
+#define RTC_IO_TOUCH_PAD13_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD13_DAC_S  23
+/* RTC_IO_TOUCH_PAD13_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD13_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD13_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD13_START_V  0x1
+#define RTC_IO_TOUCH_PAD13_START_S  22
+/* RTC_IO_TOUCH_PAD13_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD13_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD13_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD13_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD13_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD13_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD13_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD13_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD13_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD13_XPD_S  20
+/* RTC_IO_TOUCH_PAD13_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD13_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD13_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD13_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD13_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD13_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD13_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD13_FUN_SEL_M  ((RTC_IO_TOUCH_PAD13_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD13_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD13_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD13_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD13_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD13_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD13_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD13_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD13_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD13_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD13_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD13_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD13_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD13_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD13_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD13_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD13_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD13_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD13_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD13_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD13_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD13_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD13_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD13_FUN_IE_S  13
+
+#define RTC_IO_TOUCH_PAD14_REG          (DR_REG_RTCIO_BASE + 0x2f0)
+/* RTC_IO_TOUCH_PAD14_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_TOUCH_PAD14_DRV  0x00000003
+#define RTC_IO_TOUCH_PAD14_DRV_M  ((RTC_IO_TOUCH_PAD14_DRV_V)<<(RTC_IO_TOUCH_PAD14_DRV_S))
+#define RTC_IO_TOUCH_PAD14_DRV_V  0x3
+#define RTC_IO_TOUCH_PAD14_DRV_S  29
+/* RTC_IO_TOUCH_PAD14_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_TOUCH_PAD14_RDE  (BIT(28))
+#define RTC_IO_TOUCH_PAD14_RDE_M  (BIT(28))
+#define RTC_IO_TOUCH_PAD14_RDE_V  0x1
+#define RTC_IO_TOUCH_PAD14_RDE_S  28
+/* RTC_IO_TOUCH_PAD14_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_TOUCH_PAD14_RUE  (BIT(27))
+#define RTC_IO_TOUCH_PAD14_RUE_M  (BIT(27))
+#define RTC_IO_TOUCH_PAD14_RUE_V  0x1
+#define RTC_IO_TOUCH_PAD14_RUE_S  27
+/* RTC_IO_TOUCH_PAD14_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */
+/*description: TOUCH_DAC*/
+#define RTC_IO_TOUCH_PAD14_DAC  0x00000007
+#define RTC_IO_TOUCH_PAD14_DAC_M  ((RTC_IO_TOUCH_PAD14_DAC_V)<<(RTC_IO_TOUCH_PAD14_DAC_S))
+#define RTC_IO_TOUCH_PAD14_DAC_V  0x7
+#define RTC_IO_TOUCH_PAD14_DAC_S  23
+/* RTC_IO_TOUCH_PAD14_START : R/W ;bitpos:[22] ;default: 1'd0 ; */
+/*description: TOUCH_START*/
+#define RTC_IO_TOUCH_PAD14_START  (BIT(22))
+#define RTC_IO_TOUCH_PAD14_START_M  (BIT(22))
+#define RTC_IO_TOUCH_PAD14_START_V  0x1
+#define RTC_IO_TOUCH_PAD14_START_S  22
+/* RTC_IO_TOUCH_PAD14_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */
+/*description: TOUCH_TIE_OPT*/
+#define RTC_IO_TOUCH_PAD14_TIE_OPT  (BIT(21))
+#define RTC_IO_TOUCH_PAD14_TIE_OPT_M  (BIT(21))
+#define RTC_IO_TOUCH_PAD14_TIE_OPT_V  0x1
+#define RTC_IO_TOUCH_PAD14_TIE_OPT_S  21
+/* RTC_IO_TOUCH_PAD14_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: TOUCH_XPD*/
+#define RTC_IO_TOUCH_PAD14_XPD  (BIT(20))
+#define RTC_IO_TOUCH_PAD14_XPD_M  (BIT(20))
+#define RTC_IO_TOUCH_PAD14_XPD_V  0x1
+#define RTC_IO_TOUCH_PAD14_XPD_S  20
+/* RTC_IO_TOUCH_PAD14_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_TOUCH_PAD14_MUX_SEL  (BIT(19))
+#define RTC_IO_TOUCH_PAD14_MUX_SEL_M  (BIT(19))
+#define RTC_IO_TOUCH_PAD14_MUX_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD14_MUX_SEL_S  19
+/* RTC_IO_TOUCH_PAD14_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_TOUCH_PAD14_FUN_SEL  0x00000003
+#define RTC_IO_TOUCH_PAD14_FUN_SEL_M  ((RTC_IO_TOUCH_PAD14_FUN_SEL_V)<<(RTC_IO_TOUCH_PAD14_FUN_SEL_S))
+#define RTC_IO_TOUCH_PAD14_FUN_SEL_V  0x3
+#define RTC_IO_TOUCH_PAD14_FUN_SEL_S  17
+/* RTC_IO_TOUCH_PAD14_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_TOUCH_PAD14_SLP_SEL  (BIT(16))
+#define RTC_IO_TOUCH_PAD14_SLP_SEL_M  (BIT(16))
+#define RTC_IO_TOUCH_PAD14_SLP_SEL_V  0x1
+#define RTC_IO_TOUCH_PAD14_SLP_SEL_S  16
+/* RTC_IO_TOUCH_PAD14_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD14_SLP_IE  (BIT(15))
+#define RTC_IO_TOUCH_PAD14_SLP_IE_M  (BIT(15))
+#define RTC_IO_TOUCH_PAD14_SLP_IE_V  0x1
+#define RTC_IO_TOUCH_PAD14_SLP_IE_S  15
+/* RTC_IO_TOUCH_PAD14_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_TOUCH_PAD14_SLP_OE  (BIT(14))
+#define RTC_IO_TOUCH_PAD14_SLP_OE_M  (BIT(14))
+#define RTC_IO_TOUCH_PAD14_SLP_OE_V  0x1
+#define RTC_IO_TOUCH_PAD14_SLP_OE_S  14
+/* RTC_IO_TOUCH_PAD14_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_TOUCH_PAD14_FUN_IE  (BIT(13))
+#define RTC_IO_TOUCH_PAD14_FUN_IE_M  (BIT(13))
+#define RTC_IO_TOUCH_PAD14_FUN_IE_V  0x1
+#define RTC_IO_TOUCH_PAD14_FUN_IE_S  13
+
+#define RTC_IO_XTAL_32P_PAD_REG          (DR_REG_RTCIO_BASE + 0x300)
+/* RTC_IO_X32P_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_X32P_DRV  0x00000003
+#define RTC_IO_X32P_DRV_M  ((RTC_IO_X32P_DRV_V)<<(RTC_IO_X32P_DRV_S))
+#define RTC_IO_X32P_DRV_V  0x3
+#define RTC_IO_X32P_DRV_S  29
+/* RTC_IO_X32P_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_X32P_RDE  (BIT(28))
+#define RTC_IO_X32P_RDE_M  (BIT(28))
+#define RTC_IO_X32P_RDE_V  0x1
+#define RTC_IO_X32P_RDE_S  28
+/* RTC_IO_X32P_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_X32P_RUE  (BIT(27))
+#define RTC_IO_X32P_RUE_M  (BIT(27))
+#define RTC_IO_X32P_RUE_V  0x1
+#define RTC_IO_X32P_RUE_S  27
+/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_X32P_MUX_SEL  (BIT(19))
+#define RTC_IO_X32P_MUX_SEL_M  (BIT(19))
+#define RTC_IO_X32P_MUX_SEL_V  0x1
+#define RTC_IO_X32P_MUX_SEL_S  19
+/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_X32P_FUN_SEL  0x00000003
+#define RTC_IO_X32P_FUN_SEL_M  ((RTC_IO_X32P_FUN_SEL_V)<<(RTC_IO_X32P_FUN_SEL_S))
+#define RTC_IO_X32P_FUN_SEL_V  0x3
+#define RTC_IO_X32P_FUN_SEL_S  17
+/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_X32P_SLP_SEL  (BIT(16))
+#define RTC_IO_X32P_SLP_SEL_M  (BIT(16))
+#define RTC_IO_X32P_SLP_SEL_V  0x1
+#define RTC_IO_X32P_SLP_SEL_S  16
+/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_X32P_SLP_IE  (BIT(15))
+#define RTC_IO_X32P_SLP_IE_M  (BIT(15))
+#define RTC_IO_X32P_SLP_IE_V  0x1
+#define RTC_IO_X32P_SLP_IE_S  15
+/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_X32P_SLP_OE  (BIT(14))
+#define RTC_IO_X32P_SLP_OE_M  (BIT(14))
+#define RTC_IO_X32P_SLP_OE_V  0x1
+#define RTC_IO_X32P_SLP_OE_S  14
+/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_X32P_FUN_IE  (BIT(13))
+#define RTC_IO_X32P_FUN_IE_M  (BIT(13))
+#define RTC_IO_X32P_FUN_IE_V  0x1
+#define RTC_IO_X32P_FUN_IE_S  13
+
+#define RTC_IO_XTAL_32N_PAD_REG          (DR_REG_RTCIO_BASE + 0x310)
+/* RTC_IO_X32N_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_X32N_DRV  0x00000003
+#define RTC_IO_X32N_DRV_M  ((RTC_IO_X32N_DRV_V)<<(RTC_IO_X32N_DRV_S))
+#define RTC_IO_X32N_DRV_V  0x3
+#define RTC_IO_X32N_DRV_S  29
+/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: RDE*/
+#define RTC_IO_X32N_RDE  (BIT(28))
+#define RTC_IO_X32N_RDE_M  (BIT(28))
+#define RTC_IO_X32N_RDE_V  0x1
+#define RTC_IO_X32N_RDE_S  28
+/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_X32N_RUE  (BIT(27))
+#define RTC_IO_X32N_RUE_M  (BIT(27))
+#define RTC_IO_X32N_RUE_V  0x1
+#define RTC_IO_X32N_RUE_S  27
+/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_X32N_MUX_SEL  (BIT(19))
+#define RTC_IO_X32N_MUX_SEL_M  (BIT(19))
+#define RTC_IO_X32N_MUX_SEL_V  0x1
+#define RTC_IO_X32N_MUX_SEL_S  19
+/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_X32N_FUN_SEL  0x00000003
+#define RTC_IO_X32N_FUN_SEL_M  ((RTC_IO_X32N_FUN_SEL_V)<<(RTC_IO_X32N_FUN_SEL_S))
+#define RTC_IO_X32N_FUN_SEL_V  0x3
+#define RTC_IO_X32N_FUN_SEL_S  17
+/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_X32N_SLP_SEL  (BIT(16))
+#define RTC_IO_X32N_SLP_SEL_M  (BIT(16))
+#define RTC_IO_X32N_SLP_SEL_V  0x1
+#define RTC_IO_X32N_SLP_SEL_S  16
+/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_X32N_SLP_IE  (BIT(15))
+#define RTC_IO_X32N_SLP_IE_M  (BIT(15))
+#define RTC_IO_X32N_SLP_IE_V  0x1
+#define RTC_IO_X32N_SLP_IE_S  15
+/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_X32N_SLP_OE  (BIT(14))
+#define RTC_IO_X32N_SLP_OE_M  (BIT(14))
+#define RTC_IO_X32N_SLP_OE_V  0x1
+#define RTC_IO_X32N_SLP_OE_S  14
+/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_X32N_FUN_IE  (BIT(13))
+#define RTC_IO_X32N_FUN_IE_M  (BIT(13))
+#define RTC_IO_X32N_FUN_IE_V  0x1
+#define RTC_IO_X32N_FUN_IE_S  13
+
+#define RTC_IO_PAD_DAC1_REG          (DR_REG_RTCIO_BASE + 0x320)
+/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: PDAC1_DRV*/
+#define RTC_IO_PDAC1_DRV  0x00000003
+#define RTC_IO_PDAC1_DRV_M  ((RTC_IO_PDAC1_DRV_V)<<(RTC_IO_PDAC1_DRV_S))
+#define RTC_IO_PDAC1_DRV_V  0x3
+#define RTC_IO_PDAC1_DRV_S  29
+/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: PDAC1_RDE*/
+#define RTC_IO_PDAC1_RDE  (BIT(28))
+#define RTC_IO_PDAC1_RDE_M  (BIT(28))
+#define RTC_IO_PDAC1_RDE_V  0x1
+#define RTC_IO_PDAC1_RDE_S  28
+/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: PDAC1_RUE*/
+#define RTC_IO_PDAC1_RUE  (BIT(27))
+#define RTC_IO_PDAC1_RUE_M  (BIT(27))
+#define RTC_IO_PDAC1_RUE_V  0x1
+#define RTC_IO_PDAC1_RUE_S  27
+/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_PDAC1_MUX_SEL  (BIT(19))
+#define RTC_IO_PDAC1_MUX_SEL_M  (BIT(19))
+#define RTC_IO_PDAC1_MUX_SEL_V  0x1
+#define RTC_IO_PDAC1_MUX_SEL_S  19
+/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: PDAC1 function sel*/
+#define RTC_IO_PDAC1_FUN_SEL  0x00000003
+#define RTC_IO_PDAC1_FUN_SEL_M  ((RTC_IO_PDAC1_FUN_SEL_V)<<(RTC_IO_PDAC1_FUN_SEL_S))
+#define RTC_IO_PDAC1_FUN_SEL_V  0x3
+#define RTC_IO_PDAC1_FUN_SEL_S  17
+/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_PDAC1_SLP_SEL  (BIT(16))
+#define RTC_IO_PDAC1_SLP_SEL_M  (BIT(16))
+#define RTC_IO_PDAC1_SLP_SEL_V  0x1
+#define RTC_IO_PDAC1_SLP_SEL_S  16
+/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_PDAC1_SLP_IE  (BIT(15))
+#define RTC_IO_PDAC1_SLP_IE_M  (BIT(15))
+#define RTC_IO_PDAC1_SLP_IE_V  0x1
+#define RTC_IO_PDAC1_SLP_IE_S  15
+/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_PDAC1_SLP_OE  (BIT(14))
+#define RTC_IO_PDAC1_SLP_OE_M  (BIT(14))
+#define RTC_IO_PDAC1_SLP_OE_V  0x1
+#define RTC_IO_PDAC1_SLP_OE_S  14
+/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_PDAC1_FUN_IE  (BIT(13))
+#define RTC_IO_PDAC1_FUN_IE_M  (BIT(13))
+#define RTC_IO_PDAC1_FUN_IE_V  0x1
+#define RTC_IO_PDAC1_FUN_IE_S  13
+/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR
+ ADC FSM to control PDAC1_XPD_DAC*/
+#define RTC_IO_PDAC1_DAC_XPD_FORCE  (BIT(12))
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_M  (BIT(12))
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_V  0x1
+#define RTC_IO_PDAC1_DAC_XPD_FORCE_S  12
+/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: PDAC1_XPD_DAC*/
+#define RTC_IO_PDAC1_XPD_DAC  (BIT(11))
+#define RTC_IO_PDAC1_XPD_DAC_M  (BIT(11))
+#define RTC_IO_PDAC1_XPD_DAC_V  0x1
+#define RTC_IO_PDAC1_XPD_DAC_S  11
+/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: PDAC1_DAC*/
+#define RTC_IO_PDAC1_DAC  0x000000FF
+#define RTC_IO_PDAC1_DAC_M  ((RTC_IO_PDAC1_DAC_V)<<(RTC_IO_PDAC1_DAC_S))
+#define RTC_IO_PDAC1_DAC_V  0xFF
+#define RTC_IO_PDAC1_DAC_S  3
+
+#define RTC_IO_PAD_DAC2_REG          (DR_REG_RTCIO_BASE + 0x330)
+/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: PDAC2_DRV*/
+#define RTC_IO_PDAC2_DRV  0x00000003
+#define RTC_IO_PDAC2_DRV_M  ((RTC_IO_PDAC2_DRV_V)<<(RTC_IO_PDAC2_DRV_S))
+#define RTC_IO_PDAC2_DRV_V  0x3
+#define RTC_IO_PDAC2_DRV_S  29
+/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: PDAC2_RDE*/
+#define RTC_IO_PDAC2_RDE  (BIT(28))
+#define RTC_IO_PDAC2_RDE_M  (BIT(28))
+#define RTC_IO_PDAC2_RDE_V  0x1
+#define RTC_IO_PDAC2_RDE_S  28
+/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: PDAC2_RUE*/
+#define RTC_IO_PDAC2_RUE  (BIT(27))
+#define RTC_IO_PDAC2_RUE_M  (BIT(27))
+#define RTC_IO_PDAC2_RUE_V  0x1
+#define RTC_IO_PDAC2_RUE_S  27
+/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_PDAC2_MUX_SEL  (BIT(19))
+#define RTC_IO_PDAC2_MUX_SEL_M  (BIT(19))
+#define RTC_IO_PDAC2_MUX_SEL_V  0x1
+#define RTC_IO_PDAC2_MUX_SEL_S  19
+/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: PDAC1 function sel*/
+#define RTC_IO_PDAC2_FUN_SEL  0x00000003
+#define RTC_IO_PDAC2_FUN_SEL_M  ((RTC_IO_PDAC2_FUN_SEL_V)<<(RTC_IO_PDAC2_FUN_SEL_S))
+#define RTC_IO_PDAC2_FUN_SEL_V  0x3
+#define RTC_IO_PDAC2_FUN_SEL_S  17
+/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_PDAC2_SLP_SEL  (BIT(16))
+#define RTC_IO_PDAC2_SLP_SEL_M  (BIT(16))
+#define RTC_IO_PDAC2_SLP_SEL_V  0x1
+#define RTC_IO_PDAC2_SLP_SEL_S  16
+/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_PDAC2_SLP_IE  (BIT(15))
+#define RTC_IO_PDAC2_SLP_IE_M  (BIT(15))
+#define RTC_IO_PDAC2_SLP_IE_V  0x1
+#define RTC_IO_PDAC2_SLP_IE_S  15
+/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_PDAC2_SLP_OE  (BIT(14))
+#define RTC_IO_PDAC2_SLP_OE_M  (BIT(14))
+#define RTC_IO_PDAC2_SLP_OE_V  0x1
+#define RTC_IO_PDAC2_SLP_OE_S  14
+/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_PDAC2_FUN_IE  (BIT(13))
+#define RTC_IO_PDAC2_FUN_IE_M  (BIT(13))
+#define RTC_IO_PDAC2_FUN_IE_V  0x1
+#define RTC_IO_PDAC2_FUN_IE_S  13
+/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC 0: use SAR
+ ADC FSM to control PDAC2_XPD_DAC*/
+#define RTC_IO_PDAC2_DAC_XPD_FORCE  (BIT(12))
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_M  (BIT(12))
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_V  0x1
+#define RTC_IO_PDAC2_DAC_XPD_FORCE_S  12
+/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: PDAC2_XPD_DAC*/
+#define RTC_IO_PDAC2_XPD_DAC  (BIT(11))
+#define RTC_IO_PDAC2_XPD_DAC_M  (BIT(11))
+#define RTC_IO_PDAC2_XPD_DAC_V  0x1
+#define RTC_IO_PDAC2_XPD_DAC_S  11
+/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[10:3] ;default: 8'd0 ; */
+/*description: PDAC2_DAC*/
+#define RTC_IO_PDAC2_DAC  0x000000FF
+#define RTC_IO_PDAC2_DAC_M  ((RTC_IO_PDAC2_DAC_V)<<(RTC_IO_PDAC2_DAC_S))
+#define RTC_IO_PDAC2_DAC_V  0xFF
+#define RTC_IO_PDAC2_DAC_S  3
+
+#define RTC_IO_RTC_PAD19_REG          (DR_REG_RTCIO_BASE + 0x340)
+/* RTC_IO_PAD19_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_PAD19_DRV  0x00000003
+#define RTC_IO_PAD19_DRV_M  ((RTC_IO_PAD19_DRV_V)<<(RTC_IO_PAD19_DRV_S))
+#define RTC_IO_PAD19_DRV_V  0x3
+#define RTC_IO_PAD19_DRV_S  29
+/* RTC_IO_PAD19_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: RDE*/
+#define RTC_IO_PAD19_RDE  (BIT(28))
+#define RTC_IO_PAD19_RDE_M  (BIT(28))
+#define RTC_IO_PAD19_RDE_V  0x1
+#define RTC_IO_PAD19_RDE_S  28
+/* RTC_IO_PAD19_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_PAD19_RUE  (BIT(27))
+#define RTC_IO_PAD19_RUE_M  (BIT(27))
+#define RTC_IO_PAD19_RUE_V  0x1
+#define RTC_IO_PAD19_RUE_S  27
+/* RTC_IO_PAD19_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_PAD19_MUX_SEL  (BIT(19))
+#define RTC_IO_PAD19_MUX_SEL_M  (BIT(19))
+#define RTC_IO_PAD19_MUX_SEL_V  0x1
+#define RTC_IO_PAD19_MUX_SEL_S  19
+/* RTC_IO_PAD19_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_PAD19_FUN_SEL  0x00000003
+#define RTC_IO_PAD19_FUN_SEL_M  ((RTC_IO_PAD19_FUN_SEL_V)<<(RTC_IO_PAD19_FUN_SEL_S))
+#define RTC_IO_PAD19_FUN_SEL_V  0x3
+#define RTC_IO_PAD19_FUN_SEL_S  17
+/* RTC_IO_PAD19_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_PAD19_SLP_SEL  (BIT(16))
+#define RTC_IO_PAD19_SLP_SEL_M  (BIT(16))
+#define RTC_IO_PAD19_SLP_SEL_V  0x1
+#define RTC_IO_PAD19_SLP_SEL_S  16
+/* RTC_IO_PAD19_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_PAD19_SLP_IE  (BIT(15))
+#define RTC_IO_PAD19_SLP_IE_M  (BIT(15))
+#define RTC_IO_PAD19_SLP_IE_V  0x1
+#define RTC_IO_PAD19_SLP_IE_S  15
+/* RTC_IO_PAD19_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_PAD19_SLP_OE  (BIT(14))
+#define RTC_IO_PAD19_SLP_OE_M  (BIT(14))
+#define RTC_IO_PAD19_SLP_OE_V  0x1
+#define RTC_IO_PAD19_SLP_OE_S  14
+/* RTC_IO_PAD19_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_PAD19_FUN_IE  (BIT(13))
+#define RTC_IO_PAD19_FUN_IE_M  (BIT(13))
+#define RTC_IO_PAD19_FUN_IE_V  0x1
+#define RTC_IO_PAD19_FUN_IE_S  13
+
+#define RTC_IO_RTC_PAD20_REG          (DR_REG_RTCIO_BASE + 0x350)
+/* RTC_IO_PAD20_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_PAD20_DRV  0x00000003
+#define RTC_IO_PAD20_DRV_M  ((RTC_IO_PAD20_DRV_V)<<(RTC_IO_PAD20_DRV_S))
+#define RTC_IO_PAD20_DRV_V  0x3
+#define RTC_IO_PAD20_DRV_S  29
+/* RTC_IO_PAD20_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: RDE*/
+#define RTC_IO_PAD20_RDE  (BIT(28))
+#define RTC_IO_PAD20_RDE_M  (BIT(28))
+#define RTC_IO_PAD20_RDE_V  0x1
+#define RTC_IO_PAD20_RDE_S  28
+/* RTC_IO_PAD20_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_PAD20_RUE  (BIT(27))
+#define RTC_IO_PAD20_RUE_M  (BIT(27))
+#define RTC_IO_PAD20_RUE_V  0x1
+#define RTC_IO_PAD20_RUE_S  27
+/* RTC_IO_PAD20_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_PAD20_MUX_SEL  (BIT(19))
+#define RTC_IO_PAD20_MUX_SEL_M  (BIT(19))
+#define RTC_IO_PAD20_MUX_SEL_V  0x1
+#define RTC_IO_PAD20_MUX_SEL_S  19
+/* RTC_IO_PAD20_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_PAD20_FUN_SEL  0x00000003
+#define RTC_IO_PAD20_FUN_SEL_M  ((RTC_IO_PAD20_FUN_SEL_V)<<(RTC_IO_PAD20_FUN_SEL_S))
+#define RTC_IO_PAD20_FUN_SEL_V  0x3
+#define RTC_IO_PAD20_FUN_SEL_S  17
+/* RTC_IO_PAD20_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_PAD20_SLP_SEL  (BIT(16))
+#define RTC_IO_PAD20_SLP_SEL_M  (BIT(16))
+#define RTC_IO_PAD20_SLP_SEL_V  0x1
+#define RTC_IO_PAD20_SLP_SEL_S  16
+/* RTC_IO_PAD20_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_PAD20_SLP_IE  (BIT(15))
+#define RTC_IO_PAD20_SLP_IE_M  (BIT(15))
+#define RTC_IO_PAD20_SLP_IE_V  0x1
+#define RTC_IO_PAD20_SLP_IE_S  15
+/* RTC_IO_PAD20_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_PAD20_SLP_OE  (BIT(14))
+#define RTC_IO_PAD20_SLP_OE_M  (BIT(14))
+#define RTC_IO_PAD20_SLP_OE_V  0x1
+#define RTC_IO_PAD20_SLP_OE_S  14
+/* RTC_IO_PAD20_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_PAD20_FUN_IE  (BIT(13))
+#define RTC_IO_PAD20_FUN_IE_M  (BIT(13))
+#define RTC_IO_PAD20_FUN_IE_V  0x1
+#define RTC_IO_PAD20_FUN_IE_S  13
+
+#define RTC_IO_RTC_PAD21_REG          (DR_REG_RTCIO_BASE + 0x360)
+/* RTC_IO_PAD21_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */
+/*description: DRV*/
+#define RTC_IO_PAD21_DRV  0x00000003
+#define RTC_IO_PAD21_DRV_M  ((RTC_IO_PAD21_DRV_V)<<(RTC_IO_PAD21_DRV_S))
+#define RTC_IO_PAD21_DRV_V  0x3
+#define RTC_IO_PAD21_DRV_S  29
+/* RTC_IO_PAD21_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */
+/*description: RDE*/
+#define RTC_IO_PAD21_RDE  (BIT(28))
+#define RTC_IO_PAD21_RDE_M  (BIT(28))
+#define RTC_IO_PAD21_RDE_V  0x1
+#define RTC_IO_PAD21_RDE_S  28
+/* RTC_IO_PAD21_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: RUE*/
+#define RTC_IO_PAD21_RUE  (BIT(27))
+#define RTC_IO_PAD21_RUE_M  (BIT(27))
+#define RTC_IO_PAD21_RUE_V  0x1
+#define RTC_IO_PAD21_RUE_S  27
+/* RTC_IO_PAD21_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */
+/*description: 1: use RTC GPIO 0: use digital GPIO*/
+#define RTC_IO_PAD21_MUX_SEL  (BIT(19))
+#define RTC_IO_PAD21_MUX_SEL_M  (BIT(19))
+#define RTC_IO_PAD21_MUX_SEL_V  0x1
+#define RTC_IO_PAD21_MUX_SEL_S  19
+/* RTC_IO_PAD21_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */
+/*description: function sel*/
+#define RTC_IO_PAD21_FUN_SEL  0x00000003
+#define RTC_IO_PAD21_FUN_SEL_M  ((RTC_IO_PAD21_FUN_SEL_V)<<(RTC_IO_PAD21_FUN_SEL_S))
+#define RTC_IO_PAD21_FUN_SEL_V  0x3
+#define RTC_IO_PAD21_FUN_SEL_S  17
+/* RTC_IO_PAD21_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */
+/*description: 1: enable sleep mode during sleep 0: no sleep mode*/
+#define RTC_IO_PAD21_SLP_SEL  (BIT(16))
+#define RTC_IO_PAD21_SLP_SEL_M  (BIT(16))
+#define RTC_IO_PAD21_SLP_SEL_V  0x1
+#define RTC_IO_PAD21_SLP_SEL_S  16
+/* RTC_IO_PAD21_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */
+/*description: input enable in sleep mode*/
+#define RTC_IO_PAD21_SLP_IE  (BIT(15))
+#define RTC_IO_PAD21_SLP_IE_M  (BIT(15))
+#define RTC_IO_PAD21_SLP_IE_V  0x1
+#define RTC_IO_PAD21_SLP_IE_S  15
+/* RTC_IO_PAD21_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */
+/*description: output enable in sleep mode*/
+#define RTC_IO_PAD21_SLP_OE  (BIT(14))
+#define RTC_IO_PAD21_SLP_OE_M  (BIT(14))
+#define RTC_IO_PAD21_SLP_OE_V  0x1
+#define RTC_IO_PAD21_SLP_OE_S  14
+/* RTC_IO_PAD21_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: input enable in work mode*/
+#define RTC_IO_PAD21_FUN_IE  (BIT(13))
+#define RTC_IO_PAD21_FUN_IE_M  (BIT(13))
+#define RTC_IO_PAD21_FUN_IE_V  0x1
+#define RTC_IO_PAD21_FUN_IE_S  13
+
+#define RTC_IO_EXT_WAKEUP0_REG          (DR_REG_RTCIO_BASE + 0x370)
+/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: */
+#define RTC_IO_EXT_WAKEUP0_SEL  0x0000001F
+#define RTC_IO_EXT_WAKEUP0_SEL_M  ((RTC_IO_EXT_WAKEUP0_SEL_V)<<(RTC_IO_EXT_WAKEUP0_SEL_S))
+#define RTC_IO_EXT_WAKEUP0_SEL_V  0x1F
+#define RTC_IO_EXT_WAKEUP0_SEL_S  27
+
+#define RTC_IO_XTL_EXT_CTR_REG          (DR_REG_RTCIO_BASE + 0x380)
+/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */
+/*description: select RTC GPIO 0 ~ 17 to control XTAL*/
+#define RTC_IO_XTL_EXT_CTR_SEL  0x0000001F
+#define RTC_IO_XTL_EXT_CTR_SEL_M  ((RTC_IO_XTL_EXT_CTR_SEL_V)<<(RTC_IO_XTL_EXT_CTR_SEL_S))
+#define RTC_IO_XTL_EXT_CTR_SEL_V  0x1F
+#define RTC_IO_XTL_EXT_CTR_SEL_S  27
+
+#define RTC_IO_SAR_I2C_IO_REG          (DR_REG_RTCIO_BASE + 0x390)
+/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
+/*description: */
+#define RTC_IO_SAR_I2C_SDA_SEL  0x00000003
+#define RTC_IO_SAR_I2C_SDA_SEL_M  ((RTC_IO_SAR_I2C_SDA_SEL_V)<<(RTC_IO_SAR_I2C_SDA_SEL_S))
+#define RTC_IO_SAR_I2C_SDA_SEL_V  0x3
+#define RTC_IO_SAR_I2C_SDA_SEL_S  30
+/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
+/*description: */
+#define RTC_IO_SAR_I2C_SCL_SEL  0x00000003
+#define RTC_IO_SAR_I2C_SCL_SEL_M  ((RTC_IO_SAR_I2C_SCL_SEL_V)<<(RTC_IO_SAR_I2C_SCL_SEL_S))
+#define RTC_IO_SAR_I2C_SCL_SEL_V  0x3
+#define RTC_IO_SAR_I2C_SCL_SEL_S  28
+/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */
+/*description: */
+#define RTC_IO_SAR_DEBUG_BIT_SEL  0x0000001F
+#define RTC_IO_SAR_DEBUG_BIT_SEL_M  ((RTC_IO_SAR_DEBUG_BIT_SEL_V)<<(RTC_IO_SAR_DEBUG_BIT_SEL_S))
+#define RTC_IO_SAR_DEBUG_BIT_SEL_V  0x1F
+#define RTC_IO_SAR_DEBUG_BIT_SEL_S  23
+
+#define RTC_IO_DATE_REG          (DR_REG_RTCIO_BASE + 0x7f0)
+/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1808030 ; */
+/*description: */
+#define RTC_IO_IO_DATE  0x0FFFFFFF
+#define RTC_IO_IO_DATE_M  ((RTC_IO_IO_DATE_V)<<(RTC_IO_IO_DATE_S))
+#define RTC_IO_IO_DATE_V  0xFFFFFFF
+#define RTC_IO_IO_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_RTC_IO_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/rtc_io_struct.h b/components/soc/esp32s2beta/include/soc/rtc_io_struct.h
new file mode 100644
index 000000000..1339d5628
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/rtc_io_struct.h
@@ -0,0 +1,356 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_RTC_IO_STRUCT_H_
+#define _SOC_RTC_IO_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reserved0:        10;
+            uint32_t data:             22;              /*RTC GPIO 0 ~ 21 output data*/
+        };
+        uint32_t val;
+    } out;
+    union {
+        struct {
+            uint32_t reserved0:             10;
+            uint32_t w1ts:                  22;         /*RTC GPIO 0 ~ 21 output data write 1 to set*/
+        };
+        uint32_t val;
+    } out_w1ts;
+    union {
+        struct {
+            uint32_t reserved0:             10;
+            uint32_t w1tc:                  22;         /*RTC GPIO 0 ~ 21 output data write 1 to clear*/
+        };
+        uint32_t val;
+    } out_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:      10;
+            uint32_t enable:         22;                /*RTC GPIO 0 ~ 21 enable*/
+        };
+        uint32_t val;
+    } enable;
+    union {
+        struct {
+            uint32_t reserved0:           10;
+            uint32_t w1ts:                22;           /*RTC GPIO 0 ~ 21 enable write 1 to set*/
+        };
+        uint32_t val;
+    } enable_w1ts;
+    union {
+        struct {
+            uint32_t reserved0:           10;
+            uint32_t w1tc:                22;           /*RTC GPIO 0 ~ 21 enable write 1 to clear*/
+        };
+        uint32_t val;
+    } enable_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:          10;
+            uint32_t status:             22;            /*RTC GPIO 0 ~ 21 interrupt status*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t reserved0:               10;
+            uint32_t w1ts:                    22;       /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
+        };
+        uint32_t val;
+    } status_w1ts;
+    union {
+        struct {
+            uint32_t reserved0:               10;
+            uint32_t w1tc:                    22;       /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
+        };
+        uint32_t val;
+    } status_w1tc;
+    union {
+        struct {
+            uint32_t reserved0:       10;
+            uint32_t in:              22;               /*RTC GPIO input data*/
+        };
+        uint32_t val;
+    } in_val;
+    union {
+        struct {
+            uint32_t reserved0:                   2;
+            uint32_t pad_driver:                  1;    /*if set to 0: normal output  if set to 1: open drain*/
+            uint32_t reserved3:                   4;
+            uint32_t int_type:                    3;    /*if set to 0: GPIO interrupt disable   if set to 1: rising edge trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+            uint32_t wakeup_enable:               1;    /*RTC GPIO wakeup enable bit*/
+            uint32_t reserved11:                 21;
+        };
+        uint32_t val;
+    } pin[21];
+    union {
+        struct {
+            uint32_t reserved0:                    2;
+            uint32_t rtc_gpio_pin21_pad_driver:    1;   /*if set to 0: normal output  if set to 1: open drain*/
+            uint32_t reserved3:                    4;
+            uint32_t rtc_gpio_pin21_int_type:      3;   /*if set to 0: GPIO interrupt disable   if set to 1: rising edge trigger   if set to 2: falling edge trigger  if set to 3: any edge trigger  if set to 4: low level trigger   if set to 5: high level trigger*/
+            uint32_t rtc_gpio_pin21_wakeup_enable: 1;   /*RTC GPIO wakeup enable bit*/
+            uint32_t reserved11:                  21;
+        };
+        uint32_t val;
+    } pin21;
+    union {
+        struct {
+            uint32_t sel0:                    5;
+            uint32_t sel1:                    5;
+            uint32_t sel2:                    5;
+            uint32_t sel3:                    5;
+            uint32_t sel4:                    5;
+            uint32_t no_gating_12m:           1;
+            uint32_t reserved26:              6;
+        };
+        uint32_t val;
+    } debug_sel;
+    union {
+        struct {
+            uint32_t reserved0:         13;
+            uint32_t fun_ie:             1;             /*input enable in work mode*/
+            uint32_t slp_oe:             1;             /*output enable in sleep mode*/
+            uint32_t slp_ie:             1;             /*input enable in sleep mode*/
+            uint32_t slp_sel:            1;             /*1: enable sleep mode during sleep 0: no sleep mode*/
+            uint32_t fun_sel:            2;             /*function sel*/
+            uint32_t mux_sel:            1;             /*1: use RTC GPIO 0: use digital GPIO*/
+            uint32_t xpd:                1;             /*TOUCH_XPD*/
+            uint32_t tie_opt:            1;             /*TOUCH_TIE_OPT*/
+            uint32_t start:              1;             /*TOUCH_START*/
+            uint32_t dac:                3;             /*TOUCH_DAC*/
+            uint32_t reserved26:         1;
+            uint32_t rue:                1;             /*RUE*/
+            uint32_t rde:                1;             /*RDE*/
+            uint32_t drv:                2;             /*DRV*/
+            uint32_t reserved31:         1;
+        };
+        uint32_t val;
+    } touch_pad[15];
+    union {
+        struct {
+            uint32_t reserved0:   13;
+            uint32_t x32p_fun_ie:  1;                   /*input enable in work mode*/
+            uint32_t x32p_slp_oe:  1;                   /*output enable in sleep mode*/
+            uint32_t x32p_slp_ie:  1;                   /*input enable in sleep mode*/
+            uint32_t x32p_slp_sel: 1;                   /*1: enable sleep mode during sleep 0: no sleep mode*/
+            uint32_t x32p_fun_sel: 2;                   /*function sel*/
+            uint32_t x32p_mux_sel: 1;                   /*1: use RTC GPIO 0: use digital GPIO*/
+            uint32_t reserved20:   7;
+            uint32_t x32p_rue:     1;                   /*RUE*/
+            uint32_t x32p_rde:     1;                   /*RDE*/
+            uint32_t x32p_drv:     2;                   /*DRV*/
+            uint32_t reserved31:   1;
+        };
+        uint32_t val;
+    } xtal_32p_pad;
+    union {
+        struct {
+            uint32_t reserved0:   13;
+            uint32_t x32n_fun_ie:  1;                   /*input enable in work mode*/
+            uint32_t x32n_slp_oe:  1;                   /*output enable in sleep mode*/
+            uint32_t x32n_slp_ie:  1;                   /*input enable in sleep mode*/
+            uint32_t x32n_slp_sel: 1;                   /*1: enable sleep mode during sleep 0: no sleep mode*/
+            uint32_t x32n_fun_sel: 2;                   /*function sel*/
+            uint32_t x32n_mux_sel: 1;                   /*1: use RTC GPIO 0: use digital GPIO*/
+            uint32_t reserved20:   7;
+            uint32_t x32n_rue:     1;                   /*RUE*/
+            uint32_t x32n_rde:     1;                   /*RDE*/
+            uint32_t x32n_drv:     2;                   /*DRV*/
+            uint32_t reserved31:   1;
+        };
+        uint32_t val;
+    } xtal_32n_pad;
+    union {
+        struct {
+            uint32_t reserved0:           3;
+            uint32_t dac:                 8;            /*PDAC1_DAC*/
+            uint32_t xpd_dac:             1;            /*PDAC1_XPD_DAC*/
+            uint32_t dac_xpd_force:       1;            /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
+            uint32_t fun_ie:              1;            /*input enable in work mode*/
+            uint32_t slp_oe:              1;            /*output enable in sleep mode*/
+            uint32_t slp_ie:              1;            /*input enable in sleep mode*/
+            uint32_t slp_sel:             1;            /*1: enable sleep mode during sleep 0: no sleep mode*/
+            uint32_t fun_sel:             2;            /*PDAC1 function sel*/
+            uint32_t mux_sel:             1;            /*1: use RTC GPIO 0: use digital GPIO*/
+            uint32_t reserved20:          7;
+            uint32_t rue:                 1;            /*PDAC1_RUE*/
+            uint32_t rde:                 1;            /*PDAC1_RDE*/
+            uint32_t drv:                 2;            /*PDAC1_DRV*/
+            uint32_t reserved31:          1;
+        };
+        uint32_t val;
+    } pad_dac[2];
+    union {
+        struct {
+            uint32_t reserved0:        13;
+            uint32_t rtc_pad19_fun_ie:  1;              /*input enable in work mode*/
+            uint32_t rtc_pad19_slp_oe:  1;              /*output enable in sleep mode*/
+            uint32_t rtc_pad19_slp_ie:  1;              /*input enable in sleep mode*/
+            uint32_t rtc_pad19_slp_sel: 1;              /*1: enable sleep mode during sleep 0: no sleep mode*/
+            uint32_t rtc_pad19_fun_sel: 2;              /*function sel*/
+            uint32_t rtc_pad19_mux_sel: 1;              /*1: use RTC GPIO 0: use digital GPIO*/
+            uint32_t reserved20:        7;
+            uint32_t rtc_pad19_rue:     1;              /*RUE*/
+            uint32_t rtc_pad19_rde:     1;              /*RDE*/
+            uint32_t rtc_pad19_drv:     2;              /*DRV*/
+            uint32_t reserved31:        1;
+        };
+        uint32_t val;
+    } rtc_pad19;
+    union {
+        struct {
+            uint32_t reserved0:        13;
+            uint32_t rtc_pad20_fun_ie:  1;              /*input enable in work mode*/
+            uint32_t rtc_pad20_slp_oe:  1;              /*output enable in sleep mode*/
+            uint32_t rtc_pad20_slp_ie:  1;              /*input enable in sleep mode*/
+            uint32_t rtc_pad20_slp_sel: 1;              /*1: enable sleep mode during sleep 0: no sleep mode*/
+            uint32_t rtc_pad20_fun_sel: 2;              /*function sel*/
+            uint32_t rtc_pad20_mux_sel: 1;              /*1: use RTC GPIO 0: use digital GPIO*/
+            uint32_t reserved20:        7;
+            uint32_t rtc_pad20_rue:     1;              /*RUE*/
+            uint32_t rtc_pad20_rde:     1;              /*RDE*/
+            uint32_t rtc_pad20_drv:     2;              /*DRV*/
+            uint32_t reserved31:        1;
+        };
+        uint32_t val;
+    } rtc_pad20;
+    union {
+        struct {
+            uint32_t reserved0:        13;
+            uint32_t rtc_pad21_fun_ie:  1;              /*input enable in work mode*/
+            uint32_t rtc_pad21_slp_oe:  1;              /*output enable in sleep mode*/
+            uint32_t rtc_pad21_slp_ie:  1;              /*input enable in sleep mode*/
+            uint32_t rtc_pad21_slp_sel: 1;              /*1: enable sleep mode during sleep 0: no sleep mode*/
+            uint32_t rtc_pad21_fun_sel: 2;              /*function sel*/
+            uint32_t rtc_pad21_mux_sel: 1;              /*1: use RTC GPIO 0: use digital GPIO*/
+            uint32_t reserved20:        7;
+            uint32_t rtc_pad21_rue:     1;              /*RUE*/
+            uint32_t rtc_pad21_rde:     1;              /*RDE*/
+            uint32_t rtc_pad21_drv:     2;              /*DRV*/
+            uint32_t reserved31:        1;
+        };
+        uint32_t val;
+    } rtc_pad21;
+    union {
+        struct {
+            uint32_t reserved0:      27;
+            uint32_t sel:             5;
+        };
+        uint32_t val;
+    } ext_wakeup0;
+    union {
+        struct {
+            uint32_t reserved0:      27;
+            uint32_t sel:             5;                /*select RTC GPIO 0 ~ 17 to control XTAL*/
+        };
+        uint32_t val;
+    } xtl_ext_ctr;
+    union {
+        struct {
+            uint32_t reserved0:        23;
+            uint32_t debug_bit_sel:     5;
+            uint32_t scl_sel:           2;
+            uint32_t sda_sel:           2;
+        };
+        uint32_t val;
+    } sar_i2c_io;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t reserved_fc;
+    uint32_t reserved_100;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    union {
+        struct {
+            uint32_t date:      28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } date;
+} rtc_io_dev_t;
+extern rtc_io_dev_t RTCIO;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_RTC_IO_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/sdmmc_reg.h b/components/soc/esp32s2beta/include/soc/sdmmc_reg.h
new file mode 100644
index 000000000..2f9c68f80
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/sdmmc_reg.h
@@ -0,0 +1,96 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SDMMC_REG_H_
+#define _SOC_SDMMC_REG_H_
+#include "soc.h"
+
+#define SDMMC_CTRL_REG          (DR_REG_SDMMC_BASE + 0x00)
+#define SDMMC_PWREN_REG         (DR_REG_SDMMC_BASE + 0x04)
+#define SDMMC_CLKDIV_REG        (DR_REG_SDMMC_BASE + 0x08)
+#define SDMMC_CLKSRC_REG        (DR_REG_SDMMC_BASE + 0x0c)
+#define SDMMC_CLKENA_REG        (DR_REG_SDMMC_BASE + 0x10)
+#define SDMMC_TMOUT_REG         (DR_REG_SDMMC_BASE + 0x14)
+#define SDMMC_CTYPE_REG         (DR_REG_SDMMC_BASE + 0x18)
+#define SDMMC_BLKSIZ_REG        (DR_REG_SDMMC_BASE + 0x1c)
+#define SDMMC_BYTCNT_REG        (DR_REG_SDMMC_BASE + 0x20)
+#define SDMMC_INTMASK_REG       (DR_REG_SDMMC_BASE + 0x24)
+#define SDMMC_CMDARG_REG        (DR_REG_SDMMC_BASE + 0x28)
+#define SDMMC_CMD_REG           (DR_REG_SDMMC_BASE + 0x2c)
+#define SDMMC_RESP0_REG         (DR_REG_SDMMC_BASE + 0x30)
+#define SDMMC_RESP1_REG         (DR_REG_SDMMC_BASE + 0x34)
+#define SDMMC_RESP2_REG         (DR_REG_SDMMC_BASE + 0x38)
+#define SDMMC_RESP3_REG         (DR_REG_SDMMC_BASE + 0x3c)
+
+#define SDMMC_MINTSTS_REG       (DR_REG_SDMMC_BASE + 0x40)
+#define SDMMC_RINTSTS_REG       (DR_REG_SDMMC_BASE + 0x44)
+#define SDMMC_STATUS_REG        (DR_REG_SDMMC_BASE + 0x48)
+#define SDMMC_FIFOTH_REG        (DR_REG_SDMMC_BASE + 0x4c)
+#define SDMMC_CDETECT_REG       (DR_REG_SDMMC_BASE + 0x50)
+#define SDMMC_WRTPRT_REG        (DR_REG_SDMMC_BASE + 0x54)
+#define SDMMC_GPIO_REG          (DR_REG_SDMMC_BASE + 0x58)
+#define SDMMC_TCBCNT_REG        (DR_REG_SDMMC_BASE + 0x5c)
+#define SDMMC_TBBCNT_REG        (DR_REG_SDMMC_BASE + 0x60)
+#define SDMMC_DEBNCE_REG        (DR_REG_SDMMC_BASE + 0x64)
+#define SDMMC_USRID_REG         (DR_REG_SDMMC_BASE + 0x68)
+#define SDMMC_VERID_REG         (DR_REG_SDMMC_BASE + 0x6c)
+#define SDMMC_HCON_REG          (DR_REG_SDMMC_BASE + 0x70)
+#define SDMMC_UHS_REG_REG       (DR_REG_SDMMC_BASE + 0x74)
+#define SDMMC_RST_N_REG         (DR_REG_SDMMC_BASE + 0x78)
+#define SDMMC_BMOD_REG          (DR_REG_SDMMC_BASE + 0x80)
+#define SDMMC_PLDMND_REG        (DR_REG_SDMMC_BASE + 0x84)
+#define SDMMC_DBADDR_REG        (DR_REG_SDMMC_BASE + 0x88)
+#define SDMMC_DBADDRU_REG       (DR_REG_SDMMC_BASE + 0x8c)
+#define SDMMC_IDSTS_REG         (DR_REG_SDMMC_BASE + 0x8c)
+#define SDMMC_IDINTEN_REG       (DR_REG_SDMMC_BASE + 0x90)
+#define SDMMC_DSCADDR_REG       (DR_REG_SDMMC_BASE + 0x94)
+#define SDMMC_DSCADDRL_REG      (DR_REG_SDMMC_BASE + 0x98)
+#define SDMMC_DSCADDRU_REG      (DR_REG_SDMMC_BASE + 0x9c)
+#define SDMMC_BUFADDRL_REG      (DR_REG_SDMMC_BASE + 0xa0)
+#define SDMMC_BUFADDRU_REG      (DR_REG_SDMMC_BASE + 0xa4)
+#define SDMMC_CARDTHRCTL_REG    (DR_REG_SDMMC_BASE + 0x100)
+#define SDMMC_BACK_END_POWER_REG    (DR_REG_SDMMC_BASE + 0x104)
+#define SDMMC_UHS_REG_EXT_REG   (DR_REG_SDMMC_BASE + 0x108)
+#define SDMMC_EMMC_DDR_REG_REG  (DR_REG_SDMMC_BASE + 0x10c)
+#define SDMMC_ENABLE_SHIFT_REG  (DR_REG_SDMMC_BASE + 0x110)
+
+#define SDMMC_CLOCK_REG         (DR_REG_SDMMC_BASE + 0x800)
+
+#define SDMMC_INTMASK_IO_SLOT1  BIT(17)
+#define SDMMC_INTMASK_IO_SLOT0  BIT(16)
+#define SDMMC_INTMASK_EBE       BIT(15)
+#define SDMMC_INTMASK_ACD       BIT(14)
+#define SDMMC_INTMASK_SBE       BIT(13)
+#define SDMMC_INTMASK_HLE       BIT(12)
+#define SDMMC_INTMASK_FRUN      BIT(11)
+#define SDMMC_INTMASK_HTO       BIT(10)
+#define SDMMC_INTMASK_DTO       BIT(9)
+#define SDMMC_INTMASK_RTO       BIT(8)
+#define SDMMC_INTMASK_DCRC      BIT(7)
+#define SDMMC_INTMASK_RCRC      BIT(6)
+#define SDMMC_INTMASK_RXDR      BIT(5)
+#define SDMMC_INTMASK_TXDR      BIT(4)
+#define SDMMC_INTMASK_DATA_OVER BIT(3)
+#define SDMMC_INTMASK_CMD_DONE  BIT(2)
+#define SDMMC_INTMASK_RESP_ERR  BIT(1)
+#define SDMMC_INTMASK_CD        BIT(0)
+
+#define SDMMC_IDMAC_INTMASK_AI  BIT(9)
+#define SDMMC_IDMAC_INTMASK_NI  BIT(8)
+#define SDMMC_IDMAC_INTMASK_CES BIT(5)
+#define SDMMC_IDMAC_INTMASK_DU  BIT(4)
+#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
+#define SDMMC_IDMAC_INTMASK_RI  BIT(1)
+#define SDMMC_IDMAC_INTMASK_TI  BIT(0)
+
+#endif /* _SOC_SDMMC_REG_H_  */
diff --git a/components/soc/esp32s2beta/include/soc/sdmmc_struct.h b/components/soc/esp32s2beta/include/soc/sdmmc_struct.h
new file mode 100644
index 000000000..7e3c6912e
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/sdmmc_struct.h
@@ -0,0 +1,377 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SDMMC_STRUCT_H_
+#define _SOC_SDMMC_STRUCT_H_
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    uint32_t reserved1: 1;
+    uint32_t disable_int_on_completion: 1;
+    uint32_t last_descriptor: 1;
+    uint32_t first_descriptor: 1;
+    uint32_t second_address_chained: 1;
+    uint32_t end_of_ring: 1;
+    uint32_t reserved2: 24;
+    uint32_t card_error_summary: 1;
+    uint32_t owned_by_idmac: 1;
+    uint32_t buffer1_size: 13;
+    uint32_t buffer2_size: 13;
+    uint32_t reserved3: 6;
+    void* buffer1_ptr;
+    union {
+        void* buffer2_ptr;
+        void* next_desc_ptr;
+    };
+} sdmmc_desc_t;
+
+#define SDMMC_DMA_MAX_BUF_LEN 4096
+
+_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
+
+
+typedef struct {
+    uint32_t cmd_index: 6;          ///< Command index
+    uint32_t response_expect: 1;    ///< set if response is expected
+    uint32_t response_long: 1;      ///< 0: short response expected, 1: long response expected
+    uint32_t check_response_crc: 1; ///< set if controller should check response CRC
+    uint32_t data_expected: 1;      ///< 0: no data expected, 1: data expected
+    uint32_t rw: 1;                 ///< 0: read from card, 1: write to card (don't care if no data expected)
+    uint32_t stream_mode: 1;        ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
+    uint32_t send_auto_stop: 1;     ///< set to send stop at the end of the transfer
+    uint32_t wait_complete: 1;      ///< 0: send command at once, 1: wait for previous command to complete
+    uint32_t stop_abort_cmd: 1;     ///< set if this is a stop or abort command intended to stop current transfer
+    uint32_t send_init: 1;          ///< set to send init sequence (80 clocks of 1)
+    uint32_t card_num: 5;           ///< card number
+    uint32_t update_clk_reg: 1;     ///< 0: normal command, 1: don't send command, just update clock registers
+    uint32_t read_ceata: 1;         ///< set if performing read from CE-ATA device
+    uint32_t ccs_expected: 1;       ///< set if CCS is expected from CE-ATA device
+    uint32_t enable_boot: 1;        ///< set for mandatory boot mode
+    uint32_t expect_boot_ack: 1;    ///< when set along with enable_boot, controller expects boot ack pattern
+    uint32_t disable_boot: 1;       ///< set to terminate boot operation (don't set along with enable_boot)
+    uint32_t boot_mode: 1;          ///< 0: mandatory boot operation, 1: alternate boot operation
+    uint32_t volt_switch: 1;        ///< set to enable voltage switching (for CMD11 only)
+    uint32_t use_hold_reg: 1;       ///< clear to bypass HOLD register
+    uint32_t reserved: 1;
+    uint32_t start_command: 1;      ///< Start command; once command is sent to the card, bit is cleared.
+} sdmmc_hw_cmd_t;  ///< command format used in cmd register; this structure is defined to make it easier to build command values
+
+_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
+
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t controller_reset: 1;
+            uint32_t fifo_reset: 1;
+            uint32_t dma_reset: 1;
+            uint32_t reserved1: 1;
+            uint32_t int_enable: 1;
+            uint32_t dma_enable: 1;
+            uint32_t read_wait: 1;
+            uint32_t send_irq_response: 1;
+            uint32_t abort_read_data: 1;
+            uint32_t send_ccsd: 1;
+            uint32_t send_auto_stop_ccsd: 1;
+            uint32_t ceata_device_interrupt_status: 1;
+            uint32_t reserved2: 4;
+            uint32_t card_voltage_a: 4;
+            uint32_t card_voltage_b: 4;
+            uint32_t enable_od_pullup: 1;
+            uint32_t use_internal_dma: 1;
+            uint32_t reserved3: 6;
+        };
+        uint32_t val;
+    } ctrl;
+
+    uint32_t pwren;             ///< 1: enable power to card, 0: disable power to card
+
+    union {
+        struct {
+            uint32_t div0: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
+            uint32_t div1: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
+            uint32_t div2: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
+            uint32_t div3: 8;   ///< 0: bypass, 1-255: divide clock by (2*div0).
+        };
+        uint32_t val;
+    } clkdiv;
+
+    union {
+        struct {
+            uint32_t card0: 2;            ///< 0-3: select clock divider for card 0 among div0-div3
+            uint32_t card1: 2;            ///< 0-3: select clock divider for card 1 among div0-div3
+            uint32_t reserved: 28;
+        };
+        uint32_t val;
+    } clksrc;
+
+    union {
+        struct {
+            uint32_t cclk_enable: 16;       ///< 1: enable clock to card, 0: disable clock
+            uint32_t cclk_low_power: 16;    ///< 1: enable clock gating when card is idle, 0: disable clock gating
+        };
+        uint32_t val;
+    } clkena;
+
+    union {
+        struct {
+            uint32_t response: 8;       ///< response timeout, in card output clock cycles
+            uint32_t data: 24;          ///< data read timeout, in card output clock cycles
+        };
+        uint32_t val;
+    } tmout;
+
+    union {
+        struct {
+            uint32_t card_width: 16;    ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
+            uint32_t card_width_8: 16;  ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
+        };
+        uint32_t val;
+    } ctype;
+
+    uint32_t blksiz: 16;        ///< block size, default 0x200
+    uint32_t : 16;
+
+    uint32_t bytcnt;            ///< number of bytes to be transferred
+
+    union {
+        struct {
+            uint32_t cd: 1;             ///< Card detect interrupt enable
+            uint32_t re: 1;             ///< Response error interrupt enable
+            uint32_t cmd_done: 1;       ///< Command done interrupt enable
+            uint32_t dto: 1;            ///< Data transfer over interrupt enable
+            uint32_t txdr: 1;           ///< Transmit FIFO data request interrupt enable
+            uint32_t rxdr: 1;           ///< Receive FIFO data request interrupt enable
+            uint32_t rcrc: 1;           ///< Response CRC error interrupt enable
+            uint32_t dcrc: 1;           ///< Data CRC error interrupt enable
+            uint32_t rto: 1;            ///< Response timeout interrupt enable
+            uint32_t drto: 1;           ///< Data read timeout interrupt enable
+            uint32_t hto: 1;            ///< Data starvation-by-host timeout interrupt enable
+            uint32_t frun: 1;           ///< FIFO underrun/overrun error interrupt enable
+            uint32_t hle: 1;            ///< Hardware locked write error interrupt enable
+            uint32_t sbi_bci: 1;        ///< Start bit error / busy clear interrupt enable
+            uint32_t acd: 1;            ///< Auto command done interrupt enable
+            uint32_t ebe: 1;            ///< End bit error / write no CRC interrupt enable
+            uint32_t sdio: 16;          ///< SDIO interrupt enable
+        };
+        uint32_t val;
+    } intmask;
+
+    uint32_t cmdarg;        ///< Command argument to be passed to card
+
+    sdmmc_hw_cmd_t cmd;
+
+    uint32_t resp[4];           ///< Response from card
+
+    union {
+        struct {
+            uint32_t cd: 1;             ///< Card detect interrupt masked status
+            uint32_t re: 1;             ///< Response error interrupt masked status
+            uint32_t cmd_done: 1;       ///< Command done interrupt masked status
+            uint32_t dto: 1;            ///< Data transfer over interrupt masked status
+            uint32_t txdr: 1;           ///< Transmit FIFO data request interrupt masked status
+            uint32_t rxdr: 1;           ///< Receive FIFO data request interrupt masked status
+            uint32_t rcrc: 1;           ///< Response CRC error interrupt masked status
+            uint32_t dcrc: 1;           ///< Data CRC error interrupt masked status
+            uint32_t rto: 1;            ///< Response timeout interrupt masked status
+            uint32_t drto: 1;           ///< Data read timeout interrupt masked status
+            uint32_t hto: 1;            ///< Data starvation-by-host timeout interrupt masked status
+            uint32_t frun: 1;           ///< FIFO underrun/overrun error interrupt masked status
+            uint32_t hle: 1;            ///< Hardware locked write error interrupt masked status
+            uint32_t sbi_bci: 1;        ///< Start bit error / busy clear interrupt masked status
+            uint32_t acd: 1;            ///< Auto command done interrupt masked status
+            uint32_t ebe: 1;            ///< End bit error / write no CRC interrupt masked status
+            uint32_t sdio: 16;          ///< SDIO interrupt masked status
+        };
+        uint32_t val;
+    } mintsts;
+
+    union {
+        struct {
+            uint32_t cd: 1;             ///< Card detect raw interrupt status
+            uint32_t re: 1;             ///< Response error raw interrupt status
+            uint32_t cmd_done: 1;       ///< Command done raw interrupt status
+            uint32_t dto: 1;            ///< Data transfer over raw interrupt status
+            uint32_t txdr: 1;           ///< Transmit FIFO data request raw interrupt status
+            uint32_t rxdr: 1;           ///< Receive FIFO data request raw interrupt status
+            uint32_t rcrc: 1;           ///< Response CRC error raw interrupt status
+            uint32_t dcrc: 1;           ///< Data CRC error raw interrupt status
+            uint32_t rto: 1;            ///< Response timeout raw interrupt status
+            uint32_t drto: 1;           ///< Data read timeout raw interrupt status
+            uint32_t hto: 1;            ///< Data starvation-by-host timeout raw interrupt status
+            uint32_t frun: 1;           ///< FIFO underrun/overrun error raw interrupt status
+            uint32_t hle: 1;            ///< Hardware locked write error raw interrupt status
+            uint32_t sbi_bci: 1;        ///< Start bit error / busy clear raw interrupt status
+            uint32_t acd: 1;            ///< Auto command done raw interrupt status
+            uint32_t ebe: 1;            ///< End bit error / write no CRC raw interrupt status
+            uint32_t sdio: 16;          ///< SDIO raw interrupt status
+        };
+        uint32_t val;
+    } rintsts;                          ///< interrupts can be cleared by writing this register
+
+    union {
+        struct {
+            uint32_t fifo_rx_watermark: 1;  ///< FIFO reached receive watermark level
+            uint32_t fifo_tx_watermark: 1;  ///< FIFO reached transmit watermark level
+            uint32_t fifo_empty: 1;         ///< FIFO is empty
+            uint32_t fifo_full: 1;          ///< FIFO is full
+            uint32_t cmd_fsm_state: 4;      ///< command FSM state
+            uint32_t data3_status: 1;       ///< this bit reads 1 if card is present
+            uint32_t data_busy: 1;          ///< this bit reads 1 if card is busy
+            uint32_t data_fsm_busy: 1;      ///< this bit reads 1 if transmit/receive FSM is busy
+            uint32_t response_index: 6;     ///< index of the previous response
+            uint32_t fifo_count: 13;        ///< number of filled locations in the FIFO
+            uint32_t dma_ack: 1;            ///< DMA acknowledge signal
+            uint32_t dma_req: 1;            ///< DMA request signal
+        };
+        uint32_t val;
+    } status;
+
+    union {
+        struct {
+            uint32_t tx_watermark: 12;      ///< FIFO TX watermark level
+            uint32_t reserved1: 4;
+            uint32_t rx_watermark: 12;      ///< FIFO RX watermark level
+            uint32_t dw_dma_mts: 3;
+            uint32_t reserved2: 1;
+        };
+        uint32_t val;
+    } fifoth;
+
+    union {
+        struct {
+            uint32_t cards: 2;              ///< bit N reads 0 if card N is present
+            uint32_t reserved: 30;
+        };
+        uint32_t val;
+    } cdetect;
+
+    union {
+        struct {
+            uint32_t cards: 2;              ///< bit N reads 1 if card N is write protected
+            uint32_t reserved: 30;
+        };
+        uint32_t val;
+    } wrtprt;
+
+    uint32_t gpio;      ///< unused
+    uint32_t tcbcnt;    ///< transferred (to card) byte count
+    uint32_t tbbcnt;    ///< transferred from host to FIFO byte count
+
+    union {
+        struct {
+            uint32_t debounce_count: 24;    ///< number of host cycles used by debounce filter, typical time should be 5-25ms
+            uint32_t reserved: 8;
+        };
+    } debnce;
+
+    uint32_t usrid;     ///< user ID
+    uint32_t verid;     ///< IP block version
+    uint32_t hcon;      ///< compile-time IP configuration
+    uint32_t uhs;       ///< TBD
+
+    union {
+        struct {
+            uint32_t cards: 2;          ///< bit N resets card N, active low
+            uint32_t reserved: 30;
+        };
+    } rst_n;
+
+    uint32_t reserved_7c;
+
+    union {
+        struct {
+            uint32_t sw_reset: 1;       ///< set to reset DMA controller
+            uint32_t fb: 1;             ///< set if AHB master performs fixed burst transfers
+            uint32_t dsl: 5;            ///< descriptor skip length: number of words to skip between two unchained descriptors
+            uint32_t enable: 1;         ///< set to enable IDMAC
+            uint32_t pbl: 3;            ///< programmable burst length
+            uint32_t reserved: 21;
+        };
+        uint32_t val;
+    } bmod;
+
+    uint32_t pldmnd;                    ///< set any bit to resume IDMAC FSM from suspended state
+    sdmmc_desc_t* dbaddr;        ///< descriptor list base
+
+    union {
+        struct {
+            uint32_t ti: 1;         ///< transmit interrupt status
+            uint32_t ri: 1;         ///< receive interrupt status
+            uint32_t fbe: 1;        ///< fatal bus error
+            uint32_t reserved1: 1;
+            uint32_t du: 1;         ///< descriptor unavailable
+            uint32_t ces: 1;        ///< card error summary
+            uint32_t reserved2: 2;
+            uint32_t nis: 1;        ///< normal interrupt summary
+            uint32_t fbe_code: 3;   ///< code of fatal bus error
+            uint32_t fsm: 4;        ///< DMAC FSM state
+            uint32_t reserved3: 15;
+        };
+        uint32_t val;
+    } idsts;
+
+    union {
+        struct {
+            uint32_t ti: 1;         ///< transmit interrupt enable
+            uint32_t ri: 1;         ///< receive interrupt enable
+            uint32_t fbe: 1;        ///< fatal bus error interrupt enable
+            uint32_t reserved1: 1;
+            uint32_t du: 1;         ///< descriptor unavailable interrupt enable
+            uint32_t ces: 1;        ///< card error interrupt enable
+            uint32_t reserved2: 2;
+            uint32_t ni: 1;         ///< normal interrupt interrupt enable
+            uint32_t ai: 1;         ///< abnormal interrupt enable
+            uint32_t reserved3: 22;
+        };
+        uint32_t val;
+    } idinten;
+
+    uint32_t dscaddr;       ///< current host descriptor address
+    uint32_t dscaddrl;      ///< unused
+    uint32_t dscaddru;      ///< unused
+    uint32_t bufaddrl;      ///< unused
+    uint32_t bufaddru;      ///< unused
+    uint32_t reserved_a8[22];
+    uint32_t cardthrctl;
+    uint32_t back_end_power;
+    uint32_t uhs_reg_ext;
+    uint32_t emmc_ddr_reg;
+    uint32_t enable_shift;
+    uint32_t reserved_114[443];
+    union {
+        struct {
+            uint32_t phase_dout: 3;         ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
+            uint32_t phase_din: 3;          ///< phase of data input clock
+            uint32_t phase_core: 3;         ///< phase of the clock to SDMMC peripheral
+            uint32_t div_factor_p: 4;       ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
+            uint32_t div_factor_h: 4;       ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
+            uint32_t div_factor_m: 4;       ///< should be equal to div_factor_p
+        };
+        uint32_t val;
+    } clock;
+} sdmmc_dev_t;
+extern sdmmc_dev_t SDMMC;
+
+_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //_SOC_SDMMC_STRUCT_H_
diff --git a/components/soc/esp32s2beta/include/soc/sens_reg.h b/components/soc/esp32s2beta/include/soc/sens_reg.h
new file mode 100644
index 000000000..a00c59c9a
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/sens_reg.h
@@ -0,0 +1,1267 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENS_REG_H_
+#define _SOC_SENS_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SENS_SAR_READ_CTRL_REG          (DR_REG_SENS_BASE + 0x0000)
+/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */
+/*description: Invert SAR ADC1 data*/
+#define SENS_SAR1_DATA_INV  (BIT(28))
+#define SENS_SAR1_DATA_INV_M  (BIT(28))
+#define SENS_SAR1_DATA_INV_V  0x1
+#define SENS_SAR1_DATA_INV_S  28
+/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[27] ;default: 1'd0 ; */
+/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL  0: SAR ADC1 controlled by RTC ADC1 CTRL*/
+#define SENS_SAR1_DIG_FORCE  (BIT(27))
+#define SENS_SAR1_DIG_FORCE_M  (BIT(27))
+#define SENS_SAR1_DIG_FORCE_V  0x1
+#define SENS_SAR1_DIG_FORCE_S  27
+/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: */
+#define SENS_SAR1_SAMPLE_NUM  0x000000FF
+#define SENS_SAR1_SAMPLE_NUM_M  ((SENS_SAR1_SAMPLE_NUM_V)<<(SENS_SAR1_SAMPLE_NUM_S))
+#define SENS_SAR1_SAMPLE_NUM_V  0xFF
+#define SENS_SAR1_SAMPLE_NUM_S  19
+/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SENS_SAR1_CLK_GATED  (BIT(18))
+#define SENS_SAR1_CLK_GATED_M  (BIT(18))
+#define SENS_SAR1_CLK_GATED_V  0x1
+#define SENS_SAR1_CLK_GATED_S  18
+/* SENS_SAR1_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */
+/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width
+  11: for 12-bit width*/
+#define SENS_SAR1_SAMPLE_BIT  0x00000003
+#define SENS_SAR1_SAMPLE_BIT_M  ((SENS_SAR1_SAMPLE_BIT_V)<<(SENS_SAR1_SAMPLE_BIT_S))
+#define SENS_SAR1_SAMPLE_BIT_V  0x3
+#define SENS_SAR1_SAMPLE_BIT_S  16
+/* SENS_SAR1_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */
+/*description: sample cycles for SAR ADC1*/
+#define SENS_SAR1_SAMPLE_CYCLE  0x000000FF
+#define SENS_SAR1_SAMPLE_CYCLE_M  ((SENS_SAR1_SAMPLE_CYCLE_V)<<(SENS_SAR1_SAMPLE_CYCLE_S))
+#define SENS_SAR1_SAMPLE_CYCLE_V  0xFF
+#define SENS_SAR1_SAMPLE_CYCLE_S  8
+/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: clock divider*/
+#define SENS_SAR1_CLK_DIV  0x000000FF
+#define SENS_SAR1_CLK_DIV_M  ((SENS_SAR1_CLK_DIV_V)<<(SENS_SAR1_CLK_DIV_S))
+#define SENS_SAR1_CLK_DIV_V  0xFF
+#define SENS_SAR1_CLK_DIV_S  0
+
+#define SENS_SAR_READ_STATUS1_REG          (DR_REG_SENS_BASE + 0x0004)
+/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR1_READER_STATUS  0xFFFFFFFF
+#define SENS_SAR1_READER_STATUS_M  ((SENS_SAR1_READER_STATUS_V)<<(SENS_SAR1_READER_STATUS_S))
+#define SENS_SAR1_READER_STATUS_V  0xFFFFFFFF
+#define SENS_SAR1_READER_STATUS_S  0
+
+#define SENS_SAR_MEAS_WAIT1_REG          (DR_REG_SENS_BASE + 0x0008)
+/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT2  0x0000FFFF
+#define SENS_SAR_AMP_WAIT2_M  ((SENS_SAR_AMP_WAIT2_V)<<(SENS_SAR_AMP_WAIT2_S))
+#define SENS_SAR_AMP_WAIT2_V  0xFFFF
+#define SENS_SAR_AMP_WAIT2_S  16
+/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT1  0x0000FFFF
+#define SENS_SAR_AMP_WAIT1_M  ((SENS_SAR_AMP_WAIT1_V)<<(SENS_SAR_AMP_WAIT1_S))
+#define SENS_SAR_AMP_WAIT1_V  0xFFFF
+#define SENS_SAR_AMP_WAIT1_S  0
+
+#define SENS_SAR_MEAS_WAIT2_REG          (DR_REG_SENS_BASE + 0x000c)
+/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[27:20] ;default: 8'd2 ; */
+/*description: */
+#define SENS_SAR2_RSTB_WAIT  0x000000FF
+#define SENS_SAR2_RSTB_WAIT_M  ((SENS_SAR2_RSTB_WAIT_V)<<(SENS_SAR2_RSTB_WAIT_S))
+#define SENS_SAR2_RSTB_WAIT_V  0xFF
+#define SENS_SAR2_RSTB_WAIT_S  20
+/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
+/*description: */
+#define SENS_FORCE_XPD_SAR  0x00000003
+#define SENS_FORCE_XPD_SAR_M  ((SENS_FORCE_XPD_SAR_V)<<(SENS_FORCE_XPD_SAR_S))
+#define SENS_FORCE_XPD_SAR_V  0x3
+#define SENS_FORCE_XPD_SAR_S  18
+/* reserved for driver to check */
+#define SENS_FORCE_XPD_SAR_SW_M (BIT1)
+#define SENS_FORCE_XPD_SAR_FSM 0 // Use FSM to control power down
+#define SENS_FORCE_XPD_SAR_PD  2 // Force power down
+#define SENS_FORCE_XPD_SAR_PU  3 // Force power up
+/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
+/*description: */
+#define SENS_FORCE_XPD_AMP  0x00000003
+#define SENS_FORCE_XPD_AMP_M  ((SENS_FORCE_XPD_AMP_V)<<(SENS_FORCE_XPD_AMP_S))
+#define SENS_FORCE_XPD_AMP_V  0x3
+#define SENS_FORCE_XPD_AMP_S  16
+#define SENS_FORCE_XPD_AMP_FSM 0 // Use FSM to control power down
+#define SENS_FORCE_XPD_AMP_PD  2 // Force power down
+#define SENS_FORCE_XPD_AMP_PU  3 // Force power up
+/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */
+/*description: */
+#define SENS_SAR_AMP_WAIT3  0x0000FFFF
+#define SENS_SAR_AMP_WAIT3_M  ((SENS_SAR_AMP_WAIT3_V)<<(SENS_SAR_AMP_WAIT3_S))
+#define SENS_SAR_AMP_WAIT3_V  0xFFFF
+#define SENS_SAR_AMP_WAIT3_S  0
+
+#define SENS_SAR_MEAS_CTRL_REG          (DR_REG_SENS_BASE + 0x0010)
+/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */
+/*description: */
+#define SENS_SAR2_XPD_WAIT  0x000000FF
+#define SENS_SAR2_XPD_WAIT_M  ((SENS_SAR2_XPD_WAIT_V)<<(SENS_SAR2_XPD_WAIT_S))
+#define SENS_SAR2_XPD_WAIT_V  0xFF
+#define SENS_SAR2_XPD_WAIT_S  24
+/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[23:20] ;default: 4'b0000 ; */
+/*description: */
+#define SENS_SAR_RSTB_FSM  0x0000000F
+#define SENS_SAR_RSTB_FSM_M  ((SENS_SAR_RSTB_FSM_V)<<(SENS_SAR_RSTB_FSM_S))
+#define SENS_SAR_RSTB_FSM_V  0xF
+#define SENS_SAR_RSTB_FSM_S  20
+/* SENS_XPD_SAR_FSM : R/W ;bitpos:[19:16] ;default: 4'b0111 ; */
+/*description: */
+#define SENS_XPD_SAR_FSM  0x0000000F
+#define SENS_XPD_SAR_FSM_M  ((SENS_XPD_SAR_FSM_V)<<(SENS_XPD_SAR_FSM_S))
+#define SENS_XPD_SAR_FSM_V  0xF
+#define SENS_XPD_SAR_FSM_S  16
+/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FSM  0x0000000F
+#define SENS_AMP_SHORT_REF_GND_FSM_M  ((SENS_AMP_SHORT_REF_GND_FSM_V)<<(SENS_AMP_SHORT_REF_GND_FSM_S))
+#define SENS_AMP_SHORT_REF_GND_FSM_V  0xF
+#define SENS_AMP_SHORT_REF_GND_FSM_S  12
+/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[11:8] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FSM  0x0000000F
+#define SENS_AMP_SHORT_REF_FSM_M  ((SENS_AMP_SHORT_REF_FSM_V)<<(SENS_AMP_SHORT_REF_FSM_S))
+#define SENS_AMP_SHORT_REF_FSM_V  0xF
+#define SENS_AMP_SHORT_REF_FSM_S  8
+/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[7:4] ;default: 4'b1000 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FSM  0x0000000F
+#define SENS_AMP_RST_FB_FSM_M  ((SENS_AMP_RST_FB_FSM_V)<<(SENS_AMP_RST_FB_FSM_S))
+#define SENS_AMP_RST_FB_FSM_V  0xF
+#define SENS_AMP_RST_FB_FSM_S  4
+/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[3:0] ;default: 4'b1111 ; */
+/*description: */
+#define SENS_XPD_SAR_AMP_FSM  0x0000000F
+#define SENS_XPD_SAR_AMP_FSM_M  ((SENS_XPD_SAR_AMP_FSM_V)<<(SENS_XPD_SAR_AMP_FSM_S))
+#define SENS_XPD_SAR_AMP_FSM_V  0xF
+#define SENS_XPD_SAR_AMP_FSM_S  0
+
+#define SENS_SAR_READ_STATUS2_REG          (DR_REG_SENS_BASE + 0x0014)
+/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR2_READER_STATUS  0xFFFFFFFF
+#define SENS_SAR2_READER_STATUS_M  ((SENS_SAR2_READER_STATUS_V)<<(SENS_SAR2_READER_STATUS_S))
+#define SENS_SAR2_READER_STATUS_V  0xFFFFFFFF
+#define SENS_SAR2_READER_STATUS_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC0_REG          (DR_REG_SENS_BASE + 0x0018)
+/* SENS_SLEEP_CYCLES_S0 : R/W ;bitpos:[31:0] ;default: 32'd200 ; */
+/*description: sleep cycles for ULP-coprocessor timer*/
+#define SENS_SLEEP_CYCLES_S0  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S0_M  ((SENS_SLEEP_CYCLES_S0_V)<<(SENS_SLEEP_CYCLES_S0_S))
+#define SENS_SLEEP_CYCLES_S0_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S0_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC1_REG          (DR_REG_SENS_BASE + 0x001c)
+/* SENS_SLEEP_CYCLES_S1 : R/W ;bitpos:[31:0] ;default: 32'd100 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S1  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S1_M  ((SENS_SLEEP_CYCLES_S1_V)<<(SENS_SLEEP_CYCLES_S1_S))
+#define SENS_SLEEP_CYCLES_S1_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S1_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC2_REG          (DR_REG_SENS_BASE + 0x0020)
+/* SENS_SLEEP_CYCLES_S2 : R/W ;bitpos:[31:0] ;default: 32'd50 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S2  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S2_M  ((SENS_SLEEP_CYCLES_S2_V)<<(SENS_SLEEP_CYCLES_S2_S))
+#define SENS_SLEEP_CYCLES_S2_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S2_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC3_REG          (DR_REG_SENS_BASE + 0x0024)
+/* SENS_SLEEP_CYCLES_S3 : R/W ;bitpos:[31:0] ;default: 32'd40 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S3  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S3_M  ((SENS_SLEEP_CYCLES_S3_V)<<(SENS_SLEEP_CYCLES_S3_S))
+#define SENS_SLEEP_CYCLES_S3_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S3_S  0
+
+#define SENS_ULP_CP_SLEEP_CYC4_REG          (DR_REG_SENS_BASE + 0x0028)
+/* SENS_SLEEP_CYCLES_S4 : R/W ;bitpos:[31:0] ;default: 32'd20 ; */
+/*description: */
+#define SENS_SLEEP_CYCLES_S4  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S4_M  ((SENS_SLEEP_CYCLES_S4_V)<<(SENS_SLEEP_CYCLES_S4_S))
+#define SENS_SLEEP_CYCLES_S4_V  0xFFFFFFFF
+#define SENS_SLEEP_CYCLES_S4_S  0
+
+#define SENS_SAR_START_FORCE_REG          (DR_REG_SENS_BASE + 0x002c)
+/* SENS_SAR2_PWDET_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: N/A*/
+#define SENS_SAR2_PWDET_EN  (BIT(24))
+#define SENS_SAR2_PWDET_EN_M  (BIT(24))
+#define SENS_SAR2_PWDET_EN_V  0x1
+#define SENS_SAR2_PWDET_EN_S  24
+/* SENS_SAR1_STOP : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: stop SAR ADC1 conversion*/
+#define SENS_SAR1_STOP  (BIT(23))
+#define SENS_SAR1_STOP_M  (BIT(23))
+#define SENS_SAR1_STOP_V  0x1
+#define SENS_SAR1_STOP_S  23
+/* SENS_SAR2_STOP : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: stop SAR ADC2 conversion*/
+#define SENS_SAR2_STOP  (BIT(22))
+#define SENS_SAR2_STOP_M  (BIT(22))
+#define SENS_SAR2_STOP_V  0x1
+#define SENS_SAR2_STOP_S  22
+/* SENS_PC_INIT : R/W ;bitpos:[21:11] ;default: 11'b0 ; */
+/*description: initialized PC for ULP-coprocessor*/
+#define SENS_PC_INIT  0x000007FF
+#define SENS_PC_INIT_M  ((SENS_PC_INIT_V)<<(SENS_PC_INIT_S))
+#define SENS_PC_INIT_V  0x7FF
+#define SENS_PC_INIT_S  11
+/* SENS_SARCLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SARCLK_EN  (BIT(10))
+#define SENS_SARCLK_EN_M  (BIT(10))
+#define SENS_SARCLK_EN_V  0x1
+#define SENS_SARCLK_EN_S  10
+/* SENS_ULP_CP_START_TOP : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: Write 1 to start ULP-coprocessor  only active when reg_ulp_cp_force_start_top
+ = 1*/
+#define SENS_ULP_CP_START_TOP  (BIT(9))
+#define SENS_ULP_CP_START_TOP_M  (BIT(9))
+#define SENS_ULP_CP_START_TOP_V  0x1
+#define SENS_ULP_CP_START_TOP_S  9
+/* SENS_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: 1: ULP-coprocessor is started by SW  0: ULP-coprocessor is started by timer*/
+#define SENS_ULP_CP_FORCE_START_TOP  (BIT(8))
+#define SENS_ULP_CP_FORCE_START_TOP_M  (BIT(8))
+#define SENS_ULP_CP_FORCE_START_TOP_V  0x1
+#define SENS_ULP_CP_FORCE_START_TOP_S  8
+/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[7:5] ;default: 3'b0 ; */
+/*description: SAR2_PWDET_CCT  PA power detector capacitance tuning.*/
+#define SENS_SAR2_PWDET_CCT  0x00000007
+#define SENS_SAR2_PWDET_CCT_M  ((SENS_SAR2_PWDET_CCT_V)<<(SENS_SAR2_PWDET_CCT_S))
+#define SENS_SAR2_PWDET_CCT_V  0x7
+#define SENS_SAR2_PWDET_CCT_S  5
+/* SENS_SAR2_EN_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: SAR2_EN_TEST  only active when reg_sar2_dig_force = 0*/
+#define SENS_SAR2_EN_TEST  (BIT(4))
+#define SENS_SAR2_EN_TEST_M  (BIT(4))
+#define SENS_SAR2_EN_TEST_V  0x1
+#define SENS_SAR2_EN_TEST_S  4
+/* SENS_SAR2_BIT_WIDTH : R/W ;bitpos:[3:2] ;default: 2'b11 ; */
+/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
+#define SENS_SAR2_BIT_WIDTH  0x00000003
+#define SENS_SAR2_BIT_WIDTH_M  ((SENS_SAR2_BIT_WIDTH_V)<<(SENS_SAR2_BIT_WIDTH_S))
+#define SENS_SAR2_BIT_WIDTH_V  0x3
+#define SENS_SAR2_BIT_WIDTH_S  2
+/* SENS_SAR1_BIT_WIDTH : R/W ;bitpos:[1:0] ;default: 2'b11 ; */
+/*description: 00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
+#define SENS_SAR1_BIT_WIDTH  0x00000003
+#define SENS_SAR1_BIT_WIDTH_M  ((SENS_SAR1_BIT_WIDTH_V)<<(SENS_SAR1_BIT_WIDTH_S))
+#define SENS_SAR1_BIT_WIDTH_V  0x3
+#define SENS_SAR1_BIT_WIDTH_S  0
+
+#define SENS_SAR_MEM_WR_CTRL_REG          (DR_REG_SENS_BASE + 0x0030)
+/* SENS_ULP_CP_CLK_FO : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: ulp coprocessor clk force on*/
+#define SENS_ULP_CP_CLK_FO  (BIT(23))
+#define SENS_ULP_CP_CLK_FO_M  (BIT(23))
+#define SENS_ULP_CP_CLK_FO_V  0x1
+#define SENS_ULP_CP_CLK_FO_S  23
+/* SENS_RTC_MEM_WR_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */
+/*description: */
+#define SENS_RTC_MEM_WR_OFFST_CLR  (BIT(22))
+#define SENS_RTC_MEM_WR_OFFST_CLR_M  (BIT(22))
+#define SENS_RTC_MEM_WR_OFFST_CLR_V  0x1
+#define SENS_RTC_MEM_WR_OFFST_CLR_S  22
+/* SENS_MEM_WR_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */
+/*description: */
+#define SENS_MEM_WR_ADDR_SIZE  0x000007FF
+#define SENS_MEM_WR_ADDR_SIZE_M  ((SENS_MEM_WR_ADDR_SIZE_V)<<(SENS_MEM_WR_ADDR_SIZE_S))
+#define SENS_MEM_WR_ADDR_SIZE_V  0x7FF
+#define SENS_MEM_WR_ADDR_SIZE_S  11
+/* SENS_MEM_WR_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */
+/*description: */
+#define SENS_MEM_WR_ADDR_INIT  0x000007FF
+#define SENS_MEM_WR_ADDR_INIT_M  ((SENS_MEM_WR_ADDR_INIT_V)<<(SENS_MEM_WR_ADDR_INIT_S))
+#define SENS_MEM_WR_ADDR_INIT_V  0x7FF
+#define SENS_MEM_WR_ADDR_INIT_S  0
+
+#define SENS_SAR_ATTEN1_REG          (DR_REG_SENS_BASE + 0x0034)
+/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
+#define SENS_SAR1_ATTEN  0xFFFFFFFF
+#define SENS_SAR1_ATTEN_M  ((SENS_SAR1_ATTEN_V)<<(SENS_SAR1_ATTEN_S))
+#define SENS_SAR1_ATTEN_V  0xFFFFFFFF
+#define SENS_SAR1_ATTEN_S  0
+#define SENS_SAR1_ATTEN_VAL_MASK   0x3
+#define SENS_SAR2_ATTEN_VAL_MASK   0x3
+
+#define SENS_SAR_ATTEN2_REG          (DR_REG_SENS_BASE + 0x0038)
+/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
+/*description: 2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
+#define SENS_SAR2_ATTEN  0xFFFFFFFF
+#define SENS_SAR2_ATTEN_M  ((SENS_SAR2_ATTEN_V)<<(SENS_SAR2_ATTEN_S))
+#define SENS_SAR2_ATTEN_V  0xFFFFFFFF
+#define SENS_SAR2_ATTEN_S  0
+
+#define SENS_SAR_SLAVE_ADDR1_REG          (DR_REG_SENS_BASE + 0x003c)
+/* SENS_SARADC_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */
+/*description: */
+#define SENS_SARADC_MEAS_STATUS  0x000000FF
+#define SENS_SARADC_MEAS_STATUS_M  ((SENS_SARADC_MEAS_STATUS_V)<<(SENS_SARADC_MEAS_STATUS_S))
+#define SENS_SARADC_MEAS_STATUS_V  0xFF
+#define SENS_SARADC_MEAS_STATUS_S  22
+/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR0  0x000007FF
+#define SENS_I2C_SLAVE_ADDR0_M  ((SENS_I2C_SLAVE_ADDR0_V)<<(SENS_I2C_SLAVE_ADDR0_S))
+#define SENS_I2C_SLAVE_ADDR0_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR0_S  11
+/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR1  0x000007FF
+#define SENS_I2C_SLAVE_ADDR1_M  ((SENS_I2C_SLAVE_ADDR1_V)<<(SENS_I2C_SLAVE_ADDR1_S))
+#define SENS_I2C_SLAVE_ADDR1_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR1_S  0
+
+#define SENS_SAR_SLAVE_ADDR2_REG          (DR_REG_SENS_BASE + 0x0040)
+/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR2  0x000007FF
+#define SENS_I2C_SLAVE_ADDR2_M  ((SENS_I2C_SLAVE_ADDR2_V)<<(SENS_I2C_SLAVE_ADDR2_S))
+#define SENS_I2C_SLAVE_ADDR2_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR2_S  11
+/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR3  0x000007FF
+#define SENS_I2C_SLAVE_ADDR3_M  ((SENS_I2C_SLAVE_ADDR3_V)<<(SENS_I2C_SLAVE_ADDR3_S))
+#define SENS_I2C_SLAVE_ADDR3_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR3_S  0
+
+#define SENS_SAR_SLAVE_ADDR3_REG          (DR_REG_SENS_BASE + 0x0044)
+/* SENS_TSENS_RDY_OUT : RO ;bitpos:[30] ;default: 1'h0 ; */
+/*description: indicate temperature sensor out ready*/
+#define SENS_TSENS_RDY_OUT  (BIT(30))
+#define SENS_TSENS_RDY_OUT_M  (BIT(30))
+#define SENS_TSENS_RDY_OUT_V  0x1
+#define SENS_TSENS_RDY_OUT_S  30
+/* SENS_TSENS_OUT : RO ;bitpos:[29:22] ;default: 8'h0 ; */
+/*description: temperature sensor data out*/
+#define SENS_TSENS_OUT  0x000000FF
+#define SENS_TSENS_OUT_M  ((SENS_TSENS_OUT_V)<<(SENS_TSENS_OUT_S))
+#define SENS_TSENS_OUT_V  0xFF
+#define SENS_TSENS_OUT_S  22
+/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR4  0x000007FF
+#define SENS_I2C_SLAVE_ADDR4_M  ((SENS_I2C_SLAVE_ADDR4_V)<<(SENS_I2C_SLAVE_ADDR4_S))
+#define SENS_I2C_SLAVE_ADDR4_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR4_S  11
+/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR5  0x000007FF
+#define SENS_I2C_SLAVE_ADDR5_M  ((SENS_I2C_SLAVE_ADDR5_V)<<(SENS_I2C_SLAVE_ADDR5_S))
+#define SENS_I2C_SLAVE_ADDR5_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR5_S  0
+
+#define SENS_SAR_SLAVE_ADDR4_REG          (DR_REG_SENS_BASE + 0x0048)
+/* SENS_I2C_DONE : RO ;bitpos:[30] ;default: 1'h0 ; */
+/*description: indicate I2C done*/
+#define SENS_I2C_DONE  (BIT(30))
+#define SENS_I2C_DONE_M  (BIT(30))
+#define SENS_I2C_DONE_V  0x1
+#define SENS_I2C_DONE_S  30
+/* SENS_I2C_RDATA : RO ;bitpos:[29:22] ;default: 8'h0 ; */
+/*description: I2C read data*/
+#define SENS_I2C_RDATA  0x000000FF
+#define SENS_I2C_RDATA_M  ((SENS_I2C_RDATA_V)<<(SENS_I2C_RDATA_S))
+#define SENS_I2C_RDATA_V  0xFF
+#define SENS_I2C_RDATA_S  22
+/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR6  0x000007FF
+#define SENS_I2C_SLAVE_ADDR6_M  ((SENS_I2C_SLAVE_ADDR6_V)<<(SENS_I2C_SLAVE_ADDR6_S))
+#define SENS_I2C_SLAVE_ADDR6_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR6_S  11
+/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SENS_I2C_SLAVE_ADDR7  0x000007FF
+#define SENS_I2C_SLAVE_ADDR7_M  ((SENS_I2C_SLAVE_ADDR7_V)<<(SENS_I2C_SLAVE_ADDR7_S))
+#define SENS_I2C_SLAVE_ADDR7_V  0x7FF
+#define SENS_I2C_SLAVE_ADDR7_S  0
+
+#define SENS_SAR_TSENS_CTRL_REG          (DR_REG_SENS_BASE + 0x004c)
+/* SENS_TSENS_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: select saradc_reg 0: select efuse*/
+#define SENS_TSENS_FORCE  (BIT(31))
+#define SENS_TSENS_FORCE_M  (BIT(31))
+#define SENS_TSENS_FORCE_V  0x1
+#define SENS_TSENS_FORCE_S  31
+/* SENS_TSENS_DOS : R/W ;bitpos:[30:27] ;default: 4'd7 ; */
+/*description: Temperature sensor calibration bits*/
+#define SENS_TSENS_DOS  0x0000000F
+#define SENS_TSENS_DOS_M  ((SENS_TSENS_DOS_V)<<(SENS_TSENS_DOS_S))
+#define SENS_TSENS_DOS_V  0xF
+#define SENS_TSENS_DOS_S  27
+/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: temperature sensor dump out  only active when reg_tsens_power_up_force = 1*/
+#define SENS_TSENS_DUMP_OUT  (BIT(26))
+#define SENS_TSENS_DUMP_OUT_M  (BIT(26))
+#define SENS_TSENS_DUMP_OUT_V  0x1
+#define SENS_TSENS_DUMP_OUT_S  26
+/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: dump out & power up controlled by SW  0: by FSM*/
+#define SENS_TSENS_POWER_UP_FORCE  (BIT(25))
+#define SENS_TSENS_POWER_UP_FORCE_M  (BIT(25))
+#define SENS_TSENS_POWER_UP_FORCE_V  0x1
+#define SENS_TSENS_POWER_UP_FORCE_S  25
+/* SENS_TSENS_POWER_UP : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: temperature sensor power up*/
+#define SENS_TSENS_POWER_UP  (BIT(24))
+#define SENS_TSENS_POWER_UP_M  (BIT(24))
+#define SENS_TSENS_POWER_UP_V  0x1
+#define SENS_TSENS_POWER_UP_S  24
+/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[23:16] ;default: 8'd6 ; */
+/*description: temperature sensor clock divider*/
+#define SENS_TSENS_CLK_DIV  0x000000FF
+#define SENS_TSENS_CLK_DIV_M  ((SENS_TSENS_CLK_DIV_V)<<(SENS_TSENS_CLK_DIV_S))
+#define SENS_TSENS_CLK_DIV_V  0xFF
+#define SENS_TSENS_CLK_DIV_S  16
+/* SENS_TSENS_IN_INV : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: invert temperature sensor data*/
+#define SENS_TSENS_IN_INV  (BIT(15))
+#define SENS_TSENS_IN_INV_M  (BIT(15))
+#define SENS_TSENS_IN_INV_V  0x1
+#define SENS_TSENS_IN_INV_S  15
+/* SENS_TSENS_CLK_GATED : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define SENS_TSENS_CLK_GATED  (BIT(14))
+#define SENS_TSENS_CLK_GATED_M  (BIT(14))
+#define SENS_TSENS_CLK_GATED_V  0x1
+#define SENS_TSENS_CLK_GATED_S  14
+/* SENS_TSENS_CLK_INV : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define SENS_TSENS_CLK_INV  (BIT(13))
+#define SENS_TSENS_CLK_INV_M  (BIT(13))
+#define SENS_TSENS_CLK_INV_V  0x1
+#define SENS_TSENS_CLK_INV_S  13
+/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SENS_TSENS_XPD_FORCE  (BIT(12))
+#define SENS_TSENS_XPD_FORCE_M  (BIT(12))
+#define SENS_TSENS_XPD_FORCE_V  0x1
+#define SENS_TSENS_XPD_FORCE_S  12
+/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */
+/*description: */
+#define SENS_TSENS_XPD_WAIT  0x00000FFF
+#define SENS_TSENS_XPD_WAIT_M  ((SENS_TSENS_XPD_WAIT_V)<<(SENS_TSENS_XPD_WAIT_S))
+#define SENS_TSENS_XPD_WAIT_V  0xFFF
+#define SENS_TSENS_XPD_WAIT_S  0
+
+#define SENS_SAR_I2C_CTRL_REG          (DR_REG_SENS_BASE + 0x0050)
+/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: I2C started by SW  0: I2C started by FSM*/
+#define SENS_SAR_I2C_START_FORCE  (BIT(29))
+#define SENS_SAR_I2C_START_FORCE_M  (BIT(29))
+#define SENS_SAR_I2C_START_FORCE_V  0x1
+#define SENS_SAR_I2C_START_FORCE_S  29
+/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: start I2C  only active when reg_sar_i2c_start_force = 1*/
+#define SENS_SAR_I2C_START  (BIT(28))
+#define SENS_SAR_I2C_START_M  (BIT(28))
+#define SENS_SAR_I2C_START_V  0x1
+#define SENS_SAR_I2C_START_S  28
+/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */
+/*description: I2C control data  only active when reg_sar_i2c_start_force = 1*/
+#define SENS_SAR_I2C_CTRL  0x0FFFFFFF
+#define SENS_SAR_I2C_CTRL_M  ((SENS_SAR_I2C_CTRL_V)<<(SENS_SAR_I2C_CTRL_S))
+#define SENS_SAR_I2C_CTRL_V  0xFFFFFFF
+#define SENS_SAR_I2C_CTRL_S  0
+
+#define SENS_SAR_MEAS_START1_REG          (DR_REG_SENS_BASE + 0x0054)
+/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW  0: SAR ADC1
+ pad enable bitmap is controlled by ULP-coprocessor*/
+#define SENS_SAR1_EN_PAD_FORCE  (BIT(31))
+#define SENS_SAR1_EN_PAD_FORCE_M  (BIT(31))
+#define SENS_SAR1_EN_PAD_FORCE_V  0x1
+#define SENS_SAR1_EN_PAD_FORCE_S  31
+/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
+/*description: SAR ADC1 pad enable bitmap  only active when reg_sar1_en_pad_force = 1*/
+#define SENS_SAR1_EN_PAD  0x00000FFF
+#define SENS_SAR1_EN_PAD_M  ((SENS_SAR1_EN_PAD_V)<<(SENS_SAR1_EN_PAD_S))
+#define SENS_SAR1_EN_PAD_V  0xFFF
+#define SENS_SAR1_EN_PAD_S  19
+/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SAR ADC1 controller (in RTC) is started by SW  0: SAR ADC1
+ controller is started by ULP-coprocessor*/
+#define SENS_MEAS1_START_FORCE  (BIT(18))
+#define SENS_MEAS1_START_FORCE_M  (BIT(18))
+#define SENS_MEAS1_START_FORCE_V  0x1
+#define SENS_MEAS1_START_FORCE_S  18
+/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: SAR ADC1 controller (in RTC) starts conversion  only active when
+ reg_meas1_start_force = 1*/
+#define SENS_MEAS1_START_SAR  (BIT(17))
+#define SENS_MEAS1_START_SAR_M  (BIT(17))
+#define SENS_MEAS1_START_SAR_V  0x1
+#define SENS_MEAS1_START_SAR_S  17
+/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: SAR ADC1 conversion done indication*/
+#define SENS_MEAS1_DONE_SAR  (BIT(16))
+#define SENS_MEAS1_DONE_SAR_M  (BIT(16))
+#define SENS_MEAS1_DONE_SAR_V  0x1
+#define SENS_MEAS1_DONE_SAR_S  16
+/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: SAR ADC1 data*/
+#define SENS_MEAS1_DATA_SAR  0x0000FFFF
+#define SENS_MEAS1_DATA_SAR_M  ((SENS_MEAS1_DATA_SAR_V)<<(SENS_MEAS1_DATA_SAR_S))
+#define SENS_MEAS1_DATA_SAR_V  0xFFFF
+#define SENS_MEAS1_DATA_SAR_S  0
+
+#define SENS_SAR_TOUCH_CTRL1_REG          (DR_REG_SENS_BASE + 0x0058)
+/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: 1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled
+ by FSM in ULP-coprocessor*/
+#define SENS_HALL_PHASE_FORCE  (BIT(27))
+#define SENS_HALL_PHASE_FORCE_M  (BIT(27))
+#define SENS_HALL_PHASE_FORCE_V  0x1
+#define SENS_HALL_PHASE_FORCE_S  27
+/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by
+ FSM in ULP-coprocessor*/
+#define SENS_XPD_HALL_FORCE  (BIT(26))
+#define SENS_XPD_HALL_FORCE_M  (BIT(26))
+#define SENS_XPD_HALL_FORCE_V  0x1
+#define SENS_XPD_HALL_FORCE_S  26
+/* SENS_TOUCH_OUT_1EN : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: 1: wakeup interrupt is generated if SET1 is “touched”  0:
+ wakeup interrupt is generated only if SET1 & SET2 is both “touched”*/
+#define SENS_TOUCH_OUT_1EN  (BIT(25))
+#define SENS_TOUCH_OUT_1EN_M  (BIT(25))
+#define SENS_TOUCH_OUT_1EN_V  0x1
+#define SENS_TOUCH_OUT_1EN_S  25
+/* SENS_TOUCH_OUT_SEL : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: when the counter is greater then the threshold  the touch
+ pad is considered as “touched”  0: when the counter is less than the threshold  the touch pad is considered as “touched”*/
+#define SENS_TOUCH_OUT_SEL  (BIT(24))
+#define SENS_TOUCH_OUT_SEL_M  (BIT(24))
+#define SENS_TOUCH_OUT_SEL_V  0x1
+#define SENS_TOUCH_OUT_SEL_S  24
+/* SENS_TOUCH_XPD_WAIT : R/W ;bitpos:[23:16] ;default: 8'h4 ; */
+/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
+#define SENS_TOUCH_XPD_WAIT  0x000000FF
+#define SENS_TOUCH_XPD_WAIT_M  ((SENS_TOUCH_XPD_WAIT_V)<<(SENS_TOUCH_XPD_WAIT_S))
+#define SENS_TOUCH_XPD_WAIT_V  0xFF
+#define SENS_TOUCH_XPD_WAIT_S  16
+/* SENS_TOUCH_MEAS_DELAY : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: the meas length (in 8MHz)*/
+#define SENS_TOUCH_MEAS_DELAY  0x0000FFFF
+#define SENS_TOUCH_MEAS_DELAY_M  ((SENS_TOUCH_MEAS_DELAY_V)<<(SENS_TOUCH_MEAS_DELAY_S))
+#define SENS_TOUCH_MEAS_DELAY_V  0xFFFF
+#define SENS_TOUCH_MEAS_DELAY_S  0
+
+#define SENS_SAR_TOUCH_THRES1_REG          (DR_REG_SENS_BASE + 0x005c)
+/* SENS_TOUCH_OUT_TH0 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 0*/
+#define SENS_TOUCH_OUT_TH0  0x0000FFFF
+#define SENS_TOUCH_OUT_TH0_M  ((SENS_TOUCH_OUT_TH0_V)<<(SENS_TOUCH_OUT_TH0_S))
+#define SENS_TOUCH_OUT_TH0_V  0xFFFF
+#define SENS_TOUCH_OUT_TH0_S  16
+/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 1*/
+#define SENS_TOUCH_OUT_TH1  0x0000FFFF
+#define SENS_TOUCH_OUT_TH1_M  ((SENS_TOUCH_OUT_TH1_V)<<(SENS_TOUCH_OUT_TH1_S))
+#define SENS_TOUCH_OUT_TH1_V  0xFFFF
+#define SENS_TOUCH_OUT_TH1_S  0
+
+#define SENS_SAR_TOUCH_THRES2_REG          (DR_REG_SENS_BASE + 0x0060)
+/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 2*/
+#define SENS_TOUCH_OUT_TH2  0x0000FFFF
+#define SENS_TOUCH_OUT_TH2_M  ((SENS_TOUCH_OUT_TH2_V)<<(SENS_TOUCH_OUT_TH2_S))
+#define SENS_TOUCH_OUT_TH2_V  0xFFFF
+#define SENS_TOUCH_OUT_TH2_S  16
+/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 3*/
+#define SENS_TOUCH_OUT_TH3  0x0000FFFF
+#define SENS_TOUCH_OUT_TH3_M  ((SENS_TOUCH_OUT_TH3_V)<<(SENS_TOUCH_OUT_TH3_S))
+#define SENS_TOUCH_OUT_TH3_V  0xFFFF
+#define SENS_TOUCH_OUT_TH3_S  0
+
+#define SENS_SAR_TOUCH_THRES3_REG          (DR_REG_SENS_BASE + 0x0064)
+/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 4*/
+#define SENS_TOUCH_OUT_TH4  0x0000FFFF
+#define SENS_TOUCH_OUT_TH4_M  ((SENS_TOUCH_OUT_TH4_V)<<(SENS_TOUCH_OUT_TH4_S))
+#define SENS_TOUCH_OUT_TH4_V  0xFFFF
+#define SENS_TOUCH_OUT_TH4_S  16
+/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 5*/
+#define SENS_TOUCH_OUT_TH5  0x0000FFFF
+#define SENS_TOUCH_OUT_TH5_M  ((SENS_TOUCH_OUT_TH5_V)<<(SENS_TOUCH_OUT_TH5_S))
+#define SENS_TOUCH_OUT_TH5_V  0xFFFF
+#define SENS_TOUCH_OUT_TH5_S  0
+
+#define SENS_SAR_TOUCH_THRES4_REG          (DR_REG_SENS_BASE + 0x0068)
+/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 6*/
+#define SENS_TOUCH_OUT_TH6  0x0000FFFF
+#define SENS_TOUCH_OUT_TH6_M  ((SENS_TOUCH_OUT_TH6_V)<<(SENS_TOUCH_OUT_TH6_S))
+#define SENS_TOUCH_OUT_TH6_V  0xFFFF
+#define SENS_TOUCH_OUT_TH6_S  16
+/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 7*/
+#define SENS_TOUCH_OUT_TH7  0x0000FFFF
+#define SENS_TOUCH_OUT_TH7_M  ((SENS_TOUCH_OUT_TH7_V)<<(SENS_TOUCH_OUT_TH7_S))
+#define SENS_TOUCH_OUT_TH7_V  0xFFFF
+#define SENS_TOUCH_OUT_TH7_S  0
+
+#define SENS_SAR_TOUCH_THRES5_REG          (DR_REG_SENS_BASE + 0x006c)
+/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 8*/
+#define SENS_TOUCH_OUT_TH8  0x0000FFFF
+#define SENS_TOUCH_OUT_TH8_M  ((SENS_TOUCH_OUT_TH8_V)<<(SENS_TOUCH_OUT_TH8_S))
+#define SENS_TOUCH_OUT_TH8_V  0xFFFF
+#define SENS_TOUCH_OUT_TH8_S  16
+/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the threshold for touch pad 9*/
+#define SENS_TOUCH_OUT_TH9  0x0000FFFF
+#define SENS_TOUCH_OUT_TH9_M  ((SENS_TOUCH_OUT_TH9_V)<<(SENS_TOUCH_OUT_TH9_S))
+#define SENS_TOUCH_OUT_TH9_V  0xFFFF
+#define SENS_TOUCH_OUT_TH9_S  0
+
+#define SENS_SAR_TOUCH_OUT1_REG          (DR_REG_SENS_BASE + 0x0070)
+/* SENS_TOUCH_MEAS_OUT0 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 0*/
+#define SENS_TOUCH_MEAS_OUT0  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT0_M  ((SENS_TOUCH_MEAS_OUT0_V)<<(SENS_TOUCH_MEAS_OUT0_S))
+#define SENS_TOUCH_MEAS_OUT0_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT0_S  16
+/* SENS_TOUCH_MEAS_OUT1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 1*/
+#define SENS_TOUCH_MEAS_OUT1  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT1_M  ((SENS_TOUCH_MEAS_OUT1_V)<<(SENS_TOUCH_MEAS_OUT1_S))
+#define SENS_TOUCH_MEAS_OUT1_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT1_S  0
+
+#define SENS_SAR_TOUCH_OUT2_REG          (DR_REG_SENS_BASE + 0x0074)
+/* SENS_TOUCH_MEAS_OUT2 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 2*/
+#define SENS_TOUCH_MEAS_OUT2  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT2_M  ((SENS_TOUCH_MEAS_OUT2_V)<<(SENS_TOUCH_MEAS_OUT2_S))
+#define SENS_TOUCH_MEAS_OUT2_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT2_S  16
+/* SENS_TOUCH_MEAS_OUT3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 3*/
+#define SENS_TOUCH_MEAS_OUT3  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT3_M  ((SENS_TOUCH_MEAS_OUT3_V)<<(SENS_TOUCH_MEAS_OUT3_S))
+#define SENS_TOUCH_MEAS_OUT3_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT3_S  0
+
+#define SENS_SAR_TOUCH_OUT3_REG          (DR_REG_SENS_BASE + 0x0078)
+/* SENS_TOUCH_MEAS_OUT4 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 4*/
+#define SENS_TOUCH_MEAS_OUT4  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT4_M  ((SENS_TOUCH_MEAS_OUT4_V)<<(SENS_TOUCH_MEAS_OUT4_S))
+#define SENS_TOUCH_MEAS_OUT4_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT4_S  16
+/* SENS_TOUCH_MEAS_OUT5 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 5*/
+#define SENS_TOUCH_MEAS_OUT5  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT5_M  ((SENS_TOUCH_MEAS_OUT5_V)<<(SENS_TOUCH_MEAS_OUT5_S))
+#define SENS_TOUCH_MEAS_OUT5_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT5_S  0
+
+#define SENS_SAR_TOUCH_OUT4_REG          (DR_REG_SENS_BASE + 0x007c)
+/* SENS_TOUCH_MEAS_OUT6 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 6*/
+#define SENS_TOUCH_MEAS_OUT6  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT6_M  ((SENS_TOUCH_MEAS_OUT6_V)<<(SENS_TOUCH_MEAS_OUT6_S))
+#define SENS_TOUCH_MEAS_OUT6_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT6_S  16
+/* SENS_TOUCH_MEAS_OUT7 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 7*/
+#define SENS_TOUCH_MEAS_OUT7  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT7_M  ((SENS_TOUCH_MEAS_OUT7_V)<<(SENS_TOUCH_MEAS_OUT7_S))
+#define SENS_TOUCH_MEAS_OUT7_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT7_S  0
+
+#define SENS_SAR_TOUCH_OUT5_REG          (DR_REG_SENS_BASE + 0x0080)
+/* SENS_TOUCH_MEAS_OUT8 : RO ;bitpos:[31:16] ;default: 16'h0 ; */
+/*description: the counter for touch pad 8*/
+#define SENS_TOUCH_MEAS_OUT8  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT8_M  ((SENS_TOUCH_MEAS_OUT8_V)<<(SENS_TOUCH_MEAS_OUT8_S))
+#define SENS_TOUCH_MEAS_OUT8_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT8_S  16
+/* SENS_TOUCH_MEAS_OUT9 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: the counter for touch pad 9*/
+#define SENS_TOUCH_MEAS_OUT9  0x0000FFFF
+#define SENS_TOUCH_MEAS_OUT9_M  ((SENS_TOUCH_MEAS_OUT9_V)<<(SENS_TOUCH_MEAS_OUT9_S))
+#define SENS_TOUCH_MEAS_OUT9_V  0xFFFF
+#define SENS_TOUCH_MEAS_OUT9_S  0
+
+#define SENS_SAR_TOUCH_CTRL2_REG          (DR_REG_SENS_BASE + 0x0084)
+/* SENS_TOUCH_MEAS_EN_CLR : WO ;bitpos:[30] ;default: 1'h0 ; */
+/*description: to clear reg_touch_meas_en*/
+#define SENS_TOUCH_MEAS_EN_CLR  (BIT(30))
+#define SENS_TOUCH_MEAS_EN_CLR_M  (BIT(30))
+#define SENS_TOUCH_MEAS_EN_CLR_V  0x1
+#define SENS_TOUCH_MEAS_EN_CLR_S  30
+/* SENS_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[29:14] ;default: 16'h100 ; */
+/*description: sleep cycles for timer*/
+#define SENS_TOUCH_SLEEP_CYCLES  0x0000FFFF
+#define SENS_TOUCH_SLEEP_CYCLES_M  ((SENS_TOUCH_SLEEP_CYCLES_V)<<(SENS_TOUCH_SLEEP_CYCLES_S))
+#define SENS_TOUCH_SLEEP_CYCLES_V  0xFFFF
+#define SENS_TOUCH_SLEEP_CYCLES_S  14
+/* SENS_TOUCH_START_FORCE : R/W ;bitpos:[13] ;default: 1'h0 ; */
+/*description: 1: to start touch fsm by SW  0: to start touch fsm by timer*/
+#define SENS_TOUCH_START_FORCE  (BIT(13))
+#define SENS_TOUCH_START_FORCE_M  (BIT(13))
+#define SENS_TOUCH_START_FORCE_V  0x1
+#define SENS_TOUCH_START_FORCE_S  13
+/* SENS_TOUCH_START_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: 1: start touch fsm  valid when reg_touch_start_force is set*/
+#define SENS_TOUCH_START_EN  (BIT(12))
+#define SENS_TOUCH_START_EN_M  (BIT(12))
+#define SENS_TOUCH_START_EN_V  0x1
+#define SENS_TOUCH_START_EN_S  12
+/* SENS_TOUCH_START_FSM_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm  0: TOUCH_START
+ & TOUCH_XPD is controlled by registers*/
+#define SENS_TOUCH_START_FSM_EN  (BIT(11))
+#define SENS_TOUCH_START_FSM_EN_M  (BIT(11))
+#define SENS_TOUCH_START_FSM_EN_V  0x1
+#define SENS_TOUCH_START_FSM_EN_S  11
+/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[10] ;default: 1'h0 ; */
+/*description: fsm set 1 to indicate touch touch meas is done*/
+#define SENS_TOUCH_MEAS_DONE  (BIT(10))
+#define SENS_TOUCH_MEAS_DONE_M  (BIT(10))
+#define SENS_TOUCH_MEAS_DONE_V  0x1
+#define SENS_TOUCH_MEAS_DONE_S  10
+/* SENS_TOUCH_MEAS_EN : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: 10-bit register to indicate which pads are “touched”*/
+#define SENS_TOUCH_MEAS_EN  0x000003FF
+#define SENS_TOUCH_MEAS_EN_M  ((SENS_TOUCH_MEAS_EN_V)<<(SENS_TOUCH_MEAS_EN_S))
+#define SENS_TOUCH_MEAS_EN_V  0x3FF
+#define SENS_TOUCH_MEAS_EN_S  0
+
+#define SENS_SAR_TOUCH_ENABLE_REG          (DR_REG_SENS_BASE + 0x008c)
+/* SENS_TOUCH_PAD_OUTEN1 : R/W ;bitpos:[29:20] ;default: 10'h3ff ; */
+/*description: Bitmap defining SET1 for generating wakeup interrupt. SET1 is
+ “touched” only if at least one of touch pad in SET1 is “touched”.*/
+#define SENS_TOUCH_PAD_OUTEN1  0x000003FF
+#define SENS_TOUCH_PAD_OUTEN1_M  ((SENS_TOUCH_PAD_OUTEN1_V)<<(SENS_TOUCH_PAD_OUTEN1_S))
+#define SENS_TOUCH_PAD_OUTEN1_V  0x3FF
+#define SENS_TOUCH_PAD_OUTEN1_S  20
+/* SENS_TOUCH_PAD_OUTEN2 : R/W ;bitpos:[19:10] ;default: 10'h3ff ; */
+/*description: Bitmap defining SET2 for generating wakeup interrupt. SET2 is
+ “touched” only if at least one of touch pad in SET2 is “touched”.*/
+#define SENS_TOUCH_PAD_OUTEN2  0x000003FF
+#define SENS_TOUCH_PAD_OUTEN2_M  ((SENS_TOUCH_PAD_OUTEN2_V)<<(SENS_TOUCH_PAD_OUTEN2_S))
+#define SENS_TOUCH_PAD_OUTEN2_V  0x3FF
+#define SENS_TOUCH_PAD_OUTEN2_S  10
+/* SENS_TOUCH_PAD_WORKEN : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
+/*description: Bitmap defining the working set during the measurement.*/
+#define SENS_TOUCH_PAD_WORKEN  0x000003FF
+#define SENS_TOUCH_PAD_WORKEN_M  ((SENS_TOUCH_PAD_WORKEN_V)<<(SENS_TOUCH_PAD_WORKEN_S))
+#define SENS_TOUCH_PAD_WORKEN_V  0x3FF
+#define SENS_TOUCH_PAD_WORKEN_S  0
+
+#define SENS_SAR_TOUCH_CTRL3_REG          (DR_REG_SENS_BASE + 0x0090)
+/* SENS_TOUCH_MEAS_RAW : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: touch sensor raw result*/
+#define SENS_TOUCH_MEAS_RAW  0x000003FF
+#define SENS_TOUCH_MEAS_RAW_M  ((SENS_TOUCH_MEAS_RAW_V)<<(SENS_TOUCH_MEAS_RAW_S))
+#define SENS_TOUCH_MEAS_RAW_V  0x3FF
+#define SENS_TOUCH_MEAS_RAW_S  0
+
+#define SENS_SAR_READ_CTRL2_REG          (DR_REG_SENS_BASE + 0x0094)
+/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Invert SAR ADC2 data*/
+#define SENS_SAR2_DATA_INV  (BIT(29))
+#define SENS_SAR2_DATA_INV_M  (BIT(29))
+#define SENS_SAR2_DATA_INV_V  0x1
+#define SENS_SAR2_DATA_INV_S  29
+/* SENS_SAR2_DIG_FORCE : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL  0: SAR
+ ADC2 controlled by RTC ADC2 CTRL*/
+#define SENS_SAR2_DIG_FORCE  (BIT(28))
+#define SENS_SAR2_DIG_FORCE_M  (BIT(28))
+#define SENS_SAR2_DIG_FORCE_V  0x1
+#define SENS_SAR2_DIG_FORCE_S  28
+/* SENS_SAR2_PWDET_FORCE : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR2_PWDET_FORCE  (BIT(27))
+#define SENS_SAR2_PWDET_FORCE_M  (BIT(27))
+#define SENS_SAR2_PWDET_FORCE_V  0x1
+#define SENS_SAR2_PWDET_FORCE_S  27
+/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */
+/*description: */
+#define SENS_SAR2_SAMPLE_NUM  0x000000FF
+#define SENS_SAR2_SAMPLE_NUM_M  ((SENS_SAR2_SAMPLE_NUM_V)<<(SENS_SAR2_SAMPLE_NUM_S))
+#define SENS_SAR2_SAMPLE_NUM_V  0xFF
+#define SENS_SAR2_SAMPLE_NUM_S  19
+/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SENS_SAR2_CLK_GATED  (BIT(18))
+#define SENS_SAR2_CLK_GATED_M  (BIT(18))
+#define SENS_SAR2_CLK_GATED_V  0x1
+#define SENS_SAR2_CLK_GATED_S  18
+/* SENS_SAR2_SAMPLE_BIT : R/W ;bitpos:[17:16] ;default: 2'd3 ; */
+/*description: 00: for 9-bit width  01: for 10-bit width  10: for 11-bit width
+  11: for 12-bit width*/
+#define SENS_SAR2_SAMPLE_BIT  0x00000003
+#define SENS_SAR2_SAMPLE_BIT_M  ((SENS_SAR2_SAMPLE_BIT_V)<<(SENS_SAR2_SAMPLE_BIT_S))
+#define SENS_SAR2_SAMPLE_BIT_V  0x3
+#define SENS_SAR2_SAMPLE_BIT_S  16
+/* SENS_SAR2_SAMPLE_CYCLE : R/W ;bitpos:[15:8] ;default: 8'd9 ; */
+/*description: sample cycles for SAR ADC2*/
+#define SENS_SAR2_SAMPLE_CYCLE  0x000000FF
+#define SENS_SAR2_SAMPLE_CYCLE_M  ((SENS_SAR2_SAMPLE_CYCLE_V)<<(SENS_SAR2_SAMPLE_CYCLE_S))
+#define SENS_SAR2_SAMPLE_CYCLE_V  0xFF
+#define SENS_SAR2_SAMPLE_CYCLE_S  8
+/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
+/*description: clock divider*/
+#define SENS_SAR2_CLK_DIV  0x000000FF
+#define SENS_SAR2_CLK_DIV_M  ((SENS_SAR2_CLK_DIV_V)<<(SENS_SAR2_CLK_DIV_S))
+#define SENS_SAR2_CLK_DIV_V  0xFF
+#define SENS_SAR2_CLK_DIV_S  0
+
+#define SENS_SAR_MEAS_START2_REG          (DR_REG_SENS_BASE + 0x0098)
+/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW  0: SAR ADC2
+ pad enable bitmap is controlled by ULP-coprocessor*/
+#define SENS_SAR2_EN_PAD_FORCE  (BIT(31))
+#define SENS_SAR2_EN_PAD_FORCE_M  (BIT(31))
+#define SENS_SAR2_EN_PAD_FORCE_V  0x1
+#define SENS_SAR2_EN_PAD_FORCE_S  31
+/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */
+/*description: SAR ADC2 pad enable bitmap  only active when reg_sar2_en_pad_force = 1*/
+#define SENS_SAR2_EN_PAD  0x00000FFF
+#define SENS_SAR2_EN_PAD_M  ((SENS_SAR2_EN_PAD_V)<<(SENS_SAR2_EN_PAD_S))
+#define SENS_SAR2_EN_PAD_V  0xFFF
+#define SENS_SAR2_EN_PAD_S  19
+/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: 1: SAR ADC2 controller (in RTC) is started by SW  0: SAR ADC2
+ controller is started by ULP-coprocessor*/
+#define SENS_MEAS2_START_FORCE  (BIT(18))
+#define SENS_MEAS2_START_FORCE_M  (BIT(18))
+#define SENS_MEAS2_START_FORCE_V  0x1
+#define SENS_MEAS2_START_FORCE_S  18
+/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: SAR ADC2 controller (in RTC) starts conversion  only active when
+ reg_meas2_start_force = 1*/
+#define SENS_MEAS2_START_SAR  (BIT(17))
+#define SENS_MEAS2_START_SAR_M  (BIT(17))
+#define SENS_MEAS2_START_SAR_V  0x1
+#define SENS_MEAS2_START_SAR_S  17
+/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: SAR ADC2 conversion done indication*/
+#define SENS_MEAS2_DONE_SAR  (BIT(16))
+#define SENS_MEAS2_DONE_SAR_M  (BIT(16))
+#define SENS_MEAS2_DONE_SAR_V  0x1
+#define SENS_MEAS2_DONE_SAR_S  16
+/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: SAR ADC2 data*/
+#define SENS_MEAS2_DATA_SAR  0x0000FFFF
+#define SENS_MEAS2_DATA_SAR_M  ((SENS_MEAS2_DATA_SAR_V)<<(SENS_MEAS2_DATA_SAR_S))
+#define SENS_MEAS2_DATA_SAR_V  0xFFFF
+#define SENS_MEAS2_DATA_SAR_S  0
+
+#define SENS_SAR_DAC_CTRL1_REG          (DR_REG_SENS_BASE + 0x009c)
+/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: invert PDAC_CLK*/
+#define SENS_DAC_CLK_INV  (BIT(25))
+#define SENS_DAC_CLK_INV_M  (BIT(25))
+#define SENS_DAC_CLK_INV_V  0x1
+#define SENS_DAC_CLK_INV_S  25
+/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: 1: force PDAC_CLK to high*/
+#define SENS_DAC_CLK_FORCE_HIGH  (BIT(24))
+#define SENS_DAC_CLK_FORCE_HIGH_M  (BIT(24))
+#define SENS_DAC_CLK_FORCE_HIGH_V  0x1
+#define SENS_DAC_CLK_FORCE_HIGH_S  24
+/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: 1: force PDAC_CLK to low*/
+#define SENS_DAC_CLK_FORCE_LOW  (BIT(23))
+#define SENS_DAC_CLK_FORCE_LOW_M  (BIT(23))
+#define SENS_DAC_CLK_FORCE_LOW_V  0x1
+#define SENS_DAC_CLK_FORCE_LOW_S  23
+/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: DAC1 & DAC2 use DMA  0: DAC1 & DAC2 do not use DMA*/
+#define SENS_DAC_DIG_FORCE  (BIT(22))
+#define SENS_DAC_DIG_FORCE_M  (BIT(22))
+#define SENS_DAC_DIG_FORCE_V  0x1
+#define SENS_DAC_DIG_FORCE_S  22
+/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */
+/*description: */
+#define SENS_DEBUG_BIT_SEL  0x0000001F
+#define SENS_DEBUG_BIT_SEL_M  ((SENS_DEBUG_BIT_SEL_V)<<(SENS_DEBUG_BIT_SEL_S))
+#define SENS_DEBUG_BIT_SEL_V  0x1F
+#define SENS_DEBUG_BIT_SEL_S  17
+/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: 1: enable CW generator  0: disable CW generator*/
+#define SENS_SW_TONE_EN  (BIT(16))
+#define SENS_SW_TONE_EN_M  (BIT(16))
+#define SENS_SW_TONE_EN_V  0x1
+#define SENS_SW_TONE_EN_S  16
+/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: frequency step for CW generator  can be used to adjust the frequency*/
+#define SENS_SW_FSTEP  0x0000FFFF
+#define SENS_SW_FSTEP_M  ((SENS_SW_FSTEP_V)<<(SENS_SW_FSTEP_S))
+#define SENS_SW_FSTEP_V  0xFFFF
+#define SENS_SW_FSTEP_S  0
+
+#define SENS_SAR_DAC_CTRL2_REG          (DR_REG_SENS_BASE + 0x00a0)
+/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]  0: to
+ select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/
+#define SENS_DAC_CW_EN2  (BIT(25))
+#define SENS_DAC_CW_EN2_M  (BIT(25))
+#define SENS_DAC_CW_EN2_V  0x1
+#define SENS_DAC_CW_EN2_S  25
+/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]  0: to
+ select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/
+#define SENS_DAC_CW_EN1  (BIT(24))
+#define SENS_DAC_CW_EN1_M  (BIT(24))
+#define SENS_DAC_CW_EN1_V  0x1
+#define SENS_DAC_CW_EN1_S  24
+/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */
+/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB
+  11: invert all bits except MSB*/
+#define SENS_DAC_INV2  0x00000003
+#define SENS_DAC_INV2_M  ((SENS_DAC_INV2_V)<<(SENS_DAC_INV2_S))
+#define SENS_DAC_INV2_V  0x3
+#define SENS_DAC_INV2_S  22
+/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */
+/*description: 00: do not invert any bits  01: invert all bits  10: invert MSB
+  11: invert all bits except MSB*/
+#define SENS_DAC_INV1  0x00000003
+#define SENS_DAC_INV1_M  ((SENS_DAC_INV1_V)<<(SENS_DAC_INV1_S))
+#define SENS_DAC_INV1_V  0x3
+#define SENS_DAC_INV1_S  20
+/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
+#define SENS_DAC_SCALE2  0x00000003
+#define SENS_DAC_SCALE2_M  ((SENS_DAC_SCALE2_V)<<(SENS_DAC_SCALE2_S))
+#define SENS_DAC_SCALE2_V  0x3
+#define SENS_DAC_SCALE2_S  18
+/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */
+/*description: 00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
+#define SENS_DAC_SCALE1  0x00000003
+#define SENS_DAC_SCALE1_M  ((SENS_DAC_SCALE1_V)<<(SENS_DAC_SCALE1_S))
+#define SENS_DAC_SCALE1_V  0x3
+#define SENS_DAC_SCALE1_S  16
+/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
+/*description: DC offset for DAC2 CW generator*/
+#define SENS_DAC_DC2  0x000000FF
+#define SENS_DAC_DC2_M  ((SENS_DAC_DC2_V)<<(SENS_DAC_DC2_S))
+#define SENS_DAC_DC2_V  0xFF
+#define SENS_DAC_DC2_S  8
+/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: DC offset for DAC1 CW generator*/
+#define SENS_DAC_DC1  0x000000FF
+#define SENS_DAC_DC1_M  ((SENS_DAC_DC1_V)<<(SENS_DAC_DC1_S))
+#define SENS_DAC_DC1_V  0xFF
+#define SENS_DAC_DC1_S  0
+
+#define SENS_SAR_MEAS_CTRL2_REG          (DR_REG_SENS_BASE + 0x00a4)
+/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[18:17] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FORCE  0x00000003
+#define SENS_AMP_SHORT_REF_GND_FORCE_M  ((SENS_AMP_SHORT_REF_GND_FORCE_V)<<(SENS_AMP_SHORT_REF_GND_FORCE_S))
+#define SENS_AMP_SHORT_REF_GND_FORCE_V  0x3
+#define SENS_AMP_SHORT_REF_GND_FORCE_S  17
+/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[16:15] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FORCE  0x00000003
+#define SENS_AMP_SHORT_REF_FORCE_M  ((SENS_AMP_SHORT_REF_FORCE_V)<<(SENS_AMP_SHORT_REF_FORCE_S))
+#define SENS_AMP_SHORT_REF_FORCE_V  0x3
+#define SENS_AMP_SHORT_REF_FORCE_S  15
+/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[14:13] ;default: 2'b0 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FORCE  0x00000003
+#define SENS_AMP_RST_FB_FORCE_M  ((SENS_AMP_RST_FB_FORCE_V)<<(SENS_AMP_RST_FB_FORCE_S))
+#define SENS_AMP_RST_FB_FORCE_V  0x3
+#define SENS_AMP_RST_FB_FORCE_S  13
+/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[12:11] ;default: 2'b0 ; */
+/*description: */
+#define SENS_SAR2_RSTB_FORCE  0x00000003
+#define SENS_SAR2_RSTB_FORCE_M  ((SENS_SAR2_RSTB_FORCE_V)<<(SENS_SAR2_RSTB_FORCE_S))
+#define SENS_SAR2_RSTB_FORCE_V  0x3
+#define SENS_SAR2_RSTB_FORCE_S  11
+/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR_RSTB_FSM_IDLE  (BIT(10))
+#define SENS_SAR_RSTB_FSM_IDLE_M  (BIT(10))
+#define SENS_SAR_RSTB_FSM_IDLE_V  0x1
+#define SENS_SAR_RSTB_FSM_IDLE_S  10
+/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SENS_XPD_SAR_FSM_IDLE  (BIT(9))
+#define SENS_XPD_SAR_FSM_IDLE_M  (BIT(9))
+#define SENS_XPD_SAR_FSM_IDLE_V  0x1
+#define SENS_XPD_SAR_FSM_IDLE_S  9
+/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE  (BIT(8))
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M  (BIT(8))
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V  0x1
+#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S  8
+/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_SHORT_REF_FSM_IDLE  (BIT(7))
+#define SENS_AMP_SHORT_REF_FSM_IDLE_M  (BIT(7))
+#define SENS_AMP_SHORT_REF_FSM_IDLE_V  0x1
+#define SENS_AMP_SHORT_REF_FSM_IDLE_S  7
+/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SENS_AMP_RST_FB_FSM_IDLE  (BIT(6))
+#define SENS_AMP_RST_FB_FSM_IDLE_M  (BIT(6))
+#define SENS_AMP_RST_FB_FSM_IDLE_V  0x1
+#define SENS_AMP_RST_FB_FSM_IDLE_S  6
+/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SENS_XPD_SAR_AMP_FSM_IDLE  (BIT(5))
+#define SENS_XPD_SAR_AMP_FSM_IDLE_M  (BIT(5))
+#define SENS_XPD_SAR_AMP_FSM_IDLE_V  0x1
+#define SENS_XPD_SAR_AMP_FSM_IDLE_S  5
+/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SENS_SAR1_DAC_XPD_FSM_IDLE  (BIT(4))
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_M  (BIT(4))
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_V  0x1
+#define SENS_SAR1_DAC_XPD_FSM_IDLE_S  4
+/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */
+/*description: */
+#define SENS_SAR1_DAC_XPD_FSM  0x0000000F
+#define SENS_SAR1_DAC_XPD_FSM_M  ((SENS_SAR1_DAC_XPD_FSM_V)<<(SENS_SAR1_DAC_XPD_FSM_S))
+#define SENS_SAR1_DAC_XPD_FSM_V  0xF
+#define SENS_SAR1_DAC_XPD_FSM_S  0
+
+#define SENS_SAR_COCPU_CTRL_REG          (DR_REG_SENS_BASE + 0x00a8)
+/* SENS_COCPU_TRAP : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: check cocpu whether in trap state*/
+#define SENS_COCPU_TRAP  (BIT(28))
+#define SENS_COCPU_TRAP_M  (BIT(28))
+#define SENS_COCPU_TRAP_V  0x1
+#define SENS_COCPU_TRAP_S  28
+/* SENS_COCPU_EOI : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: check cocpu whether in interrupt state*/
+#define SENS_COCPU_EOI  (BIT(27))
+#define SENS_COCPU_EOI_M  (BIT(27))
+#define SENS_COCPU_EOI_V  0x1
+#define SENS_COCPU_EOI_S  27
+/* SENS_COCPU_RESET_N : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: check cocpu whether in reset state*/
+#define SENS_COCPU_RESET_N  (BIT(26))
+#define SENS_COCPU_RESET_N_M  (BIT(26))
+#define SENS_COCPU_RESET_N_V  0x1
+#define SENS_COCPU_RESET_N_S  26
+/* SENS_COCPU_CLK_EN : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: check cocpu whether clk on*/
+#define SENS_COCPU_CLK_EN  (BIT(25))
+#define SENS_COCPU_CLK_EN_M  (BIT(25))
+#define SENS_COCPU_CLK_EN_V  0x1
+#define SENS_COCPU_CLK_EN_S  25
+/* SENS_COCPU_INT_TRIGGER : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: trigger cocpu register interrupt*/
+#define SENS_COCPU_INT_TRIGGER  (BIT(24))
+#define SENS_COCPU_INT_TRIGGER_M  (BIT(24))
+#define SENS_COCPU_INT_TRIGGER_V  0x1
+#define SENS_COCPU_INT_TRIGGER_S  24
+/* SENS_COCPU_DONE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: done signal used by riscv to control timer.*/
+#define SENS_COCPU_DONE  (BIT(23))
+#define SENS_COCPU_DONE_M  (BIT(23))
+#define SENS_COCPU_DONE_V  0x1
+#define SENS_COCPU_DONE_S  23
+/* SENS_COCPU_DONE_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: 1: select riscv done 0: select ulp done*/
+#define SENS_COCPU_DONE_FORCE  (BIT(22))
+#define SENS_COCPU_DONE_FORCE_M  (BIT(22))
+#define SENS_COCPU_DONE_FORCE_V  0x1
+#define SENS_COCPU_DONE_FORCE_S  22
+/* SENS_COCPU_SEL : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: 1: old ULP 0: new riscV*/
+#define SENS_COCPU_SEL  (BIT(21))
+#define SENS_COCPU_SEL_M  (BIT(21))
+#define SENS_COCPU_SEL_V  0x1
+#define SENS_COCPU_SEL_S  21
+/* SENS_COCPU_SHUT_RESET_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: to reset cocpu*/
+#define SENS_COCPU_SHUT_RESET_EN  (BIT(20))
+#define SENS_COCPU_SHUT_RESET_EN_M  (BIT(20))
+#define SENS_COCPU_SHUT_RESET_EN_V  0x1
+#define SENS_COCPU_SHUT_RESET_EN_S  20
+/* SENS_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[19:14] ;default: 6'd24 ; */
+/*description: time from shut cocpu to disable clk*/
+#define SENS_COCPU_SHUT_2_CLK_DIS  0x0000003F
+#define SENS_COCPU_SHUT_2_CLK_DIS_M  ((SENS_COCPU_SHUT_2_CLK_DIS_V)<<(SENS_COCPU_SHUT_2_CLK_DIS_S))
+#define SENS_COCPU_SHUT_2_CLK_DIS_V  0x3F
+#define SENS_COCPU_SHUT_2_CLK_DIS_S  14
+/* SENS_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: to shut cocpu*/
+#define SENS_COCPU_SHUT  (BIT(13))
+#define SENS_COCPU_SHUT_M  (BIT(13))
+#define SENS_COCPU_SHUT_V  0x1
+#define SENS_COCPU_SHUT_S  13
+/* SENS_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */
+/*description: time from start cocpu to give start interrupt*/
+#define SENS_COCPU_START_2_INTR_EN  0x0000003F
+#define SENS_COCPU_START_2_INTR_EN_M  ((SENS_COCPU_START_2_INTR_EN_V)<<(SENS_COCPU_START_2_INTR_EN_S))
+#define SENS_COCPU_START_2_INTR_EN_V  0x3F
+#define SENS_COCPU_START_2_INTR_EN_S  7
+/* SENS_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */
+/*description: time from start cocpu to pull down reset*/
+#define SENS_COCPU_START_2_RESET_DIS  0x0000003F
+#define SENS_COCPU_START_2_RESET_DIS_M  ((SENS_COCPU_START_2_RESET_DIS_V)<<(SENS_COCPU_START_2_RESET_DIS_S))
+#define SENS_COCPU_START_2_RESET_DIS_V  0x3F
+#define SENS_COCPU_START_2_RESET_DIS_S  1
+/* SENS_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: cocpu clk force on*/
+#define SENS_COCPU_CLK_FO  (BIT(0))
+#define SENS_COCPU_CLK_FO_M  (BIT(0))
+#define SENS_COCPU_CLK_FO_V  0x1
+#define SENS_COCPU_CLK_FO_S  0
+
+#define SENS_SAR_COCPU_INT_REG          (DR_REG_SENS_BASE + 0x00ac)
+/* SENS_COCPU_EBREAK_INT : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: int from ebreak*/
+#define SENS_COCPU_EBREAK_INT  (BIT(24))
+#define SENS_COCPU_EBREAK_INT_M  (BIT(24))
+#define SENS_COCPU_EBREAK_INT_V  0x1
+#define SENS_COCPU_EBREAK_INT_S  24
+/* SENS_COCPU_INT : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: int from register*/
+#define SENS_COCPU_INT  (BIT(23))
+#define SENS_COCPU_INT_M  (BIT(23))
+#define SENS_COCPU_INT_V  0x1
+#define SENS_COCPU_INT_S  23
+/* SENS_COCPU_START_INT : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: int from start*/
+#define SENS_COCPU_START_INT  (BIT(22))
+#define SENS_COCPU_START_INT_M  (BIT(22))
+#define SENS_COCPU_START_INT_V  0x1
+#define SENS_COCPU_START_INT_S  22
+/* SENS_COCPU_TSENS_INT : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: int from tsens*/
+#define SENS_COCPU_TSENS_INT  (BIT(21))
+#define SENS_COCPU_TSENS_INT_M  (BIT(21))
+#define SENS_COCPU_TSENS_INT_V  0x1
+#define SENS_COCPU_TSENS_INT_S  21
+/* SENS_COCPU_SARADC_INT : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: int from saradc*/
+#define SENS_COCPU_SARADC_INT  (BIT(20))
+#define SENS_COCPU_SARADC_INT_M  (BIT(20))
+#define SENS_COCPU_SARADC_INT_V  0x1
+#define SENS_COCPU_SARADC_INT_S  20
+/* SENS_COCPU_EBREAK_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: int clear entry*/
+#define SENS_COCPU_EBREAK_INT_CLR  (BIT(14))
+#define SENS_COCPU_EBREAK_INT_CLR_M  (BIT(14))
+#define SENS_COCPU_EBREAK_INT_CLR_V  0x1
+#define SENS_COCPU_EBREAK_INT_CLR_S  14
+/* SENS_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_INT_CLR  (BIT(13))
+#define SENS_COCPU_INT_CLR_M  (BIT(13))
+#define SENS_COCPU_INT_CLR_V  0x1
+#define SENS_COCPU_INT_CLR_S  13
+/* SENS_COCPU_START_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_START_INT_CLR  (BIT(12))
+#define SENS_COCPU_START_INT_CLR_M  (BIT(12))
+#define SENS_COCPU_START_INT_CLR_V  0x1
+#define SENS_COCPU_START_INT_CLR_S  12
+/* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_TSENS_INT_CLR  (BIT(11))
+#define SENS_COCPU_TSENS_INT_CLR_M  (BIT(11))
+#define SENS_COCPU_TSENS_INT_CLR_V  0x1
+#define SENS_COCPU_TSENS_INT_CLR_S  11
+/* SENS_COCPU_SARADC_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SENS_COCPU_SARADC_INT_CLR  (BIT(10))
+#define SENS_COCPU_SARADC_INT_CLR_M  (BIT(10))
+#define SENS_COCPU_SARADC_INT_CLR_V  0x1
+#define SENS_COCPU_SARADC_INT_CLR_S  10
+/* SENS_COCPU_EBREAK_INT_ENA : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: int enable entry*/
+#define SENS_COCPU_EBREAK_INT_ENA  (BIT(4))
+#define SENS_COCPU_EBREAK_INT_ENA_M  (BIT(4))
+#define SENS_COCPU_EBREAK_INT_ENA_V  0x1
+#define SENS_COCPU_EBREAK_INT_ENA_S  4
+/* SENS_COCPU_INT_ENA : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SENS_COCPU_INT_ENA  (BIT(3))
+#define SENS_COCPU_INT_ENA_M  (BIT(3))
+#define SENS_COCPU_INT_ENA_V  0x1
+#define SENS_COCPU_INT_ENA_S  3
+/* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SENS_COCPU_START_INT_ENA  (BIT(2))
+#define SENS_COCPU_START_INT_ENA_M  (BIT(2))
+#define SENS_COCPU_START_INT_ENA_V  0x1
+#define SENS_COCPU_START_INT_ENA_S  2
+/* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SENS_COCPU_TSENS_INT_ENA  (BIT(1))
+#define SENS_COCPU_TSENS_INT_ENA_M  (BIT(1))
+#define SENS_COCPU_TSENS_INT_ENA_V  0x1
+#define SENS_COCPU_TSENS_INT_ENA_S  1
+/* SENS_COCPU_SARADC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENS_COCPU_SARADC_INT_ENA  (BIT(0))
+#define SENS_COCPU_SARADC_INT_ENA_M  (BIT(0))
+#define SENS_COCPU_SARADC_INT_ENA_V  0x1
+#define SENS_COCPU_SARADC_INT_ENA_S  0
+
+#define SENS_SAR_NOUSE_REG          (DR_REG_SENS_BASE + 0x00F8)
+/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SENS_SAR_NOUSE  0xFFFFFFFF
+#define SENS_SAR_NOUSE_M  ((SENS_SAR_NOUSE_V)<<(SENS_SAR_NOUSE_S))
+#define SENS_SAR_NOUSE_V  0xFFFFFFFF
+#define SENS_SAR_NOUSE_S  0
+
+#define SENS_SARDATE_REG          (DR_REG_SENS_BASE + 0x00FC)
+/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1703080 ; */
+/*description: */
+#define SENS_SAR_DATE  0x0FFFFFFF
+#define SENS_SAR_DATE_M  ((SENS_SAR_DATE_V)<<(SENS_SAR_DATE_S))
+#define SENS_SAR_DATE_V  0xFFFFFFF
+#define SENS_SAR_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENS_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/sens_struct.h b/components/soc/esp32s2beta/include/soc/sens_struct.h
new file mode 100644
index 000000000..fb0ec358f
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/sens_struct.h
@@ -0,0 +1,373 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENS_STRUCT_H_
+#define _SOC_SENS_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t sar1_clk_div:      8;                /*clock divider*/
+            uint32_t sar1_sample_cycle: 8;                /*sample cycles for SAR ADC1*/
+            uint32_t sar1_sample_bit:   2;                /*00: for 9-bit width  01: for 10-bit width  10: for 11-bit width  11: for 12-bit width*/
+            uint32_t sar1_clk_gated:    1;
+            uint32_t sar1_sample_num:   8;
+            uint32_t sar1_dig_force:    1;                /*1: SAR ADC1 controlled by DIG ADC1 CTRL  0: SAR ADC1 controlled by RTC ADC1 CTRL*/
+            uint32_t sar1_data_inv:     1;                /*Invert SAR ADC1 data*/
+            uint32_t reserved29:        3;
+        };
+        uint32_t val;
+    } sar_read_ctrl;
+    uint32_t sar_read_status1;                            /**/
+    union {
+        struct {
+            uint32_t sar_amp_wait1:16;
+            uint32_t sar_amp_wait2:16;
+        };
+        uint32_t val;
+    } sar_meas_wait1;
+    union {
+        struct {
+            uint32_t sar_amp_wait3: 16;
+            uint32_t force_xpd_amp:  2;
+            uint32_t force_xpd_sar:  2;
+            uint32_t sar2_rstb_wait: 8;
+            uint32_t reserved28:     4;
+        };
+        uint32_t val;
+    } sar_meas_wait2;
+    union {
+        struct {
+            uint32_t xpd_sar_amp_fsm:       4;
+            uint32_t amp_rst_fb_fsm:        4;
+            uint32_t amp_short_ref_fsm:     4;
+            uint32_t amp_short_ref_gnd_fsm: 4;
+            uint32_t xpd_sar_fsm:           4;
+            uint32_t sar_rstb_fsm:          4;
+            uint32_t sar2_xpd_wait:         8;
+        };
+        uint32_t val;
+    } sar_meas_ctrl;
+    uint32_t sar_read_status2;                            /**/
+    uint32_t ulp_cp_sleep_cyc0;                           /*sleep cycles for ULP-coprocessor timer*/
+    uint32_t ulp_cp_sleep_cyc1;                           /**/
+    uint32_t ulp_cp_sleep_cyc2;                           /**/
+    uint32_t ulp_cp_sleep_cyc3;                           /**/
+    uint32_t ulp_cp_sleep_cyc4;                           /**/
+    union {
+        struct {
+            uint32_t sar1_bit_width:         2;           /*00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
+            uint32_t sar2_bit_width:         2;           /*00: 9 bit  01: 10 bits  10: 11bits  11: 12bits*/
+            uint32_t sar2_en_test:           1;           /*SAR2_EN_TEST  only active when reg_sar2_dig_force = 0*/
+            uint32_t sar2_pwdet_cct:         3;           /*SAR2_PWDET_CCT  PA power detector capacitance tuning.*/
+            uint32_t ulp_cp_force_start_top: 1;           /*1: ULP-coprocessor is started by SW  0: ULP-coprocessor is started by timer*/
+            uint32_t ulp_cp_start_top:       1;           /*Write 1 to start ULP-coprocessor  only active when reg_ulp_cp_force_start_top = 1*/
+            uint32_t sarclk_en:              1;
+            uint32_t pc_init:               11;           /*initialized PC for ULP-coprocessor*/
+            uint32_t sar2_stop:              1;           /*stop SAR ADC2 conversion*/
+            uint32_t sar1_stop:              1;           /*stop SAR ADC1 conversion*/
+            uint32_t sar2_pwdet_en:          1;           /*N/A*/
+            uint32_t reserved25:             7;
+        };
+        uint32_t val;
+    } sar_start_force;
+    union {
+        struct {
+            uint32_t mem_wr_addr_init:    11;
+            uint32_t mem_wr_addr_size:    11;
+            uint32_t rtc_mem_wr_offst_clr: 1;
+            uint32_t ulp_cp_clk_fo:        1;             /*ulp coprocessor clk force on*/
+            uint32_t reserved24:           8;
+        };
+        uint32_t val;
+    } sar_mem_wr_ctrl;
+    uint32_t sar_atten1;                                  /*2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
+    uint32_t sar_atten2;                                  /*2-bit attenuation for each pad  11:1dB  10:6dB  01:3dB  00:0dB*/
+    union {
+        struct {
+            uint32_t i2c_slave_addr1:   11;
+            uint32_t i2c_slave_addr0:   11;
+            uint32_t meas_status:        8;
+            uint32_t reserved30:         2;
+        };
+        uint32_t val;
+    } sar_slave_addr1;
+    union {
+        struct {
+            uint32_t i2c_slave_addr3:11;
+            uint32_t i2c_slave_addr2:11;
+            uint32_t reserved22:     10;
+        };
+        uint32_t val;
+    } sar_slave_addr2;
+    union {
+        struct {
+            uint32_t i2c_slave_addr5:11;
+            uint32_t i2c_slave_addr4:11;
+            uint32_t tsens_out:       8;                  /*temperature sensor data out*/
+            uint32_t tsens_rdy_out:   1;                  /*indicate temperature sensor out ready*/
+            uint32_t reserved31:      1;
+        };
+        uint32_t val;
+    } sar_slave_addr3;
+    union {
+        struct {
+            uint32_t i2c_slave_addr7:11;
+            uint32_t i2c_slave_addr6:11;
+            uint32_t i2c_rdata:       8;                  /*I2C read data*/
+            uint32_t i2c_done:        1;                  /*indicate I2C done*/
+            uint32_t reserved31:      1;
+        };
+        uint32_t val;
+    } sar_slave_addr4;
+    union {
+        struct {
+            uint32_t tsens_xpd_wait:      12;
+            uint32_t tsens_xpd_force:      1;
+            uint32_t tsens_clk_inv:        1;
+            uint32_t tsens_clk_gated:      1;
+            uint32_t tsens_in_inv:         1;             /*invert temperature sensor data*/
+            uint32_t tsens_clk_div:        8;             /*temperature sensor clock divider*/
+            uint32_t tsens_power_up:       1;             /*temperature sensor power up*/
+            uint32_t tsens_power_up_force: 1;             /*1: dump out & power up controlled by SW  0: by FSM*/
+            uint32_t tsens_dump_out:       1;             /*temperature sensor dump out  only active when reg_tsens_power_up_force = 1*/
+            uint32_t tsens_dos:            4;             /*Temperature sensor calibration bits*/
+            uint32_t tsens_force:          1;             /*1: select saradc_reg 0: select efuse*/
+        };
+        uint32_t val;
+    } sar_tctrl;
+    union {
+        struct {
+            uint32_t sar_i2c_ctrl:       28;              /*I2C control data  only active when reg_sar_i2c_start_force = 1*/
+            uint32_t sar_i2c_start:       1;              /*start I2C  only active when reg_sar_i2c_start_force = 1*/
+            uint32_t sar_i2c_start_force: 1;              /*1: I2C started by SW  0: I2C started by FSM*/
+            uint32_t reserved30:          2;
+        };
+        uint32_t val;
+    } sar_i2c_ctrl;
+    union {
+        struct {
+            uint32_t meas1_data_sar:   16;                /*SAR ADC1 data*/
+            uint32_t meas1_done_sar:    1;                /*SAR ADC1 conversion done indication*/
+            uint32_t meas1_start_sar:   1;                /*SAR ADC1 controller (in RTC) starts conversion  only active when reg_meas1_start_force = 1*/
+            uint32_t meas1_start_force: 1;                /*1: SAR ADC1 controller (in RTC) is started by SW  0: SAR ADC1 controller is started by ULP-coprocessor*/
+            uint32_t sar1_en_pad:      12;                /*SAR ADC1 pad enable bitmap  only active when reg_sar1_en_pad_force = 1*/
+            uint32_t sar1_en_pad_force: 1;                /*1: SAR ADC1 pad enable bitmap is controlled by SW  0: SAR ADC1 pad enable bitmap is controlled by ULP-coprocessor*/
+        };
+        uint32_t val;
+    } sar_meas_start1;
+    union {
+        struct {
+            uint32_t touch_meas_delay:16;                 /*the meas length (in 8MHz)*/
+            uint32_t touch_xpd_wait:   8;                 /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
+            uint32_t touch_out_sel:    1;                 /*1: when the counter is greater then the threshold  the touch pad is considered as “touched”  0: when the counter is less than the threshold  the touch pad is considered as “touched”*/
+            uint32_t touch_out_1en:    1;                 /*1: wakeup interrupt is generated if SET1 is “touched”  0: wakeup interrupt is generated only if SET1 & SET2 is both “touched”*/
+            uint32_t xpd_hall_force:   1;                 /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
+            uint32_t hall_phase_force: 1;                 /*1: HALL PHASE is controlled by SW  0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
+            uint32_t reserved28:       4;
+        };
+        uint32_t val;
+    } sar_touch_ctrl1;
+    union {
+        struct {
+            uint32_t l_thresh:     16;                    /*the threshold for touch pad 1*/
+            uint32_t h_thresh:     16;                    /*the threshold for touch pad 0*/
+        };
+        uint32_t val;
+    } touch_thresh[5];
+    union {
+        struct {
+            uint32_t l_val:          16;                  /*the counter for touch pad 1*/
+            uint32_t h_val:          16;                  /*the counter for touch pad 0*/
+        };
+        uint32_t val;
+    } touch_meas[5];
+    union {
+        struct {
+            uint32_t touch_meas_en:     10;               /*10-bit register to indicate which pads are “touched”*/
+            uint32_t touch_meas_done:    1;               /*fsm set 1 to indicate touch touch meas is done*/
+            uint32_t touch_start_fsm_en: 1;               /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm  0: TOUCH_START & TOUCH_XPD is controlled by registers*/
+            uint32_t touch_start_en:     1;               /*1: start touch fsm  valid when reg_touch_start_force is set*/
+            uint32_t touch_start_force:  1;               /*1: to start touch fsm by SW  0: to start touch fsm by timer*/
+            uint32_t touch_sleep_cycles:16;               /*sleep cycles for timer*/
+            uint32_t touch_meas_en_clr:  1;               /*to clear reg_touch_meas_en*/
+            uint32_t reserved31:         1;
+        };
+        uint32_t val;
+    } sar_touch_ctrl2;
+    uint32_t reserved_88;
+    union {
+        struct {
+            uint32_t touch_pad_worken:10;                 /*Bitmap defining the working set during the measurement.*/
+            uint32_t touch_pad_outen2:10;                 /*Bitmap defining SET2 for generating wakeup interrupt. SET2 is “touched” only if at least one of touch pad in SET2 is “touched”.*/
+            uint32_t touch_pad_outen1:10;                 /*Bitmap defining SET1 for generating wakeup interrupt. SET1 is “touched” only if at least one of touch pad in SET1 is “touched”.*/
+            uint32_t reserved30:       2;
+        };
+        uint32_t val;
+    } sar_touch_enable;
+    union {
+        struct {
+            uint32_t touch_meas_raw:10;                   /*touch sensor raw result*/
+            uint32_t reserved10:    22;
+        };
+        uint32_t val;
+    } sar_touch_ctrl3;
+    union {
+        struct {
+            uint32_t sar2_clk_div:      8;                /*clock divider*/
+            uint32_t sar2_sample_cycle: 8;                /*sample cycles for SAR ADC2*/
+            uint32_t sar2_sample_bit:   2;                /*00: for 9-bit width  01: for 10-bit width  10: for 11-bit width  11: for 12-bit width*/
+            uint32_t sar2_clk_gated:    1;
+            uint32_t sar2_sample_num:   8;
+            uint32_t sar2_pwdet_force:  1;
+            uint32_t sar2_dig_force:    1;                /*1: SAR ADC2 controlled by DIG ADC2 CTRL or PWDET CTRL  0: SAR ADC2 controlled by RTC ADC2 CTRL*/
+            uint32_t sar2_data_inv:     1;                /*Invert SAR ADC2 data*/
+            uint32_t reserved30:        2;
+        };
+        uint32_t val;
+    } sar_read_ctrl2;
+    union {
+        struct {
+            uint32_t meas2_data_sar:   16;                /*SAR ADC2 data*/
+            uint32_t meas2_done_sar:    1;                /*SAR ADC2 conversion done indication*/
+            uint32_t meas2_start_sar:   1;                /*SAR ADC2 controller (in RTC) starts conversion  only active when reg_meas2_start_force = 1*/
+            uint32_t meas2_start_force: 1;                /*1: SAR ADC2 controller (in RTC) is started by SW  0: SAR ADC2 controller is started by ULP-coprocessor*/
+            uint32_t sar2_en_pad:      12;                /*SAR ADC2 pad enable bitmap  only active when reg_sar2_en_pad_force = 1*/
+            uint32_t sar2_en_pad_force: 1;                /*1: SAR ADC2 pad enable bitmap is controlled by SW  0: SAR ADC2 pad enable bitmap is controlled by ULP-coprocessor*/
+        };
+        uint32_t val;
+    } sar_meas_start2;
+    union {
+        struct {
+            uint32_t sw_fstep:          16;               /*frequency step for CW generator  can be used to adjust the frequency*/
+            uint32_t sw_tone_en:         1;               /*1: enable CW generator  0: disable CW generator*/
+            uint32_t debug_bit_sel:      5;
+            uint32_t dac_dig_force:      1;               /*1: DAC1 & DAC2 use DMA  0: DAC1 & DAC2 do not use DMA*/
+            uint32_t dac_clk_force_low:  1;               /*1: force PDAC_CLK to low*/
+            uint32_t dac_clk_force_high: 1;               /*1: force PDAC_CLK to high*/
+            uint32_t dac_clk_inv:        1;               /*1: invert PDAC_CLK*/
+            uint32_t reserved26:         6;
+        };
+        uint32_t val;
+    } sar_dac_ctrl1;
+    union {
+        struct {
+            uint32_t dac_dc1:    8;                       /*DC offset for DAC1 CW generator*/
+            uint32_t dac_dc2:    8;                       /*DC offset for DAC2 CW generator*/
+            uint32_t dac_scale1: 2;                       /*00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
+            uint32_t dac_scale2: 2;                       /*00: no scale  01: scale to 1/2  10: scale to 1/4  scale to 1/8*/
+            uint32_t dac_inv1:   2;                       /*00: do not invert any bits  01: invert all bits  10: invert MSB  11: invert all bits except MSB*/
+            uint32_t dac_inv2:   2;                       /*00: do not invert any bits  01: invert all bits  10: invert MSB  11: invert all bits except MSB*/
+            uint32_t dac_cw_en1: 1;                       /*1: to select CW generator as source to PDAC1_DAC[7:0]  0: to select register reg_pdac1_dac[7:0] as source to PDAC1_DAC[7:0]*/
+            uint32_t dac_cw_en2: 1;                       /*1: to select CW generator as source to PDAC2_DAC[7:0]  0: to select register reg_pdac2_dac[7:0] as source to PDAC2_DAC[7:0]*/
+            uint32_t reserved26: 6;
+        };
+        uint32_t val;
+    } sar_dac_ctrl2;
+    union {
+        struct {
+            uint32_t sar1_dac_xpd_fsm:           4;
+            uint32_t sar1_dac_xpd_fsm_idle:      1;
+            uint32_t xpd_sar_amp_fsm_idle:       1;
+            uint32_t amp_rst_fb_fsm_idle:        1;
+            uint32_t amp_short_ref_fsm_idle:     1;
+            uint32_t amp_short_ref_gnd_fsm_idle: 1;
+            uint32_t xpd_sar_fsm_idle:           1;
+            uint32_t sar_rstb_fsm_idle:          1;
+            uint32_t sar2_rstb_force:            2;
+            uint32_t amp_rst_fb_force:           2;
+            uint32_t amp_short_ref_force:        2;
+            uint32_t amp_short_ref_gnd_force:    2;
+            uint32_t reserved19:                13;
+        };
+        uint32_t val;
+    } sar_meas_ctrl2;
+    union {
+        struct {
+            uint32_t clk_fo:                  1;          /*cocpu clk force on*/
+            uint32_t start_2_reset_dis:       6;          /*time from start cocpu to pull down reset*/
+            uint32_t start_2_intr_en:         6;          /*time from start cocpu to give start interrupt*/
+            uint32_t shut:                    1;          /*to shut cocpu*/
+            uint32_t shut_2_clk_dis:          6;          /*time from shut cocpu to disable clk*/
+            uint32_t shut_reset_en:           1;          /*to reset cocpu*/
+            uint32_t sel:                     1;          /*1: old ULP 0: new riscV*/
+            uint32_t done_force:              1;          /*1: select riscv done 0: select ulp done*/
+            uint32_t done:                    1;          /*done signal used by riscv to control timer.*/
+            uint32_t int_trigger:             1;          /*trigger cocpu register interrupt*/
+            uint32_t clk_en:                  1;          /*check cocpu whether clk on*/
+            uint32_t reset_n:                 1;          /*check cocpu whether in reset state*/
+            uint32_t eoi:                     1;          /*check cocpu whether in interrupt state*/
+            uint32_t trap:                    1;          /*check cocpu whether in trap state*/
+            uint32_t reserved29:              3;
+        };
+        uint32_t val;
+    } sar_cocpu_ctrl;
+    union {
+        struct {
+            uint32_t saradc_int_ena:               1;
+            uint32_t tsens_int_ena:                1;
+            uint32_t start_int_ena:                1;
+            uint32_t cocpu_int_ena:                1;
+            uint32_t ebreak_int_ena:               1;             /*int enable entry*/
+            uint32_t reserved5:            5;
+            uint32_t saradc_int_clr:               1;
+            uint32_t tsens_int_clr:                1;
+            uint32_t start_int_clr:                1;
+            uint32_t cocpu_int_clr:                1;
+            uint32_t ebreak_int_clr:               1;             /*int clear entry*/
+            uint32_t reserved15:           5;
+            uint32_t saradc_int:           1;             /*int from saradc*/
+            uint32_t tsens_int:            1;             /*int from tsens*/
+            uint32_t start_int:            1;             /*int from start*/
+            uint32_t cocpu_int:                  1;             /*int from register*/
+            uint32_t ebreak_int:           1;             /*int from ebreak*/
+            uint32_t reserved25:           7;
+        };
+        uint32_t val;
+    } sar_cocpu_int;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t sar_nouse;                                   /**/
+    union {
+        struct {
+            uint32_t sar_date:  28;
+            uint32_t reserved28: 4;
+        };
+        uint32_t val;
+    } sardate;
+} sens_dev_t;
+extern sens_dev_t SENS;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SENS_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/sensitive_reg.h b/components/soc/esp32s2beta/include/soc/sensitive_reg.h
new file mode 100644
index 000000000..cceee7bd8
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/sensitive_reg.h
@@ -0,0 +1,1220 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SENSITIVE_REG_H_
+#define _SOC_SENSITIVE_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define DPORT_PMS_SDIO_0_REG          (DR_REG_SENSITIVE_BASE + 0x000)
+/* DPORT_PMS_SDIO_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_SDIO_LOCK  (BIT(0))
+#define DPORT_PMS_SDIO_LOCK_M  (BIT(0))
+#define DPORT_PMS_SDIO_LOCK_V  0x1
+#define DPORT_PMS_SDIO_LOCK_S  0
+
+#define DPORT_PMS_SDIO_1_REG          (DR_REG_SENSITIVE_BASE + 0x004)
+/* DPORT_PMS_SDIO_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_SDIO_DISABLE  (BIT(0))
+#define DPORT_PMS_SDIO_DISABLE_M  (BIT(0))
+#define DPORT_PMS_SDIO_DISABLE_V  0x1
+#define DPORT_PMS_SDIO_DISABLE_S  0
+
+#define DPORT_PMS_MAC_DUMP_0_REG          (DR_REG_SENSITIVE_BASE + 0x008)
+/* DPORT_PMS_MAC_DUMP_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_MAC_DUMP_LOCK  (BIT(0))
+#define DPORT_PMS_MAC_DUMP_LOCK_M  (BIT(0))
+#define DPORT_PMS_MAC_DUMP_LOCK_V  0x1
+#define DPORT_PMS_MAC_DUMP_LOCK_S  0
+
+#define DPORT_PMS_MAC_DUMP_1_REG          (DR_REG_SENSITIVE_BASE + 0x00C)
+/* DPORT_PMS_MAC_DUMP_CONNECT : R/W ;bitpos:[11:0] ;default: 12'b000011100100 ; */
+/*description: */
+#define DPORT_PMS_MAC_DUMP_CONNECT  0x00000FFF
+#define DPORT_PMS_MAC_DUMP_CONNECT_M  ((DPORT_PMS_MAC_DUMP_CONNECT_V)<<(DPORT_PMS_MAC_DUMP_CONNECT_S))
+#define DPORT_PMS_MAC_DUMP_CONNECT_V  0xFFF
+#define DPORT_PMS_MAC_DUMP_CONNECT_S  0
+
+#define DPORT_PMS_PRO_IRAM0_0_REG          (DR_REG_SENSITIVE_BASE + 0x010)
+/* DPORT_PMS_PRO_IRAM0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_LOCK  (BIT(0))
+#define DPORT_PMS_PRO_IRAM0_LOCK_M  (BIT(0))
+#define DPORT_PMS_PRO_IRAM0_LOCK_V  0x1
+#define DPORT_PMS_PRO_IRAM0_LOCK_S  0
+
+#define DPORT_PMS_PRO_IRAM0_1_REG          (DR_REG_SENSITIVE_BASE + 0x014)
+/* DPORT_PMS_PRO_IRAM0_SRAM_3_W : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_W  (BIT(11))
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_W_M  (BIT(11))
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_W_S  11
+/* DPORT_PMS_PRO_IRAM0_SRAM_3_R : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_R  (BIT(10))
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_R_M  (BIT(10))
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_R_S  10
+/* DPORT_PMS_PRO_IRAM0_SRAM_3_F : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_F  (BIT(9))
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_F_M  (BIT(9))
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_3_F_S  9
+/* DPORT_PMS_PRO_IRAM0_SRAM_2_W : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_W  (BIT(8))
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_W_M  (BIT(8))
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_W_S  8
+/* DPORT_PMS_PRO_IRAM0_SRAM_2_R : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_R  (BIT(7))
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_R_M  (BIT(7))
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_R_S  7
+/* DPORT_PMS_PRO_IRAM0_SRAM_2_F : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_F  (BIT(6))
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_F_M  (BIT(6))
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_2_F_S  6
+/* DPORT_PMS_PRO_IRAM0_SRAM_1_W : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_W  (BIT(5))
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_W_M  (BIT(5))
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_W_S  5
+/* DPORT_PMS_PRO_IRAM0_SRAM_1_R : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_R  (BIT(4))
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_R_M  (BIT(4))
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_R_S  4
+/* DPORT_PMS_PRO_IRAM0_SRAM_1_F : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_F  (BIT(3))
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_F_M  (BIT(3))
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_1_F_S  3
+/* DPORT_PMS_PRO_IRAM0_SRAM_0_W : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_W  (BIT(2))
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_W_M  (BIT(2))
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_W_S  2
+/* DPORT_PMS_PRO_IRAM0_SRAM_0_R : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_R  (BIT(1))
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_R_M  (BIT(1))
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_R_S  1
+/* DPORT_PMS_PRO_IRAM0_SRAM_0_F : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_F  (BIT(0))
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_F_M  (BIT(0))
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_0_F_S  0
+
+#define DPORT_PMS_PRO_IRAM0_2_REG          (DR_REG_SENSITIVE_BASE + 0x018)
+/* DPORT_PMS_PRO_IRAM0_SRAM_4_H_W : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W  (BIT(22))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W_M  (BIT(22))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_W_S  22
+/* DPORT_PMS_PRO_IRAM0_SRAM_4_H_R : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R  (BIT(21))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R_M  (BIT(21))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_R_S  21
+/* DPORT_PMS_PRO_IRAM0_SRAM_4_H_F : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F  (BIT(20))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F_M  (BIT(20))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_H_F_S  20
+/* DPORT_PMS_PRO_IRAM0_SRAM_4_L_W : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W  (BIT(19))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W_M  (BIT(19))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_W_S  19
+/* DPORT_PMS_PRO_IRAM0_SRAM_4_L_R : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R  (BIT(18))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R_M  (BIT(18))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_R_S  18
+/* DPORT_PMS_PRO_IRAM0_SRAM_4_L_F : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F  (BIT(17))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F_M  (BIT(17))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_L_F_S  17
+/* DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR : R/W ;bitpos:[16:0] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR  0x0001FFFF
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_M  ((DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S))
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_V  0x1FFFF
+#define DPORT_PMS_PRO_IRAM0_SRAM_4_SPLTADDR_S  0
+
+#define DPORT_PMS_PRO_IRAM0_3_REG          (DR_REG_SENSITIVE_BASE + 0x01C)
+/* DPORT_PMS_PRO_IRAM0_RTCFAST_H_W : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W  (BIT(16))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W_M  (BIT(16))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_W_S  16
+/* DPORT_PMS_PRO_IRAM0_RTCFAST_H_R : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R  (BIT(15))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R_M  (BIT(15))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_R_S  15
+/* DPORT_PMS_PRO_IRAM0_RTCFAST_H_F : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F  (BIT(14))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F_M  (BIT(14))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_H_F_S  14
+/* DPORT_PMS_PRO_IRAM0_RTCFAST_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W  (BIT(13))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W_M  (BIT(13))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W_V  0x1
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_W_S  13
+/* DPORT_PMS_PRO_IRAM0_RTCFAST_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R  (BIT(12))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R_M  (BIT(12))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R_V  0x1
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_R_S  12
+/* DPORT_PMS_PRO_IRAM0_RTCFAST_L_F : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F  (BIT(11))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F_M  (BIT(11))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F_V  0x1
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_L_F_S  11
+/* DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR  0x000007FF
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_M  ((DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_V)<<(DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S))
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_V  0x7FF
+#define DPORT_PMS_PRO_IRAM0_RTCFAST_SPLTADDR_S  0
+
+#define DPORT_PMS_PRO_IRAM0_4_REG          (DR_REG_SENSITIVE_BASE + 0x020)
+/* DPORT_PMS_PRO_IRAM0_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_ILG_INTR  (BIT(2))
+#define DPORT_PMS_PRO_IRAM0_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_PRO_IRAM0_ILG_INTR_V  0x1
+#define DPORT_PMS_PRO_IRAM0_ILG_INTR_S  2
+/* DPORT_PMS_PRO_IRAM0_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_ILG_EN  (BIT(1))
+#define DPORT_PMS_PRO_IRAM0_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_PRO_IRAM0_ILG_EN_V  0x1
+#define DPORT_PMS_PRO_IRAM0_ILG_EN_S  1
+/* DPORT_PMS_PRO_IRAM0_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_ILG_CLR  (BIT(0))
+#define DPORT_PMS_PRO_IRAM0_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_PRO_IRAM0_ILG_CLR_V  0x1
+#define DPORT_PMS_PRO_IRAM0_ILG_CLR_S  0
+
+#define DPORT_PMS_PRO_IRAM0_5_REG          (DR_REG_SENSITIVE_BASE + 0x024)
+/* DPORT_PMS_PRO_IRAM0_ILG_ST : RO ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_IRAM0_ILG_ST  0x003FFFFF
+#define DPORT_PMS_PRO_IRAM0_ILG_ST_M  ((DPORT_PMS_PRO_IRAM0_ILG_ST_V)<<(DPORT_PMS_PRO_IRAM0_ILG_ST_S))
+#define DPORT_PMS_PRO_IRAM0_ILG_ST_V  0x3FFFFF
+#define DPORT_PMS_PRO_IRAM0_ILG_ST_S  0
+
+#define DPORT_PMS_PRO_DRAM0_0_REG          (DR_REG_SENSITIVE_BASE + 0x028)
+/* DPORT_PMS_PRO_DRAM0_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_LOCK  (BIT(0))
+#define DPORT_PMS_PRO_DRAM0_LOCK_M  (BIT(0))
+#define DPORT_PMS_PRO_DRAM0_LOCK_V  0x1
+#define DPORT_PMS_PRO_DRAM0_LOCK_S  0
+
+#define DPORT_PMS_PRO_DRAM0_1_REG          (DR_REG_SENSITIVE_BASE + 0x02C)
+/* DPORT_PMS_PRO_DRAM0_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W  (BIT(28))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W_M  (BIT(28))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_W_S  28
+/* DPORT_PMS_PRO_DRAM0_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R  (BIT(27))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R_M  (BIT(27))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_H_R_S  27
+/* DPORT_PMS_PRO_DRAM0_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W  (BIT(26))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W_M  (BIT(26))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_W_S  26
+/* DPORT_PMS_PRO_DRAM0_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R  (BIT(25))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R_M  (BIT(25))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_L_R_S  25
+/* DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR  0x0001FFFF
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_M  ((DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S))
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_V  0x1FFFF
+#define DPORT_PMS_PRO_DRAM0_SRAM_4_SPLTADDR_S  8
+/* DPORT_PMS_PRO_DRAM0_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_W  (BIT(7))
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_W_M  (BIT(7))
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_W_S  7
+/* DPORT_PMS_PRO_DRAM0_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_R  (BIT(6))
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_R_M  (BIT(6))
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_3_R_S  6
+/* DPORT_PMS_PRO_DRAM0_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_W  (BIT(5))
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_W_M  (BIT(5))
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_W_S  5
+/* DPORT_PMS_PRO_DRAM0_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_R  (BIT(4))
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_R_M  (BIT(4))
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_2_R_S  4
+/* DPORT_PMS_PRO_DRAM0_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_W  (BIT(3))
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_W_M  (BIT(3))
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_W_S  3
+/* DPORT_PMS_PRO_DRAM0_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_R  (BIT(2))
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_R_M  (BIT(2))
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_1_R_S  2
+/* DPORT_PMS_PRO_DRAM0_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_W  (BIT(1))
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_W_M  (BIT(1))
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_W_S  1
+/* DPORT_PMS_PRO_DRAM0_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_R  (BIT(0))
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_R_M  (BIT(0))
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_SRAM_0_R_S  0
+
+#define DPORT_PMS_PRO_DRAM0_2_REG          (DR_REG_SENSITIVE_BASE + 0x030)
+/* DPORT_PMS_PRO_DRAM0_RTCFAST_H_W : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W  (BIT(14))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W_M  (BIT(14))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_W_S  14
+/* DPORT_PMS_PRO_DRAM0_RTCFAST_H_R : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R  (BIT(13))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R_M  (BIT(13))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_H_R_S  13
+/* DPORT_PMS_PRO_DRAM0_RTCFAST_L_W : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W  (BIT(12))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W_M  (BIT(12))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W_V  0x1
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_W_S  12
+/* DPORT_PMS_PRO_DRAM0_RTCFAST_L_R : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R  (BIT(11))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R_M  (BIT(11))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R_V  0x1
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_L_R_S  11
+/* DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR  0x000007FF
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_M  ((DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_V)<<(DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S))
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_V  0x7FF
+#define DPORT_PMS_PRO_DRAM0_RTCFAST_SPLTADDR_S  0
+
+#define DPORT_PMS_PRO_DRAM0_3_REG          (DR_REG_SENSITIVE_BASE + 0x034)
+/* DPORT_PMS_PRO_DRAM0_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_ILG_INTR  (BIT(2))
+#define DPORT_PMS_PRO_DRAM0_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_PRO_DRAM0_ILG_INTR_V  0x1
+#define DPORT_PMS_PRO_DRAM0_ILG_INTR_S  2
+/* DPORT_PMS_PRO_DRAM0_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_ILG_EN  (BIT(1))
+#define DPORT_PMS_PRO_DRAM0_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_PRO_DRAM0_ILG_EN_V  0x1
+#define DPORT_PMS_PRO_DRAM0_ILG_EN_S  1
+/* DPORT_PMS_PRO_DRAM0_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_ILG_CLR  (BIT(0))
+#define DPORT_PMS_PRO_DRAM0_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_PRO_DRAM0_ILG_CLR_V  0x1
+#define DPORT_PMS_PRO_DRAM0_ILG_CLR_S  0
+
+#define DPORT_PMS_PRO_DRAM0_4_REG          (DR_REG_SENSITIVE_BASE + 0x038)
+/* DPORT_PMS_PRO_DRAM0_ILG_ST : RO ;bitpos:[25:0] ;default: 26'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DRAM0_ILG_ST  0x03FFFFFF
+#define DPORT_PMS_PRO_DRAM0_ILG_ST_M  ((DPORT_PMS_PRO_DRAM0_ILG_ST_V)<<(DPORT_PMS_PRO_DRAM0_ILG_ST_S))
+#define DPORT_PMS_PRO_DRAM0_ILG_ST_V  0x3FFFFFF
+#define DPORT_PMS_PRO_DRAM0_ILG_ST_S  0
+
+#define DPORT_PMS_PRO_DPORT_0_REG          (DR_REG_SENSITIVE_BASE + 0x03C)
+/* DPORT_PMS_PRO_DPORT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_LOCK  (BIT(0))
+#define DPORT_PMS_PRO_DPORT_LOCK_M  (BIT(0))
+#define DPORT_PMS_PRO_DPORT_LOCK_V  0x1
+#define DPORT_PMS_PRO_DPORT_LOCK_S  0
+
+#define DPORT_PMS_PRO_DPORT_1_REG          (DR_REG_SENSITIVE_BASE + 0x040)
+/* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID : R/W ;bitpos:[19:16] ;default: 4'b0000 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID  0x0000000F
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_M  ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_S))
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_V  0xF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_VALID_S  16
+/* DPORT_PMS_PRO_DPORT_RTCSLOW_H_W : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W  (BIT(15))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W_M  (BIT(15))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W_V  0x1
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_W_S  15
+/* DPORT_PMS_PRO_DPORT_RTCSLOW_H_R : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R  (BIT(14))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R_M  (BIT(14))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R_V  0x1
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_H_R_S  14
+/* DPORT_PMS_PRO_DPORT_RTCSLOW_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W  (BIT(13))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W_M  (BIT(13))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W_V  0x1
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_W_S  13
+/* DPORT_PMS_PRO_DPORT_RTCSLOW_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R  (BIT(12))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R_M  (BIT(12))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R_V  0x1
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_L_R_S  12
+/* DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR : R/W ;bitpos:[11:1] ;default: 11'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR  0x000007FF
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_M  ((DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_V)<<(DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S))
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_V  0x7FF
+#define DPORT_PMS_PRO_DPORT_RTCSLOW_SPLTADDR_S  1
+/* DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID  (BIT(0))
+#define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID_M  (BIT(0))
+#define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID_V  0x1
+#define DPORT_PMS_PRO_DPORT_APB_PERIPHERAL_FORBID_S  0
+
+#define DPORT_PMS_PRO_DPORT_2_REG          (DR_REG_SENSITIVE_BASE + 0x044)
+/* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0  0x0003FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_M  ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_S))
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_V  0x3FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_0_S  0
+
+#define DPORT_PMS_PRO_DPORT_3_REG          (DR_REG_SENSITIVE_BASE + 0x048)
+/* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1  0x0003FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_M  ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_S))
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_V  0x3FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_1_S  0
+
+#define DPORT_PMS_PRO_DPORT_4_REG          (DR_REG_SENSITIVE_BASE + 0x04C)
+/* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2  0x0003FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_M  ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_S))
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_V  0x3FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_2_S  0
+
+#define DPORT_PMS_PRO_DPORT_5_REG          (DR_REG_SENSITIVE_BASE + 0x050)
+/* DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3 : R/W ;bitpos:[17:0] ;default: 18'h0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3  0x0003FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_M  ((DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_V)<<(DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_S))
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_V  0x3FFFF
+#define DPORT_PMS_PRO_DPORT_RESERVE_FIFO_3_S  0
+
+#define DPORT_PMS_PRO_DPORT_6_REG          (DR_REG_SENSITIVE_BASE + 0x054)
+/* DPORT_PMS_PRO_DPORT_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_ILG_INTR  (BIT(2))
+#define DPORT_PMS_PRO_DPORT_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_PRO_DPORT_ILG_INTR_V  0x1
+#define DPORT_PMS_PRO_DPORT_ILG_INTR_S  2
+/* DPORT_PMS_PRO_DPORT_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_ILG_EN  (BIT(1))
+#define DPORT_PMS_PRO_DPORT_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_PRO_DPORT_ILG_EN_V  0x1
+#define DPORT_PMS_PRO_DPORT_ILG_EN_S  1
+/* DPORT_PMS_PRO_DPORT_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_ILG_CLR  (BIT(0))
+#define DPORT_PMS_PRO_DPORT_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_PRO_DPORT_ILG_CLR_V  0x1
+#define DPORT_PMS_PRO_DPORT_ILG_CLR_S  0
+
+#define DPORT_PMS_PRO_DPORT_7_REG          (DR_REG_SENSITIVE_BASE + 0x058)
+/* DPORT_PMS_PRO_DPORT_ILG_ST : RO ;bitpos:[25:0] ;default: 26'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_DPORT_ILG_ST  0x03FFFFFF
+#define DPORT_PMS_PRO_DPORT_ILG_ST_M  ((DPORT_PMS_PRO_DPORT_ILG_ST_V)<<(DPORT_PMS_PRO_DPORT_ILG_ST_S))
+#define DPORT_PMS_PRO_DPORT_ILG_ST_V  0x3FFFFFF
+#define DPORT_PMS_PRO_DPORT_ILG_ST_S  0
+
+#define DPORT_PMS_PRO_AHB_0_REG          (DR_REG_SENSITIVE_BASE + 0x05C)
+/* DPORT_PMS_PRO_AHB_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_LOCK  (BIT(0))
+#define DPORT_PMS_PRO_AHB_LOCK_M  (BIT(0))
+#define DPORT_PMS_PRO_AHB_LOCK_V  0x1
+#define DPORT_PMS_PRO_AHB_LOCK_S  0
+
+#define DPORT_PMS_PRO_AHB_1_REG          (DR_REG_SENSITIVE_BASE + 0x060)
+/* DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W  (BIT(16))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W_M  (BIT(16))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_W_S  16
+/* DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R  (BIT(15))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R_M  (BIT(15))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_R_S  15
+/* DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F  (BIT(14))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F_M  (BIT(14))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_H_F_S  14
+/* DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W  (BIT(13))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W_M  (BIT(13))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_W_S  13
+/* DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R  (BIT(12))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R_M  (BIT(12))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_R_S  12
+/* DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F  (BIT(11))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F_M  (BIT(11))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_L_F_S  11
+/* DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR  0x000007FF
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_M  ((DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_V)<<(DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_V  0x7FF
+#define DPORT_PMS_PRO_AHB_RTCSLOW_0_SPLTADDR_S  0
+
+#define DPORT_PMS_PRO_AHB_2_REG          (DR_REG_SENSITIVE_BASE + 0x064)
+/* DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W  (BIT(16))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W_M  (BIT(16))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_W_S  16
+/* DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R  (BIT(15))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R_M  (BIT(15))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_R_S  15
+/* DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F  (BIT(14))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F_M  (BIT(14))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_H_F_S  14
+/* DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W  (BIT(13))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W_M  (BIT(13))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_W_S  13
+/* DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R  (BIT(12))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R_M  (BIT(12))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_R_S  12
+/* DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F  (BIT(11))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F_M  (BIT(11))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F_V  0x1
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_L_F_S  11
+/* DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR : R/W ;bitpos:[10:0] ;default: 11'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR  0x000007FF
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_M  ((DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_V)<<(DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S))
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_V  0x7FF
+#define DPORT_PMS_PRO_AHB_RTCSLOW_1_SPLTADDR_S  0
+
+#define DPORT_PMS_PRO_AHB_3_REG          (DR_REG_SENSITIVE_BASE + 0x068)
+/* DPORT_PMS_PRO_AHB_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_ILG_INTR  (BIT(2))
+#define DPORT_PMS_PRO_AHB_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_PRO_AHB_ILG_INTR_V  0x1
+#define DPORT_PMS_PRO_AHB_ILG_INTR_S  2
+/* DPORT_PMS_PRO_AHB_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_ILG_EN  (BIT(1))
+#define DPORT_PMS_PRO_AHB_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_PRO_AHB_ILG_EN_V  0x1
+#define DPORT_PMS_PRO_AHB_ILG_EN_S  1
+/* DPORT_PMS_PRO_AHB_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_ILG_CLR  (BIT(0))
+#define DPORT_PMS_PRO_AHB_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_PRO_AHB_ILG_CLR_V  0x1
+#define DPORT_PMS_PRO_AHB_ILG_CLR_S  0
+
+#define DPORT_PMS_PRO_AHB_4_REG          (DR_REG_SENSITIVE_BASE + 0x06C)
+/* DPORT_PMS_PRO_AHB_ILG_ST : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_AHB_ILG_ST  0xFFFFFFFF
+#define DPORT_PMS_PRO_AHB_ILG_ST_M  ((DPORT_PMS_PRO_AHB_ILG_ST_V)<<(DPORT_PMS_PRO_AHB_ILG_ST_S))
+#define DPORT_PMS_PRO_AHB_ILG_ST_V  0xFFFFFFFF
+#define DPORT_PMS_PRO_AHB_ILG_ST_S  0
+
+#define DPORT_PMS_PRO_TRACE_0_REG          (DR_REG_SENSITIVE_BASE + 0x070)
+/* DPORT_PMS_PRO_TRACE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_TRACE_LOCK  (BIT(0))
+#define DPORT_PMS_PRO_TRACE_LOCK_M  (BIT(0))
+#define DPORT_PMS_PRO_TRACE_LOCK_V  0x1
+#define DPORT_PMS_PRO_TRACE_LOCK_S  0
+
+#define DPORT_PMS_PRO_TRACE_1_REG          (DR_REG_SENSITIVE_BASE + 0x074)
+/* DPORT_PMS_PRO_TRACE_DISABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_TRACE_DISABLE  (BIT(0))
+#define DPORT_PMS_PRO_TRACE_DISABLE_M  (BIT(0))
+#define DPORT_PMS_PRO_TRACE_DISABLE_V  0x1
+#define DPORT_PMS_PRO_TRACE_DISABLE_S  0
+
+#define DPORT_PMS_PRO_CACHE_0_REG          (DR_REG_SENSITIVE_BASE + 0x078)
+/* DPORT_PMS_PRO_CACHE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_CACHE_LOCK  (BIT(0))
+#define DPORT_PMS_PRO_CACHE_LOCK_M  (BIT(0))
+#define DPORT_PMS_PRO_CACHE_LOCK_V  0x1
+#define DPORT_PMS_PRO_CACHE_LOCK_S  0
+
+#define DPORT_PMS_PRO_CACHE_1_REG          (DR_REG_SENSITIVE_BASE + 0x07C)
+/* DPORT_PMS_PRO_CACHE_CONNECT : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_CACHE_CONNECT  0x0000FFFF
+#define DPORT_PMS_PRO_CACHE_CONNECT_M  ((DPORT_PMS_PRO_CACHE_CONNECT_V)<<(DPORT_PMS_PRO_CACHE_CONNECT_S))
+#define DPORT_PMS_PRO_CACHE_CONNECT_V  0xFFFF
+#define DPORT_PMS_PRO_CACHE_CONNECT_S  0
+
+#define DPORT_PMS_PRO_CACHE_2_REG          (DR_REG_SENSITIVE_BASE + 0x080)
+/* DPORT_PMS_PRO_CACHE_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_CACHE_ILG_INTR  (BIT(2))
+#define DPORT_PMS_PRO_CACHE_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_PRO_CACHE_ILG_INTR_V  0x1
+#define DPORT_PMS_PRO_CACHE_ILG_INTR_S  2
+/* DPORT_PMS_PRO_CACHE_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_CACHE_ILG_EN  (BIT(1))
+#define DPORT_PMS_PRO_CACHE_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_PRO_CACHE_ILG_EN_V  0x1
+#define DPORT_PMS_PRO_CACHE_ILG_EN_S  1
+/* DPORT_PMS_PRO_CACHE_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_CACHE_ILG_CLR  (BIT(0))
+#define DPORT_PMS_PRO_CACHE_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_PRO_CACHE_ILG_CLR_V  0x1
+#define DPORT_PMS_PRO_CACHE_ILG_CLR_S  0
+
+#define DPORT_PMS_PRO_CACHE_3_REG          (DR_REG_SENSITIVE_BASE + 0x084)
+/* DPORT_PMS_PRO_CACHE_ILG_ST_I : RO ;bitpos:[16:0] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_CACHE_ILG_ST_I  0x0001FFFF
+#define DPORT_PMS_PRO_CACHE_ILG_ST_I_M  ((DPORT_PMS_PRO_CACHE_ILG_ST_I_V)<<(DPORT_PMS_PRO_CACHE_ILG_ST_I_S))
+#define DPORT_PMS_PRO_CACHE_ILG_ST_I_V  0x1FFFF
+#define DPORT_PMS_PRO_CACHE_ILG_ST_I_S  0
+
+#define DPORT_PMS_PRO_CACHE_4_REG          (DR_REG_SENSITIVE_BASE + 0x088)
+/* DPORT_PMS_PRO_CACHE_ILG_ST_D : RO ;bitpos:[16:0] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_PMS_PRO_CACHE_ILG_ST_D  0x0001FFFF
+#define DPORT_PMS_PRO_CACHE_ILG_ST_D_M  ((DPORT_PMS_PRO_CACHE_ILG_ST_D_V)<<(DPORT_PMS_PRO_CACHE_ILG_ST_D_S))
+#define DPORT_PMS_PRO_CACHE_ILG_ST_D_V  0x1FFFF
+#define DPORT_PMS_PRO_CACHE_ILG_ST_D_S  0
+
+#define DPORT_PMS_DMA_APB_I_0_REG          (DR_REG_SENSITIVE_BASE + 0x08C)
+/* DPORT_PMS_DMA_APB_I_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_LOCK  (BIT(0))
+#define DPORT_PMS_DMA_APB_I_LOCK_M  (BIT(0))
+#define DPORT_PMS_DMA_APB_I_LOCK_V  0x1
+#define DPORT_PMS_DMA_APB_I_LOCK_S  0
+
+#define DPORT_PMS_DMA_APB_I_1_REG          (DR_REG_SENSITIVE_BASE + 0x090)
+/* DPORT_PMS_DMA_APB_I_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_W  (BIT(28))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_W_M  (BIT(28))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_W_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_W_S  28
+/* DPORT_PMS_DMA_APB_I_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_R  (BIT(27))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_R_M  (BIT(27))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_R_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_4_H_R_S  27
+/* DPORT_PMS_DMA_APB_I_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_W  (BIT(26))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_W_M  (BIT(26))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_W_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_W_S  26
+/* DPORT_PMS_DMA_APB_I_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_R  (BIT(25))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_R_M  (BIT(25))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_R_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_4_L_R_S  25
+/* DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR  0x0001FFFF
+#define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_M  ((DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_S))
+#define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_V  0x1FFFF
+#define DPORT_PMS_DMA_APB_I_SRAM_4_SPLTADDR_S  8
+/* DPORT_PMS_DMA_APB_I_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_3_W  (BIT(7))
+#define DPORT_PMS_DMA_APB_I_SRAM_3_W_M  (BIT(7))
+#define DPORT_PMS_DMA_APB_I_SRAM_3_W_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_3_W_S  7
+/* DPORT_PMS_DMA_APB_I_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_3_R  (BIT(6))
+#define DPORT_PMS_DMA_APB_I_SRAM_3_R_M  (BIT(6))
+#define DPORT_PMS_DMA_APB_I_SRAM_3_R_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_3_R_S  6
+/* DPORT_PMS_DMA_APB_I_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_2_W  (BIT(5))
+#define DPORT_PMS_DMA_APB_I_SRAM_2_W_M  (BIT(5))
+#define DPORT_PMS_DMA_APB_I_SRAM_2_W_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_2_W_S  5
+/* DPORT_PMS_DMA_APB_I_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_2_R  (BIT(4))
+#define DPORT_PMS_DMA_APB_I_SRAM_2_R_M  (BIT(4))
+#define DPORT_PMS_DMA_APB_I_SRAM_2_R_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_2_R_S  4
+/* DPORT_PMS_DMA_APB_I_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_1_W  (BIT(3))
+#define DPORT_PMS_DMA_APB_I_SRAM_1_W_M  (BIT(3))
+#define DPORT_PMS_DMA_APB_I_SRAM_1_W_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_1_W_S  3
+/* DPORT_PMS_DMA_APB_I_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_1_R  (BIT(2))
+#define DPORT_PMS_DMA_APB_I_SRAM_1_R_M  (BIT(2))
+#define DPORT_PMS_DMA_APB_I_SRAM_1_R_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_1_R_S  2
+/* DPORT_PMS_DMA_APB_I_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_0_W  (BIT(1))
+#define DPORT_PMS_DMA_APB_I_SRAM_0_W_M  (BIT(1))
+#define DPORT_PMS_DMA_APB_I_SRAM_0_W_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_0_W_S  1
+/* DPORT_PMS_DMA_APB_I_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_SRAM_0_R  (BIT(0))
+#define DPORT_PMS_DMA_APB_I_SRAM_0_R_M  (BIT(0))
+#define DPORT_PMS_DMA_APB_I_SRAM_0_R_V  0x1
+#define DPORT_PMS_DMA_APB_I_SRAM_0_R_S  0
+
+#define DPORT_PMS_DMA_APB_I_2_REG          (DR_REG_SENSITIVE_BASE + 0x094)
+/* DPORT_PMS_DMA_APB_I_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_ILG_INTR  (BIT(2))
+#define DPORT_PMS_DMA_APB_I_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_DMA_APB_I_ILG_INTR_V  0x1
+#define DPORT_PMS_DMA_APB_I_ILG_INTR_S  2
+/* DPORT_PMS_DMA_APB_I_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_ILG_EN  (BIT(1))
+#define DPORT_PMS_DMA_APB_I_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_DMA_APB_I_ILG_EN_V  0x1
+#define DPORT_PMS_DMA_APB_I_ILG_EN_S  1
+/* DPORT_PMS_DMA_APB_I_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_ILG_CLR  (BIT(0))
+#define DPORT_PMS_DMA_APB_I_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_DMA_APB_I_ILG_CLR_V  0x1
+#define DPORT_PMS_DMA_APB_I_ILG_CLR_S  0
+
+#define DPORT_PMS_DMA_APB_I_3_REG          (DR_REG_SENSITIVE_BASE + 0x098)
+/* DPORT_PMS_DMA_APB_I_ILG_ST : RO ;bitpos:[22:0] ;default: 23'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_APB_I_ILG_ST  0x007FFFFF
+#define DPORT_PMS_DMA_APB_I_ILG_ST_M  ((DPORT_PMS_DMA_APB_I_ILG_ST_V)<<(DPORT_PMS_DMA_APB_I_ILG_ST_S))
+#define DPORT_PMS_DMA_APB_I_ILG_ST_V  0x7FFFFF
+#define DPORT_PMS_DMA_APB_I_ILG_ST_S  0
+
+#define DPORT_PMS_DMA_RX_I_0_REG          (DR_REG_SENSITIVE_BASE + 0x09C)
+/* DPORT_PMS_DMA_RX_I_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_LOCK  (BIT(0))
+#define DPORT_PMS_DMA_RX_I_LOCK_M  (BIT(0))
+#define DPORT_PMS_DMA_RX_I_LOCK_V  0x1
+#define DPORT_PMS_DMA_RX_I_LOCK_S  0
+
+#define DPORT_PMS_DMA_RX_I_1_REG          (DR_REG_SENSITIVE_BASE + 0x0A0)
+/* DPORT_PMS_DMA_RX_I_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_W  (BIT(28))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_W_M  (BIT(28))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_W_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_W_S  28
+/* DPORT_PMS_DMA_RX_I_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_R  (BIT(27))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_R_M  (BIT(27))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_R_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_4_H_R_S  27
+/* DPORT_PMS_DMA_RX_I_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_W  (BIT(26))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_W_M  (BIT(26))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_W_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_W_S  26
+/* DPORT_PMS_DMA_RX_I_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_R  (BIT(25))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_R_M  (BIT(25))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_R_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_4_L_R_S  25
+/* DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR  0x0001FFFF
+#define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_M  ((DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_S))
+#define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_V  0x1FFFF
+#define DPORT_PMS_DMA_RX_I_SRAM_4_SPLTADDR_S  8
+/* DPORT_PMS_DMA_RX_I_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_3_W  (BIT(7))
+#define DPORT_PMS_DMA_RX_I_SRAM_3_W_M  (BIT(7))
+#define DPORT_PMS_DMA_RX_I_SRAM_3_W_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_3_W_S  7
+/* DPORT_PMS_DMA_RX_I_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_3_R  (BIT(6))
+#define DPORT_PMS_DMA_RX_I_SRAM_3_R_M  (BIT(6))
+#define DPORT_PMS_DMA_RX_I_SRAM_3_R_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_3_R_S  6
+/* DPORT_PMS_DMA_RX_I_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_2_W  (BIT(5))
+#define DPORT_PMS_DMA_RX_I_SRAM_2_W_M  (BIT(5))
+#define DPORT_PMS_DMA_RX_I_SRAM_2_W_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_2_W_S  5
+/* DPORT_PMS_DMA_RX_I_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_2_R  (BIT(4))
+#define DPORT_PMS_DMA_RX_I_SRAM_2_R_M  (BIT(4))
+#define DPORT_PMS_DMA_RX_I_SRAM_2_R_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_2_R_S  4
+/* DPORT_PMS_DMA_RX_I_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_1_W  (BIT(3))
+#define DPORT_PMS_DMA_RX_I_SRAM_1_W_M  (BIT(3))
+#define DPORT_PMS_DMA_RX_I_SRAM_1_W_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_1_W_S  3
+/* DPORT_PMS_DMA_RX_I_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_1_R  (BIT(2))
+#define DPORT_PMS_DMA_RX_I_SRAM_1_R_M  (BIT(2))
+#define DPORT_PMS_DMA_RX_I_SRAM_1_R_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_1_R_S  2
+/* DPORT_PMS_DMA_RX_I_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_0_W  (BIT(1))
+#define DPORT_PMS_DMA_RX_I_SRAM_0_W_M  (BIT(1))
+#define DPORT_PMS_DMA_RX_I_SRAM_0_W_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_0_W_S  1
+/* DPORT_PMS_DMA_RX_I_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_SRAM_0_R  (BIT(0))
+#define DPORT_PMS_DMA_RX_I_SRAM_0_R_M  (BIT(0))
+#define DPORT_PMS_DMA_RX_I_SRAM_0_R_V  0x1
+#define DPORT_PMS_DMA_RX_I_SRAM_0_R_S  0
+
+#define DPORT_PMS_DMA_RX_I_2_REG          (DR_REG_SENSITIVE_BASE + 0x0A4)
+/* DPORT_PMS_DMA_RX_I_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_ILG_INTR  (BIT(2))
+#define DPORT_PMS_DMA_RX_I_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_DMA_RX_I_ILG_INTR_V  0x1
+#define DPORT_PMS_DMA_RX_I_ILG_INTR_S  2
+/* DPORT_PMS_DMA_RX_I_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_ILG_EN  (BIT(1))
+#define DPORT_PMS_DMA_RX_I_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_DMA_RX_I_ILG_EN_V  0x1
+#define DPORT_PMS_DMA_RX_I_ILG_EN_S  1
+/* DPORT_PMS_DMA_RX_I_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_ILG_CLR  (BIT(0))
+#define DPORT_PMS_DMA_RX_I_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_DMA_RX_I_ILG_CLR_V  0x1
+#define DPORT_PMS_DMA_RX_I_ILG_CLR_S  0
+
+#define DPORT_PMS_DMA_RX_I_3_REG          (DR_REG_SENSITIVE_BASE + 0x0A8)
+/* DPORT_PMS_DMA_RX_I_ILG_ST : RO ;bitpos:[22:0] ;default: 23'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_RX_I_ILG_ST  0x007FFFFF
+#define DPORT_PMS_DMA_RX_I_ILG_ST_M  ((DPORT_PMS_DMA_RX_I_ILG_ST_V)<<(DPORT_PMS_DMA_RX_I_ILG_ST_S))
+#define DPORT_PMS_DMA_RX_I_ILG_ST_V  0x7FFFFF
+#define DPORT_PMS_DMA_RX_I_ILG_ST_S  0
+
+#define DPORT_PMS_DMA_TX_I_0_REG          (DR_REG_SENSITIVE_BASE + 0x0AC)
+/* DPORT_PMS_DMA_TX_I_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_LOCK  (BIT(0))
+#define DPORT_PMS_DMA_TX_I_LOCK_M  (BIT(0))
+#define DPORT_PMS_DMA_TX_I_LOCK_V  0x1
+#define DPORT_PMS_DMA_TX_I_LOCK_S  0
+
+#define DPORT_PMS_DMA_TX_I_1_REG          (DR_REG_SENSITIVE_BASE + 0x0B0)
+/* DPORT_PMS_DMA_TX_I_SRAM_4_H_W : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_W  (BIT(28))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_W_M  (BIT(28))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_W_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_W_S  28
+/* DPORT_PMS_DMA_TX_I_SRAM_4_H_R : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_R  (BIT(27))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_R_M  (BIT(27))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_R_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_4_H_R_S  27
+/* DPORT_PMS_DMA_TX_I_SRAM_4_L_W : R/W ;bitpos:[26] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_W  (BIT(26))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_W_M  (BIT(26))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_W_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_W_S  26
+/* DPORT_PMS_DMA_TX_I_SRAM_4_L_R : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_R  (BIT(25))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_R_M  (BIT(25))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_R_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_4_L_R_S  25
+/* DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR : R/W ;bitpos:[24:8] ;default: 17'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR  0x0001FFFF
+#define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_M  ((DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_V)<<(DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_S))
+#define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_V  0x1FFFF
+#define DPORT_PMS_DMA_TX_I_SRAM_4_SPLTADDR_S  8
+/* DPORT_PMS_DMA_TX_I_SRAM_3_W : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_3_W  (BIT(7))
+#define DPORT_PMS_DMA_TX_I_SRAM_3_W_M  (BIT(7))
+#define DPORT_PMS_DMA_TX_I_SRAM_3_W_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_3_W_S  7
+/* DPORT_PMS_DMA_TX_I_SRAM_3_R : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_3_R  (BIT(6))
+#define DPORT_PMS_DMA_TX_I_SRAM_3_R_M  (BIT(6))
+#define DPORT_PMS_DMA_TX_I_SRAM_3_R_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_3_R_S  6
+/* DPORT_PMS_DMA_TX_I_SRAM_2_W : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_2_W  (BIT(5))
+#define DPORT_PMS_DMA_TX_I_SRAM_2_W_M  (BIT(5))
+#define DPORT_PMS_DMA_TX_I_SRAM_2_W_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_2_W_S  5
+/* DPORT_PMS_DMA_TX_I_SRAM_2_R : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_2_R  (BIT(4))
+#define DPORT_PMS_DMA_TX_I_SRAM_2_R_M  (BIT(4))
+#define DPORT_PMS_DMA_TX_I_SRAM_2_R_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_2_R_S  4
+/* DPORT_PMS_DMA_TX_I_SRAM_1_W : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_1_W  (BIT(3))
+#define DPORT_PMS_DMA_TX_I_SRAM_1_W_M  (BIT(3))
+#define DPORT_PMS_DMA_TX_I_SRAM_1_W_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_1_W_S  3
+/* DPORT_PMS_DMA_TX_I_SRAM_1_R : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_1_R  (BIT(2))
+#define DPORT_PMS_DMA_TX_I_SRAM_1_R_M  (BIT(2))
+#define DPORT_PMS_DMA_TX_I_SRAM_1_R_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_1_R_S  2
+/* DPORT_PMS_DMA_TX_I_SRAM_0_W : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_0_W  (BIT(1))
+#define DPORT_PMS_DMA_TX_I_SRAM_0_W_M  (BIT(1))
+#define DPORT_PMS_DMA_TX_I_SRAM_0_W_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_0_W_S  1
+/* DPORT_PMS_DMA_TX_I_SRAM_0_R : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_SRAM_0_R  (BIT(0))
+#define DPORT_PMS_DMA_TX_I_SRAM_0_R_M  (BIT(0))
+#define DPORT_PMS_DMA_TX_I_SRAM_0_R_V  0x1
+#define DPORT_PMS_DMA_TX_I_SRAM_0_R_S  0
+
+#define DPORT_PMS_DMA_TX_I_2_REG          (DR_REG_SENSITIVE_BASE + 0x0B4)
+/* DPORT_PMS_DMA_TX_I_ILG_INTR : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_ILG_INTR  (BIT(2))
+#define DPORT_PMS_DMA_TX_I_ILG_INTR_M  (BIT(2))
+#define DPORT_PMS_DMA_TX_I_ILG_INTR_V  0x1
+#define DPORT_PMS_DMA_TX_I_ILG_INTR_S  2
+/* DPORT_PMS_DMA_TX_I_ILG_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_ILG_EN  (BIT(1))
+#define DPORT_PMS_DMA_TX_I_ILG_EN_M  (BIT(1))
+#define DPORT_PMS_DMA_TX_I_ILG_EN_V  0x1
+#define DPORT_PMS_DMA_TX_I_ILG_EN_S  1
+/* DPORT_PMS_DMA_TX_I_ILG_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_ILG_CLR  (BIT(0))
+#define DPORT_PMS_DMA_TX_I_ILG_CLR_M  (BIT(0))
+#define DPORT_PMS_DMA_TX_I_ILG_CLR_V  0x1
+#define DPORT_PMS_DMA_TX_I_ILG_CLR_S  0
+
+#define DPORT_PMS_DMA_TX_I_3_REG          (DR_REG_SENSITIVE_BASE + 0x0B8)
+/* DPORT_PMS_DMA_TX_I_ILG_ST : RO ;bitpos:[22:0] ;default: 23'b0 ; */
+/*description: */
+#define DPORT_PMS_DMA_TX_I_ILG_ST  0x007FFFFF
+#define DPORT_PMS_DMA_TX_I_ILG_ST_M  ((DPORT_PMS_DMA_TX_I_ILG_ST_V)<<(DPORT_PMS_DMA_TX_I_ILG_ST_S))
+#define DPORT_PMS_DMA_TX_I_ILG_ST_V  0x7FFFFF
+#define DPORT_PMS_DMA_TX_I_ILG_ST_S  0
+
+#define DPORT_PRO_BOOT_LOCATION_0_REG          (DR_REG_SENSITIVE_BASE + 0x0BC)
+/* DPORT_PRO_BOOT_LOCATION_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_BOOT_LOCATION_LOCK  (BIT(0))
+#define DPORT_PRO_BOOT_LOCATION_LOCK_M  (BIT(0))
+#define DPORT_PRO_BOOT_LOCATION_LOCK_V  0x1
+#define DPORT_PRO_BOOT_LOCATION_LOCK_S  0
+
+#define DPORT_PRO_BOOT_LOCATION_1_REG          (DR_REG_SENSITIVE_BASE + 0x0C0)
+/* DPORT_PRO_BOOT_REMAP : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_BOOT_REMAP  (BIT(0))
+#define DPORT_PRO_BOOT_REMAP_M  (BIT(0))
+#define DPORT_PRO_BOOT_REMAP_V  0x1
+#define DPORT_PRO_BOOT_REMAP_S  0
+
+#define DPORT_CACHE_SOURCE_0_REG          (DR_REG_SENSITIVE_BASE + 0x0C4)
+/* DPORT_CACHE_SOURCE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CACHE_SOURCE_LOCK  (BIT(0))
+#define DPORT_CACHE_SOURCE_LOCK_M  (BIT(0))
+#define DPORT_CACHE_SOURCE_LOCK_V  0x1
+#define DPORT_CACHE_SOURCE_LOCK_S  0
+
+#define DPORT_CACHE_SOURCE_1_REG          (DR_REG_SENSITIVE_BASE + 0x0C8)
+/* DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0  (BIT(5))
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0_M  (BIT(5))
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0_V  0x1
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DROM0_S  5
+/* DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT  (BIT(4))
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT_M  (BIT(4))
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT_V  0x1
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DPORT_S  4
+/* DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0  (BIT(3))
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0_M  (BIT(3))
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0_V  0x1
+#define DPORT_PRO_CACHE_D_SOURCE_PRO_DRAM0_S  3
+/* DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0  (BIT(2))
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0_M  (BIT(2))
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0_V  0x1
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_DROM0_S  2
+/* DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0  (BIT(1))
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0_M  (BIT(1))
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0_V  0x1
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IROM0_S  1
+/* DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1  (BIT(0))
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1_M  (BIT(0))
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1_V  0x1
+#define DPORT_PRO_CACHE_I_SOURCE_PRO_IRAM1_S  0
+
+#define DPORT_APB_PERIPHERAL_0_REG          (DR_REG_SENSITIVE_BASE + 0x0CC)
+/* DPORT_APB_PERIPHERAL_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APB_PERIPHERAL_LOCK  (BIT(0))
+#define DPORT_APB_PERIPHERAL_LOCK_M  (BIT(0))
+#define DPORT_APB_PERIPHERAL_LOCK_V  0x1
+#define DPORT_APB_PERIPHERAL_LOCK_S  0
+
+#define DPORT_APB_PERIPHERAL_1_REG          (DR_REG_SENSITIVE_BASE + 0x0D0)
+/* DPORT_APB_PERIPHERAL_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APB_PERIPHERAL_SPLIT_BURST  (BIT(0))
+#define DPORT_APB_PERIPHERAL_SPLIT_BURST_M  (BIT(0))
+#define DPORT_APB_PERIPHERAL_SPLIT_BURST_V  0x1
+#define DPORT_APB_PERIPHERAL_SPLIT_BURST_S  0
+
+#define DPORT_PMS_OCCUPY_0_REG          (DR_REG_SENSITIVE_BASE + 0x0D4)
+/* DPORT_PMS_OCCUPY_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PMS_OCCUPY_LOCK  (BIT(0))
+#define DPORT_PMS_OCCUPY_LOCK_M  (BIT(0))
+#define DPORT_PMS_OCCUPY_LOCK_V  0x1
+#define DPORT_PMS_OCCUPY_LOCK_S  0
+
+#define DPORT_PMS_OCCUPY_1_REG          (DR_REG_SENSITIVE_BASE + 0x0D8)
+/* DPORT_PMS_OCCUPY_CACHE : R/W ;bitpos:[3:0] ;default: 4'b0000 ; */
+/*description: */
+#define DPORT_PMS_OCCUPY_CACHE  0x0000000F
+#define DPORT_PMS_OCCUPY_CACHE_M  ((DPORT_PMS_OCCUPY_CACHE_V)<<(DPORT_PMS_OCCUPY_CACHE_S))
+#define DPORT_PMS_OCCUPY_CACHE_V  0xF
+#define DPORT_PMS_OCCUPY_CACHE_S  0
+
+#define DPORT_PMS_OCCUPY_2_REG          (DR_REG_SENSITIVE_BASE + 0x0DC)
+/* DPORT_PMS_OCCUPY_MAC_DUMP : R/W ;bitpos:[3:0] ;default: 4'b0000 ; */
+/*description: */
+#define DPORT_PMS_OCCUPY_MAC_DUMP  0x0000000F
+#define DPORT_PMS_OCCUPY_MAC_DUMP_M  ((DPORT_PMS_OCCUPY_MAC_DUMP_V)<<(DPORT_PMS_OCCUPY_MAC_DUMP_S))
+#define DPORT_PMS_OCCUPY_MAC_DUMP_V  0xF
+#define DPORT_PMS_OCCUPY_MAC_DUMP_S  0
+
+#define DPORT_PMS_OCCUPY_3_REG          (DR_REG_SENSITIVE_BASE + 0x0E0)
+/* DPORT_PMS_OCCUPY_PRO_TRACE : R/W ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: */
+#define DPORT_PMS_OCCUPY_PRO_TRACE  0x0003FFFF
+#define DPORT_PMS_OCCUPY_PRO_TRACE_M  ((DPORT_PMS_OCCUPY_PRO_TRACE_V)<<(DPORT_PMS_OCCUPY_PRO_TRACE_S))
+#define DPORT_PMS_OCCUPY_PRO_TRACE_V  0x3FFFF
+#define DPORT_PMS_OCCUPY_PRO_TRACE_S  0
+
+#define DPORT_CACHE_TAG_ACCESS_0_REG          (DR_REG_SENSITIVE_BASE + 0x0E4)
+/* DPORT_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CACHE_TAG_ACCESS_LOCK  (BIT(0))
+#define DPORT_CACHE_TAG_ACCESS_LOCK_M  (BIT(0))
+#define DPORT_CACHE_TAG_ACCESS_LOCK_V  0x1
+#define DPORT_CACHE_TAG_ACCESS_LOCK_S  0
+
+#define DPORT_CACHE_TAG_ACCESS_1_REG          (DR_REG_SENSITIVE_BASE + 0x0E8)
+/* DPORT_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_D_TAG_WR_ACS  (BIT(3))
+#define DPORT_PRO_D_TAG_WR_ACS_M  (BIT(3))
+#define DPORT_PRO_D_TAG_WR_ACS_V  0x1
+#define DPORT_PRO_D_TAG_WR_ACS_S  3
+/* DPORT_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_D_TAG_RD_ACS  (BIT(2))
+#define DPORT_PRO_D_TAG_RD_ACS_M  (BIT(2))
+#define DPORT_PRO_D_TAG_RD_ACS_V  0x1
+#define DPORT_PRO_D_TAG_RD_ACS_S  2
+/* DPORT_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_I_TAG_WR_ACS  (BIT(1))
+#define DPORT_PRO_I_TAG_WR_ACS_M  (BIT(1))
+#define DPORT_PRO_I_TAG_WR_ACS_V  0x1
+#define DPORT_PRO_I_TAG_WR_ACS_S  1
+/* DPORT_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_I_TAG_RD_ACS  (BIT(0))
+#define DPORT_PRO_I_TAG_RD_ACS_M  (BIT(0))
+#define DPORT_PRO_I_TAG_RD_ACS_V  0x1
+#define DPORT_PRO_I_TAG_RD_ACS_S  0
+
+#define SENSITIVE_CLOCK_GATE_REG          (DR_REG_SENSITIVE_BASE + 0x0EC)
+/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SENSITIVE_CLK_EN  (BIT(0))
+#define SENSITIVE_CLK_EN_M  (BIT(0))
+#define SENSITIVE_CLK_EN_V  0x1
+#define SENSITIVE_CLK_EN_S  0
+
+#define SENSITIVE_DATE_REG          (DR_REG_SENSITIVE_BASE + 0xFFC)
+/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h1809042 ; */
+/*description: */
+#define SENSITIVE_DATE  0x0FFFFFFF
+#define SENSITIVE_DATE_M  ((SENSITIVE_DATE_V)<<(SENSITIVE_DATE_S))
+#define SENSITIVE_DATE_V  0xFFFFFFF
+#define SENSITIVE_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SENSITIVE_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/slc_reg.h b/components/soc/esp32s2beta/include/soc/slc_reg.h
new file mode 100644
index 000000000..a4f59af99
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/slc_reg.h
@@ -0,0 +1,1914 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SLC_REG_H_
+#define _SOC_SLC_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SLC_CONF0_REG          (DR_REG_SLC_BASE + 0x0)
+/* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_MASK_EN  (BIT(18))
+#define SLC_SLC0_WR_RETRY_MASK_EN_M  (BIT(18))
+#define SLC_SLC0_WR_RETRY_MASK_EN_V  0x1
+#define SLC_SLC0_WR_RETRY_MASK_EN_S  18
+/* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TOKEN_SEL  (BIT(15))
+#define SLC_SLC0_TOKEN_SEL_M  (BIT(15))
+#define SLC_SLC0_TOKEN_SEL_V  0x1
+#define SLC_SLC0_TOKEN_SEL_S  15
+/* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TOKEN_AUTO_CLR  (BIT(14))
+#define SLC_SLC0_TOKEN_AUTO_CLR_M  (BIT(14))
+#define SLC_SLC0_TOKEN_AUTO_CLR_V  0x1
+#define SLC_SLC0_TOKEN_AUTO_CLR_S  14
+/* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TXDATA_BURST_EN  (BIT(13))
+#define SLC_SLC0_TXDATA_BURST_EN_M  (BIT(13))
+#define SLC_SLC0_TXDATA_BURST_EN_V  0x1
+#define SLC_SLC0_TXDATA_BURST_EN_S  13
+/* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TXDSCR_BURST_EN  (BIT(12))
+#define SLC_SLC0_TXDSCR_BURST_EN_M  (BIT(12))
+#define SLC_SLC0_TXDSCR_BURST_EN_V  0x1
+#define SLC_SLC0_TXDSCR_BURST_EN_S  12
+/* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_AUTO_RET  (BIT(11))
+#define SLC_SLC0_TXLINK_AUTO_RET_M  (BIT(11))
+#define SLC_SLC0_TXLINK_AUTO_RET_V  0x1
+#define SLC_SLC0_TXLINK_AUTO_RET_S  11
+/* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_AUTO_RET  (BIT(10))
+#define SLC_SLC0_RXLINK_AUTO_RET_M  (BIT(10))
+#define SLC_SLC0_RXLINK_AUTO_RET_V  0x1
+#define SLC_SLC0_RXLINK_AUTO_RET_S  10
+/* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RXDATA_BURST_EN  (BIT(9))
+#define SLC_SLC0_RXDATA_BURST_EN_M  (BIT(9))
+#define SLC_SLC0_RXDATA_BURST_EN_V  0x1
+#define SLC_SLC0_RXDATA_BURST_EN_S  9
+/* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RXDSCR_BURST_EN  (BIT(8))
+#define SLC_SLC0_RXDSCR_BURST_EN_M  (BIT(8))
+#define SLC_SLC0_RXDSCR_BURST_EN_V  0x1
+#define SLC_SLC0_RXDSCR_BURST_EN_S  8
+/* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_NO_RESTART_CLR  (BIT(7))
+#define SLC_SLC0_RX_NO_RESTART_CLR_M  (BIT(7))
+#define SLC_SLC0_RX_NO_RESTART_CLR_V  0x1
+#define SLC_SLC0_RX_NO_RESTART_CLR_S  7
+/* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_AUTO_WRBACK  (BIT(6))
+#define SLC_SLC0_RX_AUTO_WRBACK_M  (BIT(6))
+#define SLC_SLC0_RX_AUTO_WRBACK_V  0x1
+#define SLC_SLC0_RX_AUTO_WRBACK_S  6
+/* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_LOOP_TEST  (BIT(5))
+#define SLC_SLC0_RX_LOOP_TEST_M  (BIT(5))
+#define SLC_SLC0_RX_LOOP_TEST_V  0x1
+#define SLC_SLC0_RX_LOOP_TEST_S  5
+/* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TX_LOOP_TEST  (BIT(4))
+#define SLC_SLC0_TX_LOOP_TEST_M  (BIT(4))
+#define SLC_SLC0_TX_LOOP_TEST_V  0x1
+#define SLC_SLC0_TX_LOOP_TEST_S  4
+/* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_AHBM_RST  (BIT(3))
+#define SLC_AHBM_RST_M  (BIT(3))
+#define SLC_AHBM_RST_V  0x1
+#define SLC_AHBM_RST_S  3
+/* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_AHBM_FIFO_RST  (BIT(2))
+#define SLC_AHBM_FIFO_RST_M  (BIT(2))
+#define SLC_AHBM_FIFO_RST_V  0x1
+#define SLC_AHBM_FIFO_RST_S  2
+/* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_RST  (BIT(1))
+#define SLC_SLC0_RX_RST_M  (BIT(1))
+#define SLC_SLC0_RX_RST_V  0x1
+#define SLC_SLC0_RX_RST_S  1
+/* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_RST  (BIT(0))
+#define SLC_SLC0_TX_RST_M  (BIT(0))
+#define SLC_SLC0_TX_RST_V  0x1
+#define SLC_SLC0_TX_RST_S  0
+
+#define SLC_0INT_RAW_REG          (DR_REG_SLC_BASE + 0x4)
+/* SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_S  27
+/* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S  26
+/* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_RAW  (BIT(25))
+#define SLC_CMD_DTC_INT_RAW_M  (BIT(25))
+#define SLC_CMD_DTC_INT_RAW_V  0x1
+#define SLC_CMD_DTC_INT_RAW_S  25
+/* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S  24
+/* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S  23
+/* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S  22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S  21
+/* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S  20
+/* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S  19
+/* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_RAW  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_RAW_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_RAW_V  0x1
+#define SLC_SLC0_TOHOST_INT_RAW_S  18
+/* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_RAW  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_RAW_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_RX_EOF_INT_RAW_S  17
+/* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_RAW  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_RAW_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_RAW_V  0x1
+#define SLC_SLC0_RX_DONE_INT_RAW_S  16
+/* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S  15
+/* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_RAW  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_RAW_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_RAW_V  0x1
+#define SLC_SLC0_TX_DONE_INT_RAW_S  14
+/* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S  13
+/* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S  12
+/* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_RAW  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_RAW_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_RAW_V  0x1
+#define SLC_SLC0_TX_OVF_INT_RAW_S  11
+/* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_RAW  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_RAW_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_RAW_V  0x1
+#define SLC_SLC0_RX_UDF_INT_RAW_S  10
+/* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_RAW  (BIT(9))
+#define SLC_SLC0_TX_START_INT_RAW_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_RAW_V  0x1
+#define SLC_SLC0_TX_START_INT_RAW_S  9
+/* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_RAW  (BIT(8))
+#define SLC_SLC0_RX_START_INT_RAW_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_RAW_V  0x1
+#define SLC_SLC0_RX_START_INT_RAW_S  8
+/* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_RAW  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_RAW_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT7_INT_RAW_S  7
+/* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_RAW  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_RAW_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT6_INT_RAW_S  6
+/* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_RAW  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_RAW_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT5_INT_RAW_S  5
+/* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_RAW  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_RAW_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT4_INT_RAW_S  4
+/* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_RAW  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_RAW_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT3_INT_RAW_S  3
+/* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_RAW  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_RAW_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT2_INT_RAW_S  2
+/* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_RAW  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_RAW_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT1_INT_RAW_S  1
+/* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_RAW  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_RAW_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_RAW_V  0x1
+#define SLC_FRHOST_BIT0_INT_RAW_S  0
+
+#define SLC_0INT_ST_REG          (DR_REG_SLC_BASE + 0x8)
+/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_S  27
+/* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S  26
+/* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ST  (BIT(25))
+#define SLC_CMD_DTC_INT_ST_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ST_V  0x1
+#define SLC_CMD_DTC_INT_ST_S  25
+/* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ST  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ST_S  24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S  23
+/* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ST  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ST_S  22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S  21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S  20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S  19
+/* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ST  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST_V  0x1
+#define SLC_SLC0_TOHOST_INT_ST_S  18
+/* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ST  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ST_S  17
+/* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ST  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ST_S  16
+/* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ST  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ST_S  15
+/* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ST  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ST_S  14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S  13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S  12
+/* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ST  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ST_S  11
+/* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ST  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ST_S  10
+/* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ST  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST_V  0x1
+#define SLC_SLC0_TX_START_INT_ST_S  9
+/* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ST  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST_V  0x1
+#define SLC_SLC0_RX_START_INT_ST_S  8
+/* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ST  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST_V  0x1
+#define SLC_FRHOST_BIT7_INT_ST_S  7
+/* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ST  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST_V  0x1
+#define SLC_FRHOST_BIT6_INT_ST_S  6
+/* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ST  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST_V  0x1
+#define SLC_FRHOST_BIT5_INT_ST_S  5
+/* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ST  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST_V  0x1
+#define SLC_FRHOST_BIT4_INT_ST_S  4
+/* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ST  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST_V  0x1
+#define SLC_FRHOST_BIT3_INT_ST_S  3
+/* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ST  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST_V  0x1
+#define SLC_FRHOST_BIT2_INT_ST_S  2
+/* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ST  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST_V  0x1
+#define SLC_FRHOST_BIT1_INT_ST_S  1
+/* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ST  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST_V  0x1
+#define SLC_FRHOST_BIT0_INT_ST_S  0
+
+#define SLC_0INT_ENA_REG          (DR_REG_SLC_BASE + 0xC)
+/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_S  27
+/* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S  26
+/* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ENA  (BIT(25))
+#define SLC_CMD_DTC_INT_ENA_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ENA_V  0x1
+#define SLC_CMD_DTC_INT_ENA_S  25
+/* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S  24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S  23
+/* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S  22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S  21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S  20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S  19
+/* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ENA  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA_V  0x1
+#define SLC_SLC0_TOHOST_INT_ENA_S  18
+/* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ENA  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ENA_S  17
+/* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ENA  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ENA_S  16
+/* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S  15
+/* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ENA  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ENA_S  14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S  13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S  12
+/* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ENA  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ENA_S  11
+/* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ENA  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ENA_S  10
+/* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ENA  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA_V  0x1
+#define SLC_SLC0_TX_START_INT_ENA_S  9
+/* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ENA  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA_V  0x1
+#define SLC_SLC0_RX_START_INT_ENA_S  8
+/* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ENA  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT7_INT_ENA_S  7
+/* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ENA  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT6_INT_ENA_S  6
+/* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ENA  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT5_INT_ENA_S  5
+/* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ENA  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT4_INT_ENA_S  4
+/* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ENA  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT3_INT_ENA_S  3
+/* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ENA  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT2_INT_ENA_S  2
+/* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ENA  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT1_INT_ENA_S  1
+/* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ENA  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA_V  0x1
+#define SLC_FRHOST_BIT0_INT_ENA_S  0
+
+#define SLC_0INT_CLR_REG          (DR_REG_SLC_BASE + 0x10)
+/* SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_S  27
+/* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S  26
+/* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_CLR  (BIT(25))
+#define SLC_CMD_DTC_INT_CLR_M  (BIT(25))
+#define SLC_CMD_DTC_INT_CLR_V  0x1
+#define SLC_CMD_DTC_INT_CLR_S  25
+/* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S  24
+/* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S  23
+/* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S  22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S  21
+/* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S  20
+/* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S  19
+/* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_CLR  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_CLR_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_CLR_V  0x1
+#define SLC_SLC0_TOHOST_INT_CLR_S  18
+/* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_CLR  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_CLR_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_RX_EOF_INT_CLR_S  17
+/* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_CLR  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_CLR_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_CLR_V  0x1
+#define SLC_SLC0_RX_DONE_INT_CLR_S  16
+/* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S  15
+/* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_CLR  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_CLR_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_CLR_V  0x1
+#define SLC_SLC0_TX_DONE_INT_CLR_S  14
+/* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S  13
+/* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S  12
+/* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_CLR  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_CLR_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_CLR_V  0x1
+#define SLC_SLC0_TX_OVF_INT_CLR_S  11
+/* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_CLR  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_CLR_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_CLR_V  0x1
+#define SLC_SLC0_RX_UDF_INT_CLR_S  10
+/* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_CLR  (BIT(9))
+#define SLC_SLC0_TX_START_INT_CLR_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_CLR_V  0x1
+#define SLC_SLC0_TX_START_INT_CLR_S  9
+/* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_CLR  (BIT(8))
+#define SLC_SLC0_RX_START_INT_CLR_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_CLR_V  0x1
+#define SLC_SLC0_RX_START_INT_CLR_S  8
+/* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_CLR  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_CLR_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT7_INT_CLR_S  7
+/* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_CLR  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_CLR_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT6_INT_CLR_S  6
+/* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_CLR  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_CLR_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT5_INT_CLR_S  5
+/* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_CLR  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_CLR_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT4_INT_CLR_S  4
+/* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_CLR  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_CLR_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT3_INT_CLR_S  3
+/* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_CLR  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_CLR_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT2_INT_CLR_S  2
+/* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_CLR  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_CLR_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT1_INT_CLR_S  1
+/* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_CLR  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_CLR_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_CLR_V  0x1
+#define SLC_FRHOST_BIT0_INT_CLR_S  0
+
+#define SLC_RX_STATUS_REG          (DR_REG_SLC_BASE + 0x24)
+/* SLC_SLC0_RX_BUF_LEN : RO ;bitpos:[13:2] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_BUF_LEN  0x00000FFF
+#define SLC_SLC0_RX_BUF_LEN_M  ((SLC_SLC0_RX_BUF_LEN_V)<<(SLC_SLC0_RX_BUF_LEN_S))
+#define SLC_SLC0_RX_BUF_LEN_V  0xFFF
+#define SLC_SLC0_RX_BUF_LEN_S  2
+/* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_EMPTY  (BIT(1))
+#define SLC_SLC0_RX_EMPTY_M  (BIT(1))
+#define SLC_SLC0_RX_EMPTY_V  0x1
+#define SLC_SLC0_RX_EMPTY_S  1
+/* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_FULL  (BIT(0))
+#define SLC_SLC0_RX_FULL_M  (BIT(0))
+#define SLC_SLC0_RX_FULL_V  0x1
+#define SLC_SLC0_RX_FULL_S  0
+
+#define SLC_0RXFIFO_PUSH_REG          (DR_REG_SLC_BASE + 0x28)
+/* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_RXFIFO_PUSH  (BIT(16))
+#define SLC_SLC0_RXFIFO_PUSH_M  (BIT(16))
+#define SLC_SLC0_RXFIFO_PUSH_V  0x1
+#define SLC_SLC0_RXFIFO_PUSH_S  16
+/* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define SLC_SLC0_RXFIFO_WDATA  0x000001FF
+#define SLC_SLC0_RXFIFO_WDATA_M  ((SLC_SLC0_RXFIFO_WDATA_V)<<(SLC_SLC0_RXFIFO_WDATA_S))
+#define SLC_SLC0_RXFIFO_WDATA_V  0x1FF
+#define SLC_SLC0_RXFIFO_WDATA_S  0
+
+#define SLC_TX_STATUS_REG          (DR_REG_SLC_BASE + 0x30)
+/* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TX_EMPTY  (BIT(1))
+#define SLC_SLC0_TX_EMPTY_M  (BIT(1))
+#define SLC_SLC0_TX_EMPTY_V  0x1
+#define SLC_SLC0_TX_EMPTY_S  1
+/* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_FULL  (BIT(0))
+#define SLC_SLC0_TX_FULL_M  (BIT(0))
+#define SLC_SLC0_TX_FULL_V  0x1
+#define SLC_SLC0_TX_FULL_S  0
+
+#define SLC_0TXFIFO_POP_REG          (DR_REG_SLC_BASE + 0x34)
+/* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TXFIFO_POP  (BIT(16))
+#define SLC_SLC0_TXFIFO_POP_M  (BIT(16))
+#define SLC_SLC0_TXFIFO_POP_V  0x1
+#define SLC_SLC0_TXFIFO_POP_S  16
+/* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: */
+#define SLC_SLC0_TXFIFO_RDATA  0x000007FF
+#define SLC_SLC0_TXFIFO_RDATA_M  ((SLC_SLC0_TXFIFO_RDATA_V)<<(SLC_SLC0_TXFIFO_RDATA_S))
+#define SLC_SLC0_TXFIFO_RDATA_V  0x7FF
+#define SLC_SLC0_TXFIFO_RDATA_S  0
+
+#define SLC_0RX_LINK_REG          (DR_REG_SLC_BASE + 0x3C)
+/* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_PARK  (BIT(31))
+#define SLC_SLC0_RXLINK_PARK_M  (BIT(31))
+#define SLC_SLC0_RXLINK_PARK_V  0x1
+#define SLC_SLC0_RXLINK_PARK_S  31
+/* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_RESTART  (BIT(30))
+#define SLC_SLC0_RXLINK_RESTART_M  (BIT(30))
+#define SLC_SLC0_RXLINK_RESTART_V  0x1
+#define SLC_SLC0_RXLINK_RESTART_S  30
+/* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_START  (BIT(29))
+#define SLC_SLC0_RXLINK_START_M  (BIT(29))
+#define SLC_SLC0_RXLINK_START_V  0x1
+#define SLC_SLC0_RXLINK_START_S  29
+/* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_STOP  (BIT(28))
+#define SLC_SLC0_RXLINK_STOP_M  (BIT(28))
+#define SLC_SLC0_RXLINK_STOP_V  0x1
+#define SLC_SLC0_RXLINK_STOP_S  28
+/* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_ADDR  0x000FFFFF
+#define SLC_SLC0_RXLINK_ADDR_M  ((SLC_SLC0_RXLINK_ADDR_V)<<(SLC_SLC0_RXLINK_ADDR_S))
+#define SLC_SLC0_RXLINK_ADDR_V  0xFFFFF
+#define SLC_SLC0_RXLINK_ADDR_S  0
+
+#define SLC_0TX_LINK_REG          (DR_REG_SLC_BASE + 0x40)
+/* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_PARK  (BIT(31))
+#define SLC_SLC0_TXLINK_PARK_M  (BIT(31))
+#define SLC_SLC0_TXLINK_PARK_V  0x1
+#define SLC_SLC0_TXLINK_PARK_S  31
+/* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_RESTART  (BIT(30))
+#define SLC_SLC0_TXLINK_RESTART_M  (BIT(30))
+#define SLC_SLC0_TXLINK_RESTART_V  0x1
+#define SLC_SLC0_TXLINK_RESTART_S  30
+/* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_START  (BIT(29))
+#define SLC_SLC0_TXLINK_START_M  (BIT(29))
+#define SLC_SLC0_TXLINK_START_V  0x1
+#define SLC_SLC0_TXLINK_START_S  29
+/* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_STOP  (BIT(28))
+#define SLC_SLC0_TXLINK_STOP_M  (BIT(28))
+#define SLC_SLC0_TXLINK_STOP_V  0x1
+#define SLC_SLC0_TXLINK_STOP_S  28
+/* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_ADDR  0x000FFFFF
+#define SLC_SLC0_TXLINK_ADDR_M  ((SLC_SLC0_TXLINK_ADDR_V)<<(SLC_SLC0_TXLINK_ADDR_S))
+#define SLC_SLC0_TXLINK_ADDR_V  0xFFFFF
+#define SLC_SLC0_TXLINK_ADDR_S  0
+
+#define SLC_INTVEC_TOHOST_REG          (DR_REG_SLC_BASE + 0x4C)
+/* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INTVEC  0x000000FF
+#define SLC_SLC0_TOHOST_INTVEC_M  ((SLC_SLC0_TOHOST_INTVEC_V)<<(SLC_SLC0_TOHOST_INTVEC_S))
+#define SLC_SLC0_TOHOST_INTVEC_V  0xFF
+#define SLC_SLC0_TOHOST_INTVEC_S  0
+
+#define SLC_0TOKEN0_REG          (DR_REG_SLC_BASE + 0x50)
+/* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0  0x00000FFF
+#define SLC_SLC0_TOKEN0_M  ((SLC_SLC0_TOKEN0_V)<<(SLC_SLC0_TOKEN0_S))
+#define SLC_SLC0_TOKEN0_V  0xFFF
+#define SLC_SLC0_TOKEN0_S  16
+/* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_INC_MORE  (BIT(14))
+#define SLC_SLC0_TOKEN0_INC_MORE_M  (BIT(14))
+#define SLC_SLC0_TOKEN0_INC_MORE_V  0x1
+#define SLC_SLC0_TOKEN0_INC_MORE_S  14
+/* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_INC  (BIT(13))
+#define SLC_SLC0_TOKEN0_INC_M  (BIT(13))
+#define SLC_SLC0_TOKEN0_INC_V  0x1
+#define SLC_SLC0_TOKEN0_INC_S  13
+/* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_WR  (BIT(12))
+#define SLC_SLC0_TOKEN0_WR_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_WR_V  0x1
+#define SLC_SLC0_TOKEN0_WR_S  12
+/* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_WDATA  0x00000FFF
+#define SLC_SLC0_TOKEN0_WDATA_M  ((SLC_SLC0_TOKEN0_WDATA_V)<<(SLC_SLC0_TOKEN0_WDATA_S))
+#define SLC_SLC0_TOKEN0_WDATA_V  0xFFF
+#define SLC_SLC0_TOKEN0_WDATA_S  0
+
+#define SLC_0TOKEN1_REG          (DR_REG_SLC_BASE + 0x54)
+/* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1  0x00000FFF
+#define SLC_SLC0_TOKEN1_M  ((SLC_SLC0_TOKEN1_V)<<(SLC_SLC0_TOKEN1_S))
+#define SLC_SLC0_TOKEN1_V  0xFFF
+#define SLC_SLC0_TOKEN1_S  16
+/* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_INC_MORE  (BIT(14))
+#define SLC_SLC0_TOKEN1_INC_MORE_M  (BIT(14))
+#define SLC_SLC0_TOKEN1_INC_MORE_V  0x1
+#define SLC_SLC0_TOKEN1_INC_MORE_S  14
+/* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_INC  (BIT(13))
+#define SLC_SLC0_TOKEN1_INC_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_INC_V  0x1
+#define SLC_SLC0_TOKEN1_INC_S  13
+/* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_WR  (BIT(12))
+#define SLC_SLC0_TOKEN1_WR_M  (BIT(12))
+#define SLC_SLC0_TOKEN1_WR_V  0x1
+#define SLC_SLC0_TOKEN1_WR_S  12
+/* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_WDATA  0x00000FFF
+#define SLC_SLC0_TOKEN1_WDATA_M  ((SLC_SLC0_TOKEN1_WDATA_V)<<(SLC_SLC0_TOKEN1_WDATA_S))
+#define SLC_SLC0_TOKEN1_WDATA_V  0xFFF
+#define SLC_SLC0_TOKEN1_WDATA_S  0
+
+#define SLC_CONF1_REG          (DR_REG_SLC_BASE + 0x60)
+/* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CLK_EN  (BIT(22))
+#define SLC_CLK_EN_M  (BIT(22))
+#define SLC_CLK_EN_V  0x1
+#define SLC_CLK_EN_S  22
+/* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_HOST_INT_LEVEL_SEL  (BIT(19))
+#define SLC_HOST_INT_LEVEL_SEL_M  (BIT(19))
+#define SLC_HOST_INT_LEVEL_SEL_V  0x1
+#define SLC_HOST_INT_LEVEL_SEL_S  19
+/* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_STITCH_EN  (BIT(6))
+#define SLC_SLC0_RX_STITCH_EN_M  (BIT(6))
+#define SLC_SLC0_RX_STITCH_EN_V  0x1
+#define SLC_SLC0_RX_STITCH_EN_S  6
+/* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_TX_STITCH_EN  (BIT(5))
+#define SLC_SLC0_TX_STITCH_EN_M  (BIT(5))
+#define SLC_SLC0_TX_STITCH_EN_V  0x1
+#define SLC_SLC0_TX_STITCH_EN_S  5
+/* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_LEN_AUTO_CLR  (BIT(4))
+#define SLC_SLC0_LEN_AUTO_CLR_M  (BIT(4))
+#define SLC_SLC0_LEN_AUTO_CLR_V  0x1
+#define SLC_SLC0_LEN_AUTO_CLR_S  4
+/* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SLC_CMD_HOLD_EN  (BIT(3))
+#define SLC_CMD_HOLD_EN_M  (BIT(3))
+#define SLC_CMD_HOLD_EN_V  0x1
+#define SLC_CMD_HOLD_EN_S  3
+/* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_CHECK_SUM_EN  (BIT(2))
+#define SLC_SLC0_RX_CHECK_SUM_EN_M  (BIT(2))
+#define SLC_SLC0_RX_CHECK_SUM_EN_V  0x1
+#define SLC_SLC0_RX_CHECK_SUM_EN_S  2
+/* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_CHECK_SUM_EN  (BIT(1))
+#define SLC_SLC0_TX_CHECK_SUM_EN_M  (BIT(1))
+#define SLC_SLC0_TX_CHECK_SUM_EN_V  0x1
+#define SLC_SLC0_TX_CHECK_SUM_EN_S  1
+/* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_CHECK_OWNER  (BIT(0))
+#define SLC_SLC0_CHECK_OWNER_M  (BIT(0))
+#define SLC_SLC0_CHECK_OWNER_V  0x1
+#define SLC_SLC0_CHECK_OWNER_S  0
+
+#define SLC_0_STATE0_REG          (DR_REG_SLC_BASE + 0x64)
+/* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_STATE0  0xFFFFFFFF
+#define SLC_SLC0_STATE0_M  ((SLC_SLC0_STATE0_V)<<(SLC_SLC0_STATE0_S))
+#define SLC_SLC0_STATE0_V  0xFFFFFFFF
+#define SLC_SLC0_STATE0_S  0
+
+#define SLC_0_STATE1_REG          (DR_REG_SLC_BASE + 0x68)
+/* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_STATE1  0xFFFFFFFF
+#define SLC_SLC0_STATE1_M  ((SLC_SLC0_STATE1_V)<<(SLC_SLC0_STATE1_S))
+#define SLC_SLC0_STATE1_V  0xFFFFFFFF
+#define SLC_SLC0_STATE1_S  0
+
+#define SLC_BRIDGE_CONF_REG          (DR_REG_SLC_BASE + 0x74)
+/* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */
+/*description: */
+#define SLC_TX_PUSH_IDLE_NUM  0x0000FFFF
+#define SLC_TX_PUSH_IDLE_NUM_M  ((SLC_TX_PUSH_IDLE_NUM_V)<<(SLC_TX_PUSH_IDLE_NUM_S))
+#define SLC_TX_PUSH_IDLE_NUM_V  0xFFFF
+#define SLC_TX_PUSH_IDLE_NUM_S  16
+/* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */
+/*description: */
+#define SLC_HDA_MAP_128K  (BIT(13))
+#define SLC_HDA_MAP_128K_M  (BIT(13))
+#define SLC_HDA_MAP_128K_V  0x1
+#define SLC_HDA_MAP_128K_S  13
+/* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */
+/*description: */
+#define SLC_SLC0_TX_DUMMY_MODE  (BIT(12))
+#define SLC_SLC0_TX_DUMMY_MODE_M  (BIT(12))
+#define SLC_SLC0_TX_DUMMY_MODE_V  0x1
+#define SLC_SLC0_TX_DUMMY_MODE_S  12
+/* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */
+/*description: */
+#define SLC_FIFO_MAP_ENA  0x0000000F
+#define SLC_FIFO_MAP_ENA_M  ((SLC_FIFO_MAP_ENA_V)<<(SLC_FIFO_MAP_ENA_S))
+#define SLC_FIFO_MAP_ENA_V  0xF
+#define SLC_FIFO_MAP_ENA_S  8
+/* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */
+/*description: */
+#define SLC_TXEOF_ENA  0x0000003F
+#define SLC_TXEOF_ENA_M  ((SLC_TXEOF_ENA_V)<<(SLC_TXEOF_ENA_S))
+#define SLC_TXEOF_ENA_V  0x3F
+#define SLC_TXEOF_ENA_S  0
+
+#define SLC_0_TO_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x78)
+/* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TO_EOF_DES_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_DES_ADDR_M  ((SLC_SLC0_TO_EOF_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_DES_ADDR_S))
+#define SLC_SLC0_TO_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_DES_ADDR_S  0
+
+#define SLC_0_TX_EOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x7C)
+/* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M  ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_SUC_EOF_DES_ADDR_S))
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S  0
+
+#define SLC_0_TO_EOF_BFR_DES_ADDR_REG          (DR_REG_SLC_BASE + 0x80)
+/* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M  ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V)<<(SLC_SLC0_TO_EOF_BFR_DES_ADDR_S))
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S  0
+
+#define SLC_AHB_TEST_REG          (DR_REG_SLC_BASE + 0x90)
+/* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define SLC_AHB_TESTADDR  0x00000003
+#define SLC_AHB_TESTADDR_M  ((SLC_AHB_TESTADDR_V)<<(SLC_AHB_TESTADDR_S))
+#define SLC_AHB_TESTADDR_V  0x3
+#define SLC_AHB_TESTADDR_S  4
+/* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define SLC_AHB_TESTMODE  0x00000007
+#define SLC_AHB_TESTMODE_M  ((SLC_AHB_TESTMODE_V)<<(SLC_AHB_TESTMODE_S))
+#define SLC_AHB_TESTMODE_V  0x7
+#define SLC_AHB_TESTMODE_S  0
+
+#define SLC_SDIO_ST_REG          (DR_REG_SLC_BASE + 0x94)
+/* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */
+/*description: */
+#define SLC_FUNC1_ACC_STATE  0x0000001F
+#define SLC_FUNC1_ACC_STATE_M  ((SLC_FUNC1_ACC_STATE_V)<<(SLC_FUNC1_ACC_STATE_S))
+#define SLC_FUNC1_ACC_STATE_V  0x1F
+#define SLC_FUNC1_ACC_STATE_S  16
+/* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */
+/*description: */
+#define SLC_BUS_ST  0x00000007
+#define SLC_BUS_ST_M  ((SLC_BUS_ST_V)<<(SLC_BUS_ST_S))
+#define SLC_BUS_ST_V  0x7
+#define SLC_BUS_ST_S  12
+/* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SDIO_WAKEUP  (BIT(8))
+#define SLC_SDIO_WAKEUP_M  (BIT(8))
+#define SLC_SDIO_WAKEUP_V  0x1
+#define SLC_SDIO_WAKEUP_S  8
+/* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: */
+#define SLC_FUNC_ST  0x0000000F
+#define SLC_FUNC_ST_M  ((SLC_FUNC_ST_V)<<(SLC_FUNC_ST_S))
+#define SLC_FUNC_ST_V  0xF
+#define SLC_FUNC_ST_S  4
+#define SLC_FUNC_ST_IDLE 2
+/* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define SLC_CMD_ST  0x00000007
+#define SLC_CMD_ST_M  ((SLC_CMD_ST_V)<<(SLC_CMD_ST_S))
+#define SLC_CMD_ST_V  0x7
+#define SLC_CMD_ST_S  0
+#define SLC_CMD_ST_IDLE 1
+
+#define SLC_RX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0x98)
+/* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */
+/*description: */
+#define SLC_SLC0_RD_RETRY_THRESHOLD  0x000007FF
+#define SLC_SLC0_RD_RETRY_THRESHOLD_M  ((SLC_SLC0_RD_RETRY_THRESHOLD_V)<<(SLC_SLC0_RD_RETRY_THRESHOLD_S))
+#define SLC_SLC0_RD_RETRY_THRESHOLD_V  0x7FF
+#define SLC_SLC0_RD_RETRY_THRESHOLD_S  5
+/* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_FILL_EN  (BIT(4))
+#define SLC_SLC0_RX_FILL_EN_M  (BIT(4))
+#define SLC_SLC0_RX_FILL_EN_V  0x1
+#define SLC_SLC0_RX_FILL_EN_S  4
+/* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_MODE  (BIT(3))
+#define SLC_SLC0_RX_EOF_MODE_M  (BIT(3))
+#define SLC_SLC0_RX_EOF_MODE_V  0x1
+#define SLC_SLC0_RX_EOF_MODE_S  3
+/* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_FILL_MODE  (BIT(2))
+#define SLC_SLC0_RX_FILL_MODE_M  (BIT(2))
+#define SLC_SLC0_RX_FILL_MODE_V  0x1
+#define SLC_SLC0_RX_FILL_MODE_S  2
+/* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SLC_SLC0_INFOR_NO_REPLACE  (BIT(1))
+#define SLC_SLC0_INFOR_NO_REPLACE_M  (BIT(1))
+#define SLC_SLC0_INFOR_NO_REPLACE_V  0x1
+#define SLC_SLC0_INFOR_NO_REPLACE_S  1
+/* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN_NO_REPLACE  (BIT(0))
+#define SLC_SLC0_TOKEN_NO_REPLACE_M  (BIT(0))
+#define SLC_SLC0_TOKEN_NO_REPLACE_V  0x1
+#define SLC_SLC0_TOKEN_NO_REPLACE_S  0
+
+#define SLC_0_TXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0x9C)
+/* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_DSCR  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_M  ((SLC_SLC0_TXLINK_DSCR_V)<<(SLC_SLC0_TXLINK_DSCR_S))
+#define SLC_SLC0_TXLINK_DSCR_V  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_S  0
+
+#define SLC_0_TXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xA0)
+/* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_DSCR_BF0  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF0_M  ((SLC_SLC0_TXLINK_DSCR_BF0_V)<<(SLC_SLC0_TXLINK_DSCR_BF0_S))
+#define SLC_SLC0_TXLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF0_S  0
+
+#define SLC_0_TXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xA4)
+/* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_TXLINK_DSCR_BF1  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF1_M  ((SLC_SLC0_TXLINK_DSCR_BF1_V)<<(SLC_SLC0_TXLINK_DSCR_BF1_S))
+#define SLC_SLC0_TXLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SLC_SLC0_TXLINK_DSCR_BF1_S  0
+
+#define SLC_0_RXLINK_DSCR_REG          (DR_REG_SLC_BASE + 0xA8)
+/* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_DSCR  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_M  ((SLC_SLC0_RXLINK_DSCR_V)<<(SLC_SLC0_RXLINK_DSCR_S))
+#define SLC_SLC0_RXLINK_DSCR_V  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_S  0
+
+#define SLC_0_RXLINK_DSCR_BF0_REG          (DR_REG_SLC_BASE + 0xAC)
+/* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_DSCR_BF0  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF0_M  ((SLC_SLC0_RXLINK_DSCR_BF0_V)<<(SLC_SLC0_RXLINK_DSCR_BF0_S))
+#define SLC_SLC0_RXLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF0_S  0
+
+#define SLC_0_RXLINK_DSCR_BF1_REG          (DR_REG_SLC_BASE + 0xB0)
+/* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RXLINK_DSCR_BF1  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF1_M  ((SLC_SLC0_RXLINK_DSCR_BF1_V)<<(SLC_SLC0_RXLINK_DSCR_BF1_S))
+#define SLC_SLC0_RXLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SLC_SLC0_RXLINK_DSCR_BF1_S  0
+
+#define SLC_0_TX_ERREOF_DES_ADDR_REG          (DR_REG_SLC_BASE + 0xCC)
+/* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M  ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V)<<(SLC_SLC0_TX_ERR_EOF_DES_ADDR_S))
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S  0
+
+#define SLC_TOKEN_LAT_REG          (DR_REG_SLC_BASE + 0xD4)
+/* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN  0x00000FFF
+#define SLC_SLC0_TOKEN_M  ((SLC_SLC0_TOKEN_V)<<(SLC_SLC0_TOKEN_S))
+#define SLC_SLC0_TOKEN_V  0xFFF
+#define SLC_SLC0_TOKEN_S  0
+
+#define SLC_TX_DSCR_CONF_REG          (DR_REG_SLC_BASE + 0xD8)
+/* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */
+/*description: */
+#define SLC_WR_RETRY_THRESHOLD  0x000007FF
+#define SLC_WR_RETRY_THRESHOLD_M  ((SLC_WR_RETRY_THRESHOLD_V)<<(SLC_WR_RETRY_THRESHOLD_S))
+#define SLC_WR_RETRY_THRESHOLD_V  0x7FF
+#define SLC_WR_RETRY_THRESHOLD_S  0
+
+#define SLC_CMD_INFOR0_REG          (DR_REG_SLC_BASE + 0xDC)
+/* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_CMD_CONTENT0  0xFFFFFFFF
+#define SLC_CMD_CONTENT0_M  ((SLC_CMD_CONTENT0_V)<<(SLC_CMD_CONTENT0_S))
+#define SLC_CMD_CONTENT0_V  0xFFFFFFFF
+#define SLC_CMD_CONTENT0_S  0
+
+#define SLC_CMD_INFOR1_REG          (DR_REG_SLC_BASE + 0xE0)
+/* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_CMD_CONTENT1  0xFFFFFFFF
+#define SLC_CMD_CONTENT1_M  ((SLC_CMD_CONTENT1_V)<<(SLC_CMD_CONTENT1_S))
+#define SLC_CMD_CONTENT1_V  0xFFFFFFFF
+#define SLC_CMD_CONTENT1_S  0
+
+#define SLC_0_LEN_CONF_REG          (DR_REG_SLC_BASE + 0xE4)
+/* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_NEW_PKT_IND  (BIT(28))
+#define SLC_SLC0_TX_NEW_PKT_IND_M  (BIT(28))
+#define SLC_SLC0_TX_NEW_PKT_IND_V  0x1
+#define SLC_SLC0_TX_NEW_PKT_IND_S  28
+/* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_NEW_PKT_IND  (BIT(27))
+#define SLC_SLC0_RX_NEW_PKT_IND_M  (BIT(27))
+#define SLC_SLC0_RX_NEW_PKT_IND_V  0x1
+#define SLC_SLC0_RX_NEW_PKT_IND_S  27
+/* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_GET_USED_DSCR  (BIT(26))
+#define SLC_SLC0_TX_GET_USED_DSCR_M  (BIT(26))
+#define SLC_SLC0_TX_GET_USED_DSCR_V  0x1
+#define SLC_SLC0_TX_GET_USED_DSCR_S  26
+/* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_GET_USED_DSCR  (BIT(25))
+#define SLC_SLC0_RX_GET_USED_DSCR_M  (BIT(25))
+#define SLC_SLC0_RX_GET_USED_DSCR_V  0x1
+#define SLC_SLC0_RX_GET_USED_DSCR_S  25
+/* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_PACKET_LOAD_EN  (BIT(24))
+#define SLC_SLC0_TX_PACKET_LOAD_EN_M  (BIT(24))
+#define SLC_SLC0_TX_PACKET_LOAD_EN_V  0x1
+#define SLC_SLC0_TX_PACKET_LOAD_EN_S  24
+/* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_PACKET_LOAD_EN  (BIT(23))
+#define SLC_SLC0_RX_PACKET_LOAD_EN_M  (BIT(23))
+#define SLC_SLC0_RX_PACKET_LOAD_EN_V  0x1
+#define SLC_SLC0_RX_PACKET_LOAD_EN_S  23
+/* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_LEN_INC_MORE  (BIT(22))
+#define SLC_SLC0_LEN_INC_MORE_M  (BIT(22))
+#define SLC_SLC0_LEN_INC_MORE_V  0x1
+#define SLC_SLC0_LEN_INC_MORE_S  22
+/* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_LEN_INC  (BIT(21))
+#define SLC_SLC0_LEN_INC_M  (BIT(21))
+#define SLC_SLC0_LEN_INC_V  0x1
+#define SLC_SLC0_LEN_INC_S  21
+/* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_LEN_WR  (BIT(20))
+#define SLC_SLC0_LEN_WR_M  (BIT(20))
+#define SLC_SLC0_LEN_WR_V  0x1
+#define SLC_SLC0_LEN_WR_S  20
+/* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_LEN_WDATA  0x000FFFFF
+#define SLC_SLC0_LEN_WDATA_M  ((SLC_SLC0_LEN_WDATA_V)<<(SLC_SLC0_LEN_WDATA_S))
+#define SLC_SLC0_LEN_WDATA_V  0xFFFFF
+#define SLC_SLC0_LEN_WDATA_S  0
+
+#define SLC_0_LENGTH_REG          (DR_REG_SLC_BASE + 0xE8)
+/* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define SLC_SLC0_LEN  0x000FFFFF
+#define SLC_SLC0_LEN_M  ((SLC_SLC0_LEN_V)<<(SLC_SLC0_LEN_S))
+#define SLC_SLC0_LEN_V  0xFFFFF
+#define SLC_SLC0_LEN_S  0
+
+#define SLC_0_TXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xEC)
+/* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_H_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S  0
+
+#define SLC_0_TXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF0)
+/* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_E_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S  0
+
+#define SLC_0_RXPKT_H_DSCR_REG          (DR_REG_SLC_BASE + 0xF4)
+/* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_H_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S  0
+
+#define SLC_0_RXPKT_E_DSCR_REG          (DR_REG_SLC_BASE + 0xF8)
+/* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_E_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S  0
+
+#define SLC_0_TXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0xFC)
+/* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_START_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S  0
+
+#define SLC_0_TXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x100)
+/* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_TX_PKT_END_DSCR_ADDR_S))
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S  0
+
+#define SLC_0_RXPKTU_H_DSCR_REG          (DR_REG_SLC_BASE + 0x104)
+/* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_START_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S  0
+
+#define SLC_0_RXPKTU_E_DSCR_REG          (DR_REG_SLC_BASE + 0x108)
+/* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M  ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V)<<(SLC_SLC0_RX_PKT_END_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S  0
+
+#define SLC_SEQ_POSITION_REG          (DR_REG_SLC_BASE + 0x114)
+/* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */
+/*description: */
+#define SLC_SLC0_SEQ_POSITION  0x000000FF
+#define SLC_SLC0_SEQ_POSITION_M  ((SLC_SLC0_SEQ_POSITION_V)<<(SLC_SLC0_SEQ_POSITION_S))
+#define SLC_SLC0_SEQ_POSITION_V  0xFF
+#define SLC_SLC0_SEQ_POSITION_S  0
+
+#define SLC_0_DSCR_REC_CONF_REG          (DR_REG_SLC_BASE + 0x118)
+/* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_REC_LIM  0x000003FF
+#define SLC_SLC0_RX_DSCR_REC_LIM_M  ((SLC_SLC0_RX_DSCR_REC_LIM_V)<<(SLC_SLC0_RX_DSCR_REC_LIM_S))
+#define SLC_SLC0_RX_DSCR_REC_LIM_V  0x3FF
+#define SLC_SLC0_RX_DSCR_REC_LIM_S  0
+
+#define SLC_SDIO_CRC_ST0_REG          (DR_REG_SLC_BASE + 0x11C)
+/* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT3_CRC_ERR_CNT  0x000000FF
+#define SLC_DAT3_CRC_ERR_CNT_M  ((SLC_DAT3_CRC_ERR_CNT_V)<<(SLC_DAT3_CRC_ERR_CNT_S))
+#define SLC_DAT3_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT3_CRC_ERR_CNT_S  24
+/* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT2_CRC_ERR_CNT  0x000000FF
+#define SLC_DAT2_CRC_ERR_CNT_M  ((SLC_DAT2_CRC_ERR_CNT_V)<<(SLC_DAT2_CRC_ERR_CNT_S))
+#define SLC_DAT2_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT2_CRC_ERR_CNT_S  16
+/* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT1_CRC_ERR_CNT  0x000000FF
+#define SLC_DAT1_CRC_ERR_CNT_M  ((SLC_DAT1_CRC_ERR_CNT_V)<<(SLC_DAT1_CRC_ERR_CNT_S))
+#define SLC_DAT1_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT1_CRC_ERR_CNT_S  8
+/* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SLC_DAT0_CRC_ERR_CNT  0x000000FF
+#define SLC_DAT0_CRC_ERR_CNT_M  ((SLC_DAT0_CRC_ERR_CNT_V)<<(SLC_DAT0_CRC_ERR_CNT_S))
+#define SLC_DAT0_CRC_ERR_CNT_V  0xFF
+#define SLC_DAT0_CRC_ERR_CNT_S  0
+
+#define SLC_SDIO_CRC_ST1_REG          (DR_REG_SLC_BASE + 0x120)
+/* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SLC_ERR_CNT_CLR  (BIT(31))
+#define SLC_ERR_CNT_CLR_M  (BIT(31))
+#define SLC_ERR_CNT_CLR_V  0x1
+#define SLC_ERR_CNT_CLR_S  31
+/* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SLC_CMD_CRC_ERR_CNT  0x000000FF
+#define SLC_CMD_CRC_ERR_CNT_M  ((SLC_CMD_CRC_ERR_CNT_V)<<(SLC_CMD_CRC_ERR_CNT_S))
+#define SLC_CMD_CRC_ERR_CNT_V  0xFF
+#define SLC_CMD_CRC_ERR_CNT_S  0
+
+#define SLC_0_EOF_START_DES_REG          (DR_REG_SLC_BASE + 0x124)
+/* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_EOF_START_DES_ADDR  0xFFFFFFFF
+#define SLC_SLC0_EOF_START_DES_ADDR_M  ((SLC_SLC0_EOF_START_DES_ADDR_V)<<(SLC_SLC0_EOF_START_DES_ADDR_S))
+#define SLC_SLC0_EOF_START_DES_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_EOF_START_DES_ADDR_S  0
+
+#define SLC_0_PUSH_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x128)
+/* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M  ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V)<<(SLC_SLC0_RX_PUSH_DSCR_ADDR_S))
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S  0
+
+#define SLC_0_DONE_DSCR_ADDR_REG          (DR_REG_SLC_BASE + 0x12C)
+/* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_M  ((SLC_SLC0_RX_DONE_DSCR_ADDR_V)<<(SLC_SLC0_RX_DONE_DSCR_ADDR_S))
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_RX_DONE_DSCR_ADDR_S  0
+
+#define SLC_0_SUB_START_DES_REG          (DR_REG_SLC_BASE + 0x130)
+/* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR  0xFFFFFFFF
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M  ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V)<<(SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S))
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V  0xFFFFFFFF
+#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S  0
+
+#define SLC_0_DSCR_CNT_REG          (DR_REG_SLC_BASE + 0x134)
+/* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_GET_EOF_OCC  (BIT(16))
+#define SLC_SLC0_RX_GET_EOF_OCC_M  (BIT(16))
+#define SLC_SLC0_RX_GET_EOF_OCC_V  0x1
+#define SLC_SLC0_RX_GET_EOF_OCC_S  16
+/* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_CNT_LAT  0x000003FF
+#define SLC_SLC0_RX_DSCR_CNT_LAT_M  ((SLC_SLC0_RX_DSCR_CNT_LAT_V)<<(SLC_SLC0_RX_DSCR_CNT_LAT_S))
+#define SLC_SLC0_RX_DSCR_CNT_LAT_V  0x3FF
+#define SLC_SLC0_RX_DSCR_CNT_LAT_S  0
+
+#define SLC_0_LEN_LIM_CONF_REG          (DR_REG_SLC_BASE + 0x138)
+/* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */
+/*description: */
+#define SLC_SLC0_LEN_LIM  0x000FFFFF
+#define SLC_SLC0_LEN_LIM_M  ((SLC_SLC0_LEN_LIM_V)<<(SLC_SLC0_LEN_LIM_S))
+#define SLC_SLC0_LEN_LIM_V  0xFFFFF
+#define SLC_SLC0_LEN_LIM_S  0
+
+#define SLC_0INT_ST1_REG          (DR_REG_SLC_BASE + 0x13C)
+/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_S  27
+/* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S  26
+/* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ST1  (BIT(25))
+#define SLC_CMD_DTC_INT_ST1_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ST1_V  0x1
+#define SLC_CMD_DTC_INT_ST1_S  25
+/* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S  24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S  23
+/* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S  22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S  21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S  20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S  19
+/* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ST1  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST1_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ST1_V  0x1
+#define SLC_SLC0_TOHOST_INT_ST1_S  18
+/* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ST1  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST1_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ST1_S  17
+/* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ST1  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST1_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ST1_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ST1_S  16
+/* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S  15
+/* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ST1  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST1_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ST1_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ST1_S  14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S  13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S  12
+/* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ST1  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST1_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ST1_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ST1_S  11
+/* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ST1  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST1_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ST1_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ST1_S  10
+/* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ST1  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST1_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ST1_V  0x1
+#define SLC_SLC0_TX_START_INT_ST1_S  9
+/* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ST1  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST1_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ST1_V  0x1
+#define SLC_SLC0_RX_START_INT_ST1_S  8
+/* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ST1  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST1_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT7_INT_ST1_S  7
+/* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ST1  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST1_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT6_INT_ST1_S  6
+/* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ST1  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST1_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT5_INT_ST1_S  5
+/* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ST1  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST1_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT4_INT_ST1_S  4
+/* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ST1  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST1_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT3_INT_ST1_S  3
+/* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ST1  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST1_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT2_INT_ST1_S  2
+/* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ST1  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST1_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT1_INT_ST1_S  1
+/* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ST1  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST1_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ST1_V  0x1
+#define SLC_FRHOST_BIT0_INT_ST1_S  0
+
+#define SLC_0INT_ENA1_REG          (DR_REG_SLC_BASE + 0x140)
+/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M  (BIT(27))
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V  0x1
+#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S  27
+/* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M  (BIT(26))
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S  26
+/* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define SLC_CMD_DTC_INT_ENA1  (BIT(25))
+#define SLC_CMD_DTC_INT_ENA1_M  (BIT(25))
+#define SLC_CMD_DTC_INT_ENA1_V  0x1
+#define SLC_CMD_DTC_INT_ENA1_S  25
+/* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M  (BIT(24))
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S  24
+/* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M  (BIT(23))
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V  0x1
+#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S  23
+/* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M  (BIT(22))
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V  0x1
+#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S  22
+/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M  (BIT(21))
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S  21
+/* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M  (BIT(20))
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S  20
+/* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M  (BIT(19))
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S  19
+/* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOHOST_INT_ENA1  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA1_M  (BIT(18))
+#define SLC_SLC0_TOHOST_INT_ENA1_V  0x1
+#define SLC_SLC0_TOHOST_INT_ENA1_S  18
+/* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_EOF_INT_ENA1  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA1_M  (BIT(17))
+#define SLC_SLC0_RX_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_EOF_INT_ENA1_S  17
+/* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_DONE_INT_ENA1  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA1_M  (BIT(16))
+#define SLC_SLC0_RX_DONE_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_DONE_INT_ENA1_S  16
+/* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M  (BIT(15))
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S  15
+/* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_DONE_INT_ENA1  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA1_M  (BIT(14))
+#define SLC_SLC0_TX_DONE_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_DONE_INT_ENA1_S  14
+/* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M  (BIT(13))
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V  0x1
+#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S  13
+/* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M  (BIT(12))
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V  0x1
+#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S  12
+/* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_OVF_INT_ENA1  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA1_M  (BIT(11))
+#define SLC_SLC0_TX_OVF_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_OVF_INT_ENA1_S  11
+/* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_UDF_INT_ENA1  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA1_M  (BIT(10))
+#define SLC_SLC0_RX_UDF_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_UDF_INT_ENA1_S  10
+/* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_TX_START_INT_ENA1  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA1_M  (BIT(9))
+#define SLC_SLC0_TX_START_INT_ENA1_V  0x1
+#define SLC_SLC0_TX_START_INT_ENA1_S  9
+/* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SLC_SLC0_RX_START_INT_ENA1  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA1_M  (BIT(8))
+#define SLC_SLC0_RX_START_INT_ENA1_V  0x1
+#define SLC_SLC0_RX_START_INT_ENA1_S  8
+/* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT7_INT_ENA1  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA1_M  (BIT(7))
+#define SLC_FRHOST_BIT7_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT7_INT_ENA1_S  7
+/* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT6_INT_ENA1  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA1_M  (BIT(6))
+#define SLC_FRHOST_BIT6_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT6_INT_ENA1_S  6
+/* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT5_INT_ENA1  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA1_M  (BIT(5))
+#define SLC_FRHOST_BIT5_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT5_INT_ENA1_S  5
+/* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT4_INT_ENA1  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA1_M  (BIT(4))
+#define SLC_FRHOST_BIT4_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT4_INT_ENA1_S  4
+/* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT3_INT_ENA1  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA1_M  (BIT(3))
+#define SLC_FRHOST_BIT3_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT3_INT_ENA1_S  3
+/* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT2_INT_ENA1  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA1_M  (BIT(2))
+#define SLC_FRHOST_BIT2_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT2_INT_ENA1_S  2
+/* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT1_INT_ENA1  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA1_M  (BIT(1))
+#define SLC_FRHOST_BIT1_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT1_INT_ENA1_S  1
+/* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SLC_FRHOST_BIT0_INT_ENA1  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA1_M  (BIT(0))
+#define SLC_FRHOST_BIT0_INT_ENA1_V  0x1
+#define SLC_FRHOST_BIT0_INT_ENA1_S  0
+
+#define SLC_DATE_REG          (DR_REG_SLC_BASE + 0x1F8)
+/* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */
+/*description: */
+#define SLC_DATE  0xFFFFFFFF
+#define SLC_DATE_M  ((SLC_DATE_V)<<(SLC_DATE_S))
+#define SLC_DATE_V  0xFFFFFFFF
+#define SLC_DATE_S  0
+
+#define SLC_ID_REG          (DR_REG_SLC_BASE + 0x1FC)
+/* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */
+/*description: */
+#define SLC_ID  0xFFFFFFFF
+#define SLC_ID_M  ((SLC_ID_V)<<(SLC_ID_S))
+#define SLC_ID_V  0xFFFFFFFF
+#define SLC_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SLC_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/slc_struct.h b/components/soc/esp32s2beta/include/soc/slc_struct.h
new file mode 100644
index 000000000..74cb22c37
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/slc_struct.h
@@ -0,0 +1,588 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SLC_STRUCT_H_
+#define _SOC_SLC_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t slc0_tx_rst:            1;
+            uint32_t slc0_rx_rst:            1;
+            uint32_t ahbm_fifo_rst:          1;
+            uint32_t ahbm_rst:               1;
+            uint32_t slc0_tx_loop_test:      1;
+            uint32_t slc0_rx_loop_test:      1;
+            uint32_t slc0_rx_auto_wrback:    1;
+            uint32_t slc0_rx_no_restart_clr: 1;
+            uint32_t slc0_rxdscr_burst_en:   1;
+            uint32_t slc0_rxdata_burst_en:   1;
+            uint32_t slc0_rxlink_auto_ret:   1;
+            uint32_t slc0_txlink_auto_ret:   1;
+            uint32_t slc0_txdscr_burst_en:   1;
+            uint32_t slc0_txdata_burst_en:   1;
+            uint32_t slc0_token_auto_clr:    1;
+            uint32_t slc0_token_sel:         1;
+            uint32_t reserved16:             2;
+            uint32_t slc0_wr_retry_mask_en:  1;
+            uint32_t reserved19:            13;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t frhost_bit0:                   1;
+            uint32_t frhost_bit1:                   1;
+            uint32_t frhost_bit2:                   1;
+            uint32_t frhost_bit3:                   1;
+            uint32_t frhost_bit4:                   1;
+            uint32_t frhost_bit5:                   1;
+            uint32_t frhost_bit6:                   1;
+            uint32_t frhost_bit7:                   1;
+            uint32_t rx_start:                      1;
+            uint32_t tx_start:                      1;
+            uint32_t rx_udf:                        1;
+            uint32_t tx_ovf:                        1;
+            uint32_t token0_1to0:                   1;
+            uint32_t token1_1to0:                   1;
+            uint32_t tx_done:                       1;
+            uint32_t tx_suc_eof:                    1;
+            uint32_t rx_done:                       1;
+            uint32_t rx_eof:                        1;
+            uint32_t tohost:                        1;
+            uint32_t tx_dscr_err:                   1;
+            uint32_t rx_dscr_err:                   1;
+            uint32_t tx_dscr_empty:                 1;
+            uint32_t host_rd_ack:                   1;
+            uint32_t wr_retry_done:                 1;
+            uint32_t tx_err_eof:                    1;
+            uint32_t cmd_dtc:                       1;
+            uint32_t rx_quick_eof:                  1;
+            uint32_t host_pop_eof_err:              1;
+            uint32_t reserved28:                    4;
+        };
+        uint32_t val;
+    } slc0_int_raw;
+    union {
+        struct {
+            uint32_t frhost_bit0:                  1;
+            uint32_t frhost_bit1:                  1;
+            uint32_t frhost_bit2:                  1;
+            uint32_t frhost_bit3:                  1;
+            uint32_t frhost_bit4:                  1;
+            uint32_t frhost_bit5:                  1;
+            uint32_t frhost_bit6:                  1;
+            uint32_t frhost_bit7:                  1;
+            uint32_t rx_start:                     1;
+            uint32_t tx_start:                     1;
+            uint32_t rx_udf:                       1;
+            uint32_t tx_ovf:                       1;
+            uint32_t token0_1to0:                  1;
+            uint32_t token1_1to0:                  1;
+            uint32_t tx_done:                      1;
+            uint32_t tx_suc_eof:                   1;
+            uint32_t rx_done:                      1;
+            uint32_t rx_eof:                       1;
+            uint32_t tohost:                       1;
+            uint32_t tx_dscr_err:                  1;
+            uint32_t rx_dscr_err:                  1;
+            uint32_t tx_dscr_empty:                1;
+            uint32_t host_rd_ack:                  1;
+            uint32_t wr_retry_done:                1;
+            uint32_t tx_err_eof:                   1;
+            uint32_t cmd_dtc:                      1;
+            uint32_t rx_quick_eof:                 1;
+            uint32_t host_pop_eof_err:             1;
+            uint32_t reserved28:                   4;
+        };
+        uint32_t val;
+    } slc0_int_st;
+    union {
+        struct {
+            uint32_t frhost_bit0:                   1;
+            uint32_t frhost_bit1:                   1;
+            uint32_t frhost_bit2:                   1;
+            uint32_t frhost_bit3:                   1;
+            uint32_t frhost_bit4:                   1;
+            uint32_t frhost_bit5:                   1;
+            uint32_t frhost_bit6:                   1;
+            uint32_t frhost_bit7:                   1;
+            uint32_t rx_start:                      1;
+            uint32_t tx_start:                      1;
+            uint32_t rx_udf:                        1;
+            uint32_t tx_ovf:                        1;
+            uint32_t token0_1to0:                   1;
+            uint32_t token1_1to0:                   1;
+            uint32_t tx_done:                       1;
+            uint32_t tx_suc_eof:                    1;
+            uint32_t rx_done:                       1;
+            uint32_t rx_eof:                        1;
+            uint32_t tohost:                        1;
+            uint32_t tx_dscr_err:                   1;
+            uint32_t rx_dscr_err:                   1;
+            uint32_t tx_dscr_empty:                 1;
+            uint32_t host_rd_ack:                   1;
+            uint32_t wr_retry_done:                 1;
+            uint32_t tx_err_eof:                    1;
+            uint32_t cmd_dtc:                       1;
+            uint32_t rx_quick_eof:                  1;
+            uint32_t host_pop_eof_err:              1;
+            uint32_t reserved28:                    4;
+        };
+        uint32_t val;
+    } slc0_int_ena;
+    union {
+        struct {
+            uint32_t frhost_bit0:                   1;
+            uint32_t frhost_bit1:                   1;
+            uint32_t frhost_bit2:                   1;
+            uint32_t frhost_bit3:                   1;
+            uint32_t frhost_bit4:                   1;
+            uint32_t frhost_bit5:                   1;
+            uint32_t frhost_bit6:                   1;
+            uint32_t frhost_bit7:                   1;
+            uint32_t rx_start:                      1;
+            uint32_t tx_start:                      1;
+            uint32_t rx_udf:                        1;
+            uint32_t tx_ovf:                        1;
+            uint32_t token0_1to0:                   1;
+            uint32_t token1_1to0:                   1;
+            uint32_t tx_done:                       1;
+            uint32_t tx_suc_eof:                    1;
+            uint32_t rx_done:                       1;
+            uint32_t rx_eof:                        1;
+            uint32_t tohost:                        1;
+            uint32_t tx_dscr_err:                   1;
+            uint32_t rx_dscr_err:                   1;
+            uint32_t tx_dscr_empty:                 1;
+            uint32_t host_rd_ack:                   1;
+            uint32_t wr_retry_done:                 1;
+            uint32_t tx_err_eof:                    1;
+            uint32_t cmd_dtc:                       1;
+            uint32_t rx_quick_eof:                  1;
+            uint32_t host_pop_eof_err:              1;
+            uint32_t reserved28:                    4;
+        };
+        uint32_t val;
+    } slc0_int_clr;
+    uint32_t reserved_14;
+    uint32_t reserved_18;
+    uint32_t reserved_1c;
+    uint32_t reserved_20;
+    union {
+        struct {
+            uint32_t slc0_rx_full:    1;
+            uint32_t slc0_rx_empty:   1;
+            uint32_t slc0_rx_buf_len:12;
+            uint32_t reserved14:     18;
+        };
+        uint32_t val;
+    } rx_status;
+    union {
+        struct {
+            uint32_t rxfifo_wdata:      9;
+            uint32_t reserved9:         7;
+            uint32_t rxfifo_push:       1;
+            uint32_t reserved17:       15;
+        };
+        uint32_t val;
+    } slc0_rxfifo_push;
+    uint32_t reserved_2c;
+    union {
+        struct {
+            uint32_t slc0_tx_full:  1;
+            uint32_t slc0_tx_empty: 1;
+            uint32_t reserved2:    30;
+        };
+        uint32_t val;
+    } tx_status;
+    union {
+        struct {
+            uint32_t txfifo_rdata:     11;
+            uint32_t reserved11:        5;
+            uint32_t txfifo_pop:        1;
+            uint32_t reserved17:       15;
+        };
+        uint32_t val;
+    } slc0_txfifo_pop;
+    uint32_t reserved_38;
+    union {
+        struct {
+            uint32_t addr:               20;
+            uint32_t reserved20:          8;
+            uint32_t stop:                1;
+            uint32_t start:               1;
+            uint32_t restart:             1;
+            uint32_t park:                1;
+        };
+        uint32_t val;
+    } slc0_rx_link;
+    union {
+        struct {
+            uint32_t addr:               20;
+            uint32_t reserved20:          8;
+            uint32_t stop:                1;
+            uint32_t start:               1;
+            uint32_t restart:             1;
+            uint32_t park:                1;
+        };
+        uint32_t val;
+    } slc0_tx_link;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    union {
+        struct {
+            uint32_t slc0_intvec:        8;
+            uint32_t reserved8:         24;
+        };
+        uint32_t val;
+    } intvec_tohost;
+    union {
+        struct {
+            uint32_t wdata:               12;
+            uint32_t wr:                   1;
+            uint32_t inc:                  1;
+            uint32_t inc_more:             1;
+            uint32_t reserved15:           1;
+            uint32_t token0:              12;
+            uint32_t reserved28:           4;
+        };
+        uint32_t val;
+    } slc0_token0;
+    union {
+        struct {
+            uint32_t wdata:               12;
+            uint32_t wr:                   1;
+            uint32_t inc:                  1;
+            uint32_t inc_more:             1;
+            uint32_t reserved15:           1;
+            uint32_t token1:              12;
+            uint32_t reserved28:           4;
+        };
+        uint32_t val;
+    } slc0_token1;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    union {
+        struct {
+            uint32_t slc0_check_owner:     1;
+            uint32_t slc0_tx_check_sum_en: 1;
+            uint32_t slc0_rx_check_sum_en: 1;
+            uint32_t cmd_hold_en:          1;
+            uint32_t slc0_len_auto_clr:    1;
+            uint32_t slc0_tx_stitch_en:    1;
+            uint32_t slc0_rx_stitch_en:    1;
+            uint32_t reserved7:           12;
+            uint32_t host_int_level_sel:   1;
+            uint32_t reserved20:           2;
+            uint32_t clk_en:               1;
+            uint32_t reserved23:           9;
+        };
+        uint32_t val;
+    } conf1;
+    uint32_t slc0_state0;                                 /**/
+    uint32_t slc0_state1;                                 /**/
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    union {
+        struct {
+            uint32_t txeof_ena:          6;
+            uint32_t reserved6:          2;
+            uint32_t fifo_map_ena:       4;
+            uint32_t slc0_tx_dummy_mode: 1;
+            uint32_t hda_map_128k:       1;
+            uint32_t reserved14:         2;
+            uint32_t tx_push_idle_num:  16;
+        };
+        uint32_t val;
+    } bridge_conf;
+    uint32_t slc0_to_eof_des_addr;                        /**/
+    uint32_t slc0_tx_eof_des_addr;                        /**/
+    uint32_t slc0_to_eof_bfr_des_addr;                    /**/
+    uint32_t reserved_84;
+    uint32_t reserved_88;
+    uint32_t reserved_8c;
+    union {
+        struct {
+            uint32_t mode:         3;
+            uint32_t reserved3:    1;
+            uint32_t addr:         2;
+            uint32_t reserved6:   26;
+        };
+        uint32_t val;
+    } ahb_test;
+    union {
+        struct {
+            uint32_t cmd_st:          3;
+            uint32_t reserved3:       1;
+            uint32_t func_st:         4;
+            uint32_t sdio_wakeup:     1;
+            uint32_t reserved9:       3;
+            uint32_t bus_st:          3;
+            uint32_t reserved15:      1;
+            uint32_t func1_acc_state: 5;
+            uint32_t reserved21:     11;
+        };
+        uint32_t val;
+    } sdio_st;
+    union {
+        struct {
+            uint32_t slc0_token_no_replace:   1;
+            uint32_t slc0_infor_no_replace:   1;
+            uint32_t slc0_rx_fill_mode:       1;
+            uint32_t slc0_rx_eof_mode:        1;
+            uint32_t slc0_rx_fill_en:         1;
+            uint32_t slc0_rd_retry_threshold:11;
+            uint32_t reserved16:             16;
+        };
+        uint32_t val;
+    } rx_dscr_conf;
+    uint32_t slc0_txlink_dscr;                            /**/
+    uint32_t slc0_txlink_dscr_bf0;                        /**/
+    uint32_t slc0_txlink_dscr_bf1;                        /**/
+    uint32_t slc0_rxlink_dscr;                            /**/
+    uint32_t slc0_rxlink_dscr_bf0;                        /**/
+    uint32_t slc0_rxlink_dscr_bf1;                        /**/
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t slc0_tx_erreof_des_addr;                     /**/
+    uint32_t reserved_d0;
+    union {
+        struct {
+            uint32_t slc0_token:12;
+            uint32_t reserved12:20;
+        };
+        uint32_t val;
+    } token_lat;
+    union {
+        struct {
+            uint32_t wr_retry_threshold:11;
+            uint32_t reserved11:        21;
+        };
+        uint32_t val;
+    } tx_dscr_conf;
+    uint32_t cmd_infor0;                                  /**/
+    uint32_t cmd_infor1;                                  /**/
+    union {
+        struct {
+            uint32_t len_wdata:             20;
+            uint32_t len_wr:                 1;
+            uint32_t len_inc:                1;
+            uint32_t len_inc_more:           1;
+            uint32_t rx_packet_load_en:      1;
+            uint32_t tx_packet_load_en:      1;
+            uint32_t rx_get_used_dscr:       1;
+            uint32_t tx_get_used_dscr:       1;
+            uint32_t rx_new_pkt_ind:         1;
+            uint32_t tx_new_pkt_ind:         1;
+            uint32_t reserved29:             3;
+        };
+        uint32_t val;
+    } slc0_len_conf;
+    union {
+        struct {
+            uint32_t len:       20;
+            uint32_t reserved20:12;
+        };
+        uint32_t val;
+    } slc0_length;
+    uint32_t slc0_txpkt_h_dscr;                           /**/
+    uint32_t slc0_txpkt_e_dscr;                           /**/
+    uint32_t slc0_rxpkt_h_dscr;                           /**/
+    uint32_t slc0_rxpkt_e_dscr;                           /**/
+    uint32_t slc0_txpktu_h_dscr;                          /**/
+    uint32_t slc0_txpktu_e_dscr;                          /**/
+    uint32_t slc0_rxpktu_h_dscr;                          /**/
+    uint32_t slc0_rxpktu_e_dscr;                          /**/
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    union {
+        struct {
+            uint32_t slc0_position:     8;
+            uint32_t reserved8:        24;
+        };
+        uint32_t val;
+    } seq_position;
+    union {
+        struct {
+            uint32_t rx_dscr_rec_lim:     10;
+            uint32_t reserved10:          22;
+        };
+        uint32_t val;
+    } slc0_dscr_rec_conf;
+    union {
+        struct {
+            uint32_t dat0_crc_err_cnt: 8;
+            uint32_t dat1_crc_err_cnt: 8;
+            uint32_t dat2_crc_err_cnt: 8;
+            uint32_t dat3_crc_err_cnt: 8;
+        };
+        uint32_t val;
+    } sdio_crc_st0;
+    union {
+        struct {
+            uint32_t cmd_crc_err_cnt: 8;
+            uint32_t reserved8:      23;
+            uint32_t err_cnt_clr:     1;
+        };
+        uint32_t val;
+    } sdio_crc_st1;
+    uint32_t slc0_eof_start_des;                          /**/
+    uint32_t slc0_push_dscr_addr;                         /**/
+    uint32_t slc0_done_dscr_addr;                         /**/
+    uint32_t slc0_sub_start_des;                          /**/
+    union {
+        struct {
+            uint32_t rx_dscr_cnt_lat:     10;
+            uint32_t reserved10:           6;
+            uint32_t rx_get_eof_occ:       1;
+            uint32_t reserved17:          15;
+        };
+        uint32_t val;
+    } slc0_dscr_cnt;
+    union {
+        struct {
+            uint32_t len_lim:     20;
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } slc0_len_lim_conf;
+    union {
+        struct {
+            uint32_t frhost_bit01:                  1;
+            uint32_t frhost_bit11:                  1;
+            uint32_t frhost_bit21:                  1;
+            uint32_t frhost_bit31:                  1;
+            uint32_t frhost_bit41:                  1;
+            uint32_t frhost_bit51:                  1;
+            uint32_t frhost_bit61:                  1;
+            uint32_t frhost_bit71:                  1;
+            uint32_t rx_start1:                     1;
+            uint32_t tx_start1:                     1;
+            uint32_t rx_udf1:                       1;
+            uint32_t tx_ovf1:                       1;
+            uint32_t token0_1to01:                  1;
+            uint32_t token1_1to01:                  1;
+            uint32_t tx_done1:                      1;
+            uint32_t tx_suc_eof1:                   1;
+            uint32_t rx_done1:                      1;
+            uint32_t rx_eof1:                       1;
+            uint32_t tohost1:                       1;
+            uint32_t tx_dscr_err1:                  1;
+            uint32_t rx_dscr_err1:                  1;
+            uint32_t tx_dscr_empty1:                1;
+            uint32_t host_rd_ack1:                  1;
+            uint32_t wr_retry_done1:                1;
+            uint32_t tx_err_eof1:                   1;
+            uint32_t cmd_dtc1:                      1;
+            uint32_t rx_quick_eof1:                 1;
+            uint32_t host_pop_eof_err1:             1;
+            uint32_t reserved28:                    4;
+        };
+        uint32_t val;
+    } slc0_int_st1;
+    union {
+        struct {
+            uint32_t frhost_bit01:                   1;
+            uint32_t frhost_bit11:                   1;
+            uint32_t frhost_bit21:                   1;
+            uint32_t frhost_bit31:                   1;
+            uint32_t frhost_bit41:                   1;
+            uint32_t frhost_bit51:                   1;
+            uint32_t frhost_bit61:                   1;
+            uint32_t frhost_bit71:                   1;
+            uint32_t rx_start1:                      1;
+            uint32_t tx_start1:                      1;
+            uint32_t rx_udf1:                        1;
+            uint32_t tx_ovf1:                        1;
+            uint32_t token0_1to01:                   1;
+            uint32_t token1_1to01:                   1;
+            uint32_t tx_done1:                       1;
+            uint32_t tx_suc_eof1:                    1;
+            uint32_t rx_done1:                       1;
+            uint32_t rx_eof1:                        1;
+            uint32_t tohost1:                        1;
+            uint32_t tx_dscr_err1:                   1;
+            uint32_t rx_dscr_err1:                   1;
+            uint32_t tx_dscr_empty1:                 1;
+            uint32_t host_rd_ack1:                   1;
+            uint32_t wr_retry_done1:                 1;
+            uint32_t tx_err_eof1:                    1;
+            uint32_t cmd_dtc1:                       1;
+            uint32_t rx_quick_eof1:                  1;
+            uint32_t host_pop_eof_err1:              1;
+            uint32_t reserved28:                     4;
+        };
+        uint32_t val;
+    } slc0_int_ena1;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t date;                                     /**/
+    uint32_t id;                                       /**/
+} slc_dev_t;
+extern slc_dev_t SLC;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SLC_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/soc.h b/components/soc/esp32s2beta/include/soc/soc.h
new file mode 100644
index 000000000..d00ae1c47
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/soc.h
@@ -0,0 +1,373 @@
+// Copyright 2010-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _ESP32_SOC_H_
+#define _ESP32_SOC_H_
+
+#ifndef __ASSEMBLER__
+#include <stdint.h>
+#include "esp_assert.h"
+#endif
+
+//Register Bits{{
+#define BIT31   0x80000000
+#define BIT30   0x40000000
+#define BIT29   0x20000000
+#define BIT28   0x10000000
+#define BIT27   0x08000000
+#define BIT26   0x04000000
+#define BIT25   0x02000000
+#define BIT24   0x01000000
+#define BIT23   0x00800000
+#define BIT22   0x00400000
+#define BIT21   0x00200000
+#define BIT20   0x00100000
+#define BIT19   0x00080000
+#define BIT18   0x00040000
+#define BIT17   0x00020000
+#define BIT16   0x00010000
+#define BIT15   0x00008000
+#define BIT14   0x00004000
+#define BIT13   0x00002000
+#define BIT12   0x00001000
+#define BIT11   0x00000800
+#define BIT10   0x00000400
+#define BIT9     0x00000200
+#define BIT8     0x00000100
+#define BIT7     0x00000080
+#define BIT6     0x00000040
+#define BIT5     0x00000020
+#define BIT4     0x00000010
+#define BIT3     0x00000008
+#define BIT2     0x00000004
+#define BIT1     0x00000002
+#define BIT0     0x00000001
+//}}
+
+#define PRO_CPU_NUM (0)
+
+#define DR_REG_SYSTEM_BASE                      0x3f4c0000
+#define DR_REG_SENSITIVE_BASE                   0x3f4c1000
+#define DR_REG_INTERRUPT_BASE                   0x3f4c2000
+#define DR_REG_DMA_COPY_BASE                    0x3f4c3000
+#define DR_REG_EXTMEM_BASE                      0x3f4c4000
+#define DR_REG_MMU_TABLE                        0x3f4c5000
+#define DR_REG_ITAG_TABLE                       0x3f4c6000
+#define DR_REG_DTAG_TABLE                       0x3f4c7000
+#define DR_REG_AES_BASE                         0x3f4c8000
+#define DR_REG_SHA_BASE                         0x3f4c9000
+#define DR_REG_RSA_BASE                         0x3f4ca000
+#define DR_REG_SECURE_BOOT_BASE                 0x3f4cb000
+#define DR_REG_HMAC_BASE                        0x3f4cc000
+#define DR_REG_DIGITAL_SINGNATURE_BASE          0x3f4cd000
+#define DR_REG_ASSIST_DEBUG_BASE                0x3f4ce000
+#define DR_REG_DEDICATED_GPIO_BASE              0x3f4cf000
+#define DR_REG_INTRUSION_BASE                   0x3f4d0000
+#define DR_REG_DPORT_END                        0x3f4d3FFC
+#define DR_REG_UART_BASE                        0x3f400000
+#define DR_REG_SPI1_BASE                        0x3f402000
+#define DR_REG_SPI0_BASE                        0x3f403000
+#define DR_REG_GPIO_BASE                        0x3f404000
+#define DR_REG_GPIO_SD_BASE                     0x3f404f00
+#define DR_REG_FE2_BASE                         0x3f405000
+#define DR_REG_FE_BASE                          0x3f406000
+#define DR_REG_FRC_TIMER_BASE                   0x3f407000
+#define DR_REG_RTCCNTL_BASE                     0x3f408000
+#define DR_REG_RTCIO_BASE                       0x3f408400
+#define DR_REG_SENS_BASE                        0x3f408800
+#define DR_REG_RTC_I2C_BASE                     0x3f408C00
+#define DR_REG_IO_MUX_BASE                      0x3f409000
+#define DR_REG_HINF_BASE                        0x3f40B000
+#define DR_REG_I2S_BASE                         0x3f40F000
+#define DR_REG_UART1_BASE                       0x3f410000
+#define DR_REG_I2C_EXT_BASE                     0x3f413000
+#define DR_REG_UHCI0_BASE                       0x3f414000
+#define DR_REG_SLCHOST_BASE                     0x3f415000
+#define DR_REG_RMT_BASE                         0x3f416000
+#define DR_REG_PCNT_BASE                        0x3f417000
+#define DR_REG_SLC_BASE                         0x3f418000
+#define DR_REG_LEDC_BASE                        0x3f419000
+#define DR_REG_EFUSE_BASE                       0x3f41A000
+#define DR_REG_NRX_BASE                         0x3f41CC00
+#define DR_REG_BB_BASE                          0x3f41D000
+#define DR_REG_TIMERGROUP0_BASE                 0x3f41F000
+#define DR_REG_TIMERGROUP1_BASE                 0x3f420000
+#define DR_REG_RTC_SLOWMEM_BASE                 0x3f421000
+#define DR_REG_SPI2_BASE                        0x3f424000
+#define DR_REG_SPI3_BASE                        0x3f425000
+#define DR_REG_SYSCON_BASE                      0x3f426000
+#define DR_REG_APB_CTRL_BASE                    0x3f426000    /* Old name for SYSCON, to be removed */
+#define DR_REG_I2C1_EXT_BASE                    0x3f427000
+#define DR_REG_SPI4_BASE                        0x3f437000
+#define DR_REG_USB_WRAP_BASE                    0x3f439000
+
+#define REG_UHCI_BASE(i)         (DR_REG_UHCI0_BASE)
+#define REG_UART_BASE( i )  (DR_REG_UART_BASE + (i) * 0x10000 )
+#define REG_UART_AHB_BASE(i)  (0x60000000 + (i) * 0x10000 )
+#define UART_FIFO_AHB_REG(i)  (REG_UART_AHB_BASE(i) + 0x0)
+#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
+#define REG_TIMG_BASE(i)              (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
+#define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
+#define REG_I2C_BASE(i)    (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
+
+//Registers Operation {{
+#define ETS_UNCACHED_ADDR(addr) (addr)
+#define ETS_CACHED_ADDR(addr) (addr) 
+
+#ifndef __ASSEMBLER__
+#define BIT(nr)                 (1UL << (nr))
+#else
+#define BIT(nr)                 (1 << (nr))
+#endif
+
+#ifndef __ASSEMBLER__
+
+#define IS_DPORT_REG(_r) (((_r) >= DR_REG_DPORT_BASE) && (_r) <= DR_REG_DPORT_END)
+
+#if !defined( BOOTLOADER_BUILD ) && !defined( CONFIG_FREERTOS_UNICORE ) && defined( ESP_PLATFORM )
+#define ASSERT_IF_DPORT_REG(_r, OP)  TRY_STATIC_ASSERT(!IS_DPORT_REG(_r), (Cannot use OP for DPORT registers use DPORT_##OP));
+#else
+#define ASSERT_IF_DPORT_REG(_r, OP)
+#endif
+
+//write value to register
+#define REG_WRITE(_r, _v) ({                                                                                           \
+            ASSERT_IF_DPORT_REG((_r), REG_WRITE);                                                                      \
+            (*(volatile uint32_t *)(_r)) = (_v);                                                                       \
+        })
+
+//read value from register
+#define REG_READ(_r) ({                                                                                                \
+            ASSERT_IF_DPORT_REG((_r), REG_READ);                                                                       \
+            (*(volatile uint32_t *)(_r));                                                                              \
+        })
+
+//get bit or get bits from register
+#define REG_GET_BIT(_r, _b)  ({                                                                                        \
+            ASSERT_IF_DPORT_REG((_r), REG_GET_BIT);                                                                    \
+            (*(volatile uint32_t*)(_r) & (_b));                                                                        \
+        })
+
+//set bit or set bits to register
+#define REG_SET_BIT(_r, _b)  ({                                                                                        \
+            ASSERT_IF_DPORT_REG((_r), REG_SET_BIT);                                                                    \
+            (*(volatile uint32_t*)(_r) |= (_b));                                                                       \
+        })
+
+//clear bit or clear bits of register
+#define REG_CLR_BIT(_r, _b)  ({                                                                                        \
+            ASSERT_IF_DPORT_REG((_r), REG_CLR_BIT);                                                                    \
+            (*(volatile uint32_t*)(_r) &= ~(_b));                                                                      \
+        })
+
+//set bits of register controlled by mask
+#define REG_SET_BITS(_r, _b, _m) ({                                                                                    \
+            ASSERT_IF_DPORT_REG((_r), REG_SET_BITS);                                                                   \
+            (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m)));                         \
+        })
+
+//get field from register, uses field _S & _V to determine mask
+#define REG_GET_FIELD(_r, _f) ({                                                                                       \
+            ASSERT_IF_DPORT_REG((_r), REG_GET_FIELD);                                                                  \
+            ((REG_READ(_r) >> (_f##_S)) & (_f##_V));                                                                   \
+        })
+
+//set field of a register from variable, uses field _S & _V to determine mask
+#define REG_SET_FIELD(_r, _f, _v) ({                                                                                   \
+            ASSERT_IF_DPORT_REG((_r), REG_SET_FIELD);                                                                  \
+            (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S)))));                \
+        })
+
+//get field value from a variable, used when _f is not left shifted by _f##_S
+#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
+
+//get field value from a variable, used when _f is left shifted by _f##_S
+#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
+
+//set field value to a variable, used when _f is not left shifted by _f##_S
+#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
+
+//set field value to a variable, used when _f is left shifted by _f##_S
+#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
+
+//generate a value from a field value, used when _f is not left shifted by _f##_S
+#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
+
+//generate a value from a field value, used when _f is left shifted by _f##_S
+#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
+
+//read value from register
+#define READ_PERI_REG(addr) ({                                                                                         \
+            ASSERT_IF_DPORT_REG((addr), READ_PERI_REG);                                                                \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr)));                                                         \
+        })
+
+//write value to register
+#define WRITE_PERI_REG(addr, val) ({                                                                                   \
+            ASSERT_IF_DPORT_REG((addr), WRITE_PERI_REG);                                                               \
+            (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val);                                       \
+        })
+
+//clear bits of register controlled by mask
+#define CLEAR_PERI_REG_MASK(reg, mask) ({                                                                              \
+            ASSERT_IF_DPORT_REG((reg), CLEAR_PERI_REG_MASK);                                                           \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask))));                                                     \
+        })
+
+//set bits of register controlled by mask
+#define SET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_MASK);                                                             \
+            WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask)));                                                        \
+        })
+
+//get bits of register controlled by mask
+#define GET_PERI_REG_MASK(reg, mask) ({                                                                                \
+            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_MASK);                                                             \
+            (READ_PERI_REG(reg) & (mask));                                                                             \
+        })
+
+//get bits of register controlled by highest bit and lowest bit
+#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({                                                                        \
+            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS);                                                             \
+            ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1));                                            \
+        })
+
+//set bits of register controlled by mask and shift
+#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({                                                                  \
+            ASSERT_IF_DPORT_REG((reg), SET_PERI_REG_BITS);                                                             \
+            (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) ));      \
+        })
+
+//get field of register
+#define GET_PERI_REG_BITS2(reg, mask,shift) ({                                                                         \
+            ASSERT_IF_DPORT_REG((reg), GET_PERI_REG_BITS2);                                                            \
+            ((READ_PERI_REG(reg)>>(shift))&(mask));                                                                    \
+        })
+
+#endif /* !__ASSEMBLER__ */
+//}}
+
+//Periheral Clock {{
+#define  APB_CLK_FREQ_ROM                            ( 40*1000000 )
+#define  CPU_CLK_FREQ_ROM                            APB_CLK_FREQ_ROM
+#define  UART_CLK_FREQ_ROM                           APB_CLK_FREQ_ROM
+#define  CPU_CLK_FREQ                                APB_CLK_FREQ
+#define  APB_CLK_FREQ                                ( 80*1000000 )       //unit: Hz
+#define  REF_CLK_FREQ                                ( 1000000 )
+#define  UART_CLK_FREQ                               APB_CLK_FREQ
+#define  WDT_CLK_FREQ                                APB_CLK_FREQ
+#define  TIMER_CLK_FREQ                              (80000000>>4) //80MHz divided by 16
+#define  SPI_CLK_DIV                                 4
+#define  TICKS_PER_US_ROM                            40              // CPU is 80MHz
+//}}
+
+/* Overall memory map */
+#define SOC_DROM_LOW    0x3F000000
+#define SOC_DROM_HIGH   0x3F400000
+#define SOC_IROM_LOW    0x40080000
+#define SOC_IROM_HIGH   0x40c00000
+#define SOC_IRAM_LOW    0x40020000
+#define SOC_IRAM_HIGH   0x40070000
+#define SOC_RTC_IRAM_LOW  0x40070000
+#define SOC_RTC_IRAM_HIGH 0x40072000
+#define SOC_RTC_DRAM_LOW  0x3ff9e000
+#define SOC_RTC_DRAM_HIGH 0x3ffa0000
+#define SOC_RTC_DATA_LOW  0x50000000
+#define SOC_RTC_DATA_HIGH 0x50002000
+#define SOC_EXTRAM_DATA_LOW 0x3F500000
+#define SOC_EXTRAM_DATA_HIGH 0x3FF90000
+#define SOC_SLOW_EXTRAM_DATA_LOW 0x61800000
+#define SOC_SLOW_EXTRAM_DATA_HIGH 0x61c00000
+
+//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
+#define SOC_DIRAM_IRAM_LOW    0x40020000
+#define SOC_DIRAM_IRAM_HIGH   0x4006FFFC
+#define SOC_DIRAM_DRAM_LOW    0x3FFB0000
+#define SOC_DIRAM_DRAM_HIGH   0x3FFFFFFC
+
+// Region of memory accessible via DMA. See esp_ptr_dma_capable().
+#define SOC_DMA_LOW  0x3FFB0000
+#define SOC_DMA_HIGH 0x40000000
+
+// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
+#define SOC_BYTE_ACCESSIBLE_LOW     0x3FF9E000
+#define SOC_BYTE_ACCESSIBLE_HIGH    0x40000000
+
+//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
+//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
+#define SOC_MEM_INTERNAL_LOW        0x3FF9E000
+#define SOC_MEM_INTERNAL_HIGH       0x40072000
+
+//interrupt cpu using table, Please see the core-isa.h
+/*************************************************************************************************************
+ *      Intr num                Level           Type                    PRO CPU usage           APP CPU uasge
+ *      0                       1               extern level            WMAC                    Reserved
+ *      1                       1               extern level            BT/BLE Host HCI DMA     BT/BLE Host HCI DMA
+ *      2                       1               extern level
+ *      3                       1               extern level
+ *      4                       1               extern level            WBB
+ *      5                       1               extern level            BT/BLE Controller       BT/BLE Controller
+ *      6                       1               timer                   FreeRTOS Tick(L1)       FreeRTOS Tick(L1)
+ *      7                       1               software                BT/BLE VHCI             BT/BLE VHCI
+ *      8                       1               extern level            BT/BLE BB(RX/TX)        BT/BLE BB(RX/TX)
+ *      9                       1               extern level
+ *      10                      1               extern edge
+ *      11                      3               profiling
+ *      12                      1               extern level
+ *      13                      1               extern level
+ *      14                      7               nmi                     Reserved                Reserved
+ *      15                      3               timer                   FreeRTOS Tick(L3)       FreeRTOS Tick(L3)
+ *      16                      5               timer
+ *      17                      1               extern level
+ *      18                      1               extern level
+ *      19                      2               extern level
+ *      20                      2               extern level
+ *      21                      2               extern level
+ *      22                      3               extern edge
+ *      23                      3               extern level
+ *      24                      4               extern level            TG1_WDT
+ *      25                      4               extern level            CACHEERR
+ *      26                      5               extern level
+ *      27                      3               extern level            Reserved                Reserved
+ *      28                      4               extern edge             DPORT ACCESS            DPORT ACCESS
+ *      29                      3               software                Reserved                Reserved
+ *      30                      4               extern edge             Reserved                Reserved
+ *      31                      5               extern level
+ *************************************************************************************************************
+ */
+
+//CPU0 Interrupt number reserved, not touch this.
+#define ETS_WMAC_INUM                           0
+#define ETS_BT_HOST_INUM                        1
+#define ETS_WBB_INUM                            4
+#define ETS_TG0_T1_INUM                         10 /**< use edge interrupt*/
+#define ETS_FRC1_INUM                           22
+#define ETS_T1_WDT_INUM                         24
+#define ETS_CACHEERR_INUM                       25
+#define ETS_DPORT_INUM                          28
+
+//CPU0 Interrupt number used in ROM, should be cancelled in SDK
+#define ETS_SLC_INUM                            1
+#define ETS_UART0_INUM                          5
+#define ETS_UART1_INUM                          5
+//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
+#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
+#define ETS_GPIO_INUM       4
+
+//Other interrupt number should be managed by the user
+
+//Invalid interrupt for number interrupt matrix
+#define ETS_INVALID_INUM                        6
+
+#endif /* _ESP32_SOC_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/soc_ulp.h b/components/soc/esp32s2beta/include/soc/soc_ulp.h
new file mode 100644
index 000000000..e8c20d2b5
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/soc_ulp.h
@@ -0,0 +1,46 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#pragma once
+
+// This file contains various convenience macros to be used in ULP programs.
+
+// Helper macros to calculate bit field width from mask, using the preprocessor.
+// Used later in READ_RTC_FIELD and WRITE_RTC_FIELD.
+#define IS_BIT_SET(m, i) (((m) >> (i)) & 1)
+#define MASK_TO_WIDTH_HELPER1(m, i)  IS_BIT_SET(m, i)
+#define MASK_TO_WIDTH_HELPER2(m, i)  (MASK_TO_WIDTH_HELPER1(m, i)  + MASK_TO_WIDTH_HELPER1(m, i + 1))
+#define MASK_TO_WIDTH_HELPER4(m, i)  (MASK_TO_WIDTH_HELPER2(m, i)  + MASK_TO_WIDTH_HELPER2(m, i + 2))
+#define MASK_TO_WIDTH_HELPER8(m, i)  (MASK_TO_WIDTH_HELPER4(m, i)  + MASK_TO_WIDTH_HELPER4(m, i + 4))
+#define MASK_TO_WIDTH_HELPER16(m, i) (MASK_TO_WIDTH_HELPER8(m, i)  + MASK_TO_WIDTH_HELPER8(m, i + 8))
+#define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16))
+
+// Peripheral register access macros, build around REG_RD and REG_WR instructions.
+// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
+
+// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
+#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \
+    REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit)
+
+// Write immediate value into rtc_reg[low_bit + bit_width - 1 : low_bit], bit_width <= 8
+#define WRITE_RTC_REG(rtc_reg, low_bit, bit_width, value) \
+    REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value) & 0xff)
+
+// Read from a field in rtc_reg into R0, up to 16 bits
+#define READ_RTC_FIELD(rtc_reg, field) \
+    READ_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER16(field ## _V, 0))
+
+// Write immediate value into a field in rtc_reg, up to 8 bits
+#define WRITE_RTC_FIELD(rtc_reg, field, value) \
+    WRITE_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER8(field ## _V, 0), ((value) & field ## _V))
+
diff --git a/components/soc/esp32s2beta/include/soc/spi_mem_reg.h b/components/soc/esp32s2beta/include/soc/spi_mem_reg.h
new file mode 100644
index 000000000..dfe4be5ce
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/spi_mem_reg.h
@@ -0,0 +1,1893 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_MEM_REG_H_
+#define _SOC_SPI_MEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define REG_SPI_MEM_BASE(i)     (DR_REG_SPI0_BASE - (i) * 0x1000)
+
+#define SPI_MEM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x000)
+/* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Read flash enable. Read flash operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_READ  (BIT(31))
+#define SPI_MEM_FLASH_READ_M  (BIT(31))
+#define SPI_MEM_FLASH_READ_V  0x1
+#define SPI_MEM_FLASH_READ_S  31
+/* SPI_MEM_FLASH_WREN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Write flash enable.  Write enable command will be sent when the
+ bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WREN  (BIT(30))
+#define SPI_MEM_FLASH_WREN_M  (BIT(30))
+#define SPI_MEM_FLASH_WREN_V  0x1
+#define SPI_MEM_FLASH_WREN_S  30
+/* SPI_MEM_FLASH_WRDI : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Write flash disable. Write disable command will be sent when
+ the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WRDI  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_M  (BIT(29))
+#define SPI_MEM_FLASH_WRDI_V  0x1
+#define SPI_MEM_FLASH_WRDI_S  29
+/* SPI_MEM_FLASH_RDID : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Read JEDEC ID . Read ID command will be sent when the bit is
+ set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RDID  (BIT(28))
+#define SPI_MEM_FLASH_RDID_M  (BIT(28))
+#define SPI_MEM_FLASH_RDID_V  0x1
+#define SPI_MEM_FLASH_RDID_S  28
+/* SPI_MEM_FLASH_RDSR : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: Read status register-1.  Read status operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RDSR  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_M  (BIT(27))
+#define SPI_MEM_FLASH_RDSR_V  0x1
+#define SPI_MEM_FLASH_RDSR_S  27
+/* SPI_MEM_FLASH_WRSR : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: Write status register enable.   Write status operation  will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_WRSR  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_M  (BIT(26))
+#define SPI_MEM_FLASH_WRSR_V  0x1
+#define SPI_MEM_FLASH_WRSR_S  26
+/* SPI_MEM_FLASH_PP : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: Page program enable(1 byte ~256 bytes data to be programmed).
+ Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PP  (BIT(25))
+#define SPI_MEM_FLASH_PP_M  (BIT(25))
+#define SPI_MEM_FLASH_PP_V  0x1
+#define SPI_MEM_FLASH_PP_S  25
+/* SPI_MEM_FLASH_SE : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: Sector erase enable(4KB). Sector erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_SE  (BIT(24))
+#define SPI_MEM_FLASH_SE_M  (BIT(24))
+#define SPI_MEM_FLASH_SE_V  0x1
+#define SPI_MEM_FLASH_SE_S  24
+/* SPI_MEM_FLASH_BE : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: Block erase enable(32KB) .  Block erase operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_BE  (BIT(23))
+#define SPI_MEM_FLASH_BE_M  (BIT(23))
+#define SPI_MEM_FLASH_BE_V  0x1
+#define SPI_MEM_FLASH_BE_S  23
+/* SPI_MEM_FLASH_CE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: Chip erase enable. Chip erase operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_CE  (BIT(22))
+#define SPI_MEM_FLASH_CE_M  (BIT(22))
+#define SPI_MEM_FLASH_CE_V  0x1
+#define SPI_MEM_FLASH_CE_S  22
+/* SPI_MEM_FLASH_DP : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: Drive Flash into power down.  An operation will be triggered
+ when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_DP  (BIT(21))
+#define SPI_MEM_FLASH_DP_M  (BIT(21))
+#define SPI_MEM_FLASH_DP_V  0x1
+#define SPI_MEM_FLASH_DP_S  21
+/* SPI_MEM_FLASH_RES : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: This bit combined with reg_resandres bit releases Flash from
+ the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_RES  (BIT(20))
+#define SPI_MEM_FLASH_RES_M  (BIT(20))
+#define SPI_MEM_FLASH_RES_V  0x1
+#define SPI_MEM_FLASH_RES_S  20
+/* SPI_MEM_FLASH_HPM : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: Drive Flash into high performance mode.  The bit will be cleared
+ once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_HPM  (BIT(19))
+#define SPI_MEM_FLASH_HPM_M  (BIT(19))
+#define SPI_MEM_FLASH_HPM_V  0x1
+#define SPI_MEM_FLASH_HPM_S  19
+/* SPI_MEM_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_USR  (BIT(18))
+#define SPI_MEM_USR_M  (BIT(18))
+#define SPI_MEM_USR_V  0x1
+#define SPI_MEM_USR_S  18
+/* SPI_MEM_FLASH_PE : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: In user mode  it is set to indicate that program/erase operation
+ will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PE  (BIT(17))
+#define SPI_MEM_FLASH_PE_M  (BIT(17))
+#define SPI_MEM_FLASH_PE_V  0x1
+#define SPI_MEM_FLASH_PE_S  17
+
+#define SPI_MEM_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x004)
+/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: In user mode  it is the memory address. other then the bit0-bit23
+ is the memory address  the bit24-bit31 are the byte length of a transfer.*/
+#define SPI_MEM_USR_ADDR_VALUE  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_M  ((SPI_MEM_USR_ADDR_VALUE_V)<<(SPI_MEM_USR_ADDR_VALUE_S))
+#define SPI_MEM_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_MEM_USR_ADDR_VALUE_S  0
+
+#define SPI_MEM_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x008)
+/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 4 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_QIO  (BIT(24))
+#define SPI_MEM_FREAD_QIO_M  (BIT(24))
+#define SPI_MEM_FREAD_QIO_V  0x1
+#define SPI_MEM_FREAD_QIO_S  24
+/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: In the read operations address phase and read-data phase apply
+ 2 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_DIO  (BIT(23))
+#define SPI_MEM_FREAD_DIO_M  (BIT(23))
+#define SPI_MEM_FREAD_DIO_V  0x1
+#define SPI_MEM_FREAD_DIO_S  23
+/* SPI_MEM_WRSR_2B : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: two bytes data will be written to status register when it is
+ set. 1: enable 0: disable.*/
+#define SPI_MEM_WRSR_2B  (BIT(22))
+#define SPI_MEM_WRSR_2B_M  (BIT(22))
+#define SPI_MEM_WRSR_2B_V  0x1
+#define SPI_MEM_WRSR_2B_S  22
+/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+#define SPI_MEM_WP_REG  (BIT(21))
+#define SPI_MEM_WP_REG_M  (BIT(21))
+#define SPI_MEM_WP_REG_V  0x1
+#define SPI_MEM_WP_REG_S  21
+/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_QUAD  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_M  (BIT(20))
+#define SPI_MEM_FREAD_QUAD_V  0x1
+#define SPI_MEM_FREAD_QUAD_S  20
+/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity  1: high 0  low*/
+#define SPI_MEM_D_POL  (BIT(19))
+#define SPI_MEM_D_POL_M  (BIT(19))
+#define SPI_MEM_D_POL_V  0x1
+#define SPI_MEM_D_POL_S  19
+/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity  1: high 0  low*/
+#define SPI_MEM_Q_POL  (BIT(18))
+#define SPI_MEM_Q_POL_M  (BIT(18))
+#define SPI_MEM_Q_POL_V  0x1
+#define SPI_MEM_Q_POL_S  18
+/* SPI_MEM_RESANDRES : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: The Device ID is read out to SPI_MEM_RD_STATUS register   this
+ bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
+#define SPI_MEM_RESANDRES  (BIT(15))
+#define SPI_MEM_RESANDRES_M  (BIT(15))
+#define SPI_MEM_RESANDRES_V  0x1
+#define SPI_MEM_RESANDRES_S  15
+/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+#define SPI_MEM_FREAD_DUAL  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_M  (BIT(14))
+#define SPI_MEM_FREAD_DUAL_V  0x1
+#define SPI_MEM_FREAD_DUAL_S  14
+/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio
+  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
+#define SPI_MEM_FASTRD_MODE  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_M  (BIT(13))
+#define SPI_MEM_FASTRD_MODE_V  0x1
+#define SPI_MEM_FASTRD_MODE_S  13
+/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI1   enable crc32 when writing encrypted data to flash.
+ 1: enable 0:disable*/
+#define SPI_MEM_TX_CRC_EN  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_M  (BIT(11))
+#define SPI_MEM_TX_CRC_EN_V  0x1
+#define SPI_MEM_TX_CRC_EN_S  11
+/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI1   initialize crc32 module before writing encrypted data
+ to flash. Active low.*/
+#define SPI_MEM_FCS_CRC_EN  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_M  (BIT(10))
+#define SPI_MEM_FCS_CRC_EN_V  0x1
+#define SPI_MEM_FCS_CRC_EN_S  10
+/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable*/
+#define SPI_MEM_FCMD_QUAD  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_M  (BIT(8))
+#define SPI_MEM_FCMD_QUAD_V  0x1
+#define SPI_MEM_FCMD_QUAD_S  8
+/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable*/
+#define SPI_MEM_FCMD_DUAL  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_M  (BIT(7))
+#define SPI_MEM_FCMD_DUAL_V  0x1
+#define SPI_MEM_FCMD_DUAL_S  7
+/* SPI_MEM_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller.*/
+#define SPI_MEM_DUMMY_OUT  (BIT(3))
+#define SPI_MEM_DUMMY_OUT_M  (BIT(3))
+#define SPI_MEM_DUMMY_OUT_V  0x1
+#define SPI_MEM_DUMMY_OUT_S  3
+
+#define SPI_MEM_CTRL1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x00C)
+/* SPI_MEM_CS_DLY_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify CS line timing.*/
+#define SPI_MEM_CS_DLY_EDGE  (BIT(31))
+#define SPI_MEM_CS_DLY_EDGE_M  (BIT(31))
+#define SPI_MEM_CS_DLY_EDGE_V  0x1
+#define SPI_MEM_CS_DLY_EDGE_S  31
+/* SPI_MEM_CS_DLY_MODE : R/W ;bitpos:[30:28] ;default: 3'h0 ; */
+/*description: The cs signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk*/
+#define SPI_MEM_CS_DLY_MODE  0x00000007
+#define SPI_MEM_CS_DLY_MODE_M  ((SPI_MEM_CS_DLY_MODE_V)<<(SPI_MEM_CS_DLY_MODE_S))
+#define SPI_MEM_CS_DLY_MODE_V  0x7
+#define SPI_MEM_CS_DLY_MODE_S  28
+/* SPI_MEM_CS_DLY_NUM : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
+/*description: spi_mem_cs signal is delayed by system clock cycles*/
+#define SPI_MEM_CS_DLY_NUM  0x00000003
+#define SPI_MEM_CS_DLY_NUM_M  ((SPI_MEM_CS_DLY_NUM_V)<<(SPI_MEM_CS_DLY_NUM_S))
+#define SPI_MEM_CS_DLY_NUM_V  0x3
+#define SPI_MEM_CS_DLY_NUM_S  26
+/* SPI_MEM_CS_HOLD_DLY : R/W ;bitpos:[25:14] ;default: 12'h1 ; */
+/*description: SPI fsm is delayed to idle by spi clock cycles.*/
+#define SPI_MEM_CS_HOLD_DLY  0x00000FFF
+#define SPI_MEM_CS_HOLD_DLY_M  ((SPI_MEM_CS_HOLD_DLY_V)<<(SPI_MEM_CS_HOLD_DLY_S))
+#define SPI_MEM_CS_HOLD_DLY_V  0xFFF
+#define SPI_MEM_CS_HOLD_DLY_S  14
+/* SPI_MEM_CS_HOLD_DLY_RES : R/W ;bitpos:[13:2] ;default: 12'hfff ; */
+/*description: Delay cycles of resume Flash when resume Flash from standby mode
+ is enable by spi clock.*/
+#define SPI_MEM_CS_HOLD_DLY_RES  0x00000FFF
+#define SPI_MEM_CS_HOLD_DLY_RES_M  ((SPI_MEM_CS_HOLD_DLY_RES_V)<<(SPI_MEM_CS_HOLD_DLY_RES_S))
+#define SPI_MEM_CS_HOLD_DLY_RES_V  0xFFF
+#define SPI_MEM_CS_HOLD_DLY_RES_S  2
+/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+#define SPI_MEM_CLK_MODE  0x00000003
+#define SPI_MEM_CLK_MODE_M  ((SPI_MEM_CLK_MODE_V)<<(SPI_MEM_CLK_MODE_S))
+#define SPI_MEM_CLK_MODE_V  0x3
+#define SPI_MEM_CLK_MODE_S  0
+
+#define SPI_MEM_CTRL2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x010)
+/* SPI_MEM_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: The FSM will be reset.*/
+#define SPI_MEM_SYNC_RESET  (BIT(31))
+#define SPI_MEM_SYNC_RESET_M  (BIT(31))
+#define SPI_MEM_SYNC_RESET_V  0x1
+#define SPI_MEM_SYNC_RESET_S  31
+/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[25:13] ;default: 13'h1 ; */
+/*description: Spi cs signal is delayed to inactive by spi clock this bits are
+ combined with spi_mem_cs_hold bit.*/
+#define SPI_MEM_CS_HOLD_TIME  0x00001FFF
+#define SPI_MEM_CS_HOLD_TIME_M  ((SPI_MEM_CS_HOLD_TIME_V)<<(SPI_MEM_CS_HOLD_TIME_S))
+#define SPI_MEM_CS_HOLD_TIME_V  0x1FFF
+#define SPI_MEM_CS_HOLD_TIME_S  13
+/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
+/*description: (cycles-1) of prepare phase by spi clock this bits are combined
+ with spi_mem_cs_setup bit.*/
+#define SPI_MEM_CS_SETUP_TIME  0x00001FFF
+#define SPI_MEM_CS_SETUP_TIME_M  ((SPI_MEM_CS_SETUP_TIME_V)<<(SPI_MEM_CS_SETUP_TIME_S))
+#define SPI_MEM_CS_SETUP_TIME_V  0x1FFF
+#define SPI_MEM_CS_SETUP_TIME_S  0
+
+#define SPI_MEM_CLOCK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x014)
+/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: reserved*/
+#define SPI_MEM_CLK_EQU_SYSCLK  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_CLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_CLK_EQU_SYSCLK_S  31
+/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk
+ frequency is system/(spi_mem_clkcnt_N+1)*/
+#define SPI_MEM_CLKCNT_N  0x000000FF
+#define SPI_MEM_CLKCNT_N_M  ((SPI_MEM_CLKCNT_N_V)<<(SPI_MEM_CLKCNT_N_S))
+#define SPI_MEM_CLKCNT_N_V  0xFF
+#define SPI_MEM_CLKCNT_N_S  16
+/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+#define SPI_MEM_CLKCNT_H  0x000000FF
+#define SPI_MEM_CLKCNT_H_M  ((SPI_MEM_CLKCNT_H_V)<<(SPI_MEM_CLKCNT_H_S))
+#define SPI_MEM_CLKCNT_H_V  0xFF
+#define SPI_MEM_CLKCNT_H_S  8
+/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: In the master mode it must be equal to spi_mem_clkcnt_N.*/
+#define SPI_MEM_CLKCNT_L  0x000000FF
+#define SPI_MEM_CLKCNT_L_M  ((SPI_MEM_CLKCNT_L_V)<<(SPI_MEM_CLKCNT_L_S))
+#define SPI_MEM_CLKCNT_L_V  0xFF
+#define SPI_MEM_CLKCNT_L_S  0
+
+#define SPI_MEM_USER_REG(i)          (REG_SPI_MEM_BASE(i) + 0x018)
+/* SPI_MEM_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation.*/
+#define SPI_MEM_USR_COMMAND  (BIT(31))
+#define SPI_MEM_USR_COMMAND_M  (BIT(31))
+#define SPI_MEM_USR_COMMAND_V  0x1
+#define SPI_MEM_USR_COMMAND_S  31
+/* SPI_MEM_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation.*/
+#define SPI_MEM_USR_ADDR  (BIT(30))
+#define SPI_MEM_USR_ADDR_M  (BIT(30))
+#define SPI_MEM_USR_ADDR_V  0x1
+#define SPI_MEM_USR_ADDR_S  30
+/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation.*/
+#define SPI_MEM_USR_DUMMY  (BIT(29))
+#define SPI_MEM_USR_DUMMY_M  (BIT(29))
+#define SPI_MEM_USR_DUMMY_V  0x1
+#define SPI_MEM_USR_DUMMY_S  29
+/* SPI_MEM_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation.*/
+#define SPI_MEM_USR_MISO  (BIT(28))
+#define SPI_MEM_USR_MISO_M  (BIT(28))
+#define SPI_MEM_USR_MISO_V  0x1
+#define SPI_MEM_USR_MISO_S  28
+/* SPI_MEM_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation.*/
+#define SPI_MEM_USR_MOSI  (BIT(27))
+#define SPI_MEM_USR_MOSI_M  (BIT(27))
+#define SPI_MEM_USR_MOSI_V  0x1
+#define SPI_MEM_USR_MOSI_S  27
+/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable.*/
+#define SPI_MEM_USR_DUMMY_IDLE  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_MEM_USR_DUMMY_IDLE_V  0x1
+#define SPI_MEM_USR_DUMMY_IDLE_S  26
+/* SPI_MEM_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+ 1: enable 0: disable.*/
+#define SPI_MEM_USR_MOSI_HIGHPART  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_MEM_USR_MOSI_HIGHPART_V  0x1
+#define SPI_MEM_USR_MOSI_HIGHPART_S  25
+/* SPI_MEM_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+ 1: enable 0: disable.*/
+#define SPI_MEM_USR_MISO_HIGHPART  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_MEM_USR_MISO_HIGHPART_V  0x1
+#define SPI_MEM_USR_MISO_HIGHPART_S  24
+/* SPI_MEM_FWRITE_QIO : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 4 signals.*/
+#define SPI_MEM_FWRITE_QIO  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_M  (BIT(15))
+#define SPI_MEM_FWRITE_QIO_V  0x1
+#define SPI_MEM_FWRITE_QIO_S  15
+/* SPI_MEM_FWRITE_DIO : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the write operations address phase and read-data phase apply 2 signals.*/
+#define SPI_MEM_FWRITE_DIO  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_M  (BIT(14))
+#define SPI_MEM_FWRITE_DIO_V  0x1
+#define SPI_MEM_FWRITE_DIO_S  14
+/* SPI_MEM_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals*/
+#define SPI_MEM_FWRITE_QUAD  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_M  (BIT(13))
+#define SPI_MEM_FWRITE_QUAD_V  0x1
+#define SPI_MEM_FWRITE_QUAD_S  13
+/* SPI_MEM_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals*/
+#define SPI_MEM_FWRITE_DUAL  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_M  (BIT(12))
+#define SPI_MEM_FWRITE_DUAL_V  0x1
+#define SPI_MEM_FWRITE_DUAL_S  12
+/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi
+ signal delay mode.*/
+#define SPI_MEM_CK_OUT_EDGE  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_OUT_EDGE_V  0x1
+#define SPI_MEM_CK_OUT_EDGE_S  9
+/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+#define SPI_MEM_CS_SETUP  (BIT(7))
+#define SPI_MEM_CS_SETUP_M  (BIT(7))
+#define SPI_MEM_CS_SETUP_V  0x1
+#define SPI_MEM_CS_SETUP_S  7
+/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+#define SPI_MEM_CS_HOLD  (BIT(6))
+#define SPI_MEM_CS_HOLD_M  (BIT(6))
+#define SPI_MEM_CS_HOLD_V  0x1
+#define SPI_MEM_CS_HOLD_S  6
+
+#define SPI_MEM_USER1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x01C)
+/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_ADDR_BITLEN  0x0000003F
+#define SPI_MEM_USR_ADDR_BITLEN_M  ((SPI_MEM_USR_ADDR_BITLEN_V)<<(SPI_MEM_USR_ADDR_BITLEN_S))
+#define SPI_MEM_USR_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_USR_ADDR_BITLEN_S  26
+/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_mem_clk cycles of dummy phase. The register
+ value shall be (cycle_num-1).*/
+#define SPI_MEM_USR_DUMMY_CYCLELEN  0x000000FF
+#define SPI_MEM_USR_DUMMY_CYCLELEN_M  ((SPI_MEM_USR_DUMMY_CYCLELEN_V)<<(SPI_MEM_USR_DUMMY_CYCLELEN_S))
+#define SPI_MEM_USR_DUMMY_CYCLELEN_V  0xFF
+#define SPI_MEM_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_MEM_USER2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x020)
+/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/
+#define SPI_MEM_USR_COMMAND_BITLEN  0x0000000F
+#define SPI_MEM_USR_COMMAND_BITLEN_M  ((SPI_MEM_USR_COMMAND_BITLEN_V)<<(SPI_MEM_USR_COMMAND_BITLEN_S))
+#define SPI_MEM_USR_COMMAND_BITLEN_V  0xF
+#define SPI_MEM_USR_COMMAND_BITLEN_S  28
+/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command.*/
+#define SPI_MEM_USR_COMMAND_VALUE  0x0000FFFF
+#define SPI_MEM_USR_COMMAND_VALUE_M  ((SPI_MEM_USR_COMMAND_VALUE_V)<<(SPI_MEM_USR_COMMAND_VALUE_S))
+#define SPI_MEM_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_MEM_USR_COMMAND_VALUE_S  0
+
+#define SPI_MEM_MOSI_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x024)
+/* SPI_MEM_USR_MOSI_DBITLEN : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_MOSI_DBITLEN  0x000007FF
+#define SPI_MEM_USR_MOSI_DBITLEN_M  ((SPI_MEM_USR_MOSI_DBITLEN_V)<<(SPI_MEM_USR_MOSI_DBITLEN_S))
+#define SPI_MEM_USR_MOSI_DBITLEN_V  0x7FF
+#define SPI_MEM_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MEM_MISO_DLEN_REG(i)          (REG_SPI_MEM_BASE(i) + 0x028)
+/* SPI_MEM_USR_MISO_DBITLEN : R/W ;bitpos:[10:0] ;default: 11'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1).*/
+#define SPI_MEM_USR_MISO_DBITLEN  0x000007FF
+#define SPI_MEM_USR_MISO_DBITLEN_M  ((SPI_MEM_USR_MISO_DBITLEN_V)<<(SPI_MEM_USR_MISO_DBITLEN_S))
+#define SPI_MEM_USR_MISO_DBITLEN_V  0x7FF
+#define SPI_MEM_USR_MISO_DBITLEN_S  0
+
+#define SPI_MEM_RD_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x02C)
+/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */
+/*description: Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode
+ bit.*/
+#define SPI_MEM_WB_MODE  0x000000FF
+#define SPI_MEM_WB_MODE_M  ((SPI_MEM_WB_MODE_V)<<(SPI_MEM_WB_MODE_S))
+#define SPI_MEM_WB_MODE_V  0xFF
+#define SPI_MEM_WB_MODE_S  16
+/* SPI_MEM_STATUS : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+#define SPI_MEM_STATUS  0x0000FFFF
+#define SPI_MEM_STATUS_M  ((SPI_MEM_STATUS_V)<<(SPI_MEM_STATUS_S))
+#define SPI_MEM_STATUS_V  0xFFFF
+#define SPI_MEM_STATUS_S  0
+
+#define SPI_MEM_EXT_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x030)
+/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The register are the higher 32bits in the 64 bits address mode.*/
+#define SPI_MEM_EXT_ADDR  0xFFFFFFFF
+#define SPI_MEM_EXT_ADDR_M  ((SPI_MEM_EXT_ADDR_V)<<(SPI_MEM_EXT_ADDR_S))
+#define SPI_MEM_EXT_ADDR_V  0xFFFFFFFF
+#define SPI_MEM_EXT_ADDR_S  0
+
+#define SPI_MEM_MISC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x034)
+/* SPI_MEM_AUTO_PER : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: reserved*/
+#define SPI_MEM_AUTO_PER  (BIT(11))
+#define SPI_MEM_AUTO_PER_M  (BIT(11))
+#define SPI_MEM_AUTO_PER_V  0x1
+#define SPI_MEM_AUTO_PER_S  11
+/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set.*/
+#define SPI_MEM_CS_KEEP_ACTIVE  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_M  (BIT(10))
+#define SPI_MEM_CS_KEEP_ACTIVE_V  0x1
+#define SPI_MEM_CS_KEEP_ACTIVE_S  10
+/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle*/
+#define SPI_MEM_CK_IDLE_EDGE  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_M  (BIT(9))
+#define SPI_MEM_CK_IDLE_EDGE_V  0x1
+#define SPI_MEM_CK_IDLE_EDGE_S  9
+/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0   sram is connected to SUBPINs.*/
+#define SPI_MEM_SSUB_PIN  (BIT(8))
+#define SPI_MEM_SSUB_PIN_M  (BIT(8))
+#define SPI_MEM_SSUB_PIN_V  0x1
+#define SPI_MEM_SSUB_PIN_S  8
+/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0   flash is connected to SUBPINs.*/
+#define SPI_MEM_FSUB_PIN  (BIT(7))
+#define SPI_MEM_FSUB_PIN_M  (BIT(7))
+#define SPI_MEM_FSUB_PIN_V  0x1
+#define SPI_MEM_FSUB_PIN_S  7
+/* SPI_MEM_CS_POL : R/W ;bitpos:[6:5] ;default: 2'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line 
+ the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/
+#define SPI_MEM_CS_POL  0x00000003
+#define SPI_MEM_CS_POL_M  ((SPI_MEM_CS_POL_V)<<(SPI_MEM_CS_POL_S))
+#define SPI_MEM_CS_POL_V  0x3
+#define SPI_MEM_CS_POL_S  5
+/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The bit is used to enable the intterrupt of SPI transmitting done.*/
+#define SPI_MEM_TRANS_END_INT_ENA  (BIT(4))
+#define SPI_MEM_TRANS_END_INT_ENA_M  (BIT(4))
+#define SPI_MEM_TRANS_END_INT_ENA_V  0x1
+#define SPI_MEM_TRANS_END_INT_ENA_S  4
+/* SPI_MEM_TRANS_END : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to indicate the transimitting is done.*/
+#define SPI_MEM_TRANS_END  (BIT(3))
+#define SPI_MEM_TRANS_END_M  (BIT(3))
+#define SPI_MEM_TRANS_END_V  0x1
+#define SPI_MEM_TRANS_END_S  3
+/* SPI_MEM_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS1 pin enable  1: disable CS1  0: spi_mem_cs1 signal is from/to CS1 pin*/
+#define SPI_MEM_CS1_DIS  (BIT(1))
+#define SPI_MEM_CS1_DIS_M  (BIT(1))
+#define SPI_MEM_CS1_DIS_V  0x1
+#define SPI_MEM_CS1_DIS_S  1
+/* SPI_MEM_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS0 pin enable  1: disable CS0  0: spi_mem_cs0 signal is from/to CS0 pin*/
+#define SPI_MEM_CS0_DIS  (BIT(0))
+#define SPI_MEM_CS0_DIS_M  (BIT(0))
+#define SPI_MEM_CS0_DIS_V  0x1
+#define SPI_MEM_CS0_DIS_S  0
+
+#define SPI_MEM_TX_CRC_REG(i)          (REG_SPI_MEM_BASE(i) + 0x038)
+/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: For SPI1  the value of crc32.*/
+#define SPI_MEM_TX_CRC_DATA  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_M  ((SPI_MEM_TX_CRC_DATA_V)<<(SPI_MEM_TX_CRC_DATA_S))
+#define SPI_MEM_TX_CRC_DATA_V  0xFFFFFFFF
+#define SPI_MEM_TX_CRC_DATA_S  0
+
+#define SPI_MEM_CACHE_FCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x03C)
+/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: For SPI0 flash  address phase apply 4 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FADDR_QUAD  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_M  (BIT(8))
+#define SPI_MEM_FADDR_QUAD_V  0x1
+#define SPI_MEM_FADDR_QUAD_S  8
+/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: For SPI0 flash  dout phase apply 4 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FDOUT_QUAD  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_M  (BIT(7))
+#define SPI_MEM_FDOUT_QUAD_V  0x1
+#define SPI_MEM_FDOUT_QUAD_S  7
+/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: For SPI0 flash  din phase apply 4 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_qio.*/
+#define SPI_MEM_FDIN_QUAD  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_M  (BIT(6))
+#define SPI_MEM_FDIN_QUAD_V  0x1
+#define SPI_MEM_FDIN_QUAD_S  6
+/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: For SPI0 flash  address phase apply 2 signals. 1: enable 0: disable.
+  The bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FADDR_DUAL  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_M  (BIT(5))
+#define SPI_MEM_FADDR_DUAL_V  0x1
+#define SPI_MEM_FADDR_DUAL_S  5
+/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: For SPI0 flash  dout phase apply 2 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FDOUT_DUAL  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_M  (BIT(4))
+#define SPI_MEM_FDOUT_DUAL_V  0x1
+#define SPI_MEM_FDOUT_DUAL_S  4
+/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0 flash  din phase apply 2 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_fread_dio.*/
+#define SPI_MEM_FDIN_DUAL  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_M  (BIT(3))
+#define SPI_MEM_FDIN_DUAL_V  0x1
+#define SPI_MEM_FDIN_DUAL_S  3
+/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_FLASH_USR_CMD  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_M  (BIT(2))
+#define SPI_MEM_CACHE_FLASH_USR_CMD_V  0x1
+#define SPI_MEM_CACHE_FLASH_USR_CMD_S  2
+/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0   cache  read flash with 4 bytes command  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_USR_CMD_4BYTE  (BIT(1))
+#define SPI_MEM_CACHE_USR_CMD_4BYTE_M  (BIT(1))
+#define SPI_MEM_CACHE_USR_CMD_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_CMD_4BYTE_S  1
+/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0  Cache access enable  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_REQ_EN  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_M  (BIT(0))
+#define SPI_MEM_CACHE_REQ_EN_V  0x1
+#define SPI_MEM_CACHE_REQ_EN_S  0
+
+#define SPI_MEM_CACHE_SCTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x040)
+/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[29:22] ;default: 8'b1 ; */
+/*description: For SPI0  In the sram mode  it is the length in bits of write
+ dummy phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN  0x000000FF
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_WDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V  0xFF
+#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S  22
+/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: For SPI0  In the spi sram mode cache write sram for user define command*/
+#define SPI_MEM_CACHE_SRAM_USR_WCMD  (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_M  (BIT(20))
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_WCMD_S  20
+/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */
+/*description: For SPI0  In the sram mode  it is the length in bits of address
+ phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_SRAM_ADDR_BITLEN  0x0000003F
+#define SPI_MEM_SRAM_ADDR_BITLEN_M  ((SPI_MEM_SRAM_ADDR_BITLEN_V)<<(SPI_MEM_SRAM_ADDR_BITLEN_S))
+#define SPI_MEM_SRAM_ADDR_BITLEN_V  0x3F
+#define SPI_MEM_SRAM_ADDR_BITLEN_S  14
+/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[13:6] ;default: 8'b1 ; */
+/*description: For SPI0  In the sram mode  it is the length in bits of read
+ dummy phase. The register value shall be (bit_num-1).*/
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN  0x000000FF
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M  ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V)<<(SPI_MEM_SRAM_RDUMMY_CYCLELEN_S))
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V  0xFF
+#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S  6
+/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: For SPI0  In the spi sram mode cache read sram for user define command.*/
+#define SPI_MEM_CACHE_SRAM_USR_RCMD  (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_M  (BIT(5))
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_V  0x1
+#define SPI_MEM_CACHE_SRAM_USR_RCMD_S  5
+/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: For SPI0  In the spi sram mode  it is the enable bit of dummy
+ phase for read operations.*/
+#define SPI_MEM_USR_RD_SRAM_DUMMY  (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_M  (BIT(4))
+#define SPI_MEM_USR_RD_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_RD_SRAM_DUMMY_S  4
+/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: For SPI0  In the spi sram mode  it is the enable bit of dummy
+ phase for write operations.*/
+#define SPI_MEM_USR_WR_SRAM_DUMMY  (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_M  (BIT(3))
+#define SPI_MEM_USR_WR_SRAM_DUMMY_V  0x1
+#define SPI_MEM_USR_WR_SRAM_DUMMY_S  3
+/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: For SPI0  In the spi sram mode  spi quad I/O mode enable  1: enable  0:disable*/
+#define SPI_MEM_USR_SRAM_QIO  (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_M  (BIT(2))
+#define SPI_MEM_USR_SRAM_QIO_V  0x1
+#define SPI_MEM_USR_SRAM_QIO_S  2
+/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For SPI0  In the spi sram mode  spi dual I/O mode enable  1: enable  0:disable*/
+#define SPI_MEM_USR_SRAM_DIO  (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_M  (BIT(1))
+#define SPI_MEM_USR_SRAM_DIO_V  0x1
+#define SPI_MEM_USR_SRAM_DIO_S  1
+/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: For SPI0  In the spi sram mode  cache read flash with 4 bytes
+ command  1: enable  0:disable.*/
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE  (BIT(0))
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M  (BIT(0))
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V  0x1
+#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S  0
+
+#define SPI_MEM_SRAM_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x044)
+/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: For SPI0 sram  cmd phase apply 4 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_qio.*/
+#define SPI_MEM_SCMD_QUAD  (BIT(17))
+#define SPI_MEM_SCMD_QUAD_M  (BIT(17))
+#define SPI_MEM_SCMD_QUAD_V  0x1
+#define SPI_MEM_SCMD_QUAD_S  17
+/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: For SPI0 sram  address phase apply 4 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_qio.*/
+#define SPI_MEM_SADDR_QUAD  (BIT(16))
+#define SPI_MEM_SADDR_QUAD_M  (BIT(16))
+#define SPI_MEM_SADDR_QUAD_V  0x1
+#define SPI_MEM_SADDR_QUAD_S  16
+/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: For SPI0 sram  dout phase apply 4 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_qio.*/
+#define SPI_MEM_SDOUT_QUAD  (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_M  (BIT(15))
+#define SPI_MEM_SDOUT_QUAD_V  0x1
+#define SPI_MEM_SDOUT_QUAD_S  15
+/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: For SPI0 sram  din phase apply 4 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_qio.*/
+#define SPI_MEM_SDIN_QUAD  (BIT(14))
+#define SPI_MEM_SDIN_QUAD_M  (BIT(14))
+#define SPI_MEM_SDIN_QUAD_V  0x1
+#define SPI_MEM_SDIN_QUAD_S  14
+/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: For SPI0 sram  cmd phase apply 2 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_dio.*/
+#define SPI_MEM_SCMD_DUAL  (BIT(13))
+#define SPI_MEM_SCMD_DUAL_M  (BIT(13))
+#define SPI_MEM_SCMD_DUAL_V  0x1
+#define SPI_MEM_SCMD_DUAL_S  13
+/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: For SPI0 sram  address phase apply 2 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_dio.*/
+#define SPI_MEM_SADDR_DUAL  (BIT(12))
+#define SPI_MEM_SADDR_DUAL_M  (BIT(12))
+#define SPI_MEM_SADDR_DUAL_V  0x1
+#define SPI_MEM_SADDR_DUAL_S  12
+/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: For SPI0 sram  dout phase apply 2 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_dio.*/
+#define SPI_MEM_SDOUT_DUAL  (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_M  (BIT(11))
+#define SPI_MEM_SDOUT_DUAL_V  0x1
+#define SPI_MEM_SDOUT_DUAL_S  11
+/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: For SPI0 sram  din phase apply 2 signals. 1: enable 0: disable.
+ The bit is the same with spi_mem_usr_sram_dio.*/
+#define SPI_MEM_SDIN_DUAL  (BIT(10))
+#define SPI_MEM_SDIN_DUAL_M  (BIT(10))
+#define SPI_MEM_SDIN_DUAL_V  0x1
+#define SPI_MEM_SDIN_DUAL_S  10
+/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */
+/*description: Mode bits in the psram fast read mode  it is combined with spi_mem_fastrd_mode
+ bit.*/
+#define SPI_MEM_SWB_MODE  0x000000FF
+#define SPI_MEM_SWB_MODE_M  ((SPI_MEM_SWB_MODE_V)<<(SPI_MEM_SWB_MODE_S))
+#define SPI_MEM_SWB_MODE_V  0xFF
+#define SPI_MEM_SWB_MODE_S  2
+/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+#define SPI_MEM_SCLK_MODE  0x00000003
+#define SPI_MEM_SCLK_MODE_M  ((SPI_MEM_SCLK_MODE_V)<<(SPI_MEM_SCLK_MODE_S))
+#define SPI_MEM_SCLK_MODE_V  0x3
+#define SPI_MEM_SCLK_MODE_S  0
+
+#define SPI_MEM_SRAM_DRD_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x048)
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the length in bits of
+ command phase for sram. The register value shall be (bit_num-1).*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN  0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the read command value
+ of command phase for sram.*/
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE  0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_DWR_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x04C)
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the in bits of command
+ phase  for sram. The register value shall be (bit_num-1).*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN  0x0000000F
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V  0xF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S  28
+/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
+/*description: For SPI0 When cache mode is enable it is the write command value
+ of command phase for sram.*/
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE  0x0000FFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M  ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V)<<(SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S))
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V  0xFFFF
+#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S  0
+
+#define SPI_MEM_SRAM_CLK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x050)
+/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: For SPI0 sram interface  1: spi_mem_clk is eqaul to system 0:
+ spi_mem_clk is divided from system clock.*/
+#define SPI_MEM_SCLK_EQU_SYSCLK  (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_MEM_SCLK_EQU_SYSCLK_V  0x1
+#define SPI_MEM_SCLK_EQU_SYSCLK_S  31
+/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */
+/*description: For SPI0 sram interface  it is the divider of spi_mem_clk. So
+ spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+#define SPI_MEM_SCLKCNT_N  0x000000FF
+#define SPI_MEM_SCLKCNT_N_M  ((SPI_MEM_SCLKCNT_N_V)<<(SPI_MEM_SCLKCNT_N_S))
+#define SPI_MEM_SCLKCNT_N_V  0xFF
+#define SPI_MEM_SCLKCNT_N_S  16
+/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
+/*description: For SPI0 sram interface  it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
+#define SPI_MEM_SCLKCNT_H  0x000000FF
+#define SPI_MEM_SCLKCNT_H_M  ((SPI_MEM_SCLKCNT_H_V)<<(SPI_MEM_SCLKCNT_H_S))
+#define SPI_MEM_SCLKCNT_H_V  0xFF
+#define SPI_MEM_SCLKCNT_H_S  8
+/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */
+/*description: For SPI0 sram interface  it must be equal to spi_mem_clkcnt_N.*/
+#define SPI_MEM_SCLKCNT_L  0x000000FF
+#define SPI_MEM_SCLKCNT_L_M  ((SPI_MEM_SCLKCNT_L_V)<<(SPI_MEM_SCLKCNT_L_S))
+#define SPI_MEM_SCLKCNT_L_V  0xFF
+#define SPI_MEM_SCLKCNT_L_S  0
+
+#define SPI_MEM_FSM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x054)
+/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The status of spi state machine. 0: idle state  1: preparation
+ state  2: send command state  3: send data state  4: red data state  5:write data state  6: wait state  7: done state.*/
+#define SPI_MEM_ST  0x00000007
+#define SPI_MEM_ST_M  ((SPI_MEM_ST_V)<<(SPI_MEM_ST_S))
+#define SPI_MEM_ST_V  0x7
+#define SPI_MEM_ST_S  0
+
+#define SPI_MEM_HOLD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x058)
+/* SPI_MEM_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'd3 ; */
+/*description: This register is for two SPI masters to share the same cs clock
+ and data signals. The bits of one SPI are set  if the other SPI is busy  the SPI will be hold. 1(3): hold at  idle  phase 2: hold at  prepare  phase.*/
+#define SPI_MEM_HOLD_ENA  0x00000003
+#define SPI_MEM_HOLD_ENA_M  ((SPI_MEM_HOLD_ENA_V)<<(SPI_MEM_HOLD_ENA_S))
+#define SPI_MEM_HOLD_ENA_V  0x3
+#define SPI_MEM_HOLD_ENA_S  0
+
+#define SPI_MEM_DMA_CONF_REG(i)          (REG_SPI_MEM_BASE(i) + 0x05C)
+/* SPI_MEM_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: spi dma continue tx/rx data.*/
+#define SPI_MEM_DMA_CONTINUE  (BIT(16))
+#define SPI_MEM_DMA_CONTINUE_M  (BIT(16))
+#define SPI_MEM_DMA_CONTINUE_V  0x1
+#define SPI_MEM_DMA_CONTINUE_S  16
+/* SPI_MEM_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: spi dma write data stop when in continue tx/rx mode.*/
+#define SPI_MEM_DMA_TX_STOP  (BIT(15))
+#define SPI_MEM_DMA_TX_STOP_M  (BIT(15))
+#define SPI_MEM_DMA_TX_STOP_V  0x1
+#define SPI_MEM_DMA_TX_STOP_S  15
+/* SPI_MEM_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: spi dma read data stop  when in continue tx/rx mode.*/
+#define SPI_MEM_DMA_RX_STOP  (BIT(14))
+#define SPI_MEM_DMA_RX_STOP_M  (BIT(14))
+#define SPI_MEM_DMA_RX_STOP_V  0x1
+#define SPI_MEM_DMA_RX_STOP_S  14
+/* SPI_MEM_DMA_MEM_TRANS_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: reserved*/
+#define SPI_MEM_DMA_MEM_TRANS_ENA  (BIT(13))
+#define SPI_MEM_DMA_MEM_TRANS_ENA_M  (BIT(13))
+#define SPI_MEM_DMA_MEM_TRANS_ENA_V  0x1
+#define SPI_MEM_DMA_MEM_TRANS_ENA_S  13
+/* SPI_MEM_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: spi dma read data from memory in burst mode.*/
+#define SPI_MEM_OUT_DATA_BURST_EN  (BIT(12))
+#define SPI_MEM_OUT_DATA_BURST_EN_M  (BIT(12))
+#define SPI_MEM_OUT_DATA_BURST_EN_V  0x1
+#define SPI_MEM_OUT_DATA_BURST_EN_S  12
+/* SPI_MEM_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: read descriptor use burst mode when write data to memory.*/
+#define SPI_MEM_INDSCR_BURST_EN  (BIT(11))
+#define SPI_MEM_INDSCR_BURST_EN_M  (BIT(11))
+#define SPI_MEM_INDSCR_BURST_EN_V  0x1
+#define SPI_MEM_INDSCR_BURST_EN_S  11
+/* SPI_MEM_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: read descriptor use burst mode when read data for memory.*/
+#define SPI_MEM_OUTDSCR_BURST_EN  (BIT(10))
+#define SPI_MEM_OUTDSCR_BURST_EN_M  (BIT(10))
+#define SPI_MEM_OUTDSCR_BURST_EN_V  0x1
+#define SPI_MEM_OUTDSCR_BURST_EN_S  10
+/* SPI_MEM_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: out eof flag generation mode . 1: when dma pop all data from
+ fifo  0:when ahb push all data to fifo.*/
+#define SPI_MEM_OUT_EOF_MODE  (BIT(9))
+#define SPI_MEM_OUT_EOF_MODE_M  (BIT(9))
+#define SPI_MEM_OUT_EOF_MODE_V  0x1
+#define SPI_MEM_OUT_EOF_MODE_S  9
+/* SPI_MEM_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: when the bit is set  DMA continue to use the next inlink node
+ when the length of inlink is 0.*/
+#define SPI_MEM_OUT_AUTO_WRBACK  (BIT(8))
+#define SPI_MEM_OUT_AUTO_WRBACK_M  (BIT(8))
+#define SPI_MEM_OUT_AUTO_WRBACK_V  0x1
+#define SPI_MEM_OUT_AUTO_WRBACK_S  8
+/* SPI_MEM_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set bit to test out link.*/
+#define SPI_MEM_OUT_LOOP_TEST  (BIT(7))
+#define SPI_MEM_OUT_LOOP_TEST_M  (BIT(7))
+#define SPI_MEM_OUT_LOOP_TEST_V  0x1
+#define SPI_MEM_OUT_LOOP_TEST_S  7
+/* SPI_MEM_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set bit to test in link.*/
+#define SPI_MEM_IN_LOOP_TEST  (BIT(6))
+#define SPI_MEM_IN_LOOP_TEST_M  (BIT(6))
+#define SPI_MEM_IN_LOOP_TEST_V  0x1
+#define SPI_MEM_IN_LOOP_TEST_S  6
+/* SPI_MEM_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Reset spi dma ahb master.*/
+#define SPI_MEM_AHBM_RST  (BIT(5))
+#define SPI_MEM_AHBM_RST_M  (BIT(5))
+#define SPI_MEM_AHBM_RST_V  0x1
+#define SPI_MEM_AHBM_RST_S  5
+/* SPI_MEM_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Reset spi dma ahb master fifo pointer.*/
+#define SPI_MEM_AHBM_FIFO_RST  (BIT(4))
+#define SPI_MEM_AHBM_FIFO_RST_M  (BIT(4))
+#define SPI_MEM_AHBM_FIFO_RST_V  0x1
+#define SPI_MEM_AHBM_FIFO_RST_S  4
+/* SPI_MEM_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/
+#define SPI_MEM_OUT_RST  (BIT(3))
+#define SPI_MEM_OUT_RST_M  (BIT(3))
+#define SPI_MEM_OUT_RST_V  0x1
+#define SPI_MEM_OUT_RST_S  3
+/* SPI_MEM_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/
+#define SPI_MEM_IN_RST  (BIT(2))
+#define SPI_MEM_IN_RST_M  (BIT(2))
+#define SPI_MEM_IN_RST_V  0x1
+#define SPI_MEM_IN_RST_S  2
+/* SPI_MEM_DMA_TX_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: spi dma tx data enable.*/
+#define SPI_MEM_DMA_TX_ENA  (BIT(1))
+#define SPI_MEM_DMA_TX_ENA_M  (BIT(1))
+#define SPI_MEM_DMA_TX_ENA_V  0x1
+#define SPI_MEM_DMA_TX_ENA_S  1
+/* SPI_MEM_DMA_RX_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: spi dma rx data enable.*/
+#define SPI_MEM_DMA_RX_ENA  (BIT(0))
+#define SPI_MEM_DMA_RX_ENA_M  (BIT(0))
+#define SPI_MEM_DMA_RX_ENA_V  0x1
+#define SPI_MEM_DMA_RX_ENA_S  0
+
+#define SPI_MEM_DMA_OUT_LINK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x060)
+/* SPI_MEM_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set the bit to mount on new outlink descriptors.*/
+#define SPI_MEM_OUTLINK_RESTART  (BIT(30))
+#define SPI_MEM_OUTLINK_RESTART_M  (BIT(30))
+#define SPI_MEM_OUTLINK_RESTART_V  0x1
+#define SPI_MEM_OUTLINK_RESTART_S  30
+/* SPI_MEM_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set the bit to start to use outlink descriptor.*/
+#define SPI_MEM_OUTLINK_START  (BIT(29))
+#define SPI_MEM_OUTLINK_START_M  (BIT(29))
+#define SPI_MEM_OUTLINK_START_V  0x1
+#define SPI_MEM_OUTLINK_START_S  29
+/* SPI_MEM_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set the bit to stop to use outlink descriptor.*/
+#define SPI_MEM_OUTLINK_STOP  (BIT(28))
+#define SPI_MEM_OUTLINK_STOP_M  (BIT(28))
+#define SPI_MEM_OUTLINK_STOP_V  0x1
+#define SPI_MEM_OUTLINK_STOP_S  28
+/* SPI_MEM_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of the first outlink descriptor.*/
+#define SPI_MEM_OUTLINK_ADDR  0x000FFFFF
+#define SPI_MEM_OUTLINK_ADDR_M  ((SPI_MEM_OUTLINK_ADDR_V)<<(SPI_MEM_OUTLINK_ADDR_S))
+#define SPI_MEM_OUTLINK_ADDR_V  0xFFFFF
+#define SPI_MEM_OUTLINK_ADDR_S  0
+
+#define SPI_MEM_DMA_IN_LINK_REG(i)          (REG_SPI_MEM_BASE(i) + 0x064)
+/* SPI_MEM_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set the bit to mount on new inlink descriptors.*/
+#define SPI_MEM_INLINK_RESTART  (BIT(30))
+#define SPI_MEM_INLINK_RESTART_M  (BIT(30))
+#define SPI_MEM_INLINK_RESTART_V  0x1
+#define SPI_MEM_INLINK_RESTART_S  30
+/* SPI_MEM_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set the bit to start to use inlink descriptor.*/
+#define SPI_MEM_INLINK_START  (BIT(29))
+#define SPI_MEM_INLINK_START_M  (BIT(29))
+#define SPI_MEM_INLINK_START_V  0x1
+#define SPI_MEM_INLINK_START_S  29
+/* SPI_MEM_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set the bit to stop to use inlink descriptor.*/
+#define SPI_MEM_INLINK_STOP  (BIT(28))
+#define SPI_MEM_INLINK_STOP_M  (BIT(28))
+#define SPI_MEM_INLINK_STOP_V  0x1
+#define SPI_MEM_INLINK_STOP_S  28
+/* SPI_MEM_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: when the bit is set  the inlink descriptor returns to the first
+ link node when a packet is error.*/
+#define SPI_MEM_INLINK_AUTO_RET  (BIT(20))
+#define SPI_MEM_INLINK_AUTO_RET_M  (BIT(20))
+#define SPI_MEM_INLINK_AUTO_RET_V  0x1
+#define SPI_MEM_INLINK_AUTO_RET_S  20
+/* SPI_MEM_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of the first inlink descriptor.*/
+#define SPI_MEM_INLINK_ADDR  0x000FFFFF
+#define SPI_MEM_INLINK_ADDR_M  ((SPI_MEM_INLINK_ADDR_V)<<(SPI_MEM_INLINK_ADDR_S))
+#define SPI_MEM_INLINK_ADDR_V  0xFFFFF
+#define SPI_MEM_INLINK_ADDR_S  0
+
+#define SPI_MEM_DMA_INT_ENA_REG(i)          (REG_SPI_MEM_BASE(i) + 0x068)
+/* SPI_MEM_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for sending all the packets to host done.*/
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA_M  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA_V  0x1
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ENA_S  8
+/* SPI_MEM_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for sending a packet to host done.*/
+#define SPI_MEM_OUT_EOF_INT_ENA  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_ENA_M  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_ENA_V  0x1
+#define SPI_MEM_OUT_EOF_INT_ENA_S  7
+/* SPI_MEM_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for completing usage of a outlink descriptor .*/
+#define SPI_MEM_OUT_DONE_INT_ENA  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_ENA_M  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_ENA_V  0x1
+#define SPI_MEM_OUT_DONE_INT_ENA_S  6
+/* SPI_MEM_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for completing receiving all the packets from host.*/
+#define SPI_MEM_IN_SUC_EOF_INT_ENA  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_ENA_M  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_ENA_V  0x1
+#define SPI_MEM_IN_SUC_EOF_INT_ENA_S  5
+/* SPI_MEM_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for receiving error.*/
+#define SPI_MEM_IN_ERR_EOF_INT_ENA  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_ENA_M  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_ENA_V  0x1
+#define SPI_MEM_IN_ERR_EOF_INT_ENA_S  4
+/* SPI_MEM_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for completing usage of a inlink descriptor.*/
+#define SPI_MEM_IN_DONE_INT_ENA  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_ENA_M  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_ENA_V  0x1
+#define SPI_MEM_IN_DONE_INT_ENA_S  3
+/* SPI_MEM_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for inlink descriptor error.*/
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA_M  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA_V  0x1
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ENA_S  2
+/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for outlink descriptor error.*/
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA_M  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA_V  0x1
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ENA_S  1
+/* SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for lack of enough inlink descriptors.*/
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA_M  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA_V  0x1
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ENA_S  0
+
+#define SPI_MEM_DMA_INT_RAW_REG(i)          (REG_SPI_MEM_BASE(i) + 0x06C)
+/* SPI_MEM_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for sending all the packets to host done.*/
+#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW_M  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW_V  0x1
+#define SPI_MEM_OUT_TOTAL_EOF_INT_RAW_S  8
+/* SPI_MEM_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for sending a packet to host done.*/
+#define SPI_MEM_OUT_EOF_INT_RAW  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_RAW_M  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_RAW_V  0x1
+#define SPI_MEM_OUT_EOF_INT_RAW_S  7
+/* SPI_MEM_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for completing usage of a outlink descriptor.*/
+#define SPI_MEM_OUT_DONE_INT_RAW  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_RAW_M  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_RAW_V  0x1
+#define SPI_MEM_OUT_DONE_INT_RAW_S  6
+/* SPI_MEM_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for completing receiving all the packets from host.*/
+#define SPI_MEM_IN_SUC_EOF_INT_RAW  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_RAW_M  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_RAW_V  0x1
+#define SPI_MEM_IN_SUC_EOF_INT_RAW_S  5
+/* SPI_MEM_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for receiving error.*/
+#define SPI_MEM_IN_ERR_EOF_INT_RAW  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_RAW_M  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_RAW_V  0x1
+#define SPI_MEM_IN_ERR_EOF_INT_RAW_S  4
+/* SPI_MEM_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for completing usage of a inlink descriptor.*/
+#define SPI_MEM_IN_DONE_INT_RAW  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_RAW_M  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_RAW_V  0x1
+#define SPI_MEM_IN_DONE_INT_RAW_S  3
+/* SPI_MEM_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for inlink descriptor error.*/
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW_M  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW_V  0x1
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_RAW_S  2
+/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for outlink descriptor error.*/
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW_M  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW_V  0x1
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_RAW_S  1
+/* SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for lack of enough inlink descriptors.*/
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW_M  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW_V  0x1
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_RAW_S  0
+
+#define SPI_MEM_DMA_INT_ST_REG(i)          (REG_SPI_MEM_BASE(i) + 0x070)
+/* SPI_MEM_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for sending all the packets to host done.*/
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ST  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ST_M  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ST_V  0x1
+#define SPI_MEM_OUT_TOTAL_EOF_INT_ST_S  8
+/* SPI_MEM_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for sending a packet to host done.*/
+#define SPI_MEM_OUT_EOF_INT_ST  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_ST_M  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_ST_V  0x1
+#define SPI_MEM_OUT_EOF_INT_ST_S  7
+/* SPI_MEM_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for completing usage of a outlink descriptor.*/
+#define SPI_MEM_OUT_DONE_INT_ST  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_ST_M  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_ST_V  0x1
+#define SPI_MEM_OUT_DONE_INT_ST_S  6
+/* SPI_MEM_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for completing receiving all the packets from host.*/
+#define SPI_MEM_IN_SUC_EOF_INT_ST  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_ST_M  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_ST_V  0x1
+#define SPI_MEM_IN_SUC_EOF_INT_ST_S  5
+/* SPI_MEM_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for receiving error.*/
+#define SPI_MEM_IN_ERR_EOF_INT_ST  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_ST_M  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_ST_V  0x1
+#define SPI_MEM_IN_ERR_EOF_INT_ST_S  4
+/* SPI_MEM_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for completing usage of a inlink descriptor.*/
+#define SPI_MEM_IN_DONE_INT_ST  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_ST_M  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_ST_V  0x1
+#define SPI_MEM_IN_DONE_INT_ST_S  3
+/* SPI_MEM_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for inlink descriptor error.*/
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST_M  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST_V  0x1
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_ST_S  2
+/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for outlink descriptor error.*/
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST_M  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST_V  0x1
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_ST_S  1
+/* SPI_MEM_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for lack of enough inlink descriptors.*/
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST_M  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST_V  0x1
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_ST_S  0
+
+#define SPI_MEM_DMA_INT_CLR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x074)
+/* SPI_MEM_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for sending all the packets to host done.*/
+#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR_M  (BIT(8))
+#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR_V  0x1
+#define SPI_MEM_OUT_TOTAL_EOF_INT_CLR_S  8
+/* SPI_MEM_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for sending a packet to host done.*/
+#define SPI_MEM_OUT_EOF_INT_CLR  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_CLR_M  (BIT(7))
+#define SPI_MEM_OUT_EOF_INT_CLR_V  0x1
+#define SPI_MEM_OUT_EOF_INT_CLR_S  7
+/* SPI_MEM_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for completing usage of a outlink descriptor.*/
+#define SPI_MEM_OUT_DONE_INT_CLR  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_CLR_M  (BIT(6))
+#define SPI_MEM_OUT_DONE_INT_CLR_V  0x1
+#define SPI_MEM_OUT_DONE_INT_CLR_S  6
+/* SPI_MEM_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for completing receiving all the packets from host.*/
+#define SPI_MEM_IN_SUC_EOF_INT_CLR  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_CLR_M  (BIT(5))
+#define SPI_MEM_IN_SUC_EOF_INT_CLR_V  0x1
+#define SPI_MEM_IN_SUC_EOF_INT_CLR_S  5
+/* SPI_MEM_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for receiving error.*/
+#define SPI_MEM_IN_ERR_EOF_INT_CLR  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_CLR_M  (BIT(4))
+#define SPI_MEM_IN_ERR_EOF_INT_CLR_V  0x1
+#define SPI_MEM_IN_ERR_EOF_INT_CLR_S  4
+/* SPI_MEM_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for completing usage of a inlink descriptor.*/
+#define SPI_MEM_IN_DONE_INT_CLR  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_CLR_M  (BIT(3))
+#define SPI_MEM_IN_DONE_INT_CLR_V  0x1
+#define SPI_MEM_IN_DONE_INT_CLR_S  3
+/* SPI_MEM_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for inlink descriptor error.*/
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR_M  (BIT(2))
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR_V  0x1
+#define SPI_MEM_INLINK_DSCR_ERROR_INT_CLR_S  2
+/* SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for outlink descriptor error.*/
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR_M  (BIT(1))
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR_V  0x1
+#define SPI_MEM_OUTLINK_DSCR_ERROR_INT_CLR_S  1
+/* SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for lack of enough inlink descriptors.*/
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR_M  (BIT(0))
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR_V  0x1
+#define SPI_MEM_INLINK_DSCR_EMPTY_INT_CLR_S  0
+
+#define SPI_MEM_IN_ERR_EOF_DES_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x078)
+/* SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The inlink descriptor address when spi dma produce receiving error.*/
+#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR  0xFFFFFFFF
+#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_M  ((SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_S))
+#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SPI_MEM_DMA_IN_ERR_EOF_DES_ADDR_S  0
+
+#define SPI_MEM_IN_SUC_EOF_DES_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x07C)
+/* SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/
+#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR  0xFFFFFFFF
+#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_M  ((SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_S))
+#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SPI_MEM_DMA_IN_SUC_EOF_DES_ADDR_S  0
+
+#define SPI_MEM_INLINK_DSCR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x080)
+/* SPI_MEM_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in descriptor pointer.*/
+#define SPI_MEM_DMA_INLINK_DSCR  0xFFFFFFFF
+#define SPI_MEM_DMA_INLINK_DSCR_M  ((SPI_MEM_DMA_INLINK_DSCR_V)<<(SPI_MEM_DMA_INLINK_DSCR_S))
+#define SPI_MEM_DMA_INLINK_DSCR_V  0xFFFFFFFF
+#define SPI_MEM_DMA_INLINK_DSCR_S  0
+
+#define SPI_MEM_INLINK_DSCR_BF0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x084)
+/* SPI_MEM_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of next in descriptor pointer.*/
+#define SPI_MEM_DMA_INLINK_DSCR_BF0  0xFFFFFFFF
+#define SPI_MEM_DMA_INLINK_DSCR_BF0_M  ((SPI_MEM_DMA_INLINK_DSCR_BF0_V)<<(SPI_MEM_DMA_INLINK_DSCR_BF0_S))
+#define SPI_MEM_DMA_INLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SPI_MEM_DMA_INLINK_DSCR_BF0_S  0
+
+#define SPI_MEM_INLINK_DSCR_BF1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x088)
+/* SPI_MEM_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in descriptor data buffer pointer.*/
+#define SPI_MEM_DMA_INLINK_DSCR_BF1  0xFFFFFFFF
+#define SPI_MEM_DMA_INLINK_DSCR_BF1_M  ((SPI_MEM_DMA_INLINK_DSCR_BF1_V)<<(SPI_MEM_DMA_INLINK_DSCR_BF1_S))
+#define SPI_MEM_DMA_INLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SPI_MEM_DMA_INLINK_DSCR_BF1_S  0
+
+#define SPI_MEM_OUT_EOF_BFR_DES_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x08C)
+/* SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of buffer relative to the outlink descriptor that produce eof.*/
+#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR  0xFFFFFFFF
+#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_M  ((SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_S))
+#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
+#define SPI_MEM_DMA_OUT_EOF_BFR_DES_ADDR_S  0
+
+#define SPI_MEM_OUT_EOF_DES_ADDR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x090)
+/* SPI_MEM_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The last outlink descriptor address when spi dma produce to_eof.*/
+#define SPI_MEM_DMA_OUT_EOF_DES_ADDR  0xFFFFFFFF
+#define SPI_MEM_DMA_OUT_EOF_DES_ADDR_M  ((SPI_MEM_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_MEM_DMA_OUT_EOF_DES_ADDR_S))
+#define SPI_MEM_DMA_OUT_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SPI_MEM_DMA_OUT_EOF_DES_ADDR_S  0
+
+#define SPI_MEM_OUTLINK_DSCR_REG(i)          (REG_SPI_MEM_BASE(i) + 0x094)
+/* SPI_MEM_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out descriptor pointer.*/
+#define SPI_MEM_DMA_OUTLINK_DSCR  0xFFFFFFFF
+#define SPI_MEM_DMA_OUTLINK_DSCR_M  ((SPI_MEM_DMA_OUTLINK_DSCR_V)<<(SPI_MEM_DMA_OUTLINK_DSCR_S))
+#define SPI_MEM_DMA_OUTLINK_DSCR_V  0xFFFFFFFF
+#define SPI_MEM_DMA_OUTLINK_DSCR_S  0
+
+#define SPI_MEM_OUTLINK_DSCR_BF0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x098)
+/* SPI_MEM_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of next out descriptor pointer.*/
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF0  0xFFFFFFFF
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF0_M  ((SPI_MEM_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_MEM_DMA_OUTLINK_DSCR_BF0_S))
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF0_S  0
+
+#define SPI_MEM_OUTLINK_DSCR_BF1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x09C)
+/* SPI_MEM_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out descriptor data buffer pointer.*/
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF1  0xFFFFFFFF
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF1_M  ((SPI_MEM_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_MEM_DMA_OUTLINK_DSCR_BF1_S))
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SPI_MEM_DMA_OUTLINK_DSCR_BF1_S  0
+
+#define SPI_MEM_DMA_OUTSTATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A0)
+/* SPI_MEM_DMA_OUTFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: SPI dma outfifo is empty.*/
+#define SPI_MEM_DMA_OUTFIFO_EMPTY  (BIT(31))
+#define SPI_MEM_DMA_OUTFIFO_EMPTY_M  (BIT(31))
+#define SPI_MEM_DMA_OUTFIFO_EMPTY_V  0x1
+#define SPI_MEM_DMA_OUTFIFO_EMPTY_S  31
+/* SPI_MEM_DMA_OUTFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI dma outfifo is full.*/
+#define SPI_MEM_DMA_OUTFIFO_FULL  (BIT(30))
+#define SPI_MEM_DMA_OUTFIFO_FULL_M  (BIT(30))
+#define SPI_MEM_DMA_OUTFIFO_FULL_V  0x1
+#define SPI_MEM_DMA_OUTFIFO_FULL_S  30
+/* SPI_MEM_DMA_OUTFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */
+/*description: The remains of SPI dma outfifo data.*/
+#define SPI_MEM_DMA_OUTFIFO_CNT  0x0000007F
+#define SPI_MEM_DMA_OUTFIFO_CNT_M  ((SPI_MEM_DMA_OUTFIFO_CNT_V)<<(SPI_MEM_DMA_OUTFIFO_CNT_S))
+#define SPI_MEM_DMA_OUTFIFO_CNT_V  0x7F
+#define SPI_MEM_DMA_OUTFIFO_CNT_S  23
+/* SPI_MEM_DMA_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: SPI dma out data state.*/
+#define SPI_MEM_DMA_OUT_STATE  0x00000007
+#define SPI_MEM_DMA_OUT_STATE_M  ((SPI_MEM_DMA_OUT_STATE_V)<<(SPI_MEM_DMA_OUT_STATE_S))
+#define SPI_MEM_DMA_OUT_STATE_V  0x7
+#define SPI_MEM_DMA_OUT_STATE_S  20
+/* SPI_MEM_DMA_OUTDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: SPI dma out descriptor state.*/
+#define SPI_MEM_DMA_OUTDSCR_STATE  0x00000003
+#define SPI_MEM_DMA_OUTDSCR_STATE_M  ((SPI_MEM_DMA_OUTDSCR_STATE_V)<<(SPI_MEM_DMA_OUTDSCR_STATE_S))
+#define SPI_MEM_DMA_OUTDSCR_STATE_V  0x3
+#define SPI_MEM_DMA_OUTDSCR_STATE_S  18
+/* SPI_MEM_DMA_OUTDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: SPI dma out descriptor address.*/
+#define SPI_MEM_DMA_OUTDSCR_ADDR  0x0003FFFF
+#define SPI_MEM_DMA_OUTDSCR_ADDR_M  ((SPI_MEM_DMA_OUTDSCR_ADDR_V)<<(SPI_MEM_DMA_OUTDSCR_ADDR_S))
+#define SPI_MEM_DMA_OUTDSCR_ADDR_V  0x3FFFF
+#define SPI_MEM_DMA_OUTDSCR_ADDR_S  0
+
+#define SPI_MEM_DMA_INSTATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A4)
+/* SPI_MEM_DMA_INFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: SPI dma infifo is empty.*/
+#define SPI_MEM_DMA_INFIFO_EMPTY  (BIT(31))
+#define SPI_MEM_DMA_INFIFO_EMPTY_M  (BIT(31))
+#define SPI_MEM_DMA_INFIFO_EMPTY_V  0x1
+#define SPI_MEM_DMA_INFIFO_EMPTY_S  31
+/* SPI_MEM_DMA_INFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI dma infifo is full.*/
+#define SPI_MEM_DMA_INFIFO_FULL  (BIT(30))
+#define SPI_MEM_DMA_INFIFO_FULL_M  (BIT(30))
+#define SPI_MEM_DMA_INFIFO_FULL_V  0x1
+#define SPI_MEM_DMA_INFIFO_FULL_S  30
+/* SPI_MEM_DMA_INFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */
+/*description: The remains of SPI dma infifo data.*/
+#define SPI_MEM_DMA_INFIFO_CNT  0x0000007F
+#define SPI_MEM_DMA_INFIFO_CNT_M  ((SPI_MEM_DMA_INFIFO_CNT_V)<<(SPI_MEM_DMA_INFIFO_CNT_S))
+#define SPI_MEM_DMA_INFIFO_CNT_V  0x7F
+#define SPI_MEM_DMA_INFIFO_CNT_S  23
+/* SPI_MEM_DMA_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: SPI dma in data state.*/
+#define SPI_MEM_DMA_IN_STATE  0x00000007
+#define SPI_MEM_DMA_IN_STATE_M  ((SPI_MEM_DMA_IN_STATE_V)<<(SPI_MEM_DMA_IN_STATE_S))
+#define SPI_MEM_DMA_IN_STATE_V  0x7
+#define SPI_MEM_DMA_IN_STATE_S  20
+/* SPI_MEM_DMA_INDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: SPI dma in descriptor state.*/
+#define SPI_MEM_DMA_INDSCR_STATE  0x00000003
+#define SPI_MEM_DMA_INDSCR_STATE_M  ((SPI_MEM_DMA_INDSCR_STATE_V)<<(SPI_MEM_DMA_INDSCR_STATE_S))
+#define SPI_MEM_DMA_INDSCR_STATE_V  0x3
+#define SPI_MEM_DMA_INDSCR_STATE_S  18
+/* SPI_MEM_DMA_INDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: SPI dma in descriptor address.*/
+#define SPI_MEM_DMA_INDSCR_ADDR  0x0003FFFF
+#define SPI_MEM_DMA_INDSCR_ADDR_M  ((SPI_MEM_DMA_INDSCR_ADDR_V)<<(SPI_MEM_DMA_INDSCR_ADDR_S))
+#define SPI_MEM_DMA_INDSCR_ADDR_V  0x3FFFF
+#define SPI_MEM_DMA_INDSCR_ADDR_S  0
+
+#define SPI_MEM_W0_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0A8)
+/* SPI_MEM_BUF0 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF0  0xFFFFFFFF
+#define SPI_MEM_BUF0_M  ((SPI_MEM_BUF0_V)<<(SPI_MEM_BUF0_S))
+#define SPI_MEM_BUF0_V  0xFFFFFFFF
+#define SPI_MEM_BUF0_S  0
+
+#define SPI_MEM_W1_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0AC)
+/* SPI_MEM_BUF1 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF1  0xFFFFFFFF
+#define SPI_MEM_BUF1_M  ((SPI_MEM_BUF1_V)<<(SPI_MEM_BUF1_S))
+#define SPI_MEM_BUF1_V  0xFFFFFFFF
+#define SPI_MEM_BUF1_S  0
+
+#define SPI_MEM_W2_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B0)
+/* SPI_MEM_BUF2 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF2  0xFFFFFFFF
+#define SPI_MEM_BUF2_M  ((SPI_MEM_BUF2_V)<<(SPI_MEM_BUF2_S))
+#define SPI_MEM_BUF2_V  0xFFFFFFFF
+#define SPI_MEM_BUF2_S  0
+
+#define SPI_MEM_W3_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B4)
+/* SPI_MEM_BUF3 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF3  0xFFFFFFFF
+#define SPI_MEM_BUF3_M  ((SPI_MEM_BUF3_V)<<(SPI_MEM_BUF3_S))
+#define SPI_MEM_BUF3_V  0xFFFFFFFF
+#define SPI_MEM_BUF3_S  0
+
+#define SPI_MEM_W4_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0B8)
+/* SPI_MEM_BUF4 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF4  0xFFFFFFFF
+#define SPI_MEM_BUF4_M  ((SPI_MEM_BUF4_V)<<(SPI_MEM_BUF4_S))
+#define SPI_MEM_BUF4_V  0xFFFFFFFF
+#define SPI_MEM_BUF4_S  0
+
+#define SPI_MEM_W5_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0BC)
+/* SPI_MEM_BUF5 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF5  0xFFFFFFFF
+#define SPI_MEM_BUF5_M  ((SPI_MEM_BUF5_V)<<(SPI_MEM_BUF5_S))
+#define SPI_MEM_BUF5_V  0xFFFFFFFF
+#define SPI_MEM_BUF5_S  0
+
+#define SPI_MEM_W6_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C0)
+/* SPI_MEM_BUF6 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF6  0xFFFFFFFF
+#define SPI_MEM_BUF6_M  ((SPI_MEM_BUF6_V)<<(SPI_MEM_BUF6_S))
+#define SPI_MEM_BUF6_V  0xFFFFFFFF
+#define SPI_MEM_BUF6_S  0
+
+#define SPI_MEM_W7_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C4)
+/* SPI_MEM_BUF7 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF7  0xFFFFFFFF
+#define SPI_MEM_BUF7_M  ((SPI_MEM_BUF7_V)<<(SPI_MEM_BUF7_S))
+#define SPI_MEM_BUF7_V  0xFFFFFFFF
+#define SPI_MEM_BUF7_S  0
+
+#define SPI_MEM_W8_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0C8)
+/* SPI_MEM_BUF8 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF8  0xFFFFFFFF
+#define SPI_MEM_BUF8_M  ((SPI_MEM_BUF8_V)<<(SPI_MEM_BUF8_S))
+#define SPI_MEM_BUF8_V  0xFFFFFFFF
+#define SPI_MEM_BUF8_S  0
+
+#define SPI_MEM_W9_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0CC)
+/* SPI_MEM_BUF9 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF9  0xFFFFFFFF
+#define SPI_MEM_BUF9_M  ((SPI_MEM_BUF9_V)<<(SPI_MEM_BUF9_S))
+#define SPI_MEM_BUF9_V  0xFFFFFFFF
+#define SPI_MEM_BUF9_S  0
+
+#define SPI_MEM_W10_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0D0)
+/* SPI_MEM_BUF10 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF10  0xFFFFFFFF
+#define SPI_MEM_BUF10_M  ((SPI_MEM_BUF10_V)<<(SPI_MEM_BUF10_S))
+#define SPI_MEM_BUF10_V  0xFFFFFFFF
+#define SPI_MEM_BUF10_S  0
+
+#define SPI_MEM_W11_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0D4)
+/* SPI_MEM_BUF11 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF11  0xFFFFFFFF
+#define SPI_MEM_BUF11_M  ((SPI_MEM_BUF11_V)<<(SPI_MEM_BUF11_S))
+#define SPI_MEM_BUF11_V  0xFFFFFFFF
+#define SPI_MEM_BUF11_S  0
+
+#define SPI_MEM_W12_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0D8)
+/* SPI_MEM_BUF12 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF12  0xFFFFFFFF
+#define SPI_MEM_BUF12_M  ((SPI_MEM_BUF12_V)<<(SPI_MEM_BUF12_S))
+#define SPI_MEM_BUF12_V  0xFFFFFFFF
+#define SPI_MEM_BUF12_S  0
+
+#define SPI_MEM_W13_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0DC)
+/* SPI_MEM_BUF13 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF13  0xFFFFFFFF
+#define SPI_MEM_BUF13_M  ((SPI_MEM_BUF13_V)<<(SPI_MEM_BUF13_S))
+#define SPI_MEM_BUF13_V  0xFFFFFFFF
+#define SPI_MEM_BUF13_S  0
+
+#define SPI_MEM_W14_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0E0)
+/* SPI_MEM_BUF14 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF14  0xFFFFFFFF
+#define SPI_MEM_BUF14_M  ((SPI_MEM_BUF14_V)<<(SPI_MEM_BUF14_S))
+#define SPI_MEM_BUF14_V  0xFFFFFFFF
+#define SPI_MEM_BUF14_S  0
+
+#define SPI_MEM_W15_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0E4)
+/* SPI_MEM_BUF15 : SRW ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_MEM_BUF15  0xFFFFFFFF
+#define SPI_MEM_BUF15_M  ((SPI_MEM_BUF15_V)<<(SPI_MEM_BUF15_S))
+#define SPI_MEM_BUF15_V  0xFFFFFFFF
+#define SPI_MEM_BUF15_S  0
+
+#define SPI_MEM_FLASH_WAITI_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0E8)
+/* SPI_MEM_WAITI_DUMMY_CYCLELEN : R/W ;bitpos:[17:10] ;default: 8'h0 ; */
+/*description: The dummy cycle length when auto wait flash idle*/
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN  0x000000FF
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_M  ((SPI_MEM_WAITI_DUMMY_CYCLELEN_V)<<(SPI_MEM_WAITI_DUMMY_CYCLELEN_S))
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_V  0xFF
+#define SPI_MEM_WAITI_DUMMY_CYCLELEN_S  10
+/* SPI_MEM_WAITI_CMD : R/W ;bitpos:[9:2] ;default: 8'h05 ; */
+/*description: The command to auto wait idle*/
+#define SPI_MEM_WAITI_CMD  0x000000FF
+#define SPI_MEM_WAITI_CMD_M  ((SPI_MEM_WAITI_CMD_V)<<(SPI_MEM_WAITI_CMD_S))
+#define SPI_MEM_WAITI_CMD_V  0xFF
+#define SPI_MEM_WAITI_CMD_S  2
+/* SPI_MEM_WAITI_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The dummy phase enable when auto wait flash idle*/
+#define SPI_MEM_WAITI_DUMMY  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_M  (BIT(1))
+#define SPI_MEM_WAITI_DUMMY_V  0x1
+#define SPI_MEM_WAITI_DUMMY_S  1
+/* SPI_MEM_WAITI_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: auto-waiting flash idle operation when program flash or erase
+ flash. 1: enable 0: disable.*/
+#define SPI_MEM_WAITI_EN  (BIT(0))
+#define SPI_MEM_WAITI_EN_M  (BIT(0))
+#define SPI_MEM_WAITI_EN_V  0x1
+#define SPI_MEM_WAITI_EN_S  0
+
+#define SPI_MEM_FLASH_SUS_CMD_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0EC)
+/* SPI_MEM_FLASH_PES : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: program erase suspend bit  program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PES  (BIT(1))
+#define SPI_MEM_FLASH_PES_M  (BIT(1))
+#define SPI_MEM_FLASH_PES_V  0x1
+#define SPI_MEM_FLASH_PES_S  1
+/* SPI_MEM_FLASH_PER : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: program erase resume bit  program erase suspend operation will
+ be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_MEM_FLASH_PER  (BIT(0))
+#define SPI_MEM_FLASH_PER_M  (BIT(0))
+#define SPI_MEM_FLASH_PER_V  0x1
+#define SPI_MEM_FLASH_PER_S  0
+
+#define SPI_MEM_FLASH_SUS_CTRL_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0F0)
+/* SPI_MEM_FLASH_PES_COMMAND : R/W ;bitpos:[16:9] ;default: 8'h75 ; */
+/*description: Program/Erase suspend command.*/
+#define SPI_MEM_FLASH_PES_COMMAND  0x000000FF
+#define SPI_MEM_FLASH_PES_COMMAND_M  ((SPI_MEM_FLASH_PES_COMMAND_V)<<(SPI_MEM_FLASH_PES_COMMAND_S))
+#define SPI_MEM_FLASH_PES_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PES_COMMAND_S  9
+/* SPI_MEM_FLASH_PER_COMMAND : R/W ;bitpos:[8:1] ;default: 8'h7a ; */
+/*description: Program/Erase resume command.*/
+#define SPI_MEM_FLASH_PER_COMMAND  0x000000FF
+#define SPI_MEM_FLASH_PER_COMMAND_M  ((SPI_MEM_FLASH_PER_COMMAND_V)<<(SPI_MEM_FLASH_PER_COMMAND_S))
+#define SPI_MEM_FLASH_PER_COMMAND_V  0xFF
+#define SPI_MEM_FLASH_PER_COMMAND_S  1
+/* SPI_MEM_FLASH_PES_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Auto-suspending enable*/
+#define SPI_MEM_FLASH_PES_EN  (BIT(0))
+#define SPI_MEM_FLASH_PES_EN_M  (BIT(0))
+#define SPI_MEM_FLASH_PES_EN_V  0x1
+#define SPI_MEM_FLASH_PES_EN_S  0
+
+#define SPI_MEM_SUS_STATUS_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0F4)
+/* SPI_MEM_FLASH_SUS : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: The status of flash suspend  only used in SPI1.*/
+#define SPI_MEM_FLASH_SUS  (BIT(0))
+#define SPI_MEM_FLASH_SUS_M  (BIT(0))
+#define SPI_MEM_FLASH_SUS_V  0x1
+#define SPI_MEM_FLASH_SUS_S  0
+
+#define SPI_MEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0F8)
+/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: add extra dummy spi clock cycle length for spi clock calibration.*/
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN  0x00000003
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_MEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V  0x3
+#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The bit is used to enable timing auto-calibration for all reading operations.*/
+#define SPI_MEM_TIMING_CALI  (BIT(1))
+#define SPI_MEM_TIMING_CALI_M  (BIT(1))
+#define SPI_MEM_TIMING_CALI_V  0x1
+#define SPI_MEM_TIMING_CALI_S  1
+/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: The bit is used to enable timing adjust clock for all reading operations.*/
+#define SPI_MEM_TIMING_CLK_ENA  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_MEM_TIMING_CLK_ENA_V  0x1
+#define SPI_MEM_TIMING_CLK_ENA_S  0
+
+#define SPI_MEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x0FC)
+/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN3_MODE  0x00000007
+#define SPI_MEM_DIN3_MODE_M  ((SPI_MEM_DIN3_MODE_V)<<(SPI_MEM_DIN3_MODE_S))
+#define SPI_MEM_DIN3_MODE_V  0x7
+#define SPI_MEM_DIN3_MODE_S  9
+/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN2_MODE  0x00000007
+#define SPI_MEM_DIN2_MODE_M  ((SPI_MEM_DIN2_MODE_V)<<(SPI_MEM_DIN2_MODE_S))
+#define SPI_MEM_DIN2_MODE_V  0x7
+#define SPI_MEM_DIN2_MODE_S  6
+/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN1_MODE  0x00000007
+#define SPI_MEM_DIN1_MODE_M  ((SPI_MEM_DIN1_MODE_V)<<(SPI_MEM_DIN1_MODE_S))
+#define SPI_MEM_DIN1_MODE_V  0x7
+#define SPI_MEM_DIN1_MODE_S  3
+/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_MEM_DIN0_MODE  0x00000007
+#define SPI_MEM_DIN0_MODE_M  ((SPI_MEM_DIN0_MODE_V)<<(SPI_MEM_DIN0_MODE_S))
+#define SPI_MEM_DIN0_MODE_V  0x7
+#define SPI_MEM_DIN0_MODE_S  0
+
+#define SPI_MEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x100)
+/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN3_NUM  0x00000003
+#define SPI_MEM_DIN3_NUM_M  ((SPI_MEM_DIN3_NUM_V)<<(SPI_MEM_DIN3_NUM_S))
+#define SPI_MEM_DIN3_NUM_V  0x3
+#define SPI_MEM_DIN3_NUM_S  6
+/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN2_NUM  0x00000003
+#define SPI_MEM_DIN2_NUM_M  ((SPI_MEM_DIN2_NUM_V)<<(SPI_MEM_DIN2_NUM_S))
+#define SPI_MEM_DIN2_NUM_V  0x3
+#define SPI_MEM_DIN2_NUM_S  4
+/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN1_NUM  0x00000003
+#define SPI_MEM_DIN1_NUM_M  ((SPI_MEM_DIN1_NUM_V)<<(SPI_MEM_DIN1_NUM_S))
+#define SPI_MEM_DIN1_NUM_V  0x3
+#define SPI_MEM_DIN1_NUM_S  2
+/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DIN0_NUM  0x00000003
+#define SPI_MEM_DIN0_NUM_M  ((SPI_MEM_DIN0_NUM_V)<<(SPI_MEM_DIN0_NUM_S))
+#define SPI_MEM_DIN0_NUM_V  0x3
+#define SPI_MEM_DIN0_NUM_S  0
+
+#define SPI_MEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x104)
+/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT3_MODE  0x00000007
+#define SPI_MEM_DOUT3_MODE_M  ((SPI_MEM_DOUT3_MODE_V)<<(SPI_MEM_DOUT3_MODE_S))
+#define SPI_MEM_DOUT3_MODE_V  0x7
+#define SPI_MEM_DOUT3_MODE_S  9
+/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT2_MODE  0x00000007
+#define SPI_MEM_DOUT2_MODE_M  ((SPI_MEM_DOUT2_MODE_V)<<(SPI_MEM_DOUT2_MODE_S))
+#define SPI_MEM_DOUT2_MODE_V  0x7
+#define SPI_MEM_DOUT2_MODE_S  6
+/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT1_MODE  0x00000007
+#define SPI_MEM_DOUT1_MODE_M  ((SPI_MEM_DOUT1_MODE_V)<<(SPI_MEM_DOUT1_MODE_S))
+#define SPI_MEM_DOUT1_MODE_V  0x7
+#define SPI_MEM_DOUT1_MODE_S  3
+/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_MEM_DOUT0_MODE  0x00000007
+#define SPI_MEM_DOUT0_MODE_M  ((SPI_MEM_DOUT0_MODE_V)<<(SPI_MEM_DOUT0_MODE_S))
+#define SPI_MEM_DOUT0_MODE_V  0x7
+#define SPI_MEM_DOUT0_MODE_S  0
+
+#define SPI_MEM_DOUT_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x108)
+/* SPI_MEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DOUT3_NUM  0x00000003
+#define SPI_MEM_DOUT3_NUM_M  ((SPI_MEM_DOUT3_NUM_V)<<(SPI_MEM_DOUT3_NUM_S))
+#define SPI_MEM_DOUT3_NUM_V  0x3
+#define SPI_MEM_DOUT3_NUM_S  6
+/* SPI_MEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DOUT2_NUM  0x00000003
+#define SPI_MEM_DOUT2_NUM_M  ((SPI_MEM_DOUT2_NUM_V)<<(SPI_MEM_DOUT2_NUM_S))
+#define SPI_MEM_DOUT2_NUM_V  0x3
+#define SPI_MEM_DOUT2_NUM_S  4
+/* SPI_MEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DOUT1_NUM  0x00000003
+#define SPI_MEM_DOUT1_NUM_M  ((SPI_MEM_DOUT1_NUM_V)<<(SPI_MEM_DOUT1_NUM_S))
+#define SPI_MEM_DOUT1_NUM_V  0x3
+#define SPI_MEM_DOUT1_NUM_S  2
+/* SPI_MEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_MEM_DOUT0_NUM  0x00000003
+#define SPI_MEM_DOUT0_NUM_M  ((SPI_MEM_DOUT0_NUM_V)<<(SPI_MEM_DOUT0_NUM_S))
+#define SPI_MEM_DOUT0_NUM_V  0x3
+#define SPI_MEM_DOUT0_NUM_S  0
+
+#define SPI_SMEM_TIMING_CALI_REG(i)          (REG_SPI_MEM_BASE(i) + 0x10C)
+/* SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[3:2] ;default: 2'd0 ; */
+/*description: For sram  add extra dummy spi clock cycle length for spi clock calibration.*/
+#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN  0x00000003
+#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M  ((SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V)<<(SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S))
+#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V  0x3
+#define SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S  2
+/* SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: For sram  the bit is used to enable timing auto-calibration for
+ all reading operations.*/
+#define SPI_SMEM_TIMING_CALI  (BIT(1))
+#define SPI_SMEM_TIMING_CALI_M  (BIT(1))
+#define SPI_SMEM_TIMING_CALI_V  0x1
+#define SPI_SMEM_TIMING_CALI_S  1
+/* SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: For sram  the bit is used to enable timing adjust clock for all
+ reading operations.*/
+#define SPI_SMEM_TIMING_CLK_ENA  (BIT(0))
+#define SPI_SMEM_TIMING_CLK_ENA_M  (BIT(0))
+#define SPI_SMEM_TIMING_CLK_ENA_V  0x1
+#define SPI_SMEM_TIMING_CLK_ENA_S  0
+
+#define SPI_SMEM_DIN_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x110)
+/* SPI_SMEM_DIN3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_SMEM_DIN3_MODE  0x00000007
+#define SPI_SMEM_DIN3_MODE_M  ((SPI_SMEM_DIN3_MODE_V)<<(SPI_SMEM_DIN3_MODE_S))
+#define SPI_SMEM_DIN3_MODE_V  0x7
+#define SPI_SMEM_DIN3_MODE_S  9
+/* SPI_SMEM_DIN2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_SMEM_DIN2_MODE  0x00000007
+#define SPI_SMEM_DIN2_MODE_M  ((SPI_SMEM_DIN2_MODE_V)<<(SPI_SMEM_DIN2_MODE_S))
+#define SPI_SMEM_DIN2_MODE_V  0x7
+#define SPI_SMEM_DIN2_MODE_S  6
+/* SPI_SMEM_DIN1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_SMEM_DIN1_MODE  0x00000007
+#define SPI_SMEM_DIN1_MODE_M  ((SPI_SMEM_DIN1_MODE_V)<<(SPI_SMEM_DIN1_MODE_S))
+#define SPI_SMEM_DIN1_MODE_V  0x7
+#define SPI_SMEM_DIN1_MODE_S  3
+/* SPI_SMEM_DIN0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb   3: input with the posedge of clk_160  4 input with the negedge of clk_160  5: input with the spi_clk high edge   6: input with the spi_clk low edge*/
+#define SPI_SMEM_DIN0_MODE  0x00000007
+#define SPI_SMEM_DIN0_MODE_M  ((SPI_SMEM_DIN0_MODE_V)<<(SPI_SMEM_DIN0_MODE_S))
+#define SPI_SMEM_DIN0_MODE_V  0x7
+#define SPI_SMEM_DIN0_MODE_S  0
+
+#define SPI_SMEM_DIN_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x114)
+/* SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DIN3_NUM  0x00000003
+#define SPI_SMEM_DIN3_NUM_M  ((SPI_SMEM_DIN3_NUM_V)<<(SPI_SMEM_DIN3_NUM_S))
+#define SPI_SMEM_DIN3_NUM_V  0x3
+#define SPI_SMEM_DIN3_NUM_S  6
+/* SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DIN2_NUM  0x00000003
+#define SPI_SMEM_DIN2_NUM_M  ((SPI_SMEM_DIN2_NUM_V)<<(SPI_SMEM_DIN2_NUM_S))
+#define SPI_SMEM_DIN2_NUM_V  0x3
+#define SPI_SMEM_DIN2_NUM_S  4
+/* SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DIN1_NUM  0x00000003
+#define SPI_SMEM_DIN1_NUM_M  ((SPI_SMEM_DIN1_NUM_V)<<(SPI_SMEM_DIN1_NUM_S))
+#define SPI_SMEM_DIN1_NUM_V  0x3
+#define SPI_SMEM_DIN1_NUM_S  2
+/* SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DIN0_NUM  0x00000003
+#define SPI_SMEM_DIN0_NUM_M  ((SPI_SMEM_DIN0_NUM_V)<<(SPI_SMEM_DIN0_NUM_S))
+#define SPI_SMEM_DIN0_NUM_V  0x3
+#define SPI_SMEM_DIN0_NUM_S  0
+
+#define SPI_SMEM_DOUT_MODE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x118)
+/* SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[11:9] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_SMEM_DOUT3_MODE  0x00000007
+#define SPI_SMEM_DOUT3_MODE_M  ((SPI_SMEM_DOUT3_MODE_V)<<(SPI_SMEM_DOUT3_MODE_S))
+#define SPI_SMEM_DOUT3_MODE_V  0x7
+#define SPI_SMEM_DOUT3_MODE_S  9
+/* SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[8:6] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_SMEM_DOUT2_MODE  0x00000007
+#define SPI_SMEM_DOUT2_MODE_M  ((SPI_SMEM_DOUT2_MODE_V)<<(SPI_SMEM_DOUT2_MODE_S))
+#define SPI_SMEM_DOUT2_MODE_V  0x7
+#define SPI_SMEM_DOUT2_MODE_S  6
+/* SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[5:3] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_SMEM_DOUT1_MODE  0x00000007
+#define SPI_SMEM_DOUT1_MODE_M  ((SPI_SMEM_DOUT1_MODE_V)<<(SPI_SMEM_DOUT1_MODE_S))
+#define SPI_SMEM_DOUT1_MODE_V  0x7
+#define SPI_SMEM_DOUT1_MODE_S  3
+/* SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge  6: output with the spi_clk low edge*/
+#define SPI_SMEM_DOUT0_MODE  0x00000007
+#define SPI_SMEM_DOUT0_MODE_M  ((SPI_SMEM_DOUT0_MODE_V)<<(SPI_SMEM_DOUT0_MODE_S))
+#define SPI_SMEM_DOUT0_MODE_V  0x7
+#define SPI_SMEM_DOUT0_MODE_S  0
+
+#define SPI_SMEM_DOUT_NUM_REG(i)          (REG_SPI_MEM_BASE(i) + 0x11C)
+/* SPI_SMEM_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DOUT3_NUM  0x00000003
+#define SPI_SMEM_DOUT3_NUM_M  ((SPI_SMEM_DOUT3_NUM_V)<<(SPI_SMEM_DOUT3_NUM_S))
+#define SPI_SMEM_DOUT3_NUM_V  0x3
+#define SPI_SMEM_DOUT3_NUM_S  6
+/* SPI_SMEM_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DOUT2_NUM  0x00000003
+#define SPI_SMEM_DOUT2_NUM_M  ((SPI_SMEM_DOUT2_NUM_V)<<(SPI_SMEM_DOUT2_NUM_S))
+#define SPI_SMEM_DOUT2_NUM_V  0x3
+#define SPI_SMEM_DOUT2_NUM_S  4
+/* SPI_SMEM_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DOUT1_NUM  0x00000003
+#define SPI_SMEM_DOUT1_NUM_M  ((SPI_SMEM_DOUT1_NUM_V)<<(SPI_SMEM_DOUT1_NUM_S))
+#define SPI_SMEM_DOUT1_NUM_V  0x3
+#define SPI_SMEM_DOUT1_NUM_S  2
+/* SPI_SMEM_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_SMEM_DOUT0_NUM  0x00000003
+#define SPI_SMEM_DOUT0_NUM_M  ((SPI_SMEM_DOUT0_NUM_V)<<(SPI_SMEM_DOUT0_NUM_S))
+#define SPI_SMEM_DOUT0_NUM_V  0x3
+#define SPI_SMEM_DOUT0_NUM_S  0
+
+#define SPI_MEM_CLOCK_GATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x120)
+/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SPI_MEM_CLK_EN  (BIT(0))
+#define SPI_MEM_CLK_EN_M  (BIT(0))
+#define SPI_MEM_CLK_EN_V  0x1
+#define SPI_MEM_CLK_EN_S  0
+
+#define SPI_MEM_DATE_REG(i)          (REG_SPI_MEM_BASE(i) + 0x3FC)
+/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810250 ; */
+/*description: SPI register version.*/
+#define SPI_MEM_DATE  0x0FFFFFFF
+#define SPI_MEM_DATE_M  ((SPI_MEM_DATE_V)<<(SPI_MEM_DATE_S))
+#define SPI_MEM_DATE_V  0xFFFFFFF
+#define SPI_MEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_MEM_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/spi_mem_struct.h b/components/soc/esp32s2beta/include/soc/spi_mem_struct.h
new file mode 100644
index 000000000..30d47c8b9
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/spi_mem_struct.h
@@ -0,0 +1,741 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_MEM_STRUCT_H_
+#define _SOC_SPI_MEM_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reserved0: 17;                             /*reserved*/
+            uint32_t flash_pe:   1;                             /*In user mode  it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t usr:        1;                             /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_hpm:  1;                             /*Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_res:  1;                             /*This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_dp:   1;                             /*Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_ce:   1;                             /*Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_be:   1;                             /*Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_se:   1;                             /*Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_pp:   1;                             /*Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.*/
+            uint32_t flash_wrsr: 1;                             /*Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_rdsr: 1;                             /*Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_rdid: 1;                             /*Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_wrdi: 1;                             /*Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_wren: 1;                             /*Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+            uint32_t flash_read: 1;                             /*Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.*/
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;                                              /*In user mode  it is the memory address. other then the bit0-bit23 is the memory address  the bit24-bit31 are the byte length of a transfer.*/
+    union {
+        struct {
+            uint32_t reserved0:        3;                       /*reserved*/
+            uint32_t dummy_out:        1;                       /*In the dummy phase the signal level of spi is output by the spi controller.*/
+            uint32_t reserved4:        3;                       /*reserved*/
+            uint32_t fcmd_dual:        1;                       /*Apply 2 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_quad:        1;                       /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t reserved9:        1;                       /*reserved*/
+            uint32_t fcs_crc_en:       1;                       /*For SPI1   initialize crc32 module before writing encrypted data to flash. Active low.*/
+            uint32_t tx_crc_en:        1;                       /*For SPI1   enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
+            uint32_t reserved12:       1;                       /*reserved*/
+            uint32_t fastrd_mode:      1;                       /*This bit enable the bits: spi_mem_fread_qio  spi_mem_fread_dio  spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
+            uint32_t fread_dual:       1;                       /*In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+            uint32_t resandres:        1;                       /*The Device ID is read out to SPI_MEM_RD_STATUS register   this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.*/
+            uint32_t reserved16:       1;                       /*reserved*/
+            uint32_t flash_suspending: 1;                       /*The status of flash suspend  only used in SPI1.*/
+            uint32_t q_pol:            1;                       /*The bit is used to set MISO line polarity  1: high 0  low*/
+            uint32_t d_pol:            1;                       /*The bit is used to set MOSI line polarity  1: high 0  low*/
+            uint32_t fread_quad:       1;                       /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+            uint32_t wp:               1;                       /*Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+            uint32_t wrsr_2b:          1;                       /*two bytes data will be written to status register when it is set. 1: enable 0: disable.*/
+            uint32_t fread_dio:        1;                       /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
+            uint32_t fread_qio:        1;                       /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
+            uint32_t reserved25:       7;                       /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode:          2;                      /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t cs_hold_delay_res:12;                      /*Delay cycles of resume Flash when resume Flash is enable by spi clock.*/
+            uint32_t cs_hold_delay:     6;                      /*SPI cs signal is delayed by spi clock cycles.*/
+            uint32_t reserved20:       12;                      /*reserved*/
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time:13;                          /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
+            uint32_t cs_hold_time: 13;                          /*delay cycles of cs pin by spi clock this bits are combined with spi_mem_cs_hold bit.*/
+            uint32_t cs_delay_mode: 2;                          /*spi_mem_cs signal is delayed by spi_mem_clk . 0: zero 1: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by half cycle  else delayed by one cycle 2: if spi_mem_ck_out_edge or spi_mem_ck_i_edge is set 1 delayed by one cycle  else delayed by half cycle 3: delayed one cycle*/
+            uint32_t cs_delay_num:  2;                          /*spi_mem_cs signal is delayed by system clock cycles*/
+            uint32_t cs_delay_edge: 1;                          /*The bit is used to select the spi clock edge to modify CS line timing.*/
+            uint32_t sync_reset:    1;                          /*The FSM will be reset.*/
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l:       8;                         /*In the master mode it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/
+            uint32_t clkcnt_h:       8;                         /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
+            uint32_t clkcnt_n:       8;                         /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24:     7;                         /*In the master mode it is pre-divider of spi_mem_clk.*/
+            uint32_t clk_equ_sysclk: 1;                         /*reserved*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t reserved0:         6;                      /*reserved*/
+            uint32_t cs_hold:           1;                      /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+            uint32_t cs_setup:          1;                      /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+            uint32_t ck_i_edge:         1;                      /*In the slave mode the bit is same as spi_mem_ck_out_edge in master mode. It is combined with  spi_mem_miso_delay_mode bits.*/
+            uint32_t ck_out_edge:       1;                      /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
+            uint32_t reserved10:        2;                      /*reserved*/
+            uint32_t fwrite_dual:       1;                      /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad:       1;                      /*In the write operations read-data phase apply 4 signals*/
+            uint32_t fwrite_dio:        1;                      /*In the write operations address phase and read-data phase apply 2 signals.*/
+            uint32_t fwrite_qio:        1;                      /*In the write operations address phase and read-data phase apply 4 signals.*/
+            uint32_t reserved16:        8;                      /*reserved*/
+            uint32_t usr_miso_highpart: 1;                      /*read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
+            uint32_t usr_mosi_highpart: 1;                      /*write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.*/
+            uint32_t usr_dummy_idle:    1;                      /*spi clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi:          1;                      /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso:          1;                      /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy:         1;                      /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr:          1;                      /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command:       1;                      /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen: 8;                     /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t reserved8:         18;                     /*reserved*/
+            uint32_t usr_addr_bitlen:    6;                     /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value: 16;                     /*The value of  command.*/
+            uint32_t reserved16:        12;                     /*reserved*/
+            uint32_t usr_command_bitlen: 4;                     /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len:11;                       /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved11:      21;                       /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len:11;                       /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved11:      21;                       /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    union {
+        struct {
+            uint32_t status:    16;                             /*The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.*/
+            uint32_t wb_mode:    8;                             /*Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t reserved24: 8;                             /*reserved*/
+        };
+        uint32_t val;
+    } rd_status;
+    uint32_t ext_addr;                                          /*The register are the higher 32bits in the 64 bits address mode.*/
+    union {
+        struct {
+            uint32_t cs0_dis:           1;                      /*SPI CS0 pin enable  1: disable CS0  0: spi_mem_cs0 signal is from/to CS0 pin*/
+            uint32_t cs1_dis:           1;                      /*SPI CS1 pin enable  1: disable CS1  0: spi_mem_cs1 signal is from/to CS1 pin*/
+            uint32_t reserved2:         1;                      /*reserved*/
+            uint32_t trans_end:         1;                      /*The bit is used to indicate the transimitting is done.*/
+            uint32_t trans_end_en:         1;                      /*The bit is used to enable the intterrupt of SPI transmitting done.*/
+            uint32_t cs_pol:            2;                      /*In the master mode the bits are the polarity of spi cs line  the value is equivalent to spi_mem_cs ^ spi_mem_master_cs_pol.*/
+            uint32_t fsub_pin:          1;                      /*For SPI0   flash is connected to SUBPINs.*/
+            uint32_t ssub_pin:          1;                      /*For SPI0   sram is connected to SUBPINs.*/
+            uint32_t ck_idle_edge:      1;                      /*1: spi clk line is high when idle     0: spi clk line is low when idle*/
+            uint32_t cs_keep_active:    1;                      /*spi cs line keep low when the bit is set.*/
+            uint32_t auto_per:          1;                      /*reserved*/
+            uint32_t reserved12:       20;                      /*reserved*/
+        };
+        uint32_t val;
+    } misc;
+    uint32_t tx_crc;                                            /*For SPI1  the value of crc32.*/
+    union {
+        struct {
+            uint32_t req_en:              1;                    /*For SPI0  Cache access enable  1: enable  0:disable.*/
+            uint32_t usr_cmd_4byte:       1;                    /*For SPI0   cache  read flash with 4 bytes command  1: enable  0:disable.*/
+            uint32_t flash_usr_cmd:       1;                    /*For SPI0   cache  read flash for user define command  1: enable  0:disable.*/
+            uint32_t fdin_dual:           1;                    /*For SPI0 flash  din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdout_dual:          1;                    /*For SPI0 flash  dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
+            uint32_t faddr_dual:          1;                    /*For SPI0 flash  address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.*/
+            uint32_t fdin_quad:           1;                    /*For SPI0 flash  din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t fdout_quad:          1;                    /*For SPI0 flash  dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t faddr_quad:          1;                    /*For SPI0 flash  address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.*/
+            uint32_t reserved9:          23;                    /*reserved*/
+        };
+        uint32_t val;
+    } cache_fctrl;
+    union {
+        struct {
+            uint32_t usr_scmd_4byte:       1;                   /*For SPI0  In the spi sram mode  cache read flash with 4 bytes command  1: enable  0:disable.*/
+            uint32_t usr_sram_dio:         1;                   /*For SPI0  In the spi sram mode  spi dual I/O mode enable  1: enable  0:disable*/
+            uint32_t usr_sram_qio:         1;                   /*For SPI0  In the spi sram mode  spi quad I/O mode enable  1: enable  0:disable*/
+            uint32_t usr_wr_sram_dummy:    1;                   /*For SPI0  In the spi sram mode  it is the enable bit of dummy phase for write operations.*/
+            uint32_t usr_rd_sram_dummy:    1;                   /*For SPI0  In the spi sram mode  it is the enable bit of dummy phase for read operations.*/
+            uint32_t cache_sram_usr_rcmd:  1;                   /*For SPI0  In the spi sram mode cache read sram for user define command.*/
+            uint32_t sram_rdummy_cyclelen: 8;                   /*For SPI0  In the sram mode  it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t sram_addr_bitlen:     6;                   /*For SPI0  In the sram mode  it is the length in bits of address phase. The register value shall be (bit_num-1).*/
+            uint32_t cache_sram_usr_wcmd:  1;                   /*For SPI0  In the spi sram mode cache write sram for user define command*/
+            uint32_t reserved21:           1;                   /*reserved*/
+            uint32_t sram_wdummy_cyclelen: 8;                   /*For SPI0  In the sram mode  it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
+            uint32_t reserved30:           2;                   /*reserved*/
+        };
+        uint32_t val;
+    } cache_sctrl;
+    union {
+        struct {
+            uint32_t sclk_mode:  2;                             /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t swb_mode:   8;                             /*Mode bits in the psram fast read mode  it is combined with spi_mem_fastrd_mode bit.*/
+            uint32_t sdin_dual:  1;                             /*For SPI0 sram  din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t sdout_dual: 1;                             /*For SPI0 sram  dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t saddr_dual: 1;                             /*For SPI0 sram  address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t scmd_dual:  1;                             /*For SPI0 sram  cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
+            uint32_t sdin_quad:  1;                             /*For SPI0 sram  din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t sdout_quad: 1;                             /*For SPI0 sram  dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t saddr_quad: 1;                             /*For SPI0 sram  address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t scmd_quad:  1;                             /*For SPI0 sram  cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
+            uint32_t reserved18:14;                             /*reserved*/
+        };
+        uint32_t val;
+    } sram_cmd;
+    union {
+        struct {
+            uint32_t usr_rd_cmd_value:            16;           /*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/
+            uint32_t reserved16:                  12;           /*reserved*/
+            uint32_t usr_rd_cmd_bitlen:            4;           /*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_drd_cmd;
+    union {
+        struct {
+            uint32_t usr_wr_cmd_value:            16;           /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/
+            uint32_t reserved16:                  12;           /*reserved*/
+            uint32_t usr_wr_cmd_bitlen:            4;           /*For SPI0 When cache mode is enable it is the in bits of command phase  for sram. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } sram_dwr_cmd;
+    union {
+        struct {
+            uint32_t cnt_l:           8;                        /*For SPI0 sram interface  it must be equal to spi_mem_clkcnt_N. In the slave mode it must be 0.*/
+            uint32_t cnt_h:           8;                        /*For SPI0 sram interface  it must be floor((spi_mem_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
+            uint32_t cnt_n:           8;                        /*For SPI0 sram interface  it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
+            uint32_t reserved24:      7;                        /*reserved*/
+            uint32_t equ_sysclk:      1;                        /*For SPI0 sram interface  1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
+        };
+        uint32_t val;
+    } sram_clk;
+    union {
+        struct {
+            uint32_t st:         3;                             /*The status of spi state machine. 0: idle state  1: preparation state  2: send command state  3: send data state  4: red data state  5:write data state  6: wait state  7: done state.*/
+            uint32_t reserved3: 29;                             /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    union {
+        struct {
+            uint32_t hold_ena:   2;                             /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set  if the other SPI is busy  the SPI will be hold. 1(3): hold at  idle  phase 2: hold at  prepare  phase.*/
+            uint32_t reserved2: 30;                             /*reserved*/
+        };
+        uint32_t val;
+    } hold;
+    union {
+        struct {
+            uint32_t dma_rx_ena:        1;                      /*spi dma rx data enable.*/
+            uint32_t dma_tx_ena:        1;                      /*spi dma tx data enable.*/
+            uint32_t in_rst:            1;                      /*The bit is used to reset in dma fsm and in data fifo pointer.*/
+            uint32_t out_rst:           1;                      /*The bit is used to reset out dma fsm and out data fifo pointer.*/
+            uint32_t ahbm_fifo_rst:     1;                      /*Reset spi dma ahb master fifo pointer.*/
+            uint32_t ahbm_rst:          1;                      /*Reset spi dma ahb master.*/
+            uint32_t in_loop_test:      1;                      /*Set bit to test in link.*/
+            uint32_t out_loop_test:     1;                      /*Set bit to test out link.*/
+            uint32_t out_auto_wrback:   1;                      /*when the bit is set  DMA continue to use the next inlink node when the length of inlink is 0.*/
+            uint32_t out_eof_mode:      1;                      /*out eof flag generation mode . 1: when dma pop all data from fifo  0:when ahb push all data to fifo.*/
+            uint32_t outdscr_burst_en:  1;                      /*read descriptor use burst mode when read data for memory.*/
+            uint32_t indscr_burst_en:   1;                      /*read descriptor use burst mode when write data to memory.*/
+            uint32_t out_data_burst_en: 1;                      /*spi dma read data from memory in burst mode.*/
+            uint32_t dma_mem_trans_ena: 1;                      /*reserved*/
+            uint32_t dma_rx_stop:       1;                      /*spi dma read data stop  when in continue tx/rx mode.*/
+            uint32_t dma_tx_stop:       1;                      /*spi dma write data stop when in continue tx/rx mode.*/
+            uint32_t dma_continue:      1;                      /*spi dma continue tx/rx data.*/
+            uint32_t reserved17:       15;                      /*reserved*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t addr:           20;                        /*The address of the first outlink descriptor.*/
+            uint32_t reserved20:      8;                        /*reserved*/
+            uint32_t stop:            1;                        /*Set the bit to stop to use outlink descriptor.*/
+            uint32_t start:           1;                        /*Set the bit to start to use outlink descriptor.*/
+            uint32_t restart:         1;                        /*Set the bit to mount on new outlink descriptors.*/
+            uint32_t reserved31:      1;                        /*reserved*/
+        };
+        uint32_t val;
+    } dma_out_link;
+    union {
+        struct {
+            uint32_t addr:           20;                        /*The address of the first inlink descriptor.*/
+            uint32_t auto_ret:        1;                        /*when the bit is set  the inlink descriptor returns to the first link node when a packet is error.*/
+            uint32_t reserved21:      7;                        /*reserved*/
+            uint32_t stop:            1;                        /*Set the bit to stop to use inlink descriptor.*/
+            uint32_t start:           1;                        /*Set the bit to start to use inlink descriptor.*/
+            uint32_t restart:         1;                        /*Set the bit to mount on new inlink descriptors.*/
+            uint32_t reserved31:      1;                        /*reserved*/
+        };
+        uint32_t val;
+    } dma_in_link;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:          1;             /*The enable bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:         1;             /*The enable bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:          1;             /*The enable bit for inlink descriptor error.*/
+            uint32_t in_done:                    1;             /*The enable bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                 1;             /*The enable bit for receiving error.*/
+            uint32_t in_suc_eof:                 1;             /*The enable bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                   1;             /*The enable bit for completing usage of a outlink descriptor .*/
+            uint32_t out_eof:                    1;             /*The enable bit for sending a packet to host done.*/
+            uint32_t out_total_eof:              1;             /*The enable bit for sending all the packets to host done.*/
+            uint32_t reserved9:                 23;             /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:          1;             /*The raw bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:         1;             /*The raw bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:          1;             /*The raw bit for inlink descriptor error.*/
+            uint32_t in_done:                    1;             /*The raw bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                 1;             /*The raw bit for receiving error.*/
+            uint32_t in_suc_eof:                 1;             /*The raw bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                   1;             /*The raw bit for completing usage of a outlink descriptor.*/
+            uint32_t out_eof:                    1;             /*The raw bit for sending a packet to host done.*/
+            uint32_t out_total_eof:              1;             /*The raw bit for sending all the packets to host done.*/
+            uint32_t reserved9:                 23;             /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:         1;              /*The status bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:        1;              /*The status bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:         1;              /*The status bit for inlink descriptor error.*/
+            uint32_t in_done:                   1;              /*The status bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                1;              /*The status bit for receiving error.*/
+            uint32_t in_suc_eof:                1;              /*The status bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                  1;              /*The status bit for completing usage of a outlink descriptor.*/
+            uint32_t out_eof:                   1;              /*The status bit for sending a packet to host done.*/
+            uint32_t out_total_eof:             1;              /*The status bit for sending all the packets to host done.*/
+            uint32_t reserved9:                23;              /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:          1;             /*The clear bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:         1;             /*The clear bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:          1;             /*The clear bit for inlink descriptor error.*/
+            uint32_t in_done:                    1;             /*The clear bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                 1;             /*The clear bit for receiving error.*/
+            uint32_t in_suc_eof:                 1;             /*The clear bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                   1;             /*The clear bit for completing usage of a outlink descriptor.*/
+            uint32_t out_eof:                    1;             /*The clear bit for sending a packet to host done.*/
+            uint32_t out_total_eof:              1;             /*The clear bit for sending all the packets to host done.*/
+            uint32_t reserved9:                 23;             /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    uint32_t dma_in_err_eof_des_addr;                               /*The inlink descriptor address when spi dma produce receiving error.*/
+    uint32_t dma_in_suc_eof_des_addr;                               /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
+    uint32_t dma_inlink_dscr;                                       /*The content of current in descriptor pointer.*/
+    uint32_t dma_inlink_dscr_bf0;                                   /*The content of next in descriptor pointer.*/
+    uint32_t dma_inlink_dscr_bf1;                                   /*The content of current in descriptor data buffer pointer.*/
+    uint32_t dma_out_eof_bfr_des_addr;                              /*The address of buffer relative to the outlink descriptor that produce eof.*/
+    uint32_t dma_out_eof_des_addr;                                  /*The last outlink descriptor address when spi dma produce to_eof.*/
+    uint32_t dma_outlink_dscr;                                      /*The content of current out descriptor pointer.*/
+    uint32_t dma_outlink_dscr_bf0;                                  /*The content of next out descriptor pointer.*/
+    uint32_t dma_outlink_dscr_bf1;                                  /*The content of current out descriptor data buffer pointer.*/
+    union {
+        struct {
+            uint32_t out_dscr_addr:    18;                      /*SPI dma out descriptor address.*/
+            uint32_t out_dscr_state:    2;                      /*SPI dma out descriptor state.*/
+            uint32_t out_state:         3;                      /*SPI dma out data state.*/
+            uint32_t out_fifo_cnt:      7;                      /*The remains of SPI dma outfifo data.*/
+            uint32_t out_fifo_full:     1;                      /*SPI dma outfifo is full.*/
+            uint32_t out_fifo_empty:    1;                      /*SPI dma outfifo is empty.*/
+        };
+        uint32_t val;
+    } dma_out_status;
+    union {
+        struct {
+            uint32_t in_dscr_addr:    18;                       /*SPI dma in descriptor address.*/
+            uint32_t in_dscr_state:    2;                       /*SPI dma in descriptor state.*/
+            uint32_t in_state:         3;                       /*SPI dma in data state.*/
+            uint32_t in_fifo_cnt:      7;                       /*The remains of SPI dma infifo data.*/
+            uint32_t in_fifo_full:     1;                       /*SPI dma infifo is full.*/
+            uint32_t in_fifo_empty:    1;                       /*SPI dma infifo is empty.*/
+        };
+        uint32_t val;
+    } dma_in_status;
+    uint32_t data_buf[16];                                                /*data buffer*/
+    union {
+        struct {
+            uint32_t waiti_en:             1;                   /*auto-waiting flash idle operation when program flash or erase flash. 1: enable 0: disable.*/
+            uint32_t waiti_dummy:          1;                   /*The dummy phase enable when auto wait flash idle*/
+            uint32_t waiti_cmd:            8;                   /*The command to auto wait idle*/
+            uint32_t waiti_dummy_cyclelen: 8;                   /*The dummy cycle length when auto wait flash idle*/
+            uint32_t reserved18:          14;                   /*reserved*/
+        };
+        uint32_t val;
+    } flash_waiti_ctrl;
+    union {
+        struct {
+            uint32_t flash_per:  1;                             /*program erase resume bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t flash_pes:  1;                             /*program erase suspend bit  program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t reserved2: 30;
+        };
+        uint32_t val;
+    } flash_sus_cmd;
+    union {
+        struct {
+            uint32_t flash_pes_en:      1;                      /*Auto-suspending enable*/
+            uint32_t flash_per_command: 8;                      /*Program/Erase resume command.*/
+            uint32_t flash_pes_command: 8;                      /*Program/Erase suspend command.*/
+            uint32_t reserved17:       15;
+        };
+        uint32_t val;
+    } flash_sus_ctrl;
+    union {
+        struct {
+            uint32_t din0_mode:     2;                          /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t din1_mode:     2;                          /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t din2_mode:     2;                          /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t din3_mode:     2;                          /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t reserved8:    10;                          /*reserved*/
+            uint32_t din0_dly_edge: 1;                          /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t din1_dly_edge: 1;                          /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t din2_dly_edge: 1;                          /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t din3_dly_edge: 1;                          /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t reserved22:   10;                          /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num:   2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din1_num:   2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din2_num:   2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din3_num:   2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved8: 24;                             /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode:     2;                         /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout1_mode:     2;                         /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout2_mode:     2;                         /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout3_mode:     2;                         /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t reserved8:     10;                         /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout0_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t dout1_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t dout2_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t dout3_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t reserved22:    10;                         /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t dout0_num:  2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t dout1_num:  2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t dout2_num:  2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t dout3_num:  2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved8: 24;                             /*reserved*/
+        };
+        uint32_t val;
+    } dout_num;
+    union {
+        struct {
+            uint32_t sdin0_mode:     2;                         /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t sdin1_mode:     2;                         /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t sdin2_mode:     2;                         /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t sdin3_mode:     2;                         /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t reserved8:     10;
+            uint32_t sdin0_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t sdin1_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t sdin2_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t sdin3_dly_edge: 1;                         /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t reserved22:    10;                         /*reserved*/
+        };
+        uint32_t val;
+    } sdin_mode;
+    union {
+        struct {
+            uint32_t sdin0_num:  2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t sdin1_num:  2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t sdin2_num:  2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t sdin3_num:  2;                             /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved8: 24;                             /*reserved*/
+        };
+        uint32_t val;
+    } sdin_num;
+    union {
+        struct {
+            uint32_t sdout0_mode:     2;                        /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t sdout1_mode:     2;                        /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t sdout2_mode:     2;                        /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t sdout3_mode:     2;                        /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t reserved8:      10;                        /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t sdout0_dly_edge: 1;                        /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t sdout1_dly_edge: 1;                        /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t sdout2_dly_edge: 1;                        /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t sdout3_dly_edge: 1;                        /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t reserved22:     10;                        /*reserved*/
+        };
+        uint32_t val;
+    } sdout_mode;
+    union {
+        struct {
+            uint32_t sdout0_num: 2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t sdout1_num: 2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t sdout2_num: 2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t sdout3_num: 2;                             /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved8: 24;                             /*reserved*/
+        };
+        uint32_t val;
+    } sdout_num;
+    union {
+        struct {
+            uint32_t clk_en:     1;
+            uint32_t reserved1: 31;
+        };
+        uint32_t val;
+    } clock_gate;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date:      28;                             /*SPI register version.*/
+            uint32_t reserved28: 4;                             /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_mem_dev_t;
+extern spi_mem_dev_t SPIMEM0;
+extern spi_mem_dev_t SPIMEM1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SPI_MEM_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/spi_pins.h b/components/soc/esp32s2beta/include/soc/spi_pins.h
new file mode 100644
index 000000000..c91341786
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/spi_pins.h
@@ -0,0 +1,40 @@
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_SPI_PINS_H_
+#define _SOC_SPI_PINS_H_
+
+#define SPI_PERIPH_NUM          4
+
+#define SPI_FUNC_NUM            2
+#define SPI_IOMUX_PIN_NUM_HD    27
+#define SPI_IOMUX_PIN_NUM_CS    29
+#define SPI_IOMUX_PIN_NUM_MOSI  32
+#define SPI_IOMUX_PIN_NUM_CLK   30
+#define SPI_IOMUX_PIN_NUM_MISO  31
+#define SPI_IOMUX_PIN_NUM_WP    28
+//TODO: add the next slot
+
+#define FSPI_FUNC_NUM           0
+#define FSPI_IOMUX_PIN_NUM_HD   9
+#define FSPI_IOMUX_PIN_NUM_CS   10
+#define FSPI_IOMUX_PIN_NUM_MOSI 11
+#define FSPI_IOMUX_PIN_NUM_CLK  12
+#define FSPI_IOMUX_PIN_NUM_MISO 13
+#define FSPI_IOMUX_PIN_NUM_WP   14
+//TODO: add the next slot
+
+//HSPI and VSPI have no iomux pins
+
+#endif
\ No newline at end of file
diff --git a/components/soc/esp32s2beta/include/soc/spi_reg.h b/components/soc/esp32s2beta/include/soc/spi_reg.h
new file mode 100644
index 000000000..27a2cfc40
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/spi_reg.h
@@ -0,0 +1,1646 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_REG_H_
+#define _SOC_SPI_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define REG_SPI_BASE(i)     (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 )))
+
+#define SPI_CMD_REG(i)          (REG_SPI_BASE(i) + 0x000)
+/* SPI_USR : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: User define command enable.  An operation will be triggered when
+ the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+#define SPI_USR  (BIT(18))
+#define SPI_USR_M  (BIT(18))
+#define SPI_USR_V  0x1
+#define SPI_USR_S  18
+
+#define SPI_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x004)
+/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: [31:8]:address to slave  [7:0]:Reserved.*/
+#define SPI_USR_ADDR_VALUE  0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_M  ((SPI_USR_ADDR_VALUE_V)<<(SPI_USR_ADDR_VALUE_S))
+#define SPI_USR_ADDR_VALUE_V  0xFFFFFFFF
+#define SPI_USR_ADDR_VALUE_S  0
+
+#define SPI_CTRL_REG(i)          (REG_SPI_BASE(i) + 0x008)
+/* SPI_DEFINE_SLV_ADDR : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: set spi_usr_addr and spi_usr_addr_value in spi defined slave
+ mode. 1: disable 0:enable.*/
+#define SPI_DEFINE_SLV_ADDR  (BIT(27))
+#define SPI_DEFINE_SLV_ADDR_M  (BIT(27))
+#define SPI_DEFINE_SLV_ADDR_V  0x1
+#define SPI_DEFINE_SLV_ADDR_S  27
+/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
+#define SPI_WR_BIT_ORDER  (BIT(26))
+#define SPI_WR_BIT_ORDER_M  (BIT(26))
+#define SPI_WR_BIT_ORDER_V  0x1
+#define SPI_WR_BIT_ORDER_S  26
+/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: In read-data (MISO) phase 1: LSB first 0: MSB first*/
+#define SPI_RD_BIT_ORDER  (BIT(25))
+#define SPI_RD_BIT_ORDER_M  (BIT(25))
+#define SPI_RD_BIT_ORDER_V  0x1
+#define SPI_RD_BIT_ORDER_S  25
+/* SPI_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+#define SPI_WP_REG  (BIT(21))
+#define SPI_WP_REG_M  (BIT(21))
+#define SPI_WP_REG_V  0x1
+#define SPI_WP_REG_S  21
+/* SPI_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+#define SPI_FREAD_QUAD  (BIT(20))
+#define SPI_FREAD_QUAD_M  (BIT(20))
+#define SPI_FREAD_QUAD_V  0x1
+#define SPI_FREAD_QUAD_S  20
+/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */
+/*description: The bit is used to set MOSI line polarity  1: high 0  low*/
+#define SPI_D_POL  (BIT(19))
+#define SPI_D_POL_M  (BIT(19))
+#define SPI_D_POL_V  0x1
+#define SPI_D_POL_S  19
+/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: The bit is used to set MISO line polarity  1: high 0  low*/
+#define SPI_Q_POL  (BIT(18))
+#define SPI_Q_POL_M  (BIT(18))
+#define SPI_Q_POL_V  0x1
+#define SPI_Q_POL_S  18
+/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+#define SPI_FREAD_DUAL  (BIT(14))
+#define SPI_FREAD_DUAL_M  (BIT(14))
+#define SPI_FREAD_DUAL_V  0x1
+#define SPI_FREAD_DUAL_S  14
+/* SPI_FAST_RD_MODE : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: Enable 2/4 lines addr command  including read and write command.*/
+#define SPI_FAST_RD_MODE  (BIT(13))
+#define SPI_FAST_RD_MODE_M  (BIT(13))
+#define SPI_FAST_RD_MODE_V  0x1
+#define SPI_FAST_RD_MODE_S  13
+/* SPI_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: Apply 4 signals during command phase 1:enable 0: disable*/
+#define SPI_FCMD_QUAD  (BIT(8))
+#define SPI_FCMD_QUAD_M  (BIT(8))
+#define SPI_FCMD_QUAD_V  0x1
+#define SPI_FCMD_QUAD_S  8
+/* SPI_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Apply 2 signals during command phase 1:enable 0: disable*/
+#define SPI_FCMD_DUAL  (BIT(7))
+#define SPI_FCMD_DUAL_M  (BIT(7))
+#define SPI_FCMD_DUAL_V  0x1
+#define SPI_FCMD_DUAL_S  7
+/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Apply 4 signals during addr phase 1:enable 0: disable*/
+#define SPI_FADDR_QUAD  (BIT(6))
+#define SPI_FADDR_QUAD_M  (BIT(6))
+#define SPI_FADDR_QUAD_V  0x1
+#define SPI_FADDR_QUAD_S  6
+/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Apply 2 signals during addr phase 1:enable 0: disable*/
+#define SPI_FADDR_DUAL  (BIT(5))
+#define SPI_FADDR_DUAL_M  (BIT(5))
+#define SPI_FADDR_DUAL_V  0x1
+#define SPI_FADDR_DUAL_S  5
+/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: In the dummy phase the signal level of spi is output by the spi controller.*/
+#define SPI_DUMMY_OUT  (BIT(3))
+#define SPI_DUMMY_OUT_M  (BIT(3))
+#define SPI_DUMMY_OUT_V  0x1
+#define SPI_DUMMY_OUT_S  3
+/* SPI_EXT_HOLD_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: Set the bit to hold spi. The bit is combined with spi_usr_prep_hold
+ spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol.*/
+#define SPI_EXT_HOLD_EN  (BIT(2))
+#define SPI_EXT_HOLD_EN_M  (BIT(2))
+#define SPI_EXT_HOLD_EN_V  0x1
+#define SPI_EXT_HOLD_EN_S  2
+
+#define SPI_CTRL1_REG(i)          (REG_SPI_BASE(i) + 0x00C)
+/* SPI_CS_HOLD_DELAY : R/W ;bitpos:[19:14] ;default: 6'h1 ; */
+/*description: SPI cs signal is delayed by spi clock cycles.*/
+#define SPI_CS_HOLD_DELAY  0x0000003F
+#define SPI_CS_HOLD_DELAY_M  ((SPI_CS_HOLD_DELAY_V)<<(SPI_CS_HOLD_DELAY_S))
+#define SPI_CS_HOLD_DELAY_V  0x3F
+#define SPI_CS_HOLD_DELAY_S  14
+/* SPI_W16_17_WR_ENA : R/W ;bitpos:[4] ;default: 1'h1 ; */
+/*description: 1:reg_buf[16] [17] can be written   0:reg_buf[16] [17] can not  be written.*/
+#define SPI_W16_17_WR_ENA  (BIT(4))
+#define SPI_W16_17_WR_ENA_M  (BIT(4))
+#define SPI_W16_17_WR_ENA_V  0x1
+#define SPI_W16_17_WR_ENA_S  4
+/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: It saves half a cycle when tsck is the same as rsck. 1: output
+ data at rsck posedge   0: output data at tsck posedge*/
+#define SPI_RSCK_DATA_OUT  (BIT(3))
+#define SPI_RSCK_DATA_OUT_M  (BIT(3))
+#define SPI_RSCK_DATA_OUT_V  0x1
+#define SPI_RSCK_DATA_OUT_S  3
+/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: {CPOL  CPHA} 1: support spi clk mode 1 and 3  first edge output data B[0]/B[7]*/
+#define SPI_CLK_MODE_13  (BIT(2))
+#define SPI_CLK_MODE_13_M  (BIT(2))
+#define SPI_CLK_MODE_13_V  0x1
+#define SPI_CLK_MODE_13_S  2
+/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1:
+ SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+#define SPI_CLK_MODE  0x00000003
+#define SPI_CLK_MODE_M  ((SPI_CLK_MODE_V)<<(SPI_CLK_MODE_S))
+#define SPI_CLK_MODE_V  0x3
+#define SPI_CLK_MODE_S  0
+
+#define SPI_CTRL2_REG(i)          (REG_SPI_BASE(i) + 0x010)
+/* SPI_CS_DELAY_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define SPI_CS_DELAY_EDGE  (BIT(31))
+#define SPI_CS_DELAY_EDGE_M  (BIT(31))
+#define SPI_CS_DELAY_EDGE_V  0x1
+#define SPI_CS_DELAY_EDGE_S  31
+/* SPI_CS_DELAY_NUM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
+/*description: spi_cs signal is delayed by system clock cycles*/
+#define SPI_CS_DELAY_NUM  0x00000003
+#define SPI_CS_DELAY_NUM_M  ((SPI_CS_DELAY_NUM_V)<<(SPI_CS_DELAY_NUM_S))
+#define SPI_CS_DELAY_NUM_V  0x3
+#define SPI_CS_DELAY_NUM_S  28
+/* SPI_CS_DELAY_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
+/*description: spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge
+ or spi_ck_i_edge is set 1 delayed by half cycle  else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle  else delayed by half cycle 3: delayed one cycle*/
+#define SPI_CS_DELAY_MODE  0x00000003
+#define SPI_CS_DELAY_MODE_M  ((SPI_CS_DELAY_MODE_V)<<(SPI_CS_DELAY_MODE_S))
+#define SPI_CS_DELAY_MODE_V  0x3
+#define SPI_CS_DELAY_MODE_S  26
+/* SPI_CS_HOLD_TIME : R/W ;bitpos:[25:13] ;default: 13'h1 ; */
+/*description: delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.*/
+#define SPI_CS_HOLD_TIME  0x00001FFF
+#define SPI_CS_HOLD_TIME_M  ((SPI_CS_HOLD_TIME_V)<<(SPI_CS_HOLD_TIME_S))
+#define SPI_CS_HOLD_TIME_V  0x1FFF
+#define SPI_CS_HOLD_TIME_S  13
+/* SPI_CS_SETUP_TIME : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
+/*description: (cycles-1) of prepare phase by spi clock this bits are combined
+ with spi_cs_setup bit.*/
+#define SPI_CS_SETUP_TIME  0x00001FFF
+#define SPI_CS_SETUP_TIME_M  ((SPI_CS_SETUP_TIME_V)<<(SPI_CS_SETUP_TIME_S))
+#define SPI_CS_SETUP_TIME_V  0x1FFF
+#define SPI_CS_SETUP_TIME_S  0
+
+#define SPI_CLOCK_REG(i)          (REG_SPI_BASE(i) + 0x014)
+/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is
+ divided from system clock.*/
+#define SPI_CLK_EQU_SYSCLK  (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_M  (BIT(31))
+#define SPI_CLK_EQU_SYSCLK_V  0x1
+#define SPI_CLK_EQU_SYSCLK_S  31
+/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */
+/*description: In the master mode it is pre-divider of spi_clk.*/
+#define SPI_CLKDIV_PRE  0x00001FFF
+#define SPI_CLKDIV_PRE_M  ((SPI_CLKDIV_PRE_V)<<(SPI_CLKDIV_PRE_S))
+#define SPI_CLKDIV_PRE_V  0x1FFF
+#define SPI_CLKDIV_PRE_S  18
+/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */
+/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency
+ is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
+#define SPI_CLKCNT_N  0x0000003F
+#define SPI_CLKCNT_N_M  ((SPI_CLKCNT_N_V)<<(SPI_CLKCNT_N_S))
+#define SPI_CLKCNT_N_V  0x3F
+#define SPI_CLKCNT_N_S  12
+/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */
+/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In
+ the slave mode it must be 0.*/
+#define SPI_CLKCNT_H  0x0000003F
+#define SPI_CLKCNT_H_M  ((SPI_CLKCNT_H_V)<<(SPI_CLKCNT_H_S))
+#define SPI_CLKCNT_H_V  0x3F
+#define SPI_CLKCNT_H_S  6
+/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
+/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave
+ mode it must be 0.*/
+#define SPI_CLKCNT_L  0x0000003F
+#define SPI_CLKCNT_L_M  ((SPI_CLKCNT_L_V)<<(SPI_CLKCNT_L_S))
+#define SPI_CLKCNT_L_V  0x3F
+#define SPI_CLKCNT_L_S  0
+
+#define SPI_USER_REG(i)          (REG_SPI_BASE(i) + 0x018)
+/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */
+/*description: This bit enable the command phase of an operation.*/
+#define SPI_USR_COMMAND  (BIT(31))
+#define SPI_USR_COMMAND_M  (BIT(31))
+#define SPI_USR_COMMAND_V  0x1
+#define SPI_USR_COMMAND_S  31
+/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: This bit enable the address phase of an operation.*/
+#define SPI_USR_ADDR  (BIT(30))
+#define SPI_USR_ADDR_M  (BIT(30))
+#define SPI_USR_ADDR_V  0x1
+#define SPI_USR_ADDR_S  30
+/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: This bit enable the dummy phase of an operation.*/
+#define SPI_USR_DUMMY  (BIT(29))
+#define SPI_USR_DUMMY_M  (BIT(29))
+#define SPI_USR_DUMMY_V  0x1
+#define SPI_USR_DUMMY_S  29
+/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: This bit enable the read-data phase of an operation.*/
+#define SPI_USR_MISO  (BIT(28))
+#define SPI_USR_MISO_M  (BIT(28))
+#define SPI_USR_MISO_V  0x1
+#define SPI_USR_MISO_S  28
+/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: This bit enable the write-data phase of an operation.*/
+#define SPI_USR_MOSI  (BIT(27))
+#define SPI_USR_MOSI_M  (BIT(27))
+#define SPI_USR_MOSI_V  0x1
+#define SPI_USR_MOSI_S  27
+/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: spi clock is disable in dummy phase when the bit is enable.*/
+#define SPI_USR_DUMMY_IDLE  (BIT(26))
+#define SPI_USR_DUMMY_IDLE_M  (BIT(26))
+#define SPI_USR_DUMMY_IDLE_V  0x1
+#define SPI_USR_DUMMY_IDLE_S  26
+/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15.
+ 1: enable 0: disable.*/
+#define SPI_USR_MOSI_HIGHPART  (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_M  (BIT(25))
+#define SPI_USR_MOSI_HIGHPART_V  0x1
+#define SPI_USR_MOSI_HIGHPART_S  25
+/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15.
+ 1: enable 0: disable.*/
+#define SPI_USR_MISO_HIGHPART  (BIT(24))
+#define SPI_USR_MISO_HIGHPART_M  (BIT(24))
+#define SPI_USR_MISO_HIGHPART_V  0x1
+#define SPI_USR_MISO_HIGHPART_S  24
+/* SPI_USR_PREP_HOLD : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_PREP_HOLD  (BIT(23))
+#define SPI_USR_PREP_HOLD_M  (BIT(23))
+#define SPI_USR_PREP_HOLD_V  0x1
+#define SPI_USR_PREP_HOLD_S  23
+/* SPI_USR_CMD_HOLD : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: spi is hold at command state the bit are combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_CMD_HOLD  (BIT(22))
+#define SPI_USR_CMD_HOLD_M  (BIT(22))
+#define SPI_USR_CMD_HOLD_V  0x1
+#define SPI_USR_CMD_HOLD_S  22
+/* SPI_USR_ADDR_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: spi is hold at address state the bit are combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_ADDR_HOLD  (BIT(21))
+#define SPI_USR_ADDR_HOLD_M  (BIT(21))
+#define SPI_USR_ADDR_HOLD_V  0x1
+#define SPI_USR_ADDR_HOLD_S  21
+/* SPI_USR_DUMMY_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_DUMMY_HOLD  (BIT(20))
+#define SPI_USR_DUMMY_HOLD_M  (BIT(20))
+#define SPI_USR_DUMMY_HOLD_V  0x1
+#define SPI_USR_DUMMY_HOLD_S  20
+/* SPI_USR_DIN_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: spi is hold at data in state the bit are combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_DIN_HOLD  (BIT(19))
+#define SPI_USR_DIN_HOLD_M  (BIT(19))
+#define SPI_USR_DIN_HOLD_V  0x1
+#define SPI_USR_DIN_HOLD_S  19
+/* SPI_USR_DOUT_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: spi is hold at data out state the bit are combined with spi_usr_hold_pol bit.*/
+#define SPI_USR_DOUT_HOLD  (BIT(18))
+#define SPI_USR_DOUT_HOLD_M  (BIT(18))
+#define SPI_USR_DOUT_HOLD_V  0x1
+#define SPI_USR_DOUT_HOLD_S  18
+/* SPI_USR_HOLD_POL : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: It is combined with hold bits to set the polarity of spi hold
+ line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
+#define SPI_USR_HOLD_POL  (BIT(17))
+#define SPI_USR_HOLD_POL_M  (BIT(17))
+#define SPI_USR_HOLD_POL_V  0x1
+#define SPI_USR_HOLD_POL_S  17
+/* SPI_SIO : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: Set the bit to enable 3-line half duplex communication mosi and
+ miso signals share the same pin. 1: enable 0: disable.*/
+#define SPI_SIO  (BIT(16))
+#define SPI_SIO_M  (BIT(16))
+#define SPI_SIO_V  0x1
+#define SPI_SIO_S  16
+/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 4 signals*/
+#define SPI_FWRITE_QUAD  (BIT(13))
+#define SPI_FWRITE_QUAD_M  (BIT(13))
+#define SPI_FWRITE_QUAD_V  0x1
+#define SPI_FWRITE_QUAD_S  13
+/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: In the write operations read-data phase apply 2 signals*/
+#define SPI_FWRITE_DUAL  (BIT(12))
+#define SPI_FWRITE_DUAL_M  (BIT(12))
+#define SPI_FWRITE_DUAL_V  0x1
+#define SPI_FWRITE_DUAL_S  12
+/* SPI_WR_BYTE_ORDER : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
+#define SPI_WR_BYTE_ORDER  (BIT(11))
+#define SPI_WR_BYTE_ORDER_M  (BIT(11))
+#define SPI_WR_BYTE_ORDER_V  0x1
+#define SPI_WR_BYTE_ORDER_S  11
+/* SPI_RD_BYTE_ORDER : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: In read-data (MISO) phase 1: big-endian 0: little_endian*/
+#define SPI_RD_BYTE_ORDER  (BIT(10))
+#define SPI_RD_BYTE_ORDER_M  (BIT(10))
+#define SPI_RD_BYTE_ORDER_V  0x1
+#define SPI_RD_BYTE_ORDER_S  10
+/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
+#define SPI_CK_OUT_EDGE  (BIT(9))
+#define SPI_CK_OUT_EDGE_M  (BIT(9))
+#define SPI_CK_OUT_EDGE_V  0x1
+#define SPI_CK_OUT_EDGE_S  9
+/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: In the slave mode  this bit can be used to change the polarity
+ of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
+#define SPI_RSCK_I_EDGE  (BIT(8))
+#define SPI_RSCK_I_EDGE_M  (BIT(8))
+#define SPI_RSCK_I_EDGE_V  0x1
+#define SPI_RSCK_I_EDGE_S  8
+/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+#define SPI_CS_SETUP  (BIT(7))
+#define SPI_CS_SETUP_M  (BIT(7))
+#define SPI_CS_SETUP_V  0x1
+#define SPI_CS_SETUP_S  7
+/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+#define SPI_CS_HOLD  (BIT(6))
+#define SPI_CS_HOLD_M  (BIT(6))
+#define SPI_CS_HOLD_V  0x1
+#define SPI_CS_HOLD_S  6
+/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: In the slave mode  this bit can be used to change the polarity
+ of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
+#define SPI_TSCK_I_EDGE  (BIT(5))
+#define SPI_TSCK_I_EDGE_M  (BIT(5))
+#define SPI_TSCK_I_EDGE_V  0x1
+#define SPI_TSCK_I_EDGE_S  5
+/* SPI_TX_START_BIT : R/W ;bitpos:[3:1] ;default: 3'd7 ; */
+/*description: It determines the start time of tx output data. It can be used
+ for timing adjustment in MISO slave mode.*/
+#define SPI_TX_START_BIT  0x00000007
+#define SPI_TX_START_BIT_M  ((SPI_TX_START_BIT_V)<<(SPI_TX_START_BIT_S))
+#define SPI_TX_START_BIT_V  0x7
+#define SPI_TX_START_BIT_S  1
+/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: Set the bit to enable full duplex communication. 1: enable 0: disable.*/
+#define SPI_DOUTDIN  (BIT(0))
+#define SPI_DOUTDIN_M  (BIT(0))
+#define SPI_DOUTDIN_V  0x1
+#define SPI_DOUTDIN_S  0
+
+#define SPI_USER1_REG(i)          (REG_SPI_BASE(i) + 0x01C)
+/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */
+/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/
+#define SPI_USR_ADDR_BITLEN  0x0000003F
+#define SPI_USR_ADDR_BITLEN_M  ((SPI_USR_ADDR_BITLEN_V)<<(SPI_USR_ADDR_BITLEN_S))
+#define SPI_USR_ADDR_BITLEN_V  0x3F
+#define SPI_USR_ADDR_BITLEN_S  26
+/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */
+/*description: The length in spi_clk cycles of dummy phase. The register value
+ shall be (cycle_num-1).*/
+#define SPI_USR_DUMMY_CYCLELEN  0x000000FF
+#define SPI_USR_DUMMY_CYCLELEN_M  ((SPI_USR_DUMMY_CYCLELEN_V)<<(SPI_USR_DUMMY_CYCLELEN_S))
+#define SPI_USR_DUMMY_CYCLELEN_V  0xFF
+#define SPI_USR_DUMMY_CYCLELEN_S  0
+
+#define SPI_USER2_REG(i)          (REG_SPI_BASE(i) + 0x020)
+/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */
+/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/
+#define SPI_USR_COMMAND_BITLEN  0x0000000F
+#define SPI_USR_COMMAND_BITLEN_M  ((SPI_USR_COMMAND_BITLEN_V)<<(SPI_USR_COMMAND_BITLEN_S))
+#define SPI_USR_COMMAND_BITLEN_V  0xF
+#define SPI_USR_COMMAND_BITLEN_S  28
+/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */
+/*description: The value of  command.*/
+#define SPI_USR_COMMAND_VALUE  0x0000FFFF
+#define SPI_USR_COMMAND_VALUE_M  ((SPI_USR_COMMAND_VALUE_V)<<(SPI_USR_COMMAND_VALUE_S))
+#define SPI_USR_COMMAND_VALUE_V  0xFFFF
+#define SPI_USR_COMMAND_VALUE_S  0
+
+#define SPI_MOSI_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x024)
+/* SPI_USR_MOSI_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: The length in bits of write-data. The register value shall be (bit_num-1).*/
+#define SPI_USR_MOSI_DBITLEN  0x00FFFFFF
+#define SPI_USR_MOSI_DBITLEN_M  ((SPI_USR_MOSI_DBITLEN_V)<<(SPI_USR_MOSI_DBITLEN_S))
+#define SPI_USR_MOSI_DBITLEN_V  0xFFFFFF
+#define SPI_USR_MOSI_DBITLEN_S  0
+
+#define SPI_MISO_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x028)
+/* SPI_USR_MISO_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: The length in bits of  read-data. The register value shall be (bit_num-1).*/
+#define SPI_USR_MISO_DBITLEN  0x00FFFFFF
+#define SPI_USR_MISO_DBITLEN_M  ((SPI_USR_MISO_DBITLEN_V)<<(SPI_USR_MISO_DBITLEN_S))
+#define SPI_USR_MISO_DBITLEN_V  0xFFFFFF
+#define SPI_USR_MISO_DBITLEN_S  0
+
+#define SPI_SLV_WR_STATUS_REG(i)          (REG_SPI_BASE(i) + 0x02C)
+/* SPI_SLV_WR_STATUS : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: In the master mode this register are the higher 32bits in the
+ 64 bits address condition.*/
+#define SPI_SLV_WR_STATUS  0xFFFFFFFF
+#define SPI_SLV_WR_STATUS_M  ((SPI_SLV_WR_STATUS_V)<<(SPI_SLV_WR_STATUS_S))
+#define SPI_SLV_WR_STATUS_V  0xFFFFFFFF
+#define SPI_SLV_WR_STATUS_S  0
+
+#define SPI_MISC_REG(i)          (REG_SPI_BASE(i) + 0x030)
+/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: 1:  spi quad input swap enable  0:  spi quad input swap disable*/
+#define SPI_QUAD_DIN_PIN_SWAP  (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_M  (BIT(31))
+#define SPI_QUAD_DIN_PIN_SWAP_V  0x1
+#define SPI_QUAD_DIN_PIN_SWAP_S  31
+/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: spi cs line keep low when the bit is set.*/
+#define SPI_CS_KEEP_ACTIVE  (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_M  (BIT(30))
+#define SPI_CS_KEEP_ACTIVE_V  0x1
+#define SPI_CS_KEEP_ACTIVE_S  30
+/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: 1: spi clk line is high when idle     0: spi clk line is low when idle*/
+#define SPI_CK_IDLE_EDGE  (BIT(29))
+#define SPI_CK_IDLE_EDGE_M  (BIT(29))
+#define SPI_CK_IDLE_EDGE_V  0x1
+#define SPI_CK_IDLE_EDGE_S  29
+/* SPI_Q_IDLE_OUT : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: The idle output value of spi_q.*/
+#define SPI_Q_IDLE_OUT  (BIT(27))
+#define SPI_Q_IDLE_OUT_M  (BIT(27))
+#define SPI_Q_IDLE_OUT_V  0x1
+#define SPI_Q_IDLE_OUT_S  27
+/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: spi slave input cs polarity select. 1: inv  0: not change*/
+#define SPI_SLAVE_CS_POL  (BIT(23))
+#define SPI_SLAVE_CS_POL_M  (BIT(23))
+#define SPI_SLAVE_CS_POL_V  0x1
+#define SPI_SLAVE_CS_POL_S  23
+/* SPI_MASTER_CS_POL : R/W ;bitpos:[8:6] ;default: 3'b0 ; */
+/*description: In the master mode the bits are the polarity of spi cs line 
+ the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
+#define SPI_MASTER_CS_POL  0x00000007
+#define SPI_MASTER_CS_POL_M  ((SPI_MASTER_CS_POL_V)<<(SPI_MASTER_CS_POL_S))
+#define SPI_MASTER_CS_POL_V  0x7
+#define SPI_MASTER_CS_POL_S  6
+/* SPI_CK_DIS : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: 1: spi clk out disable   0: spi clk out enable*/
+#define SPI_CK_DIS  (BIT(5))
+#define SPI_CK_DIS_M  (BIT(5))
+#define SPI_CK_DIS_V  0x1
+#define SPI_CK_DIS_S  5
+/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: SPI CS2 pin enable  1: disable CS2  0: spi_cs2 signal is from/to CS2 pin*/
+#define SPI_CS2_DIS  (BIT(2))
+#define SPI_CS2_DIS_M  (BIT(2))
+#define SPI_CS2_DIS_V  0x1
+#define SPI_CS2_DIS_S  2
+/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: SPI CS1 pin enable  1: disable CS1  0: spi_cs1 signal is from/to CS1 pin*/
+#define SPI_CS1_DIS  (BIT(1))
+#define SPI_CS1_DIS_M  (BIT(1))
+#define SPI_CS1_DIS_V  0x1
+#define SPI_CS1_DIS_S  1
+/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: SPI CS0 pin enable  1: disable CS0  0: spi_cs0 signal is from/to CS0 pin*/
+#define SPI_CS0_DIS  (BIT(0))
+#define SPI_CS0_DIS_M  (BIT(0))
+#define SPI_CS0_DIS_V  0x1
+#define SPI_CS0_DIS_S  0
+
+#define SPI_SLAVE_REG(i)          (REG_SPI_BASE(i) + 0x034)
+/* SPI_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: Software reset enable  reset the spi clock line cs line and data lines.*/
+#define SPI_SYNC_RESET  (BIT(31))
+#define SPI_SYNC_RESET_M  (BIT(31))
+#define SPI_SYNC_RESET_V  0x1
+#define SPI_SYNC_RESET_S  31
+/* SPI_SLAVE_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set SPI work mode. 1: slave mode 0: master mode.*/
+#define SPI_SLAVE_MODE  (BIT(30))
+#define SPI_SLAVE_MODE_M  (BIT(30))
+#define SPI_SLAVE_MODE_V  0x1
+#define SPI_SLAVE_MODE_S  30
+/* SPI_TRANS_CNT : RO ;bitpos:[26:23] ;default: 4'b0 ; */
+/*description: The operations counter in both the master mode and the slave mode.*/
+#define SPI_TRANS_CNT  0x0000000F
+#define SPI_TRANS_CNT_M  ((SPI_TRANS_CNT_V)<<(SPI_TRANS_CNT_S))
+#define SPI_TRANS_CNT_V  0xF
+#define SPI_TRANS_CNT_S  23
+/* SPI_INT_EN : R/W ;bitpos:[9:5] ;default: 5'b1_1111 ; */
+/*description: Interrupt enable bits for the below 5 sources*/
+#define SPI_INT_EN  0x0000001F
+#define SPI_INT_EN_M  ((SPI_INT_EN_V)<<(SPI_INT_EN_S))
+#define SPI_INT_EN_V  0x1F
+#define SPI_INT_EN_S  5
+/* SPI_TRANS_DONE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of any operation in
+ both the master mode and the slave mode.*/
+#define SPI_TRANS_DONE  (BIT(4))
+#define SPI_TRANS_DONE_M  (BIT(4))
+#define SPI_TRANS_DONE_V  0x1
+#define SPI_TRANS_DONE_S  4
+
+#define SPI_SLAVE1_REG(i)          (REG_SPI_BASE(i) + 0x038)
+/* SPI_SLV_LAST_ADDR : R/W ;bitpos:[21:15] ;default: 7'b0 ; */
+/*description: In the slave mode it is the value of address.*/
+#define SPI_SLV_LAST_ADDR  0x0000007F
+#define SPI_SLV_LAST_ADDR_M  ((SPI_SLV_LAST_ADDR_V)<<(SPI_SLV_LAST_ADDR_S))
+#define SPI_SLV_LAST_ADDR_V  0x7F
+#define SPI_SLV_LAST_ADDR_S  15
+/* SPI_SLV_LAST_COMMAND : R/W ;bitpos:[14:12] ;default: 3'b0 ; */
+/*description: In the slave mode it is the value of command.*/
+#define SPI_SLV_LAST_COMMAND  0x00000007
+#define SPI_SLV_LAST_COMMAND_M  ((SPI_SLV_LAST_COMMAND_V)<<(SPI_SLV_LAST_COMMAND_S))
+#define SPI_SLV_LAST_COMMAND_V  0x7
+#define SPI_SLV_LAST_COMMAND_S  12
+/* SPI_SLV_WR_DMA_DONE : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of dma write operation
+ in the slave mode.*/
+#define SPI_SLV_WR_DMA_DONE  (BIT(11))
+#define SPI_SLV_WR_DMA_DONE_M  (BIT(11))
+#define SPI_SLV_WR_DMA_DONE_V  0x1
+#define SPI_SLV_WR_DMA_DONE_S  11
+/* SPI_SLV_WR_ADDR_BYTELEN : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: In the slave mode it is the address length in bytes for write-buffer
+ operation. The register value shall be byte_num.*/
+#define SPI_SLV_WR_ADDR_BYTELEN  0x0000000F
+#define SPI_SLV_WR_ADDR_BYTELEN_M  ((SPI_SLV_WR_ADDR_BYTELEN_V)<<(SPI_SLV_WR_ADDR_BYTELEN_S))
+#define SPI_SLV_WR_ADDR_BYTELEN_V  0xF
+#define SPI_SLV_WR_ADDR_BYTELEN_S  4
+/* SPI_SLV_RD_ADDR_BYTELEN : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: In the slave mode it is the address length in bytes for read-buffer
+ operation. The register value shall be byte_num.*/
+#define SPI_SLV_RD_ADDR_BYTELEN  0x0000000F
+#define SPI_SLV_RD_ADDR_BYTELEN_M  ((SPI_SLV_RD_ADDR_BYTELEN_V)<<(SPI_SLV_RD_ADDR_BYTELEN_S))
+#define SPI_SLV_RD_ADDR_BYTELEN_V  0xF
+#define SPI_SLV_RD_ADDR_BYTELEN_S  0
+
+#define SPI_SLAVE2_REG(i)          (REG_SPI_BASE(i) + 0x03C)
+/* SPI_SLV_RD_DMA_DONE : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of dma read operation
+ in the slave mode.*/
+#define SPI_SLV_RD_DMA_DONE  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_M  (BIT(8))
+#define SPI_SLV_RD_DMA_DONE_V  0x1
+#define SPI_SLV_RD_DMA_DONE_S  8
+/* SPI_SLV_WR_DUMMY_BYTELEN : R/W ;bitpos:[7:4] ;default: 4'h0 ; */
+/*description: In the slave mode it is the length in spi_clk byte cycles of
+ dummy phase for write operations.*/
+#define SPI_SLV_WR_DUMMY_BYTELEN  0x0000000F
+#define SPI_SLV_WR_DUMMY_BYTELEN_M  ((SPI_SLV_WR_DUMMY_BYTELEN_V)<<(SPI_SLV_WR_DUMMY_BYTELEN_S))
+#define SPI_SLV_WR_DUMMY_BYTELEN_V  0xF
+#define SPI_SLV_WR_DUMMY_BYTELEN_S  4
+/* SPI_SLV_RD_DUMMY_BYTELEN : R/W ;bitpos:[3:0] ;default: 4'h0 ; */
+/*description: In the slave mode it is the length in spi_clk byte cycles of
+ dummy phase for read operations.*/
+#define SPI_SLV_RD_DUMMY_BYTELEN  0x0000000F
+#define SPI_SLV_RD_DUMMY_BYTELEN_M  ((SPI_SLV_RD_DUMMY_BYTELEN_V)<<(SPI_SLV_RD_DUMMY_BYTELEN_S))
+#define SPI_SLV_RD_DUMMY_BYTELEN_V  0xF
+#define SPI_SLV_RD_DUMMY_BYTELEN_S  0
+
+#define SPI_SLV_WRBUF_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x040)
+/* SPI_SLV_WR_BUF_DONE : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of write-buffer operation
+ in the slave mode.*/
+#define SPI_SLV_WR_BUF_DONE  (BIT(24))
+#define SPI_SLV_WR_BUF_DONE_M  (BIT(24))
+#define SPI_SLV_WR_BUF_DONE_V  0x1
+#define SPI_SLV_WR_BUF_DONE_S  24
+/* SPI_SLV_WRBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: In the slave mode it is the length in bits for write-buffer operations.
+ The register value shall be (bit_num-1).*/
+#define SPI_SLV_WRBUF_DBITLEN  0x00FFFFFF
+#define SPI_SLV_WRBUF_DBITLEN_M  ((SPI_SLV_WRBUF_DBITLEN_V)<<(SPI_SLV_WRBUF_DBITLEN_S))
+#define SPI_SLV_WRBUF_DBITLEN_V  0xFFFFFF
+#define SPI_SLV_WRBUF_DBITLEN_S  0
+
+#define SPI_SLV_RDBUF_DLEN_REG(i)          (REG_SPI_BASE(i) + 0x044)
+/* SPI_SLV_RD_BUF_DONE : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: The interrupt raw bit for the completion of read-buffer operation
+ in the slave mode.*/
+#define SPI_SLV_RD_BUF_DONE  (BIT(24))
+#define SPI_SLV_RD_BUF_DONE_M  (BIT(24))
+#define SPI_SLV_RD_BUF_DONE_V  0x1
+#define SPI_SLV_RD_BUF_DONE_S  24
+/* SPI_SLV_RDBUF_DBITLEN : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
+/*description: In the slave mode it is the length in bits for read-buffer operations.
+ The register value shall be (bit_num-1).*/
+#define SPI_SLV_RDBUF_DBITLEN  0x00FFFFFF
+#define SPI_SLV_RDBUF_DBITLEN_M  ((SPI_SLV_RDBUF_DBITLEN_V)<<(SPI_SLV_RDBUF_DBITLEN_S))
+#define SPI_SLV_RDBUF_DBITLEN_V  0xFFFFFF
+#define SPI_SLV_RDBUF_DBITLEN_S  0
+
+#define SPI_SLV_RD_BYTE_REG(i)          (REG_SPI_BASE(i) + 0x048)
+/* SPI_SLV_RDATA_BIT : RW ;bitpos:[23:0] ;default: 24'b0 ; */
+/*description: In the slave mode it is the byte number of read data.*/
+#define SPI_SLV_RDATA_BIT  0x00FFFFFF
+#define SPI_SLV_RDATA_BIT_M  ((SPI_SLV_RDATA_BIT_V)<<(SPI_SLV_RDATA_BIT_S))
+#define SPI_SLV_RDATA_BIT_V  0xFFFFFF
+#define SPI_SLV_RDATA_BIT_S  0
+
+#define SPI_FSM_REG(i)          (REG_SPI_BASE(i) + 0x050)
+/* SPI_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: The status of spi state machine. 0: idle state  1: preparation
+ state  2: send command state  3: send data state  4: red data state  5:write data state  6: wait state  7: done state.*/
+#define SPI_ST  0x00000007
+#define SPI_ST_M  ((SPI_ST_V)<<(SPI_ST_S))
+#define SPI_ST_V  0x7
+#define SPI_ST_S  0
+
+#define SPI_HOLD_REG(i)          (REG_SPI_BASE(i) + 0x054)
+/* SPI_HOLD_OUT_TIME : R/W ;bitpos:[6:4] ;default: 3'b0 ; */
+/*description: set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/
+#define SPI_HOLD_OUT_TIME  0x00000007
+#define SPI_HOLD_OUT_TIME_M  ((SPI_HOLD_OUT_TIME_V)<<(SPI_HOLD_OUT_TIME_S))
+#define SPI_HOLD_OUT_TIME_V  0x7
+#define SPI_HOLD_OUT_TIME_S  4
+/* SPI_HOLD_OUT_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: Enable set spi output hold value to spi_hold_reg. It can be used
+ to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/
+#define SPI_HOLD_OUT_EN  (BIT(3))
+#define SPI_HOLD_OUT_EN_M  (BIT(3))
+#define SPI_HOLD_OUT_EN_V  0x1
+#define SPI_HOLD_OUT_EN_S  3
+/* SPI_HOLD_VAL_REG : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: spi hold output value  which should be used with spi_hold_out_en.*/
+#define SPI_HOLD_VAL_REG  (BIT(2))
+#define SPI_HOLD_VAL_REG_M  (BIT(2))
+#define SPI_HOLD_VAL_REG_V  0x1
+#define SPI_HOLD_VAL_REG_S  2
+/* SPI_INT_HOLD_ENA : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: This register is for two SPI masters to share the same cs clock
+ and data signals. The bits of one SPI are set  if the other SPI is busy  the SPI will be hold. 1(3): hold at  idle  phase 2: hold at  prepare  phase.*/
+#define SPI_INT_HOLD_ENA  0x00000003
+#define SPI_INT_HOLD_ENA_M  ((SPI_INT_HOLD_ENA_V)<<(SPI_INT_HOLD_ENA_S))
+#define SPI_INT_HOLD_ENA_V  0x3
+#define SPI_INT_HOLD_ENA_S  0
+
+#define SPI_DMA_CONF_REG(i)          (REG_SPI_BASE(i) + 0x058)
+/* SPI_DMA_CONTINUE : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: spi dma continue tx/rx data.*/
+#define SPI_DMA_CONTINUE  (BIT(16))
+#define SPI_DMA_CONTINUE_M  (BIT(16))
+#define SPI_DMA_CONTINUE_V  0x1
+#define SPI_DMA_CONTINUE_S  16
+/* SPI_DMA_TX_STOP : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: spi dma write data stop when in continue tx/rx mode.*/
+#define SPI_DMA_TX_STOP  (BIT(15))
+#define SPI_DMA_TX_STOP_M  (BIT(15))
+#define SPI_DMA_TX_STOP_V  0x1
+#define SPI_DMA_TX_STOP_S  15
+/* SPI_DMA_RX_STOP : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: spi dma read data stop  when in continue tx/rx mode.*/
+#define SPI_DMA_RX_STOP  (BIT(14))
+#define SPI_DMA_RX_STOP_M  (BIT(14))
+#define SPI_DMA_RX_STOP_V  0x1
+#define SPI_DMA_RX_STOP_S  14
+/* SPI_MEM_TRANS_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SPI_MEM_TRANS_EN  (BIT(13))
+#define SPI_MEM_TRANS_EN_M  (BIT(13))
+#define SPI_MEM_TRANS_EN_V  0x1
+#define SPI_MEM_TRANS_EN_S  13
+/* SPI_OUT_DATA_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: spi dma read data from memory in burst mode.*/
+#define SPI_OUT_DATA_BURST_EN  (BIT(12))
+#define SPI_OUT_DATA_BURST_EN_M  (BIT(12))
+#define SPI_OUT_DATA_BURST_EN_V  0x1
+#define SPI_OUT_DATA_BURST_EN_S  12
+/* SPI_INDSCR_BURST_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: read descriptor use burst mode when write data to memory.*/
+#define SPI_INDSCR_BURST_EN  (BIT(11))
+#define SPI_INDSCR_BURST_EN_M  (BIT(11))
+#define SPI_INDSCR_BURST_EN_V  0x1
+#define SPI_INDSCR_BURST_EN_S  11
+/* SPI_OUTDSCR_BURST_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: read descriptor use burst mode when read data for memory.*/
+#define SPI_OUTDSCR_BURST_EN  (BIT(10))
+#define SPI_OUTDSCR_BURST_EN_M  (BIT(10))
+#define SPI_OUTDSCR_BURST_EN_V  0x1
+#define SPI_OUTDSCR_BURST_EN_S  10
+/* SPI_OUT_EOF_MODE : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: out eof flag generation mode . 1: when dma pop all data from
+ fifo  0:when ahb push all data to fifo.*/
+#define SPI_OUT_EOF_MODE  (BIT(9))
+#define SPI_OUT_EOF_MODE_M  (BIT(9))
+#define SPI_OUT_EOF_MODE_V  0x1
+#define SPI_OUT_EOF_MODE_S  9
+/* SPI_OUT_AUTO_WRBACK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: when the bit is set  DMA continue to use the next inlink node
+ when the length of inlink is 0.*/
+#define SPI_OUT_AUTO_WRBACK  (BIT(8))
+#define SPI_OUT_AUTO_WRBACK_M  (BIT(8))
+#define SPI_OUT_AUTO_WRBACK_V  0x1
+#define SPI_OUT_AUTO_WRBACK_S  8
+/* SPI_OUT_LOOP_TEST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: Set bit to test out link.*/
+#define SPI_OUT_LOOP_TEST  (BIT(7))
+#define SPI_OUT_LOOP_TEST_M  (BIT(7))
+#define SPI_OUT_LOOP_TEST_V  0x1
+#define SPI_OUT_LOOP_TEST_S  7
+/* SPI_IN_LOOP_TEST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: Set bit to test in link.*/
+#define SPI_IN_LOOP_TEST  (BIT(6))
+#define SPI_IN_LOOP_TEST_M  (BIT(6))
+#define SPI_IN_LOOP_TEST_V  0x1
+#define SPI_IN_LOOP_TEST_S  6
+/* SPI_AHBM_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: Reset spi dma ahb master.*/
+#define SPI_AHBM_RST  (BIT(5))
+#define SPI_AHBM_RST_M  (BIT(5))
+#define SPI_AHBM_RST_V  0x1
+#define SPI_AHBM_RST_S  5
+/* SPI_AHBM_FIFO_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: Reset spi dma ahb master fifo pointer.*/
+#define SPI_AHBM_FIFO_RST  (BIT(4))
+#define SPI_AHBM_FIFO_RST_M  (BIT(4))
+#define SPI_AHBM_FIFO_RST_V  0x1
+#define SPI_AHBM_FIFO_RST_S  4
+/* SPI_OUT_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The bit is used to reset out dma fsm and out data fifo pointer.*/
+#define SPI_OUT_RST  (BIT(3))
+#define SPI_OUT_RST_M  (BIT(3))
+#define SPI_OUT_RST_V  0x1
+#define SPI_OUT_RST_S  3
+/* SPI_IN_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The bit is used to reset in dma fsm and in data fifo pointer.*/
+#define SPI_IN_RST  (BIT(2))
+#define SPI_IN_RST_M  (BIT(2))
+#define SPI_IN_RST_V  0x1
+#define SPI_IN_RST_S  2
+
+#define SPI_DMA_OUT_LINK_REG(i)          (REG_SPI_BASE(i) + 0x05C)
+/* SPI_DMA_TX_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: spi dma write data status bit.*/
+#define SPI_DMA_TX_ENA  (BIT(31))
+#define SPI_DMA_TX_ENA_M  (BIT(31))
+#define SPI_DMA_TX_ENA_V  0x1
+#define SPI_DMA_TX_ENA_S  31
+/* SPI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set the bit to mount on new outlink descriptors.*/
+#define SPI_OUTLINK_RESTART  (BIT(30))
+#define SPI_OUTLINK_RESTART_M  (BIT(30))
+#define SPI_OUTLINK_RESTART_V  0x1
+#define SPI_OUTLINK_RESTART_S  30
+/* SPI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set the bit to start to use outlink descriptor.*/
+#define SPI_OUTLINK_START  (BIT(29))
+#define SPI_OUTLINK_START_M  (BIT(29))
+#define SPI_OUTLINK_START_V  0x1
+#define SPI_OUTLINK_START_S  29
+/* SPI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set the bit to stop to use outlink descriptor.*/
+#define SPI_OUTLINK_STOP  (BIT(28))
+#define SPI_OUTLINK_STOP_M  (BIT(28))
+#define SPI_OUTLINK_STOP_V  0x1
+#define SPI_OUTLINK_STOP_S  28
+/* SPI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of the first outlink descriptor.*/
+#define SPI_OUTLINK_ADDR  0x000FFFFF
+#define SPI_OUTLINK_ADDR_M  ((SPI_OUTLINK_ADDR_V)<<(SPI_OUTLINK_ADDR_S))
+#define SPI_OUTLINK_ADDR_V  0xFFFFF
+#define SPI_OUTLINK_ADDR_S  0
+
+#define SPI_DMA_IN_LINK_REG(i)          (REG_SPI_BASE(i) + 0x060)
+/* SPI_DMA_RX_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: spi dma read data status bit.*/
+#define SPI_DMA_RX_ENA  (BIT(31))
+#define SPI_DMA_RX_ENA_M  (BIT(31))
+#define SPI_DMA_RX_ENA_V  0x1
+#define SPI_DMA_RX_ENA_S  31
+/* SPI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: Set the bit to mount on new inlink descriptors.*/
+#define SPI_INLINK_RESTART  (BIT(30))
+#define SPI_INLINK_RESTART_M  (BIT(30))
+#define SPI_INLINK_RESTART_V  0x1
+#define SPI_INLINK_RESTART_S  30
+/* SPI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: Set the bit to start to use inlink descriptor.*/
+#define SPI_INLINK_START  (BIT(29))
+#define SPI_INLINK_START_M  (BIT(29))
+#define SPI_INLINK_START_V  0x1
+#define SPI_INLINK_START_S  29
+/* SPI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: Set the bit to stop to use inlink descriptor.*/
+#define SPI_INLINK_STOP  (BIT(28))
+#define SPI_INLINK_STOP_M  (BIT(28))
+#define SPI_INLINK_STOP_V  0x1
+#define SPI_INLINK_STOP_S  28
+/* SPI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: when the bit is set  the inlink descriptor returns to the first
+ link node when a packet is error.*/
+#define SPI_INLINK_AUTO_RET  (BIT(20))
+#define SPI_INLINK_AUTO_RET_M  (BIT(20))
+#define SPI_INLINK_AUTO_RET_V  0x1
+#define SPI_INLINK_AUTO_RET_S  20
+/* SPI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: The address of the first inlink descriptor.*/
+#define SPI_INLINK_ADDR  0x000FFFFF
+#define SPI_INLINK_ADDR_M  ((SPI_INLINK_ADDR_V)<<(SPI_INLINK_ADDR_S))
+#define SPI_INLINK_ADDR_V  0xFFFFF
+#define SPI_INLINK_ADDR_S  0
+
+#define SPI_DMA_INT_ENA_REG(i)          (REG_SPI_BASE(i) + 0x064)
+/* SPI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The enable bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_ENA  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ENA_M  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ENA_V  0x1
+#define SPI_OUT_TOTAL_EOF_INT_ENA_S  8
+/* SPI_OUT_EOF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The enable bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_ENA  (BIT(7))
+#define SPI_OUT_EOF_INT_ENA_M  (BIT(7))
+#define SPI_OUT_EOF_INT_ENA_V  0x1
+#define SPI_OUT_EOF_INT_ENA_S  7
+/* SPI_OUT_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The enable bit for completing usage of a outlink descriptor .*/
+#define SPI_OUT_DONE_INT_ENA  (BIT(6))
+#define SPI_OUT_DONE_INT_ENA_M  (BIT(6))
+#define SPI_OUT_DONE_INT_ENA_V  0x1
+#define SPI_OUT_DONE_INT_ENA_S  6
+/* SPI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The enable bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_ENA  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ENA_M  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ENA_V  0x1
+#define SPI_IN_SUC_EOF_INT_ENA_S  5
+/* SPI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The enable bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_ENA  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ENA_M  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ENA_V  0x1
+#define SPI_IN_ERR_EOF_INT_ENA_S  4
+/* SPI_IN_DONE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The enable bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_ENA  (BIT(3))
+#define SPI_IN_DONE_INT_ENA_M  (BIT(3))
+#define SPI_IN_DONE_INT_ENA_V  0x1
+#define SPI_IN_DONE_INT_ENA_S  3
+/* SPI_INLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The enable bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_ENA  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_M  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_V  0x1
+#define SPI_INLINK_DSCR_ERROR_INT_ENA_S  2
+/* SPI_OUTLINK_DSCR_ERROR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The enable bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_M  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_V  0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_ENA_S  1
+/* SPI_INLINK_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The enable bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_M  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_V  0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_ENA_S  0
+
+#define SPI_DMA_INT_RAW_REG(i)          (REG_SPI_BASE(i) + 0x068)
+/* SPI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The raw bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_RAW  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_RAW_M  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_RAW_V  0x1
+#define SPI_OUT_TOTAL_EOF_INT_RAW_S  8
+/* SPI_OUT_EOF_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The raw bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_RAW  (BIT(7))
+#define SPI_OUT_EOF_INT_RAW_M  (BIT(7))
+#define SPI_OUT_EOF_INT_RAW_V  0x1
+#define SPI_OUT_EOF_INT_RAW_S  7
+/* SPI_OUT_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The raw bit for completing usage of a outlink descriptor.*/
+#define SPI_OUT_DONE_INT_RAW  (BIT(6))
+#define SPI_OUT_DONE_INT_RAW_M  (BIT(6))
+#define SPI_OUT_DONE_INT_RAW_V  0x1
+#define SPI_OUT_DONE_INT_RAW_S  6
+/* SPI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The raw bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_RAW  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_RAW_M  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_RAW_V  0x1
+#define SPI_IN_SUC_EOF_INT_RAW_S  5
+/* SPI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The raw bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_RAW  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_RAW_M  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_RAW_V  0x1
+#define SPI_IN_ERR_EOF_INT_RAW_S  4
+/* SPI_IN_DONE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The raw bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_RAW  (BIT(3))
+#define SPI_IN_DONE_INT_RAW_M  (BIT(3))
+#define SPI_IN_DONE_INT_RAW_V  0x1
+#define SPI_IN_DONE_INT_RAW_S  3
+/* SPI_INLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The raw bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_RAW  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_M  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_V  0x1
+#define SPI_INLINK_DSCR_ERROR_INT_RAW_S  2
+/* SPI_OUTLINK_DSCR_ERROR_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The raw bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_M  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_V  0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_RAW_S  1
+/* SPI_INLINK_DSCR_EMPTY_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The raw bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_M  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_V  0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_RAW_S  0
+
+#define SPI_DMA_INT_ST_REG(i)          (REG_SPI_BASE(i) + 0x06C)
+/* SPI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The status bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_ST  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ST_M  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_ST_V  0x1
+#define SPI_OUT_TOTAL_EOF_INT_ST_S  8
+/* SPI_OUT_EOF_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The status bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_ST  (BIT(7))
+#define SPI_OUT_EOF_INT_ST_M  (BIT(7))
+#define SPI_OUT_EOF_INT_ST_V  0x1
+#define SPI_OUT_EOF_INT_ST_S  7
+/* SPI_OUT_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The status bit for completing usage of a outlink descriptor.*/
+#define SPI_OUT_DONE_INT_ST  (BIT(6))
+#define SPI_OUT_DONE_INT_ST_M  (BIT(6))
+#define SPI_OUT_DONE_INT_ST_V  0x1
+#define SPI_OUT_DONE_INT_ST_S  6
+/* SPI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The status bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_ST  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ST_M  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_ST_V  0x1
+#define SPI_IN_SUC_EOF_INT_ST_S  5
+/* SPI_IN_ERR_EOF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The status bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_ST  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ST_M  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_ST_V  0x1
+#define SPI_IN_ERR_EOF_INT_ST_S  4
+/* SPI_IN_DONE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The status bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_ST  (BIT(3))
+#define SPI_IN_DONE_INT_ST_M  (BIT(3))
+#define SPI_IN_DONE_INT_ST_V  0x1
+#define SPI_IN_DONE_INT_ST_S  3
+/* SPI_INLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The status bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_ST  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ST_M  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_ST_V  0x1
+#define SPI_INLINK_DSCR_ERROR_INT_ST_S  2
+/* SPI_OUTLINK_DSCR_ERROR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The status bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_M  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_V  0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_ST_S  1
+/* SPI_INLINK_DSCR_EMPTY_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The status bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_ST  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_M  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_V  0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_ST_S  0
+
+#define SPI_DMA_INT_CLR_REG(i)          (REG_SPI_BASE(i) + 0x070)
+/* SPI_OUT_TOTAL_EOF_INT_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: The clear bit for sending all the packets to host done.*/
+#define SPI_OUT_TOTAL_EOF_INT_CLR  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_CLR_M  (BIT(8))
+#define SPI_OUT_TOTAL_EOF_INT_CLR_V  0x1
+#define SPI_OUT_TOTAL_EOF_INT_CLR_S  8
+/* SPI_OUT_EOF_INT_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: The clear bit for sending a packet to host done.*/
+#define SPI_OUT_EOF_INT_CLR  (BIT(7))
+#define SPI_OUT_EOF_INT_CLR_M  (BIT(7))
+#define SPI_OUT_EOF_INT_CLR_V  0x1
+#define SPI_OUT_EOF_INT_CLR_S  7
+/* SPI_OUT_DONE_INT_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: The clear bit for completing usage of a outlink descriptor.*/
+#define SPI_OUT_DONE_INT_CLR  (BIT(6))
+#define SPI_OUT_DONE_INT_CLR_M  (BIT(6))
+#define SPI_OUT_DONE_INT_CLR_V  0x1
+#define SPI_OUT_DONE_INT_CLR_S  6
+/* SPI_IN_SUC_EOF_INT_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: The clear bit for completing receiving all the packets from host.*/
+#define SPI_IN_SUC_EOF_INT_CLR  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_CLR_M  (BIT(5))
+#define SPI_IN_SUC_EOF_INT_CLR_V  0x1
+#define SPI_IN_SUC_EOF_INT_CLR_S  5
+/* SPI_IN_ERR_EOF_INT_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: The clear bit for receiving error.*/
+#define SPI_IN_ERR_EOF_INT_CLR  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_CLR_M  (BIT(4))
+#define SPI_IN_ERR_EOF_INT_CLR_V  0x1
+#define SPI_IN_ERR_EOF_INT_CLR_S  4
+/* SPI_IN_DONE_INT_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: The clear bit for completing usage of a inlink descriptor.*/
+#define SPI_IN_DONE_INT_CLR  (BIT(3))
+#define SPI_IN_DONE_INT_CLR_M  (BIT(3))
+#define SPI_IN_DONE_INT_CLR_V  0x1
+#define SPI_IN_DONE_INT_CLR_S  3
+/* SPI_INLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: The clear bit for inlink descriptor error.*/
+#define SPI_INLINK_DSCR_ERROR_INT_CLR  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_M  (BIT(2))
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_V  0x1
+#define SPI_INLINK_DSCR_ERROR_INT_CLR_S  2
+/* SPI_OUTLINK_DSCR_ERROR_INT_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: The clear bit for outlink descriptor error.*/
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_M  (BIT(1))
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_V  0x1
+#define SPI_OUTLINK_DSCR_ERROR_INT_CLR_S  1
+/* SPI_INLINK_DSCR_EMPTY_INT_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: The clear bit for lack of enough inlink descriptors.*/
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_M  (BIT(0))
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_V  0x1
+#define SPI_INLINK_DSCR_EMPTY_INT_CLR_S  0
+
+#define SPI_IN_ERR_EOF_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x074)
+/* SPI_DMA_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The inlink descriptor address when spi dma produce receiving error.*/
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR  0xFFFFFFFF
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_M  ((SPI_DMA_IN_ERR_EOF_DES_ADDR_V)<<(SPI_DMA_IN_ERR_EOF_DES_ADDR_S))
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SPI_DMA_IN_ERR_EOF_DES_ADDR_S  0
+
+#define SPI_IN_SUC_EOF_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x078)
+/* SPI_DMA_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The last inlink descriptor address when spi dma produce from_suc_eof.*/
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR  0xFFFFFFFF
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_M  ((SPI_DMA_IN_SUC_EOF_DES_ADDR_V)<<(SPI_DMA_IN_SUC_EOF_DES_ADDR_S))
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SPI_DMA_IN_SUC_EOF_DES_ADDR_S  0
+
+#define SPI_INLINK_DSCR_REG(i)          (REG_SPI_BASE(i) + 0x07C)
+/* SPI_DMA_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in descriptor pointer.*/
+#define SPI_DMA_INLINK_DSCR  0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_M  ((SPI_DMA_INLINK_DSCR_V)<<(SPI_DMA_INLINK_DSCR_S))
+#define SPI_DMA_INLINK_DSCR_V  0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_S  0
+
+#define SPI_INLINK_DSCR_BF0_REG(i)          (REG_SPI_BASE(i) + 0x080)
+/* SPI_DMA_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of next in descriptor pointer.*/
+#define SPI_DMA_INLINK_DSCR_BF0  0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF0_M  ((SPI_DMA_INLINK_DSCR_BF0_V)<<(SPI_DMA_INLINK_DSCR_BF0_S))
+#define SPI_DMA_INLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF0_S  0
+
+#define SPI_INLINK_DSCR_BF1_REG(i)          (REG_SPI_BASE(i) + 0x084)
+/* SPI_DMA_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current in descriptor data buffer pointer.*/
+#define SPI_DMA_INLINK_DSCR_BF1  0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF1_M  ((SPI_DMA_INLINK_DSCR_BF1_V)<<(SPI_DMA_INLINK_DSCR_BF1_S))
+#define SPI_DMA_INLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SPI_DMA_INLINK_DSCR_BF1_S  0
+
+#define SPI_OUT_EOF_BFR_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x088)
+/* SPI_DMA_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The address of buffer relative to the outlink descriptor that produce eof.*/
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR  0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_M  ((SPI_DMA_OUT_EOF_BFR_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_BFR_DES_ADDR_S))
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_BFR_DES_ADDR_S  0
+
+#define SPI_OUT_EOF_DES_ADDR_REG(i)          (REG_SPI_BASE(i) + 0x08C)
+/* SPI_DMA_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The last outlink descriptor address when spi dma produce to_eof.*/
+#define SPI_DMA_OUT_EOF_DES_ADDR  0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_DES_ADDR_M  ((SPI_DMA_OUT_EOF_DES_ADDR_V)<<(SPI_DMA_OUT_EOF_DES_ADDR_S))
+#define SPI_DMA_OUT_EOF_DES_ADDR_V  0xFFFFFFFF
+#define SPI_DMA_OUT_EOF_DES_ADDR_S  0
+
+#define SPI_OUTLINK_DSCR_REG(i)          (REG_SPI_BASE(i) + 0x090)
+/* SPI_DMA_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out descriptor pointer.*/
+#define SPI_DMA_OUTLINK_DSCR  0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_M  ((SPI_DMA_OUTLINK_DSCR_V)<<(SPI_DMA_OUTLINK_DSCR_S))
+#define SPI_DMA_OUTLINK_DSCR_V  0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_S  0
+
+#define SPI_OUTLINK_DSCR_BF0_REG(i)          (REG_SPI_BASE(i) + 0x094)
+/* SPI_DMA_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of next out descriptor pointer.*/
+#define SPI_DMA_OUTLINK_DSCR_BF0  0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF0_M  ((SPI_DMA_OUTLINK_DSCR_BF0_V)<<(SPI_DMA_OUTLINK_DSCR_BF0_S))
+#define SPI_DMA_OUTLINK_DSCR_BF0_V  0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF0_S  0
+
+#define SPI_OUTLINK_DSCR_BF1_REG(i)          (REG_SPI_BASE(i) + 0x098)
+/* SPI_DMA_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: The content of current out descriptor data buffer pointer.*/
+#define SPI_DMA_OUTLINK_DSCR_BF1  0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF1_M  ((SPI_DMA_OUTLINK_DSCR_BF1_V)<<(SPI_DMA_OUTLINK_DSCR_BF1_S))
+#define SPI_DMA_OUTLINK_DSCR_BF1_V  0xFFFFFFFF
+#define SPI_DMA_OUTLINK_DSCR_BF1_S  0
+
+#define SPI_DMA_OUTSTATUS_REG(i)          (REG_SPI_BASE(i) + 0x09C)
+/* SPI_DMA_OUTFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: SPI dma outfifo is empty.*/
+#define SPI_DMA_OUTFIFO_EMPTY  (BIT(31))
+#define SPI_DMA_OUTFIFO_EMPTY_M  (BIT(31))
+#define SPI_DMA_OUTFIFO_EMPTY_V  0x1
+#define SPI_DMA_OUTFIFO_EMPTY_S  31
+/* SPI_DMA_OUTFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI dma outfifo is full.*/
+#define SPI_DMA_OUTFIFO_FULL  (BIT(30))
+#define SPI_DMA_OUTFIFO_FULL_M  (BIT(30))
+#define SPI_DMA_OUTFIFO_FULL_V  0x1
+#define SPI_DMA_OUTFIFO_FULL_S  30
+/* SPI_DMA_OUTFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */
+/*description: The remains of SPI dma outfifo data.*/
+#define SPI_DMA_OUTFIFO_CNT  0x0000007F
+#define SPI_DMA_OUTFIFO_CNT_M  ((SPI_DMA_OUTFIFO_CNT_V)<<(SPI_DMA_OUTFIFO_CNT_S))
+#define SPI_DMA_OUTFIFO_CNT_V  0x7F
+#define SPI_DMA_OUTFIFO_CNT_S  23
+/* SPI_DMA_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: SPI dma out data state.*/
+#define SPI_DMA_OUT_STATE  0x00000007
+#define SPI_DMA_OUT_STATE_M  ((SPI_DMA_OUT_STATE_V)<<(SPI_DMA_OUT_STATE_S))
+#define SPI_DMA_OUT_STATE_V  0x7
+#define SPI_DMA_OUT_STATE_S  20
+/* SPI_DMA_OUTDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: SPI dma out descriptor state.*/
+#define SPI_DMA_OUTDSCR_STATE  0x00000003
+#define SPI_DMA_OUTDSCR_STATE_M  ((SPI_DMA_OUTDSCR_STATE_V)<<(SPI_DMA_OUTDSCR_STATE_S))
+#define SPI_DMA_OUTDSCR_STATE_V  0x3
+#define SPI_DMA_OUTDSCR_STATE_S  18
+/* SPI_DMA_OUTDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: SPI dma out descriptor address.*/
+#define SPI_DMA_OUTDSCR_ADDR  0x0003FFFF
+#define SPI_DMA_OUTDSCR_ADDR_M  ((SPI_DMA_OUTDSCR_ADDR_V)<<(SPI_DMA_OUTDSCR_ADDR_S))
+#define SPI_DMA_OUTDSCR_ADDR_V  0x3FFFF
+#define SPI_DMA_OUTDSCR_ADDR_S  0
+
+#define SPI_DMA_INSTATUS_REG(i)          (REG_SPI_BASE(i) + 0x0A0)
+/* SPI_DMA_INFIFO_EMPTY : RO ;bitpos:[31] ;default: 1'b1 ; */
+/*description: SPI dma infifo is empty.*/
+#define SPI_DMA_INFIFO_EMPTY  (BIT(31))
+#define SPI_DMA_INFIFO_EMPTY_M  (BIT(31))
+#define SPI_DMA_INFIFO_EMPTY_V  0x1
+#define SPI_DMA_INFIFO_EMPTY_S  31
+/* SPI_DMA_INFIFO_FULL : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: SPI dma infifo is full.*/
+#define SPI_DMA_INFIFO_FULL  (BIT(30))
+#define SPI_DMA_INFIFO_FULL_M  (BIT(30))
+#define SPI_DMA_INFIFO_FULL_V  0x1
+#define SPI_DMA_INFIFO_FULL_S  30
+/* SPI_DMA_INFIFO_CNT : RO ;bitpos:[29:23] ;default: 7'b0 ; */
+/*description: The remains of SPI dma infifo data.*/
+#define SPI_DMA_INFIFO_CNT  0x0000007F
+#define SPI_DMA_INFIFO_CNT_M  ((SPI_DMA_INFIFO_CNT_V)<<(SPI_DMA_INFIFO_CNT_S))
+#define SPI_DMA_INFIFO_CNT_V  0x7F
+#define SPI_DMA_INFIFO_CNT_S  23
+/* SPI_DMA_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: SPI dma in data state.*/
+#define SPI_DMA_IN_STATE  0x00000007
+#define SPI_DMA_IN_STATE_M  ((SPI_DMA_IN_STATE_V)<<(SPI_DMA_IN_STATE_S))
+#define SPI_DMA_IN_STATE_V  0x7
+#define SPI_DMA_IN_STATE_S  20
+/* SPI_DMA_INDSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: SPI dma in descriptor state.*/
+#define SPI_DMA_INDSCR_STATE  0x00000003
+#define SPI_DMA_INDSCR_STATE_M  ((SPI_DMA_INDSCR_STATE_V)<<(SPI_DMA_INDSCR_STATE_S))
+#define SPI_DMA_INDSCR_STATE_V  0x3
+#define SPI_DMA_INDSCR_STATE_S  18
+/* SPI_DMA_INDSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: SPI dma in descriptor address.*/
+#define SPI_DMA_INDSCR_ADDR  0x0003FFFF
+#define SPI_DMA_INDSCR_ADDR_M  ((SPI_DMA_INDSCR_ADDR_V)<<(SPI_DMA_INDSCR_ADDR_S))
+#define SPI_DMA_INDSCR_ADDR_V  0x3FFFF
+#define SPI_DMA_INDSCR_ADDR_S  0
+
+#define SPI_W0_REG(i)          (REG_SPI_BASE(i) + 0x0A4)
+/* SPI_BUF0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF0  0xFFFFFFFF
+#define SPI_BUF0_M  ((SPI_BUF0_V)<<(SPI_BUF0_S))
+#define SPI_BUF0_V  0xFFFFFFFF
+#define SPI_BUF0_S  0
+
+#define SPI_W1_REG(i)          (REG_SPI_BASE(i) + 0x0A8)
+/* SPI_BUF1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF1  0xFFFFFFFF
+#define SPI_BUF1_M  ((SPI_BUF1_V)<<(SPI_BUF1_S))
+#define SPI_BUF1_V  0xFFFFFFFF
+#define SPI_BUF1_S  0
+
+#define SPI_W2_REG(i)          (REG_SPI_BASE(i) + 0x0AC)
+/* SPI_BUF2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF2  0xFFFFFFFF
+#define SPI_BUF2_M  ((SPI_BUF2_V)<<(SPI_BUF2_S))
+#define SPI_BUF2_V  0xFFFFFFFF
+#define SPI_BUF2_S  0
+
+#define SPI_W3_REG(i)          (REG_SPI_BASE(i) + 0x0B0)
+/* SPI_BUF3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF3  0xFFFFFFFF
+#define SPI_BUF3_M  ((SPI_BUF3_V)<<(SPI_BUF3_S))
+#define SPI_BUF3_V  0xFFFFFFFF
+#define SPI_BUF3_S  0
+
+#define SPI_W4_REG(i)          (REG_SPI_BASE(i) + 0x0B4)
+/* SPI_BUF4 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF4  0xFFFFFFFF
+#define SPI_BUF4_M  ((SPI_BUF4_V)<<(SPI_BUF4_S))
+#define SPI_BUF4_V  0xFFFFFFFF
+#define SPI_BUF4_S  0
+
+#define SPI_W5_REG(i)          (REG_SPI_BASE(i) + 0x0B8)
+/* SPI_BUF5 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF5  0xFFFFFFFF
+#define SPI_BUF5_M  ((SPI_BUF5_V)<<(SPI_BUF5_S))
+#define SPI_BUF5_V  0xFFFFFFFF
+#define SPI_BUF5_S  0
+
+#define SPI_W6_REG(i)          (REG_SPI_BASE(i) + 0x0BC)
+/* SPI_BUF6 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF6  0xFFFFFFFF
+#define SPI_BUF6_M  ((SPI_BUF6_V)<<(SPI_BUF6_S))
+#define SPI_BUF6_V  0xFFFFFFFF
+#define SPI_BUF6_S  0
+
+#define SPI_W7_REG(i)          (REG_SPI_BASE(i) + 0x0C0)
+/* SPI_BUF7 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF7  0xFFFFFFFF
+#define SPI_BUF7_M  ((SPI_BUF7_V)<<(SPI_BUF7_S))
+#define SPI_BUF7_V  0xFFFFFFFF
+#define SPI_BUF7_S  0
+
+#define SPI_W8_REG(i)          (REG_SPI_BASE(i) + 0x0C4)
+/* SPI_BUF8 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF8  0xFFFFFFFF
+#define SPI_BUF8_M  ((SPI_BUF8_V)<<(SPI_BUF8_S))
+#define SPI_BUF8_V  0xFFFFFFFF
+#define SPI_BUF8_S  0
+
+#define SPI_W9_REG(i)          (REG_SPI_BASE(i) + 0x0C8)
+/* SPI_BUF9 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF9  0xFFFFFFFF
+#define SPI_BUF9_M  ((SPI_BUF9_V)<<(SPI_BUF9_S))
+#define SPI_BUF9_V  0xFFFFFFFF
+#define SPI_BUF9_S  0
+
+#define SPI_W10_REG(i)          (REG_SPI_BASE(i) + 0x0CC)
+/* SPI_BUF10 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF10  0xFFFFFFFF
+#define SPI_BUF10_M  ((SPI_BUF10_V)<<(SPI_BUF10_S))
+#define SPI_BUF10_V  0xFFFFFFFF
+#define SPI_BUF10_S  0
+
+#define SPI_W11_REG(i)          (REG_SPI_BASE(i) + 0x0D0)
+/* SPI_BUF11 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF11  0xFFFFFFFF
+#define SPI_BUF11_M  ((SPI_BUF11_V)<<(SPI_BUF11_S))
+#define SPI_BUF11_V  0xFFFFFFFF
+#define SPI_BUF11_S  0
+
+#define SPI_W12_REG(i)          (REG_SPI_BASE(i) + 0x0D4)
+/* SPI_BUF12 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF12  0xFFFFFFFF
+#define SPI_BUF12_M  ((SPI_BUF12_V)<<(SPI_BUF12_S))
+#define SPI_BUF12_V  0xFFFFFFFF
+#define SPI_BUF12_S  0
+
+#define SPI_W13_REG(i)          (REG_SPI_BASE(i) + 0x0D8)
+/* SPI_BUF13 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF13  0xFFFFFFFF
+#define SPI_BUF13_M  ((SPI_BUF13_V)<<(SPI_BUF13_S))
+#define SPI_BUF13_V  0xFFFFFFFF
+#define SPI_BUF13_S  0
+
+#define SPI_W14_REG(i)          (REG_SPI_BASE(i) + 0x0DC)
+/* SPI_BUF14 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF14  0xFFFFFFFF
+#define SPI_BUF14_M  ((SPI_BUF14_V)<<(SPI_BUF14_S))
+#define SPI_BUF14_V  0xFFFFFFFF
+#define SPI_BUF14_S  0
+
+#define SPI_W15_REG(i)          (REG_SPI_BASE(i) + 0x0E0)
+/* SPI_BUF15 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF15  0xFFFFFFFF
+#define SPI_BUF15_M  ((SPI_BUF15_V)<<(SPI_BUF15_S))
+#define SPI_BUF15_V  0xFFFFFFFF
+#define SPI_BUF15_S  0
+
+#define SPI_W16_REG(i)          (REG_SPI_BASE(i) + 0x0E4)
+/* SPI_BUF16 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF16  0xFFFFFFFF
+#define SPI_BUF16_M  ((SPI_BUF16_V)<<(SPI_BUF16_S))
+#define SPI_BUF16_V  0xFFFFFFFF
+#define SPI_BUF16_S  0
+
+#define SPI_W17_REG(i)          (REG_SPI_BASE(i) + 0x0E8)
+/* SPI_BUF17 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: data buffer*/
+#define SPI_BUF17  0xFFFFFFFF
+#define SPI_BUF17_M  ((SPI_BUF17_V)<<(SPI_BUF17_S))
+#define SPI_BUF17_V  0xFFFFFFFF
+#define SPI_BUF17_S  0
+
+#define SPI_DIN_MODE_REG(i)          (REG_SPI_BASE(i) + 0x0EC)
+/* SPI_DIN3_DLY_EDGE : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify input line timing.*/
+#define SPI_DIN3_DLY_EDGE  (BIT(21))
+#define SPI_DIN3_DLY_EDGE_M  (BIT(21))
+#define SPI_DIN3_DLY_EDGE_V  0x1
+#define SPI_DIN3_DLY_EDGE_S  21
+/* SPI_DIN2_DLY_EDGE : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify input line timing.*/
+#define SPI_DIN2_DLY_EDGE  (BIT(20))
+#define SPI_DIN2_DLY_EDGE_M  (BIT(20))
+#define SPI_DIN2_DLY_EDGE_V  0x1
+#define SPI_DIN2_DLY_EDGE_S  20
+/* SPI_DIN1_DLY_EDGE : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify input line timing.*/
+#define SPI_DIN1_DLY_EDGE  (BIT(19))
+#define SPI_DIN1_DLY_EDGE_M  (BIT(19))
+#define SPI_DIN1_DLY_EDGE_V  0x1
+#define SPI_DIN1_DLY_EDGE_S  19
+/* SPI_DIN0_DLY_EDGE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify input line timing.*/
+#define SPI_DIN0_DLY_EDGE  (BIT(18))
+#define SPI_DIN0_DLY_EDGE_M  (BIT(18))
+#define SPI_DIN0_DLY_EDGE_V  0x1
+#define SPI_DIN0_DLY_EDGE_S  18
+/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+#define SPI_DIN3_MODE  0x00000003
+#define SPI_DIN3_MODE_M  ((SPI_DIN3_MODE_V)<<(SPI_DIN3_MODE_S))
+#define SPI_DIN3_MODE_V  0x3
+#define SPI_DIN3_MODE_S  6
+/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+#define SPI_DIN2_MODE  0x00000003
+#define SPI_DIN2_MODE_M  ((SPI_DIN2_MODE_V)<<(SPI_DIN2_MODE_S))
+#define SPI_DIN2_MODE_V  0x3
+#define SPI_DIN2_MODE_S  4
+/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+#define SPI_DIN1_MODE  0x00000003
+#define SPI_DIN1_MODE_M  ((SPI_DIN1_MODE_V)<<(SPI_DIN1_MODE_S))
+#define SPI_DIN1_MODE_V  0x3
+#define SPI_DIN1_MODE_S  2
+/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: input
+ without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+#define SPI_DIN0_MODE  0x00000003
+#define SPI_DIN0_MODE_M  ((SPI_DIN0_MODE_V)<<(SPI_DIN0_MODE_S))
+#define SPI_DIN0_MODE_V  0x3
+#define SPI_DIN0_MODE_S  0
+
+#define SPI_DIN_NUM_REG(i)          (REG_SPI_BASE(i) + 0x0F0)
+/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DIN3_NUM  0x00000003
+#define SPI_DIN3_NUM_M  ((SPI_DIN3_NUM_V)<<(SPI_DIN3_NUM_S))
+#define SPI_DIN3_NUM_V  0x3
+#define SPI_DIN3_NUM_S  6
+/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DIN2_NUM  0x00000003
+#define SPI_DIN2_NUM_M  ((SPI_DIN2_NUM_V)<<(SPI_DIN2_NUM_S))
+#define SPI_DIN2_NUM_V  0x3
+#define SPI_DIN2_NUM_S  4
+/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DIN1_NUM  0x00000003
+#define SPI_DIN1_NUM_M  ((SPI_DIN1_NUM_V)<<(SPI_DIN1_NUM_S))
+#define SPI_DIN1_NUM_V  0x3
+#define SPI_DIN1_NUM_S  2
+/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the input signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DIN0_NUM  0x00000003
+#define SPI_DIN0_NUM_M  ((SPI_DIN0_NUM_V)<<(SPI_DIN0_NUM_S))
+#define SPI_DIN0_NUM_V  0x3
+#define SPI_DIN0_NUM_S  0
+
+#define SPI_DOUT_MODE_REG(i)          (REG_SPI_BASE(i) + 0x0F4)
+/* SPI_DOUT4_DLY_EDGE : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify output line timing.*/
+#define SPI_DOUT4_DLY_EDGE  (BIT(22))
+#define SPI_DOUT4_DLY_EDGE_M  (BIT(22))
+#define SPI_DOUT4_DLY_EDGE_V  0x1
+#define SPI_DOUT4_DLY_EDGE_S  22
+/* SPI_DOUT3_DLY_EDGE : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify output line timing.*/
+#define SPI_DOUT3_DLY_EDGE  (BIT(21))
+#define SPI_DOUT3_DLY_EDGE_M  (BIT(21))
+#define SPI_DOUT3_DLY_EDGE_V  0x1
+#define SPI_DOUT3_DLY_EDGE_S  21
+/* SPI_DOUT2_DLY_EDGE : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify output line timing.*/
+#define SPI_DOUT2_DLY_EDGE  (BIT(20))
+#define SPI_DOUT2_DLY_EDGE_M  (BIT(20))
+#define SPI_DOUT2_DLY_EDGE_V  0x1
+#define SPI_DOUT2_DLY_EDGE_S  20
+/* SPI_DOUT1_DLY_EDGE : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify output line timing.*/
+#define SPI_DOUT1_DLY_EDGE  (BIT(19))
+#define SPI_DOUT1_DLY_EDGE_M  (BIT(19))
+#define SPI_DOUT1_DLY_EDGE_V  0x1
+#define SPI_DOUT1_DLY_EDGE_S  19
+/* SPI_DOUT0_DLY_EDGE : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: The bit is used to select the spi clock edge to modify output line timing.*/
+#define SPI_DOUT0_DLY_EDGE  (BIT(18))
+#define SPI_DOUT0_DLY_EDGE_M  (BIT(18))
+#define SPI_DOUT0_DLY_EDGE_V  0x1
+#define SPI_DOUT0_DLY_EDGE_S  18
+/* SPI_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+#define SPI_DOUT4_MODE  0x00000003
+#define SPI_DOUT4_MODE_M  ((SPI_DOUT4_MODE_V)<<(SPI_DOUT4_MODE_S))
+#define SPI_DOUT4_MODE_V  0x3
+#define SPI_DOUT4_MODE_S  8
+/* SPI_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+#define SPI_DOUT3_MODE  0x00000003
+#define SPI_DOUT3_MODE_M  ((SPI_DOUT3_MODE_V)<<(SPI_DOUT3_MODE_S))
+#define SPI_DOUT3_MODE_V  0x3
+#define SPI_DOUT3_MODE_S  6
+/* SPI_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+#define SPI_DOUT2_MODE  0x00000003
+#define SPI_DOUT2_MODE_M  ((SPI_DOUT2_MODE_V)<<(SPI_DOUT2_MODE_S))
+#define SPI_DOUT2_MODE_V  0x3
+#define SPI_DOUT2_MODE_S  4
+/* SPI_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+#define SPI_DOUT1_MODE  0x00000003
+#define SPI_DOUT1_MODE_M  ((SPI_DOUT1_MODE_V)<<(SPI_DOUT1_MODE_S))
+#define SPI_DOUT1_MODE_V  0x3
+#define SPI_DOUT1_MODE_S  2
+/* SPI_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: output
+ without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+#define SPI_DOUT0_MODE  0x00000003
+#define SPI_DOUT0_MODE_M  ((SPI_DOUT0_MODE_V)<<(SPI_DOUT0_MODE_S))
+#define SPI_DOUT0_MODE_V  0x3
+#define SPI_DOUT0_MODE_S  0
+
+#define SPI_DOUT_NUM_REG(i)          (REG_SPI_BASE(i) + 0x0F8)
+/* SPI_DOUT4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DOUT4_NUM  0x00000003
+#define SPI_DOUT4_NUM_M  ((SPI_DOUT4_NUM_V)<<(SPI_DOUT4_NUM_S))
+#define SPI_DOUT4_NUM_V  0x3
+#define SPI_DOUT4_NUM_S  8
+/* SPI_DOUT3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DOUT3_NUM  0x00000003
+#define SPI_DOUT3_NUM_M  ((SPI_DOUT3_NUM_V)<<(SPI_DOUT3_NUM_S))
+#define SPI_DOUT3_NUM_V  0x3
+#define SPI_DOUT3_NUM_S  6
+/* SPI_DOUT2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DOUT2_NUM  0x00000003
+#define SPI_DOUT2_NUM_M  ((SPI_DOUT2_NUM_V)<<(SPI_DOUT2_NUM_S))
+#define SPI_DOUT2_NUM_V  0x3
+#define SPI_DOUT2_NUM_S  4
+/* SPI_DOUT1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DOUT1_NUM  0x00000003
+#define SPI_DOUT1_NUM_M  ((SPI_DOUT1_NUM_V)<<(SPI_DOUT1_NUM_S))
+#define SPI_DOUT1_NUM_V  0x3
+#define SPI_DOUT1_NUM_S  2
+/* SPI_DOUT0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
+/*description: the output signals are delayed by system clock cycles  0: delayed
+ by 1 cycle  1: delayed by 2 cycles ...*/
+#define SPI_DOUT0_NUM  0x00000003
+#define SPI_DOUT0_NUM_M  ((SPI_DOUT0_NUM_V)<<(SPI_DOUT0_NUM_S))
+#define SPI_DOUT0_NUM_V  0x3
+#define SPI_DOUT0_NUM_S  0
+
+#define SPI_SPR_CFG0_REG(i)          (REG_SPI_BASE(i) + 0x0FC)
+/* SPI_SOP_DQS_EDGE : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define SPI_SOP_DQS_EDGE  (BIT(21))
+#define SPI_SOP_DQS_EDGE_M  (BIT(21))
+#define SPI_SOP_DQS_EDGE_V  0x1
+#define SPI_SOP_DQS_EDGE_S  21
+/* SPI_SOP_WCMD : R/W ;bitpos:[20:13] ;default: 8'd2 ; */
+/*description: */
+#define SPI_SOP_WCMD  0x000000FF
+#define SPI_SOP_WCMD_M  ((SPI_SOP_WCMD_V)<<(SPI_SOP_WCMD_S))
+#define SPI_SOP_WCMD_V  0xFF
+#define SPI_SOP_WCMD_S  13
+/* SPI_SOP_RCMD : R/W ;bitpos:[12:5] ;default: 8'd3 ; */
+/*description: */
+#define SPI_SOP_RCMD  0x000000FF
+#define SPI_SOP_RCMD_M  ((SPI_SOP_RCMD_V)<<(SPI_SOP_RCMD_S))
+#define SPI_SOP_RCMD_V  0xFF
+#define SPI_SOP_RCMD_S  5
+/* SPI_SOP_MODE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */
+/*description: */
+#define SPI_SOP_MODE  0x0000000F
+#define SPI_SOP_MODE_M  ((SPI_SOP_MODE_V)<<(SPI_SOP_MODE_S))
+#define SPI_SOP_MODE_V  0xF
+#define SPI_SOP_MODE_S  1
+/* SPI_SOP_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SPI_SOP_EN  (BIT(0))
+#define SPI_SOP_EN_M  (BIT(0))
+#define SPI_SOP_EN_V  0x1
+#define SPI_SOP_EN_S  0
+
+#define SPI_SPR_CFG1_REG(i)          (REG_SPI_BASE(i) + 0x100)
+/* SPI_SOP_DC_MODE : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define SPI_SOP_DC_MODE  (BIT(24))
+#define SPI_SOP_DC_MODE_M  (BIT(24))
+#define SPI_SOP_DC_MODE_V  0x1
+#define SPI_SOP_DC_MODE_S  24
+/* SPI_SOP_DLEN : R/W ;bitpos:[23:18] ;default: 6'd0 ; */
+/*description: */
+#define SPI_SOP_DLEN  0x0000003F
+#define SPI_SOP_DLEN_M  ((SPI_SOP_DLEN_V)<<(SPI_SOP_DLEN_S))
+#define SPI_SOP_DLEN_V  0x3F
+#define SPI_SOP_DLEN_S  18
+/* SPI_SOP_LEN : R/W ;bitpos:[17:12] ;default: 6'd0 ; */
+/*description: */
+#define SPI_SOP_LEN  0x0000003F
+#define SPI_SOP_LEN_M  ((SPI_SOP_LEN_V)<<(SPI_SOP_LEN_S))
+#define SPI_SOP_LEN_V  0x3F
+#define SPI_SOP_LEN_S  12
+/* SPI_SOP_ITL : R/W ;bitpos:[11:0] ;default: 12'd0 ; */
+/*description: */
+#define SPI_SOP_ITL  0x00000FFF
+#define SPI_SOP_ITL_M  ((SPI_SOP_ITL_V)<<(SPI_SOP_ITL_S))
+#define SPI_SOP_ITL_V  0xFFF
+#define SPI_SOP_ITL_S  0
+
+#define SPI_DATE_REG(i)          (REG_SPI_BASE(i) + 0x3FC)
+/* SPI_DATE : RW ;bitpos:[27:0] ;default: 32'h1809190 ; */
+/*description: SPI register version.*/
+#define SPI_DATE  0x0FFFFFFF
+#define SPI_DATE_M  ((SPI_DATE_V)<<(SPI_DATE_S))
+#define SPI_DATE_V  0xFFFFFFF
+#define SPI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SPI_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/spi_struct.h b/components/soc/esp32s2beta/include/soc/spi_struct.h
new file mode 100644
index 000000000..b2c19b969
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/spi_struct.h
@@ -0,0 +1,677 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SPI_STRUCT_H_
+#define _SOC_SPI_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t reserved0: 18;                       /*reserved*/
+            uint32_t usr:        1;                       /*User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.*/
+            uint32_t reserved19:13;
+        };
+        uint32_t val;
+    } cmd;
+    uint32_t addr;                                        /*[31:8]:address to slave  [7:0]:Reserved.*/
+    union {
+        struct {
+            uint32_t reserved0:       2;                  /*reserved*/
+            uint32_t ext_hold_en:     1;                  /*Set the bit to hold spi. The bit is combined with spi_usr_prep_hold spi_usr_cmd_hold spi_usr_addr_hold spi_usr_dummy_hold spi_usr_din_hold spi_usr_dout_hold and spi_usr_hold_pol.*/
+            uint32_t dummy_out:       1;                  /*In the dummy phase the signal level of spi is output by the spi controller.*/
+            uint32_t reserved4:       1;                  /*reserved*/
+            uint32_t faddr_dual:      1;                  /*Apply 2 signals during addr phase 1:enable 0: disable*/
+            uint32_t faddr_quad:      1;                  /*Apply 4 signals during addr phase 1:enable 0: disable*/
+            uint32_t fcmd_dual:       1;                  /*Apply 2 signals during command phase 1:enable 0: disable*/
+            uint32_t fcmd_quad:       1;                  /*Apply 4 signals during command phase 1:enable 0: disable*/
+            uint32_t reserved9:       4;
+            uint32_t fast_rd_mode:    1;                  /*Enable 2/4 lines addr command  including read and write command.*/
+            uint32_t fread_dual:      1;                  /*In the read operations  read-data phase apply 2 signals. 1: enable 0: disable.*/
+            uint32_t reserved15:      3;
+            uint32_t q_pol:           1;                  /*The bit is used to set MISO line polarity  1: high 0  low*/
+            uint32_t d_pol:           1;                  /*The bit is used to set MOSI line polarity  1: high 0  low*/
+            uint32_t fread_quad:      1;                  /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
+            uint32_t wp:              1;                  /*Write protect signal output when SPI is idle.  1: output high  0: output low.*/
+            uint32_t reserved22:      3;                  /*reserved*/
+            uint32_t rd_bit_order:    1;                  /*In read-data (MISO) phase 1: LSB first 0: MSB first*/
+            uint32_t wr_bit_order:    1;                  /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first*/
+            uint32_t define_addr:     1;                  /*set spi_usr_addr and spi_usr_addr_value in spi defined slave mode. 1: disable 0:enable.*/
+            uint32_t reserved28:      4;                  /*reserved*/
+        };
+        uint32_t val;
+    } ctrl;
+    union {
+        struct {
+            uint32_t clk_mode:      2;                    /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
+            uint32_t clk_mode_13:   1;                    /*{CPOL  CPHA} 1: support spi clk mode 1 and 3  first edge output data B[0]/B[7]*/
+            uint32_t rsck_data_out: 1;                    /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge*/
+            uint32_t w16_17_wr_ena: 1;                    /*1:reg_buf[16] [17] can be written   0:reg_buf[16] [17] can not  be written.*/
+            uint32_t reserved5:     9;                    /*reserved*/
+            uint32_t cs_hold_delay: 6;                    /*SPI cs signal is delayed by spi clock cycles.*/
+            uint32_t reserved20:   12;
+        };
+        uint32_t val;
+    } ctrl1;
+    union {
+        struct {
+            uint32_t cs_setup_time:13;                    /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit.*/
+            uint32_t cs_hold_time: 13;                    /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.*/
+            uint32_t cs_delay_mode: 2;                    /*spi_cs signal is delayed by spi_clk . 0: zero 1: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by half cycle  else delayed by one cycle 2: if spi_ck_out_edge or spi_ck_i_edge is set 1 delayed by one cycle  else delayed by half cycle 3: delayed one cycle*/
+            uint32_t cs_delay_num:  2;                    /*spi_cs signal is delayed by system clock cycles*/
+            uint32_t reserved30:    1;                    /*reserved*/
+            uint32_t cs_delay_edge: 1;
+        };
+        uint32_t val;
+    } ctrl2;
+    union {
+        struct {
+            uint32_t clkcnt_l:       6;                   /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0.*/
+            uint32_t clkcnt_h:       6;                   /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0.*/
+            uint32_t clkcnt_n:       6;                   /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1)*/
+            uint32_t clkdiv_pre:    13;                   /*In the master mode it is pre-divider of spi_clk.*/
+            uint32_t clk_equ_sysclk: 1;                   /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock.*/
+        };
+        uint32_t val;
+    } clock;
+    union {
+        struct {
+            uint32_t doutdin:           1;                /*Set the bit to enable full duplex communication. 1: enable 0: disable.*/
+            uint32_t tx_start_bit:      3;                /*It determines the start time of tx output data. It can be used for timing adjustment in MISO slave mode.*/
+            uint32_t reserved4:         1;                /*reserved*/
+            uint32_t tsck_i_edge:       1;                /*In the slave mode  this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/
+            uint32_t cs_hold:           1;                /*spi cs keep low when spi is in  done  phase. 1: enable 0: disable.*/
+            uint32_t cs_setup:          1;                /*spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.*/
+            uint32_t rsck_i_edge:       1;                /*In the slave mode  this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/
+            uint32_t ck_out_edge:       1;                /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.*/
+            uint32_t rd_byte_order:     1;                /*In read-data (MISO) phase 1: big-endian 0: little_endian*/
+            uint32_t wr_byte_order:     1;                /*In command address write-data (MOSI) phases 1: big-endian 0: litte_endian*/
+            uint32_t fwrite_dual:       1;                /*In the write operations read-data phase apply 2 signals*/
+            uint32_t fwrite_quad:       1;                /*In the write operations read-data phase apply 4 signals*/
+            uint32_t reserved14:        1;                /*reserved*/
+            uint32_t reserved15:        1;                /*reserved*/
+            uint32_t sio:               1;                /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable.*/
+            uint32_t usr_hold_pol:      1;                /*It is combined with hold bits to set the polarity of spi hold line 1: spi will be held when spi hold line is high 0: spi will be held when spi hold line is low*/
+            uint32_t usr_dout_hold:     1;                /*spi is hold at data out state the bit are combined with spi_usr_hold_pol bit.*/
+            uint32_t usr_din_hold:      1;                /*spi is hold at data in state the bit are combined with spi_usr_hold_pol bit.*/
+            uint32_t usr_dummy_hold:    1;                /*spi is hold at dummy state the bit are combined with spi_usr_hold_pol bit.*/
+            uint32_t usr_addr_hold:     1;                /*spi is hold at address state the bit are combined with spi_usr_hold_pol bit.*/
+            uint32_t usr_cmd_hold:      1;                /*spi is hold at command state the bit are combined with spi_usr_hold_pol bit.*/
+            uint32_t usr_prep_hold:     1;                /*spi is hold at prepare state the bit are combined with spi_usr_hold_pol bit.*/
+            uint32_t usr_miso_highpart: 1;                /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
+            uint32_t usr_mosi_highpart: 1;                /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.*/
+            uint32_t usr_dummy_idle:    1;                /*spi clock is disable in dummy phase when the bit is enable.*/
+            uint32_t usr_mosi:          1;                /*This bit enable the write-data phase of an operation.*/
+            uint32_t usr_miso:          1;                /*This bit enable the read-data phase of an operation.*/
+            uint32_t usr_dummy:         1;                /*This bit enable the dummy phase of an operation.*/
+            uint32_t usr_addr:          1;                /*This bit enable the address phase of an operation.*/
+            uint32_t usr_command:       1;                /*This bit enable the command phase of an operation.*/
+        };
+        uint32_t val;
+    } user;
+    union {
+        struct {
+            uint32_t usr_dummy_cyclelen: 8;               /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
+            uint32_t reserved8:         18;               /*reserved*/
+            uint32_t usr_addr_bitlen:    6;               /*The length in bits of address phase. The register value shall be (bit_num-1).*/
+        };
+        uint32_t val;
+    } user1;
+    union {
+        struct {
+            uint32_t usr_command_value: 16;               /*The value of  command.*/
+            uint32_t reserved16:        12;               /*reserved*/
+            uint32_t usr_command_bitlen: 4;               /*The length in bits of command phase. The register value shall be (bit_num-1)*/
+        };
+        uint32_t val;
+    } user2;
+    union {
+        struct {
+            uint32_t usr_mosi_bit_len:24;                 /*The length in bits of write-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved24:       8;                 /*reserved*/
+        };
+        uint32_t val;
+    } mosi_dlen;
+    union {
+        struct {
+            uint32_t usr_miso_bit_len:24;                 /*The length in bits of  read-data. The register value shall be (bit_num-1).*/
+            uint32_t reserved24:       8;                 /*reserved*/
+        };
+        uint32_t val;
+    } miso_dlen;
+    uint32_t slv_wr_status;                               /*In the master mode this register are the higher 32bits in the 64 bits address condition.*/
+    union {
+        struct {
+            uint32_t cs0_dis:           1;                /*SPI CS0 pin enable  1: disable CS0  0: spi_cs0 signal is from/to CS0 pin*/
+            uint32_t cs1_dis:           1;                /*SPI CS1 pin enable  1: disable CS1  0: spi_cs1 signal is from/to CS1 pin*/
+            uint32_t cs2_dis:           1;                /*SPI CS2 pin enable  1: disable CS2  0: spi_cs2 signal is from/to CS2 pin*/
+            uint32_t reserved3:         2;                /*reserved*/
+            uint32_t ck_dis:            1;                /*1: spi clk out disable   0: spi clk out enable*/
+            uint32_t master_cs_pol:     3;                /*In the master mode the bits are the polarity of spi cs line  the value is equivalent to spi_cs ^ spi_master_cs_pol.*/
+            uint32_t reserved9:        14;                /*reserved*/
+            uint32_t slave_cs_pol:      1;                /*spi slave input cs polarity select. 1: inv  0: not change*/
+            uint32_t reserved24:        3;                /*reserved*/
+            uint32_t q_idle_out:        1;                /*The idle output value of spi_q.*/
+            uint32_t reserved28:        1;                /*reserved*/
+            uint32_t ck_idle_edge:      1;                /*1: spi clk line is high when idle     0: spi clk line is low when idle*/
+            uint32_t cs_keep_active:    1;                /*spi cs line keep low when the bit is set.*/
+            uint32_t quad_din_pin_swap: 1;                /*1:  spi quad input swap enable  0:  spi quad input swap disable*/
+        };
+        uint32_t val;
+    } misc;
+    union {
+        struct {
+            uint32_t reserved0:  4;                       /*reserved*/
+            uint32_t trans_done: 1;                       /*The interrupt raw bit for the completion of any operation in both the master mode and the slave mode.*/
+            uint32_t rd_buf_inten:     1;                   /*The interrupt enable bit for the completion of read-buffer operation in the slave mode.*/
+            uint32_t wr_buf_inten:     1;                   /*The interrupt enable bit for the completion of write-buffer operation in the slave mode.*/
+            uint32_t rd_dma_inten:     1;                   /*The interrupt enable bit for the completion of read-status operation in the slave mode.*/
+            uint32_t wr_dma_inten:     1;                   /*The interrupt enable bit for the completion of write-status operation in the slave mode.*/
+            uint32_t trans_inten:      1;                   /*The interrupt enable bit for the completion of any operation in both the master mode and the slave mode.*/
+            uint32_t reserved10:13;                       /*reserved*/
+            uint32_t trans_cnt:  4;                       /*The operations counter in both the master mode and the slave mode.*/
+            uint32_t reserved27: 1;                       /*reserved*/
+            uint32_t reserved28: 1;                       /*reserved*/
+            uint32_t reserved29: 1;                       /*reserved*/
+            uint32_t slave_mode: 1;                       /*Set SPI work mode. 1: slave mode 0: master mode.*/
+            uint32_t sync_reset: 1;                       /*Software reset enable  reset the spi clock line cs line and data lines.*/
+        };
+        uint32_t val;
+    } slave;
+    union {
+        struct {
+            uint32_t rd_addr_bytelen:     4;              /*In the slave mode it is the address length in bytes for read-buffer operation. The register value shall be byte_num.*/
+            uint32_t wr_addr_bytelen:     4;              /*In the slave mode it is the address length in bytes for write-buffer operation. The register value shall be byte_num.*/
+            uint32_t reserved8:           3;              /*reserved*/
+            uint32_t wr_dma_done:         1;              /*The interrupt raw bit for the completion of dma write operation in the slave mode.*/
+            uint32_t last_command:        3;              /*In the slave mode it is the value of command.*/
+            uint32_t last_addr:           7;              /*In the slave mode it is the value of address.*/
+            uint32_t reserved22:         10;              /*reserved*/
+        };
+        uint32_t val;
+    } slave1;
+    union {
+        struct {
+            uint32_t rd_dummy_bytelen:     4;             /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for read operations.*/
+            uint32_t wr_dummy_bytelen:     4;             /*In the slave mode it is the length in spi_clk byte cycles of dummy phase for write operations.*/
+            uint32_t rd_dma_done:          1;             /*The interrupt raw bit for the completion of dma read operation in the slave mode.*/
+            uint32_t reserved9:           23;             /*reserved*/
+        };
+        uint32_t val;
+    } slave2;
+    union {
+        struct {
+            uint32_t bit_len:          24;                /*In the slave mode it is the length in bits for write-buffer operations. The register value shall be (bit_num-1).*/
+            uint32_t wr_buf_done:       1;                /*The interrupt raw bit for the completion of write-buffer operation in the slave mode.*/
+            uint32_t reserved25:        7;                /*reserved*/
+        };
+        uint32_t val;
+    } slv_wrbuf_dlen;
+    union {
+        struct {
+            uint32_t bit_len:          24;                /*In the slave mode it is the length in bits for read-buffer operations. The register value shall be (bit_num-1).*/
+            uint32_t rd_buf_done:       1;                /*The interrupt raw bit for the completion of read-buffer operation in the slave mode.*/
+            uint32_t reserved25:        7;                /*reserved*/
+        };
+        uint32_t val;
+    } slv_rdbuf_dlen;
+    union {
+        struct {
+            uint32_t slv_rdata_bit:24;                    /*In the slave mode it is the byte number of read data.*/
+            uint32_t reserved24:    8;                    /*reserved*/
+        };
+        uint32_t val;
+    } slv_rd_byte;
+    uint32_t reserved_4c;
+    union {
+        struct {
+            uint32_t st:         3;                       /*The status of spi state machine. 0: idle state  1: preparation state  2: send command state  3: send data state  4: red data state  5:write data state  6: wait state  7: done state.*/
+            uint32_t reserved3: 29;                       /*reserved*/
+        };
+        uint32_t val;
+    } fsm;
+    union {
+        struct {
+            uint32_t int_hold_ena:  2;                    /*This register is for two SPI masters to share the same cs clock and data signals. The bits of one SPI are set  if the other SPI is busy  the SPI will be hold. 1(3): hold at  idle  phase 2: hold at  prepare  phase.*/
+            uint32_t hold_val:      1;                    /*spi hold output value  which should be used with spi_hold_out_en.*/
+            uint32_t hold_out_en:   1;                    /*Enable set spi output hold value to spi_hold_reg. It can be used to hold spi state machine with spi_ext_hold_en and other usr hold signals.*/
+            uint32_t hold_out_time: 3;                    /*set the hold cycles of output spi_hold signal when spi_hold_out_en is enable.*/
+            uint32_t reserved7:    25;                    /*reserved*/
+        };
+        uint32_t val;
+    } hold;
+    union {
+        struct {
+            uint32_t reserved0:         2;                /*reserved*/
+            uint32_t in_rst:            1;                /*The bit is used to reset in dma fsm and in data fifo pointer.*/
+            uint32_t out_rst:           1;                /*The bit is used to reset out dma fsm and out data fifo pointer.*/
+            uint32_t ahbm_fifo_rst:     1;                /*Reset spi dma ahb master fifo pointer.*/
+            uint32_t ahbm_rst:          1;                /*Reset spi dma ahb master.*/
+            uint32_t in_loop_test:      1;                /*Set bit to test in link.*/
+            uint32_t out_loop_test:     1;                /*Set bit to test out link.*/
+            uint32_t out_auto_wrback:   1;                /*when the bit is set  DMA continue to use the next inlink node when the length of inlink is 0.*/
+            uint32_t out_eof_mode:      1;                /*out eof flag generation mode . 1: when dma pop all data from fifo  0:when ahb push all data to fifo.*/
+            uint32_t outdscr_burst_en:  1;                /*read descriptor use burst mode when read data for memory.*/
+            uint32_t indscr_burst_en:   1;                /*read descriptor use burst mode when write data to memory.*/
+            uint32_t out_data_burst_en: 1;                /*spi dma read data from memory in burst mode.*/
+            uint32_t mem_trans_en:      1;
+            uint32_t dma_rx_stop:       1;                /*spi dma read data stop  when in continue tx/rx mode.*/
+            uint32_t dma_tx_stop:       1;                /*spi dma write data stop when in continue tx/rx mode.*/
+            uint32_t dma_continue:      1;                /*spi dma continue tx/rx data.*/
+            uint32_t reserved17:       15;                /*reserved*/
+        };
+        uint32_t val;
+    } dma_conf;
+    union {
+        struct {
+            uint32_t addr:           20;                  /*The address of the first outlink descriptor.*/
+            uint32_t reserved20:      8;                  /*reserved*/
+            uint32_t stop:            1;                  /*Set the bit to stop to use outlink descriptor.*/
+            uint32_t start:           1;                  /*Set the bit to start to use outlink descriptor.*/
+            uint32_t restart:         1;                  /*Set the bit to mount on new outlink descriptors.*/
+            uint32_t dma_tx_ena:      1;                  /*spi dma write data status bit.*/
+        };
+        uint32_t val;
+    } dma_out_link;
+    union {
+        struct {
+            uint32_t addr:           20;                  /*The address of the first inlink descriptor.*/
+            uint32_t auto_ret:        1;                  /*when the bit is set  the inlink descriptor returns to the first link node when a packet is error.*/
+            uint32_t reserved21:      7;                  /*reserved*/
+            uint32_t stop:            1;                  /*Set the bit to stop to use inlink descriptor.*/
+            uint32_t start:           1;                  /*Set the bit to start to use inlink descriptor.*/
+            uint32_t restart:         1;                  /*Set the bit to mount on new inlink descriptors.*/
+            uint32_t dma_rx_ena:      1;                  /*spi dma read data status bit.*/
+        };
+        uint32_t val;
+    } dma_in_link;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:          1;       /*The enable bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:         1;       /*The enable bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:          1;       /*The enable bit for inlink descriptor error.*/
+            uint32_t in_done:                    1;       /*The enable bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                 1;       /*The enable bit for receiving error.*/
+            uint32_t in_suc_eof:                 1;       /*The enable bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                   1;       /*The enable bit for completing usage of a outlink descriptor .*/
+            uint32_t out_eof:                    1;       /*The enable bit for sending a packet to host done.*/
+            uint32_t out_total_eof:              1;       /*The enable bit for sending all the packets to host done.*/
+            uint32_t reserved9:                 23;       /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_ena;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:          1;       /*The raw bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:         1;       /*The raw bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:          1;       /*The raw bit for inlink descriptor error.*/
+            uint32_t in_done:                    1;       /*The raw bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                 1;       /*The raw bit for receiving error.*/
+            uint32_t in_suc_eof:                 1;       /*The raw bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                   1;       /*The raw bit for completing usage of a outlink descriptor.*/
+            uint32_t out_eof:                    1;       /*The raw bit for sending a packet to host done.*/
+            uint32_t out_total_eof:              1;       /*The raw bit for sending all the packets to host done.*/
+            uint32_t reserved9:                 23;       /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_raw;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:         1;        /*The status bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:        1;        /*The status bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:         1;        /*The status bit for inlink descriptor error.*/
+            uint32_t in_done:                   1;        /*The status bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                1;        /*The status bit for receiving error.*/
+            uint32_t in_suc_eof:                1;        /*The status bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                  1;        /*The status bit for completing usage of a outlink descriptor.*/
+            uint32_t out_eof:                   1;        /*The status bit for sending a packet to host done.*/
+            uint32_t out_total_eof:             1;        /*The status bit for sending all the packets to host done.*/
+            uint32_t reserved9:                23;        /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_st;
+    union {
+        struct {
+            uint32_t inlink_dscr_empty:          1;       /*The clear bit for lack of enough inlink descriptors.*/
+            uint32_t outlink_dscr_error:         1;       /*The clear bit for outlink descriptor error.*/
+            uint32_t inlink_dscr_error:          1;       /*The clear bit for inlink descriptor error.*/
+            uint32_t in_done:                    1;       /*The clear bit for completing usage of a inlink descriptor.*/
+            uint32_t in_err_eof:                 1;       /*The clear bit for receiving error.*/
+            uint32_t in_suc_eof:                 1;       /*The clear bit for completing receiving all the packets from host.*/
+            uint32_t out_done:                   1;       /*The clear bit for completing usage of a outlink descriptor.*/
+            uint32_t out_eof:                    1;       /*The clear bit for sending a packet to host done.*/
+            uint32_t out_total_eof:              1;       /*The clear bit for sending all the packets to host done.*/
+            uint32_t reserved9:                 23;       /*reserved*/
+        };
+        uint32_t val;
+    } dma_int_clr;
+    uint32_t dma_in_err_eof_des_addr;                         /*The inlink descriptor address when spi dma produce receiving error.*/
+    uint32_t dma_in_suc_eof_des_addr;                         /*The last inlink descriptor address when spi dma produce from_suc_eof.*/
+    uint32_t dma_inlink_dscr;                                 /*The content of current in descriptor pointer.*/
+    uint32_t dma_inlink_dscr_bf0;                             /*The content of next in descriptor pointer.*/
+    uint32_t dma_inlink_dscr_bf1;                             /*The content of current in descriptor data buffer pointer.*/
+    uint32_t dma_out_eof_bfr_des_addr;                        /*The address of buffer relative to the outlink descriptor that produce eof.*/
+    uint32_t dma_out_eof_des_addr;                            /*The last outlink descriptor address when spi dma produce to_eof.*/
+    uint32_t dma_outlink_dscr;                                /*The content of current out descriptor pointer.*/
+    uint32_t dma_outlink_dscr_bf0;                            /*The content of next out descriptor pointer.*/
+    uint32_t dma_outlink_dscr_bf1;                            /*The content of current out descriptor data buffer pointer.*/
+    union {
+        struct {
+            uint32_t out_dscr_addr:    18;                /*SPI dma out descriptor address.*/
+            uint32_t out_dscr_state:    2;                /*SPI dma out descriptor state.*/
+            uint32_t out_state:         3;                /*SPI dma out data state.*/
+            uint32_t out_fifo_cnt:      7;                /*The remains of SPI dma outfifo data.*/
+            uint32_t out_fifo_full:     1;                /*SPI dma outfifo is full.*/
+            uint32_t out_fifo_empty:    1;                /*SPI dma outfifo is empty.*/
+        };
+        uint32_t val;
+    } dma_out_status;
+    union {
+        struct {
+            uint32_t in_dscr_addr:    18;                 /*SPI dma in descriptor address.*/
+            uint32_t in_dscr_state:    2;                 /*SPI dma in descriptor state.*/
+            uint32_t in_state:         3;                 /*SPI dma in data state.*/
+            uint32_t in_fifo_cnt:      7;                 /*The remains of SPI dma infifo data.*/
+            uint32_t in_fifo_full:     1;                 /*SPI dma infifo is full.*/
+            uint32_t in_fifo_empty:    1;                 /*SPI dma infifo is empty.*/
+        };
+        uint32_t val;
+    } dma_in_status;
+    uint32_t data_buf[18];                                          /*data buffer*/
+    union {
+        struct {
+            uint32_t din0_mode:     2;                    /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t din1_mode:     2;                    /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t din2_mode:     2;                    /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t din3_mode:     2;                    /*the input signals are delayed by system clock cycles  0: input without delayed  1: input with the posedge of clk_apb 2 input with the negedge of clk_apb  3: input with the spi_clk*/
+            uint32_t reserved8:    10;
+            uint32_t din0_dly_edge: 1;                    /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t din1_dly_edge: 1;                    /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t din2_dly_edge: 1;                    /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t din3_dly_edge: 1;                    /*The bit is used to select the spi clock edge to modify input line timing.*/
+            uint32_t reserved22:   10;                    /*reserved*/
+        };
+        uint32_t val;
+    } din_mode;
+    union {
+        struct {
+            uint32_t din0_num:   2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din1_num:   2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din2_num:   2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t din3_num:   2;                       /*the input signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved8: 24;                       /*reserved*/
+        };
+        uint32_t val;
+    } din_num;
+    union {
+        struct {
+            uint32_t dout0_mode:     2;                   /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout1_mode:     2;                   /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout2_mode:     2;                   /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout3_mode:     2;                   /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout4_mode:     2;                   /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t reserved10:     8;                   /*the output signals are delayed by system clock cycles  0: output without delayed  1: output with the posedge of clk_apb 2 output with the negedge of clk_apb  3: output with the spi_clk*/
+            uint32_t dout0_dly_edge: 1;                   /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t dout1_dly_edge: 1;                   /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t dout2_dly_edge: 1;                   /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t dout3_dly_edge: 1;                   /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t dout4_dly_edge: 1;                   /*The bit is used to select the spi clock edge to modify output line timing.*/
+            uint32_t reserved23:     9;                   /*reserved*/
+        };
+        uint32_t val;
+    } dout_mode;
+    union {
+        struct {
+            uint32_t dout0_num:  2;                       /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t dout1_num:  2;                       /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t dout2_num:  2;                       /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t dout3_num:  2;                       /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t dout4_num:  2;                       /*the output signals are delayed by system clock cycles  0: delayed by 1 cycle  1: delayed by 2 cycles ...*/
+            uint32_t reserved10:22;                       /*reserved*/
+        };
+        uint32_t val;
+    } dout_num;
+    union {
+        struct {
+            uint32_t sop_en:       1;
+            uint32_t sop_mode:     4;
+            uint32_t sop_rcmd:     8;
+            uint32_t sop_wcmd:     8;
+            uint32_t sop_dqs_edge: 1;
+            uint32_t reserved22:  10;
+        };
+        uint32_t val;
+    } spr_cfg0;
+    union {
+        struct {
+            uint32_t sop_itl:    12;
+            uint32_t sop_len:     6;
+            uint32_t sop_dlen:    6;
+            uint32_t sop_dc_mode: 1;
+            uint32_t reserved25:  7;
+        };
+        uint32_t val;
+    } spr_cfg1;
+    uint32_t reserved_104;
+    uint32_t reserved_108;
+    uint32_t reserved_10c;
+    uint32_t reserved_110;
+    uint32_t reserved_114;
+    uint32_t reserved_118;
+    uint32_t reserved_11c;
+    uint32_t reserved_120;
+    uint32_t reserved_124;
+    uint32_t reserved_128;
+    uint32_t reserved_12c;
+    uint32_t reserved_130;
+    uint32_t reserved_134;
+    uint32_t reserved_138;
+    uint32_t reserved_13c;
+    uint32_t reserved_140;
+    uint32_t reserved_144;
+    uint32_t reserved_148;
+    uint32_t reserved_14c;
+    uint32_t reserved_150;
+    uint32_t reserved_154;
+    uint32_t reserved_158;
+    uint32_t reserved_15c;
+    uint32_t reserved_160;
+    uint32_t reserved_164;
+    uint32_t reserved_168;
+    uint32_t reserved_16c;
+    uint32_t reserved_170;
+    uint32_t reserved_174;
+    uint32_t reserved_178;
+    uint32_t reserved_17c;
+    uint32_t reserved_180;
+    uint32_t reserved_184;
+    uint32_t reserved_188;
+    uint32_t reserved_18c;
+    uint32_t reserved_190;
+    uint32_t reserved_194;
+    uint32_t reserved_198;
+    uint32_t reserved_19c;
+    uint32_t reserved_1a0;
+    uint32_t reserved_1a4;
+    uint32_t reserved_1a8;
+    uint32_t reserved_1ac;
+    uint32_t reserved_1b0;
+    uint32_t reserved_1b4;
+    uint32_t reserved_1b8;
+    uint32_t reserved_1bc;
+    uint32_t reserved_1c0;
+    uint32_t reserved_1c4;
+    uint32_t reserved_1c8;
+    uint32_t reserved_1cc;
+    uint32_t reserved_1d0;
+    uint32_t reserved_1d4;
+    uint32_t reserved_1d8;
+    uint32_t reserved_1dc;
+    uint32_t reserved_1e0;
+    uint32_t reserved_1e4;
+    uint32_t reserved_1e8;
+    uint32_t reserved_1ec;
+    uint32_t reserved_1f0;
+    uint32_t reserved_1f4;
+    uint32_t reserved_1f8;
+    uint32_t reserved_1fc;
+    uint32_t reserved_200;
+    uint32_t reserved_204;
+    uint32_t reserved_208;
+    uint32_t reserved_20c;
+    uint32_t reserved_210;
+    uint32_t reserved_214;
+    uint32_t reserved_218;
+    uint32_t reserved_21c;
+    uint32_t reserved_220;
+    uint32_t reserved_224;
+    uint32_t reserved_228;
+    uint32_t reserved_22c;
+    uint32_t reserved_230;
+    uint32_t reserved_234;
+    uint32_t reserved_238;
+    uint32_t reserved_23c;
+    uint32_t reserved_240;
+    uint32_t reserved_244;
+    uint32_t reserved_248;
+    uint32_t reserved_24c;
+    uint32_t reserved_250;
+    uint32_t reserved_254;
+    uint32_t reserved_258;
+    uint32_t reserved_25c;
+    uint32_t reserved_260;
+    uint32_t reserved_264;
+    uint32_t reserved_268;
+    uint32_t reserved_26c;
+    uint32_t reserved_270;
+    uint32_t reserved_274;
+    uint32_t reserved_278;
+    uint32_t reserved_27c;
+    uint32_t reserved_280;
+    uint32_t reserved_284;
+    uint32_t reserved_288;
+    uint32_t reserved_28c;
+    uint32_t reserved_290;
+    uint32_t reserved_294;
+    uint32_t reserved_298;
+    uint32_t reserved_29c;
+    uint32_t reserved_2a0;
+    uint32_t reserved_2a4;
+    uint32_t reserved_2a8;
+    uint32_t reserved_2ac;
+    uint32_t reserved_2b0;
+    uint32_t reserved_2b4;
+    uint32_t reserved_2b8;
+    uint32_t reserved_2bc;
+    uint32_t reserved_2c0;
+    uint32_t reserved_2c4;
+    uint32_t reserved_2c8;
+    uint32_t reserved_2cc;
+    uint32_t reserved_2d0;
+    uint32_t reserved_2d4;
+    uint32_t reserved_2d8;
+    uint32_t reserved_2dc;
+    uint32_t reserved_2e0;
+    uint32_t reserved_2e4;
+    uint32_t reserved_2e8;
+    uint32_t reserved_2ec;
+    uint32_t reserved_2f0;
+    uint32_t reserved_2f4;
+    uint32_t reserved_2f8;
+    uint32_t reserved_2fc;
+    uint32_t reserved_300;
+    uint32_t reserved_304;
+    uint32_t reserved_308;
+    uint32_t reserved_30c;
+    uint32_t reserved_310;
+    uint32_t reserved_314;
+    uint32_t reserved_318;
+    uint32_t reserved_31c;
+    uint32_t reserved_320;
+    uint32_t reserved_324;
+    uint32_t reserved_328;
+    uint32_t reserved_32c;
+    uint32_t reserved_330;
+    uint32_t reserved_334;
+    uint32_t reserved_338;
+    uint32_t reserved_33c;
+    uint32_t reserved_340;
+    uint32_t reserved_344;
+    uint32_t reserved_348;
+    uint32_t reserved_34c;
+    uint32_t reserved_350;
+    uint32_t reserved_354;
+    uint32_t reserved_358;
+    uint32_t reserved_35c;
+    uint32_t reserved_360;
+    uint32_t reserved_364;
+    uint32_t reserved_368;
+    uint32_t reserved_36c;
+    uint32_t reserved_370;
+    uint32_t reserved_374;
+    uint32_t reserved_378;
+    uint32_t reserved_37c;
+    uint32_t reserved_380;
+    uint32_t reserved_384;
+    uint32_t reserved_388;
+    uint32_t reserved_38c;
+    uint32_t reserved_390;
+    uint32_t reserved_394;
+    uint32_t reserved_398;
+    uint32_t reserved_39c;
+    uint32_t reserved_3a0;
+    uint32_t reserved_3a4;
+    uint32_t reserved_3a8;
+    uint32_t reserved_3ac;
+    uint32_t reserved_3b0;
+    uint32_t reserved_3b4;
+    uint32_t reserved_3b8;
+    uint32_t reserved_3bc;
+    uint32_t reserved_3c0;
+    uint32_t reserved_3c4;
+    uint32_t reserved_3c8;
+    uint32_t reserved_3cc;
+    uint32_t reserved_3d0;
+    uint32_t reserved_3d4;
+    uint32_t reserved_3d8;
+    uint32_t reserved_3dc;
+    uint32_t reserved_3e0;
+    uint32_t reserved_3e4;
+    uint32_t reserved_3e8;
+    uint32_t reserved_3ec;
+    uint32_t reserved_3f0;
+    uint32_t reserved_3f4;
+    uint32_t reserved_3f8;
+    union {
+        struct {
+            uint32_t date:      28;                       /*SPI register version.*/
+            uint32_t reserved28: 4;                       /*reserved*/
+        };
+        uint32_t val;
+    } date;
+} spi_dev_t;
+extern spi_dev_t GPSPI2;   //FSPI
+extern spi_dev_t GPSPI3;   //HSPI
+extern spi_dev_t GPSPI4;   //VSPI
+
+
+_Static_assert(sizeof(spi_dev_t)==0x400, "***invalid spi");
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_SPI_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/syscon_reg.h b/components/soc/esp32s2beta/include/soc/syscon_reg.h
new file mode 100644
index 000000000..3aa039748
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/syscon_reg.h
@@ -0,0 +1,896 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYSCON_REG_H_
+#define _SOC_SYSCON_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define SYSCON_SYSCLK_CONF_REG          (DR_REG_SYSCON_BASE + 0x000)
+/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */
+/*description: */
+#define SYSCON_SOC_CLK_SEL  0x00000003
+#define SYSCON_SOC_CLK_SEL_M  ((SYSCON_SOC_CLK_SEL_V)<<(SYSCON_SOC_CLK_SEL_S))
+#define SYSCON_SOC_CLK_SEL_V  0x3
+#define SYSCON_SOC_CLK_SEL_S  14
+#define SYSCON_SOC_CLK_SEL_XTL    0
+#define SYSCON_SOC_CLK_SEL_PLL    1
+#define SYSCON_SOC_CLK_SEL_8M     2
+#define SYSCON_SOC_CLK_SEL_APLL   3
+/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_RST_TICK_CNT  (BIT(12))
+#define SYSCON_RST_TICK_CNT_M  (BIT(12))
+#define SYSCON_RST_TICK_CNT_V  0x1
+#define SYSCON_RST_TICK_CNT_S  12
+/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_CLK_EN  (BIT(11))
+#define SYSCON_CLK_EN_M  (BIT(11))
+#define SYSCON_CLK_EN_V  0x1
+#define SYSCON_CLK_EN_S  11
+/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_CLK_320M_EN  (BIT(10))
+#define SYSCON_CLK_320M_EN_M  (BIT(10))
+#define SYSCON_CLK_320M_EN_V  0x1
+#define SYSCON_CLK_320M_EN_S  10
+/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define SYSCON_PRE_DIV_CNT  0x000003FF
+#define SYSCON_PRE_DIV_CNT_M  ((SYSCON_PRE_DIV_CNT_V)<<(SYSCON_PRE_DIV_CNT_S))
+#define SYSCON_PRE_DIV_CNT_V  0x3FF
+#define SYSCON_PRE_DIV_CNT_S  0
+
+#define SYSCON_TICK_CONF_REG          (DR_REG_SYSCON_BASE + 0x004)
+/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
+/*description: */
+#define SYSCON_TICK_ENABLE  (BIT(16))
+#define SYSCON_TICK_ENABLE_M  (BIT(16))
+#define SYSCON_TICK_ENABLE_V  0x1
+#define SYSCON_TICK_ENABLE_S  16
+/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
+/*description: */
+#define SYSCON_CK8M_TICK_NUM  0x000000FF
+#define SYSCON_CK8M_TICK_NUM_M  ((SYSCON_CK8M_TICK_NUM_V)<<(SYSCON_CK8M_TICK_NUM_S))
+#define SYSCON_CK8M_TICK_NUM_V  0xFF
+#define SYSCON_CK8M_TICK_NUM_S  8
+/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
+/*description: */
+#define SYSCON_XTAL_TICK_NUM  0x000000FF
+#define SYSCON_XTAL_TICK_NUM_M  ((SYSCON_XTAL_TICK_NUM_V)<<(SYSCON_XTAL_TICK_NUM_S))
+#define SYSCON_XTAL_TICK_NUM_V  0xFF
+#define SYSCON_XTAL_TICK_NUM_S  0
+
+#define SYSCON_SARADC_CTRL_REG          (DR_REG_SYSCON_BASE + 0x008)
+/* SYSCON_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
+/*description: force option to xpd sar blocks*/
+#define SYSCON_SARADC_XPD_SAR_FORCE  0x00000003
+#define SYSCON_SARADC_XPD_SAR_FORCE_M  ((SYSCON_SARADC_XPD_SAR_FORCE_V)<<(SYSCON_SARADC_XPD_SAR_FORCE_S))
+#define SYSCON_SARADC_XPD_SAR_FORCE_V  0x3
+#define SYSCON_SARADC_XPD_SAR_FORCE_S  27
+/* SYSCON_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: 1: I2S input data is from SAR ADC (for DMA)  0: I2S input data
+ is from GPIO matrix*/
+#define SYSCON_SARADC_DATA_TO_I2S  (BIT(26))
+#define SYSCON_SARADC_DATA_TO_I2S_M  (BIT(26))
+#define SYSCON_SARADC_DATA_TO_I2S_V  0x1
+#define SYSCON_SARADC_DATA_TO_I2S_S  26
+/* SYSCON_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
+  in this case the resolution should not be larger than 11 bits.*/
+#define SYSCON_SARADC_DATA_SAR_SEL  (BIT(25))
+#define SYSCON_SARADC_DATA_SAR_SEL_M  (BIT(25))
+#define SYSCON_SARADC_DATA_SAR_SEL_V  0x1
+#define SYSCON_SARADC_DATA_SAR_SEL_S  25
+/* SYSCON_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
+#define SYSCON_SARADC_SAR2_PATT_P_CLEAR  (BIT(24))
+#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_M  (BIT(24))
+#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_V  0x1
+#define SYSCON_SARADC_SAR2_PATT_P_CLEAR_S  24
+/* SYSCON_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
+/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
+#define SYSCON_SARADC_SAR1_PATT_P_CLEAR  (BIT(23))
+#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_M  (BIT(23))
+#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_V  0x1
+#define SYSCON_SARADC_SAR1_PATT_P_CLEAR_S  23
+/* SYSCON_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define SYSCON_SARADC_SAR2_PATT_LEN  0x0000000F
+#define SYSCON_SARADC_SAR2_PATT_LEN_M  ((SYSCON_SARADC_SAR2_PATT_LEN_V)<<(SYSCON_SARADC_SAR2_PATT_LEN_S))
+#define SYSCON_SARADC_SAR2_PATT_LEN_V  0xF
+#define SYSCON_SARADC_SAR2_PATT_LEN_S  19
+/* SYSCON_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
+/*description: 0 ~ 15 means length 1 ~ 16*/
+#define SYSCON_SARADC_SAR1_PATT_LEN  0x0000000F
+#define SYSCON_SARADC_SAR1_PATT_LEN_M  ((SYSCON_SARADC_SAR1_PATT_LEN_V)<<(SYSCON_SARADC_SAR1_PATT_LEN_S))
+#define SYSCON_SARADC_SAR1_PATT_LEN_V  0xF
+#define SYSCON_SARADC_SAR1_PATT_LEN_S  15
+/* SYSCON_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
+/*description: SAR clock divider*/
+#define SYSCON_SARADC_SAR_CLK_DIV  0x000000FF
+#define SYSCON_SARADC_SAR_CLK_DIV_M  ((SYSCON_SARADC_SAR_CLK_DIV_V)<<(SYSCON_SARADC_SAR_CLK_DIV_S))
+#define SYSCON_SARADC_SAR_CLK_DIV_V  0xFF
+#define SYSCON_SARADC_SAR_CLK_DIV_S  7
+/* SYSCON_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_SARADC_SAR_CLK_GATED  (BIT(6))
+#define SYSCON_SARADC_SAR_CLK_GATED_M  (BIT(6))
+#define SYSCON_SARADC_SAR_CLK_GATED_V  0x1
+#define SYSCON_SARADC_SAR_CLK_GATED_S  6
+/* SYSCON_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
+/*description: 0: SAR1  1: SAR2  only work for single SAR mode*/
+#define SYSCON_SARADC_SAR_SEL  (BIT(5))
+#define SYSCON_SARADC_SAR_SEL_M  (BIT(5))
+#define SYSCON_SARADC_SAR_SEL_V  0x1
+#define SYSCON_SARADC_SAR_SEL_S  5
+/* SYSCON_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
+/*description: 0: single mode  1: double mode  2: alternate mode*/
+#define SYSCON_SARADC_WORK_MODE  0x00000003
+#define SYSCON_SARADC_WORK_MODE_M  ((SYSCON_SARADC_WORK_MODE_V)<<(SYSCON_SARADC_WORK_MODE_S))
+#define SYSCON_SARADC_WORK_MODE_V  0x3
+#define SYSCON_SARADC_WORK_MODE_S  3
+/* SYSCON_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_SARADC_START  (BIT(1))
+#define SYSCON_SARADC_START_M  (BIT(1))
+#define SYSCON_SARADC_START_V  0x1
+#define SYSCON_SARADC_START_S  1
+/* SYSCON_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_SARADC_START_FORCE  (BIT(0))
+#define SYSCON_SARADC_START_FORCE_M  (BIT(0))
+#define SYSCON_SARADC_START_FORCE_V  0x1
+#define SYSCON_SARADC_START_FORCE_S  0
+
+#define SYSCON_SARADC_CTRL2_REG          (DR_REG_SYSCON_BASE + 0x00C)
+/* SYSCON_SARADC_TIMER_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
+/*description: to enable saradc timer trigger*/
+#define SYSCON_SARADC_TIMER_EN  (BIT(20))
+#define SYSCON_SARADC_TIMER_EN_M  (BIT(20))
+#define SYSCON_SARADC_TIMER_EN_V  0x1
+#define SYSCON_SARADC_TIMER_EN_S  20
+/* SYSCON_SARADC_TIMER_TARGET : R/W ;bitpos:[19:12] ;default: 8'd10 ; */
+/*description: to set saradc timer target*/
+#define SYSCON_SARADC_TIMER_TARGET  0x000000FF
+#define SYSCON_SARADC_TIMER_TARGET_M  ((SYSCON_SARADC_TIMER_TARGET_V)<<(SYSCON_SARADC_TIMER_TARGET_S))
+#define SYSCON_SARADC_TIMER_TARGET_V  0xFF
+#define SYSCON_SARADC_TIMER_TARGET_S  12
+/* SYSCON_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
+/*description: 1: select saradc timer 0: i2s_ws trigger*/
+#define SYSCON_SARADC_TIMER_SEL  (BIT(11))
+#define SYSCON_SARADC_TIMER_SEL_M  (BIT(11))
+#define SYSCON_SARADC_TIMER_SEL_V  0x1
+#define SYSCON_SARADC_TIMER_SEL_S  11
+/* SYSCON_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+#define SYSCON_SARADC_SAR2_INV  (BIT(10))
+#define SYSCON_SARADC_SAR2_INV_M  (BIT(10))
+#define SYSCON_SARADC_SAR2_INV_V  0x1
+#define SYSCON_SARADC_SAR2_INV_S  10
+/* SYSCON_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: 1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+#define SYSCON_SARADC_SAR1_INV  (BIT(9))
+#define SYSCON_SARADC_SAR1_INV_M  (BIT(9))
+#define SYSCON_SARADC_SAR1_INV_V  0x1
+#define SYSCON_SARADC_SAR1_INV_S  9
+/* SYSCON_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
+/*description: max conversion number*/
+#define SYSCON_SARADC_MAX_MEAS_NUM  0x000000FF
+#define SYSCON_SARADC_MAX_MEAS_NUM_M  ((SYSCON_SARADC_MAX_MEAS_NUM_V)<<(SYSCON_SARADC_MAX_MEAS_NUM_S))
+#define SYSCON_SARADC_MAX_MEAS_NUM_V  0xFF
+#define SYSCON_SARADC_MAX_MEAS_NUM_S  1
+/* SYSCON_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
+/*description: */
+#define SYSCON_SARADC_MEAS_NUM_LIMIT  (BIT(0))
+#define SYSCON_SARADC_MEAS_NUM_LIMIT_M  (BIT(0))
+#define SYSCON_SARADC_MEAS_NUM_LIMIT_V  0x1
+#define SYSCON_SARADC_MEAS_NUM_LIMIT_S  0
+
+#define SYSCON_SARADC_FSM_REG          (DR_REG_SYSCON_BASE + 0x010)
+/* SYSCON_SARADC_SAMPLE_CYCLE : R/W ;bitpos:[31:24] ;default: 8'd2 ; */
+/*description: sample cycles*/
+#define SYSCON_SARADC_SAMPLE_CYCLE  0x000000FF
+#define SYSCON_SARADC_SAMPLE_CYCLE_M  ((SYSCON_SARADC_SAMPLE_CYCLE_V)<<(SYSCON_SARADC_SAMPLE_CYCLE_S))
+#define SYSCON_SARADC_SAMPLE_CYCLE_V  0xFF
+#define SYSCON_SARADC_SAMPLE_CYCLE_S  24
+/* SYSCON_SARADC_SAMPLE_NUM : R/W ;bitpos:[23:16] ;default: 8'd0 ; */
+/*description: sample number*/
+#define SYSCON_SARADC_SAMPLE_NUM  0x000000FF
+#define SYSCON_SARADC_SAMPLE_NUM_M  ((SYSCON_SARADC_SAMPLE_NUM_V)<<(SYSCON_SARADC_SAMPLE_NUM_S))
+#define SYSCON_SARADC_SAMPLE_NUM_V  0xFF
+#define SYSCON_SARADC_SAMPLE_NUM_S  16
+
+#define SYSCON_SARADC_FSM_WAIT_REG          (DR_REG_SYSCON_BASE + 0x014)
+/* SYSCON_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
+/*description: */
+#define SYSCON_SARADC_STANDBY_WAIT  0x000000FF
+#define SYSCON_SARADC_STANDBY_WAIT_M  ((SYSCON_SARADC_STANDBY_WAIT_V)<<(SYSCON_SARADC_STANDBY_WAIT_S))
+#define SYSCON_SARADC_STANDBY_WAIT_V  0xFF
+#define SYSCON_SARADC_STANDBY_WAIT_S  16
+/* SYSCON_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
+/*description: */
+#define SYSCON_SARADC_RSTB_WAIT  0x000000FF
+#define SYSCON_SARADC_RSTB_WAIT_M  ((SYSCON_SARADC_RSTB_WAIT_V)<<(SYSCON_SARADC_RSTB_WAIT_S))
+#define SYSCON_SARADC_RSTB_WAIT_V  0xFF
+#define SYSCON_SARADC_RSTB_WAIT_S  8
+/* SYSCON_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
+/*description: */
+#define SYSCON_SARADC_XPD_WAIT  0x000000FF
+#define SYSCON_SARADC_XPD_WAIT_M  ((SYSCON_SARADC_XPD_WAIT_V)<<(SYSCON_SARADC_XPD_WAIT_S))
+#define SYSCON_SARADC_XPD_WAIT_V  0xFF
+#define SYSCON_SARADC_XPD_WAIT_S  0
+
+#define SYSCON_SARADC_SAR1_STATUS_REG          (DR_REG_SYSCON_BASE + 0x018)
+/* SYSCON_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define SYSCON_SARADC_SAR1_STATUS  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_STATUS_M  ((SYSCON_SARADC_SAR1_STATUS_V)<<(SYSCON_SARADC_SAR1_STATUS_S))
+#define SYSCON_SARADC_SAR1_STATUS_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_STATUS_S  0
+
+#define SYSCON_SARADC_SAR2_STATUS_REG          (DR_REG_SYSCON_BASE + 0x01C)
+/* SYSCON_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
+/*description: */
+#define SYSCON_SARADC_SAR2_STATUS  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_STATUS_M  ((SYSCON_SARADC_SAR2_STATUS_V)<<(SYSCON_SARADC_SAR2_STATUS_S))
+#define SYSCON_SARADC_SAR2_STATUS_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_STATUS_S  0
+
+#define SYSCON_SARADC_SAR1_PATT_TAB1_REG          (DR_REG_SYSCON_BASE + 0x020)
+/* SYSCON_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
+#define SYSCON_SARADC_SAR1_PATT_TAB1  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB1_M  ((SYSCON_SARADC_SAR1_PATT_TAB1_V)<<(SYSCON_SARADC_SAR1_PATT_TAB1_S))
+#define SYSCON_SARADC_SAR1_PATT_TAB1_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB1_S  0
+
+#define SYSCON_SARADC_SAR1_PATT_TAB2_REG          (DR_REG_SYSCON_BASE + 0x024)
+/* SYSCON_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
+#define SYSCON_SARADC_SAR1_PATT_TAB2  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB2_M  ((SYSCON_SARADC_SAR1_PATT_TAB2_V)<<(SYSCON_SARADC_SAR1_PATT_TAB2_S))
+#define SYSCON_SARADC_SAR1_PATT_TAB2_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB2_S  0
+
+#define SYSCON_SARADC_SAR1_PATT_TAB3_REG          (DR_REG_SYSCON_BASE + 0x028)
+/* SYSCON_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
+#define SYSCON_SARADC_SAR1_PATT_TAB3  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB3_M  ((SYSCON_SARADC_SAR1_PATT_TAB3_V)<<(SYSCON_SARADC_SAR1_PATT_TAB3_S))
+#define SYSCON_SARADC_SAR1_PATT_TAB3_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB3_S  0
+
+#define SYSCON_SARADC_SAR1_PATT_TAB4_REG          (DR_REG_SYSCON_BASE + 0x02C)
+/* SYSCON_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
+#define SYSCON_SARADC_SAR1_PATT_TAB4  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB4_M  ((SYSCON_SARADC_SAR1_PATT_TAB4_V)<<(SYSCON_SARADC_SAR1_PATT_TAB4_S))
+#define SYSCON_SARADC_SAR1_PATT_TAB4_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR1_PATT_TAB4_S  0
+
+#define SYSCON_SARADC_SAR2_PATT_TAB1_REG          (DR_REG_SYSCON_BASE + 0x030)
+/* SYSCON_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
+#define SYSCON_SARADC_SAR2_PATT_TAB1  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB1_M  ((SYSCON_SARADC_SAR2_PATT_TAB1_V)<<(SYSCON_SARADC_SAR2_PATT_TAB1_S))
+#define SYSCON_SARADC_SAR2_PATT_TAB1_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB1_S  0
+
+#define SYSCON_SARADC_SAR2_PATT_TAB2_REG          (DR_REG_SYSCON_BASE + 0x034)
+/* SYSCON_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
+#define SYSCON_SARADC_SAR2_PATT_TAB2  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB2_M  ((SYSCON_SARADC_SAR2_PATT_TAB2_V)<<(SYSCON_SARADC_SAR2_PATT_TAB2_S))
+#define SYSCON_SARADC_SAR2_PATT_TAB2_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB2_S  0
+
+#define SYSCON_SARADC_SAR2_PATT_TAB3_REG          (DR_REG_SYSCON_BASE + 0x038)
+/* SYSCON_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
+#define SYSCON_SARADC_SAR2_PATT_TAB3  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB3_M  ((SYSCON_SARADC_SAR2_PATT_TAB3_V)<<(SYSCON_SARADC_SAR2_PATT_TAB3_S))
+#define SYSCON_SARADC_SAR2_PATT_TAB3_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB3_S  0
+
+#define SYSCON_SARADC_SAR2_PATT_TAB4_REG          (DR_REG_SYSCON_BASE + 0x03C)
+/* SYSCON_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[31:0] ;default: 32'hf0f0f0f ; */
+/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
+#define SYSCON_SARADC_SAR2_PATT_TAB4  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB4_M  ((SYSCON_SARADC_SAR2_PATT_TAB4_V)<<(SYSCON_SARADC_SAR2_PATT_TAB4_S))
+#define SYSCON_SARADC_SAR2_PATT_TAB4_V  0xFFFFFFFF
+#define SYSCON_SARADC_SAR2_PATT_TAB4_S  0
+
+#define SYSCON_ADC_ARB_CTRL_REG          (DR_REG_SYSCON_BASE + 0x040)
+/* SYSCON_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: adc2 arbiter uses fixed priority*/
+#define SYSCON_ADC_ARB_FIX_PRIORITY  (BIT(12))
+#define SYSCON_ADC_ARB_FIX_PRIORITY_M  (BIT(12))
+#define SYSCON_ADC_ARB_FIX_PRIORITY_V  0x1
+#define SYSCON_ADC_ARB_FIX_PRIORITY_S  12
+/* SYSCON_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
+/*description: Set adc2 arbiter wifi priority*/
+#define SYSCON_ADC_ARB_WIFI_PRIORITY  0x00000003
+#define SYSCON_ADC_ARB_WIFI_PRIORITY_M  ((SYSCON_ADC_ARB_WIFI_PRIORITY_V)<<(SYSCON_ADC_ARB_WIFI_PRIORITY_S))
+#define SYSCON_ADC_ARB_WIFI_PRIORITY_V  0x3
+#define SYSCON_ADC_ARB_WIFI_PRIORITY_S  10
+/* SYSCON_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
+/*description: Set adc2 arbiter rtc priority*/
+#define SYSCON_ADC_ARB_RTC_PRIORITY  0x00000003
+#define SYSCON_ADC_ARB_RTC_PRIORITY_M  ((SYSCON_ADC_ARB_RTC_PRIORITY_V)<<(SYSCON_ADC_ARB_RTC_PRIORITY_S))
+#define SYSCON_ADC_ARB_RTC_PRIORITY_V  0x3
+#define SYSCON_ADC_ARB_RTC_PRIORITY_S  8
+/* SYSCON_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
+/*description: Set adc2 arbiter apb priority*/
+#define SYSCON_ADC_ARB_APB_PRIORITY  0x00000003
+#define SYSCON_ADC_ARB_APB_PRIORITY_M  ((SYSCON_ADC_ARB_APB_PRIORITY_V)<<(SYSCON_ADC_ARB_APB_PRIORITY_S))
+#define SYSCON_ADC_ARB_APB_PRIORITY_V  0x3
+#define SYSCON_ADC_ARB_APB_PRIORITY_S  6
+/* SYSCON_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: adc2 arbiter force grant*/
+#define SYSCON_ADC_ARB_GRANT_FORCE  (BIT(5))
+#define SYSCON_ADC_ARB_GRANT_FORCE_M  (BIT(5))
+#define SYSCON_ADC_ARB_GRANT_FORCE_V  0x1
+#define SYSCON_ADC_ARB_GRANT_FORCE_S  5
+/* SYSCON_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable wifi controller*/
+#define SYSCON_ADC_ARB_WIFI_FORCE  (BIT(4))
+#define SYSCON_ADC_ARB_WIFI_FORCE_M  (BIT(4))
+#define SYSCON_ADC_ARB_WIFI_FORCE_V  0x1
+#define SYSCON_ADC_ARB_WIFI_FORCE_S  4
+/* SYSCON_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enable rtc controller*/
+#define SYSCON_ADC_ARB_RTC_FORCE  (BIT(3))
+#define SYSCON_ADC_ARB_RTC_FORCE_M  (BIT(3))
+#define SYSCON_ADC_ARB_RTC_FORCE_V  0x1
+#define SYSCON_ADC_ARB_RTC_FORCE_S  3
+/* SYSCON_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: adc2 arbiter force to enableapb controller*/
+#define SYSCON_ADC_ARB_APB_FORCE  (BIT(2))
+#define SYSCON_ADC_ARB_APB_FORCE_M  (BIT(2))
+#define SYSCON_ADC_ARB_APB_FORCE_V  0x1
+#define SYSCON_ADC_ARB_APB_FORCE_S  2
+
+#define SYSCON_CLK_OUT_EN_REG          (DR_REG_SYSCON_BASE + 0x044)
+/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_XTAL_OEN  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_M  (BIT(10))
+#define SYSCON_CLK_XTAL_OEN_V  0x1
+#define SYSCON_CLK_XTAL_OEN_S  10
+/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK40X_BB_OEN  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_M  (BIT(9))
+#define SYSCON_CLK40X_BB_OEN_V  0x1
+#define SYSCON_CLK40X_BB_OEN_S  9
+/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_DAC_CPU_OEN  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_M  (BIT(8))
+#define SYSCON_CLK_DAC_CPU_OEN_V  0x1
+#define SYSCON_CLK_DAC_CPU_OEN_S  8
+/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_ADC_INF_OEN  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_M  (BIT(7))
+#define SYSCON_CLK_ADC_INF_OEN_V  0x1
+#define SYSCON_CLK_ADC_INF_OEN_S  7
+/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_320M_OEN  (BIT(6))
+#define SYSCON_CLK_320M_OEN_M  (BIT(6))
+#define SYSCON_CLK_320M_OEN_V  0x1
+#define SYSCON_CLK_320M_OEN_S  6
+/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK160_OEN  (BIT(5))
+#define SYSCON_CLK160_OEN_M  (BIT(5))
+#define SYSCON_CLK160_OEN_V  0x1
+#define SYSCON_CLK160_OEN_S  5
+/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK80_OEN  (BIT(4))
+#define SYSCON_CLK80_OEN_M  (BIT(4))
+#define SYSCON_CLK80_OEN_V  0x1
+#define SYSCON_CLK80_OEN_S  4
+/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK_BB_OEN  (BIT(3))
+#define SYSCON_CLK_BB_OEN_M  (BIT(3))
+#define SYSCON_CLK_BB_OEN_V  0x1
+#define SYSCON_CLK_BB_OEN_S  3
+/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK44_OEN  (BIT(2))
+#define SYSCON_CLK44_OEN_M  (BIT(2))
+#define SYSCON_CLK44_OEN_V  0x1
+#define SYSCON_CLK44_OEN_S  2
+/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK22_OEN  (BIT(1))
+#define SYSCON_CLK22_OEN_M  (BIT(1))
+#define SYSCON_CLK22_OEN_V  0x1
+#define SYSCON_CLK22_OEN_S  1
+/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_CLK20_OEN  (BIT(0))
+#define SYSCON_CLK20_OEN_M  (BIT(0))
+#define SYSCON_CLK20_OEN_V  0x1
+#define SYSCON_CLK20_OEN_S  0
+
+#define SYSCON_HOST_INF_SEL_REG          (DR_REG_SYSCON_BASE + 0x048)
+/* SYSCON_SPI_PRIOR : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI_PRIOR  (BIT(13))
+#define SYSCON_SPI_PRIOR_M  (BIT(13))
+#define SYSCON_SPI_PRIOR_V  0x1
+#define SYSCON_SPI_PRIOR_S  13
+/* SYSCON_SPI1_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI1_HOLD  (BIT(9))
+#define SYSCON_SPI1_HOLD_M  (BIT(9))
+#define SYSCON_SPI1_HOLD_V  0x1
+#define SYSCON_SPI1_HOLD_S  9
+/* SYSCON_SPI0_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI0_HOLD  (BIT(8))
+#define SYSCON_SPI0_HOLD_M  (BIT(8))
+#define SYSCON_SPI0_HOLD_V  0x1
+#define SYSCON_SPI0_HOLD_S  8
+/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
+/*description: */
+#define SYSCON_PERI_IO_SWAP  0x000000FF
+#define SYSCON_PERI_IO_SWAP_M  ((SYSCON_PERI_IO_SWAP_V)<<(SYSCON_PERI_IO_SWAP_S))
+#define SYSCON_PERI_IO_SWAP_V  0xFF
+#define SYSCON_PERI_IO_SWAP_S  0
+
+#define SYSCON_EXT_MEM_PMS_LOCK_REG          (DR_REG_SYSCON_BASE + 0x04C)
+/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_EXT_MEM_PMS_LOCK  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_M  (BIT(0))
+#define SYSCON_EXT_MEM_PMS_LOCK_V  0x1
+#define SYSCON_EXT_MEM_PMS_LOCK_S  0
+
+#define SYSCON_FLASH_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x050)
+/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_ATTR  0x00000007
+#define SYSCON_FLASH_ACE0_ATTR_M  ((SYSCON_FLASH_ACE0_ATTR_V)<<(SYSCON_FLASH_ACE0_ATTR_S))
+#define SYSCON_FLASH_ACE0_ATTR_V  0x7
+#define SYSCON_FLASH_ACE0_ATTR_S  0
+
+#define SYSCON_FLASH_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x054)
+/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_ATTR  0x00000007
+#define SYSCON_FLASH_ACE1_ATTR_M  ((SYSCON_FLASH_ACE1_ATTR_V)<<(SYSCON_FLASH_ACE1_ATTR_S))
+#define SYSCON_FLASH_ACE1_ATTR_V  0x7
+#define SYSCON_FLASH_ACE1_ATTR_S  0
+
+#define SYSCON_FLASH_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x058)
+/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_ATTR  0x00000007
+#define SYSCON_FLASH_ACE2_ATTR_M  ((SYSCON_FLASH_ACE2_ATTR_V)<<(SYSCON_FLASH_ACE2_ATTR_S))
+#define SYSCON_FLASH_ACE2_ATTR_V  0x7
+#define SYSCON_FLASH_ACE2_ATTR_S  0
+
+#define SYSCON_FLASH_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x05C)
+/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_ATTR  0x00000007
+#define SYSCON_FLASH_ACE3_ATTR_M  ((SYSCON_FLASH_ACE3_ATTR_V)<<(SYSCON_FLASH_ACE3_ATTR_S))
+#define SYSCON_FLASH_ACE3_ATTR_V  0x7
+#define SYSCON_FLASH_ACE3_ATTR_S  0
+
+#define SYSCON_FLASH_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x060)
+/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_M  ((SYSCON_FLASH_ACE0_ADDR_S_V)<<(SYSCON_FLASH_ACE0_ADDR_S_S))
+#define SYSCON_FLASH_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE0_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x064)
+/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_M  ((SYSCON_FLASH_ACE1_ADDR_S_V)<<(SYSCON_FLASH_ACE1_ADDR_S_S))
+#define SYSCON_FLASH_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE1_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x068)
+/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_M  ((SYSCON_FLASH_ACE2_ADDR_S_V)<<(SYSCON_FLASH_ACE2_ADDR_S_S))
+#define SYSCON_FLASH_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE2_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x06C)
+/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_ADDR_S  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_M  ((SYSCON_FLASH_ACE3_ADDR_S_V)<<(SYSCON_FLASH_ACE3_ADDR_S_S))
+#define SYSCON_FLASH_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_FLASH_ACE3_ADDR_S_S  0
+
+#define SYSCON_FLASH_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x070)
+/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE0_SIZE  0x0000FFFF
+#define SYSCON_FLASH_ACE0_SIZE_M  ((SYSCON_FLASH_ACE0_SIZE_V)<<(SYSCON_FLASH_ACE0_SIZE_S))
+#define SYSCON_FLASH_ACE0_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE0_SIZE_S  0
+
+#define SYSCON_FLASH_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x074)
+/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE1_SIZE  0x0000FFFF
+#define SYSCON_FLASH_ACE1_SIZE_M  ((SYSCON_FLASH_ACE1_SIZE_V)<<(SYSCON_FLASH_ACE1_SIZE_S))
+#define SYSCON_FLASH_ACE1_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE1_SIZE_S  0
+
+#define SYSCON_FLASH_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x078)
+/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE2_SIZE  0x0000FFFF
+#define SYSCON_FLASH_ACE2_SIZE_M  ((SYSCON_FLASH_ACE2_SIZE_V)<<(SYSCON_FLASH_ACE2_SIZE_S))
+#define SYSCON_FLASH_ACE2_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE2_SIZE_S  0
+
+#define SYSCON_FLASH_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x07C)
+/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_FLASH_ACE3_SIZE  0x0000FFFF
+#define SYSCON_FLASH_ACE3_SIZE_M  ((SYSCON_FLASH_ACE3_SIZE_V)<<(SYSCON_FLASH_ACE3_SIZE_S))
+#define SYSCON_FLASH_ACE3_SIZE_V  0xFFFF
+#define SYSCON_FLASH_ACE3_SIZE_S  0
+
+#define SYSCON_SRAM_ACE0_ATTR_REG          (DR_REG_SYSCON_BASE + 0x080)
+/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_SRAM_ACE0_ATTR  0x00000007
+#define SYSCON_SRAM_ACE0_ATTR_M  ((SYSCON_SRAM_ACE0_ATTR_V)<<(SYSCON_SRAM_ACE0_ATTR_S))
+#define SYSCON_SRAM_ACE0_ATTR_V  0x7
+#define SYSCON_SRAM_ACE0_ATTR_S  0
+
+#define SYSCON_SRAM_ACE1_ATTR_REG          (DR_REG_SYSCON_BASE + 0x084)
+/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_SRAM_ACE1_ATTR  0x00000007
+#define SYSCON_SRAM_ACE1_ATTR_M  ((SYSCON_SRAM_ACE1_ATTR_V)<<(SYSCON_SRAM_ACE1_ATTR_S))
+#define SYSCON_SRAM_ACE1_ATTR_V  0x7
+#define SYSCON_SRAM_ACE1_ATTR_S  0
+
+#define SYSCON_SRAM_ACE2_ATTR_REG          (DR_REG_SYSCON_BASE + 0x088)
+/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_SRAM_ACE2_ATTR  0x00000007
+#define SYSCON_SRAM_ACE2_ATTR_M  ((SYSCON_SRAM_ACE2_ATTR_V)<<(SYSCON_SRAM_ACE2_ATTR_S))
+#define SYSCON_SRAM_ACE2_ATTR_V  0x7
+#define SYSCON_SRAM_ACE2_ATTR_S  0
+
+#define SYSCON_SRAM_ACE3_ATTR_REG          (DR_REG_SYSCON_BASE + 0x08C)
+/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[2:0] ;default: 3'h7 ; */
+/*description: */
+#define SYSCON_SRAM_ACE3_ATTR  0x00000007
+#define SYSCON_SRAM_ACE3_ATTR_M  ((SYSCON_SRAM_ACE3_ATTR_V)<<(SYSCON_SRAM_ACE3_ATTR_S))
+#define SYSCON_SRAM_ACE3_ATTR_V  0x7
+#define SYSCON_SRAM_ACE3_ATTR_S  0
+
+#define SYSCON_SRAM_ACE0_ADDR_REG          (DR_REG_SYSCON_BASE + 0x090)
+/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_SRAM_ACE0_ADDR_S  0xFFFFFFFF
+#define SYSCON_SRAM_ACE0_ADDR_S_M  ((SYSCON_SRAM_ACE0_ADDR_S_V)<<(SYSCON_SRAM_ACE0_ADDR_S_S))
+#define SYSCON_SRAM_ACE0_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE0_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE1_ADDR_REG          (DR_REG_SYSCON_BASE + 0x094)
+/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
+/*description: */
+#define SYSCON_SRAM_ACE1_ADDR_S  0xFFFFFFFF
+#define SYSCON_SRAM_ACE1_ADDR_S_M  ((SYSCON_SRAM_ACE1_ADDR_S_V)<<(SYSCON_SRAM_ACE1_ADDR_S_S))
+#define SYSCON_SRAM_ACE1_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE1_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE2_ADDR_REG          (DR_REG_SYSCON_BASE + 0x098)
+/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
+/*description: */
+#define SYSCON_SRAM_ACE2_ADDR_S  0xFFFFFFFF
+#define SYSCON_SRAM_ACE2_ADDR_S_M  ((SYSCON_SRAM_ACE2_ADDR_S_V)<<(SYSCON_SRAM_ACE2_ADDR_S_S))
+#define SYSCON_SRAM_ACE2_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE2_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE3_ADDR_REG          (DR_REG_SYSCON_BASE + 0x09C)
+/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
+/*description: */
+#define SYSCON_SRAM_ACE3_ADDR_S  0xFFFFFFFF
+#define SYSCON_SRAM_ACE3_ADDR_S_M  ((SYSCON_SRAM_ACE3_ADDR_S_V)<<(SYSCON_SRAM_ACE3_ADDR_S_S))
+#define SYSCON_SRAM_ACE3_ADDR_S_V  0xFFFFFFFF
+#define SYSCON_SRAM_ACE3_ADDR_S_S  0
+
+#define SYSCON_SRAM_ACE0_SIZE_REG          (DR_REG_SYSCON_BASE + 0x0A0)
+/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_SRAM_ACE0_SIZE  0x0000FFFF
+#define SYSCON_SRAM_ACE0_SIZE_M  ((SYSCON_SRAM_ACE0_SIZE_V)<<(SYSCON_SRAM_ACE0_SIZE_S))
+#define SYSCON_SRAM_ACE0_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE0_SIZE_S  0
+
+#define SYSCON_SRAM_ACE1_SIZE_REG          (DR_REG_SYSCON_BASE + 0x0A4)
+/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_SRAM_ACE1_SIZE  0x0000FFFF
+#define SYSCON_SRAM_ACE1_SIZE_M  ((SYSCON_SRAM_ACE1_SIZE_V)<<(SYSCON_SRAM_ACE1_SIZE_S))
+#define SYSCON_SRAM_ACE1_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE1_SIZE_S  0
+
+#define SYSCON_SRAM_ACE2_SIZE_REG          (DR_REG_SYSCON_BASE + 0x0A8)
+/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_SRAM_ACE2_SIZE  0x0000FFFF
+#define SYSCON_SRAM_ACE2_SIZE_M  ((SYSCON_SRAM_ACE2_SIZE_V)<<(SYSCON_SRAM_ACE2_SIZE_S))
+#define SYSCON_SRAM_ACE2_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE2_SIZE_S  0
+
+#define SYSCON_SRAM_ACE3_SIZE_REG          (DR_REG_SYSCON_BASE + 0x0AC)
+/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
+/*description: */
+#define SYSCON_SRAM_ACE3_SIZE  0x0000FFFF
+#define SYSCON_SRAM_ACE3_SIZE_M  ((SYSCON_SRAM_ACE3_SIZE_V)<<(SYSCON_SRAM_ACE3_SIZE_S))
+#define SYSCON_SRAM_ACE3_SIZE_V  0xFFFF
+#define SYSCON_SRAM_ACE3_SIZE_S  0
+
+#define SYSCON_SPI0_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x0B0)
+/* SYSCON_SPI0_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define SYSCON_SPI0_REJECT_CDE  0x0000001F
+#define SYSCON_SPI0_REJECT_CDE_M  ((SYSCON_SPI0_REJECT_CDE_V)<<(SYSCON_SPI0_REJECT_CDE_S))
+#define SYSCON_SPI0_REJECT_CDE_V  0x1F
+#define SYSCON_SPI0_REJECT_CDE_S  2
+/* SYSCON_SPI0_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI0_REJECT_CLR  (BIT(1))
+#define SYSCON_SPI0_REJECT_CLR_M  (BIT(1))
+#define SYSCON_SPI0_REJECT_CLR_V  0x1
+#define SYSCON_SPI0_REJECT_CLR_S  1
+/* SYSCON_SPI0_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI0_REJECT_INT  (BIT(0))
+#define SYSCON_SPI0_REJECT_INT_M  (BIT(0))
+#define SYSCON_SPI0_REJECT_INT_V  0x1
+#define SYSCON_SPI0_REJECT_INT_S  0
+
+#define SYSCON_SPI0_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0B4)
+/* SYSCON_SPI0_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_SPI0_REJECT_ADDR  0xFFFFFFFF
+#define SYSCON_SPI0_REJECT_ADDR_M  ((SYSCON_SPI0_REJECT_ADDR_V)<<(SYSCON_SPI0_REJECT_ADDR_S))
+#define SYSCON_SPI0_REJECT_ADDR_V  0xFFFFFFFF
+#define SYSCON_SPI0_REJECT_ADDR_S  0
+
+#define SYSCON_SPI1_PMS_CTRL_REG          (DR_REG_SYSCON_BASE + 0x0B8)
+/* SYSCON_SPI1_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
+/*description: */
+#define SYSCON_SPI1_REJECT_CDE  0x0000001F
+#define SYSCON_SPI1_REJECT_CDE_M  ((SYSCON_SPI1_REJECT_CDE_V)<<(SYSCON_SPI1_REJECT_CDE_S))
+#define SYSCON_SPI1_REJECT_CDE_V  0x1F
+#define SYSCON_SPI1_REJECT_CDE_S  2
+/* SYSCON_SPI1_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI1_REJECT_CLR  (BIT(1))
+#define SYSCON_SPI1_REJECT_CLR_M  (BIT(1))
+#define SYSCON_SPI1_REJECT_CLR_V  0x1
+#define SYSCON_SPI1_REJECT_CLR_S  1
+/* SYSCON_SPI1_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_SPI1_REJECT_INT  (BIT(0))
+#define SYSCON_SPI1_REJECT_INT_M  (BIT(0))
+#define SYSCON_SPI1_REJECT_INT_V  0x1
+#define SYSCON_SPI1_REJECT_INT_S  0
+
+#define SYSCON_SPI1_REJECT_ADDR_REG          (DR_REG_SYSCON_BASE + 0x0BC)
+/* SYSCON_SPI1_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_SPI1_REJECT_ADDR  0xFFFFFFFF
+#define SYSCON_SPI1_REJECT_ADDR_M  ((SYSCON_SPI1_REJECT_ADDR_V)<<(SYSCON_SPI1_REJECT_ADDR_S))
+#define SYSCON_SPI1_REJECT_ADDR_V  0xFFFFFFFF
+#define SYSCON_SPI1_REJECT_ADDR_S  0
+
+#define SYSCON_SDIO_CTRL_REG          (DR_REG_SYSCON_BASE + 0x0C0)
+/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_SDIO_WIN_ACCESS_EN  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_M  (BIT(0))
+#define SYSCON_SDIO_WIN_ACCESS_EN_V  0x1
+#define SYSCON_SDIO_WIN_ACCESS_EN_S  0
+
+#define SYSCON_REDCY_SIG0_REG          (DR_REG_SYSCON_BASE + 0x0C4)
+/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_REDCY_ANDOR  (BIT(31))
+#define SYSCON_REDCY_ANDOR_M  (BIT(31))
+#define SYSCON_REDCY_ANDOR_V  0x1
+#define SYSCON_REDCY_ANDOR_S  31
+/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define SYSCON_REDCY_SIG0  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_M  ((SYSCON_REDCY_SIG0_V)<<(SYSCON_REDCY_SIG0_S))
+#define SYSCON_REDCY_SIG0_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG0_S  0
+
+#define SYSCON_REDCY_SIG1_REG          (DR_REG_SYSCON_BASE + 0x0C8)
+/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define SYSCON_REDCY_NANDOR  (BIT(31))
+#define SYSCON_REDCY_NANDOR_M  (BIT(31))
+#define SYSCON_REDCY_NANDOR_V  0x1
+#define SYSCON_REDCY_NANDOR_S  31
+/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
+/*description: */
+#define SYSCON_REDCY_SIG1  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_M  ((SYSCON_REDCY_SIG1_V)<<(SYSCON_REDCY_SIG1_S))
+#define SYSCON_REDCY_SIG1_V  0x7FFFFFFF
+#define SYSCON_REDCY_SIG1_S  0
+
+#define SYSCON_WIFI_BB_CFG_REG          (DR_REG_SYSCON_BASE + 0x0CC)
+/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_BB_CFG  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_M  ((SYSCON_WIFI_BB_CFG_V)<<(SYSCON_WIFI_BB_CFG_S))
+#define SYSCON_WIFI_BB_CFG_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_S  0
+
+#define SYSCON_WIFI_BB_CFG_2_REG          (DR_REG_SYSCON_BASE + 0x0D0)
+/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_BB_CFG_2  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_M  ((SYSCON_WIFI_BB_CFG_2_V)<<(SYSCON_WIFI_BB_CFG_2_S))
+#define SYSCON_WIFI_BB_CFG_2_V  0xFFFFFFFF
+#define SYSCON_WIFI_BB_CFG_2_S  0
+
+#define SYSCON_WIFI_CLK_EN_REG          (DR_REG_SYSCON_BASE + 0x0D4)
+/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define SYSCON_WIFI_CLK_EN  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_M  ((SYSCON_WIFI_CLK_EN_V)<<(SYSCON_WIFI_CLK_EN_S))
+#define SYSCON_WIFI_CLK_EN_V  0xFFFFFFFF
+#define SYSCON_WIFI_CLK_EN_S  0
+
+#define SYSCON_WIFI_RST_EN_REG          (DR_REG_SYSCON_BASE + 0x0D8)
+/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define SYSCON_WIFI_RST  0xFFFFFFFF
+#define SYSCON_WIFI_RST_M  ((SYSCON_WIFI_RST_V)<<(SYSCON_WIFI_RST_S))
+#define SYSCON_WIFI_RST_V  0xFFFFFFFF
+#define SYSCON_WIFI_RST_S  0
+
+#define DPORT_WIFI_CLK_EN_REG          SYSCON_WIFI_CLK_EN_REG
+/* DPORT_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
+/*description: */
+#define DPORT_WIFI_CLK_EN  0xFFFFFFFF
+#define DPORT_WIFI_CLK_EN_M  ((DPORT_WIFI_CLK_EN_V)<<(DPORT_WIFI_CLK_EN_S))
+#define DPORT_WIFI_CLK_EN_V  0xFFFFFFFF
+#define DPORT_WIFI_CLK_EN_S  0
+
+/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21
+   Bit15 not included here because of the bit now can't be cleared */
+#define DPORT_WIFI_CLK_WIFI_EN  0x003807cf
+#define DPORT_WIFI_CLK_WIFI_EN_M  ((DPORT_WIFI_CLK_WIFI_EN_V)<<(DPORT_WIFI_CLK_WIFI_EN_S))
+#define DPORT_WIFI_CLK_WIFI_EN_V  0x7cf
+#define DPORT_WIFI_CLK_WIFI_EN_S  0
+/* Mask for all Bluetooth clock bits - 11, 16, 17 */
+#define DPORT_WIFI_CLK_BT_EN  0x61
+#define DPORT_WIFI_CLK_BT_EN_M  ((DPORT_WIFI_CLK_BT_EN_V)<<(DPORT_WIFI_CLK_BT_EN_S))
+#define DPORT_WIFI_CLK_BT_EN_V  0x61
+#define DPORT_WIFI_CLK_BT_EN_S  11
+/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */
+#define DPORT_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9
+
+/* Digital team to check */
+//bluetooth baseband bit11
+#define DPORT_BT_BASEBAND_EN  BIT(11)
+//bluetooth LC bit16 and bit17
+#define DPORT_BT_LC_EN  (BIT(16)|BIT(17))
+
+/* Remaining single bit clock masks */
+#define DPORT_WIFI_CLK_SDIOSLAVE_EN  BIT(4)
+#define DPORT_WIFI_CLK_UNUSED_BIT5  BIT(5)
+#define DPORT_WIFI_CLK_UNUSED_BIT12  BIT(12)
+#define DPORT_WIFI_CLK_SDIO_HOST_EN  BIT(13)
+#define DPORT_WIFI_CLK_EMAC_EN  BIT(14)
+#define DPORT_WIFI_CLK_RNG_EN  BIT(15)
+
+#define DPORT_CORE_RST_EN_REG         DPORT_WIFI_RST_EN_REG
+#define DPORT_WIFI_RST_EN_REG         SYSCON_WIFI_RST_EN_REG
+/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define DPORT_WIFI_RST  0xFFFFFFFF
+#define DPORT_WIFI_RST_M  ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S))
+#define DPORT_WIFI_RST_V  0xFFFFFFFF
+#define DPORT_WIFI_RST_S  0
+#define DPORT_RW_BTLP_RST (BIT(10))
+#define DPORT_RW_BTMAC_RST (BIT(9))
+#define DPORT_MACPWR_RST (BIT(8))
+#define DPORT_EMAC_RST (BIT(7))
+#define DPORT_SDIO_HOST_RST (BIT(6))
+#define DPORT_SDIO_RST (BIT(5))
+#define DPORT_BTMAC_RST (BIT(4))
+#define DPORT_BT_RST (BIT(3))
+#define DPORT_MAC_RST (BIT(2))
+#define DPORT_FE_RST (BIT(1))
+#define DPORT_BB_RST (BIT(0))  
+
+#define SYSCON_FRONT_END_MEM_PD_REG          (DR_REG_SYSCON_BASE + 0x0DC)
+/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_DC_MEM_FORCE_PD  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_M  (BIT(5))
+#define SYSCON_DC_MEM_FORCE_PD_V  0x1
+#define SYSCON_DC_MEM_FORCE_PD_S  5
+/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_DC_MEM_FORCE_PU  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_M  (BIT(4))
+#define SYSCON_DC_MEM_FORCE_PU_V  0x1
+#define SYSCON_DC_MEM_FORCE_PU_S  4
+/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_PBUS_MEM_FORCE_PD  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_M  (BIT(3))
+#define SYSCON_PBUS_MEM_FORCE_PD_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PD_S  3
+/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_PBUS_MEM_FORCE_PU  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_M  (BIT(2))
+#define SYSCON_PBUS_MEM_FORCE_PU_V  0x1
+#define SYSCON_PBUS_MEM_FORCE_PU_S  2
+/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define SYSCON_AGC_MEM_FORCE_PD  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_M  (BIT(1))
+#define SYSCON_AGC_MEM_FORCE_PD_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PD_S  1
+/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSCON_AGC_MEM_FORCE_PU  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_M  (BIT(0))
+#define SYSCON_AGC_MEM_FORCE_PU_V  0x1
+#define SYSCON_AGC_MEM_FORCE_PU_S  0
+
+#define SYSCON_DATE_REG          (DR_REG_SYSCON_BASE + 0x3FC)
+/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h18102500 ; */
+/*description: */
+#define SYSCON_DATE  0xFFFFFFFF
+#define SYSCON_DATE_M  ((SYSCON_DATE_V)<<(SYSCON_DATE_S))
+#define SYSCON_DATE_V  0xFFFFFFFF
+#define SYSCON_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSCON_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/syscon_struct.h b/components/soc/esp32s2beta/include/soc/syscon_struct.h
new file mode 100644
index 000000000..42bd643d1
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/syscon_struct.h
@@ -0,0 +1,123 @@
+// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYSCON_STRUCT_H_
+#define _SOC_SYSCON_STRUCT_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t pre_div:       10;
+            uint32_t clk_320m_en:    1;
+            uint32_t clk_en:         1;
+            uint32_t rst_tick:       1;
+            uint32_t quick_clk_chng: 1;
+            uint32_t reserved14:    18;
+        };
+        uint32_t val;
+    }clk_conf;
+    union {
+        struct {
+            uint32_t xtal_tick:     8;
+            uint32_t reserved8:    24;
+        };
+        uint32_t val;
+    }xtal_tick_conf;
+    union {
+        struct {
+            uint32_t pll_tick:     8;
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    }pll_tick_conf;
+    union {
+        struct {
+            uint32_t ck8m_tick:     8;
+            uint32_t reserved8:    24;
+        };
+        uint32_t val;
+    }ck8m_tick_conf;
+    union {
+        struct {
+            uint32_t start_force:       1;
+            uint32_t start:             1;
+            uint32_t sar2_mux:          1;       /*1: SAR ADC2 is controlled by DIG ADC2 CTRL  0: SAR ADC2 is controlled by PWDET CTRL*/
+            uint32_t work_mode:         2;       /*0: single mode  1: double mode  2: alternate mode*/
+            uint32_t sar_sel:           1;       /*0: SAR1  1: SAR2  only work for single SAR mode*/
+            uint32_t sar_clk_gated:     1;
+            uint32_t sar_clk_div:       8;       /*SAR clock divider*/
+            uint32_t sar1_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
+            uint32_t sar2_patt_len:     4;       /*0 ~ 15 means length 1 ~ 16*/
+            uint32_t sar1_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC1 CTRL*/
+            uint32_t sar2_patt_p_clear: 1;       /*clear the pointer of pattern table for DIG ADC2 CTRL*/
+            uint32_t data_sar_sel:      1;       /*1: sar_sel will be coded by the MSB of the 16-bit output data  in this case the resolution should not be larger than 11 bits.*/
+            uint32_t data_to_i2s:       1;       /*1: I2S input data is from SAR ADC (for DMA)  0: I2S input data is from GPIO matrix*/
+            uint32_t reserved27:        5;
+        };
+        uint32_t val;
+    }saradc_ctrl;
+    union {
+        struct {
+            uint32_t meas_num_limit: 1;
+            uint32_t max_meas_num:   8;          /*max conversion number*/
+            uint32_t sar1_inv:       1;          /*1: data to DIG ADC1 CTRL is inverted  otherwise not*/
+            uint32_t sar2_inv:       1;          /*1: data to DIG ADC2 CTRL is inverted  otherwise not*/
+            uint32_t reserved11:    21;
+        };
+        uint32_t val;
+    }saradc_ctrl2;
+    union {
+        struct {
+            uint32_t rstb_wait:    8;
+            uint32_t standby_wait: 8;
+            uint32_t start_wait:   8;
+            uint32_t sample_cycle: 8;            /*sample cycles*/
+        };
+        uint32_t val;
+    }saradc_fsm;
+    uint32_t saradc_sar1_patt_tab[4];                 /*item 0 ~ 3 for ADC1 pattern table*/
+    uint32_t saradc_sar2_patt_tab[4];                 /*item 0 ~ 3 for ADC2 pattern table*/
+    union {
+        struct {
+            uint32_t apll_tick:     8;
+            uint32_t reserved8:    24;
+        };
+        uint32_t val;
+    }apll_tick_conf;
+    uint32_t reserved_40;
+    uint32_t reserved_44;
+    uint32_t reserved_48;
+    uint32_t reserved_4c;
+    uint32_t reserved_50;
+    uint32_t reserved_54;
+    uint32_t reserved_58;
+    uint32_t reserved_5c;
+    uint32_t reserved_60;
+    uint32_t reserved_64;
+    uint32_t reserved_68;
+    uint32_t reserved_6c;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t reserved_78;
+    uint32_t date;                                      /**/
+} syscon_dev_t;
+
+#ifdef __cplusplus
+}
+#endif
+extern syscon_dev_t SYSCON;
+#endif  /* _SOC_SYSCON_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/system_reg.h b/components/soc/esp32s2beta/include/soc/system_reg.h
new file mode 100644
index 000000000..2fc5512e0
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/system_reg.h
@@ -0,0 +1,891 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_SYSTEM_REG_H_
+#define _SOC_SYSTEM_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define DPORT_ROM_CTRL_0_REG          (DR_REG_SYSTEM_BASE + 0x000)
+/* DPORT_ROM_FO : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */
+/*description: */
+#define DPORT_ROM_FO  0x00000003
+#define DPORT_ROM_FO_M  ((DPORT_ROM_FO_V)<<(DPORT_ROM_FO_S))
+#define DPORT_ROM_FO_V  0x3
+#define DPORT_ROM_FO_S  0
+
+#define DPORT_ROM_CTRL_1_REG          (DR_REG_SYSTEM_BASE + 0x004)
+/* DPORT_ROM_PD : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_ROM_PD  0x00000003
+#define DPORT_ROM_PD_M  ((DPORT_ROM_PD_V)<<(DPORT_ROM_PD_S))
+#define DPORT_ROM_PD_V  0x3
+#define DPORT_ROM_PD_S  0
+
+#define DPORT_SRAM_CTRL_0_REG          (DR_REG_SYSTEM_BASE + 0x008)
+/* DPORT_SRAM_FO : R/W ;bitpos:[21:0] ;default: ~22'b0 ; */
+/*description: */
+#define DPORT_SRAM_FO  0x003FFFFF
+#define DPORT_SRAM_FO_M  ((DPORT_SRAM_FO_V)<<(DPORT_SRAM_FO_S))
+#define DPORT_SRAM_FO_V  0x3FFFFF
+#define DPORT_SRAM_FO_S  0
+
+#define DPORT_SRAM_CTRL_1_REG          (DR_REG_SYSTEM_BASE + 0x00C)
+/* DPORT_SRAM_PD : R/W ;bitpos:[21:0] ;default: 22'b0 ; */
+/*description: */
+#define DPORT_SRAM_PD  0x003FFFFF
+#define DPORT_SRAM_PD_M  ((DPORT_SRAM_PD_V)<<(DPORT_SRAM_PD_S))
+#define DPORT_SRAM_PD_V  0x3FFFFF
+#define DPORT_SRAM_PD_S  0
+
+#define DPORT_PERI_CLK_EN_REG DPORT_CPU_PERI_CLK_EN_REG
+#define DPORT_CPU_PERI_CLK_EN_REG          (DR_REG_SYSTEM_BASE + 0x010)
+/* DPORT_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_DEDICATED_GPIO  (BIT(7))
+#define DPORT_CLK_EN_DEDICATED_GPIO_M  (BIT(7))
+#define DPORT_CLK_EN_DEDICATED_GPIO_V  0x1
+#define DPORT_CLK_EN_DEDICATED_GPIO_S  7
+/* DPORT_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_ASSIST_DEBUG  (BIT(6))
+#define DPORT_CLK_EN_ASSIST_DEBUG_M  (BIT(6))
+#define DPORT_CLK_EN_ASSIST_DEBUG_V  0x1
+#define DPORT_CLK_EN_ASSIST_DEBUG_S  6
+/* DPORT_CLK_EN_DIGITAL_SIGNATURE : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_DIGITAL_SIGNATURE  (BIT(5))
+#define DPORT_CLK_EN_DIGITAL_SIGNATURE_M  (BIT(5))
+#define DPORT_CLK_EN_DIGITAL_SIGNATURE_V  0x1
+#define DPORT_CLK_EN_DIGITAL_SIGNATURE_S  5
+/* DPORT_CLK_EN_HMAC : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_HMAC  (BIT(4))
+#define DPORT_CLK_EN_HMAC_M  (BIT(4))
+#define DPORT_CLK_EN_HMAC_V  0x1
+#define DPORT_CLK_EN_HMAC_S  4
+/* DPORT_CLK_EN_SECURE_BOOT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_SECURE_BOOT  (BIT(3))
+#define DPORT_CLK_EN_SECURE_BOOT_M  (BIT(3))
+#define DPORT_CLK_EN_SECURE_BOOT_V  0x1
+#define DPORT_CLK_EN_SECURE_BOOT_S  3
+/* DPORT_CLK_EN_RSA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_RSA  (BIT(2))
+#define DPORT_CLK_EN_RSA_M  (BIT(2))
+#define DPORT_CLK_EN_RSA_V  0x1
+#define DPORT_CLK_EN_RSA_S  2
+/* DPORT_CLK_EN_SHA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_SHA  (BIT(1))
+#define DPORT_CLK_EN_SHA_M  (BIT(1))
+#define DPORT_CLK_EN_SHA_V  0x1
+#define DPORT_CLK_EN_SHA_S  1
+/* DPORT_CLK_EN_AES : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CLK_EN_AES  (BIT(0))
+#define DPORT_CLK_EN_AES_M  (BIT(0))
+#define DPORT_CLK_EN_AES_V  0x1
+#define DPORT_CLK_EN_AES_S  0
+
+#define DPORT_PERI_EN_AES DPORT_CLK_EN_AES
+#define DPORT_PERI_EN_SHA DPORT_CLK_EN_SHA
+#define DPORT_PERI_EN_RSA DPORT_CLK_EN_RSA
+/* NB: Secure boot reset will hold SHA & AES in reset */
+#define DPORT_PERI_EN_SECUREBOOT DPORT_CLK_EN_SECURE_BOOT
+/* NB: Digital signature reset will hold AES & RSA in reset */
+#define DPORT_PERI_EN_DIGITAL_SIGNATURE DPORT_CLK_EN_DIGITAL_SIGNATURE
+#define DPORT_PERI_EN_ASSIST_DEBUG DPORT_CLK_EN_ASSIST_DEBUG
+
+#define DPORT_PERI_RST_EN_REG DPORT_CPU_PERI_RST_EN_REG
+#define DPORT_CPU_PERI_RST_EN_REG          (DR_REG_SYSTEM_BASE + 0x014)
+/* DPORT_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_DEDICATED_GPIO  (BIT(7))
+#define DPORT_RST_EN_DEDICATED_GPIO_M  (BIT(7))
+#define DPORT_RST_EN_DEDICATED_GPIO_V  0x1
+#define DPORT_RST_EN_DEDICATED_GPIO_S  7
+/* DPORT_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_ASSIST_DEBUG  (BIT(6))
+#define DPORT_RST_EN_ASSIST_DEBUG_M  (BIT(6))
+#define DPORT_RST_EN_ASSIST_DEBUG_V  0x1
+#define DPORT_RST_EN_ASSIST_DEBUG_S  6
+/* DPORT_RST_EN_DIGITAL_SIGNATURE : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_DIGITAL_SIGNATURE  (BIT(5))
+#define DPORT_RST_EN_DIGITAL_SIGNATURE_M  (BIT(5))
+#define DPORT_RST_EN_DIGITAL_SIGNATURE_V  0x1
+#define DPORT_RST_EN_DIGITAL_SIGNATURE_S  5
+/* DPORT_RST_EN_HMAC : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_HMAC  (BIT(4))
+#define DPORT_RST_EN_HMAC_M  (BIT(4))
+#define DPORT_RST_EN_HMAC_V  0x1
+#define DPORT_RST_EN_HMAC_S  4
+/* DPORT_RST_EN_SECURE_BOOT : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_SECURE_BOOT  (BIT(3))
+#define DPORT_RST_EN_SECURE_BOOT_M  (BIT(3))
+#define DPORT_RST_EN_SECURE_BOOT_V  0x1
+#define DPORT_RST_EN_SECURE_BOOT_S  3
+/* DPORT_RST_EN_RSA : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_RSA  (BIT(2))
+#define DPORT_RST_EN_RSA_M  (BIT(2))
+#define DPORT_RST_EN_RSA_V  0x1
+#define DPORT_RST_EN_RSA_S  2
+/* DPORT_RST_EN_SHA : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_SHA  (BIT(1))
+#define DPORT_RST_EN_SHA_M  (BIT(1))
+#define DPORT_RST_EN_SHA_V  0x1
+#define DPORT_RST_EN_SHA_S  1
+/* DPORT_RST_EN_AES : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RST_EN_AES  (BIT(0))
+#define DPORT_RST_EN_AES_M  (BIT(0))
+#define DPORT_RST_EN_AES_V  0x1
+#define DPORT_RST_EN_AES_S  0
+
+#define DPORT_CPU_PER_CONF_REG          (DR_REG_SYSTEM_BASE + 0x018)
+/* DPORT_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_CPU_WAIT_MODE_FORCE_ON  (BIT(3))
+#define DPORT_CPU_WAIT_MODE_FORCE_ON_M  (BIT(3))
+#define DPORT_CPU_WAIT_MODE_FORCE_ON_V  0x1
+#define DPORT_CPU_WAIT_MODE_FORCE_ON_S  3
+/* DPORT_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PLL_FREQ_SEL  (BIT(2))
+#define DPORT_PLL_FREQ_SEL_M  (BIT(2))
+#define DPORT_PLL_FREQ_SEL_V  0x1
+#define DPORT_PLL_FREQ_SEL_S  2
+/* DPORT_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */
+/*description: */
+#define DPORT_CPUPERIOD_SEL  0x00000003
+#define DPORT_CPUPERIOD_SEL_M  ((DPORT_CPUPERIOD_SEL_V)<<(DPORT_CPUPERIOD_SEL_S))
+#define DPORT_CPUPERIOD_SEL_V  0x3
+#define DPORT_CPUPERIOD_SEL_S  0
+
+#define DPORT_JTAG_CTRL_0_REG          (DR_REG_SYSTEM_BASE + 0x01C)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S  0
+
+#define DPORT_JTAG_CTRL_1_REG          (DR_REG_SYSTEM_BASE + 0x020)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S  0
+
+#define DPORT_JTAG_CTRL_2_REG          (DR_REG_SYSTEM_BASE + 0x024)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S  0
+
+#define DPORT_JTAG_CTRL_3_REG          (DR_REG_SYSTEM_BASE + 0x028)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S  0
+
+#define DPORT_JTAG_CTRL_4_REG          (DR_REG_SYSTEM_BASE + 0x02C)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S  0
+
+#define DPORT_JTAG_CTRL_5_REG          (DR_REG_SYSTEM_BASE + 0x030)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S  0
+
+#define DPORT_JTAG_CTRL_6_REG          (DR_REG_SYSTEM_BASE + 0x034)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S  0
+
+#define DPORT_JTAG_CTRL_7_REG          (DR_REG_SYSTEM_BASE + 0x038)
+/* DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M  ((DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V)<<(DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S))
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V  0xFFFFFFFF
+#define DPORT_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S  0
+
+#define DPORT_MEM_PD_MASK_REG          (DR_REG_SYSTEM_BASE + 0x03C)
+/* DPORT_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_LSLP_MEM_PD_MASK  (BIT(0))
+#define DPORT_LSLP_MEM_PD_MASK_M  (BIT(0))
+#define DPORT_LSLP_MEM_PD_MASK_V  0x1
+#define DPORT_LSLP_MEM_PD_MASK_S  0
+
+#define DPORT_PERIP_CLK_EN_REG DPORT_PERIP_CLK_EN0_REG
+#define DPORT_PERIP_CLK_EN0_REG          (DR_REG_SYSTEM_BASE + 0x040)
+/* DPORT_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */
+/*description: */
+#define DPORT_SPI4_CLK_EN  (BIT(31))
+#define DPORT_SPI4_CLK_EN_M  (BIT(31))
+#define DPORT_SPI4_CLK_EN_V  0x1
+#define DPORT_SPI4_CLK_EN_S  31
+/* DPORT_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_ADC2_ARB_CLK_EN  (BIT(30))
+#define DPORT_ADC2_ARB_CLK_EN_M  (BIT(30))
+#define DPORT_ADC2_ARB_CLK_EN_V  0x1
+#define DPORT_ADC2_ARB_CLK_EN_S  30
+/* DPORT_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_SYSTIMER_CLK_EN  (BIT(29))
+#define DPORT_SYSTIMER_CLK_EN_M  (BIT(29))
+#define DPORT_SYSTIMER_CLK_EN_V  0x1
+#define DPORT_SYSTIMER_CLK_EN_S  29
+/* DPORT_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_APB_SARADC_CLK_EN  (BIT(28))
+#define DPORT_APB_SARADC_CLK_EN_M  (BIT(28))
+#define DPORT_APB_SARADC_CLK_EN_V  0x1
+#define DPORT_APB_SARADC_CLK_EN_S  28
+/* DPORT_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_SPI3_DMA_CLK_EN  (BIT(27))
+#define DPORT_SPI3_DMA_CLK_EN_M  (BIT(27))
+#define DPORT_SPI3_DMA_CLK_EN_V  0x1
+#define DPORT_SPI3_DMA_CLK_EN_S  27
+/* DPORT_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM3_CLK_EN  (BIT(26))
+#define DPORT_PWM3_CLK_EN_M  (BIT(26))
+#define DPORT_PWM3_CLK_EN_V  0x1
+#define DPORT_PWM3_CLK_EN_S  26
+/* DPORT_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM2_CLK_EN  (BIT(25))
+#define DPORT_PWM2_CLK_EN_M  (BIT(25))
+#define DPORT_PWM2_CLK_EN_V  0x1
+#define DPORT_PWM2_CLK_EN_S  25
+/* DPORT_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_UART_MEM_CLK_EN  (BIT(24))
+#define DPORT_UART_MEM_CLK_EN_M  (BIT(24))
+#define DPORT_UART_MEM_CLK_EN_V  0x1
+#define DPORT_UART_MEM_CLK_EN_S  24
+/* DPORT_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_USB_CLK_EN  (BIT(23))
+#define DPORT_USB_CLK_EN_M  (BIT(23))
+#define DPORT_USB_CLK_EN_V  0x1
+#define DPORT_USB_CLK_EN_S  23
+/* DPORT_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_SPI2_DMA_CLK_EN  (BIT(22))
+#define DPORT_SPI2_DMA_CLK_EN_M  (BIT(22))
+#define DPORT_SPI2_DMA_CLK_EN_V  0x1
+#define DPORT_SPI2_DMA_CLK_EN_S  22
+/* DPORT_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2S1_CLK_EN  (BIT(21))
+#define DPORT_I2S1_CLK_EN_M  (BIT(21))
+#define DPORT_I2S1_CLK_EN_V  0x1
+#define DPORT_I2S1_CLK_EN_S  21
+/* DPORT_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM1_CLK_EN  (BIT(20))
+#define DPORT_PWM1_CLK_EN_M  (BIT(20))
+#define DPORT_PWM1_CLK_EN_V  0x1
+#define DPORT_PWM1_CLK_EN_S  20
+/* DPORT_CAN_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CAN_CLK_EN  (BIT(19))
+#define DPORT_CAN_CLK_EN_M  (BIT(19))
+#define DPORT_CAN_CLK_EN_V  0x1
+#define DPORT_CAN_CLK_EN_S  19
+/* DPORT_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2C_EXT1_CLK_EN  (BIT(18))
+#define DPORT_I2C_EXT1_CLK_EN_M  (BIT(18))
+#define DPORT_I2C_EXT1_CLK_EN_V  0x1
+#define DPORT_I2C_EXT1_CLK_EN_S  18
+/* DPORT_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM0_CLK_EN  (BIT(17))
+#define DPORT_PWM0_CLK_EN_M  (BIT(17))
+#define DPORT_PWM0_CLK_EN_V  0x1
+#define DPORT_PWM0_CLK_EN_S  17
+/* DPORT_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_SPI3_CLK_EN  (BIT(16))
+#define DPORT_SPI3_CLK_EN_M  (BIT(16))
+#define DPORT_SPI3_CLK_EN_V  0x1
+#define DPORT_SPI3_CLK_EN_S  16
+/* DPORT_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_TIMERGROUP1_CLK_EN  (BIT(15))
+#define DPORT_TIMERGROUP1_CLK_EN_M  (BIT(15))
+#define DPORT_TIMERGROUP1_CLK_EN_V  0x1
+#define DPORT_TIMERGROUP1_CLK_EN_S  15
+/* DPORT_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_EFUSE_CLK_EN  (BIT(14))
+#define DPORT_EFUSE_CLK_EN_M  (BIT(14))
+#define DPORT_EFUSE_CLK_EN_V  0x1
+#define DPORT_EFUSE_CLK_EN_S  14
+/* DPORT_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_TIMERGROUP_CLK_EN  (BIT(13))
+#define DPORT_TIMERGROUP_CLK_EN_M  (BIT(13))
+#define DPORT_TIMERGROUP_CLK_EN_V  0x1
+#define DPORT_TIMERGROUP_CLK_EN_S  13
+/* DPORT_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_UHCI1_CLK_EN  (BIT(12))
+#define DPORT_UHCI1_CLK_EN_M  (BIT(12))
+#define DPORT_UHCI1_CLK_EN_V  0x1
+#define DPORT_UHCI1_CLK_EN_S  12
+/* DPORT_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LEDC_CLK_EN  (BIT(11))
+#define DPORT_LEDC_CLK_EN_M  (BIT(11))
+#define DPORT_LEDC_CLK_EN_V  0x1
+#define DPORT_LEDC_CLK_EN_S  11
+/* DPORT_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PCNT_CLK_EN  (BIT(10))
+#define DPORT_PCNT_CLK_EN_M  (BIT(10))
+#define DPORT_PCNT_CLK_EN_V  0x1
+#define DPORT_PCNT_CLK_EN_S  10
+/* DPORT_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_RMT_CLK_EN  (BIT(9))
+#define DPORT_RMT_CLK_EN_M  (BIT(9))
+#define DPORT_RMT_CLK_EN_V  0x1
+#define DPORT_RMT_CLK_EN_S  9
+/* DPORT_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_UHCI0_CLK_EN  (BIT(8))
+#define DPORT_UHCI0_CLK_EN_M  (BIT(8))
+#define DPORT_UHCI0_CLK_EN_V  0x1
+#define DPORT_UHCI0_CLK_EN_S  8
+/* DPORT_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2C_EXT0_CLK_EN  (BIT(7))
+#define DPORT_I2C_EXT0_CLK_EN_M  (BIT(7))
+#define DPORT_I2C_EXT0_CLK_EN_V  0x1
+#define DPORT_I2C_EXT0_CLK_EN_S  7
+/* DPORT_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_SPI2_CLK_EN  (BIT(6))
+#define DPORT_SPI2_CLK_EN_M  (BIT(6))
+#define DPORT_SPI2_CLK_EN_V  0x1
+#define DPORT_SPI2_CLK_EN_S  6
+/* DPORT_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_UART1_CLK_EN  (BIT(5))
+#define DPORT_UART1_CLK_EN_M  (BIT(5))
+#define DPORT_UART1_CLK_EN_V  0x1
+#define DPORT_UART1_CLK_EN_S  5
+/* DPORT_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2S0_CLK_EN  (BIT(4))
+#define DPORT_I2S0_CLK_EN_M  (BIT(4))
+#define DPORT_I2S0_CLK_EN_V  0x1
+#define DPORT_I2S0_CLK_EN_S  4
+/* DPORT_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_WDG_CLK_EN  (BIT(3))
+#define DPORT_WDG_CLK_EN_M  (BIT(3))
+#define DPORT_WDG_CLK_EN_V  0x1
+#define DPORT_WDG_CLK_EN_S  3
+/* DPORT_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_UART_CLK_EN  (BIT(2))
+#define DPORT_UART_CLK_EN_M  (BIT(2))
+#define DPORT_UART_CLK_EN_V  0x1
+#define DPORT_UART_CLK_EN_S  2
+/* DPORT_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_SPI01_CLK_EN  (BIT(1))
+#define DPORT_SPI01_CLK_EN_M  (BIT(1))
+#define DPORT_SPI01_CLK_EN_V  0x1
+#define DPORT_SPI01_CLK_EN_S  1
+/* DPORT_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_TIMERS_CLK_EN  (BIT(0))
+#define DPORT_TIMERS_CLK_EN_M  (BIT(0))
+#define DPORT_TIMERS_CLK_EN_V  0x1
+#define DPORT_TIMERS_CLK_EN_S  0
+
+#define DPORT_PERIP_CLK_EN1_REG          (DR_REG_SYSTEM_BASE + 0x044)
+/* DPORT_SPI_SHARED_DMA_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_SPI_SHARED_DMA_CLK_EN  (BIT(0))
+#define DPORT_SPI_SHARED_DMA_CLK_EN_M  (BIT(0))
+#define DPORT_SPI_SHARED_DMA_CLK_EN_V  0x1
+#define DPORT_SPI_SHARED_DMA_CLK_EN_S  0
+
+#define DPORT_PERIP_RST_EN_REG DPORT_PERIP_RST_EN0_REG
+#define DPORT_PERIP_RST_EN0_REG          (DR_REG_SYSTEM_BASE + 0x048)
+/* DPORT_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define DPORT_SPI4_RST  (BIT(31))
+#define DPORT_SPI4_RST_M  (BIT(31))
+#define DPORT_SPI4_RST_V  0x1
+#define DPORT_SPI4_RST_S  31
+/* DPORT_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ADC2_ARB_RST  (BIT(30))
+#define DPORT_ADC2_ARB_RST_M  (BIT(30))
+#define DPORT_ADC2_ARB_RST_V  0x1
+#define DPORT_ADC2_ARB_RST_S  30
+/* DPORT_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SYSTIMER_RST  (BIT(29))
+#define DPORT_SYSTIMER_RST_M  (BIT(29))
+#define DPORT_SYSTIMER_RST_V  0x1
+#define DPORT_SYSTIMER_RST_S  29
+/* DPORT_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_APB_SARADC_RST  (BIT(28))
+#define DPORT_APB_SARADC_RST_M  (BIT(28))
+#define DPORT_APB_SARADC_RST_V  0x1
+#define DPORT_APB_SARADC_RST_S  28
+/* DPORT_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI3_DMA_RST  (BIT(27))
+#define DPORT_SPI3_DMA_RST_M  (BIT(27))
+#define DPORT_SPI3_DMA_RST_V  0x1
+#define DPORT_SPI3_DMA_RST_S  27
+/* DPORT_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM3_RST  (BIT(26))
+#define DPORT_PWM3_RST_M  (BIT(26))
+#define DPORT_PWM3_RST_V  0x1
+#define DPORT_PWM3_RST_S  26
+/* DPORT_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM2_RST  (BIT(25))
+#define DPORT_PWM2_RST_M  (BIT(25))
+#define DPORT_PWM2_RST_V  0x1
+#define DPORT_PWM2_RST_S  25
+/* DPORT_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_UART_MEM_RST  (BIT(24))
+#define DPORT_UART_MEM_RST_M  (BIT(24))
+#define DPORT_UART_MEM_RST_V  0x1
+#define DPORT_UART_MEM_RST_S  24
+/* DPORT_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_USB_RST  (BIT(23))
+#define DPORT_USB_RST_M  (BIT(23))
+#define DPORT_USB_RST_V  0x1
+#define DPORT_USB_RST_S  23
+/* DPORT_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI2_DMA_RST  (BIT(22))
+#define DPORT_SPI2_DMA_RST_M  (BIT(22))
+#define DPORT_SPI2_DMA_RST_V  0x1
+#define DPORT_SPI2_DMA_RST_S  22
+/* DPORT_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2S1_RST  (BIT(21))
+#define DPORT_I2S1_RST_M  (BIT(21))
+#define DPORT_I2S1_RST_V  0x1
+#define DPORT_I2S1_RST_S  21
+/* DPORT_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM1_RST  (BIT(20))
+#define DPORT_PWM1_RST_M  (BIT(20))
+#define DPORT_PWM1_RST_V  0x1
+#define DPORT_PWM1_RST_S  20
+/* DPORT_CAN_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CAN_RST  (BIT(19))
+#define DPORT_CAN_RST_M  (BIT(19))
+#define DPORT_CAN_RST_V  0x1
+#define DPORT_CAN_RST_S  19
+/* DPORT_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2C_EXT1_RST  (BIT(18))
+#define DPORT_I2C_EXT1_RST_M  (BIT(18))
+#define DPORT_I2C_EXT1_RST_V  0x1
+#define DPORT_I2C_EXT1_RST_S  18
+/* DPORT_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PWM0_RST  (BIT(17))
+#define DPORT_PWM0_RST_M  (BIT(17))
+#define DPORT_PWM0_RST_V  0x1
+#define DPORT_PWM0_RST_S  17
+/* DPORT_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI3_RST  (BIT(16))
+#define DPORT_SPI3_RST_M  (BIT(16))
+#define DPORT_SPI3_RST_V  0x1
+#define DPORT_SPI3_RST_S  16
+/* DPORT_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_TIMERGROUP1_RST  (BIT(15))
+#define DPORT_TIMERGROUP1_RST_M  (BIT(15))
+#define DPORT_TIMERGROUP1_RST_V  0x1
+#define DPORT_TIMERGROUP1_RST_S  15
+/* DPORT_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_EFUSE_RST  (BIT(14))
+#define DPORT_EFUSE_RST_M  (BIT(14))
+#define DPORT_EFUSE_RST_V  0x1
+#define DPORT_EFUSE_RST_S  14
+/* DPORT_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_TIMERGROUP_RST  (BIT(13))
+#define DPORT_TIMERGROUP_RST_M  (BIT(13))
+#define DPORT_TIMERGROUP_RST_V  0x1
+#define DPORT_TIMERGROUP_RST_S  13
+/* DPORT_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_UHCI1_RST  (BIT(12))
+#define DPORT_UHCI1_RST_M  (BIT(12))
+#define DPORT_UHCI1_RST_V  0x1
+#define DPORT_UHCI1_RST_S  12
+/* DPORT_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LEDC_RST  (BIT(11))
+#define DPORT_LEDC_RST_M  (BIT(11))
+#define DPORT_LEDC_RST_V  0x1
+#define DPORT_LEDC_RST_S  11
+/* DPORT_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PCNT_RST  (BIT(10))
+#define DPORT_PCNT_RST_M  (BIT(10))
+#define DPORT_PCNT_RST_V  0x1
+#define DPORT_PCNT_RST_S  10
+/* DPORT_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_RMT_RST  (BIT(9))
+#define DPORT_RMT_RST_M  (BIT(9))
+#define DPORT_RMT_RST_V  0x1
+#define DPORT_RMT_RST_S  9
+/* DPORT_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_UHCI0_RST  (BIT(8))
+#define DPORT_UHCI0_RST_M  (BIT(8))
+#define DPORT_UHCI0_RST_V  0x1
+#define DPORT_UHCI0_RST_S  8
+/* DPORT_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2C_EXT0_RST  (BIT(7))
+#define DPORT_I2C_EXT0_RST_M  (BIT(7))
+#define DPORT_I2C_EXT0_RST_V  0x1
+#define DPORT_I2C_EXT0_RST_S  7
+/* DPORT_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI2_RST  (BIT(6))
+#define DPORT_SPI2_RST_M  (BIT(6))
+#define DPORT_SPI2_RST_V  0x1
+#define DPORT_SPI2_RST_S  6
+/* DPORT_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_UART1_RST  (BIT(5))
+#define DPORT_UART1_RST_M  (BIT(5))
+#define DPORT_UART1_RST_V  0x1
+#define DPORT_UART1_RST_S  5
+/* DPORT_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_I2S0_RST  (BIT(4))
+#define DPORT_I2S0_RST_M  (BIT(4))
+#define DPORT_I2S0_RST_V  0x1
+#define DPORT_I2S0_RST_S  4
+/* DPORT_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_WDG_RST  (BIT(3))
+#define DPORT_WDG_RST_M  (BIT(3))
+#define DPORT_WDG_RST_V  0x1
+#define DPORT_WDG_RST_S  3
+/* DPORT_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_UART_RST  (BIT(2))
+#define DPORT_UART_RST_M  (BIT(2))
+#define DPORT_UART_RST_V  0x1
+#define DPORT_UART_RST_S  2
+/* DPORT_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI01_RST  (BIT(1))
+#define DPORT_SPI01_RST_M  (BIT(1))
+#define DPORT_SPI01_RST_V  0x1
+#define DPORT_SPI01_RST_S  1
+/* DPORT_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_TIMERS_RST  (BIT(0))
+#define DPORT_TIMERS_RST_M  (BIT(0))
+#define DPORT_TIMERS_RST_V  0x1
+#define DPORT_TIMERS_RST_S  0
+
+#define DPORT_PERIP_RST_EN1_REG          (DR_REG_SYSTEM_BASE + 0x04C)
+/* DPORT_SPI_SHARED_DMA_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI_SHARED_DMA_RST  (BIT(0))
+#define DPORT_SPI_SHARED_DMA_RST_M  (BIT(0))
+#define DPORT_SPI_SHARED_DMA_RST_V  0x1
+#define DPORT_SPI_SHARED_DMA_RST_S  0
+
+#define DPORT_BT_LPCK_DIV_INT_REG          (DR_REG_SYSTEM_BASE + 0x050)
+/* DPORT_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */
+/*description: */
+#define DPORT_BT_LPCK_DIV_NUM  0x00000FFF
+#define DPORT_BT_LPCK_DIV_NUM_M  ((DPORT_BT_LPCK_DIV_NUM_V)<<(DPORT_BT_LPCK_DIV_NUM_S))
+#define DPORT_BT_LPCK_DIV_NUM_V  0xFFF
+#define DPORT_BT_LPCK_DIV_NUM_S  0
+
+#define DPORT_BT_LPCK_DIV_FRAC_REG          (DR_REG_SYSTEM_BASE + 0x054)
+/* DPORT_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LPCLK_RTC_EN  (BIT(28))
+#define DPORT_LPCLK_RTC_EN_M  (BIT(28))
+#define DPORT_LPCLK_RTC_EN_V  0x1
+#define DPORT_LPCLK_RTC_EN_S  28
+/* DPORT_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_XTAL32K  (BIT(27))
+#define DPORT_LPCLK_SEL_XTAL32K_M  (BIT(27))
+#define DPORT_LPCLK_SEL_XTAL32K_V  0x1
+#define DPORT_LPCLK_SEL_XTAL32K_S  27
+/* DPORT_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_XTAL  (BIT(26))
+#define DPORT_LPCLK_SEL_XTAL_M  (BIT(26))
+#define DPORT_LPCLK_SEL_XTAL_V  0x1
+#define DPORT_LPCLK_SEL_XTAL_S  26
+/* DPORT_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_8M  (BIT(25))
+#define DPORT_LPCLK_SEL_8M_M  (BIT(25))
+#define DPORT_LPCLK_SEL_8M_V  0x1
+#define DPORT_LPCLK_SEL_8M_S  25
+/* DPORT_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_LPCLK_SEL_RTC_SLOW  (BIT(24))
+#define DPORT_LPCLK_SEL_RTC_SLOW_M  (BIT(24))
+#define DPORT_LPCLK_SEL_RTC_SLOW_V  0x1
+#define DPORT_LPCLK_SEL_RTC_SLOW_S  24
+/* DPORT_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */
+/*description: */
+#define DPORT_BT_LPCK_DIV_A  0x00000FFF
+#define DPORT_BT_LPCK_DIV_A_M  ((DPORT_BT_LPCK_DIV_A_V)<<(DPORT_BT_LPCK_DIV_A_S))
+#define DPORT_BT_LPCK_DIV_A_V  0xFFF
+#define DPORT_BT_LPCK_DIV_A_S  12
+/* DPORT_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */
+/*description: */
+#define DPORT_BT_LPCK_DIV_B  0x00000FFF
+#define DPORT_BT_LPCK_DIV_B_M  ((DPORT_BT_LPCK_DIV_B_V)<<(DPORT_BT_LPCK_DIV_B_S))
+#define DPORT_BT_LPCK_DIV_B_V  0xFFF
+#define DPORT_BT_LPCK_DIV_B_S  0
+
+#define DPORT_CPU_INTR_FROM_CPU_0_REG          (DR_REG_SYSTEM_BASE + 0x058)
+/* DPORT_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_0  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_0_M  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_0_V  0x1
+#define DPORT_CPU_INTR_FROM_CPU_0_S  0
+
+#define DPORT_CPU_INTR_FROM_CPU_1_REG          (DR_REG_SYSTEM_BASE + 0x05C)
+/* DPORT_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_1  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_1_M  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_1_V  0x1
+#define DPORT_CPU_INTR_FROM_CPU_1_S  0
+
+#define DPORT_CPU_INTR_FROM_CPU_2_REG          (DR_REG_SYSTEM_BASE + 0x060)
+/* DPORT_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_2  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_2_M  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_2_V  0x1
+#define DPORT_CPU_INTR_FROM_CPU_2_S  0
+
+#define DPORT_CPU_INTR_FROM_CPU_3_REG          (DR_REG_SYSTEM_BASE + 0x064)
+/* DPORT_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_CPU_INTR_FROM_CPU_3  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_3_M  (BIT(0))
+#define DPORT_CPU_INTR_FROM_CPU_3_V  0x1
+#define DPORT_CPU_INTR_FROM_CPU_3_S  0
+
+#define DPORT_RSA_PD_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x068)
+/* DPORT_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_RSA_MEM_PD  (BIT(0))
+#define DPORT_RSA_MEM_PD_M  (BIT(0))
+#define DPORT_RSA_MEM_PD_V  0x1
+#define DPORT_RSA_MEM_PD_S  0
+#define DPORT_RSA_PD DPORT_RSA_MEM_PD
+
+#define DPORT_SPI_DMA_CHAN_SEL_REG DPORT_SPI_SHARED_DMA_SEL_REG
+#define DPORT_SPI_SHARED_DMA_SEL_REG          (DR_REG_SYSTEM_BASE + 0x06C)
+/* DPORT_SPI_SHARED_DMA_SEL : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_SPI_SHARED_DMA_SEL  (BIT(0))
+#define DPORT_SPI_SHARED_DMA_SEL_M  (BIT(0))
+#define DPORT_SPI_SHARED_DMA_SEL_V  0x1
+#define DPORT_SPI_SHARED_DMA_SEL_S  0
+
+#define DPORT_BUSTOEXTMEM_ENA_REG          (DR_REG_SYSTEM_BASE + 0x070)
+/* DPORT_BUSTOEXTMEM_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_BUSTOEXTMEM_ENA  (BIT(0))
+#define DPORT_BUSTOEXTMEM_ENA_M  (BIT(0))
+#define DPORT_BUSTOEXTMEM_ENA_V  0x1
+#define DPORT_BUSTOEXTMEM_ENA_S  0
+
+#define DPORT_CACHE_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x074)
+/* DPORT_PRO_CACHE_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_PRO_CACHE_RESET  (BIT(2))
+#define DPORT_PRO_CACHE_RESET_M  (BIT(2))
+#define DPORT_PRO_CACHE_RESET_V  0x1
+#define DPORT_PRO_CACHE_RESET_S  2
+/* DPORT_PRO_DCACHE_CLK_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_DCACHE_CLK_ON  (BIT(1))
+#define DPORT_PRO_DCACHE_CLK_ON_M  (BIT(1))
+#define DPORT_PRO_DCACHE_CLK_ON_V  0x1
+#define DPORT_PRO_DCACHE_CLK_ON_S  1
+/* DPORT_PRO_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define DPORT_PRO_ICACHE_CLK_ON  (BIT(0))
+#define DPORT_PRO_ICACHE_CLK_ON_M  (BIT(0))
+#define DPORT_PRO_ICACHE_CLK_ON_V  0x1
+#define DPORT_PRO_ICACHE_CLK_ON_S  0
+
+#define DPORT_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG          (DR_REG_SYSTEM_BASE + 0x078)
+/* DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT  (BIT(3))
+#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M  (BIT(3))
+#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V  0x1
+#define DPORT_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S  3
+/* DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT  (BIT(2))
+#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_M  (BIT(2))
+#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_V  0x1
+#define DPORT_ENABLE_DOWNLOAD_G0CB_DECRYPT_S  2
+/* DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT  (BIT(1))
+#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_M  (BIT(1))
+#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_V  0x1
+#define DPORT_ENABLE_DOWNLOAD_DB_ENCRYPT_S  1
+/* DPORT_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT  (BIT(0))
+#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_M  (BIT(0))
+#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_V  0x1
+#define DPORT_ENABLE_SPI_MANUAL_ENCRYPT_S  0
+
+#define DPORT_RTC_FASTMEM_CONFIG_REG          (DR_REG_SYSTEM_BASE + 0x07C)
+/* DPORT_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_RTC_MEM_CRC_FINISH  (BIT(31))
+#define DPORT_RTC_MEM_CRC_FINISH_M  (BIT(31))
+#define DPORT_RTC_MEM_CRC_FINISH_V  0x1
+#define DPORT_RTC_MEM_CRC_FINISH_S  31
+/* DPORT_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */
+/*description: */
+#define DPORT_RTC_MEM_CRC_LEN  0x000007FF
+#define DPORT_RTC_MEM_CRC_LEN_M  ((DPORT_RTC_MEM_CRC_LEN_V)<<(DPORT_RTC_MEM_CRC_LEN_S))
+#define DPORT_RTC_MEM_CRC_LEN_V  0x7FF
+#define DPORT_RTC_MEM_CRC_LEN_S  20
+/* DPORT_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */
+/*description: */
+#define DPORT_RTC_MEM_CRC_ADDR  0x000007FF
+#define DPORT_RTC_MEM_CRC_ADDR_M  ((DPORT_RTC_MEM_CRC_ADDR_V)<<(DPORT_RTC_MEM_CRC_ADDR_S))
+#define DPORT_RTC_MEM_CRC_ADDR_V  0x7FF
+#define DPORT_RTC_MEM_CRC_ADDR_S  9
+/* DPORT_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_RTC_MEM_CRC_START  (BIT(8))
+#define DPORT_RTC_MEM_CRC_START_M  (BIT(8))
+#define DPORT_RTC_MEM_CRC_START_V  0x1
+#define DPORT_RTC_MEM_CRC_START_S  8
+
+#define DPORT_RTC_FASTMEM_CRC_REG          (DR_REG_SYSTEM_BASE + 0x080)
+/* DPORT_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define DPORT_RTC_MEM_CRC_RES  0xFFFFFFFF
+#define DPORT_RTC_MEM_CRC_RES_M  ((DPORT_RTC_MEM_CRC_RES_V)<<(DPORT_RTC_MEM_CRC_RES_S))
+#define DPORT_RTC_MEM_CRC_RES_V  0xFFFFFFFF
+#define DPORT_RTC_MEM_CRC_RES_S  0
+
+#define DPORT_REDUNDANT_ECO_CTRL_REG          (DR_REG_SYSTEM_BASE + 0x084)
+/* DPORT_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_REDUNDANT_ECO_RESULT  (BIT(1))
+#define DPORT_REDUNDANT_ECO_RESULT_M  (BIT(1))
+#define DPORT_REDUNDANT_ECO_RESULT_V  0x1
+#define DPORT_REDUNDANT_ECO_RESULT_S  1
+/* DPORT_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define DPORT_REDUNDANT_ECO_DRIVE  (BIT(0))
+#define DPORT_REDUNDANT_ECO_DRIVE_M  (BIT(0))
+#define DPORT_REDUNDANT_ECO_DRIVE_V  0x1
+#define DPORT_REDUNDANT_ECO_DRIVE_S  0
+
+#define SYSTEM_CLOCK_GATE_REG          (DR_REG_SYSTEM_BASE + 0x088)
+/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define SYSTEM_CLK_EN  (BIT(0))
+#define SYSTEM_CLK_EN_M  (BIT(0))
+#define SYSTEM_CLK_EN_V  0x1
+#define SYSTEM_CLK_EN_S  0
+
+#define SYSTEM_DATE_REG          (DR_REG_SYSTEM_BASE + 0xFFC)
+/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810300 ; */
+/*description: */
+#define SYSTEM_DATE  0x0FFFFFFF
+#define SYSTEM_DATE_M  ((SYSTEM_DATE_V)<<(SYSTEM_DATE_S))
+#define SYSTEM_DATE_V  0xFFFFFFF
+#define SYSTEM_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_SYSTEM_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/timer_group_reg.h b/components/soc/esp32s2beta/include/soc/timer_group_reg.h
new file mode 100644
index 000000000..7e4e437fd
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/timer_group_reg.h
@@ -0,0 +1,724 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_TIMG_REG_H_
+#define _SOC_TIMG_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+
+/* The value that needs to be written to TIMG_WDT_WKEY to write-enable the wdt registers */
+#define TIMG_WDT_WKEY_VALUE 0x50D83AA1
+
+/* Possible values for TIMG_WDT_STGx */
+#define TIMG_WDT_STG_SEL_OFF 0
+#define TIMG_WDT_STG_SEL_INT 1
+#define TIMG_WDT_STG_SEL_RESET_CPU 2
+#define TIMG_WDT_STG_SEL_RESET_SYSTEM 3
+
+#define TIMG_T0CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0000)
+/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_EN  (BIT(31))
+#define TIMG_T0_EN_M  (BIT(31))
+#define TIMG_T0_EN_V  0x1
+#define TIMG_T0_EN_S  31
+/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_T0_INCREASE  (BIT(30))
+#define TIMG_T0_INCREASE_M  (BIT(30))
+#define TIMG_T0_INCREASE_V  0x1
+#define TIMG_T0_INCREASE_S  30
+/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_T0_AUTORELOAD  (BIT(29))
+#define TIMG_T0_AUTORELOAD_M  (BIT(29))
+#define TIMG_T0_AUTORELOAD_V  0x1
+#define TIMG_T0_AUTORELOAD_S  29
+/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
+/*description: */
+#define TIMG_T0_DIVIDER  0x0000FFFF
+#define TIMG_T0_DIVIDER_M  ((TIMG_T0_DIVIDER_V)<<(TIMG_T0_DIVIDER_S))
+#define TIMG_T0_DIVIDER_V  0xFFFF
+#define TIMG_T0_DIVIDER_S  13
+/* TIMG_T0_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_EDGE_INT_EN  (BIT(12))
+#define TIMG_T0_EDGE_INT_EN_M  (BIT(12))
+#define TIMG_T0_EDGE_INT_EN_V  0x1
+#define TIMG_T0_EDGE_INT_EN_S  12
+/* TIMG_T0_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_LEVEL_INT_EN  (BIT(11))
+#define TIMG_T0_LEVEL_INT_EN_M  (BIT(11))
+#define TIMG_T0_LEVEL_INT_EN_V  0x1
+#define TIMG_T0_LEVEL_INT_EN_S  11
+/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_ALARM_EN  (BIT(10))
+#define TIMG_T0_ALARM_EN_M  (BIT(10))
+#define TIMG_T0_ALARM_EN_V  0x1
+#define TIMG_T0_ALARM_EN_S  10
+/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_T0_USE_XTAL  (BIT(9))
+#define TIMG_T0_USE_XTAL_M  (BIT(9))
+#define TIMG_T0_USE_XTAL_V  0x1
+#define TIMG_T0_USE_XTAL_S  9
+
+#define TIMG_T0LO_REG(i)          (REG_TIMG_BASE(i) + 0x0004)
+/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_LO  0xFFFFFFFF
+#define TIMG_T0_LO_M  ((TIMG_T0_LO_V)<<(TIMG_T0_LO_S))
+#define TIMG_T0_LO_V  0xFFFFFFFF
+#define TIMG_T0_LO_S  0
+
+#define TIMG_T0HI_REG(i)          (REG_TIMG_BASE(i) + 0x0008)
+/* TIMG_T0_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_HI  0xFFFFFFFF
+#define TIMG_T0_HI_M  ((TIMG_T0_HI_V)<<(TIMG_T0_HI_S))
+#define TIMG_T0_HI_V  0xFFFFFFFF
+#define TIMG_T0_HI_S  0
+
+#define TIMG_T0UPDATE_REG(i)          (REG_TIMG_BASE(i) + 0x000c)
+/* TIMG_T0_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_UPDATE  (BIT(31))
+#define TIMG_T0_UPDATE_M  (BIT(31))
+#define TIMG_T0_UPDATE_V  0x1
+#define TIMG_T0_UPDATE_S  31
+
+#define TIMG_T0ALARMLO_REG(i)          (REG_TIMG_BASE(i) + 0x0010)
+/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_ALARM_LO  0xFFFFFFFF
+#define TIMG_T0_ALARM_LO_M  ((TIMG_T0_ALARM_LO_V)<<(TIMG_T0_ALARM_LO_S))
+#define TIMG_T0_ALARM_LO_V  0xFFFFFFFF
+#define TIMG_T0_ALARM_LO_S  0
+
+#define TIMG_T0ALARMHI_REG(i)          (REG_TIMG_BASE(i) + 0x0014)
+/* TIMG_T0_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_ALARM_HI  0xFFFFFFFF
+#define TIMG_T0_ALARM_HI_M  ((TIMG_T0_ALARM_HI_V)<<(TIMG_T0_ALARM_HI_S))
+#define TIMG_T0_ALARM_HI_V  0xFFFFFFFF
+#define TIMG_T0_ALARM_HI_S  0
+
+#define TIMG_T0LOADLO_REG(i)          (REG_TIMG_BASE(i) + 0x0018)
+/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_LOAD_LO  0xFFFFFFFF
+#define TIMG_T0_LOAD_LO_M  ((TIMG_T0_LOAD_LO_V)<<(TIMG_T0_LOAD_LO_S))
+#define TIMG_T0_LOAD_LO_V  0xFFFFFFFF
+#define TIMG_T0_LOAD_LO_S  0
+
+#define TIMG_T0LOADHI_REG(i)          (REG_TIMG_BASE(i) + 0x001c)
+/* TIMG_T0_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_LOAD_HI  0xFFFFFFFF
+#define TIMG_T0_LOAD_HI_M  ((TIMG_T0_LOAD_HI_V)<<(TIMG_T0_LOAD_HI_S))
+#define TIMG_T0_LOAD_HI_V  0xFFFFFFFF
+#define TIMG_T0_LOAD_HI_S  0
+
+#define TIMG_T0LOAD_REG(i)          (REG_TIMG_BASE(i) + 0x0020)
+/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T0_LOAD  0xFFFFFFFF
+#define TIMG_T0_LOAD_M  ((TIMG_T0_LOAD_V)<<(TIMG_T0_LOAD_S))
+#define TIMG_T0_LOAD_V  0xFFFFFFFF
+#define TIMG_T0_LOAD_S  0
+
+#define TIMG_T1CONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0024)
+/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_EN  (BIT(31))
+#define TIMG_T1_EN_M  (BIT(31))
+#define TIMG_T1_EN_V  0x1
+#define TIMG_T1_EN_S  31
+/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_T1_INCREASE  (BIT(30))
+#define TIMG_T1_INCREASE_M  (BIT(30))
+#define TIMG_T1_INCREASE_V  0x1
+#define TIMG_T1_INCREASE_S  30
+/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_T1_AUTORELOAD  (BIT(29))
+#define TIMG_T1_AUTORELOAD_M  (BIT(29))
+#define TIMG_T1_AUTORELOAD_V  0x1
+#define TIMG_T1_AUTORELOAD_S  29
+/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
+/*description: */
+#define TIMG_T1_DIVIDER  0x0000FFFF
+#define TIMG_T1_DIVIDER_M  ((TIMG_T1_DIVIDER_V)<<(TIMG_T1_DIVIDER_S))
+#define TIMG_T1_DIVIDER_V  0xFFFF
+#define TIMG_T1_DIVIDER_S  13
+/* TIMG_T1_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_EDGE_INT_EN  (BIT(12))
+#define TIMG_T1_EDGE_INT_EN_M  (BIT(12))
+#define TIMG_T1_EDGE_INT_EN_V  0x1
+#define TIMG_T1_EDGE_INT_EN_S  12
+/* TIMG_T1_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_LEVEL_INT_EN  (BIT(11))
+#define TIMG_T1_LEVEL_INT_EN_M  (BIT(11))
+#define TIMG_T1_LEVEL_INT_EN_V  0x1
+#define TIMG_T1_LEVEL_INT_EN_S  11
+/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_ALARM_EN  (BIT(10))
+#define TIMG_T1_ALARM_EN_M  (BIT(10))
+#define TIMG_T1_ALARM_EN_V  0x1
+#define TIMG_T1_ALARM_EN_S  10
+/* TIMG_T1_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_T1_USE_XTAL  (BIT(9))
+#define TIMG_T1_USE_XTAL_M  (BIT(9))
+#define TIMG_T1_USE_XTAL_V  0x1
+#define TIMG_T1_USE_XTAL_S  9
+
+#define TIMG_T1LO_REG(i)          (REG_TIMG_BASE(i) + 0x0028)
+/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T1_LO  0xFFFFFFFF
+#define TIMG_T1_LO_M  ((TIMG_T1_LO_V)<<(TIMG_T1_LO_S))
+#define TIMG_T1_LO_V  0xFFFFFFFF
+#define TIMG_T1_LO_S  0
+
+#define TIMG_T1HI_REG(i)          (REG_TIMG_BASE(i) + 0x002c)
+/* TIMG_T1_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T1_HI  0xFFFFFFFF
+#define TIMG_T1_HI_M  ((TIMG_T1_HI_V)<<(TIMG_T1_HI_S))
+#define TIMG_T1_HI_V  0xFFFFFFFF
+#define TIMG_T1_HI_S  0
+
+#define TIMG_T1UPDATE_REG(i)          (REG_TIMG_BASE(i) + 0x0030)
+/* TIMG_T1_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_UPDATE  (BIT(31))
+#define TIMG_T1_UPDATE_M  (BIT(31))
+#define TIMG_T1_UPDATE_V  0x1
+#define TIMG_T1_UPDATE_S  31
+
+#define TIMG_T1ALARMLO_REG(i)          (REG_TIMG_BASE(i) + 0x0034)
+/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T1_ALARM_LO  0xFFFFFFFF
+#define TIMG_T1_ALARM_LO_M  ((TIMG_T1_ALARM_LO_V)<<(TIMG_T1_ALARM_LO_S))
+#define TIMG_T1_ALARM_LO_V  0xFFFFFFFF
+#define TIMG_T1_ALARM_LO_S  0
+
+#define TIMG_T1ALARMHI_REG(i)          (REG_TIMG_BASE(i) + 0x0038)
+/* TIMG_T1_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T1_ALARM_HI  0xFFFFFFFF
+#define TIMG_T1_ALARM_HI_M  ((TIMG_T1_ALARM_HI_V)<<(TIMG_T1_ALARM_HI_S))
+#define TIMG_T1_ALARM_HI_V  0xFFFFFFFF
+#define TIMG_T1_ALARM_HI_S  0
+
+#define TIMG_T1LOADLO_REG(i)          (REG_TIMG_BASE(i) + 0x003c)
+/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T1_LOAD_LO  0xFFFFFFFF
+#define TIMG_T1_LOAD_LO_M  ((TIMG_T1_LOAD_LO_V)<<(TIMG_T1_LOAD_LO_S))
+#define TIMG_T1_LOAD_LO_V  0xFFFFFFFF
+#define TIMG_T1_LOAD_LO_S  0
+
+#define TIMG_T1LOADHI_REG(i)          (REG_TIMG_BASE(i) + 0x0040)
+/* TIMG_T1_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T1_LOAD_HI  0xFFFFFFFF
+#define TIMG_T1_LOAD_HI_M  ((TIMG_T1_LOAD_HI_V)<<(TIMG_T1_LOAD_HI_S))
+#define TIMG_T1_LOAD_HI_V  0xFFFFFFFF
+#define TIMG_T1_LOAD_HI_S  0
+
+#define TIMG_T1LOAD_REG(i)          (REG_TIMG_BASE(i) + 0x0044)
+/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_T1_LOAD  0xFFFFFFFF
+#define TIMG_T1_LOAD_M  ((TIMG_T1_LOAD_V)<<(TIMG_T1_LOAD_S))
+#define TIMG_T1_LOAD_V  0xFFFFFFFF
+#define TIMG_T1_LOAD_S  0
+
+#define TIMG_WDTCONFIG0_REG(i)          (REG_TIMG_BASE(i) + 0x0048)
+/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_EN  (BIT(31))
+#define TIMG_WDT_EN_M  (BIT(31))
+#define TIMG_WDT_EN_V  0x1
+#define TIMG_WDT_EN_S  31
+/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_STG0  0x00000003
+#define TIMG_WDT_STG0_M  ((TIMG_WDT_STG0_V)<<(TIMG_WDT_STG0_S))
+#define TIMG_WDT_STG0_V  0x3
+#define TIMG_WDT_STG0_S  29
+/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_STG1  0x00000003
+#define TIMG_WDT_STG1_M  ((TIMG_WDT_STG1_V)<<(TIMG_WDT_STG1_S))
+#define TIMG_WDT_STG1_V  0x3
+#define TIMG_WDT_STG1_S  27
+/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_STG2  0x00000003
+#define TIMG_WDT_STG2_M  ((TIMG_WDT_STG2_V)<<(TIMG_WDT_STG2_S))
+#define TIMG_WDT_STG2_V  0x3
+#define TIMG_WDT_STG2_S  25
+/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_STG3  0x00000003
+#define TIMG_WDT_STG3_M  ((TIMG_WDT_STG3_V)<<(TIMG_WDT_STG3_S))
+#define TIMG_WDT_STG3_V  0x3
+#define TIMG_WDT_STG3_S  23
+/* TIMG_WDT_EDGE_INT_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_EDGE_INT_EN  (BIT(22))
+#define TIMG_WDT_EDGE_INT_EN_M  (BIT(22))
+#define TIMG_WDT_EDGE_INT_EN_V  0x1
+#define TIMG_WDT_EDGE_INT_EN_S  22
+/* TIMG_WDT_LEVEL_INT_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_LEVEL_INT_EN  (BIT(21))
+#define TIMG_WDT_LEVEL_INT_EN_M  (BIT(21))
+#define TIMG_WDT_LEVEL_INT_EN_V  0x1
+#define TIMG_WDT_LEVEL_INT_EN_S  21
+/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */
+/*description: */
+#define TIMG_WDT_CPU_RESET_LENGTH  0x00000007
+#define TIMG_WDT_CPU_RESET_LENGTH_M  ((TIMG_WDT_CPU_RESET_LENGTH_V)<<(TIMG_WDT_CPU_RESET_LENGTH_S))
+#define TIMG_WDT_CPU_RESET_LENGTH_V  0x7
+#define TIMG_WDT_CPU_RESET_LENGTH_S  18
+/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */
+/*description: */
+#define TIMG_WDT_SYS_RESET_LENGTH  0x00000007
+#define TIMG_WDT_SYS_RESET_LENGTH_M  ((TIMG_WDT_SYS_RESET_LENGTH_V)<<(TIMG_WDT_SYS_RESET_LENGTH_S))
+#define TIMG_WDT_SYS_RESET_LENGTH_V  0x7
+#define TIMG_WDT_SYS_RESET_LENGTH_S  15
+/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_WDT_FLASHBOOT_MOD_EN  (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_M  (BIT(14))
+#define TIMG_WDT_FLASHBOOT_MOD_EN_V  0x1
+#define TIMG_WDT_FLASHBOOT_MOD_EN_S  14
+/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_PROCPU_RESET_EN  (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_M  (BIT(13))
+#define TIMG_WDT_PROCPU_RESET_EN_V  0x1
+#define TIMG_WDT_PROCPU_RESET_EN_S  13
+/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_WDT_APPCPU_RESET_EN  (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_M  (BIT(12))
+#define TIMG_WDT_APPCPU_RESET_EN_V  0x1
+#define TIMG_WDT_APPCPU_RESET_EN_S  12
+
+#define TIMG_WDTCONFIG1_REG(i)          (REG_TIMG_BASE(i) + 0x004c)
+/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */
+/*description: */
+#define TIMG_WDT_CLK_PRESCALE  0x0000FFFF
+#define TIMG_WDT_CLK_PRESCALE_M  ((TIMG_WDT_CLK_PRESCALE_V)<<(TIMG_WDT_CLK_PRESCALE_S))
+#define TIMG_WDT_CLK_PRESCALE_V  0xFFFF
+#define TIMG_WDT_CLK_PRESCALE_S  16
+
+#define TIMG_WDTCONFIG2_REG(i)          (REG_TIMG_BASE(i) + 0x0050)
+/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */
+/*description: */
+#define TIMG_WDT_STG0_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG0_HOLD_M  ((TIMG_WDT_STG0_HOLD_V)<<(TIMG_WDT_STG0_HOLD_S))
+#define TIMG_WDT_STG0_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG0_HOLD_S  0
+
+#define TIMG_WDTCONFIG3_REG(i)          (REG_TIMG_BASE(i) + 0x0054)
+/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */
+/*description: */
+#define TIMG_WDT_STG1_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG1_HOLD_M  ((TIMG_WDT_STG1_HOLD_V)<<(TIMG_WDT_STG1_HOLD_S))
+#define TIMG_WDT_STG1_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG1_HOLD_S  0
+
+#define TIMG_WDTCONFIG4_REG(i)          (REG_TIMG_BASE(i) + 0x0058)
+/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
+/*description: */
+#define TIMG_WDT_STG2_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG2_HOLD_M  ((TIMG_WDT_STG2_HOLD_V)<<(TIMG_WDT_STG2_HOLD_S))
+#define TIMG_WDT_STG2_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG2_HOLD_S  0
+
+#define TIMG_WDTCONFIG5_REG(i)          (REG_TIMG_BASE(i) + 0x005c)
+/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */
+/*description: */
+#define TIMG_WDT_STG3_HOLD  0xFFFFFFFF
+#define TIMG_WDT_STG3_HOLD_M  ((TIMG_WDT_STG3_HOLD_V)<<(TIMG_WDT_STG3_HOLD_S))
+#define TIMG_WDT_STG3_HOLD_V  0xFFFFFFFF
+#define TIMG_WDT_STG3_HOLD_S  0
+
+#define TIMG_WDTFEED_REG(i)          (REG_TIMG_BASE(i) + 0x0060)
+/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_WDT_FEED  0xFFFFFFFF
+#define TIMG_WDT_FEED_M  ((TIMG_WDT_FEED_V)<<(TIMG_WDT_FEED_S))
+#define TIMG_WDT_FEED_V  0xFFFFFFFF
+#define TIMG_WDT_FEED_S  0
+
+#define TIMG_WDTWPROTECT_REG(i)          (REG_TIMG_BASE(i) + 0x0064)
+/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */
+/*description: */
+#define TIMG_WDT_WKEY  0xFFFFFFFF
+#define TIMG_WDT_WKEY_M  ((TIMG_WDT_WKEY_V)<<(TIMG_WDT_WKEY_S))
+#define TIMG_WDT_WKEY_V  0xFFFFFFFF
+#define TIMG_WDT_WKEY_S  0
+
+#define TIMG_RTCCALICFG_REG(i)          (REG_TIMG_BASE(i) + 0x0068)
+/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_START  (BIT(31))
+#define TIMG_RTC_CALI_START_M  (BIT(31))
+#define TIMG_RTC_CALI_START_V  0x1
+#define TIMG_RTC_CALI_START_S  31
+/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */
+/*description: */
+#define TIMG_RTC_CALI_MAX  0x00007FFF
+#define TIMG_RTC_CALI_MAX_M  ((TIMG_RTC_CALI_MAX_V)<<(TIMG_RTC_CALI_MAX_S))
+#define TIMG_RTC_CALI_MAX_V  0x7FFF
+#define TIMG_RTC_CALI_MAX_S  16
+/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_RDY  (BIT(15))
+#define TIMG_RTC_CALI_RDY_M  (BIT(15))
+#define TIMG_RTC_CALI_RDY_V  0x1
+#define TIMG_RTC_CALI_RDY_S  15
+/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */
+/*description: */
+#define TIMG_RTC_CALI_CLK_SEL  0x00000003
+#define TIMG_RTC_CALI_CLK_SEL_M  ((TIMG_RTC_CALI_CLK_SEL_V)<<(TIMG_RTC_CALI_CLK_SEL_S))
+#define TIMG_RTC_CALI_CLK_SEL_V  0x3
+#define TIMG_RTC_CALI_CLK_SEL_S  13
+/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */
+/*description: */
+#define TIMG_RTC_CALI_START_CYCLING  (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_M  (BIT(12))
+#define TIMG_RTC_CALI_START_CYCLING_V  0x1
+#define TIMG_RTC_CALI_START_CYCLING_S  12
+
+#define TIMG_RTCCALICFG1_REG(i)          (REG_TIMG_BASE(i) + 0x006c)
+/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */
+/*description: */
+#define TIMG_RTC_CALI_VALUE  0x01FFFFFF
+#define TIMG_RTC_CALI_VALUE_M  ((TIMG_RTC_CALI_VALUE_V)<<(TIMG_RTC_CALI_VALUE_S))
+#define TIMG_RTC_CALI_VALUE_V  0x1FFFFFF
+#define TIMG_RTC_CALI_VALUE_S  7
+/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD  (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M  (BIT(0))
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V  0x1
+#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S  0
+
+#define TIMG_LACTCONFIG_REG(i)          (REG_TIMG_BASE(i) + 0x0070)
+/* TIMG_LACT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_EN  (BIT(31))
+#define TIMG_LACT_EN_M  (BIT(31))
+#define TIMG_LACT_EN_V  0x1
+#define TIMG_LACT_EN_S  31
+/* TIMG_LACT_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_INCREASE  (BIT(30))
+#define TIMG_LACT_INCREASE_M  (BIT(30))
+#define TIMG_LACT_INCREASE_V  0x1
+#define TIMG_LACT_INCREASE_S  30
+/* TIMG_LACT_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_AUTORELOAD  (BIT(29))
+#define TIMG_LACT_AUTORELOAD_M  (BIT(29))
+#define TIMG_LACT_AUTORELOAD_V  0x1
+#define TIMG_LACT_AUTORELOAD_S  29
+/* TIMG_LACT_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */
+/*description: */
+#define TIMG_LACT_DIVIDER  0x0000FFFF
+#define TIMG_LACT_DIVIDER_M  ((TIMG_LACT_DIVIDER_V)<<(TIMG_LACT_DIVIDER_S))
+#define TIMG_LACT_DIVIDER_V  0xFFFF
+#define TIMG_LACT_DIVIDER_S  13
+/* TIMG_LACT_EDGE_INT_EN : R/W ;bitpos:[12] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_EDGE_INT_EN  (BIT(12))
+#define TIMG_LACT_EDGE_INT_EN_M  (BIT(12))
+#define TIMG_LACT_EDGE_INT_EN_V  0x1
+#define TIMG_LACT_EDGE_INT_EN_S  12
+/* TIMG_LACT_LEVEL_INT_EN : R/W ;bitpos:[11] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_LEVEL_INT_EN  (BIT(11))
+#define TIMG_LACT_LEVEL_INT_EN_M  (BIT(11))
+#define TIMG_LACT_LEVEL_INT_EN_V  0x1
+#define TIMG_LACT_LEVEL_INT_EN_S  11
+/* TIMG_LACT_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_ALARM_EN  (BIT(10))
+#define TIMG_LACT_ALARM_EN_M  (BIT(10))
+#define TIMG_LACT_ALARM_EN_V  0x1
+#define TIMG_LACT_ALARM_EN_S  10
+/* TIMG_LACT_LAC_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_LAC_EN  (BIT(9))
+#define TIMG_LACT_LAC_EN_M  (BIT(9))
+#define TIMG_LACT_LAC_EN_V  0x1
+#define TIMG_LACT_LAC_EN_S  9
+/* TIMG_LACT_CPST_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
+/*description: */
+#define TIMG_LACT_CPST_EN  (BIT(8))
+#define TIMG_LACT_CPST_EN_M  (BIT(8))
+#define TIMG_LACT_CPST_EN_V  0x1
+#define TIMG_LACT_CPST_EN_S  8
+/* TIMG_LACT_RTC_ONLY : R/W ;bitpos:[7] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_RTC_ONLY  (BIT(7))
+#define TIMG_LACT_RTC_ONLY_M  (BIT(7))
+#define TIMG_LACT_RTC_ONLY_V  0x1
+#define TIMG_LACT_RTC_ONLY_S  7
+/* TIMG_LACT_USE_REFTICK : R/W ;bitpos:[6] ;default: 1'd0 ; */
+/*description: */
+#define TIMG_LACT_USE_REFTICK  (BIT(6))
+#define TIMG_LACT_USE_REFTICK_M  (BIT(6))
+#define TIMG_LACT_USE_REFTICK_V  0x1
+#define TIMG_LACT_USE_REFTICK_S  6
+
+#define TIMG_LACTRTC_REG(i)          (REG_TIMG_BASE(i) + 0x0074)
+/* TIMG_LACT_RTC_STEP_LEN : R/W ;bitpos:[31:6] ;default: 26'h0 ; */
+/*description: */
+#define TIMG_LACT_RTC_STEP_LEN  0x03FFFFFF
+#define TIMG_LACT_RTC_STEP_LEN_M  ((TIMG_LACT_RTC_STEP_LEN_V)<<(TIMG_LACT_RTC_STEP_LEN_S))
+#define TIMG_LACT_RTC_STEP_LEN_V  0x3FFFFFF
+#define TIMG_LACT_RTC_STEP_LEN_S  6
+
+#define TIMG_LACTLO_REG(i)          (REG_TIMG_BASE(i) + 0x0078)
+/* TIMG_LACT_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LO  0xFFFFFFFF
+#define TIMG_LACT_LO_M  ((TIMG_LACT_LO_V)<<(TIMG_LACT_LO_S))
+#define TIMG_LACT_LO_V  0xFFFFFFFF
+#define TIMG_LACT_LO_S  0
+
+#define TIMG_LACTHI_REG(i)          (REG_TIMG_BASE(i) + 0x007c)
+/* TIMG_LACT_HI : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_HI  0xFFFFFFFF
+#define TIMG_LACT_HI_M  ((TIMG_LACT_HI_V)<<(TIMG_LACT_HI_S))
+#define TIMG_LACT_HI_V  0xFFFFFFFF
+#define TIMG_LACT_HI_S  0
+
+#define TIMG_LACTUPDATE_REG(i)          (REG_TIMG_BASE(i) + 0x0080)
+/* TIMG_LACT_UPDATE : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_UPDATE  0xFFFFFFFF
+#define TIMG_LACT_UPDATE_M  ((TIMG_LACT_UPDATE_V)<<(TIMG_LACT_UPDATE_S))
+#define TIMG_LACT_UPDATE_V  0xFFFFFFFF
+#define TIMG_LACT_UPDATE_S  0
+
+#define TIMG_LACTALARMLO_REG(i)          (REG_TIMG_BASE(i) + 0x0084)
+/* TIMG_LACT_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_ALARM_LO  0xFFFFFFFF
+#define TIMG_LACT_ALARM_LO_M  ((TIMG_LACT_ALARM_LO_V)<<(TIMG_LACT_ALARM_LO_S))
+#define TIMG_LACT_ALARM_LO_V  0xFFFFFFFF
+#define TIMG_LACT_ALARM_LO_S  0
+
+#define TIMG_LACTALARMHI_REG(i)          (REG_TIMG_BASE(i) + 0x0088)
+/* TIMG_LACT_ALARM_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_ALARM_HI  0xFFFFFFFF
+#define TIMG_LACT_ALARM_HI_M  ((TIMG_LACT_ALARM_HI_V)<<(TIMG_LACT_ALARM_HI_S))
+#define TIMG_LACT_ALARM_HI_V  0xFFFFFFFF
+#define TIMG_LACT_ALARM_HI_S  0
+
+#define TIMG_LACTLOADLO_REG(i)          (REG_TIMG_BASE(i) + 0x008c)
+/* TIMG_LACT_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LOAD_LO  0xFFFFFFFF
+#define TIMG_LACT_LOAD_LO_M  ((TIMG_LACT_LOAD_LO_V)<<(TIMG_LACT_LOAD_LO_S))
+#define TIMG_LACT_LOAD_LO_V  0xFFFFFFFF
+#define TIMG_LACT_LOAD_LO_S  0
+
+#define TIMG_LACTLOADHI_REG(i)          (REG_TIMG_BASE(i) + 0x0090)
+/* TIMG_LACT_LOAD_HI : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LOAD_HI  0xFFFFFFFF
+#define TIMG_LACT_LOAD_HI_M  ((TIMG_LACT_LOAD_HI_V)<<(TIMG_LACT_LOAD_HI_S))
+#define TIMG_LACT_LOAD_HI_V  0xFFFFFFFF
+#define TIMG_LACT_LOAD_HI_S  0
+
+#define TIMG_LACTLOAD_REG(i)          (REG_TIMG_BASE(i) + 0x0094)
+/* TIMG_LACT_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define TIMG_LACT_LOAD  0xFFFFFFFF
+#define TIMG_LACT_LOAD_M  ((TIMG_LACT_LOAD_V)<<(TIMG_LACT_LOAD_S))
+#define TIMG_LACT_LOAD_V  0xFFFFFFFF
+#define TIMG_LACT_LOAD_S  0
+
+#define TIMG_INT_ENA_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x0098)
+/* TIMG_LACT_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_ENA  (BIT(3))
+#define TIMG_LACT_INT_ENA_M  (BIT(3))
+#define TIMG_LACT_INT_ENA_V  0x1
+#define TIMG_LACT_INT_ENA_S  3
+/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_ENA  (BIT(2))
+#define TIMG_WDT_INT_ENA_M  (BIT(2))
+#define TIMG_WDT_INT_ENA_V  0x1
+#define TIMG_WDT_INT_ENA_S  2
+/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_INT_ENA  (BIT(1))
+#define TIMG_T1_INT_ENA_M  (BIT(1))
+#define TIMG_T1_INT_ENA_V  0x1
+#define TIMG_T1_INT_ENA_S  1
+/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_ENA  (BIT(0))
+#define TIMG_T0_INT_ENA_M  (BIT(0))
+#define TIMG_T0_INT_ENA_V  0x1
+#define TIMG_T0_INT_ENA_S  0
+
+#define TIMG_INT_RAW_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x009c)
+/* TIMG_LACT_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_RAW  (BIT(3))
+#define TIMG_LACT_INT_RAW_M  (BIT(3))
+#define TIMG_LACT_INT_RAW_V  0x1
+#define TIMG_LACT_INT_RAW_S  3
+/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_RAW  (BIT(2))
+#define TIMG_WDT_INT_RAW_M  (BIT(2))
+#define TIMG_WDT_INT_RAW_V  0x1
+#define TIMG_WDT_INT_RAW_S  2
+/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_INT_RAW  (BIT(1))
+#define TIMG_T1_INT_RAW_M  (BIT(1))
+#define TIMG_T1_INT_RAW_V  0x1
+#define TIMG_T1_INT_RAW_S  1
+/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_RAW  (BIT(0))
+#define TIMG_T0_INT_RAW_M  (BIT(0))
+#define TIMG_T0_INT_RAW_V  0x1
+#define TIMG_T0_INT_RAW_S  0
+
+#define TIMG_INT_ST_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x00a0)
+/* TIMG_LACT_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_ST  (BIT(3))
+#define TIMG_LACT_INT_ST_M  (BIT(3))
+#define TIMG_LACT_INT_ST_V  0x1
+#define TIMG_LACT_INT_ST_S  3
+/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_ST  (BIT(2))
+#define TIMG_WDT_INT_ST_M  (BIT(2))
+#define TIMG_WDT_INT_ST_V  0x1
+#define TIMG_WDT_INT_ST_S  2
+/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_INT_ST  (BIT(1))
+#define TIMG_T1_INT_ST_M  (BIT(1))
+#define TIMG_T1_INT_ST_V  0x1
+#define TIMG_T1_INT_ST_S  1
+/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_ST  (BIT(0))
+#define TIMG_T0_INT_ST_M  (BIT(0))
+#define TIMG_T0_INT_ST_V  0x1
+#define TIMG_T0_INT_ST_S  0
+
+#define TIMG_INT_CLR_TIMERS_REG(i)          (REG_TIMG_BASE(i) + 0x00a4)
+/* TIMG_LACT_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_LACT_INT_CLR  (BIT(3))
+#define TIMG_LACT_INT_CLR_M  (BIT(3))
+#define TIMG_LACT_INT_CLR_V  0x1
+#define TIMG_LACT_INT_CLR_S  3
+/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_WDT_INT_CLR  (BIT(2))
+#define TIMG_WDT_INT_CLR_M  (BIT(2))
+#define TIMG_WDT_INT_CLR_V  0x1
+#define TIMG_WDT_INT_CLR_S  2
+/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T1_INT_CLR  (BIT(1))
+#define TIMG_T1_INT_CLR_M  (BIT(1))
+#define TIMG_T1_INT_CLR_V  0x1
+#define TIMG_T1_INT_CLR_S  1
+/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_T0_INT_CLR  (BIT(0))
+#define TIMG_T0_INT_CLR_M  (BIT(0))
+#define TIMG_T0_INT_CLR_V  0x1
+#define TIMG_T0_INT_CLR_S  0
+
+#define TIMG_RTCCALICFG2_REG(i)          (REG_TIMG_BASE(i) + 0x00a8)
+/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */
+/*description: timeout if cali value counts over threshold*/
+#define TIMG_RTC_CALI_TIMEOUT_THRES  0x01FFFFFF
+#define TIMG_RTC_CALI_TIMEOUT_THRES_M  ((TIMG_RTC_CALI_TIMEOUT_THRES_V)<<(TIMG_RTC_CALI_TIMEOUT_THRES_S))
+#define TIMG_RTC_CALI_TIMEOUT_THRES_V  0x1FFFFFF
+#define TIMG_RTC_CALI_TIMEOUT_THRES_S  7
+/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */
+/*description: Cycles that release calibration timeout reset*/
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT  0x0000000F
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M  ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V)<<(TIMG_RTC_CALI_TIMEOUT_RST_CNT_S))
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V  0xF
+#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S  3
+/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */
+/*description: timeout indicator*/
+#define TIMG_RTC_CALI_TIMEOUT  (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_M  (BIT(0))
+#define TIMG_RTC_CALI_TIMEOUT_V  0x1
+#define TIMG_RTC_CALI_TIMEOUT_S  0
+
+#define TIMG_NTIMERS_DATE_REG(i)          (REG_TIMG_BASE(i) + 0x00f8)
+/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h1810190 ; */
+/*description: */
+#define TIMG_NTIMERS_DATE  0x0FFFFFFF
+#define TIMG_NTIMERS_DATE_M  ((TIMG_NTIMERS_DATE_V)<<(TIMG_NTIMERS_DATE_S))
+#define TIMG_NTIMERS_DATE_V  0xFFFFFFF
+#define TIMG_NTIMERS_DATE_S  0
+
+#define TIMG_CLK_REG(i)          (REG_TIMG_BASE(i) + 0x00fc)
+/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define TIMG_CLK_EN  (BIT(31))
+#define TIMG_CLK_EN_M  (BIT(31))
+#define TIMG_CLK_EN_V  0x1
+#define TIMG_CLK_EN_S  31
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_TIMG_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/timer_group_struct.h b/components/soc/esp32s2beta/include/soc/timer_group_struct.h
new file mode 100644
index 000000000..ab4cb84f9
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/timer_group_struct.h
@@ -0,0 +1,221 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_TIMG_STRUCT_H_
+#define _SOC_TIMG_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    struct {
+        union {
+            struct {
+                uint32_t reserved0:       9;
+                uint32_t use_xtal:        1;
+                uint32_t alarm_en:        1;
+                uint32_t level_int_en:    1;
+                uint32_t edge_int_en:     1;
+                uint32_t divider:        16;
+                uint32_t autoreload:      1;
+                uint32_t increase:        1;
+                uint32_t enable:          1;
+            };
+            uint32_t val;
+        } config;
+        uint32_t cnt_low;                                      /**/
+        uint32_t cnt_high;                                      /**/
+        union {
+            struct {
+                uint32_t reserved0: 31;
+                uint32_t update:     1;
+            };
+            uint32_t val;
+        } update;
+        uint32_t alarm_low;                                 /**/
+        uint32_t alarm_high;                                 /**/
+        uint32_t load_low;                                  /**/
+        uint32_t load_high;                                  /**/
+        uint32_t reload;                                    /**/
+    } hw_timer[2];
+    union {
+        struct {
+            uint32_t reserved0:           12;
+            uint32_t appcpu_reset_en:      1;
+            uint32_t procpu_reset_en:      1;
+            uint32_t flashboot_mod_en:     1;
+            uint32_t sys_reset_length:     3;
+            uint32_t cpu_reset_length:     3;
+            uint32_t level_int_en:         1;
+            uint32_t edge_int_en:          1;
+            uint32_t stg3:                 2;
+            uint32_t stg2:                 2;
+            uint32_t stg1:                 2;
+            uint32_t stg0:                 2;
+            uint32_t en:                   1;
+        };
+        uint32_t val;
+    } wdt_config0;
+    union {
+        struct {
+            uint32_t reserved0:       16;
+            uint32_t clk_prescale:    16;
+        };
+        uint32_t val;
+    } wdt_config1;
+    uint32_t wdt_config2;                                /**/
+    uint32_t wdt_config3;                                /**/
+    uint32_t wdt_config4;                                /**/
+    uint32_t wdt_config5;                                /**/
+    uint32_t wdt_feed;                                   /**/
+    uint32_t wdt_wprotect;                               /**/
+    union {
+        struct {
+            uint32_t reserved0:             12;
+            uint32_t start_cycling:          1;
+            uint32_t clk_sel:                2;
+            uint32_t rdy:                    1;
+            uint32_t max:                   15;
+            uint32_t start:                  1;
+        };
+        uint32_t val;
+    } rtc_cali_cfg;
+    union {
+        struct {
+            uint32_t reserved0:      7;
+            uint32_t value:         25;
+        };
+        uint32_t val;
+    } rtc_cali_cfg1;
+    union {
+        struct {
+            uint32_t reserved0:         6;
+            uint32_t use_reftick:       1;
+            uint32_t rtc_only:          1;
+            uint32_t cpst_en:           1;
+            uint32_t lac_en:            1;
+            uint32_t alarm_en:          1;
+            uint32_t level_int_en:      1;
+            uint32_t edge_int_en:       1;
+            uint32_t divider:          16;
+            uint32_t autoreload:        1;
+            uint32_t increase:          1;
+            uint32_t en:                1;
+        };
+        uint32_t val;
+    } lactconfig;
+    union {
+        struct {
+            uint32_t reserved0:         6;
+            uint32_t step_len:         26;
+        };
+        uint32_t val;
+    } lactrtc;
+    uint32_t lactlo;                                    /**/
+    uint32_t lacthi;                                    /**/
+    uint32_t lactupdate;                                /**/
+    uint32_t lactalarmlo;                               /**/
+    uint32_t lactalarmhi;                               /**/
+    uint32_t lactloadlo;                                /**/
+    uint32_t lactloadhi;                                /**/
+    uint32_t lactload;                                  /**/
+    union {
+        struct {
+            uint32_t t0:           1;
+            uint32_t t1:           1;
+            uint32_t wdt:          1;
+            uint32_t lact:         1;
+            uint32_t reserved4:   28;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t t0:           1;
+            uint32_t t1:           1;
+            uint32_t wdt:          1;
+            uint32_t lact:         1;
+            uint32_t reserved4:   28;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t t0:          1;
+            uint32_t t1:          1;
+            uint32_t wdt:         1;
+            uint32_t lact:        1;
+            uint32_t reserved4:  28;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t t0:           1;
+            uint32_t t1:           1;
+            uint32_t wdt:          1;
+            uint32_t lact:         1;
+            uint32_t reserved4:   28;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t timeout:                  1;       /*timeout indicator*/
+            uint32_t reserved1:                2;
+            uint32_t timeout_rst_cnt:          4;       /*Cycles that release calibration timeout reset*/
+            uint32_t timeout_thres:           25;       /*timeout if cali value counts over threshold*/
+        };
+        uint32_t val;
+    } rtc_cali_cfg2;
+    uint32_t reserved_ac;
+    uint32_t reserved_b0;
+    uint32_t reserved_b4;
+    uint32_t reserved_b8;
+    uint32_t reserved_bc;
+    uint32_t reserved_c0;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    union {
+        struct {
+            uint32_t date:        28;
+            uint32_t reserved28:   4;
+        };
+        uint32_t val;
+    } timg_date;
+    union {
+        struct {
+            uint32_t reserved0: 31;
+            uint32_t en:         1;
+        };
+        uint32_t val;
+    } clk;
+} timg_dev_t;
+extern timg_dev_t TIMERG0;
+extern timg_dev_t TIMERG1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_TIMG_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/touch_channel.h b/components/soc/esp32s2beta/include/soc/touch_channel.h
new file mode 100644
index 000000000..a9aa838b4
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/touch_channel.h
@@ -0,0 +1,49 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_TOUCH_CHANNEL_H
+#define _SOC_TOUCH_CHANNEL_H
+
+//Touch channels
+#define TOUCH_PAD_GPIO4_CHANNEL     TOUCH_PAD_NUM0
+#define TOUCH_PAD_NUM0_GPIO_NUM     4
+
+#define TOUCH_PAD_GPIO0_CHANNEL     TOUCH_PAD_NUM1
+#define TOUCH_PAD_NUM1_GPIO_NUM     0
+
+#define TOUCH_PAD_GPIO2_CHANNEL     TOUCH_PAD_NUM2
+#define TOUCH_PAD_NUM2_GPIO_NUM     2
+
+#define TOUCH_PAD_GPIO15_CHANNEL    TOUCH_PAD_NUM3
+#define TOUCH_PAD_NUM3_GPIO_NUM     15
+
+#define TOUCH_PAD_GPIO13_CHANNEL    TOUCH_PAD_NUM4
+#define TOUCH_PAD_NUM4_GPIO_NUM     13
+
+#define TOUCH_PAD_GPIO12_CHANNEL    TOUCH_PAD_NUM5
+#define TOUCH_PAD_NUM5_GPIO_NUM     12
+
+#define TOUCH_PAD_GPIO14_CHANNEL    TOUCH_PAD_NUM6
+#define TOUCH_PAD_NUM6_GPIO_NUM     14
+
+#define TOUCH_PAD_GPIO27_CHANNEL    TOUCH_PAD_NUM7
+#define TOUCH_PAD_NUM7_GPIO_NUM     27
+
+#define TOUCH_PAD_GPIO33_CHANNEL    TOUCH_PAD_NUM8
+#define TOUCH_PAD_NUM8_GPIO_NUM     33
+
+#define TOUCH_PAD_GPIO32_CHANNEL    TOUCH_PAD_NUM9
+#define TOUCH_PAD_NUM9_GPIO_NUM     32
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/uart_channel.h b/components/soc/esp32s2beta/include/soc/uart_channel.h
new file mode 100644
index 000000000..5b8dc56d5
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/uart_channel.h
@@ -0,0 +1,61 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#ifndef _SOC_UART_CHANNEL_H
+#define _SOC_UART_CHANNEL_H
+
+//UART channels
+#define UART_GPIO1_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_TXD_DIRECT_GPIO_NUM  1
+#define UART_GPIO3_DIRECT_CHANNEL       UART_NUM_0
+#define UART_NUM_0_RXD_DIRECT_GPIO_NUM  3
+#define UART_GPIO19_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_CTS_DIRECT_GPIO_NUM  19
+#define UART_GPIO22_DIRECT_CHANNEL      UART_NUM_0
+#define UART_NUM_0_RTS_DIRECT_GPIO_NUM  22
+
+#define UART_TXD_GPIO1_DIRECT_CHANNEL   UART_GPIO1_DIRECT_CHANNEL
+#define UART_RXD_GPIO3_DIRECT_CHANNEL   UART_GPIO3_DIRECT_CHANNEL
+#define UART_CTS_GPIO19_DIRECT_CHANNEL  UART_GPIO19_DIRECT_CHANNEL
+#define UART_RTS_GPIO22_DIRECT_CHANNEL  UART_GPIO22_DIRECT_CHANNEL
+
+#define UART_GPIO10_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_TXD_DIRECT_GPIO_NUM  10
+#define UART_GPIO9_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_RXD_DIRECT_GPIO_NUM  9
+#define UART_GPIO6_DIRECT_CHANNEL       UART_NUM_1
+#define UART_NUM_1_CTS_DIRECT_GPIO_NUM  6
+#define UART_GPIO11_DIRECT_CHANNEL      UART_NUM_1
+#define UART_NUM_1_RTS_DIRECT_GPIO_NUM  11
+
+#define UART_TXD_GPIO10_DIRECT_CHANNEL  UART_GPIO10_DIRECT_CHANNEL
+#define UART_RXD_GPIO9_DIRECT_CHANNEL   UART_GPIO9_DIRECT_CHANNEL
+#define UART_CTS_GPIO6_DIRECT_CHANNEL   UART_GPIO6_DIRECT_CHANNEL
+#define UART_RTS_GPIO11_DIRECT_CHANNEL  UART_GPIO11_DIRECT_CHANNEL
+
+#define UART_GPIO17_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_TXD_DIRECT_GPIO_NUM  17
+#define UART_GPIO16_DIRECT_CHANNEL      UART_NUM_2
+#define UART_NUM_2_RXD_DIRECT_GPIO_NUM  16
+#define UART_GPIO8_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_CTS_DIRECT_GPIO_NUM  8
+#define UART_GPIO7_DIRECT_CHANNEL       UART_NUM_2
+#define UART_NUM_2_RTS_DIRECT_GPIO_NUM  7
+
+#define UART_TXD_GPIO17_DIRECT_CHANNEL  UART_GPIO17_DIRECT_CHANNEL
+#define UART_RXD_GPIO16_DIRECT_CHANNEL  UART_GPIO16_DIRECT_CHANNEL
+#define UART_CTS_GPIO8_DIRECT_CHANNEL   UART_GPIO8_DIRECT_CHANNEL
+#define UART_RTS_GPIO7_DIRECT_CHANNEL   UART_GPIO7_DIRECT_CHANNEL
+
+#endif
diff --git a/components/soc/esp32s2beta/include/soc/uart_reg.h b/components/soc/esp32s2beta/include/soc/uart_reg.h
new file mode 100644
index 000000000..ee6ffdd42
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/uart_reg.h
@@ -0,0 +1,1100 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UART_REG_H_
+#define _SOC_UART_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define UART_FIFO_REG(i)          (REG_UART_BASE(i) + 0x0)
+/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */
+/*description: */
+#define UART_RXFIFO_RD_BYTE  0x000000FF
+#define UART_RXFIFO_RD_BYTE_M  ((UART_RXFIFO_RD_BYTE_V)<<(UART_RXFIFO_RD_BYTE_S))
+#define UART_RXFIFO_RD_BYTE_V  0xFF
+#define UART_RXFIFO_RD_BYTE_S  0
+
+#define UART_INT_RAW_REG(i)          (REG_UART_BASE(i) + 0x4)
+/* UART_WAKEUP_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define UART_WAKEUP_INT_RAW  (BIT(19))
+#define UART_WAKEUP_INT_RAW_M  (BIT(19))
+#define UART_WAKEUP_INT_RAW_V  0x1
+#define UART_WAKEUP_INT_RAW_S  19
+/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define UART_AT_CMD_CHAR_DET_INT_RAW  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_RAW_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_RAW_S  18
+/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_CLASH_INT_RAW  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_M  (BIT(17))
+#define UART_RS485_CLASH_INT_RAW_V  0x1
+#define UART_RS485_CLASH_INT_RAW_S  17
+/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_FRM_ERR_INT_RAW  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_RAW_V  0x1
+#define UART_RS485_FRM_ERR_INT_RAW_S  16
+/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_PARITY_ERR_INT_RAW  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_RAW_V  0x1
+#define UART_RS485_PARITY_ERR_INT_RAW_S  15
+/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_DONE_INT_RAW  (BIT(14))
+#define UART_TX_DONE_INT_RAW_M  (BIT(14))
+#define UART_TX_DONE_INT_RAW_V  0x1
+#define UART_TX_DONE_INT_RAW_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_IDLE_DONE_INT_RAW  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_RAW_S  13
+/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_DONE_INT_RAW  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_RAW_V  0x1
+#define UART_TX_BRK_DONE_INT_RAW_S  12
+/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UART_GLITCH_DET_INT_RAW  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_M  (BIT(11))
+#define UART_GLITCH_DET_INT_RAW_V  0x1
+#define UART_GLITCH_DET_INT_RAW_S  11
+/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XOFF_INT_RAW  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_M  (BIT(10))
+#define UART_SW_XOFF_INT_RAW_V  0x1
+#define UART_SW_XOFF_INT_RAW_S  10
+/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XON_INT_RAW  (BIT(9))
+#define UART_SW_XON_INT_RAW_M  (BIT(9))
+#define UART_SW_XON_INT_RAW_V  0x1
+#define UART_SW_XON_INT_RAW_S  9
+/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_TOUT_INT_RAW  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_RAW_V  0x1
+#define UART_RXFIFO_TOUT_INT_RAW_S  8
+/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UART_BRK_DET_INT_RAW  (BIT(7))
+#define UART_BRK_DET_INT_RAW_M  (BIT(7))
+#define UART_BRK_DET_INT_RAW_V  0x1
+#define UART_BRK_DET_INT_RAW_S  7
+/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UART_CTS_CHG_INT_RAW  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_M  (BIT(6))
+#define UART_CTS_CHG_INT_RAW_V  0x1
+#define UART_CTS_CHG_INT_RAW_S  6
+/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UART_DSR_CHG_INT_RAW  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_M  (BIT(5))
+#define UART_DSR_CHG_INT_RAW_V  0x1
+#define UART_DSR_CHG_INT_RAW_S  5
+/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_OVF_INT_RAW  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_RAW_V  0x1
+#define UART_RXFIFO_OVF_INT_RAW_S  4
+/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UART_FRM_ERR_INT_RAW  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_M  (BIT(3))
+#define UART_FRM_ERR_INT_RAW_V  0x1
+#define UART_FRM_ERR_INT_RAW_S  3
+/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UART_PARITY_ERR_INT_RAW  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_M  (BIT(2))
+#define UART_PARITY_ERR_INT_RAW_V  0x1
+#define UART_PARITY_ERR_INT_RAW_S  2
+/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UART_TXFIFO_EMPTY_INT_RAW  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_RAW_V  0x1
+#define UART_TXFIFO_EMPTY_INT_RAW_S  1
+/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_FULL_INT_RAW  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_RAW_V  0x1
+#define UART_RXFIFO_FULL_INT_RAW_S  0
+
+#define UART_INT_ST_REG(i)          (REG_UART_BASE(i) + 0x8)
+/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define UART_WAKEUP_INT_ST  (BIT(19))
+#define UART_WAKEUP_INT_ST_M  (BIT(19))
+#define UART_WAKEUP_INT_ST_V  0x1
+#define UART_WAKEUP_INT_ST_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define UART_AT_CMD_CHAR_DET_INT_ST  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ST_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ST_S  18
+/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_CLASH_INT_ST  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ST_V  0x1
+#define UART_RS485_CLASH_INT_ST_S  17
+/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_FRM_ERR_INT_ST  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ST_V  0x1
+#define UART_RS485_FRM_ERR_INT_ST_S  16
+/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_PARITY_ERR_INT_ST  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ST_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ST_S  15
+/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_DONE_INT_ST  (BIT(14))
+#define UART_TX_DONE_INT_ST_M  (BIT(14))
+#define UART_TX_DONE_INT_ST_V  0x1
+#define UART_TX_DONE_INT_ST_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_IDLE_DONE_INT_ST  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ST_S  13
+/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_DONE_INT_ST  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ST_V  0x1
+#define UART_TX_BRK_DONE_INT_ST_S  12
+/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UART_GLITCH_DET_INT_ST  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ST_V  0x1
+#define UART_GLITCH_DET_INT_ST_S  11
+/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XOFF_INT_ST  (BIT(10))
+#define UART_SW_XOFF_INT_ST_M  (BIT(10))
+#define UART_SW_XOFF_INT_ST_V  0x1
+#define UART_SW_XOFF_INT_ST_S  10
+/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XON_INT_ST  (BIT(9))
+#define UART_SW_XON_INT_ST_M  (BIT(9))
+#define UART_SW_XON_INT_ST_V  0x1
+#define UART_SW_XON_INT_ST_S  9
+/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_TOUT_INT_ST  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ST_V  0x1
+#define UART_RXFIFO_TOUT_INT_ST_S  8
+/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UART_BRK_DET_INT_ST  (BIT(7))
+#define UART_BRK_DET_INT_ST_M  (BIT(7))
+#define UART_BRK_DET_INT_ST_V  0x1
+#define UART_BRK_DET_INT_ST_S  7
+/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UART_CTS_CHG_INT_ST  (BIT(6))
+#define UART_CTS_CHG_INT_ST_M  (BIT(6))
+#define UART_CTS_CHG_INT_ST_V  0x1
+#define UART_CTS_CHG_INT_ST_S  6
+/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UART_DSR_CHG_INT_ST  (BIT(5))
+#define UART_DSR_CHG_INT_ST_M  (BIT(5))
+#define UART_DSR_CHG_INT_ST_V  0x1
+#define UART_DSR_CHG_INT_ST_S  5
+/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_OVF_INT_ST  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ST_V  0x1
+#define UART_RXFIFO_OVF_INT_ST_S  4
+/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UART_FRM_ERR_INT_ST  (BIT(3))
+#define UART_FRM_ERR_INT_ST_M  (BIT(3))
+#define UART_FRM_ERR_INT_ST_V  0x1
+#define UART_FRM_ERR_INT_ST_S  3
+/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UART_PARITY_ERR_INT_ST  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ST_V  0x1
+#define UART_PARITY_ERR_INT_ST_S  2
+/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UART_TXFIFO_EMPTY_INT_ST  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ST_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ST_S  1
+/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_FULL_INT_ST  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ST_V  0x1
+#define UART_RXFIFO_FULL_INT_ST_S  0
+
+#define UART_INT_ENA_REG(i)          (REG_UART_BASE(i) + 0xC)
+/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define UART_WAKEUP_INT_ENA  (BIT(19))
+#define UART_WAKEUP_INT_ENA_M  (BIT(19))
+#define UART_WAKEUP_INT_ENA_V  0x1
+#define UART_WAKEUP_INT_ENA_S  19
+/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define UART_AT_CMD_CHAR_DET_INT_ENA  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_ENA_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_ENA_S  18
+/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_CLASH_INT_ENA  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_M  (BIT(17))
+#define UART_RS485_CLASH_INT_ENA_V  0x1
+#define UART_RS485_CLASH_INT_ENA_S  17
+/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_FRM_ERR_INT_ENA  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_ENA_V  0x1
+#define UART_RS485_FRM_ERR_INT_ENA_S  16
+/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_PARITY_ERR_INT_ENA  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_ENA_V  0x1
+#define UART_RS485_PARITY_ERR_INT_ENA_S  15
+/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_DONE_INT_ENA  (BIT(14))
+#define UART_TX_DONE_INT_ENA_M  (BIT(14))
+#define UART_TX_DONE_INT_ENA_V  0x1
+#define UART_TX_DONE_INT_ENA_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_IDLE_DONE_INT_ENA  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_ENA_S  13
+/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_DONE_INT_ENA  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_ENA_V  0x1
+#define UART_TX_BRK_DONE_INT_ENA_S  12
+/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UART_GLITCH_DET_INT_ENA  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_M  (BIT(11))
+#define UART_GLITCH_DET_INT_ENA_V  0x1
+#define UART_GLITCH_DET_INT_ENA_S  11
+/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XOFF_INT_ENA  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_M  (BIT(10))
+#define UART_SW_XOFF_INT_ENA_V  0x1
+#define UART_SW_XOFF_INT_ENA_S  10
+/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XON_INT_ENA  (BIT(9))
+#define UART_SW_XON_INT_ENA_M  (BIT(9))
+#define UART_SW_XON_INT_ENA_V  0x1
+#define UART_SW_XON_INT_ENA_S  9
+/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_TOUT_INT_ENA  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_ENA_V  0x1
+#define UART_RXFIFO_TOUT_INT_ENA_S  8
+/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UART_BRK_DET_INT_ENA  (BIT(7))
+#define UART_BRK_DET_INT_ENA_M  (BIT(7))
+#define UART_BRK_DET_INT_ENA_V  0x1
+#define UART_BRK_DET_INT_ENA_S  7
+/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UART_CTS_CHG_INT_ENA  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_M  (BIT(6))
+#define UART_CTS_CHG_INT_ENA_V  0x1
+#define UART_CTS_CHG_INT_ENA_S  6
+/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UART_DSR_CHG_INT_ENA  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_M  (BIT(5))
+#define UART_DSR_CHG_INT_ENA_V  0x1
+#define UART_DSR_CHG_INT_ENA_S  5
+/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_OVF_INT_ENA  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_ENA_V  0x1
+#define UART_RXFIFO_OVF_INT_ENA_S  4
+/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UART_FRM_ERR_INT_ENA  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_M  (BIT(3))
+#define UART_FRM_ERR_INT_ENA_V  0x1
+#define UART_FRM_ERR_INT_ENA_S  3
+/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UART_PARITY_ERR_INT_ENA  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_M  (BIT(2))
+#define UART_PARITY_ERR_INT_ENA_V  0x1
+#define UART_PARITY_ERR_INT_ENA_S  2
+/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UART_TXFIFO_EMPTY_INT_ENA  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_ENA_V  0x1
+#define UART_TXFIFO_EMPTY_INT_ENA_S  1
+/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_FULL_INT_ENA  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_ENA_V  0x1
+#define UART_RXFIFO_FULL_INT_ENA_S  0
+
+#define UART_INT_CLR_REG(i)          (REG_UART_BASE(i) + 0x10)
+/* UART_WAKEUP_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define UART_WAKEUP_INT_CLR  (BIT(19))
+#define UART_WAKEUP_INT_CLR_M  (BIT(19))
+#define UART_WAKEUP_INT_CLR_V  0x1
+#define UART_WAKEUP_INT_CLR_S  19
+/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */
+/*description: */
+#define UART_AT_CMD_CHAR_DET_INT_CLR  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_M  (BIT(18))
+#define UART_AT_CMD_CHAR_DET_INT_CLR_V  0x1
+#define UART_AT_CMD_CHAR_DET_INT_CLR_S  18
+/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_CLASH_INT_CLR  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_M  (BIT(17))
+#define UART_RS485_CLASH_INT_CLR_V  0x1
+#define UART_RS485_CLASH_INT_CLR_S  17
+/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_FRM_ERR_INT_CLR  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_M  (BIT(16))
+#define UART_RS485_FRM_ERR_INT_CLR_V  0x1
+#define UART_RS485_FRM_ERR_INT_CLR_S  16
+/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_PARITY_ERR_INT_CLR  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_M  (BIT(15))
+#define UART_RS485_PARITY_ERR_INT_CLR_V  0x1
+#define UART_RS485_PARITY_ERR_INT_CLR_S  15
+/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_DONE_INT_CLR  (BIT(14))
+#define UART_TX_DONE_INT_CLR_M  (BIT(14))
+#define UART_TX_DONE_INT_CLR_V  0x1
+#define UART_TX_DONE_INT_CLR_S  14
+/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_IDLE_DONE_INT_CLR  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_M  (BIT(13))
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_IDLE_DONE_INT_CLR_S  13
+/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_BRK_DONE_INT_CLR  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_M  (BIT(12))
+#define UART_TX_BRK_DONE_INT_CLR_V  0x1
+#define UART_TX_BRK_DONE_INT_CLR_S  12
+/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UART_GLITCH_DET_INT_CLR  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_M  (BIT(11))
+#define UART_GLITCH_DET_INT_CLR_V  0x1
+#define UART_GLITCH_DET_INT_CLR_S  11
+/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XOFF_INT_CLR  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_M  (BIT(10))
+#define UART_SW_XOFF_INT_CLR_V  0x1
+#define UART_SW_XOFF_INT_CLR_S  10
+/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_XON_INT_CLR  (BIT(9))
+#define UART_SW_XON_INT_CLR_M  (BIT(9))
+#define UART_SW_XON_INT_CLR_V  0x1
+#define UART_SW_XON_INT_CLR_S  9
+/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_TOUT_INT_CLR  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_M  (BIT(8))
+#define UART_RXFIFO_TOUT_INT_CLR_V  0x1
+#define UART_RXFIFO_TOUT_INT_CLR_S  8
+/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UART_BRK_DET_INT_CLR  (BIT(7))
+#define UART_BRK_DET_INT_CLR_M  (BIT(7))
+#define UART_BRK_DET_INT_CLR_V  0x1
+#define UART_BRK_DET_INT_CLR_S  7
+/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UART_CTS_CHG_INT_CLR  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_M  (BIT(6))
+#define UART_CTS_CHG_INT_CLR_V  0x1
+#define UART_CTS_CHG_INT_CLR_S  6
+/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UART_DSR_CHG_INT_CLR  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_M  (BIT(5))
+#define UART_DSR_CHG_INT_CLR_V  0x1
+#define UART_DSR_CHG_INT_CLR_S  5
+/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_OVF_INT_CLR  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_M  (BIT(4))
+#define UART_RXFIFO_OVF_INT_CLR_V  0x1
+#define UART_RXFIFO_OVF_INT_CLR_S  4
+/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UART_FRM_ERR_INT_CLR  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_M  (BIT(3))
+#define UART_FRM_ERR_INT_CLR_V  0x1
+#define UART_FRM_ERR_INT_CLR_S  3
+/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UART_PARITY_ERR_INT_CLR  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_M  (BIT(2))
+#define UART_PARITY_ERR_INT_CLR_V  0x1
+#define UART_PARITY_ERR_INT_CLR_S  2
+/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UART_TXFIFO_EMPTY_INT_CLR  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_M  (BIT(1))
+#define UART_TXFIFO_EMPTY_INT_CLR_V  0x1
+#define UART_TXFIFO_EMPTY_INT_CLR_S  1
+/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXFIFO_FULL_INT_CLR  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_M  (BIT(0))
+#define UART_RXFIFO_FULL_INT_CLR_V  0x1
+#define UART_RXFIFO_FULL_INT_CLR_S  0
+
+#define UART_CLKDIV_REG(i)          (REG_UART_BASE(i) + 0x14)
+/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */
+/*description: */
+#define UART_CLKDIV_FRAG  0x0000000F
+#define UART_CLKDIV_FRAG_M  ((UART_CLKDIV_FRAG_V)<<(UART_CLKDIV_FRAG_S))
+#define UART_CLKDIV_FRAG_V  0xF
+#define UART_CLKDIV_FRAG_S  20
+/* UART_CLKDIV : R/W ;bitpos:[19:0] ;default: 20'h2B6 ; */
+/*description: */
+#define UART_CLKDIV  0x000FFFFF
+#define UART_CLKDIV_M  ((UART_CLKDIV_V)<<(UART_CLKDIV_S))
+#define UART_CLKDIV_V  0xFFFFF
+#define UART_CLKDIV_S  0
+
+#define UART_AUTOBAUD_REG(i)          (REG_UART_BASE(i) + 0x18)
+/* UART_GLITCH_FILT : R/W ;bitpos:[15:8] ;default: 8'h10 ; */
+/*description: */
+#define UART_GLITCH_FILT  0x000000FF
+#define UART_GLITCH_FILT_M  ((UART_GLITCH_FILT_V)<<(UART_GLITCH_FILT_S))
+#define UART_GLITCH_FILT_V  0xFF
+#define UART_GLITCH_FILT_S  8
+/* UART_AUTOBAUD_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_AUTOBAUD_EN  (BIT(0))
+#define UART_AUTOBAUD_EN_M  (BIT(0))
+#define UART_AUTOBAUD_EN_V  0x1
+#define UART_AUTOBAUD_EN_S  0
+
+#define UART_STATUS_REG(i)          (REG_UART_BASE(i) + 0x1C)
+/* UART_TXD : RO ;bitpos:[31] ;default: 8'h0 ; */
+/*description: */
+#define UART_TXD  (BIT(31))
+#define UART_TXD_M  (BIT(31))
+#define UART_TXD_V  0x1
+#define UART_TXD_S  31
+/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define UART_RTSN  (BIT(30))
+#define UART_RTSN_M  (BIT(30))
+#define UART_RTSN_V  0x1
+#define UART_RTSN_S  30
+/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define UART_DTRN  (BIT(29))
+#define UART_DTRN_M  (BIT(29))
+#define UART_DTRN_V  0x1
+#define UART_DTRN_S  29
+/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */
+/*description: */
+#define UART_TXFIFO_CNT  0x000003FF
+#define UART_TXFIFO_CNT_M  ((UART_TXFIFO_CNT_V)<<(UART_TXFIFO_CNT_S))
+#define UART_TXFIFO_CNT_V  0x3FF
+#define UART_TXFIFO_CNT_S  16
+/* UART_RXD : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UART_RXD  (BIT(15))
+#define UART_RXD_M  (BIT(15))
+#define UART_RXD_V  0x1
+#define UART_RXD_S  15
+/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UART_CTSN  (BIT(14))
+#define UART_CTSN_M  (BIT(14))
+#define UART_CTSN_V  0x1
+#define UART_CTSN_S  14
+/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UART_DSRN  (BIT(13))
+#define UART_DSRN_M  (BIT(13))
+#define UART_DSRN_V  0x1
+#define UART_DSRN_S  13
+/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */
+/*description: */
+#define UART_RXFIFO_CNT  0x000003FF
+#define UART_RXFIFO_CNT_M  ((UART_RXFIFO_CNT_V)<<(UART_RXFIFO_CNT_S))
+#define UART_RXFIFO_CNT_V  0x3FF
+#define UART_RXFIFO_CNT_S  0
+
+#define UART_CONF0_REG(i)          (REG_UART_BASE(i) + 0x20)
+/* UART_TICK_REF_ALWAYS_ON : R/W ;bitpos:[27] ;default: 1'b1 ; */
+/*description: */
+#define UART_TICK_REF_ALWAYS_ON  (BIT(27))
+#define UART_TICK_REF_ALWAYS_ON_M  (BIT(27))
+#define UART_TICK_REF_ALWAYS_ON_V  0x1
+#define UART_TICK_REF_ALWAYS_ON_S  27
+/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */
+/*description: */
+#define UART_ERR_WR_MASK  (BIT(26))
+#define UART_ERR_WR_MASK_M  (BIT(26))
+#define UART_ERR_WR_MASK_V  0x1
+#define UART_ERR_WR_MASK_S  26
+/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */
+/*description: */
+#define UART_CLK_EN  (BIT(25))
+#define UART_CLK_EN_M  (BIT(25))
+#define UART_CLK_EN_V  0x1
+#define UART_CLK_EN_S  25
+/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */
+/*description: */
+#define UART_DTR_INV  (BIT(24))
+#define UART_DTR_INV_M  (BIT(24))
+#define UART_DTR_INV_V  0x1
+#define UART_DTR_INV_S  24
+/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */
+/*description: */
+#define UART_RTS_INV  (BIT(23))
+#define UART_RTS_INV_M  (BIT(23))
+#define UART_RTS_INV_V  0x1
+#define UART_RTS_INV_S  23
+/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */
+/*description: */
+#define UART_TXD_INV  (BIT(22))
+#define UART_TXD_INV_M  (BIT(22))
+#define UART_TXD_INV_V  0x1
+#define UART_TXD_INV_S  22
+/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */
+/*description: */
+#define UART_DSR_INV  (BIT(21))
+#define UART_DSR_INV_M  (BIT(21))
+#define UART_DSR_INV_V  0x1
+#define UART_DSR_INV_S  21
+/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */
+/*description: */
+#define UART_CTS_INV  (BIT(20))
+#define UART_CTS_INV_M  (BIT(20))
+#define UART_CTS_INV_V  0x1
+#define UART_CTS_INV_S  20
+/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */
+/*description: */
+#define UART_RXD_INV  (BIT(19))
+#define UART_RXD_INV_M  (BIT(19))
+#define UART_RXD_INV_V  0x1
+#define UART_RXD_INV_S  19
+/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */
+/*description: */
+#define UART_TXFIFO_RST  (BIT(18))
+#define UART_TXFIFO_RST_M  (BIT(18))
+#define UART_TXFIFO_RST_V  0x1
+#define UART_TXFIFO_RST_S  18
+/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */
+/*description: */
+#define UART_RXFIFO_RST  (BIT(17))
+#define UART_RXFIFO_RST_M  (BIT(17))
+#define UART_RXFIFO_RST_V  0x1
+#define UART_RXFIFO_RST_S  17
+/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define UART_IRDA_EN  (BIT(16))
+#define UART_IRDA_EN_M  (BIT(16))
+#define UART_IRDA_EN_V  0x1
+#define UART_IRDA_EN_S  16
+/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UART_TX_FLOW_EN  (BIT(15))
+#define UART_TX_FLOW_EN_M  (BIT(15))
+#define UART_TX_FLOW_EN_V  0x1
+#define UART_TX_FLOW_EN_S  15
+/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UART_LOOPBACK  (BIT(14))
+#define UART_LOOPBACK_M  (BIT(14))
+#define UART_LOOPBACK_V  0x1
+#define UART_LOOPBACK_S  14
+/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UART_IRDA_RX_INV  (BIT(13))
+#define UART_IRDA_RX_INV_M  (BIT(13))
+#define UART_IRDA_RX_INV_V  0x1
+#define UART_IRDA_RX_INV_S  13
+/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UART_IRDA_TX_INV  (BIT(12))
+#define UART_IRDA_TX_INV_M  (BIT(12))
+#define UART_IRDA_TX_INV_V  0x1
+#define UART_IRDA_TX_INV_S  12
+/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UART_IRDA_WCTL  (BIT(11))
+#define UART_IRDA_WCTL_M  (BIT(11))
+#define UART_IRDA_WCTL_V  0x1
+#define UART_IRDA_WCTL_S  11
+/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UART_IRDA_TX_EN  (BIT(10))
+#define UART_IRDA_TX_EN_M  (BIT(10))
+#define UART_IRDA_TX_EN_V  0x1
+#define UART_IRDA_TX_EN_S  10
+/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UART_IRDA_DPLX  (BIT(9))
+#define UART_IRDA_DPLX_M  (BIT(9))
+#define UART_IRDA_DPLX_V  0x1
+#define UART_IRDA_DPLX_S  9
+/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UART_TXD_BRK  (BIT(8))
+#define UART_TXD_BRK_M  (BIT(8))
+#define UART_TXD_BRK_V  0x1
+#define UART_TXD_BRK_S  8
+/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_DTR  (BIT(7))
+#define UART_SW_DTR_M  (BIT(7))
+#define UART_SW_DTR_V  0x1
+#define UART_SW_DTR_S  7
+/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_RTS  (BIT(6))
+#define UART_SW_RTS_M  (BIT(6))
+#define UART_SW_RTS_V  0x1
+#define UART_SW_RTS_S  6
+/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */
+/*description: */
+#define UART_STOP_BIT_NUM  0x00000003
+#define UART_STOP_BIT_NUM_M  ((UART_STOP_BIT_NUM_V)<<(UART_STOP_BIT_NUM_S))
+#define UART_STOP_BIT_NUM_V  0x3
+#define UART_STOP_BIT_NUM_S  4
+/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */
+/*description: */
+#define UART_BIT_NUM  0x00000003
+#define UART_BIT_NUM_M  ((UART_BIT_NUM_V)<<(UART_BIT_NUM_S))
+#define UART_BIT_NUM_V  0x3
+#define UART_BIT_NUM_S  2
+/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UART_PARITY_EN  (BIT(1))
+#define UART_PARITY_EN_M  (BIT(1))
+#define UART_PARITY_EN_V  0x1
+#define UART_PARITY_EN_S  1
+/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_PARITY  (BIT(0))
+#define UART_PARITY_M  (BIT(0))
+#define UART_PARITY_V  0x1
+#define UART_PARITY_S  0
+
+#define UART_CONF1_REG(i)          (REG_UART_BASE(i) + 0x24)
+/* UART_RX_TOUT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
+/*description: */
+#define UART_RX_TOUT_EN  (BIT(31))
+#define UART_RX_TOUT_EN_M  (BIT(31))
+#define UART_RX_TOUT_EN_V  0x1
+#define UART_RX_TOUT_EN_S  31
+/* UART_RX_FLOW_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define UART_RX_FLOW_EN  (BIT(30))
+#define UART_RX_FLOW_EN_M  (BIT(30))
+#define UART_RX_FLOW_EN_V  0x1
+#define UART_RX_FLOW_EN_S  30
+/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define UART_RX_TOUT_FLOW_DIS  (BIT(29))
+#define UART_RX_TOUT_FLOW_DIS_M  (BIT(29))
+#define UART_RX_TOUT_FLOW_DIS_V  0x1
+#define UART_RX_TOUT_FLOW_DIS_S  29
+/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */
+/*description: */
+#define UART_TXFIFO_EMPTY_THRHD  0x000001FF
+#define UART_TXFIFO_EMPTY_THRHD_M  ((UART_TXFIFO_EMPTY_THRHD_V)<<(UART_TXFIFO_EMPTY_THRHD_S))
+#define UART_TXFIFO_EMPTY_THRHD_V  0x1FF
+#define UART_TXFIFO_EMPTY_THRHD_S  9
+/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */
+/*description: */
+#define UART_RXFIFO_FULL_THRHD  0x000001FF
+#define UART_RXFIFO_FULL_THRHD_M  ((UART_RXFIFO_FULL_THRHD_V)<<(UART_RXFIFO_FULL_THRHD_S))
+#define UART_RXFIFO_FULL_THRHD_V  0x1FF
+#define UART_RXFIFO_FULL_THRHD_S  0
+
+#define UART_LOWPULSE_REG(i)          (REG_UART_BASE(i) + 0x28)
+/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: */
+#define UART_LOWPULSE_MIN_CNT  0x000FFFFF
+#define UART_LOWPULSE_MIN_CNT_M  ((UART_LOWPULSE_MIN_CNT_V)<<(UART_LOWPULSE_MIN_CNT_S))
+#define UART_LOWPULSE_MIN_CNT_V  0xFFFFF
+#define UART_LOWPULSE_MIN_CNT_S  0
+
+#define UART_HIGHPULSE_REG(i)          (REG_UART_BASE(i) + 0x2C)
+/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: */
+#define UART_HIGHPULSE_MIN_CNT  0x000FFFFF
+#define UART_HIGHPULSE_MIN_CNT_M  ((UART_HIGHPULSE_MIN_CNT_V)<<(UART_HIGHPULSE_MIN_CNT_S))
+#define UART_HIGHPULSE_MIN_CNT_V  0xFFFFF
+#define UART_HIGHPULSE_MIN_CNT_S  0
+
+#define UART_RXD_CNT_REG(i)          (REG_UART_BASE(i) + 0x30)
+/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define UART_RXD_EDGE_CNT  0x000003FF
+#define UART_RXD_EDGE_CNT_M  ((UART_RXD_EDGE_CNT_V)<<(UART_RXD_EDGE_CNT_S))
+#define UART_RXD_EDGE_CNT_V  0x3FF
+#define UART_RXD_EDGE_CNT_S  0
+
+#define UART_FLOW_CONF_REG(i)          (REG_UART_BASE(i) + 0x34)
+/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UART_SEND_XOFF  (BIT(5))
+#define UART_SEND_XOFF_M  (BIT(5))
+#define UART_SEND_XOFF_V  0x1
+#define UART_SEND_XOFF_S  5
+/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UART_SEND_XON  (BIT(4))
+#define UART_SEND_XON_M  (BIT(4))
+#define UART_SEND_XON_V  0x1
+#define UART_SEND_XON_S  4
+/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UART_FORCE_XOFF  (BIT(3))
+#define UART_FORCE_XOFF_M  (BIT(3))
+#define UART_FORCE_XOFF_V  0x1
+#define UART_FORCE_XOFF_S  3
+/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UART_FORCE_XON  (BIT(2))
+#define UART_FORCE_XON_M  (BIT(2))
+#define UART_FORCE_XON_V  0x1
+#define UART_FORCE_XON_S  2
+/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UART_XONOFF_DEL  (BIT(1))
+#define UART_XONOFF_DEL_M  (BIT(1))
+#define UART_XONOFF_DEL_V  0x1
+#define UART_XONOFF_DEL_S  1
+/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_SW_FLOW_CON_EN  (BIT(0))
+#define UART_SW_FLOW_CON_EN_M  (BIT(0))
+#define UART_SW_FLOW_CON_EN_V  0x1
+#define UART_SW_FLOW_CON_EN_S  0
+
+#define UART_SLEEP_CONF_REG(i)          (REG_UART_BASE(i) + 0x38)
+/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */
+/*description: */
+#define UART_ACTIVE_THRESHOLD  0x000003FF
+#define UART_ACTIVE_THRESHOLD_M  ((UART_ACTIVE_THRESHOLD_V)<<(UART_ACTIVE_THRESHOLD_S))
+#define UART_ACTIVE_THRESHOLD_V  0x3FF
+#define UART_ACTIVE_THRESHOLD_S  0
+
+#define UART_SWFC_CONF0_REG(i)          (REG_UART_BASE(i) + 0x3C)
+/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */
+/*description: */
+#define UART_XOFF_CHAR  0x000000FF
+#define UART_XOFF_CHAR_M  ((UART_XOFF_CHAR_V)<<(UART_XOFF_CHAR_S))
+#define UART_XOFF_CHAR_V  0xFF
+#define UART_XOFF_CHAR_S  9
+/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */
+/*description: */
+#define UART_XOFF_THRESHOLD  0x000001FF
+#define UART_XOFF_THRESHOLD_M  ((UART_XOFF_THRESHOLD_V)<<(UART_XOFF_THRESHOLD_S))
+#define UART_XOFF_THRESHOLD_V  0x1FF
+#define UART_XOFF_THRESHOLD_S  0
+
+#define UART_SWFC_CONF1_REG(i)          (REG_UART_BASE(i) + 0x40)
+/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */
+/*description: */
+#define UART_XON_CHAR  0x000000FF
+#define UART_XON_CHAR_M  ((UART_XON_CHAR_V)<<(UART_XON_CHAR_S))
+#define UART_XON_CHAR_V  0xFF
+#define UART_XON_CHAR_S  9
+/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define UART_XON_THRESHOLD  0x000001FF
+#define UART_XON_THRESHOLD_M  ((UART_XON_THRESHOLD_V)<<(UART_XON_THRESHOLD_S))
+#define UART_XON_THRESHOLD_V  0x1FF
+#define UART_XON_THRESHOLD_S  0
+
+#define UART_IDLE_CONF_REG(i)          (REG_UART_BASE(i) + 0x44)
+/* UART_TX_BRK_NUM : R/W ;bitpos:[27:20] ;default: 8'ha ; */
+/*description: */
+#define UART_TX_BRK_NUM  0x000000FF
+#define UART_TX_BRK_NUM_M  ((UART_TX_BRK_NUM_V)<<(UART_TX_BRK_NUM_S))
+#define UART_TX_BRK_NUM_V  0xFF
+#define UART_TX_BRK_NUM_S  20
+/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */
+/*description: */
+#define UART_TX_IDLE_NUM  0x000003FF
+#define UART_TX_IDLE_NUM_M  ((UART_TX_IDLE_NUM_V)<<(UART_TX_IDLE_NUM_S))
+#define UART_TX_IDLE_NUM_V  0x3FF
+#define UART_TX_IDLE_NUM_S  10
+/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */
+/*description: */
+#define UART_RX_IDLE_THRHD  0x000003FF
+#define UART_RX_IDLE_THRHD_M  ((UART_RX_IDLE_THRHD_V)<<(UART_RX_IDLE_THRHD_S))
+#define UART_RX_IDLE_THRHD_V  0x3FF
+#define UART_RX_IDLE_THRHD_S  0
+
+#define UART_RS485_CONF_REG(i)          (REG_UART_BASE(i) + 0x48)
+/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */
+/*description: */
+#define UART_RS485_TX_DLY_NUM  0x0000000F
+#define UART_RS485_TX_DLY_NUM_M  ((UART_RS485_TX_DLY_NUM_V)<<(UART_RS485_TX_DLY_NUM_S))
+#define UART_RS485_TX_DLY_NUM_V  0xF
+#define UART_RS485_TX_DLY_NUM_S  6
+/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_RX_DLY_NUM  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_M  (BIT(5))
+#define UART_RS485_RX_DLY_NUM_V  0x1
+#define UART_RS485_RX_DLY_NUM_S  5
+/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485RXBY_TX_EN  (BIT(4))
+#define UART_RS485RXBY_TX_EN_M  (BIT(4))
+#define UART_RS485RXBY_TX_EN_V  0x1
+#define UART_RS485RXBY_TX_EN_S  4
+/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485TX_RX_EN  (BIT(3))
+#define UART_RS485TX_RX_EN_M  (BIT(3))
+#define UART_RS485TX_RX_EN_V  0x1
+#define UART_RS485TX_RX_EN_S  3
+/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UART_DL1_EN  (BIT(2))
+#define UART_DL1_EN_M  (BIT(2))
+#define UART_DL1_EN_V  0x1
+#define UART_DL1_EN_S  2
+/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UART_DL0_EN  (BIT(1))
+#define UART_DL0_EN_M  (BIT(1))
+#define UART_DL0_EN_V  0x1
+#define UART_DL0_EN_S  1
+/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_RS485_EN  (BIT(0))
+#define UART_RS485_EN_M  (BIT(0))
+#define UART_RS485_EN_V  0x1
+#define UART_RS485_EN_S  0
+
+#define UART_AT_CMD_PRECNT_REG(i)          (REG_UART_BASE(i) + 0x4c)
+/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: */
+#define UART_PRE_IDLE_NUM  0x0000FFFF
+#define UART_PRE_IDLE_NUM_M  ((UART_PRE_IDLE_NUM_V)<<(UART_PRE_IDLE_NUM_S))
+#define UART_PRE_IDLE_NUM_V  0xFFFF
+#define UART_PRE_IDLE_NUM_S  0
+
+#define UART_AT_CMD_POSTCNT_REG(i)          (REG_UART_BASE(i) + 0x50)
+/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */
+/*description: */
+#define UART_POST_IDLE_NUM  0x0000FFFF
+#define UART_POST_IDLE_NUM_M  ((UART_POST_IDLE_NUM_V)<<(UART_POST_IDLE_NUM_S))
+#define UART_POST_IDLE_NUM_V  0xFFFF
+#define UART_POST_IDLE_NUM_S  0
+
+#define UART_AT_CMD_GAPTOUT_REG(i)          (REG_UART_BASE(i) + 0x54)
+/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */
+/*description: */
+#define UART_RX_GAP_TOUT  0x0000FFFF
+#define UART_RX_GAP_TOUT_M  ((UART_RX_GAP_TOUT_V)<<(UART_RX_GAP_TOUT_S))
+#define UART_RX_GAP_TOUT_V  0xFFFF
+#define UART_RX_GAP_TOUT_S  0
+
+#define UART_AT_CMD_CHAR_REG(i)          (REG_UART_BASE(i) + 0x58)
+/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */
+/*description: */
+#define UART_CHAR_NUM  0x000000FF
+#define UART_CHAR_NUM_M  ((UART_CHAR_NUM_V)<<(UART_CHAR_NUM_S))
+#define UART_CHAR_NUM_V  0xFF
+#define UART_CHAR_NUM_S  8
+/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */
+/*description: */
+#define UART_AT_CMD_CHAR  0x000000FF
+#define UART_AT_CMD_CHAR_M  ((UART_AT_CMD_CHAR_V)<<(UART_AT_CMD_CHAR_S))
+#define UART_AT_CMD_CHAR_V  0xFF
+#define UART_AT_CMD_CHAR_S  0
+
+#define UART_MEM_CONF_REG(i)          (REG_UART_BASE(i) + 0x5c)
+/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */
+/*description: */
+#define UART_RX_TOUT_THRHD  0x000003FF
+#define UART_RX_TOUT_THRHD_M  ((UART_RX_TOUT_THRHD_V)<<(UART_RX_TOUT_THRHD_S))
+#define UART_RX_TOUT_THRHD_V  0x3FF
+#define UART_RX_TOUT_THRHD_S  16
+/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */
+/*description: */
+#define UART_RX_FLOW_THRHD  0x000001FF
+#define UART_RX_FLOW_THRHD_M  ((UART_RX_FLOW_THRHD_V)<<(UART_RX_FLOW_THRHD_S))
+#define UART_RX_FLOW_THRHD_V  0x1FF
+#define UART_RX_FLOW_THRHD_S  7
+/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */
+/*description: */
+#define UART_TX_SIZE  0x00000007
+#define UART_TX_SIZE_M  ((UART_TX_SIZE_V)<<(UART_TX_SIZE_S))
+#define UART_TX_SIZE_V  0x7
+#define UART_TX_SIZE_S  4
+/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */
+/*description: */
+#define UART_RX_SIZE  0x00000007
+#define UART_RX_SIZE_M  ((UART_RX_SIZE_V)<<(UART_RX_SIZE_S))
+#define UART_RX_SIZE_V  0x7
+#define UART_RX_SIZE_S  1
+/* UART_MEM_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UART_MEM_PD  (BIT(0))
+#define UART_MEM_PD_M  (BIT(0))
+#define UART_MEM_PD_V  0x1
+#define UART_MEM_PD_S  0
+
+#define UART_MEM_TX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x60)
+/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
+/*description: */
+#define UART_TX_RADDR  0x000003FF
+#define UART_TX_RADDR_M  ((UART_TX_RADDR_V)<<(UART_TX_RADDR_S))
+#define UART_TX_RADDR_V  0x3FF
+#define UART_TX_RADDR_S  11
+/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define UART_APB_TX_WADDR  0x000003FF
+#define UART_APB_TX_WADDR_M  ((UART_APB_TX_WADDR_V)<<(UART_APB_TX_WADDR_S))
+#define UART_APB_TX_WADDR_V  0x3FF
+#define UART_APB_TX_WADDR_S  0
+
+#define UART_MEM_RX_STATUS_REG(i)          (REG_UART_BASE(i) + 0x64)
+/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */
+/*description: */
+#define UART_RX_WADDR  0x000003FF
+#define UART_RX_WADDR_M  ((UART_RX_WADDR_V)<<(UART_RX_WADDR_S))
+#define UART_RX_WADDR_V  0x3FF
+#define UART_RX_WADDR_S  11
+/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */
+/*description: */
+#define UART_APB_RX_RADDR  0x000003FF
+#define UART_APB_RX_RADDR_M  ((UART_APB_RX_RADDR_V)<<(UART_APB_RX_RADDR_S))
+#define UART_APB_RX_RADDR_V  0x3FF
+#define UART_APB_RX_RADDR_S  0
+
+#define UART_FSM_STATUS_REG(i)          (REG_UART_BASE(i) + 0x68)
+/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */
+/*description: */
+#define UART_ST_UTX_OUT  0x0000000F
+#define UART_ST_UTX_OUT_M  ((UART_ST_UTX_OUT_V)<<(UART_ST_UTX_OUT_S))
+#define UART_ST_UTX_OUT_V  0xF
+#define UART_ST_UTX_OUT_S  4
+/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */
+/*description: */
+#define UART_ST_URX_OUT  0x0000000F
+#define UART_ST_URX_OUT_M  ((UART_ST_URX_OUT_V)<<(UART_ST_URX_OUT_S))
+#define UART_ST_URX_OUT_V  0xF
+#define UART_ST_URX_OUT_S  0
+
+#define UART_POSPULSE_REG(i)          (REG_UART_BASE(i) + 0x6c)
+/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: */
+#define UART_POSEDGE_MIN_CNT  0x000FFFFF
+#define UART_POSEDGE_MIN_CNT_M  ((UART_POSEDGE_MIN_CNT_V)<<(UART_POSEDGE_MIN_CNT_S))
+#define UART_POSEDGE_MIN_CNT_V  0xFFFFF
+#define UART_POSEDGE_MIN_CNT_S  0
+
+#define UART_NEGPULSE_REG(i)          (REG_UART_BASE(i) + 0x70)
+/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[19:0] ;default: 20'hFFFFF ; */
+/*description: */
+#define UART_NEGEDGE_MIN_CNT  0x000FFFFF
+#define UART_NEGEDGE_MIN_CNT_M  ((UART_NEGEDGE_MIN_CNT_V)<<(UART_NEGEDGE_MIN_CNT_S))
+#define UART_NEGEDGE_MIN_CNT_V  0xFFFFF
+#define UART_NEGEDGE_MIN_CNT_S  0
+
+#define UART_DATE_REG(i)          (REG_UART_BASE(i) + 0x74)
+/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h18082800 ; */
+/*description: */
+#define UART_DATE  0xFFFFFFFF
+#define UART_DATE_M  ((UART_DATE_V)<<(UART_DATE_S))
+#define UART_DATE_V  0xFFFFFFFF
+#define UART_DATE_S  0
+
+#define UART_ID_REG(i)          (REG_UART_BASE(i) + 0x78)
+/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */
+/*description: */
+#define UART_ID  0xFFFFFFFF
+#define UART_ID_M  ((UART_ID_V)<<(UART_ID_S))
+#define UART_ID_V  0xFFFFFFFF
+#define UART_ID_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UART_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/uart_struct.h b/components/soc/esp32s2beta/include/soc/uart_struct.h
new file mode 100644
index 000000000..c4096d5f9
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/uart_struct.h
@@ -0,0 +1,375 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UART_STRUCT_H_
+#define _SOC_UART_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint8_t rw_byte;                 /*This register stores one byte data  read by rx fifo.*/
+            uint8_t reserved[3];
+        };
+        uint32_t val;
+    } ahb_fifo;
+    union {
+        struct {
+            uint32_t rxfifo_full:      1;           /*This interrupt raw bit turns to high level when receiver receives more data than (rx_flow_thrhd_h3 rx_flow_thrhd).*/
+            uint32_t txfifo_empty:     1;           /*This interrupt raw bit turns to high level when the amount of data in transmitter's fifo is less than ((tx_mem_cnttxfifo_cnt) .*/
+            uint32_t parity_err:       1;           /*This interrupt raw bit turns to high level when receiver detects the parity error of data.*/
+            uint32_t frm_err:          1;           /*This interrupt raw bit turns to high level when receiver detects data's frame error .*/
+            uint32_t rxfifo_ovf:       1;           /*This interrupt raw bit turns to high level when receiver receives more data than the fifo can store.*/
+            uint32_t dsr_chg:          1;           /*This interrupt raw bit turns to high level when receiver detects the edge change of dsrn signal.*/
+            uint32_t cts_chg:          1;           /*This interrupt raw bit turns to high level when receiver detects the edge change of ctsn signal.*/
+            uint32_t brk_det:          1;           /*This interrupt raw bit turns to high level when receiver detects the 0 after the stop bit.*/
+            uint32_t rxfifo_tout:      1;           /*This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.*/
+            uint32_t sw_xon:           1;           /*This interrupt raw bit turns to high level when receiver receives xoff char with uart_sw_flow_con_en is set to 1.*/
+            uint32_t sw_xoff:          1;           /*This interrupt raw bit turns to high level when receiver receives xon char with uart_sw_flow_con_en is set to 1.*/
+            uint32_t glitch_det:       1;           /*This interrupt raw bit turns to high level when receiver detects the start bit.*/
+            uint32_t tx_brk_done:      1;           /*This interrupt raw bit turns to high level when transmitter completes  sending  0 after all the data in transmitter's fifo are send.*/
+            uint32_t tx_brk_idle_done: 1;           /*This interrupt raw bit turns to high level when transmitter has kept the shortest duration after the  last data has been send.*/
+            uint32_t tx_done:          1;           /*This interrupt raw bit turns to high level when transmitter has send all the data in fifo.*/
+            uint32_t rs485_parity_err: 1;           /*This interrupt raw bit turns to high level when rs485 detects the parity error.*/
+            uint32_t rs485_frm_err:    1;           /*This interrupt raw bit turns to high level when rs485 detects the data frame error.*/
+            uint32_t rs485_clash:      1;           /*This interrupt raw bit turns to high level when rs485 detects the clash between transmitter and receiver.*/
+            uint32_t at_cmd_char_det:  1;           /*This interrupt raw bit turns to high level when receiver detects the configured at_cmd chars.*/
+            uint32_t reserved19:      13;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rxfifo_full:      1;            /*This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.*/
+            uint32_t txfifo_empty:     1;            /*This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.*/
+            uint32_t parity_err:       1;            /*This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.*/
+            uint32_t frm_err:          1;            /*This is the status bit for frm_err_int_raw when fm_err_int_ena is set to 1.*/
+            uint32_t rxfifo_ovf:       1;            /*This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.*/
+            uint32_t dsr_chg:          1;            /*This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.*/
+            uint32_t cts_chg:          1;            /*This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.*/
+            uint32_t brk_det:          1;            /*This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.*/
+            uint32_t rxfifo_tout:      1;            /*This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.*/
+            uint32_t sw_xon:           1;            /*This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.*/
+            uint32_t sw_xoff:          1;            /*This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.*/
+            uint32_t glitch_det:       1;            /*This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.*/
+            uint32_t tx_brk_done:      1;            /*This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.*/
+            uint32_t tx_brk_idle_done: 1;            /*This is the status bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.*/
+            uint32_t tx_done:          1;            /*This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.*/
+            uint32_t rs485_parity_err: 1;            /*This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.*/
+            uint32_t rs485_frm_err:    1;            /*This is the status bit for rs485_fm_err_int_raw when rs485_fm_err_int_ena is set to 1.*/
+            uint32_t rs485_clash:      1;            /*This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.*/
+            uint32_t at_cmd_char_det:  1;            /*This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.*/
+            uint32_t reserved19:      13;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rxfifo_full:      1;           /*This is the enable bit for rxfifo_full_int_st register.*/
+            uint32_t txfifo_empty:     1;           /*This is the enable bit for rxfifo_full_int_st register.*/
+            uint32_t parity_err:       1;           /*This is the enable bit for parity_err_int_st register.*/
+            uint32_t frm_err:          1;           /*This is the enable bit for frm_err_int_st register.*/
+            uint32_t rxfifo_ovf:       1;           /*This is the enable bit for rxfifo_ovf_int_st register.*/
+            uint32_t dsr_chg:          1;           /*This is the enable bit for dsr_chg_int_st register.*/
+            uint32_t cts_chg:          1;           /*This is the enable bit for cts_chg_int_st register.*/
+            uint32_t brk_det:          1;           /*This is the enable bit for brk_det_int_st register.*/
+            uint32_t rxfifo_tout:      1;           /*This is the enable bit for rxfifo_tout_int_st register.*/
+            uint32_t sw_xon:           1;           /*This is the enable bit for sw_xon_int_st register.*/
+            uint32_t sw_xoff:          1;           /*This is the enable bit for sw_xoff_int_st register.*/
+            uint32_t glitch_det:       1;           /*This is the enable bit for glitch_det_int_st register.*/
+            uint32_t tx_brk_done:      1;           /*This is the enable bit for tx_brk_done_int_st register.*/
+            uint32_t tx_brk_idle_done: 1;           /*This is the enable bit for tx_brk_idle_done_int_st register.*/
+            uint32_t tx_done:          1;           /*This is the enable bit for tx_done_int_st register.*/
+            uint32_t rs485_parity_err: 1;           /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_frm_err:    1;           /*This is the enable bit for rs485_parity_err_int_st register.*/
+            uint32_t rs485_clash:      1;           /*This is the enable bit for rs485_clash_int_st register.*/
+            uint32_t at_cmd_char_det:  1;           /*This is the enable bit for at_cmd_char_det_int_st register.*/
+            uint32_t reserved19:      13;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rxfifo_full:      1;           /*Set this bit to clear the rxfifo_full_int_raw interrupt.*/
+            uint32_t txfifo_empty:     1;           /*Set this bit to clear txfifo_empty_int_raw interrupt.*/
+            uint32_t parity_err:       1;           /*Set this bit to clear parity_err_int_raw interrupt.*/
+            uint32_t frm_err:          1;           /*Set this bit to clear frm_err_int_raw interrupt.*/
+            uint32_t rxfifo_ovf:       1;           /*Set this bit to clear rxfifo_ovf_int_raw interrupt.*/
+            uint32_t dsr_chg:          1;           /*Set this bit to clear the dsr_chg_int_raw interrupt.*/
+            uint32_t cts_chg:          1;           /*Set this bit to clear the cts_chg_int_raw interrupt.*/
+            uint32_t brk_det:          1;           /*Set this bit to clear the brk_det_int_raw interrupt.*/
+            uint32_t rxfifo_tout:      1;           /*Set this bit to clear the rxfifo_tout_int_raw interrupt.*/
+            uint32_t sw_xon:           1;           /*Set this bit to clear the sw_xon_int_raw interrupt.*/
+            uint32_t sw_xoff:          1;           /*Set this bit to clear the sw_xon_int_raw interrupt.*/
+            uint32_t glitch_det:       1;           /*Set this bit to clear the glitch_det_int_raw interrupt.*/
+            uint32_t tx_brk_done:      1;           /*Set this bit to clear the tx_brk_done_int_raw interrupt..*/
+            uint32_t tx_brk_idle_done: 1;           /*Set this bit to clear the tx_brk_idle_done_int_raw interrupt.*/
+            uint32_t tx_done:          1;           /*Set this bit to clear the tx_done_int_raw interrupt.*/
+            uint32_t rs485_parity_err: 1;           /*Set this bit to clear the rs485_parity_err_int_raw interrupt.*/
+            uint32_t rs485_frm_err:    1;           /*Set this bit to clear the rs485_frm_err_int_raw interrupt.*/
+            uint32_t rs485_clash:      1;           /*Set this bit to clear the rs485_clash_int_raw interrupt.*/
+            uint32_t at_cmd_char_det:  1;           /*Set this bit to clear the at_cmd_char_det_int_raw interrupt.*/
+            uint32_t reserved19:      13;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t div_int:    20;                /*The register value is  the  integer part of the frequency divider's factor.*/
+            uint32_t div_frag:    4;                /*The register  value is the decimal part of the frequency divider's factor.*/
+            uint32_t reserved24:  8;
+        };
+        uint32_t val;
+    } clk_div;
+    union {
+        struct {
+            uint32_t en: 1;                         /*This is the enable bit for detecting baudrate.*/
+            uint32_t reserved1:   7;
+            uint32_t glitch_filt: 8;                /*when input pulse width is lower then this value ignore this pulse.this register is used in auto-baud detect process.*/
+            uint32_t reserved16: 16;
+        };
+        uint32_t val;
+    } auto_baud;
+    union {
+        struct {
+            uint32_t rxfifo_cnt: 8;                 /*(rx_mem_cnt rxfifo_cnt) stores the byte number of valid data in receiver's fifo. rx_mem_cnt register stores the 3 most significant bits  rxfifo_cnt stores the 8 least significant bits.*/
+            uint32_t st_urx_out: 4;                 /*This register stores the value of receiver's finite state machine. 0:RX_IDLE  1:RX_STRT  2:RX_DAT0  3:RX_DAT1  4:RX_DAT2  5:RX_DAT3  6:RX_DAT4  7:RX_DAT5  8:RX_DAT6  9:RX_DAT7   10:RX_PRTY   11:RX_STP1  12:RX_STP2 13:RX_DL1*/
+            uint32_t reserved12: 1;
+            uint32_t dsrn:       1;                 /*This register stores the level value of the internal uart dsr signal.*/
+            uint32_t ctsn:       1;                 /*This register stores the level value of the internal uart cts signal.*/
+            uint32_t rxd:        1;                 /*This register stores the level value of the internal uart rxd signal.*/
+            uint32_t txfifo_cnt: 8;                 /*(tx_mem_cnt txfifo_cnt) stores the byte number of valid data in transmitter's fifo.tx_mem_cnt stores the 3 most significant bits  txfifo_cnt stores the 8 least significant bits.*/
+            uint32_t st_utx_out: 4;                 /*This register stores the value of transmitter's finite state machine. 0:TX_IDLE  1:TX_STRT  2:TX_DAT0  3:TX_DAT1  4:TX_DAT2   5:TX_DAT3 6:TX_DAT4  7:TX_DAT5  8:TX_DAT6 9:TX_DAT7  10:TX_PRTY   11:TX_STP1  12:TX_STP2  13:TX_DL0   14:TX_DL1*/
+            uint32_t reserved28: 1;
+            uint32_t dtrn:       1;                 /*The register represent the level value of the internal uart dsr signal.*/
+            uint32_t rtsn:       1;                 /*This register represent the level value of the internal uart cts signal.*/
+            uint32_t txd:        1;                 /*This register represent the  level value of the internal uart rxd signal.*/
+        };
+        uint32_t val;
+    } status;
+    union {
+        struct {
+            uint32_t parity:             1;         /*This register is used to configure the parity check mode.  0:even 1:odd*/
+            uint32_t parity_en:          1;         /*Set this bit to enable uart parity check.*/
+            uint32_t bit_num:            2;         /*This register is used to set the length of data:  0:5bits 1:6bits 2:7bits 3:8bits*/
+            uint32_t stop_bit_num:       2;         /*This register is used to set the length of  stop bit. 1:1bit  2:1.5bits  3:2bits*/
+            uint32_t sw_rts:             1;         /*This register is used to configure the software rts signal which is used in software flow control.*/
+            uint32_t sw_dtr:             1;         /*This register is used to configure the software dtr signal which is used in software flow control..*/
+            uint32_t txd_brk:            1;         /*Set this bit to enable transmitter to  send 0 when the process of sending data is done.*/
+            uint32_t irda_dplx:          1;         /*Set this bit to enable irda loop-back mode.*/
+            uint32_t irda_tx_en:         1;         /*This is the start enable bit for irda transmitter.*/
+            uint32_t irda_wctl:          1;         /*1：the irda transmitter's 11th bit is the same to the 10th bit. 0：set irda transmitter's 11th bit to 0.*/
+            uint32_t irda_tx_inv:        1;         /*Set this bit to inverse the level value of  irda transmitter's level.*/
+            uint32_t irda_rx_inv:        1;         /*Set this bit to inverse the level value of irda receiver's level.*/
+            uint32_t loopback:           1;         /*Set this bit to enable uart loop-back test mode.*/
+            uint32_t tx_flow_en:         1;         /*Set this bit to enable transmitter's flow control function.*/
+            uint32_t irda_en:            1;         /*Set this bit to enable irda protocol.*/
+            uint32_t rxfifo_rst:         1;         /*Set this bit to reset uart receiver's fifo.*/
+            uint32_t txfifo_rst:         1;         /*Set this bit to reset uart transmitter's fifo.*/
+            uint32_t rxd_inv:            1;         /*Set this bit to inverse the level value of uart rxd signal.*/
+            uint32_t cts_inv:            1;         /*Set this bit to inverse the level value of uart cts signal.*/
+            uint32_t dsr_inv:            1;         /*Set this bit to inverse the level value of uart dsr signal.*/
+            uint32_t txd_inv:            1;         /*Set this bit to inverse the level value of uart txd signal.*/
+            uint32_t rts_inv:            1;         /*Set this bit to inverse the level value of uart rts signal.*/
+            uint32_t dtr_inv:            1;         /*Set this bit to inverse the level value of uart dtr signal.*/
+            uint32_t clk_en:             1;         /*1：force clock on for registers：support clock only when write registers*/
+            uint32_t err_wr_mask:        1;         /*1：receiver stops storing data int fifo when data is wrong. 0：receiver stores the data even if the  received data is wrong.*/
+            uint32_t tick_ref_always_on: 1;         /*This register is used to select the clock.1：apb clock：ref_tick*/
+            uint32_t reserved28:         4;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t rxfifo_full_thrhd:  7;
+            uint32_t reserved7:          1;
+            uint32_t txfifo_empty_thrhd: 7;
+            uint32_t rx_tout_flow_dis:   1;
+            uint32_t rx_flow_thrhd:      7;
+            uint32_t rx_flow_en:         1;
+            uint32_t rx_tout_thrhd:      7;
+            uint32_t rx_tout_en:         1;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t min_cnt:     20;               /*This register stores the value of the minimum duration time for the low level pulse， it is used in baudrate-detect process.*/
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } lowpulse;
+    union {
+        struct {
+            uint32_t min_cnt:     20;               /*This register stores  the value of the maximum duration time for the high level pulse， it is used in baudrate-detect process.*/
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } highpulse;
+    union {
+        struct {
+            uint32_t edge_cnt:    10;               /*This register stores the count of rxd edge change， it is used in baudrate-detect process.*/
+            uint32_t reserved10:  22;
+        };
+        uint32_t val;
+    } rxd_cnt;
+    union {
+        struct {
+            uint32_t sw_flow_con_en: 1;             /*Set this bit to enable software  flow control. it is used with register sw_xon or sw_xoff .*/
+            uint32_t xonoff_del:     1;             /*Set this bit to remove flow control char from the received data.*/
+            uint32_t force_xon:      1;             /*Set this bit to clear ctsn to stop the  transmitter from sending data.*/
+            uint32_t force_xoff:     1;             /*Set this bit to set ctsn to enable the transmitter to go on sending data.*/
+            uint32_t send_xon:       1;             /*Set this bit to send xon char， it is cleared by hardware automatically.*/
+            uint32_t send_xoff:      1;             /*Set this bit to send xoff char， it is cleared by hardware automatically.*/
+            uint32_t reserved6:     26;
+        };
+        uint32_t val;
+    } flow_conf;
+    union {
+        struct {
+            uint32_t active_threshold:10;           /*When the input rxd edge changes more than this register value， the uart is active from light sleeping mode.*/
+            uint32_t reserved10:      22;
+        };
+        uint32_t val;
+    } sleep_conf;
+    union {
+        struct {
+            uint32_t xon_threshold:  8;             /*when the data amount in receiver's fifo is more than this register value， it will send a xoff char with uart_sw_flow_con_en set to 1.*/
+            uint32_t xoff_threshold: 8;             /*When the data amount in receiver's fifo is less than this register value， it will send a xon char with uart_sw_flow_con_en set to 1.*/
+            uint32_t xon_char:       8;             /*This register stores the xon flow control char.*/
+            uint32_t xoff_char:      8;             /*This register stores the xoff flow control char.*/
+        };
+        uint32_t val;
+    } swfc_conf;
+    union {
+        struct {
+            uint32_t rx_idle_thrhd:10;              /*when receiver takes more time than this register value to receive a byte data， it will produce frame end signal for uhci to stop receiving data.*/
+            uint32_t tx_idle_num:  10;              /*This register is used to configure the duration time between transfers.*/
+            uint32_t tx_brk_num:    8;              /*This register is used to configure the number of 0 send after the process of sending data is done. it is active when txd_brk is set to 1.*/
+            uint32_t reserved28:    4;
+        };
+        uint32_t val;
+    } idle_conf;
+    union {
+        struct {
+            uint32_t en:               1;           /*Set this bit to choose rs485 mode.*/
+            uint32_t dl0_en:           1;           /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t dl1_en:           1;           /*Set this bit to delay the stop bit by 1 bit.*/
+            uint32_t tx_rx_en:         1;           /*Set this bit to enable loop-back transmitter's output data signal to receiver's input data signal.*/
+            uint32_t rx_busy_tx_en:    1;           /*1: enable rs485's transmitter to send data when rs485's receiver is busy. 0:rs485's transmitter should not send data when its receiver is busy.*/
+            uint32_t rx_dly_num:       1;           /*This register is used to delay the receiver's internal data signal.*/
+            uint32_t tx_dly_num:       4;           /*This register is used to delay the transmitter's internal data signal.*/
+            uint32_t reserved10:      22;
+        };
+        uint32_t val;
+    } rs485_conf;
+    union {
+        struct {
+            uint32_t pre_idle_num:24;               /*This register is used to configure the idle duration time before the first at_cmd is received by receiver， when the the duration is less than this register value it will not take the next data received as at_cmd char.*/
+            uint32_t reserved24:   8;
+        };
+        uint32_t val;
+    } at_cmd_precnt;
+    union {
+        struct {
+            uint32_t post_idle_num:24;              /*This register is used to configure the duration time between the last at_cmd and the next data， when the duration is less than this register value  it will not take the previous data as at_cmd char.*/
+            uint32_t reserved24:    8;
+        };
+        uint32_t val;
+    } at_cmd_postcnt;
+    union {
+        struct {
+            uint32_t rx_gap_tout:24;                /*This register is used to configure the duration time between the at_cmd chars， when the duration time is less than this register value it will not take the data as continous at_cmd chars.*/
+            uint32_t reserved24:  8;
+        };
+        uint32_t val;
+    } at_cmd_gaptout;
+    union {
+        struct {
+            uint32_t data:        8;                /*This register is used to configure the content of at_cmd char.*/
+            uint32_t char_num:    8;                /*This register is used to configure the number of continuous at_cmd chars received by receiver.*/
+            uint32_t reserved16: 16;
+        };
+        uint32_t val;
+    } at_cmd_char;
+    union {
+        struct {
+            uint32_t mem_pd:             1;         /*Set this bit to power down memory，when reg_mem_pd registers in the 3 uarts are all set to 1  memory will enter low power mode.*/
+            uint32_t reserved1:          1;
+            uint32_t reserved2:          1;
+            uint32_t rx_size:            4;         /*This register is used to configure the amount of mem allocated to receiver's fifo. the default byte num is 128.*/
+            uint32_t tx_size:            4;         /*This register is used to configure the amount of mem allocated to transmitter's fifo.the default byte num is 128.*/
+            uint32_t reserved11:         4;
+            uint32_t rx_flow_thrhd_h3:   3;         /*refer to the rx_flow_thrhd's description.*/
+            uint32_t rx_tout_thrhd_h3:   3;         /*refer to the rx_tout_thrhd's description.*/
+            uint32_t xon_threshold_h2:   2;         /*refer to the uart_xon_threshold's description.*/
+            uint32_t xoff_threshold_h2:  2;         /*refer to the uart_xoff_threshold's description.*/
+            uint32_t rx_mem_full_thrhd:  3;         /*refer to the rxfifo_full_thrhd's description.*/
+            uint32_t tx_mem_empty_thrhd: 3;         /*refer to txfifo_empty_thrhd 's description.*/
+            uint32_t reserved31:         1;
+        };
+        uint32_t val;
+    } mem_conf;
+    union {
+        struct {
+            uint32_t apb_tx_waddr:11;
+            uint32_t tx_raddr:    11;
+            uint32_t reserved22:  10;
+        };
+        uint32_t val;
+    } mem_tx_status;
+    union {
+        struct {
+            uint32_t apb_rx_raddr:11;
+            uint32_t rx_waddr:    11;
+            uint32_t reserved22:  10;
+        };
+        uint32_t val;
+    } mem_rx_status;
+    union {
+        struct {
+            uint32_t rx_cnt: 3;                      /*refer to the rxfifo_cnt's description.*/
+            uint32_t tx_cnt: 3;                      /*refer to the txfifo_cnt's description.*/
+            uint32_t reserved6: 26;
+        };
+        uint32_t val;
+    } mem_cnt_status;
+    union {
+        struct {
+            uint32_t min_cnt:     20;                 /*This register stores the count of rxd pos-edge edge， it is used in baudrate-detect process.*/
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } pospulse;
+    union {
+        struct {
+            uint32_t min_cnt:     20;                 /*This register stores the count of rxd neg-edge edge， it is used in baudrate-detect process.*/
+            uint32_t reserved20:  12;
+        };
+        uint32_t val;
+    } negpulse;
+    uint32_t reserved_70;
+    uint32_t reserved_74;
+    uint32_t date;                                    /**/
+    uint32_t id;                                      /**/
+} uart_dev_t;
+extern uart_dev_t UART0;
+extern uart_dev_t UART1;
+extern uart_dev_t UART2;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_UART_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/uhci_reg.h b/components/soc/esp32s2beta/include/soc/uhci_reg.h
new file mode 100644
index 000000000..9a23fe737
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/uhci_reg.h
@@ -0,0 +1,1270 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UHCI_REG_H_
+#define _SOC_UHCI_REG_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include "soc.h"
+#define UHCI_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0x0)
+/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_UART_RX_BRK_EOF_EN  (BIT(23))
+#define UHCI_UART_RX_BRK_EOF_EN_M  (BIT(23))
+#define UHCI_UART_RX_BRK_EOF_EN_V  0x1
+#define UHCI_UART_RX_BRK_EOF_EN_S  23
+/* UHCI_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_CLK_EN  (BIT(22))
+#define UHCI_CLK_EN_M  (BIT(22))
+#define UHCI_CLK_EN_V  0x1
+#define UHCI_CLK_EN_S  22
+/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[21] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_ENCODE_CRC_EN  (BIT(21))
+#define UHCI_ENCODE_CRC_EN_M  (BIT(21))
+#define UHCI_ENCODE_CRC_EN_V  0x1
+#define UHCI_ENCODE_CRC_EN_S  21
+/* UHCI_LEN_EOF_EN : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_LEN_EOF_EN  (BIT(20))
+#define UHCI_LEN_EOF_EN_M  (BIT(20))
+#define UHCI_LEN_EOF_EN_V  0x1
+#define UHCI_LEN_EOF_EN_S  20
+/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_UART_IDLE_EOF_EN  (BIT(19))
+#define UHCI_UART_IDLE_EOF_EN_M  (BIT(19))
+#define UHCI_UART_IDLE_EOF_EN_V  0x1
+#define UHCI_UART_IDLE_EOF_EN_S  19
+/* UHCI_CRC_REC_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_CRC_REC_EN  (BIT(18))
+#define UHCI_CRC_REC_EN_M  (BIT(18))
+#define UHCI_CRC_REC_EN_V  0x1
+#define UHCI_CRC_REC_EN_S  18
+/* UHCI_HEAD_EN : R/W ;bitpos:[17] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_HEAD_EN  (BIT(17))
+#define UHCI_HEAD_EN_M  (BIT(17))
+#define UHCI_HEAD_EN_V  0x1
+#define UHCI_HEAD_EN_S  17
+/* UHCI_SEPER_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_SEPER_EN  (BIT(16))
+#define UHCI_SEPER_EN_M  (BIT(16))
+#define UHCI_SEPER_EN_V  0x1
+#define UHCI_SEPER_EN_S  16
+/* UHCI_MEM_TRANS_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_MEM_TRANS_EN  (BIT(15))
+#define UHCI_MEM_TRANS_EN_M  (BIT(15))
+#define UHCI_MEM_TRANS_EN_V  0x1
+#define UHCI_MEM_TRANS_EN_S  15
+/* UHCI_OUT_DATA_BURST_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DATA_BURST_EN  (BIT(14))
+#define UHCI_OUT_DATA_BURST_EN_M  (BIT(14))
+#define UHCI_OUT_DATA_BURST_EN_V  0x1
+#define UHCI_OUT_DATA_BURST_EN_S  14
+/* UHCI_INDSCR_BURST_EN : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_INDSCR_BURST_EN  (BIT(13))
+#define UHCI_INDSCR_BURST_EN_M  (BIT(13))
+#define UHCI_INDSCR_BURST_EN_V  0x1
+#define UHCI_INDSCR_BURST_EN_S  13
+/* UHCI_OUTDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTDSCR_BURST_EN  (BIT(12))
+#define UHCI_OUTDSCR_BURST_EN_M  (BIT(12))
+#define UHCI_OUTDSCR_BURST_EN_V  0x1
+#define UHCI_OUTDSCR_BURST_EN_S  12
+/* UHCI_UART1_CE : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_UART1_CE  (BIT(10))
+#define UHCI_UART1_CE_M  (BIT(10))
+#define UHCI_UART1_CE_V  0x1
+#define UHCI_UART1_CE_S  10
+/* UHCI_UART0_CE : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_UART0_CE  (BIT(9))
+#define UHCI_UART0_CE_M  (BIT(9))
+#define UHCI_UART0_CE_V  0x1
+#define UHCI_UART0_CE_S  9
+/* UHCI_OUT_EOF_MODE : R/W ;bitpos:[8] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_OUT_EOF_MODE  (BIT(8))
+#define UHCI_OUT_EOF_MODE_M  (BIT(8))
+#define UHCI_OUT_EOF_MODE_V  0x1
+#define UHCI_OUT_EOF_MODE_S  8
+/* UHCI_OUT_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_NO_RESTART_CLR  (BIT(7))
+#define UHCI_OUT_NO_RESTART_CLR_M  (BIT(7))
+#define UHCI_OUT_NO_RESTART_CLR_V  0x1
+#define UHCI_OUT_NO_RESTART_CLR_S  7
+/* UHCI_OUT_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_AUTO_WRBACK  (BIT(6))
+#define UHCI_OUT_AUTO_WRBACK_M  (BIT(6))
+#define UHCI_OUT_AUTO_WRBACK_V  0x1
+#define UHCI_OUT_AUTO_WRBACK_S  6
+/* UHCI_OUT_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_LOOP_TEST  (BIT(5))
+#define UHCI_OUT_LOOP_TEST_M  (BIT(5))
+#define UHCI_OUT_LOOP_TEST_V  0x1
+#define UHCI_OUT_LOOP_TEST_S  5
+/* UHCI_IN_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_LOOP_TEST  (BIT(4))
+#define UHCI_IN_LOOP_TEST_M  (BIT(4))
+#define UHCI_IN_LOOP_TEST_V  0x1
+#define UHCI_IN_LOOP_TEST_S  4
+/* UHCI_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_AHBM_RST  (BIT(3))
+#define UHCI_AHBM_RST_M  (BIT(3))
+#define UHCI_AHBM_RST_V  0x1
+#define UHCI_AHBM_RST_S  3
+/* UHCI_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_AHBM_FIFO_RST  (BIT(2))
+#define UHCI_AHBM_FIFO_RST_M  (BIT(2))
+#define UHCI_AHBM_FIFO_RST_V  0x1
+#define UHCI_AHBM_FIFO_RST_S  2
+/* UHCI_OUT_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_RST  (BIT(1))
+#define UHCI_OUT_RST_M  (BIT(1))
+#define UHCI_OUT_RST_V  0x1
+#define UHCI_OUT_RST_S  1
+/* UHCI_IN_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */
+/*description: */
+#define UHCI_IN_RST  (BIT(0))
+#define UHCI_IN_RST_M  (BIT(0))
+#define UHCI_IN_RST_V  0x1
+#define UHCI_IN_RST_S  0
+
+#define UHCI_INT_RAW_REG(i)          (REG_UHCI_BASE(i) + 0x4)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_M  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_V  0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_RAW_S  16
+/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_A_Q_INT_RAW  (BIT(15))
+#define UHCI_SEND_A_Q_INT_RAW_M  (BIT(15))
+#define UHCI_SEND_A_Q_INT_RAW_V  0x1
+#define UHCI_SEND_A_Q_INT_RAW_S  15
+/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_S_Q_INT_RAW  (BIT(14))
+#define UHCI_SEND_S_Q_INT_RAW_M  (BIT(14))
+#define UHCI_SEND_S_Q_INT_RAW_V  0x1
+#define UHCI_SEND_S_Q_INT_RAW_S  14
+/* UHCI_OUT_TOTAL_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_TOTAL_EOF_INT_RAW  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_RAW_M  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_RAW_V  0x1
+#define UHCI_OUT_TOTAL_EOF_INT_RAW_S  13
+/* UHCI_OUTLINK_EOF_ERR_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_M  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_RAW_S  12
+/* UHCI_IN_DSCR_EMPTY_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_EMPTY_INT_RAW  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_RAW_M  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_RAW_V  0x1
+#define UHCI_IN_DSCR_EMPTY_INT_RAW_S  11
+/* UHCI_OUT_DSCR_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_ERR_INT_RAW  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_RAW_M  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_RAW_V  0x1
+#define UHCI_OUT_DSCR_ERR_INT_RAW_S  10
+/* UHCI_IN_DSCR_ERR_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_ERR_INT_RAW  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_RAW_M  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_RAW_V  0x1
+#define UHCI_IN_DSCR_ERR_INT_RAW_S  9
+/* UHCI_OUT_EOF_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_EOF_INT_RAW  (BIT(8))
+#define UHCI_OUT_EOF_INT_RAW_M  (BIT(8))
+#define UHCI_OUT_EOF_INT_RAW_V  0x1
+#define UHCI_OUT_EOF_INT_RAW_S  8
+/* UHCI_OUT_DONE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DONE_INT_RAW  (BIT(7))
+#define UHCI_OUT_DONE_INT_RAW_M  (BIT(7))
+#define UHCI_OUT_DONE_INT_RAW_V  0x1
+#define UHCI_OUT_DONE_INT_RAW_S  7
+/* UHCI_IN_ERR_EOF_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_INT_RAW  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_RAW_M  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_RAW_V  0x1
+#define UHCI_IN_ERR_EOF_INT_RAW_S  6
+/* UHCI_IN_SUC_EOF_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_INT_RAW  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_RAW_M  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_RAW_V  0x1
+#define UHCI_IN_SUC_EOF_INT_RAW_S  5
+/* UHCI_IN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DONE_INT_RAW  (BIT(4))
+#define UHCI_IN_DONE_INT_RAW_M  (BIT(4))
+#define UHCI_IN_DONE_INT_RAW_V  0x1
+#define UHCI_IN_DONE_INT_RAW_S  4
+/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_HUNG_INT_RAW  (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_RAW_V  0x1
+#define UHCI_TX_HUNG_INT_RAW_S  3
+/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_HUNG_INT_RAW  (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_RAW_V  0x1
+#define UHCI_RX_HUNG_INT_RAW_S  2
+/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_START_INT_RAW  (BIT(1))
+#define UHCI_TX_START_INT_RAW_M  (BIT(1))
+#define UHCI_TX_START_INT_RAW_V  0x1
+#define UHCI_TX_START_INT_RAW_S  1
+/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_START_INT_RAW  (BIT(0))
+#define UHCI_RX_START_INT_RAW_M  (BIT(0))
+#define UHCI_RX_START_INT_RAW_V  0x1
+#define UHCI_RX_START_INT_RAW_S  0
+
+#define UHCI_INT_ST_REG(i)          (REG_UHCI_BASE(i) + 0x8)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_M  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_V  0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ST_S  16
+/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_A_Q_INT_ST  (BIT(15))
+#define UHCI_SEND_A_Q_INT_ST_M  (BIT(15))
+#define UHCI_SEND_A_Q_INT_ST_V  0x1
+#define UHCI_SEND_A_Q_INT_ST_S  15
+/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_S_Q_INT_ST  (BIT(14))
+#define UHCI_SEND_S_Q_INT_ST_M  (BIT(14))
+#define UHCI_SEND_S_Q_INT_ST_V  0x1
+#define UHCI_SEND_S_Q_INT_ST_S  14
+/* UHCI_OUT_TOTAL_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_TOTAL_EOF_INT_ST  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ST_M  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ST_V  0x1
+#define UHCI_OUT_TOTAL_EOF_INT_ST_S  13
+/* UHCI_OUTLINK_EOF_ERR_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_EOF_ERR_INT_ST  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_M  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ST_S  12
+/* UHCI_IN_DSCR_EMPTY_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_EMPTY_INT_ST  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ST_M  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ST_V  0x1
+#define UHCI_IN_DSCR_EMPTY_INT_ST_S  11
+/* UHCI_OUT_DSCR_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_ERR_INT_ST  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ST_M  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ST_V  0x1
+#define UHCI_OUT_DSCR_ERR_INT_ST_S  10
+/* UHCI_IN_DSCR_ERR_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_ERR_INT_ST  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ST_M  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ST_V  0x1
+#define UHCI_IN_DSCR_ERR_INT_ST_S  9
+/* UHCI_OUT_EOF_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_EOF_INT_ST  (BIT(8))
+#define UHCI_OUT_EOF_INT_ST_M  (BIT(8))
+#define UHCI_OUT_EOF_INT_ST_V  0x1
+#define UHCI_OUT_EOF_INT_ST_S  8
+/* UHCI_OUT_DONE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DONE_INT_ST  (BIT(7))
+#define UHCI_OUT_DONE_INT_ST_M  (BIT(7))
+#define UHCI_OUT_DONE_INT_ST_V  0x1
+#define UHCI_OUT_DONE_INT_ST_S  7
+/* UHCI_IN_ERR_EOF_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_INT_ST  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ST_M  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ST_V  0x1
+#define UHCI_IN_ERR_EOF_INT_ST_S  6
+/* UHCI_IN_SUC_EOF_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_INT_ST  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ST_M  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ST_V  0x1
+#define UHCI_IN_SUC_EOF_INT_ST_S  5
+/* UHCI_IN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DONE_INT_ST  (BIT(4))
+#define UHCI_IN_DONE_INT_ST_M  (BIT(4))
+#define UHCI_IN_DONE_INT_ST_V  0x1
+#define UHCI_IN_DONE_INT_ST_S  4
+/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_HUNG_INT_ST  (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ST_V  0x1
+#define UHCI_TX_HUNG_INT_ST_S  3
+/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_HUNG_INT_ST  (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ST_V  0x1
+#define UHCI_RX_HUNG_INT_ST_S  2
+/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_START_INT_ST  (BIT(1))
+#define UHCI_TX_START_INT_ST_M  (BIT(1))
+#define UHCI_TX_START_INT_ST_V  0x1
+#define UHCI_TX_START_INT_ST_S  1
+/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_START_INT_ST  (BIT(0))
+#define UHCI_RX_START_INT_ST_M  (BIT(0))
+#define UHCI_RX_START_INT_ST_V  0x1
+#define UHCI_RX_START_INT_ST_S  0
+
+#define UHCI_INT_ENA_REG(i)          (REG_UHCI_BASE(i) + 0xC)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_M  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_V  0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_ENA_S  16
+/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_A_Q_INT_ENA  (BIT(15))
+#define UHCI_SEND_A_Q_INT_ENA_M  (BIT(15))
+#define UHCI_SEND_A_Q_INT_ENA_V  0x1
+#define UHCI_SEND_A_Q_INT_ENA_S  15
+/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_S_Q_INT_ENA  (BIT(14))
+#define UHCI_SEND_S_Q_INT_ENA_M  (BIT(14))
+#define UHCI_SEND_S_Q_INT_ENA_V  0x1
+#define UHCI_SEND_S_Q_INT_ENA_S  14
+/* UHCI_OUT_TOTAL_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_TOTAL_EOF_INT_ENA  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ENA_M  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_ENA_V  0x1
+#define UHCI_OUT_TOTAL_EOF_INT_ENA_S  13
+/* UHCI_OUTLINK_EOF_ERR_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_M  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_ENA_S  12
+/* UHCI_IN_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_EMPTY_INT_ENA  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ENA_M  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_ENA_V  0x1
+#define UHCI_IN_DSCR_EMPTY_INT_ENA_S  11
+/* UHCI_OUT_DSCR_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_ERR_INT_ENA  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ENA_M  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_ENA_V  0x1
+#define UHCI_OUT_DSCR_ERR_INT_ENA_S  10
+/* UHCI_IN_DSCR_ERR_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_ERR_INT_ENA  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ENA_M  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_ENA_V  0x1
+#define UHCI_IN_DSCR_ERR_INT_ENA_S  9
+/* UHCI_OUT_EOF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_EOF_INT_ENA  (BIT(8))
+#define UHCI_OUT_EOF_INT_ENA_M  (BIT(8))
+#define UHCI_OUT_EOF_INT_ENA_V  0x1
+#define UHCI_OUT_EOF_INT_ENA_S  8
+/* UHCI_OUT_DONE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DONE_INT_ENA  (BIT(7))
+#define UHCI_OUT_DONE_INT_ENA_M  (BIT(7))
+#define UHCI_OUT_DONE_INT_ENA_V  0x1
+#define UHCI_OUT_DONE_INT_ENA_S  7
+/* UHCI_IN_ERR_EOF_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_INT_ENA  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ENA_M  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_ENA_V  0x1
+#define UHCI_IN_ERR_EOF_INT_ENA_S  6
+/* UHCI_IN_SUC_EOF_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_INT_ENA  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ENA_M  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_ENA_V  0x1
+#define UHCI_IN_SUC_EOF_INT_ENA_S  5
+/* UHCI_IN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DONE_INT_ENA  (BIT(4))
+#define UHCI_IN_DONE_INT_ENA_M  (BIT(4))
+#define UHCI_IN_DONE_INT_ENA_V  0x1
+#define UHCI_IN_DONE_INT_ENA_S  4
+/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_HUNG_INT_ENA  (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_ENA_V  0x1
+#define UHCI_TX_HUNG_INT_ENA_S  3
+/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_HUNG_INT_ENA  (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_ENA_V  0x1
+#define UHCI_RX_HUNG_INT_ENA_S  2
+/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_START_INT_ENA  (BIT(1))
+#define UHCI_TX_START_INT_ENA_M  (BIT(1))
+#define UHCI_TX_START_INT_ENA_V  0x1
+#define UHCI_TX_START_INT_ENA_S  1
+/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_START_INT_ENA  (BIT(0))
+#define UHCI_RX_START_INT_ENA_M  (BIT(0))
+#define UHCI_RX_START_INT_ENA_V  0x1
+#define UHCI_RX_START_INT_ENA_S  0
+
+#define UHCI_INT_CLR_REG(i)          (REG_UHCI_BASE(i) + 0x10)
+/* UHCI_DMA_INFIFO_FULL_WM_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_M  (BIT(16))
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_V  0x1
+#define UHCI_DMA_INFIFO_FULL_WM_INT_CLR_S  16
+/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_A_Q_INT_CLR  (BIT(15))
+#define UHCI_SEND_A_Q_INT_CLR_M  (BIT(15))
+#define UHCI_SEND_A_Q_INT_CLR_V  0x1
+#define UHCI_SEND_A_Q_INT_CLR_S  15
+/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SEND_S_Q_INT_CLR  (BIT(14))
+#define UHCI_SEND_S_Q_INT_CLR_M  (BIT(14))
+#define UHCI_SEND_S_Q_INT_CLR_V  0x1
+#define UHCI_SEND_S_Q_INT_CLR_S  14
+/* UHCI_OUT_TOTAL_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_TOTAL_EOF_INT_CLR  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_CLR_M  (BIT(13))
+#define UHCI_OUT_TOTAL_EOF_INT_CLR_V  0x1
+#define UHCI_OUT_TOTAL_EOF_INT_CLR_S  13
+/* UHCI_OUTLINK_EOF_ERR_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_M  (BIT(12))
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_V  0x1
+#define UHCI_OUTLINK_EOF_ERR_INT_CLR_S  12
+/* UHCI_IN_DSCR_EMPTY_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_EMPTY_INT_CLR  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_CLR_M  (BIT(11))
+#define UHCI_IN_DSCR_EMPTY_INT_CLR_V  0x1
+#define UHCI_IN_DSCR_EMPTY_INT_CLR_S  11
+/* UHCI_OUT_DSCR_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_ERR_INT_CLR  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_CLR_M  (BIT(10))
+#define UHCI_OUT_DSCR_ERR_INT_CLR_V  0x1
+#define UHCI_OUT_DSCR_ERR_INT_CLR_S  10
+/* UHCI_IN_DSCR_ERR_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_ERR_INT_CLR  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_CLR_M  (BIT(9))
+#define UHCI_IN_DSCR_ERR_INT_CLR_V  0x1
+#define UHCI_IN_DSCR_ERR_INT_CLR_S  9
+/* UHCI_OUT_EOF_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_EOF_INT_CLR  (BIT(8))
+#define UHCI_OUT_EOF_INT_CLR_M  (BIT(8))
+#define UHCI_OUT_EOF_INT_CLR_V  0x1
+#define UHCI_OUT_EOF_INT_CLR_S  8
+/* UHCI_OUT_DONE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_DONE_INT_CLR  (BIT(7))
+#define UHCI_OUT_DONE_INT_CLR_M  (BIT(7))
+#define UHCI_OUT_DONE_INT_CLR_V  0x1
+#define UHCI_OUT_DONE_INT_CLR_S  7
+/* UHCI_IN_ERR_EOF_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_INT_CLR  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_CLR_M  (BIT(6))
+#define UHCI_IN_ERR_EOF_INT_CLR_V  0x1
+#define UHCI_IN_ERR_EOF_INT_CLR_S  6
+/* UHCI_IN_SUC_EOF_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_INT_CLR  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_CLR_M  (BIT(5))
+#define UHCI_IN_SUC_EOF_INT_CLR_V  0x1
+#define UHCI_IN_SUC_EOF_INT_CLR_S  5
+/* UHCI_IN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_DONE_INT_CLR  (BIT(4))
+#define UHCI_IN_DONE_INT_CLR_M  (BIT(4))
+#define UHCI_IN_DONE_INT_CLR_V  0x1
+#define UHCI_IN_DONE_INT_CLR_S  4
+/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_HUNG_INT_CLR  (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_M  (BIT(3))
+#define UHCI_TX_HUNG_INT_CLR_V  0x1
+#define UHCI_TX_HUNG_INT_CLR_S  3
+/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_HUNG_INT_CLR  (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_M  (BIT(2))
+#define UHCI_RX_HUNG_INT_CLR_V  0x1
+#define UHCI_RX_HUNG_INT_CLR_S  2
+/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_START_INT_CLR  (BIT(1))
+#define UHCI_TX_START_INT_CLR_M  (BIT(1))
+#define UHCI_TX_START_INT_CLR_V  0x1
+#define UHCI_TX_START_INT_CLR_S  1
+/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_START_INT_CLR  (BIT(0))
+#define UHCI_RX_START_INT_CLR_M  (BIT(0))
+#define UHCI_RX_START_INT_CLR_V  0x1
+#define UHCI_RX_START_INT_CLR_S  0
+
+#define UHCI_DMA_OUT_STATUS_REG(i)          (REG_UHCI_BASE(i) + 0x14)
+/* UHCI_OUT_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_OUT_EMPTY  (BIT(1))
+#define UHCI_OUT_EMPTY_M  (BIT(1))
+#define UHCI_OUT_EMPTY_V  0x1
+#define UHCI_OUT_EMPTY_S  1
+/* UHCI_OUT_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUT_FULL  (BIT(0))
+#define UHCI_OUT_FULL_M  (BIT(0))
+#define UHCI_OUT_FULL_V  0x1
+#define UHCI_OUT_FULL_S  0
+
+#define UHCI_DMA_OUT_PUSH_REG(i)          (REG_UHCI_BASE(i) + 0x18)
+/* UHCI_OUTFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define UHCI_OUTFIFO_PUSH  (BIT(16))
+#define UHCI_OUTFIFO_PUSH_M  (BIT(16))
+#define UHCI_OUTFIFO_PUSH_V  0x1
+#define UHCI_OUTFIFO_PUSH_S  16
+/* UHCI_OUTFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
+/*description: */
+#define UHCI_OUTFIFO_WDATA  0x000001FF
+#define UHCI_OUTFIFO_WDATA_M  ((UHCI_OUTFIFO_WDATA_V)<<(UHCI_OUTFIFO_WDATA_S))
+#define UHCI_OUTFIFO_WDATA_V  0x1FF
+#define UHCI_OUTFIFO_WDATA_S  0
+
+#define UHCI_DMA_IN_STATUS_REG(i)          (REG_UHCI_BASE(i) + 0x1C)
+/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: */
+#define UHCI_RX_ERR_CAUSE  0x00000007
+#define UHCI_RX_ERR_CAUSE_M  ((UHCI_RX_ERR_CAUSE_V)<<(UHCI_RX_ERR_CAUSE_S))
+#define UHCI_RX_ERR_CAUSE_V  0x7
+#define UHCI_RX_ERR_CAUSE_S  4
+/* UHCI_IN_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_IN_EMPTY  (BIT(1))
+#define UHCI_IN_EMPTY_M  (BIT(1))
+#define UHCI_IN_EMPTY_V  0x1
+#define UHCI_IN_EMPTY_S  1
+/* UHCI_IN_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_IN_FULL  (BIT(0))
+#define UHCI_IN_FULL_M  (BIT(0))
+#define UHCI_IN_FULL_V  0x1
+#define UHCI_IN_FULL_S  0
+
+#define UHCI_DMA_IN_POP_REG(i)          (REG_UHCI_BASE(i) + 0x20)
+/* UHCI_INFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */
+/*description: */
+#define UHCI_INFIFO_POP  (BIT(16))
+#define UHCI_INFIFO_POP_M  (BIT(16))
+#define UHCI_INFIFO_POP_V  0x1
+#define UHCI_INFIFO_POP_S  16
+/* UHCI_INFIFO_RDATA : RO ;bitpos:[11:0] ;default: 12'h0 ; */
+/*description: */
+#define UHCI_INFIFO_RDATA  0x00000FFF
+#define UHCI_INFIFO_RDATA_M  ((UHCI_INFIFO_RDATA_V)<<(UHCI_INFIFO_RDATA_S))
+#define UHCI_INFIFO_RDATA_V  0xFFF
+#define UHCI_INFIFO_RDATA_S  0
+
+#define UHCI_DMA_OUT_LINK_REG(i)          (REG_UHCI_BASE(i) + 0x24)
+/* UHCI_OUTLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define UHCI_OUTLINK_PARK  (BIT(31))
+#define UHCI_OUTLINK_PARK_M  (BIT(31))
+#define UHCI_OUTLINK_PARK_V  0x1
+#define UHCI_OUTLINK_PARK_S  31
+/* UHCI_OUTLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_RESTART  (BIT(30))
+#define UHCI_OUTLINK_RESTART_M  (BIT(30))
+#define UHCI_OUTLINK_RESTART_V  0x1
+#define UHCI_OUTLINK_RESTART_S  30
+/* UHCI_OUTLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_START  (BIT(29))
+#define UHCI_OUTLINK_START_M  (BIT(29))
+#define UHCI_OUTLINK_START_V  0x1
+#define UHCI_OUTLINK_START_S  29
+/* UHCI_OUTLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_STOP  (BIT(28))
+#define UHCI_OUTLINK_STOP_M  (BIT(28))
+#define UHCI_OUTLINK_STOP_V  0x1
+#define UHCI_OUTLINK_STOP_S  28
+/* UHCI_OUTLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define UHCI_OUTLINK_ADDR  0x000FFFFF
+#define UHCI_OUTLINK_ADDR_M  ((UHCI_OUTLINK_ADDR_V)<<(UHCI_OUTLINK_ADDR_S))
+#define UHCI_OUTLINK_ADDR_V  0xFFFFF
+#define UHCI_OUTLINK_ADDR_S  0
+
+#define UHCI_DMA_IN_LINK_REG(i)          (REG_UHCI_BASE(i) + 0x28)
+/* UHCI_INLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */
+/*description: */
+#define UHCI_INLINK_PARK  (BIT(31))
+#define UHCI_INLINK_PARK_M  (BIT(31))
+#define UHCI_INLINK_PARK_V  0x1
+#define UHCI_INLINK_PARK_S  31
+/* UHCI_INLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_INLINK_RESTART  (BIT(30))
+#define UHCI_INLINK_RESTART_M  (BIT(30))
+#define UHCI_INLINK_RESTART_V  0x1
+#define UHCI_INLINK_RESTART_S  30
+/* UHCI_INLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_INLINK_START  (BIT(29))
+#define UHCI_INLINK_START_M  (BIT(29))
+#define UHCI_INLINK_START_V  0x1
+#define UHCI_INLINK_START_S  29
+/* UHCI_INLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_INLINK_STOP  (BIT(28))
+#define UHCI_INLINK_STOP_M  (BIT(28))
+#define UHCI_INLINK_STOP_V  0x1
+#define UHCI_INLINK_STOP_S  28
+/* UHCI_INLINK_AUTO_RET : R/W ;bitpos:[20] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_INLINK_AUTO_RET  (BIT(20))
+#define UHCI_INLINK_AUTO_RET_M  (BIT(20))
+#define UHCI_INLINK_AUTO_RET_V  0x1
+#define UHCI_INLINK_AUTO_RET_S  20
+/* UHCI_INLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */
+/*description: */
+#define UHCI_INLINK_ADDR  0x000FFFFF
+#define UHCI_INLINK_ADDR_M  ((UHCI_INLINK_ADDR_V)<<(UHCI_INLINK_ADDR_S))
+#define UHCI_INLINK_ADDR_V  0xFFFFF
+#define UHCI_INLINK_ADDR_S  0
+
+#define UHCI_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0x2C)
+/* UHCI_DMA_INFIFO_FULL_THRS : R/W ;bitpos:[20:9] ;default: 12'b0 ; */
+/*description: */
+#define UHCI_DMA_INFIFO_FULL_THRS  0x00000FFF
+#define UHCI_DMA_INFIFO_FULL_THRS_M  ((UHCI_DMA_INFIFO_FULL_THRS_V)<<(UHCI_DMA_INFIFO_FULL_THRS_S))
+#define UHCI_DMA_INFIFO_FULL_THRS_V  0xFFF
+#define UHCI_DMA_INFIFO_FULL_THRS_S  9
+/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SW_START  (BIT(8))
+#define UHCI_SW_START_M  (BIT(8))
+#define UHCI_SW_START_V  0x1
+#define UHCI_SW_START_S  8
+/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_WAIT_SW_START  (BIT(7))
+#define UHCI_WAIT_SW_START_M  (BIT(7))
+#define UHCI_WAIT_SW_START_V  0x1
+#define UHCI_WAIT_SW_START_S  7
+/* UHCI_CHECK_OWNER : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_CHECK_OWNER  (BIT(6))
+#define UHCI_CHECK_OWNER_M  (BIT(6))
+#define UHCI_CHECK_OWNER_V  0x1
+#define UHCI_CHECK_OWNER_S  6
+/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_TX_ACK_NUM_RE  (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_M  (BIT(5))
+#define UHCI_TX_ACK_NUM_RE_V  0x1
+#define UHCI_TX_ACK_NUM_RE_S  5
+/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_TX_CHECK_SUM_RE  (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_M  (BIT(4))
+#define UHCI_TX_CHECK_SUM_RE_V  0x1
+#define UHCI_TX_CHECK_SUM_RE_S  4
+/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SAVE_HEAD  (BIT(3))
+#define UHCI_SAVE_HEAD_M  (BIT(3))
+#define UHCI_SAVE_HEAD_V  0x1
+#define UHCI_SAVE_HEAD_S  3
+/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_CRC_DISABLE  (BIT(2))
+#define UHCI_CRC_DISABLE_M  (BIT(2))
+#define UHCI_CRC_DISABLE_V  0x1
+#define UHCI_CRC_DISABLE_S  2
+/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_CHECK_SEQ_EN  (BIT(1))
+#define UHCI_CHECK_SEQ_EN_M  (BIT(1))
+#define UHCI_CHECK_SEQ_EN_V  0x1
+#define UHCI_CHECK_SEQ_EN_S  1
+/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_CHECK_SUM_EN  (BIT(0))
+#define UHCI_CHECK_SUM_EN_M  (BIT(0))
+#define UHCI_CHECK_SUM_EN_V  0x1
+#define UHCI_CHECK_SUM_EN_S  0
+
+#define UHCI_STATE0_REG(i)          (REG_UHCI_BASE(i) + 0x30)
+/* UHCI_DECODE_STATE : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: */
+#define UHCI_DECODE_STATE  0x00000007
+#define UHCI_DECODE_STATE_M  ((UHCI_DECODE_STATE_V)<<(UHCI_DECODE_STATE_S))
+#define UHCI_DECODE_STATE_V  0x7
+#define UHCI_DECODE_STATE_S  28
+/* UHCI_INFIFO_CNT_DEBUG : RO ;bitpos:[27:23] ;default: 5'b0 ; */
+/*description: */
+#define UHCI_INFIFO_CNT_DEBUG  0x0000001F
+#define UHCI_INFIFO_CNT_DEBUG_M  ((UHCI_INFIFO_CNT_DEBUG_V)<<(UHCI_INFIFO_CNT_DEBUG_S))
+#define UHCI_INFIFO_CNT_DEBUG_V  0x1F
+#define UHCI_INFIFO_CNT_DEBUG_S  23
+/* UHCI_IN_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define UHCI_IN_STATE  0x00000007
+#define UHCI_IN_STATE_M  ((UHCI_IN_STATE_V)<<(UHCI_IN_STATE_S))
+#define UHCI_IN_STATE_V  0x7
+#define UHCI_IN_STATE_S  20
+/* UHCI_IN_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: */
+#define UHCI_IN_DSCR_STATE  0x00000003
+#define UHCI_IN_DSCR_STATE_M  ((UHCI_IN_DSCR_STATE_V)<<(UHCI_IN_DSCR_STATE_S))
+#define UHCI_IN_DSCR_STATE_V  0x3
+#define UHCI_IN_DSCR_STATE_S  18
+/* UHCI_INLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: */
+#define UHCI_INLINK_DSCR_ADDR  0x0003FFFF
+#define UHCI_INLINK_DSCR_ADDR_M  ((UHCI_INLINK_DSCR_ADDR_V)<<(UHCI_INLINK_DSCR_ADDR_S))
+#define UHCI_INLINK_DSCR_ADDR_V  0x3FFFF
+#define UHCI_INLINK_DSCR_ADDR_S  0
+
+#define UHCI_STATE1_REG(i)          (REG_UHCI_BASE(i) + 0x34)
+/* UHCI_ENCODE_STATE : RO ;bitpos:[30:28] ;default: 3'b0 ; */
+/*description: */
+#define UHCI_ENCODE_STATE  0x00000007
+#define UHCI_ENCODE_STATE_M  ((UHCI_ENCODE_STATE_V)<<(UHCI_ENCODE_STATE_S))
+#define UHCI_ENCODE_STATE_V  0x7
+#define UHCI_ENCODE_STATE_S  28
+/* UHCI_OUTFIFO_CNT : RO ;bitpos:[27:23] ;default: 5'b0 ; */
+/*description: */
+#define UHCI_OUTFIFO_CNT  0x0000001F
+#define UHCI_OUTFIFO_CNT_M  ((UHCI_OUTFIFO_CNT_V)<<(UHCI_OUTFIFO_CNT_S))
+#define UHCI_OUTFIFO_CNT_V  0x1F
+#define UHCI_OUTFIFO_CNT_S  23
+/* UHCI_OUT_STATE : RO ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define UHCI_OUT_STATE  0x00000007
+#define UHCI_OUT_STATE_M  ((UHCI_OUT_STATE_V)<<(UHCI_OUT_STATE_S))
+#define UHCI_OUT_STATE_V  0x7
+#define UHCI_OUT_STATE_S  20
+/* UHCI_OUT_DSCR_STATE : RO ;bitpos:[19:18] ;default: 2'b0 ; */
+/*description: */
+#define UHCI_OUT_DSCR_STATE  0x00000003
+#define UHCI_OUT_DSCR_STATE_M  ((UHCI_OUT_DSCR_STATE_V)<<(UHCI_OUT_DSCR_STATE_S))
+#define UHCI_OUT_DSCR_STATE_V  0x3
+#define UHCI_OUT_DSCR_STATE_S  18
+/* UHCI_OUTLINK_DSCR_ADDR : RO ;bitpos:[17:0] ;default: 18'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_DSCR_ADDR  0x0003FFFF
+#define UHCI_OUTLINK_DSCR_ADDR_M  ((UHCI_OUTLINK_DSCR_ADDR_V)<<(UHCI_OUTLINK_DSCR_ADDR_S))
+#define UHCI_OUTLINK_DSCR_ADDR_V  0x3FFFF
+#define UHCI_OUTLINK_DSCR_ADDR_S  0
+
+#define UHCI_DMA_OUT_EOF_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x38)
+/* UHCI_OUT_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_OUT_EOF_DES_ADDR  0xFFFFFFFF
+#define UHCI_OUT_EOF_DES_ADDR_M  ((UHCI_OUT_EOF_DES_ADDR_V)<<(UHCI_OUT_EOF_DES_ADDR_S))
+#define UHCI_OUT_EOF_DES_ADDR_V  0xFFFFFFFF
+#define UHCI_OUT_EOF_DES_ADDR_S  0
+
+#define UHCI_DMA_IN_SUC_EOF_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x3C)
+/* UHCI_IN_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_IN_SUC_EOF_DES_ADDR  0xFFFFFFFF
+#define UHCI_IN_SUC_EOF_DES_ADDR_M  ((UHCI_IN_SUC_EOF_DES_ADDR_V)<<(UHCI_IN_SUC_EOF_DES_ADDR_S))
+#define UHCI_IN_SUC_EOF_DES_ADDR_V  0xFFFFFFFF
+#define UHCI_IN_SUC_EOF_DES_ADDR_S  0
+
+#define UHCI_DMA_IN_ERR_EOF_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x40)
+/* UHCI_IN_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_IN_ERR_EOF_DES_ADDR  0xFFFFFFFF
+#define UHCI_IN_ERR_EOF_DES_ADDR_M  ((UHCI_IN_ERR_EOF_DES_ADDR_V)<<(UHCI_IN_ERR_EOF_DES_ADDR_S))
+#define UHCI_IN_ERR_EOF_DES_ADDR_V  0xFFFFFFFF
+#define UHCI_IN_ERR_EOF_DES_ADDR_S  0
+
+#define UHCI_DMA_OUT_EOF_BFR_DES_ADDR_REG(i)          (REG_UHCI_BASE(i) + 0x44)
+/* UHCI_OUT_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_OUT_EOF_BFR_DES_ADDR  0xFFFFFFFF
+#define UHCI_OUT_EOF_BFR_DES_ADDR_M  ((UHCI_OUT_EOF_BFR_DES_ADDR_V)<<(UHCI_OUT_EOF_BFR_DES_ADDR_S))
+#define UHCI_OUT_EOF_BFR_DES_ADDR_V  0xFFFFFFFF
+#define UHCI_OUT_EOF_BFR_DES_ADDR_S  0
+
+#define UHCI_AHB_TEST_REG(i)          (REG_UHCI_BASE(i) + 0x48)
+/* UHCI_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */
+/*description: */
+#define UHCI_AHB_TESTADDR  0x00000003
+#define UHCI_AHB_TESTADDR_M  ((UHCI_AHB_TESTADDR_V)<<(UHCI_AHB_TESTADDR_S))
+#define UHCI_AHB_TESTADDR_V  0x3
+#define UHCI_AHB_TESTADDR_S  4
+/* UHCI_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */
+/*description: */
+#define UHCI_AHB_TESTMODE  0x00000007
+#define UHCI_AHB_TESTMODE_M  ((UHCI_AHB_TESTMODE_V)<<(UHCI_AHB_TESTMODE_S))
+#define UHCI_AHB_TESTMODE_V  0x7
+#define UHCI_AHB_TESTMODE_S  0
+
+#define UHCI_DMA_IN_DSCR_REG(i)          (REG_UHCI_BASE(i) + 0x4C)
+/* UHCI_INLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define UHCI_INLINK_DSCR  0xFFFFFFFF
+#define UHCI_INLINK_DSCR_M  ((UHCI_INLINK_DSCR_V)<<(UHCI_INLINK_DSCR_S))
+#define UHCI_INLINK_DSCR_V  0xFFFFFFFF
+#define UHCI_INLINK_DSCR_S  0
+
+#define UHCI_DMA_IN_DSCR_BF0_REG(i)          (REG_UHCI_BASE(i) + 0x50)
+/* UHCI_INLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define UHCI_INLINK_DSCR_BF0  0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF0_M  ((UHCI_INLINK_DSCR_BF0_V)<<(UHCI_INLINK_DSCR_BF0_S))
+#define UHCI_INLINK_DSCR_BF0_V  0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF0_S  0
+
+#define UHCI_DMA_IN_DSCR_BF1_REG(i)          (REG_UHCI_BASE(i) + 0x54)
+/* UHCI_INLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define UHCI_INLINK_DSCR_BF1  0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF1_M  ((UHCI_INLINK_DSCR_BF1_V)<<(UHCI_INLINK_DSCR_BF1_S))
+#define UHCI_INLINK_DSCR_BF1_V  0xFFFFFFFF
+#define UHCI_INLINK_DSCR_BF1_S  0
+
+#define UHCI_DMA_OUT_DSCR_REG(i)          (REG_UHCI_BASE(i) + 0x58)
+/* UHCI_OUTLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_DSCR  0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_M  ((UHCI_OUTLINK_DSCR_V)<<(UHCI_OUTLINK_DSCR_S))
+#define UHCI_OUTLINK_DSCR_V  0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_S  0
+
+#define UHCI_DMA_OUT_DSCR_BF0_REG(i)          (REG_UHCI_BASE(i) + 0x5C)
+/* UHCI_OUTLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_DSCR_BF0  0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF0_M  ((UHCI_OUTLINK_DSCR_BF0_V)<<(UHCI_OUTLINK_DSCR_BF0_S))
+#define UHCI_OUTLINK_DSCR_BF0_V  0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF0_S  0
+
+#define UHCI_DMA_OUT_DSCR_BF1_REG(i)          (REG_UHCI_BASE(i) + 0x60)
+/* UHCI_OUTLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */
+/*description: */
+#define UHCI_OUTLINK_DSCR_BF1  0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF1_M  ((UHCI_OUTLINK_DSCR_BF1_V)<<(UHCI_OUTLINK_DSCR_BF1_S))
+#define UHCI_OUTLINK_DSCR_BF1_V  0xFFFFFFFF
+#define UHCI_OUTLINK_DSCR_BF1_S  0
+
+#define UHCI_ESCAPE_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x64)
+/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_13_ESC_EN  (BIT(7))
+#define UHCI_RX_13_ESC_EN_M  (BIT(7))
+#define UHCI_RX_13_ESC_EN_V  0x1
+#define UHCI_RX_13_ESC_EN_S  7
+/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_RX_11_ESC_EN  (BIT(6))
+#define UHCI_RX_11_ESC_EN_M  (BIT(6))
+#define UHCI_RX_11_ESC_EN_V  0x1
+#define UHCI_RX_11_ESC_EN_S  6
+/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_RX_DB_ESC_EN  (BIT(5))
+#define UHCI_RX_DB_ESC_EN_M  (BIT(5))
+#define UHCI_RX_DB_ESC_EN_V  0x1
+#define UHCI_RX_DB_ESC_EN_S  5
+/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_RX_C0_ESC_EN  (BIT(4))
+#define UHCI_RX_C0_ESC_EN_M  (BIT(4))
+#define UHCI_RX_C0_ESC_EN_V  0x1
+#define UHCI_RX_C0_ESC_EN_S  4
+/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_13_ESC_EN  (BIT(3))
+#define UHCI_TX_13_ESC_EN_M  (BIT(3))
+#define UHCI_TX_13_ESC_EN_V  0x1
+#define UHCI_TX_13_ESC_EN_S  3
+/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_TX_11_ESC_EN  (BIT(2))
+#define UHCI_TX_11_ESC_EN_M  (BIT(2))
+#define UHCI_TX_11_ESC_EN_V  0x1
+#define UHCI_TX_11_ESC_EN_S  2
+/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_TX_DB_ESC_EN  (BIT(1))
+#define UHCI_TX_DB_ESC_EN_M  (BIT(1))
+#define UHCI_TX_DB_ESC_EN_V  0x1
+#define UHCI_TX_DB_ESC_EN_S  1
+/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_TX_C0_ESC_EN  (BIT(0))
+#define UHCI_TX_C0_ESC_EN_M  (BIT(0))
+#define UHCI_TX_C0_ESC_EN_V  0x1
+#define UHCI_TX_C0_ESC_EN_S  0
+
+#define UHCI_HUNG_CONF_REG(i)          (REG_UHCI_BASE(i) + 0x68)
+/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_RXFIFO_TIMEOUT_ENA  (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_M  (BIT(23))
+#define UHCI_RXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_RXFIFO_TIMEOUT_ENA_S  23
+/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */
+/*description: */
+#define UHCI_RXFIFO_TIMEOUT_SHIFT  0x00000007
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_M  ((UHCI_RXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_RXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_RXFIFO_TIMEOUT_SHIFT_S  20
+/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */
+/*description: */
+#define UHCI_RXFIFO_TIMEOUT  0x000000FF
+#define UHCI_RXFIFO_TIMEOUT_M  ((UHCI_RXFIFO_TIMEOUT_V)<<(UHCI_RXFIFO_TIMEOUT_S))
+#define UHCI_RXFIFO_TIMEOUT_V  0xFF
+#define UHCI_RXFIFO_TIMEOUT_S  12
+/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
+/*description: */
+#define UHCI_TXFIFO_TIMEOUT_ENA  (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_M  (BIT(11))
+#define UHCI_TXFIFO_TIMEOUT_ENA_V  0x1
+#define UHCI_TXFIFO_TIMEOUT_ENA_S  11
+/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
+/*description: */
+#define UHCI_TXFIFO_TIMEOUT_SHIFT  0x00000007
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_M  ((UHCI_TXFIFO_TIMEOUT_SHIFT_V)<<(UHCI_TXFIFO_TIMEOUT_SHIFT_S))
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_V  0x7
+#define UHCI_TXFIFO_TIMEOUT_SHIFT_S  8
+/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
+/*description: */
+#define UHCI_TXFIFO_TIMEOUT  0x000000FF
+#define UHCI_TXFIFO_TIMEOUT_M  ((UHCI_TXFIFO_TIMEOUT_V)<<(UHCI_TXFIFO_TIMEOUT_S))
+#define UHCI_TXFIFO_TIMEOUT_V  0xFF
+#define UHCI_TXFIFO_TIMEOUT_S  0
+
+#define UHCI_ACK_NUM_REG(i)          (REG_UHCI_BASE(i) + 0x6C)
+
+#define UHCI_RX_HEAD_REG(i)          (REG_UHCI_BASE(i) + 0x70)
+/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_RX_HEAD  0xFFFFFFFF
+#define UHCI_RX_HEAD_M  ((UHCI_RX_HEAD_V)<<(UHCI_RX_HEAD_S))
+#define UHCI_RX_HEAD_V  0xFFFFFFFF
+#define UHCI_RX_HEAD_S  0
+
+#define UHCI_QUICK_SENT_REG(i)          (REG_UHCI_BASE(i) + 0x74)
+/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_ALWAYS_SEND_EN  (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_M  (BIT(7))
+#define UHCI_ALWAYS_SEND_EN_V  0x1
+#define UHCI_ALWAYS_SEND_EN_S  7
+/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */
+/*description: */
+#define UHCI_ALWAYS_SEND_NUM  0x00000007
+#define UHCI_ALWAYS_SEND_NUM_M  ((UHCI_ALWAYS_SEND_NUM_V)<<(UHCI_ALWAYS_SEND_NUM_S))
+#define UHCI_ALWAYS_SEND_NUM_V  0x7
+#define UHCI_ALWAYS_SEND_NUM_S  4
+/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */
+/*description: */
+#define UHCI_SINGLE_SEND_EN  (BIT(3))
+#define UHCI_SINGLE_SEND_EN_M  (BIT(3))
+#define UHCI_SINGLE_SEND_EN_V  0x1
+#define UHCI_SINGLE_SEND_EN_S  3
+/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */
+/*description: */
+#define UHCI_SINGLE_SEND_NUM  0x00000007
+#define UHCI_SINGLE_SEND_NUM_M  ((UHCI_SINGLE_SEND_NUM_V)<<(UHCI_SINGLE_SEND_NUM_S))
+#define UHCI_SINGLE_SEND_NUM_V  0x7
+#define UHCI_SINGLE_SEND_NUM_S  0
+
+#define UHCI_Q0_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x78)
+/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q0_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_M  ((UHCI_SEND_Q0_WORD0_V)<<(UHCI_SEND_Q0_WORD0_S))
+#define UHCI_SEND_Q0_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD0_S  0
+
+#define UHCI_Q0_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x7C)
+/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q0_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_M  ((UHCI_SEND_Q0_WORD1_V)<<(UHCI_SEND_Q0_WORD1_S))
+#define UHCI_SEND_Q0_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q0_WORD1_S  0
+
+#define UHCI_Q1_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x80)
+/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q1_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_M  ((UHCI_SEND_Q1_WORD0_V)<<(UHCI_SEND_Q1_WORD0_S))
+#define UHCI_SEND_Q1_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD0_S  0
+
+#define UHCI_Q1_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x84)
+/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q1_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_M  ((UHCI_SEND_Q1_WORD1_V)<<(UHCI_SEND_Q1_WORD1_S))
+#define UHCI_SEND_Q1_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q1_WORD1_S  0
+
+#define UHCI_Q2_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x88)
+/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q2_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_M  ((UHCI_SEND_Q2_WORD0_V)<<(UHCI_SEND_Q2_WORD0_S))
+#define UHCI_SEND_Q2_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD0_S  0
+
+#define UHCI_Q2_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x8C)
+/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q2_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_M  ((UHCI_SEND_Q2_WORD1_V)<<(UHCI_SEND_Q2_WORD1_S))
+#define UHCI_SEND_Q2_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q2_WORD1_S  0
+
+#define UHCI_Q3_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x90)
+/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q3_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_M  ((UHCI_SEND_Q3_WORD0_V)<<(UHCI_SEND_Q3_WORD0_S))
+#define UHCI_SEND_Q3_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD0_S  0
+
+#define UHCI_Q3_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x94)
+/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q3_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_M  ((UHCI_SEND_Q3_WORD1_V)<<(UHCI_SEND_Q3_WORD1_S))
+#define UHCI_SEND_Q3_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q3_WORD1_S  0
+
+#define UHCI_Q4_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0x98)
+/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q4_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_M  ((UHCI_SEND_Q4_WORD0_V)<<(UHCI_SEND_Q4_WORD0_S))
+#define UHCI_SEND_Q4_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD0_S  0
+
+#define UHCI_Q4_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0x9C)
+/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q4_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_M  ((UHCI_SEND_Q4_WORD1_V)<<(UHCI_SEND_Q4_WORD1_S))
+#define UHCI_SEND_Q4_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q4_WORD1_S  0
+
+#define UHCI_Q5_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0xA0)
+/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q5_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_M  ((UHCI_SEND_Q5_WORD0_V)<<(UHCI_SEND_Q5_WORD0_S))
+#define UHCI_SEND_Q5_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD0_S  0
+
+#define UHCI_Q5_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0xA4)
+/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q5_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_M  ((UHCI_SEND_Q5_WORD1_V)<<(UHCI_SEND_Q5_WORD1_S))
+#define UHCI_SEND_Q5_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q5_WORD1_S  0
+
+#define UHCI_Q6_WORD0_REG(i)          (REG_UHCI_BASE(i) + 0xA8)
+/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q6_WORD0  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_M  ((UHCI_SEND_Q6_WORD0_V)<<(UHCI_SEND_Q6_WORD0_S))
+#define UHCI_SEND_Q6_WORD0_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD0_S  0
+
+#define UHCI_Q6_WORD1_REG(i)          (REG_UHCI_BASE(i) + 0xAC)
+/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
+/*description: */
+#define UHCI_SEND_Q6_WORD1  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_M  ((UHCI_SEND_Q6_WORD1_V)<<(UHCI_SEND_Q6_WORD1_S))
+#define UHCI_SEND_Q6_WORD1_V  0xFFFFFFFF
+#define UHCI_SEND_Q6_WORD1_S  0
+
+#define UHCI_ESC_CONF0_REG(i)          (REG_UHCI_BASE(i) + 0xB0)
+/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */
+/*description: */
+#define UHCI_SEPER_ESC_CHAR1  0x000000FF
+#define UHCI_SEPER_ESC_CHAR1_M  ((UHCI_SEPER_ESC_CHAR1_V)<<(UHCI_SEPER_ESC_CHAR1_S))
+#define UHCI_SEPER_ESC_CHAR1_V  0xFF
+#define UHCI_SEPER_ESC_CHAR1_S  16
+/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: */
+#define UHCI_SEPER_ESC_CHAR0  0x000000FF
+#define UHCI_SEPER_ESC_CHAR0_M  ((UHCI_SEPER_ESC_CHAR0_V)<<(UHCI_SEPER_ESC_CHAR0_S))
+#define UHCI_SEPER_ESC_CHAR0_V  0xFF
+#define UHCI_SEPER_ESC_CHAR0_S  8
+/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */
+/*description: */
+#define UHCI_SEPER_CHAR  0x000000FF
+#define UHCI_SEPER_CHAR_M  ((UHCI_SEPER_CHAR_V)<<(UHCI_SEPER_CHAR_S))
+#define UHCI_SEPER_CHAR_V  0xFF
+#define UHCI_SEPER_CHAR_S  0
+
+#define UHCI_ESC_CONF1_REG(i)          (REG_UHCI_BASE(i) + 0xB4)
+/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */
+/*description: */
+#define UHCI_ESC_SEQ0_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ0_CHAR1_M  ((UHCI_ESC_SEQ0_CHAR1_V)<<(UHCI_ESC_SEQ0_CHAR1_S))
+#define UHCI_ESC_SEQ0_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR1_S  16
+/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: */
+#define UHCI_ESC_SEQ0_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ0_CHAR0_M  ((UHCI_ESC_SEQ0_CHAR0_V)<<(UHCI_ESC_SEQ0_CHAR0_S))
+#define UHCI_ESC_SEQ0_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ0_CHAR0_S  8
+/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */
+/*description: */
+#define UHCI_ESC_SEQ0  0x000000FF
+#define UHCI_ESC_SEQ0_M  ((UHCI_ESC_SEQ0_V)<<(UHCI_ESC_SEQ0_S))
+#define UHCI_ESC_SEQ0_V  0xFF
+#define UHCI_ESC_SEQ0_S  0
+
+#define UHCI_ESC_CONF2_REG(i)          (REG_UHCI_BASE(i) + 0xB8)
+/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */
+/*description: */
+#define UHCI_ESC_SEQ1_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ1_CHAR1_M  ((UHCI_ESC_SEQ1_CHAR1_V)<<(UHCI_ESC_SEQ1_CHAR1_S))
+#define UHCI_ESC_SEQ1_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR1_S  16
+/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: */
+#define UHCI_ESC_SEQ1_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ1_CHAR0_M  ((UHCI_ESC_SEQ1_CHAR0_V)<<(UHCI_ESC_SEQ1_CHAR0_S))
+#define UHCI_ESC_SEQ1_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ1_CHAR0_S  8
+/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */
+/*description: */
+#define UHCI_ESC_SEQ1  0x000000FF
+#define UHCI_ESC_SEQ1_M  ((UHCI_ESC_SEQ1_V)<<(UHCI_ESC_SEQ1_S))
+#define UHCI_ESC_SEQ1_V  0xFF
+#define UHCI_ESC_SEQ1_S  0
+
+#define UHCI_ESC_CONF3_REG(i)          (REG_UHCI_BASE(i) + 0xBC)
+/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */
+/*description: */
+#define UHCI_ESC_SEQ2_CHAR1  0x000000FF
+#define UHCI_ESC_SEQ2_CHAR1_M  ((UHCI_ESC_SEQ2_CHAR1_V)<<(UHCI_ESC_SEQ2_CHAR1_S))
+#define UHCI_ESC_SEQ2_CHAR1_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR1_S  16
+/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */
+/*description: */
+#define UHCI_ESC_SEQ2_CHAR0  0x000000FF
+#define UHCI_ESC_SEQ2_CHAR0_M  ((UHCI_ESC_SEQ2_CHAR0_V)<<(UHCI_ESC_SEQ2_CHAR0_S))
+#define UHCI_ESC_SEQ2_CHAR0_V  0xFF
+#define UHCI_ESC_SEQ2_CHAR0_S  8
+/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */
+/*description: */
+#define UHCI_ESC_SEQ2  0x000000FF
+#define UHCI_ESC_SEQ2_M  ((UHCI_ESC_SEQ2_V)<<(UHCI_ESC_SEQ2_S))
+#define UHCI_ESC_SEQ2_V  0xFF
+#define UHCI_ESC_SEQ2_S  0
+
+#define UHCI_PKT_THRES_REG(i)          (REG_UHCI_BASE(i) + 0xC0)
+/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */
+/*description: */
+#define UHCI_PKT_THRS  0x00001FFF
+#define UHCI_PKT_THRS_M  ((UHCI_PKT_THRS_V)<<(UHCI_PKT_THRS_S))
+#define UHCI_PKT_THRS_V  0x1FFF
+#define UHCI_PKT_THRS_S  0
+
+#define UHCI_DATE_REG(i)          (REG_UHCI_BASE(i) + 0xFC)
+/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h18073001 ; */
+/*description: */
+#define UHCI_DATE  0xFFFFFFFF
+#define UHCI_DATE_M  ((UHCI_DATE_V)<<(UHCI_DATE_S))
+#define UHCI_DATE_V  0xFFFFFFFF
+#define UHCI_DATE_S  0
+
+#ifdef __cplusplus
+}
+#endif
+
+
+
+#endif /*_SOC_UHCI_REG_H_ */
+
+
diff --git a/components/soc/esp32s2beta/include/soc/uhci_struct.h b/components/soc/esp32s2beta/include/soc/uhci_struct.h
new file mode 100644
index 000000000..aadc2a630
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/uhci_struct.h
@@ -0,0 +1,365 @@
+// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef _SOC_UHCI_STRUCT_H_
+#define _SOC_UHCI_STRUCT_H_
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef volatile struct {
+    union {
+        struct {
+            uint32_t in_rst:             1;
+            uint32_t out_rst:            1;
+            uint32_t ahbm_fifo_rst:      1;
+            uint32_t ahbm_rst:           1;
+            uint32_t in_loop_test:       1;
+            uint32_t out_loop_test:      1;
+            uint32_t out_auto_wrback:    1;
+            uint32_t out_no_restart_clr: 1;
+            uint32_t out_eof_mode:       1;
+            uint32_t uart0_ce:           1;
+            uint32_t uart1_ce:           1;
+            uint32_t reserved11:         1;
+            uint32_t outdscr_burst_en:   1;
+            uint32_t indscr_burst_en:    1;
+            uint32_t out_data_burst_en:  1;
+            uint32_t mem_trans_en:       1;
+            uint32_t seper_en:           1;
+            uint32_t head_en:            1;
+            uint32_t crc_rec_en:         1;
+            uint32_t uart_idle_eof_en:   1;
+            uint32_t len_eof_en:         1;
+            uint32_t encode_crc_en:      1;
+            uint32_t clk_en:             1;
+            uint32_t uart_rx_brk_eof_en: 1;
+            uint32_t reserved24:         8;
+        };
+        uint32_t val;
+    } conf0;
+    union {
+        struct {
+            uint32_t rx_start:                   1;
+            uint32_t tx_start:                   1;
+            uint32_t rx_hung:                    1;
+            uint32_t tx_hung:                    1;
+            uint32_t in_done:                    1;
+            uint32_t in_suc_eof:                 1;
+            uint32_t in_err_eof:                 1;
+            uint32_t out_done:                   1;
+            uint32_t out_eof:                    1;
+            uint32_t in_dscr_err:                1;
+            uint32_t out_dscr_err:               1;
+            uint32_t in_dscr_empty:              1;
+            uint32_t outlink_eof_err:            1;
+            uint32_t out_total_eof:              1;
+            uint32_t send_s_q:                   1;
+            uint32_t send_a_q:                   1;
+            uint32_t dma_in_fifo_full_wm:        1;
+            uint32_t reserved17:                15;
+        };
+        uint32_t val;
+    } int_raw;
+    union {
+        struct {
+            uint32_t rx_start:                  1;
+            uint32_t tx_start:                  1;
+            uint32_t rx_hung:                   1;
+            uint32_t tx_hung:                   1;
+            uint32_t in_done:                   1;
+            uint32_t in_suc_eof:                1;
+            uint32_t in_err_eof:                1;
+            uint32_t out_done:                  1;
+            uint32_t out_eof:                   1;
+            uint32_t in_dscr_err:               1;
+            uint32_t out_dscr_err:              1;
+            uint32_t in_dscr_empty:             1;
+            uint32_t outlink_eof_err:           1;
+            uint32_t out_total_eof:             1;
+            uint32_t send_s_q:                  1;
+            uint32_t send_a_q:                  1;
+            uint32_t dma_in_fifo_full_wm:       1;
+            uint32_t reserved17:               15;
+        };
+        uint32_t val;
+    } int_st;
+    union {
+        struct {
+            uint32_t rx_start:                   1;
+            uint32_t tx_start:                   1;
+            uint32_t rx_hung:                    1;
+            uint32_t tx_hung:                    1;
+            uint32_t in_done:                    1;
+            uint32_t in_suc_eof:                 1;
+            uint32_t in_err_eof:                 1;
+            uint32_t out_done:                   1;
+            uint32_t out_eof:                    1;
+            uint32_t in_dscr_err:                1;
+            uint32_t out_dscr_err:               1;
+            uint32_t in_dscr_empty:              1;
+            uint32_t outlink_eof_err:            1;
+            uint32_t out_total_eof:              1;
+            uint32_t send_s_q:                   1;
+            uint32_t send_a_q:                   1;
+            uint32_t dma_in_fifo_full_wm:        1;
+            uint32_t reserved17:                15;
+        };
+        uint32_t val;
+    } int_ena;
+    union {
+        struct {
+            uint32_t rx_start:                   1;
+            uint32_t tx_start:                   1;
+            uint32_t rx_hung:                    1;
+            uint32_t tx_hung:                    1;
+            uint32_t in_done:                    1;
+            uint32_t in_suc_eof:                 1;
+            uint32_t in_err_eof:                 1;
+            uint32_t out_done:                   1;
+            uint32_t out_eof:                    1;
+            uint32_t in_dscr_err:                1;
+            uint32_t out_dscr_err:               1;
+            uint32_t in_dscr_empty:              1;
+            uint32_t outlink_eof_err:            1;
+            uint32_t out_total_eof:              1;
+            uint32_t send_s_q:                   1;
+            uint32_t send_a_q:                   1;
+            uint32_t dma_in_fifo_full_wm:        1;
+            uint32_t reserved17:                15;
+        };
+        uint32_t val;
+    } int_clr;
+    union {
+        struct {
+            uint32_t full:       1;
+            uint32_t empty:      1;
+            uint32_t reserved2: 30;
+        };
+        uint32_t val;
+    } dma_out_status;
+    union {
+        struct {
+            uint32_t fifo_wdata:    9;
+            uint32_t reserved9:     7;
+            uint32_t fifo_push:     1;
+            uint32_t reserved17:   15;
+        };
+        uint32_t val;
+    } dma_out_push;
+    union {
+        struct {
+            uint32_t full:         1;
+            uint32_t empty:        1;
+            uint32_t reserved2:    2;
+            uint32_t rx_err_cause: 3;
+            uint32_t reserved7:   25;
+        };
+        uint32_t val;
+    } dma_in_status;
+    union {
+        struct {
+            uint32_t fifo_rdata:  12;
+            uint32_t reserved12:   4;
+            uint32_t fifo_pop:     1;
+            uint32_t reserved17:  15;
+        };
+        uint32_t val;
+    } dma_in_pop;
+    union {
+        struct {
+            uint32_t addr:           20;
+            uint32_t reserved20:      8;
+            uint32_t stop:            1;
+            uint32_t start:           1;
+            uint32_t restart:         1;
+            uint32_t park:            1;
+        };
+        uint32_t val;
+    } dma_out_link;
+    union {
+        struct {
+            uint32_t addr:           20;
+            uint32_t auto_ret:        1;
+            uint32_t reserved21:      7;
+            uint32_t stop:            1;
+            uint32_t start:           1;
+            uint32_t restart:         1;
+            uint32_t park:            1;
+        };
+        uint32_t val;
+    } dma_in_link;
+    union {
+        struct {
+            uint32_t check_sum_en:         1;
+            uint32_t check_seq_en:         1;
+            uint32_t crc_disable:          1;
+            uint32_t save_head:            1;
+            uint32_t tx_check_sum_re:      1;
+            uint32_t tx_ack_num_re:        1;
+            uint32_t check_owner:          1;
+            uint32_t wait_sw_start:        1;
+            uint32_t sw_start:             1;
+            uint32_t dma_in_fifo_full_thrs:12;
+            uint32_t reserved21:          11;
+        };
+        uint32_t val;
+    } conf1;
+    union {
+        struct {
+            uint32_t dscr_addr:       18;
+            uint32_t in_dscr_state:    2;
+            uint32_t in_state:         3;
+            uint32_t fifo_cnt_debug:   5;
+            uint32_t decode_state:     3;
+            uint32_t reserved31:       1;
+        };
+        uint32_t val;
+    } state0;
+    union {
+        struct {
+            uint32_t outlink_dscr_addr:18;
+            uint32_t out_dscr_state:    2;
+            uint32_t out_state:         3;
+            uint32_t fifo_cnt:          5;
+            uint32_t encode_state:      3;
+            uint32_t reserved31:        1;
+        };
+        uint32_t val;
+    } state1;
+    uint32_t dma_out_eof_des_addr;                         /**/
+    uint32_t dma_in_suc_eof_des_addr;                      /**/
+    uint32_t dma_in_err_eof_des_addr;                      /**/
+    uint32_t dma_out_eof_bfr_des_addr;                     /**/
+    union {
+        struct {
+            uint32_t test_mode:    3;
+            uint32_t reserved3:    1;
+            uint32_t test_addr:    2;
+            uint32_t reserved6:   26;
+        };
+        uint32_t val;
+    } ahb_test;
+    uint32_t dma_in_dscr;                                  /**/
+    uint32_t dma_in_dscr_bf0;                              /**/
+    uint32_t dma_in_dscr_bf1;                              /**/
+    uint32_t dma_out_dscr;                                 /**/
+    uint32_t dma_out_dscr_bf0;                             /**/
+    uint32_t dma_out_dscr_bf1;                             /**/
+    union {
+        struct {
+            uint32_t tx_c0_esc_en: 1;
+            uint32_t tx_db_esc_en: 1;
+            uint32_t tx_11_esc_en: 1;
+            uint32_t tx_13_esc_en: 1;
+            uint32_t rx_c0_esc_en: 1;
+            uint32_t rx_db_esc_en: 1;
+            uint32_t rx_11_esc_en: 1;
+            uint32_t rx_13_esc_en: 1;
+            uint32_t reserved8:   24;
+        };
+        uint32_t val;
+    } escape_conf;
+    union {
+        struct {
+            uint32_t txfifo_timeout:       8;
+            uint32_t txfifo_timeout_shift: 3;
+            uint32_t txfifo_timeout_ena:   1;
+            uint32_t rxfifo_timeout:       8;
+            uint32_t rxfifo_timeout_shift: 3;
+            uint32_t rxfifo_timeout_ena:   1;
+            uint32_t reserved24:           8;
+        };
+        uint32_t val;
+    } hung_conf;
+    uint32_t ack_num;                                      /**/
+    uint32_t rx_head;                                      /**/
+    union {
+        struct {
+            uint32_t single_send_num: 3;
+            uint32_t single_send_en:  1;
+            uint32_t always_send_num: 3;
+            uint32_t always_send_en:  1;
+            uint32_t reserved8:      24;
+        };
+        uint32_t val;
+    } quick_sent;
+    struct {
+        uint32_t w_data[2];                                     /**/
+    } q_data[7];
+    union {
+        struct {
+            uint32_t seper_char:      8;
+            uint32_t seper_esc_char0: 8;
+            uint32_t seper_esc_char1: 8;
+            uint32_t reserved24:      8;
+        };
+        uint32_t val;
+    } esc_conf0;
+    union {
+        struct {
+            uint32_t seq0:           8;
+            uint32_t seq0_char0:     8;
+            uint32_t seq0_char1:     8;
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } esc_conf1;
+    union {
+        struct {
+            uint32_t seq1:           8;
+            uint32_t seq1_char0:     8;
+            uint32_t seq1_char1:     8;
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } esc_conf2;
+    union {
+        struct {
+            uint32_t seq2:           8;
+            uint32_t seq2_char0:     8;
+            uint32_t seq2_char1:     8;
+            uint32_t reserved24:     8;
+        };
+        uint32_t val;
+    } esc_conf3;
+    union {
+        struct {
+            uint32_t thrs:      13;
+            uint32_t reserved13:19;
+        };
+        uint32_t val;
+    } pkt_thres;
+    uint32_t reserved_c4;
+    uint32_t reserved_c8;
+    uint32_t reserved_cc;
+    uint32_t reserved_d0;
+    uint32_t reserved_d4;
+    uint32_t reserved_d8;
+    uint32_t reserved_dc;
+    uint32_t reserved_e0;
+    uint32_t reserved_e4;
+    uint32_t reserved_e8;
+    uint32_t reserved_ec;
+    uint32_t reserved_f0;
+    uint32_t reserved_f4;
+    uint32_t reserved_f8;
+    uint32_t date;                                         /**/
+} uhci_dev_t;
+extern uhci_dev_t UHCI0;
+extern uhci_dev_t UHCI1;
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SOC_UHCI_STRUCT_H_ */
diff --git a/components/soc/esp32s2beta/include/soc/wdev_reg.h b/components/soc/esp32s2beta/include/soc/wdev_reg.h
new file mode 100644
index 000000000..f258088a2
--- /dev/null
+++ b/components/soc/esp32s2beta/include/soc/wdev_reg.h
@@ -0,0 +1,21 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+#include "soc.h"
+
+/* Hardware random number generator register */ 
+#define WDEV_RND_REG 0x60035100
+
diff --git a/components/soc/esp32s2beta/rtc_clk.c b/components/soc/esp32s2beta/rtc_clk.c
new file mode 100644
index 000000000..e14bcc158
--- /dev/null
+++ b/components/soc/esp32s2beta/rtc_clk.c
@@ -0,0 +1,840 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdbool.h>
+#include <stdint.h>
+#include <stddef.h>
+#include <assert.h>
+#include "rom/ets_sys.h"
+#include "rom/rtc.h"
+#include "rom/uart.h"
+#include "rom/gpio.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/rtc_io_reg.h"
+#include "soc/sens_reg.h"
+#include "soc/dport_reg.h"
+#include "soc/efuse_reg.h"
+#include "soc/syscon_reg.h"
+#include "i2c_rtc_clk.h"
+#include "soc_log.h"
+#include "sdkconfig.h"
+#include "xtensa/core-macros.h"
+
+
+#define MHZ (1000000)
+
+/* Frequency of the 8M oscillator is 8.5MHz +/- 5%, at the default DCAP setting */
+#define RTC_FAST_CLK_FREQ_8M        8500000
+#define RTC_SLOW_CLK_FREQ_150K      150000
+#define RTC_SLOW_CLK_FREQ_8MD256    (RTC_FAST_CLK_FREQ_8M / 256)
+#define RTC_SLOW_CLK_FREQ_32K       32768
+
+static const char* TAG = "rtc_clk";
+
+/* Various constants related to the analog internals of the chip.
+ * Defined here because they don't have any use outside of this file.
+ */
+
+#define BBPLL_ENDIV5_VAL_320M       0x43
+#define BBPLL_BBADC_DSMP_VAL_320M   0x84
+#define BBPLL_ENDIV5_VAL_480M       0xc3
+#define BBPLL_BBADC_DSMP_VAL_480M   0x74
+
+#define APLL_SDM_STOP_VAL_1         0x09
+#define APLL_SDM_STOP_VAL_2_REV0    0x69
+#define APLL_SDM_STOP_VAL_2_REV1    0x49
+
+#define APLL_CAL_DELAY_1            0x0f
+#define APLL_CAL_DELAY_2            0x3f
+#define APLL_CAL_DELAY_3            0x1f
+
+#define XTAL_32K_DAC_VAL    1
+#define XTAL_32K_DRES_VAL   3
+#define XTAL_32K_DGM_VAL  0
+
+#define XTAL_32K_BOOTSTRAP_DAC_VAL      3
+#define XTAL_32K_BOOTSTRAP_DRES_VAL     3
+#define XTAL_32K_BOOTSTRAP_DBIAS_VAL    0
+#define XTAL_32K_BOOTSTRAP_TIME_US      7
+
+/* Delays for various clock sources to be enabled/switched.
+ * All values are in microseconds.
+ * TODO: some of these are excessive, and should be reduced.
+ */
+#define DELAY_PLL_DBIAS_RAISE           3
+#define DELAY_PLL_ENABLE_WITH_150K      80
+#define DELAY_PLL_ENABLE_WITH_32K       160
+#define DELAY_FAST_CLK_SWITCH           3
+#define DELAY_SLOW_CLK_SWITCH           300
+#define DELAY_8M_ENABLE                 50
+
+/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
+ * 10 cycles will take approximately 300 microseconds.
+ */
+#define XTAL_FREQ_EST_CYCLES            10
+
+/* Core voltage needs to be increased in two cases:
+ * 1. running at 240 MHz
+ * 2. running with 80MHz Flash frequency
+ */
+#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
+#define DIG_DBIAS_80M_160M  RTC_CNTL_DBIAS_1V25
+#else
+#define DIG_DBIAS_80M_160M  RTC_CNTL_DBIAS_1V10
+#endif
+#define DIG_DBIAS_240M      RTC_CNTL_DBIAS_1V25
+#define DIG_DBIAS_XTAL      RTC_CNTL_DBIAS_1V10
+#define DIG_DBIAS_2M        RTC_CNTL_DBIAS_1V00
+
+/* PLL currently enabled, if any */
+typedef enum {
+    RTC_PLL_NONE,
+    RTC_PLL_320M,
+    RTC_PLL_480M
+} rtc_pll_t;
+static rtc_pll_t s_cur_pll = RTC_PLL_NONE;
+
+/* Current CPU frequency; saved in a variable for faster freq. switching */
+static rtc_cpu_freq_t s_cur_freq = RTC_CPU_FREQ_XTAL;
+
+void rtc_clk_32k_enable_internal(int dac, int dres, int dgm)
+{
+    SET_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL);
+    SET_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL);
+    CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_RUE | RTC_IO_X32P_FUN_IE | RTC_IO_X32P_RDE);
+    CLEAR_PERI_REG_MASK(RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_RUE | RTC_IO_X32N_FUN_IE | RTC_IO_X32N_RDE);
+    REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, dac);
+    REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, dres);
+    REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, dgm);
+
+    /* Differential buffer option. May need to change */
+    // CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K);
+
+    /* Clear xpd force to use xtal32k watch dog to control xtal pxd. default on */
+    CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
+}
+
+void rtc_clk_32k_enable(bool enable)
+{
+    if (enable) {
+        rtc_clk_32k_enable_internal(XTAL_32K_DAC_VAL, XTAL_32K_DRES_VAL, XTAL_32K_DGM_VAL);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K);
+        SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
+    }
+}
+
+/* Helping external 32kHz crystal to start up.
+ * External crystal connected to outputs GPIO32 GPIO33.
+ * Forms N pulses with a frequency of about 32KHz on the outputs of the crystal.
+ */
+/* I doudt whether the old function can work correctly on ESP32...Need to review when having time */
+void rtc_clk_32k_bootstrap(uint32_t cycle)
+{
+    /* Config a clock to stimulate xtal, this clock is divided by a clock mux
+     * The default selection of the clock mux is to use 8M, but it may not have enough accuracy compared with 40M xtal
+     * This clock will be a pulse clk with a double frequency of 32.768k.
+     * and then it will become a 32.768k clock with 50% duty cycle in RTC.
+     * (40M / 32.768k) * 2 = 2441 + 13/32
+     */
+    REG_SET_FIELD(DPORT_BT_LPCK_DIV_INT_REG, DPORT_BT_LPCK_DIV_NUM, 2441);
+    REG_SET_FIELD(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_BT_LPCK_DIV_A, 32);
+    REG_SET_FIELD(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_BT_LPCK_DIV_B, 13);
+
+    /* Enable clock mux with 40M */
+    SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
+    CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_8M);
+    SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL);
+
+    /* connect clock to RTC */
+    SET_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_RTC_EN);
+    /* connect clock to analog */
+    SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_ENCKINIT_XTAL_32K);
+
+    /* Enable 32k xtal */
+    rtc_clk_32k_enable_internal(XTAL_32K_BOOTSTRAP_DAC_VAL, XTAL_32K_BOOTSTRAP_DRES_VAL, XTAL_32K_BOOTSTRAP_DBIAS_VAL);
+
+    /* wait 32k xtal to be stable. Need to find a better way */
+    ets_delay_us(cycle);
+
+    /* Close clock source */
+    CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_SEL_XTAL);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_EN);
+    CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_ENCKINIT_XTAL_32K);
+    CLEAR_PERI_REG_MASK(DPORT_BT_LPCK_DIV_FRAC_REG, DPORT_LPCLK_RTC_EN);
+}
+
+bool rtc_clk_32k_enabled()
+{
+    uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
+    /* If xtal xpd is controlled by software */
+    bool xtal_xpd_sw = (xtal_conf & RTC_CNTL_XTAL32K_XPD_FORCE) >> RTC_CNTL_XTAL32K_XPD_FORCE_S;
+    /* If xtal xpd software control is on */
+    bool xtal_xpd_st = (xtal_conf & RTC_CNTL_XPD_XTAL_32K) >> RTC_CNTL_XPD_XTAL_32K_S;
+    if (xtal_xpd_sw & !xtal_xpd_st) {
+        return false;
+    } else {
+        return true;
+    }
+}
+
+void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
+{
+    if (clk_8m_en) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
+        /* no need to wait once enabled by software */
+        REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, 1);
+        ets_delay_us(DELAY_8M_ENABLE);
+    } else {
+        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
+        REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
+    }
+    /* d256 should be independent configured with 8M 
+     * Maybe we can split this function into 8m and dmd256 
+     */
+    if (d256_en) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
+    } else {
+        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
+    }
+}
+
+bool rtc_clk_8m_enabled()
+{
+    return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
+}
+
+bool rtc_clk_8md256_enabled()
+{
+    return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
+}
+
+void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
+{
+    REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
+    REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
+
+    /* BIAS I2C not exist any more, but not sure how to get the same effect yet... 
+     * if (!enable &&
+     *   REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL) != SYSCON_SOC_CLK_SEL_PLL) {
+     *   REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
+     * } else {
+     *   REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
+     * }
+     */
+
+    if (enable) {
+        /* no need to differentiate ECO chip any more 
+        uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
+        uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
+        if (is_rev0) {
+            sdm0 = 0;
+            sdm1 = 0;
+            sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
+        }
+        */
+        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
+        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
+        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
+        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
+        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1);
+        I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
+
+        /* calibration */
+        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
+        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
+        I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
+
+        /* wait for calibration end */
+        while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
+            /* use ets_delay_us so the RTC bus doesn't get flooded */
+            ets_delay_us(1);
+        }
+    }
+}
+
+void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
+{
+    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
+
+    /* Why we need to connect this clock to digital?
+     * Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead?
+     */
+    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
+            (slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
+
+    ets_delay_us(DELAY_SLOW_CLK_SWITCH);
+}
+
+rtc_slow_freq_t rtc_clk_slow_freq_get()
+{
+    return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
+}
+
+uint32_t rtc_clk_slow_freq_get_hz()
+{
+    switch(rtc_clk_slow_freq_get()) {
+        case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
+        case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
+        case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
+    }
+    return 0;
+}
+
+void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
+{
+    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
+    ets_delay_us(DELAY_FAST_CLK_SWITCH);
+}
+
+rtc_fast_freq_t rtc_clk_fast_freq_get()
+{
+    return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
+}
+
+/* In 7.2.2, cpu can run at 80M/160M/240M if PLL is 480M
+ * pll can run 80M/160M is PLL is 320M
+ */
+#define DR_REG_I2C_MST_BASE             0x3f40E000
+#define I2C_MST_ANA_STATE_REG           (DR_REG_I2C_MST_BASE + 0x040)
+#define I2C_MST_BBPLL_CAL_END           (BIT(24))
+#define I2C_MST_BBPLL_CAL_END_M         (BIT(24))
+#define I2C_MST_BBPLL_CAL_END_V         0x1
+#define I2C_MST_BBPLL_CAL_END_S         24
+
+void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq)
+{
+    uint8_t div_ref;
+    uint8_t div7_0;
+    uint8_t dr1;
+    uint8_t dr3;
+    uint8_t dchgp;
+    uint8_t dcur;
+
+    if (pll_freq == RTC_PLL_480M) {
+        /* Raise the voltage, if needed */
+        /* move to 240M logic */
+        //REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
+        /* Set this register to let digital know pll is 480M */
+        SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
+        /* Configure 480M PLL */
+        switch (xtal_freq) {
+            case RTC_XTAL_FREQ_40M:
+                div_ref = 0;
+                div7_0 = 8;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 4;
+                break;
+            case RTC_XTAL_FREQ_26M:
+                div_ref = 12;
+                div7_0 = 156;
+                dr1 = 3;
+                dr3 = 3;
+                dchgp = 4;
+                dcur = 1;
+                break;
+            case RTC_XTAL_FREQ_24M:
+                div_ref = 11;
+                div7_0 = 156;
+                dr1 = 3;
+                dr3 = 3;
+                dchgp = 4;
+                dcur = 1;
+                break;
+            default:
+                div_ref = 0;
+                div7_0 = 8;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 4;
+                break;
+        }
+        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
+    } else {
+        /* Raise the voltage */
+        //REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
+        //ets_delay_us(DELAY_PLL_DBIAS_RAISE);
+        CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
+        /* Configure 480M PLL */
+        switch (xtal_freq) {
+            case RTC_XTAL_FREQ_40M:
+                div_ref = 0;
+                div7_0 = 4;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 5;
+                break;
+            case RTC_XTAL_FREQ_26M:
+                div_ref = 12;
+                div7_0 = 236;
+                dr1 = 3;
+                dr3 = 3;
+                dchgp = 0;
+                dcur = 2;
+                break;
+            case RTC_XTAL_FREQ_24M:
+                div_ref = 11;
+                div7_0 = 236;
+                dr1 = 3;
+                dr3 = 3;
+                dchgp = 0;
+                dcur = 2;
+                break;
+            default:
+                div_ref = 0;
+                div7_0 = 4;
+                dr1 = 0;
+                dr3 = 0;
+                dchgp = 5;
+                dcur = 5;
+                break;
+        }
+        I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
+    }
+    uint8_t i2c_bbpll_lref  = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
+    uint8_t i2c_bbpll_div_7_0 = div7_0;
+    uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
+    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
+    I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
+    I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
+
+    /* this delay is replaced by polling Pll calibration end flag
+     * uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
+     *       DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
+     * ets_delay_us(delay_pll_en);
+     */
+    /* this calibration didn't work on 480M
+    need to test exact delay according to 320M
+    while (!GET_PERI_REG_MASK(I2C_MST_ANA_STATE_REG, I2C_MST_BBPLL_CAL_END)) {
+        ets_delay_us(1);
+    }
+    */
+    ets_delay_us(50000); 
+}
+
+/**
+ * Switch to XTAL frequency. Does not disable the PLL.
+ */
+static void rtc_clk_cpu_freq_to_xtal()
+{
+    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
+    ets_update_cpu_frequency(xtal_freq);
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
+    REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0);
+    REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_XTL);
+    /* Why we need to do this ? */
+    //DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL
+
+    rtc_clk_apb_freq_update(xtal_freq * MHZ);
+    s_cur_freq = RTC_CPU_FREQ_XTAL;
+}
+
+/**
+ * Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
+ * PLL must already be enabled.
+ * If switching between frequencies derived from different PLLs (320M and 480M),
+ * fall back to rtc_clk_cpu_freq_set.
+ * @param cpu_freq new CPU frequency
+ */
+static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq)
+{
+    int freq = 0;
+    if ((s_cur_pll == RTC_PLL_NONE) || ((s_cur_pll == RTC_PLL_320M) && (cpu_freq == RTC_CPU_FREQ_240M))) {
+        /* 
+         * if switch from non-pll or switch from PLL 320M to 480M
+         * need to switch PLLs, fall back to full implementation 
+         */
+        rtc_clk_cpu_freq_set(cpu_freq);
+        return;
+    }
+
+    if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
+        REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
+        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0);
+        freq = 80;
+    } else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
+        REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
+        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 1);
+        freq = 160;
+    } else if (cpu_freq == RTC_CPU_FREQ_240M) {
+        REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
+        DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 2);
+        freq = 240;
+    }
+    // REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_PLL);
+    rtc_clk_apb_freq_update(80 * MHZ);
+    ets_update_cpu_frequency(freq);
+    s_cur_freq = cpu_freq;
+}
+
+void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq)
+{
+    if (cpu_freq == s_cur_freq) {
+        return;
+    } else if (cpu_freq == RTC_CPU_FREQ_2M || s_cur_freq == RTC_CPU_FREQ_2M) {
+        /* fall back to full implementation if switch to/from 2M is needed */
+        rtc_clk_cpu_freq_set(cpu_freq);
+    } else if (cpu_freq == RTC_CPU_FREQ_XTAL) {
+        rtc_clk_cpu_freq_to_xtal();
+    } else if (cpu_freq > RTC_CPU_FREQ_XTAL) {
+        rtc_clk_cpu_freq_to_pll(cpu_freq);
+        /* Not neccessary any more */
+        //rtc_clk_wait_for_slow_cycle();
+    }
+}
+
+void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
+{
+    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
+    /* Switch CPU to XTAL frequency first */
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
+    REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_XTL);
+    REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, 0);
+    ets_update_cpu_frequency(xtal_freq);
+    /* Frequency switch is synchronized to SLOW_CLK cycle. Wait until the switch
+     * is complete before disabling the PLL.
+     */
+    /* register SOC_CLK_SEL is moved to APB domain, so this delay is not neccessary any more */
+    //rtc_clk_wait_for_slow_cycle();
+
+    DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
+
+    /* BBPLL force power down won't affect force power up setting */
+    SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
+            RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
+            RTC_CNTL_BBPLL_I2C_FORCE_PD);
+    s_cur_pll = RTC_PLL_NONE;
+    rtc_clk_apb_freq_update(xtal_freq * MHZ);
+
+    /* is APLL under force power down? */
+    /* may need equivalent function
+    uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
+
+    
+     * if (apll_fpd) {
+     *   SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
+     * }
+    */
+
+    /* now switch to the desired frequency */
+    if (cpu_freq == RTC_CPU_FREQ_XTAL) {
+        /* already at XTAL, nothing to do */
+    } else if (cpu_freq == RTC_CPU_FREQ_2M) {
+        /* set up divider to produce 2MHz from XTAL */
+        REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT, (xtal_freq / 2) - 1);
+        ets_update_cpu_frequency(2);
+        rtc_clk_apb_freq_update(2 * MHZ);
+        /* lower the voltage */
+        REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
+    } else {
+        /* use PLL as clock source */
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
+                RTC_CNTL_BB_I2C_FORCE_PD |
+                RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
+        if (cpu_freq > RTC_CPU_FREQ_2M) {
+            rtc_clk_bbpll_set(xtal_freq, RTC_PLL_320M);
+            s_cur_pll = RTC_PLL_320M;
+        } else {
+            rtc_clk_bbpll_set(xtal_freq, RTC_PLL_480M);
+            s_cur_pll = RTC_PLL_480M;
+        }
+        
+        if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
+            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
+            ets_update_cpu_frequency(80);          
+        } else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
+            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
+            ets_update_cpu_frequency(160);
+        } else if (cpu_freq == RTC_CPU_FREQ_240M) {
+            DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
+            ets_update_cpu_frequency(240);     
+        }
+        REG_SET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL, SYSCON_SOC_CLK_SEL_PLL);
+        //rtc_clk_wait_for_slow_cycle();
+        rtc_clk_apb_freq_update(80 * MHZ);
+    }
+    s_cur_freq = cpu_freq;
+}
+
+rtc_cpu_freq_t rtc_clk_cpu_freq_get()
+{
+    uint32_t soc_clk_sel = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL);
+    switch (soc_clk_sel) {
+        case SYSCON_SOC_CLK_SEL_XTL: {
+            uint32_t pre_div = REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_PRE_DIV_CNT);
+            if (pre_div == 0) {
+                return RTC_CPU_FREQ_XTAL;
+            } else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) {
+                return RTC_CPU_FREQ_2M;
+            } else {
+                assert(false && "unsupported frequency");
+            }
+            break;
+        }
+        case SYSCON_SOC_CLK_SEL_PLL: {
+            uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
+            if (cpuperiod_sel == 0) {
+                return RTC_CPU_FREQ_80M;
+            } else if (cpuperiod_sel == 1) {
+                return RTC_CPU_FREQ_160M;
+            } else if (cpuperiod_sel == 2) {
+                return RTC_CPU_FREQ_240M;
+            } else {
+                assert(false && "unsupported frequency");
+            }
+            break;
+        }
+        case SYSCON_SOC_CLK_SEL_APLL:
+        case SYSCON_SOC_CLK_SEL_8M:
+        default:
+            assert(false && "unsupported frequency");
+    }
+    return SYSCON_SOC_CLK_SEL_XTL;
+}
+
+uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
+{
+    switch (cpu_freq) {
+        case RTC_CPU_FREQ_XTAL:
+            return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ;
+        case RTC_CPU_FREQ_2M:
+            return 2 * MHZ;
+        case RTC_CPU_FREQ_80M:
+            return 80 * MHZ;
+        case RTC_CPU_FREQ_160M:
+            return 160 * MHZ;
+        case RTC_CPU_FREQ_240M:
+            return 240 * MHZ;
+        case RTC_CPU_320M_80M:
+            return 80 * MHZ;
+        case RTC_CPU_320M_160M:
+            return 160 * MHZ;
+        default:
+            assert(false && "invalid rtc_cpu_freq_t value");
+            return 0;
+    }
+}
+
+bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t* out_val)
+{
+    if (mhz == 240) {
+        *out_val = RTC_CPU_FREQ_240M;
+    } else if (mhz == 160) {
+        *out_val = RTC_CPU_FREQ_160M;
+    } else if (mhz == 80) {
+        *out_val = RTC_CPU_FREQ_80M;
+    } else if (mhz == (int) rtc_clk_xtal_freq_get()) {
+        *out_val = RTC_CPU_FREQ_XTAL;
+    } else if (mhz == 2) {
+        *out_val = RTC_CPU_FREQ_2M;
+    } else {
+        return false;
+    }
+    return true;
+}
+
+/* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
+ * lower and upper 16-bit halves. These are the routines to work with such a
+ * representation.
+ */
+static bool clk_val_is_valid(uint32_t val) {
+    return (val & 0xffff) == ((val >> 16) & 0xffff) &&
+            val != 0 &&
+            val != UINT32_MAX;
+}
+
+static uint32_t reg_val_to_clk_val(uint32_t val) {
+    return val & UINT16_MAX;
+}
+
+static uint32_t clk_val_to_reg_val(uint32_t val) {
+    return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
+}
+
+rtc_xtal_freq_t rtc_clk_xtal_freq_get()
+{
+    /* We may have already written XTAL value into RTC_XTAL_FREQ_REG */
+    uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
+    if (!clk_val_is_valid(xtal_freq_reg)) {
+        SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
+        return RTC_XTAL_FREQ_AUTO;
+    }
+    return reg_val_to_clk_val(xtal_freq_reg);
+}
+
+void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
+{
+    WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
+}
+
+static rtc_xtal_freq_t rtc_clk_xtal_freq_estimate()
+{
+    /* Enable 8M/256 clock if needed */
+    const bool clk_8m_enabled = rtc_clk_8m_enabled();
+    const bool clk_8md256_enabled = rtc_clk_8md256_enabled();
+    if (!clk_8md256_enabled) {
+        rtc_clk_8m_enable(true, true);
+    }
+
+    uint64_t cal_val = rtc_clk_cal_ratio(RTC_CAL_8MD256, XTAL_FREQ_EST_CYCLES);
+    /* cal_val contains period of 8M/256 clock in XTAL clock cycles
+     * (shifted by RTC_CLK_CAL_FRACT bits).
+     * Xtal frequency will be (cal_val * 8M / 256) / 2^19
+     */
+    uint32_t freq_mhz = (cal_val * RTC_FAST_CLK_FREQ_APPROX / MHZ / 256 ) >> RTC_CLK_CAL_FRACT;
+    /* Guess the XTAL type. For now, only 40 and 26MHz are supported.
+     */
+    switch (freq_mhz) {
+        case 21 ... 31:
+            return RTC_XTAL_FREQ_26M;
+        case 32 ... 33:
+            SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 26 MHz", freq_mhz);
+            return RTC_XTAL_FREQ_26M;
+        case 34 ... 35:
+            SOC_LOGW(TAG, "Potentially bogus XTAL frequency: %d MHz, guessing 40 MHz", freq_mhz);
+            return RTC_XTAL_FREQ_40M;
+        case 36 ... 45:
+            return RTC_XTAL_FREQ_40M;
+        default:
+            SOC_LOGW(TAG, "Bogus XTAL frequency: %d MHz", freq_mhz);
+            return RTC_XTAL_FREQ_AUTO;
+    }
+    /* Restore 8M and 8md256 clocks to original state */
+    rtc_clk_8m_enable(clk_8m_enabled, clk_8md256_enabled);
+}
+
+void rtc_clk_apb_freq_update(uint32_t apb_freq)
+{
+    WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
+}
+
+uint32_t rtc_clk_apb_freq_get()
+{
+    uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
+    // round to the nearest MHz
+    freq_hz += MHZ / 2;
+    uint32_t remainder = freq_hz % MHZ;
+    return freq_hz - remainder;
+}
+
+void rtc_clk_divider_set(uint32_t div)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
+    REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, div);
+    SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
+}
+
+void rtc_clk_8m_divider_set(uint32_t div)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
+    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, div);
+    SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
+}
+
+void rtc_clk_init(rtc_clk_config_t cfg)
+{
+    rtc_cpu_freq_t cpu_source_before = rtc_clk_cpu_freq_get();
+    
+    /* If we get a TG WDT system reset while running at 240MHz,
+     * DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
+     * APB and CPU frequencies after reset. This will cause issues with XTAL
+     * frequency estimation, so we switch to XTAL frequency first.
+     *
+     * Ideally we would only do this if SYSCON_SOC_CLK_SEL == PLL and
+     * PLL is configured for 480M, but it takes less time to switch to 40M and
+     * run the following code than querying the PLL does.
+     */
+    if (REG_GET_FIELD(SYSCON_SYSCLK_CONF_REG, SYSCON_SOC_CLK_SEL) == SYSCON_SOC_CLK_SEL_PLL) {
+        rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
+    }
+
+    /* Set tuning parameters for 8M and 150k clocks.
+     * Note: this doesn't attempt to set the clocks to precise frequencies.
+     * Instead, we calibrate these clocks against XTAL frequency later, when necessary.
+     * - SCK_DCAP value controls tuning of 150k clock.
+     *   The higher the value of DCAP is, the lower is the frequency.
+     * - CK8M_DFREQ value controls tuning of 8M clock.
+     *   CLK_8M_DFREQ constant gives the best temperature characteristics.
+     */
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
+    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
+
+    /* Configure 150k clock division */
+    rtc_clk_divider_set(cfg.clk_rtc_clk_div);
+    /* Configure 8M clock division */
+    rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
+
+    /* Enable the internal bus used to configure PLLs */
+    SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
+    CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
+
+    /* Estimate XTAL frequency */
+    rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
+    if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
+        if (clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
+            /* XTAL frequency has already been set, use existing value */
+            xtal_freq = rtc_clk_xtal_freq_get();
+        } else {
+            /* Not set yet, estimate XTAL frequency based on RTC_FAST_CLK */
+            xtal_freq = rtc_clk_xtal_freq_estimate();
+            if (xtal_freq == RTC_XTAL_FREQ_AUTO) {
+                SOC_LOGW(TAG, "Can't estimate XTAL frequency, assuming 26MHz");
+                xtal_freq = RTC_XTAL_FREQ_26M;
+            }
+        }
+    } else if (!clk_val_is_valid(READ_PERI_REG(RTC_XTAL_FREQ_REG))) {
+        /* Exact frequency was set in sdkconfig, but still warn if autodetected
+         * frequency is different. If autodetection failed, worst case we get a
+         * bit of garbage output.
+         */
+        rtc_xtal_freq_t est_xtal_freq = rtc_clk_xtal_freq_estimate();
+        if (est_xtal_freq != xtal_freq) {
+            SOC_LOGW(TAG, "Possibly invalid CONFIG_ESP32_XTAL_FREQ setting (%dMHz). Detected %d MHz.",
+                    xtal_freq, est_xtal_freq);
+        }
+    }
+    uart_tx_wait_idle(0);
+    rtc_clk_xtal_freq_update(xtal_freq);
+    rtc_clk_apb_freq_update(xtal_freq * MHZ);
+    /* Set CPU frequency */
+    rtc_clk_cpu_freq_set(cfg.cpu_freq);
+    
+    /* Re-calculate the ccount to make time calculation correct. */    
+    uint32_t freq_before = rtc_clk_cpu_freq_value(cpu_source_before) / MHZ;
+    uint32_t freq_after = rtc_clk_cpu_freq_value(cfg.cpu_freq) / MHZ;
+    XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
+
+    /* Slow & fast clocks setup */
+    if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
+        rtc_clk_32k_enable(true);
+    }
+    if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
+        bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
+        rtc_clk_8m_enable(true, need_8md256);
+    }
+    rtc_clk_fast_freq_set(cfg.fast_freq);
+    rtc_clk_slow_freq_set(cfg.slow_freq);
+}
+
+/* Name used in libphy.a:phy_chip_v7.o
+ * TODO: update the library to use rtc_clk_xtal_freq_get
+ */
+rtc_xtal_freq_t rtc_get_xtal() __attribute__((alias("rtc_clk_xtal_freq_get")));
diff --git a/components/soc/esp32s2beta/rtc_init.c b/components/soc/esp32s2beta/rtc_init.c
new file mode 100644
index 000000000..c4ce147a4
--- /dev/null
+++ b/components/soc/esp32s2beta/rtc_init.c
@@ -0,0 +1,237 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+
+#include "soc/soc.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/dport_reg.h"
+#include "soc/efuse_reg.h"
+#include "soc/gpio_reg.h"
+#include "soc/spi_mem_reg.h"
+#include "i2c_rtc_clk.h"
+
+/* Various delays to be programmed into power control state machines */
+#define RTC_CNTL_XTL_BUF_WAIT_SLP   2
+#define RTC_CNTL_PLL_BUF_WAIT_SLP   2
+#define RTC_CNTL_CK8M_WAIT_SLP      4
+#define OTHER_BLOCKS_POWERUP        1
+#define OTHER_BLOCKS_WAIT           1
+
+#define ROM_RAM_POWERUP_CYCLES   OTHER_BLOCKS_POWERUP
+#define ROM_RAM_WAIT_CYCLES      OTHER_BLOCKS_WAIT
+
+#define WIFI_POWERUP_CYCLES      OTHER_BLOCKS_POWERUP
+#define WIFI_WAIT_CYCLES         OTHER_BLOCKS_WAIT
+
+#define RTC_POWERUP_CYCLES       OTHER_BLOCKS_POWERUP
+#define RTC_WAIT_CYCLES          OTHER_BLOCKS_WAIT
+
+#define DG_WRAP_POWERUP_CYCLES   OTHER_BLOCKS_POWERUP
+#define DG_WRAP_WAIT_CYCLES      OTHER_BLOCKS_WAIT
+
+#define RTC_MEM_POWERUP_CYCLES   OTHER_BLOCKS_POWERUP
+#define RTC_MEM_WAIT_CYCLES      OTHER_BLOCKS_WAIT
+
+#ifndef CONFIG_HARDWARE_IS_FPGA
+void rtc_init(rtc_config_t cfg)
+{
+    CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
+
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, cfg.xtal_wait);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
+
+    /* Moved from rtc sleep to rtc init to save sleep function running time */
+    // set shortest possible sleep time limit
+    REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
+
+    /* This power domian removed
+    * set rom&ram timer
+    * REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_CYCLES);
+    * REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES);
+    */
+    // set wifi timer
+    REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, WIFI_POWERUP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, WIFI_WAIT_CYCLES);
+    // set rtc peri timer
+    REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, RTC_POWERUP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, RTC_WAIT_CYCLES);
+    // set digital wrap timer
+    REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, DG_WRAP_POWERUP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, DG_WRAP_WAIT_CYCLES);
+    // set rtc memory timer
+    REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, RTC_MEM_POWERUP_CYCLES);
+    REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, RTC_MEM_WAIT_CYCLES);
+
+    SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG,
+            RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD);
+
+    /* Reset RTC bias to default value (needed if waking up from deep sleep) */
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10);
+
+    if (cfg.clkctl_init) {
+        //clear CMMU clock force on
+        CLEAR_PERI_REG_MASK(DPORT_PRO_CACHE_MMU_POWER_CTRL_REG, DPORT_PRO_CACHE_MMU_MEM_FORCE_ON);
+        //clear rom clock force on
+        REG_SET_FIELD(DPORT_ROM_CTRL_0_REG, DPORT_ROM_FO, 0);
+        //clear sram clock force on
+        REG_SET_FIELD(DPORT_SRAM_CTRL_0_REG, DPORT_SRAM_FO, 0);
+        //clear tag clock force on
+        CLEAR_PERI_REG_MASK(DPORT_PRO_DCACHE_TAG_POWER_CTRL_REG, DPORT_PRO_DCACHE_TAG_MEM_FORCE_ON);
+        CLEAR_PERI_REG_MASK(DPORT_PRO_ICACHE_TAG_POWER_CTRL_REG, DPORT_PRO_ICACHE_TAG_MEM_FORCE_ON);
+        //clear register clock force on
+        CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
+        CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
+    }
+    if (cfg.pwrctl_init) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
+        //cancel xtal force pu if no need to force power up
+        //cannot cancel xtal force pu if pll is force power on
+        if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
+            CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
+        } else {
+            SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
+        }
+        // cancel BIAS force pu
+        // CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FORCE_PU);
+        // CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PU);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
+        // bias follow 8M
+        // SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_CORE_FOLW_8M);
+        // SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FOLW_8M);
+        SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_SLEEP_FOLW_8M);
+        // CLEAR APLL close
+        CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
+        SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
+
+        //cancel bbpll force pu if setting no force power up
+        if (!cfg.bbpll_fpu) {
+            CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
+            CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
+            CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
+        } else {
+            SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
+            SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);  
+            SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
+        }
+        //cancel RTC REG force PU
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PWC_FORCE_PU);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
+
+        //combine two rtc memory options
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO);
+
+        if (cfg.rtc_dboost_fpd) {
+            SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
+        } else {
+            CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
+        }
+        //cancel digital pu force
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
+
+        /* If this mask is enabled, all soc memories cannot enter power down mode */
+        /* We should control soc memory power down mode from RTC, so we will not touch this register any more */
+        CLEAR_PERI_REG_MASK(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK);
+        /* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
+        /* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
+        rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
+        rtc_sleep_pd(pd_cfg);
+
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
+        // ROM_RAM power domain is removed
+        // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_PU);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
+        // CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
+        //cancel digital PADS force no iso
+        //wangqiang ++
+        rom_i2c_writeReg_Mask(0x6a,1,0,1,0,2);
+
+        rom_i2c_writeReg_Mask(0x6a,1,2,5,4,2);
+
+#ifdef CONFIG_CHIP_IS_ESP32
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_UNHOLD);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_FORCE_NOISO);
+#endif
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
+#ifdef CONFIG_CHIP_IS_ESP32
+        SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PAD_AUTOHOLD_EN);
+        SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_DG_PAD_AUTOHOLD_EN);
+#endif
+    }
+}
+#endif
+
+rtc_vddsdio_config_t rtc_vddsdio_get_config()
+{
+    rtc_vddsdio_config_t result;
+    uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
+    result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
+    result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
+    result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
+    if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
+        // Get configuration from RTC
+        result.force = 1;
+        result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
+        result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
+        return result;
+    }
+#if 0
+    uint32_t efuse_reg = REG_READ(EFUSE_BLK0_RDATA4_REG);
+    if (efuse_reg & EFUSE_RD_SDIO_FORCE) {
+        // Get configuration from EFUSE
+        result.force = 0;
+        result.enable = (efuse_reg & EFUSE_RD_XPD_SDIO_REG_M) >> EFUSE_RD_XPD_SDIO_REG_S;
+        result.tieh = (efuse_reg & EFUSE_RD_SDIO_TIEH_M) >> EFUSE_RD_SDIO_TIEH_S;
+        //DREFH/M/L eFuse are used for EFUSE_ADC_VREF instead. Therefore tuning
+        //will only be available on older chips that don't have EFUSE_ADC_VREF
+        if(REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG ,EFUSE_RD_BLK3_PART_RESERVE) == 0){
+            //BLK3_PART_RESERVE indicates the presence of EFUSE_ADC_VREF
+            // in this case, DREFH/M/L are also set from EFUSE
+            result.drefh = (efuse_reg & EFUSE_RD_SDIO_DREFH_M) >> EFUSE_RD_SDIO_DREFH_S;
+            result.drefm = (efuse_reg & EFUSE_RD_SDIO_DREFM_M) >> EFUSE_RD_SDIO_DREFM_S;
+            result.drefl = (efuse_reg & EFUSE_RD_SDIO_DREFL_M) >> EFUSE_RD_SDIO_DREFL_S;
+        }
+        return result;
+    }
+#endif
+
+    // Otherwise, VDD_SDIO is controlled by bootstrapping pin
+    uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
+    result.force = 0;
+    result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
+    result.enable = 1;
+    return result;
+}
+
+void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
+{
+    uint32_t val = 0;
+    val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
+    val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
+    val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
+    val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
+    val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
+    val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
+    val |= RTC_CNTL_SDIO_PD_EN;
+    REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
+}
diff --git a/components/soc/esp32s2beta/rtc_pm.c b/components/soc/esp32s2beta/rtc_pm.c
new file mode 100644
index 000000000..e6dae0435
--- /dev/null
+++ b/components/soc/esp32s2beta/rtc_pm.c
@@ -0,0 +1,67 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include <assert.h>
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/apb_ctrl_reg.h"
+
+typedef enum {
+    PM_LIGHT_SLEEP = BIT(2),        /*!< WiFi PD, memory in light sleep */
+} pm_sleep_mode_t;
+
+typedef enum{
+    PM_SW_NOREJECT = 0,
+    PM_SW_REJECT   = 1
+} pm_sw_reject_t;
+
+
+/* These MAC-related functions are defined in the closed source part of
+ * RTC library
+ */
+extern void pm_mac_init();
+extern int pm_check_mac_idle();
+extern void pm_mac_deinit();
+
+/* This sleep-related function is called from the closed source part of RTC
+ * library.
+ */
+pm_sw_reject_t pm_set_sleep_mode(pm_sleep_mode_t sleep_mode, void(*pmac_save_params)())
+{
+    (void) pmac_save_params; /* unused */
+
+    pm_mac_deinit();
+    if (pm_check_mac_idle()) {
+        pm_mac_init();
+        return PM_SW_REJECT;
+    }
+
+    rtc_sleep_config_t cfg = { 0 };
+
+    switch (sleep_mode) {
+        case PM_LIGHT_SLEEP:
+            cfg.wifi_pd_en = 1;
+            cfg.dig_dbias_wak = 4;
+            cfg.dig_dbias_slp = 0;
+            cfg.rtc_dbias_wak = 0;
+            cfg.rtc_dbias_slp = 0;
+            rtc_sleep_init(cfg);
+            break;
+
+        default:
+            assert(0 && "unsupported sleep mode");
+    }
+    return PM_SW_NOREJECT;
+}
diff --git a/components/soc/esp32s2beta/rtc_sleep.c b/components/soc/esp32s2beta/rtc_sleep.c
new file mode 100644
index 000000000..bef529005
--- /dev/null
+++ b/components/soc/esp32s2beta/rtc_sleep.c
@@ -0,0 +1,189 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include "soc/soc.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/apb_ctrl_reg.h"
+#include "soc/dport_reg.h"
+#include "soc/rtc.h"
+#include "soc/i2s_reg.h"
+#include "soc/timer_group_reg.h"
+#include "soc/bb_reg.h"
+#include "soc/nrx_reg.h"
+#include "soc/fe_reg.h"
+#include "soc/rtc.h"
+#include "rom/ets_sys.h"
+
+#define MHZ (1000000)
+
+/**
+ * Configure whether certain peripherals are powered down in deep sleep
+ * @param cfg power down flags as rtc_sleep_pd_config_t structure
+ */
+void rtc_sleep_pd(rtc_sleep_pd_config_t cfg)
+{
+    REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
+    REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
+    REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_FORCE_LPU, cfg.rtc_fpu);
+    //DPORT_REG_SET_FIELD(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK, ~cfg.cpu_pd);
+    REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_PLC_MEM_FORCE_PU, cfg.i2s_fpu);
+    REG_SET_FIELD(I2S_PD_CONF_REG(0), I2S_FIFO_FORCE_PU, cfg.i2s_fpu);
+    REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_DC_MEM_FORCE_PU, cfg.fe_fpu);
+    REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
+    REG_SET_FIELD(APB_CTRL_FRONT_END_MEM_PD_REG, APB_CTRL_AGC_MEM_FORCE_PU, cfg.fe_fpu);
+    REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
+    REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
+    REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
+    REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
+    REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
+    REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
+    REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
+}
+
+void rtc_sleep_init(rtc_sleep_config_t cfg)
+{
+    /* Already defined in rtc init 
+    // set 5 PWC state machine times to fit in main state machine time
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, RTC_CNTL_XTL_BUF_WAIT_SLP);
+    REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP);
+    */
+    /* I don't think it worthes to run this function everytime as it is just a test option */
+    if (cfg.lslp_mem_inf_fpu)
+    {
+        rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(1);
+        rtc_sleep_pd(pd_cfg);
+    }
+
+    /* This option seems to be unneccessary 
+    if (cfg.rtc_mem_inf_fpu) {
+        SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
+    }
+    */
+
+    if (cfg.rtc_mem_inf_follow_cpu) {
+        SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FOLW_CPU);
+    }
+
+    if (cfg.rtc_fastmem_pd_en) {
+        SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_PD_EN);
+    }
+
+    if (cfg.rtc_slowmem_pd_en) {
+        SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_SLOWMEM_PD_EN);
+    }
+
+    if (cfg.rtc_peri_pd_en) {
+        SET_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_PD_EN);
+    }
+
+    if (cfg.wifi_pd_en) {
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_PD_EN);
+    }
+
+    /*
+#ifdef CONFIG_CHIP_IS_ESP32
+    if (cfg.rom_mem_pd_en) {
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_PD_EN);
+    }
+#endif
+    */
+
+    if (cfg.deep_slp) {
+        /* redundant ? People may not want to touch such registers after init
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG,
+                RTC_CNTL_DG_PAD_FORCE_ISO | RTC_CNTL_DG_PAD_FORCE_NOISO);
+        
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG,
+                RTC_CNTL_DG_WRAP_FORCE_PU | RTC_CNTL_DG_WRAP_FORCE_PD);
+        
+#ifdef CONFIG_CHIP_IS_ESP32
+        CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_FORCE_NOSLEEP);
+#endif
+        */
+        REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT);
+        SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
+        // Shut down parts of RTC which may have been left enabled by the wireless drivers
+        CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
+                RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
+                RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
+    } else {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
+        REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, 0);
+    }
+
+    /* enable VDDSDIO control by state machine */
+    REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
+    REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
+
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, cfg.rtc_dbias_slp);
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, cfg.rtc_dbias_wak);
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, cfg.dig_dbias_wak);
+    REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_SLP, cfg.dig_dbias_slp);
+
+    REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
+    REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
+}
+
+void rtc_sleep_set_wakeup_time(uint64_t t)
+{
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
+    WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
+}
+
+uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
+{
+    REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
+    REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
+
+    /* Start entry into sleep mode */
+    SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
+
+    while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
+            RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
+        ;
+    }
+    /* In deep sleep mode, we never get here */
+    uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
+    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
+            RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
+
+    /* restore config if it is a light sleep */
+    if (lslp_mem_inf_fpu)
+    {
+        rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
+        rtc_sleep_pd(pd_cfg);
+    }
+    /* move setting from init to sleep, so we don't need to have this any more
+    * restore DBG_ATTEN to the default value
+    REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_DBG_ATTEN, RTC_CNTL_DBG_ATTEN_DEFAULT);
+    */
+    return reject;
+}
diff --git a/components/soc/esp32s2beta/rtc_time.c b/components/soc/esp32s2beta/rtc_time.c
new file mode 100644
index 000000000..8011611a4
--- /dev/null
+++ b/components/soc/esp32s2beta/rtc_time.c
@@ -0,0 +1,166 @@
+// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include <stdint.h>
+#include "rom/ets_sys.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/timer_group_reg.h"
+
+#define MHZ (1000000)
+
+/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
+ * This feature counts the number of XTAL clock cycles within a given number of
+ * RTC_SLOW_CLK cycles.
+ *
+ * Slow clock calibration feature has two modes of operation: one-off and cycling.
+ * In cycling mode (which is enabled by default on SoC reset), counting of XTAL
+ * cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
+ * using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
+ * once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
+ * enabled using TIMG_RTC_CALI_START bit.
+ */
+
+/**
+ * @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
+ * @param cal_clk which clock to calibrate
+ * @param slowclk_cycles number of slow clock cycles to count
+ * @return number of XTAL clock cycles within the given number of slow clock cycles
+ */
+uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    /* Enable requested clock (150k clock is always on) */
+    int dig_32k_xtal_state = REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN);
+    if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_state) {
+        REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, 1);
+    }
+
+    if (cal_clk == RTC_CAL_8MD256) {
+        SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
+    }
+    /* Prepare calibration */
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
+    REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
+    /* Figure out how long to wait for calibration to finish */
+
+    /* Set timeout reg and expect time delay*/
+    uint32_t expected_freq;
+    if (cal_clk == RTC_CAL_32K_XTAL) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 12));
+        expected_freq = 32768;
+    } else if (cal_clk == RTC_CAL_8MD256) {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 12));
+        expected_freq = RTC_FAST_CLK_FREQ_APPROX / 256;
+    } else {
+        REG_SET_FIELD(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT_THRES, (slowclk_cycles << 10));
+        expected_freq = 150000;
+    }
+    uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
+    
+    /* Start calibration */
+    CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+    SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
+
+    /* Wait for calibration to finish up to another us_time_estimate */
+    ets_delay_us(us_time_estimate);
+    uint32_t cal_val;
+    while (true) {
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
+            cal_val = REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
+            break;
+        }
+        if (GET_PERI_REG_MASK(TIMG_RTCCALICFG2_REG(0), TIMG_RTC_CALI_TIMEOUT)) {
+            cal_val = 0;
+            break;
+        }
+    }
+
+    REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN, dig_32k_xtal_state);
+
+    if (cal_clk == RTC_CAL_8MD256) {
+        CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_CLK8M_D256_EN);
+    }
+
+    return cal_val;
+}
+
+uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
+    uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
+    uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
+    return ratio;
+}
+
+uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
+{
+    rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
+    uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
+    uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
+    uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
+    uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
+    return period;
+}
+
+uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
+{
+    /* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
+     * TODO: fix overflow.
+     */
+    return (time_in_us << RTC_CLK_CAL_FRACT) / period;
+}
+
+uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
+{
+    return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
+}
+
+uint64_t rtc_time_get()
+{
+    SET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_UPDATE);
+    while (GET_PERI_REG_MASK(RTC_CNTL_TIME_UPDATE_REG, RTC_CNTL_TIME_VALID) == 0) {
+        ets_delay_us(1); // might take 1 RTC slowclk period, don't flood RTC bus
+    }
+    SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG, RTC_CNTL_TIME_VALID_INT_CLR);
+    uint64_t t = READ_PERI_REG(RTC_CNTL_TIME0_REG);
+    t |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME1_REG)) << 32;
+    return t;
+}
+
+uint64_t rtc_light_slp_time_get()
+{
+    uint64_t t_wake = READ_PERI_REG(RTC_CNTL_TIME_LOW0_REG);
+    t_wake |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH0_REG)) << 32;
+    uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
+    t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
+    return (t_wake - t_slp);
+}
+
+uint64_t rtc_deep_slp_time_get()
+{
+    uint64_t t_slp = READ_PERI_REG(RTC_CNTL_TIME_LOW1_REG);
+    t_slp |= ((uint64_t) READ_PERI_REG(RTC_CNTL_TIME_HIGH1_REG)) << 32;
+    uint64_t t_wake = rtc_time_get();
+    return (t_wake - t_slp);
+}
+
+void rtc_clk_wait_for_slow_cycle() //This function may not by useful any more
+{
+    SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE);
+    while (GET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_SLOW_CLK_NEXT_EDGE)) {
+        ets_delay_us(1);
+    }
+}
+
diff --git a/components/soc/esp32s2beta/soc_log.h b/components/soc/esp32s2beta/soc_log.h
new file mode 100644
index 000000000..4cd669e11
--- /dev/null
+++ b/components/soc/esp32s2beta/soc_log.h
@@ -0,0 +1,29 @@
+// Copyright 2016-2017 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#pragma once
+
+/**
+ * @file soc_log.h
+ * @brief SOC library logging functions
+ *
+ * To make SOC library compatible with environments which don't use ESP-IDF,
+ * this header file provides wrappers for logging functions.
+ */
+
+#define SOC_LOGE(tag, fmt, ...) ets_printf("%s(err): " fmt, tag, ##__VA_ARGS__)
+#define SOC_LOGW(tag, fmt, ...) ets_printf("%s(warn): " fmt, tag, ##__VA_ARGS__)
+#define SOC_LOGI(tag, fmt, ...) ets_printf("%s(info): " fmt, tag, ##__VA_ARGS__)
+#define SOC_LOGD(tag, fmt, ...) ets_printf("%s(dbg): " fmt, tag, ##__VA_ARGS__)
+#define SOC_LOGV(tag, fmt, ...) ets_printf("%s: " fmt, tag, ##__VA_ARGS__)
diff --git a/components/soc/esp32s2beta/soc_memory_layout.c b/components/soc/esp32s2beta/soc_memory_layout.c
new file mode 100644
index 000000000..02bf28d2f
--- /dev/null
+++ b/components/soc/esp32s2beta/soc_memory_layout.c
@@ -0,0 +1,148 @@
+// Copyright 2010-2016 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+#ifndef BOOTLOADER_BUILD
+
+#include <stdlib.h>
+#include <stdint.h>
+
+#include "soc/soc.h"
+#include "soc/soc_memory_layout.h"
+#include "esp_heap_caps.h"
+#include "sdkconfig.h"
+
+/* Memory layout for ESP32 SoC */
+
+/*
+Memory type descriptors. These describe the capabilities of a type of memory in the SoC. Each type of memory
+map consist of one or more regions in the address space.
+
+Each type contains an array of prioritised capabilities; types with later entries are only taken if earlier
+ones can't fulfill the memory request.
+
+The prioritised capabilities work roughly like this:
+- For a normal malloc (MALLOC_CAP_DEFAULT), give away the DRAM-only memory first, then pass off any dual-use IRAM regions,
+  finally eat into the application memory.
+- For a malloc where 32-bit-aligned-only access is okay, first allocate IRAM, then DRAM, finally application IRAM.
+- Application mallocs (PIDx) will allocate IRAM first, if possible, then DRAM.
+- Most other malloc caps only fit in one region anyway.
+
+*/
+const soc_memory_type_desc_t soc_memory_types[] = {
+    //Type 0: DRAM
+    { "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, false},
+    // Type 1: DRAM used for startup stacks
+    { "DRAM", { MALLOC_CAP_8BIT|MALLOC_CAP_DEFAULT, MALLOC_CAP_INTERNAL|MALLOC_CAP_DMA|MALLOC_CAP_32BIT, 0 }, false, true},
+    //Type 2: DRAM which has an alias on the I-port
+    //(This DRAM is also the region used by ROM during startup)
+    { "D/IRAM", { 0, MALLOC_CAP_DMA|MALLOC_CAP_8BIT|MALLOC_CAP_INTERNAL|MALLOC_CAP_DEFAULT, MALLOC_CAP_32BIT|MALLOC_CAP_EXEC }, true, true},
+    //Type 3: IRAM
+    { "IRAM", { MALLOC_CAP_EXEC|MALLOC_CAP_32BIT|MALLOC_CAP_INTERNAL, 0, 0 }, false, false},
+    //Type 4: SPI SRAM data
+    //TODO, in fact, part of them support EDMA, to be supported.
+    { "SPIRAM", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
+    //Type 5: SPI SRAM data from AHB DBUS3, slower than normal
+    //TODO, add a bit to control the access of it
+#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
+    { "SPIRAM(Slow)", { MALLOC_CAP_SPIRAM|MALLOC_CAP_DEFAULT, 0, MALLOC_CAP_8BIT|MALLOC_CAP_32BIT}, false, false},
+#endif
+};
+
+const size_t soc_memory_type_count = sizeof(soc_memory_types)/sizeof(soc_memory_type_desc_t);
+
+/*
+Region descriptors. These describe all regions of memory available, and map them to a type in the above type.
+
+Because of requirements in the coalescing code which merges adjacent regions, this list should always be sorted
+from low to high start address.
+*/
+const soc_memory_region_t soc_memory_regions[] = {
+#ifdef CONFIG_SPIRAM_SUPPORT
+    { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW, 4, 0}, //SPI SRAM, if available
+#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
+    { SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH - SOC_SLOW_EXTRAM_DATA_LOW, 5, 0}, //SPI SRAM, if available
+#endif
+#endif
+#if CONFIG_INSTRUCTION_CACHE_8KB
+#if CONFIG_DATA_CACHE_0KB
+    { 0x3FFB2000, 0x2000, 0, 0x400B2000}, //Block 1, can be use as I/D cache memory
+    { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
+    { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
+#elif CONFIG_DATA_CACHE_8KB
+    { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
+    { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
+#else
+    { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
+#endif
+#else
+#if CONFIG_DATA_CACHE_0KB
+    { 0x3FFB4000, 0x2000, 0, 0x400B4000}, //Block 2, can be use as D cache memory
+    { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
+#elif CONFIG_DATA_CACHE_8KB
+    { 0x3FFB6000, 0x2000, 0, 0x400B6000}, //Block 3, can be use as D cache memory
+#endif
+#endif
+    { 0x3FFB8000, 0x4000, 0, 0x40028000}, //Block 4,  can be remapped to ROM, can be used as trace memory
+    { 0x3FFBC000, 0x4000, 0, 0x4002C000}, //Block 5,  can be remapped to ROM, can be used as trace memory
+    { 0x3FFC0000, 0x4000, 0, 0x40030000}, //Block 6,  can be used as trace memory
+    { 0x3FFC4000, 0x4000, 0, 0x40034000}, //Block 7,  can be used as trace memory
+    { 0x3FFC8000, 0x4000, 0, 0x40038000}, //Block 8,  can be used as trace memory
+    { 0x3FFCC000, 0x4000, 0, 0x4003C000}, //Block 9,  can be used as trace memory
+
+    { 0x3FFD0000, 0x4000, 0, 0x40040000}, //Block 10,  can be used as trace memory
+    { 0x3FFD4000, 0x4000, 0, 0x40044000}, //Block 11,  can be used as trace memory
+    { 0x3FFD8000, 0x4000, 0, 0x40048000}, //Block 12,  can be used as trace memory
+    { 0x3FFDC000, 0x4000, 0, 0x4004C000}, //Block 13,  can be used as trace memory
+    { 0x3FFE0000, 0x4000, 0, 0x40050000}, //Block 14,  can be used as trace memory
+    { 0x3FFE4000, 0x4000, 0, 0x40054000}, //Block 15,  can be used as trace memory
+    { 0x3FFE8000, 0x4000, 0, 0x40058000}, //Block 16,  can be used as trace memory
+    { 0x3FFEC000, 0x4000, 0, 0x4005C000}, //Block 17,  can be used as trace memory
+    { 0x3FFF0000, 0x4000, 0, 0x40060000}, //Block 18,  can be used for MAC dump, can be used as trace memory
+    { 0x3FFF4000, 0x4000, 0, 0x40064000}, //Block 19,  can be used for MAC dump, can be used as trace memory
+    { 0x3FFF8000, 0x4000, 0, 0x40068000}, //Block 20,  can be used for MAC dump, can be used as trace memory
+    { 0x3FFFC000, 0x4000, 1, 0x4006C000}, //Block 21,  can be used for MAC dump, can be used as trace memory, used for startup stack
+};
+
+const size_t soc_memory_region_count = sizeof(soc_memory_regions)/sizeof(soc_memory_region_t);
+
+
+extern int _data_start_xtos;
+/* Reserved memory regions
+
+   These are removed from the soc_memory_regions array when heaps are created.
+ */
+const soc_reserved_region_t soc_reserved_regions[] = {
+//    { 0x40070000, 0x40078000 }, //CPU0 cache region
+//    { 0x40078000, 0x40080000 }, //CPU1 cache region
+
+    { 0x3fff8000, (intptr_t)&_data_start_xtos}, //ROM data region
+
+#if CONFIG_MEMMAP_TRACEMEM
+#if CONFIG_MEMMAP_TRACEMEM_TWOBANKS
+    { 0x3fff8000, 0x40000000 }, //Reserve trace mem region
+#else
+    { 0x3fff8000, 0x3fffc000 }, //Reserve trace mem region
+#endif
+#endif
+
+#ifdef CONFIG_SPIRAM_SUPPORT
+    { SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_HIGH}, //SPI RAM gets added later if needed, in spiram.c; reserve it for now
+#if CONFIG_USE_AHB_DBUS3_ACCESS_SPIRAM
+    { SOC_SLOW_EXTRAM_DATA_LOW, SOC_SLOW_EXTRAM_DATA_HIGH}, //SPI RAM(Slow) gets added later if needed, in spiram.c; reserve it for now
+#endif
+#endif
+};
+
+const size_t soc_reserved_region_count = sizeof(soc_reserved_regions)/sizeof(soc_reserved_region_t);
+
+#endif
diff --git a/components/soc/esp32s2beta/sources.cmake b/components/soc/esp32s2beta/sources.cmake
new file mode 100644
index 000000000..35eb8810c
--- /dev/null
+++ b/components/soc/esp32s2beta/sources.cmake
@@ -0,0 +1,12 @@
+set(SOC_SRCS    "rtc_clk.c"
+                "rtc_init.c"
+                "rtc_pm.c"
+                "rtc_sleep.c"
+                "rtc_time.c"
+                "soc_memory_layout.c"
+                "spi_periph.c")
+
+if(NOT CMAKE_BUILD_EARLY_EXPANSION)
+    set_source_files_properties("esp32s2beta/rtc_clk.c" PROPERTIES
+                                COMPILE_FLAGS "-fno-jump-tables -fno-tree-switch-conversion")
+endif()
diff --git a/components/soc/esp32s2beta/spi_periph.c b/components/soc/esp32s2beta/spi_periph.c
new file mode 100644
index 000000000..9c8fe230b
--- /dev/null
+++ b/components/soc/esp32s2beta/spi_periph.c
@@ -0,0 +1,123 @@
+// Copyright 2015-2018 Espressif Systems (Shanghai) PTE LTD
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+
+//     http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+
+#include "soc/spi_periph.h"
+#include "stddef.h"
+
+/*
+ Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
+*/
+const spi_signal_conn_t spi_periph_signal[4] = {
+    {
+        .spiclk_out = SPICLK_OUT_IDX,
+        .spiclk_in = 0,/* SPI clock is not an input signal*/
+        .spid_out = SPID_OUT_IDX,
+        .spiq_out = SPIQ_OUT_IDX,
+        .spiwp_out = SPIWP_OUT_IDX,
+        .spihd_out = SPIHD_OUT_IDX,
+        .spid_in = SPID_IN_IDX,
+        .spiq_in = SPIQ_IN_IDX,
+        .spiwp_in = SPIWP_IN_IDX,
+        .spihd_in = SPIHD_IN_IDX,
+        .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */
+        .spics_in = 0,/* SPI cs is not an input signal*/
+        .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS,
+        .irq = ETS_SPI1_INTR_SOURCE,
+        .irq_dma = ETS_SPI1_DMA_INTR_SOURCE,
+        .module = PERIPH_SPI_MODULE,
+        .hw = (spi_dev_t *) &SPIMEM1,
+        .func = SPI_FUNC_NUM,
+    }, {
+        .spiclk_out = FSPICLK_OUT_MUX_IDX,
+        .spiclk_in = FSPICLK_IN_IDX,
+        .spid_out = FSPID_OUT_IDX,
+        .spiq_out = FSPIQ_OUT_IDX,
+        .spiwp_out = FSPIWP_OUT_IDX,
+        .spihd_out = FSPIHD_OUT_IDX,
+        .spid_in = FSPID_IN_IDX,
+        .spiq_in = FSPIQ_IN_IDX,
+        .spiwp_in = FSPIWP_IN_IDX,
+        .spihd_in = FSPIHD_IN_IDX,
+        .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX},
+        .spics_in = FSPICS0_IN_IDX,
+        .spiclk_iomux_pin = FSPI_IOMUX_PIN_NUM_CLK,
+        .spid_iomux_pin = FSPI_IOMUX_PIN_NUM_MOSI,
+        .spiq_iomux_pin = FSPI_IOMUX_PIN_NUM_MISO,
+        .spiwp_iomux_pin = FSPI_IOMUX_PIN_NUM_WP,
+        .spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD,
+        .spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS,
+        .irq = ETS_SPI2_INTR_SOURCE,
+        .irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
+        .module = PERIPH_FSPI_MODULE,
+        .hw = &GPSPI2,
+        .func = FSPI_FUNC_NUM,
+    }, {
+        .spiclk_out = SPI3_CLK_OUT_MUX_IDX,
+        .spiclk_in = SPI3_CLK_IN_IDX,
+        .spid_out = SPI3_D_OUT_IDX,
+        .spiq_out = SPI3_Q_OUT_IDX,
+        //SPI3 doesn't have wp and hd signals
+        .spiwp_out = -1,
+        .spihd_out = -1,
+        .spid_in = SPI3_D_IN_IDX,
+        .spiq_in = SPI3_Q_IN_IDX,
+        .spiwp_in = -1,
+        .spihd_in = -1,
+        .spics_out = {SPI3_CS0_OUT_IDX, SPI3_CS1_OUT_IDX, SPI3_CS2_OUT_IDX},
+        .spics_in = SPI3_CS0_IN_IDX,
+        //SPI3 doesn't have iomux pins
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = ETS_SPI3_INTR_SOURCE,
+        .irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
+        .module = PERIPH_HSPI_MODULE,
+        .hw = &GPSPI3,
+        .func = -1,
+    }, {
+        .spiclk_out = SPI4_CLK_OUT_MUX_IDX,
+        .spiclk_in = SPI4_CLK_IN_IDX,
+        .spid_out = SPI4_D_OUT_IDX,
+        .spiq_out = SPI4_Q_OUT_IDX,
+        //SPI4 doesn't have wp and hd signals
+        .spiwp_out = -1,
+        .spihd_out = -1,
+        .spid_in = SPI4_D_IN_IDX,
+        .spiq_in = SPI4_Q_IN_IDX,
+        .spiwp_in = -1,
+        .spihd_in = -1,
+        .spics_out = {SPI4_CS0_OUT_IDX, SPI4_CS1_OUT_IDX, SPI4_CS2_OUT_IDX},
+        .spics_in = SPI4_CS0_IN_IDX,
+        //SPI4 doesn't have iomux pins
+        .spiclk_iomux_pin = -1,
+        .spid_iomux_pin = -1,
+        .spiq_iomux_pin = -1,
+        .spiwp_iomux_pin = -1,
+        .spihd_iomux_pin = -1,
+        .spics0_iomux_pin = -1,
+        .irq = ETS_SPI4_INTR_SOURCE,
+        .irq_dma = ETS_SPI4_DMA_INTR_SOURCE,
+        .module = PERIPH_VSPI_MODULE,
+        .hw = &GPSPI4,
+        .func = -1,
+    }
+};
diff --git a/components/soc/esp32s2beta/test/test_rtc_clk.c b/components/soc/esp32s2beta/test/test_rtc_clk.c
new file mode 100644
index 000000000..53b437881
--- /dev/null
+++ b/components/soc/esp32s2beta/test/test_rtc_clk.c
@@ -0,0 +1,284 @@
+#include <stdio.h>
+#include "unity.h"
+#include "rom/ets_sys.h"
+#include "rom/uart.h"
+#include "soc/rtc.h"
+#include "soc/rtc_cntl_reg.h"
+#include "soc/rtc_io_reg.h"
+#include "soc/sens_reg.h"
+#include "soc/io_mux_reg.h"
+#include "driver/rtc_io.h"
+#include "test_utils.h"
+#include "freertos/FreeRTOS.h"
+#include "freertos/task.h"
+#include "freertos/semphr.h"
+#include "../esp_clk_internal.h"
+#include "esp_clk.h"
+
+
+#ifdef CONFIG_CHIP_IS_ESP32
+#define CALIBRATE_ONE(cali_clk) calibrate_one(cali_clk, #cali_clk)
+
+static uint32_t calibrate_one(rtc_cal_sel_t cal_clk, const char* name)
+{
+    const uint32_t cal_count = 1000;
+    const float factor = (1 << 19) * 1000.0f;
+    uint32_t cali_val;
+    printf("%s:\n", name);
+    for (int i = 0; i < 5; ++i) {
+        printf("calibrate (%d): ", i);
+        cali_val = rtc_clk_cal(cal_clk, cal_count);
+        printf("%.3f kHz\n", factor / (float) cali_val);
+    }
+    return cali_val;
+}
+
+TEST_CASE("RTC_SLOW_CLK sources calibration", "[rtc_clk]")
+{
+    rtc_clk_32k_enable(true);
+    rtc_clk_8m_enable(true, true);
+
+    CALIBRATE_ONE(RTC_CAL_RTC_MUX);
+    CALIBRATE_ONE(RTC_CAL_8MD256);
+    uint32_t cal_32k = CALIBRATE_ONE(RTC_CAL_32K_XTAL);
+
+    if (cal_32k == 0) {
+        printf("32K XTAL OSC has not started up");
+    } else {
+        printf("switching to RTC_SLOW_FREQ_32K_XTAL: ");
+        rtc_clk_slow_freq_set(RTC_SLOW_FREQ_32K_XTAL);
+        printf("done\n");
+
+        CALIBRATE_ONE(RTC_CAL_RTC_MUX);
+        CALIBRATE_ONE(RTC_CAL_8MD256);
+        CALIBRATE_ONE(RTC_CAL_32K_XTAL);
+    }
+
+    printf("switching to RTC_SLOW_FREQ_8MD256: ");
+    rtc_clk_slow_freq_set(RTC_SLOW_FREQ_8MD256);
+    printf("done\n");
+
+    CALIBRATE_ONE(RTC_CAL_RTC_MUX);
+    CALIBRATE_ONE(RTC_CAL_8MD256);
+    CALIBRATE_ONE(RTC_CAL_32K_XTAL);
+}
+
+/* The following two are not unit tests, but are added here to make it easy to
+ * check the frequency of 150k/32k oscillators. The following two "tests" will
+ * output either 32k or 150k clock to GPIO25.
+ */
+
+static void pull_out_clk(int sel)
+{
+    REG_SET_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M);
+    REG_CLR_BIT(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_RDE_M | RTC_IO_PDAC1_RUE_M);
+    REG_SET_FIELD(RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_FUN_SEL, 1);
+    REG_SET_FIELD(SENS_SAR_DAC_CTRL1_REG, SENS_DEBUG_BIT_SEL, 0);
+    REG_SET_FIELD(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_SEL0, sel);
+}
+
+TEST_CASE("Output 150k clock to GPIO25", "[rtc_clk][ignore]")
+{
+    pull_out_clk(RTC_IO_DEBUG_SEL0_150K_OSC);
+}
+
+TEST_CASE("Output 32k XTAL clock to GPIO25", "[rtc_clk][ignore]")
+{
+    rtc_clk_32k_enable(true);
+    pull_out_clk(RTC_IO_DEBUG_SEL0_32K_XTAL);
+}
+
+TEST_CASE("Output 8M XTAL clock to GPIO25", "[rtc_clk][ignore]")
+{
+    rtc_clk_8m_enable(true, true);
+    SET_PERI_REG_MASK(RTC_IO_RTC_DEBUG_SEL_REG, RTC_IO_DEBUG_12M_NO_GATING);
+    pull_out_clk(RTC_IO_DEBUG_SEL0_8M);
+}
+
+static void test_clock_switching(void (*switch_func)(rtc_cpu_freq_t))
+{
+    uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
+
+    const int test_duration_sec = 10;
+    ref_clock_init();
+    uint64_t t_start = ref_clock_get();
+
+    rtc_cpu_freq_t cur_freq = rtc_clk_cpu_freq_get();
+    int count = 0;
+    while (ref_clock_get() - t_start < test_duration_sec * 1000000) {
+        switch_func(RTC_CPU_FREQ_XTAL);
+        switch_func(cur_freq);
+        ++count;
+    }
+    uint64_t t_end = ref_clock_get();
+    printf("Switch count: %d. Average time to switch PLL -> XTAL -> PLL: %d us\n", count, (int) ((t_end - t_start) / count));
+    ref_clock_deinit();
+}
+
+TEST_CASE("Calculate 8M clock frequency", "[rtc_clk]")
+{
+    // calibrate 8M/256 clock against XTAL, get 8M/256 clock period
+    uint32_t rtc_8md256_period = rtc_clk_cal(RTC_CAL_8MD256, 100);
+    uint32_t rtc_fast_freq_hz = 1000000ULL * (1 << RTC_CLK_CAL_FRACT) * 256 / rtc_8md256_period;
+    printf("RTC_FAST_CLK=%d Hz\n", rtc_fast_freq_hz);
+    TEST_ASSERT_INT32_WITHIN(500000, RTC_FAST_CLK_FREQ_APPROX, rtc_fast_freq_hz);
+}
+
+TEST_CASE("Test switching between PLL and XTAL", "[rtc_clk]")
+{
+    test_clock_switching(rtc_clk_cpu_freq_set);
+}
+
+TEST_CASE("Test fast switching between PLL and XTAL", "[rtc_clk]")
+{
+    test_clock_switching(rtc_clk_cpu_freq_set_fast);
+}
+
+#define COUNT_TEST      3
+#define TIMEOUT_TEST_MS (5 + CONFIG_ESP32_RTC_CLK_CAL_CYCLES / 16)
+
+void stop_rtc_external_quartz(){
+    const uint8_t pin_32 = 32;
+    const uint8_t pin_33 = 33;
+    const uint8_t mask_32 = (1 << (pin_32 - 32));
+    const uint8_t mask_33 = (1 << (pin_33 - 32));
+
+    rtc_clk_32k_enable(false);
+
+    gpio_pad_select_gpio(pin_32);
+    gpio_pad_select_gpio(pin_33);
+    gpio_output_set_high(0, mask_32 | mask_33, mask_32 | mask_33, 0);
+    ets_delay_us(500000);
+    gpio_output_set_high(0, 0, 0, mask_32 | mask_33); // disable pins
+}
+
+static void start_freq(rtc_slow_freq_t required_src_freq, uint32_t start_delay_ms)
+{
+    int i = 0, fail = 0;
+    uint32_t start_time;
+    uint32_t end_time;
+    rtc_slow_freq_t selected_src_freq;
+    stop_rtc_external_quartz();
+#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+    uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
+    printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
+            bootstrap_cycles,
+            CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
+#else
+    uint32_t bootstrap_cycles = 5;
+    printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
+            bootstrap_cycles,
+            CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
+#endif
+    if (start_delay_ms == 0 && CONFIG_ESP32_RTC_CLK_CAL_CYCLES < 1500){
+        start_delay_ms = 50;
+        printf("Recommended increase Number of cycles for RTC_SLOW_CLK calibration to 3000!\n");
+    }
+    while(i < COUNT_TEST){
+        start_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
+        i++;
+        printf("attempt #%d/%d...", i, COUNT_TEST);
+        rtc_clk_32k_bootstrap(bootstrap_cycles);
+        ets_delay_us(start_delay_ms * 1000);
+        rtc_clk_select_rtc_slow_clk();
+        selected_src_freq = rtc_clk_slow_freq_get();
+        end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
+        printf(" [time=%d] ", (end_time - start_time) - start_delay_ms);
+        if(selected_src_freq != required_src_freq){
+            printf("FAIL. Time measurement...");
+            fail = 1;
+        } else {
+            printf("PASS. Time measurement...");
+        }
+        uint64_t clk_rtc_time;
+        uint32_t fail_measure = 0;
+        for (int j = 0; j < 3; ++j) {
+            clk_rtc_time = esp_clk_rtc_time();
+            ets_delay_us(1000000);
+            uint64_t delta = esp_clk_rtc_time() - clk_rtc_time;
+            if (delta < 900000LL || delta > 1100000){
+                printf("FAIL");
+                fail = 1;
+                fail_measure = 1;
+                break;
+            }
+        }
+        if(fail_measure == 0) {
+            printf("PASS");
+        }
+        printf(" [calibration val = %d] \n", esp_clk_slowclk_cal_get());
+        stop_rtc_external_quartz();
+        ets_delay_us(500000);
+    }
+    TEST_ASSERT_MESSAGE(fail == 0, "Test failed");
+    printf("Test passed successfully\n");
+}
+
+#ifdef CONFIG_SPIRAM_SUPPORT
+// PSRAM tests run on ESP-WROVER-KIT boards, which have the 32k XTAL installed.
+// Other tests may run on DevKitC boards, which don't have a 32k XTAL.
+TEST_CASE("Test starting external RTC quartz", "[rtc_clk]")
+{
+    int i = 0, fail = 0;
+    uint32_t start_time;
+    uint32_t end_time;
+    stop_rtc_external_quartz();
+#ifdef CONFIG_ESP32_RTC_CLOCK_SOURCE_EXTERNAL_CRYSTAL
+    uint32_t bootstrap_cycles = CONFIG_ESP32_RTC_XTAL_BOOTSTRAP_CYCLES;
+    printf("Test is started. Kconfig settings:\n External 32K crystal is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
+            bootstrap_cycles,
+            CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
+#else
+    uint32_t bootstrap_cycles = 5;
+    printf("Test is started. Kconfig settings:\n Internal RC is selected,\n Oscillation cycles = %d,\n Calibration cycles = %d.\n",
+            bootstrap_cycles,
+            CONFIG_ESP32_RTC_CLK_CAL_CYCLES);
+#endif
+    if (CONFIG_ESP32_RTC_CLK_CAL_CYCLES < 1500){
+        printf("Recommended increase Number of cycles for RTC_SLOW_CLK calibration to 3000!\n");
+    }
+    while(i < COUNT_TEST){
+        start_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
+        i++;
+        printf("attempt #%d/%d...", i, COUNT_TEST);
+        rtc_clk_32k_bootstrap(bootstrap_cycles);
+        rtc_clk_select_rtc_slow_clk();
+        end_time = xTaskGetTickCount() * (1000 / configTICK_RATE_HZ);
+        printf(" [time=%d] ", end_time - start_time);
+        if((end_time - start_time) > TIMEOUT_TEST_MS){
+            printf("FAIL\n");
+            fail = 1;
+        } else {
+            printf("PASS\n");
+        }
+        stop_rtc_external_quartz();
+        ets_delay_us(100000);
+    }
+    TEST_ASSERT_MESSAGE(fail == 0, "Test failed");
+    printf("Test passed successfully\n");
+}
+
+TEST_CASE("Test starting 'External 32kHz XTAL' on the board with it.", "[rtc_clk]")
+{
+    start_freq(RTC_SLOW_FREQ_32K_XTAL, 200);
+    start_freq(RTC_SLOW_FREQ_32K_XTAL, 0);
+}
+
+#else
+
+TEST_CASE("Test starting 'External 32kHz XTAL' on the board without it.", "[rtc_clk][ignore]")
+{
+    printf("Tries to start the 'External 32kHz XTAL' on the board without it. "
+            "Clock switching to 'Internal 150 kHz RC oscillator'.\n");
+
+    printf("This test will be successful for boards without an external crystal or non-working crystal. "
+            "First, there will be an attempt to start from the external crystal after a failure "
+            "will switch to the internal RC circuit. If the switch to the internal RC circuit "
+            "was successful then the test succeeded.\n");
+
+    start_freq(RTC_SLOW_FREQ_RTC, 200);
+    start_freq(RTC_SLOW_FREQ_RTC, 0);
+}
+
+#endif // CONFIG_SPIRAM_SUPPORT
+#endif
diff --git a/components/soc/include/soc/soc_memory_layout.h b/components/soc/include/soc/soc_memory_layout.h
index 6fb8c6519..86c5e0f72 100644
--- a/components/soc/include/soc/soc_memory_layout.h
+++ b/components/soc/include/soc/soc_memory_layout.h
@@ -160,10 +160,12 @@ inline static bool IRAM_ATTR esp_ptr_executable(const void *p)
 
 inline static bool IRAM_ATTR esp_ptr_byte_accessible(const void *p)
 {
+    intptr_t ip = (intptr_t) p;
     bool r;
-    r = ((intptr_t)p >= SOC_BYTE_ACCESSIBLE_LOW && (intptr_t)p < SOC_BYTE_ACCESSIBLE_HIGH);
-#if CONFIG_ESP32_SPIRAM_SUPPORT
-    r |= ((intptr_t)p >= SOC_EXTRAM_DATA_LOW && (intptr_t)p < SOC_EXTRAM_DATA_HIGH);
+    r = (ip >= SOC_BYTE_ACCESSIBLE_LOW && ip < SOC_BYTE_ACCESSIBLE_HIGH);
+#if CONFIG_ESP32_SPIRAM_SUPPORT && CONFIG_SPIRAM_SIZE
+// ToDo: Use SOC_EXTRAM_DATA_HIGH if CONFIG_SPIRAM_SIZE is -1 (ie max possible SPIRAM size)
+    r |= (ip >= SOC_EXTRAM_DATA_LOW && ip < (SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE));
 #endif
     return r;
 }
diff --git a/components/soc/include/soc/spi_periph.h b/components/soc/include/soc/spi_periph.h
index 812c1beca..88bc64353 100644
--- a/components/soc/include/soc/spi_periph.h
+++ b/components/soc/include/soc/spi_periph.h
@@ -21,12 +21,22 @@
 #include "soc/spi_reg.h"
 #include "soc/spi_struct.h"
 #include "soc/gpio_sig_map.h"
+#include "sdkconfig.h"
 
 #ifdef __cplusplus
 extern "C"
 {
 #endif
 
+#ifdef CONFIG_IDF_TARGET_ESP32S2BETA
+#define SPI_FREAD_DIO 0
+#define SPI_FREAD_QIO 0
+#define SPI_FWRITE_DIO 0
+#define SPI_FWRITE_QIO 0
+#endif
+
+
+
 /*
  Stores a bunch of per-spi-peripheral data.
 */
@@ -43,6 +53,10 @@ typedef struct {
     const uint8_t spihd_in;
     const uint8_t spics_out[3];     // /CS GPIO output mux signals
     const uint8_t spics_in;
+    const uint8_t spidqs_out;
+    const uint8_t spidqs_in;
+    const uint8_t spicd_out;
+    const uint8_t spicd_in;
     const uint8_t spiclk_iomux_pin;    //IO pins of IO_MUX muxed signals
     const uint8_t spid_iomux_pin;
     const uint8_t spiq_iomux_pin;
@@ -53,9 +67,10 @@ typedef struct {
     const uint8_t irq_dma;          //dma irq source for interrupt mux
     const periph_module_t module;   //peripheral module, for enabling clock etc
     spi_dev_t *hw;              //Pointer to the hardware registers
+    const int func;
 } spi_signal_conn_t;
 
-extern const spi_signal_conn_t spi_periph_signal[3];
+extern const spi_signal_conn_t spi_periph_signal[SPI_PERIPH_NUM];
 
 #ifdef __cplusplus
 }