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Merge branch 'feature/esp32s2_ref_clock_use_ll_of_rmt_pcnt' into 'master'

Browse source 
rmt/esp32s2: Update RMT: reg, struct, LL and test_utils/ref_clock.c

See merge request espressif/esp-idf!7514
This commit is contained in:
Ivan Grokhotkov 2020-02-09 20:03:32 +08:00
parent 4bfd0b961b daa9c30c8e
commit 91111263f9
5 changed files with 213 additions and 122 deletions
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2
components/esp32s2/ld/esp32s2.peripherals.ld
View file

@ -13,7 +13,7 @@ PROVIDE ( I2C0 = 0x3f413000 );
PROVIDE ( UHCI0 = 0x3f414000 );
PROVIDE ( HOST = 0x3f415000 );
PROVIDE ( RMT = 0x3f416000 );
PROVIDE ( RMTMEM = 0x3f416800 );
PROVIDE ( RMTMEM = 0x3f416400 );
PROVIDE ( PCNT = 0x3f417000 );
PROVIDE ( SLC = 0x3f418000 );
PROVIDE ( LEDC = 0x3f419000 );

4
components/soc/esp32s2/include/hal/rmt_ll.h
View file

@ -55,12 +55,12 @@ static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enabl
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->conf_ch[channel].conf0.mem_pd = enable;
dev->apb_conf.mem_force_pd = enable;
}
static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev, uint32_t channel)
{
return dev->conf_ch[channel].conf0.mem_pd;
return dev->apb_conf.mem_force_pd;
}
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)

122
components/soc/esp32s2/include/soc/rmt_reg.h
View file

@ -780,6 +780,30 @@ extern "C" {
#define RMT_APB_MEM_WADDR_CH3_S 0
#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x0050)
/* RMT_CH3_RX_THR_EVENT_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_RX_THR_EVENT_INT_RAW (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_RAW_M (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH3_RX_THR_EVENT_INT_RAW_S 23
/* RMT_CH2_RX_THR_EVENT_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define RMT_CH2_RX_THR_EVENT_INT_RAW (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_RAW_M (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH2_RX_THR_EVENT_INT_RAW_S 22
/* RMT_CH1_RX_THR_EVENT_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define RMT_CH1_RX_THR_EVENT_INT_RAW (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_RAW_M (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH1_RX_THR_EVENT_INT_RAW_S 21
/* RMT_CH0_RX_THR_EVENT_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_CH0_RX_THR_EVENT_INT_RAW (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_RAW_M (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_RAW_V 0x1
#define RMT_CH0_RX_THR_EVENT_INT_RAW_S 20
/* RMT_CH3_TX_LOOP_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_TX_LOOP_INT_RAW (BIT(19))
@ -902,6 +926,30 @@ extern "C" {
#define RMT_CH0_TX_END_INT_RAW_S 0
#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x0054)
/* RMT_CH3_RX_THR_EVENT_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_RX_THR_EVENT_INT_ST (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_ST_M (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_ST_V 0x1
#define RMT_CH3_RX_THR_EVENT_INT_ST_S 23
/* RMT_CH2_RX_THR_EVENT_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define RMT_CH2_RX_THR_EVENT_INT_ST (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_ST_M (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_ST_V 0x1
#define RMT_CH2_RX_THR_EVENT_INT_ST_S 22
/* RMT_CH1_RX_THR_EVENT_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define RMT_CH1_RX_THR_EVENT_INT_ST (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_ST_M (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_ST_V 0x1
#define RMT_CH1_RX_THR_EVENT_INT_ST_S 21
/* RMT_CH0_RX_THR_EVENT_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_CH0_RX_THR_EVENT_INT_ST (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_ST_M (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_ST_V 0x1
#define RMT_CH0_RX_THR_EVENT_INT_ST_S 20
/* RMT_CH3_TX_LOOP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_TX_LOOP_INT_ST (BIT(19))
@ -1024,6 +1072,30 @@ extern "C" {
#define RMT_CH0_TX_END_INT_ST_S 0
#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x0058)
/* RMT_CH3_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_RX_THR_EVENT_INT_ENA (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_ENA_M (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_ENA_V 0x1
#define RMT_CH3_RX_THR_EVENT_INT_ENA_S 23
/* RMT_CH2_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define RMT_CH2_RX_THR_EVENT_INT_ENA (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_ENA_M (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_ENA_V 0x1
#define RMT_CH2_RX_THR_EVENT_INT_ENA_S 22
/* RMT_CH1_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define RMT_CH1_RX_THR_EVENT_INT_ENA (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_ENA_M (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_ENA_V 0x1
#define RMT_CH1_RX_THR_EVENT_INT_ENA_S 21
/* RMT_CH0_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_CH0_RX_THR_EVENT_INT_ENA (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_ENA_M (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_ENA_V 0x1
#define RMT_CH0_RX_THR_EVENT_INT_ENA_S 20
/* RMT_CH3_TX_LOOP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_TX_LOOP_INT_ENA (BIT(19))
@ -1146,6 +1218,30 @@ extern "C" {
#define RMT_CH0_TX_END_INT_ENA_S 0
#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x005c)
/* RMT_CH3_RX_THR_EVENT_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_RX_THR_EVENT_INT_CLR (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_CLR_M (BIT(23))
#define RMT_CH3_RX_THR_EVENT_INT_CLR_V 0x1
#define RMT_CH3_RX_THR_EVENT_INT_CLR_S 23
/* RMT_CH2_RX_THR_EVENT_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */
/*description: */
#define RMT_CH2_RX_THR_EVENT_INT_CLR (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_CLR_M (BIT(22))
#define RMT_CH2_RX_THR_EVENT_INT_CLR_V 0x1
#define RMT_CH2_RX_THR_EVENT_INT_CLR_S 22
/* RMT_CH1_RX_THR_EVENT_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */
/*description: */
#define RMT_CH1_RX_THR_EVENT_INT_CLR (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_CLR_M (BIT(21))
#define RMT_CH1_RX_THR_EVENT_INT_CLR_V 0x1
#define RMT_CH1_RX_THR_EVENT_INT_CLR_S 21
/* RMT_CH0_RX_THR_EVENT_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_CH0_RX_THR_EVENT_INT_CLR (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_CLR_M (BIT(20))
#define RMT_CH0_RX_THR_EVENT_INT_CLR_V 0x1
#define RMT_CH0_RX_THR_EVENT_INT_CLR_S 20
/* RMT_CH3_TX_LOOP_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */
/*description: */
#define RMT_CH3_TX_LOOP_INT_CLR (BIT(19))
@ -1324,6 +1420,12 @@ extern "C" {
#define RMT_CARRIER_LOW_CH3_S 0
#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x0070)
/* RMT_RX_LIM_CH0 : R/W ;bitpos:[29:21] ;default: 9'h80 ; */
/*description: */
#define RMT_RX_LIM_CH0 0x000001FF
#define RMT_RX_LIM_CH0_M ((RMT_RX_LIM_CH0_V)<<(RMT_RX_LIM_CH0_S))
#define RMT_RX_LIM_CH0_V 0x1FF
#define RMT_RX_LIM_CH0_S 21
/* RMT_LOOP_COUNT_RESET_CH0 : WO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20))
@ -1350,6 +1452,12 @@ extern "C" {
#define RMT_TX_LIM_CH0_S 0
#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x0074)
/* RMT_RX_LIM_CH1 : R/W ;bitpos:[29:21] ;default: 9'h80 ; */
/*description: */
#define RMT_RX_LIM_CH1 0x000001FF
#define RMT_RX_LIM_CH1_M ((RMT_RX_LIM_CH1_V)<<(RMT_RX_LIM_CH1_S))
#define RMT_RX_LIM_CH1_V 0x1FF
#define RMT_RX_LIM_CH1_S 21
/* RMT_LOOP_COUNT_RESET_CH1 : WO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20))
@ -1376,6 +1484,12 @@ extern "C" {
#define RMT_TX_LIM_CH1_S 0
#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x0078)
/* RMT_RX_LIM_CH2 : R/W ;bitpos:[29:21] ;default: 9'h80 ; */
/*description: */
#define RMT_RX_LIM_CH2 0x000001FF
#define RMT_RX_LIM_CH2_M ((RMT_RX_LIM_CH2_V)<<(RMT_RX_LIM_CH2_S))
#define RMT_RX_LIM_CH2_V 0x1FF
#define RMT_RX_LIM_CH2_S 21
/* RMT_LOOP_COUNT_RESET_CH2 : WO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20))
@ -1402,6 +1516,12 @@ extern "C" {
#define RMT_TX_LIM_CH2_S 0
#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x007c)
/* RMT_RX_LIM_CH3 : R/W ;bitpos:[29:21] ;default: 9'h80 ; */
/*description: */
#define RMT_RX_LIM_CH3 0x000001FF
#define RMT_RX_LIM_CH3_M ((RMT_RX_LIM_CH3_V)<<(RMT_RX_LIM_CH3_S))
#define RMT_RX_LIM_CH3_V 0x1FF
#define RMT_RX_LIM_CH3_S 21
/* RMT_LOOP_COUNT_RESET_CH3 : WO ;bitpos:[20] ;default: 1'b0 ; */
/*description: */
#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20))
@ -1580,7 +1700,7 @@ extern "C" {
#define RMT_CARRIER_LOW_THRES_CH3_S 0
#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x0fc)
/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */
/* RMT_DATE : R/W ;bitpos:[31:0] ;default: 32'h19080700 ; */
/*description: */
#define RMT_DATE 0xFFFFFFFF
#define RMT_DATE_M ((RMT_DATE_V)<<(RMT_DATE_S))

106
components/soc/esp32s2/include/soc/rmt_struct.h
View file

@ -31,8 +31,7 @@ typedef volatile struct {
uint32_t carrier_eff_en: 1;
uint32_t carrier_en: 1;
uint32_t carrier_out_lv: 1;
uint32_t mem_pd: 1;
uint32_t clk_en: 1;
uint32_t reserved30: 2;
};
uint32_t val;
} conf0;
@ -52,8 +51,7 @@ typedef volatile struct {
uint32_t idle_out_lv: 1;
uint32_t idle_out_en: 1;
uint32_t tx_stop: 1;
uint32_t carrier_per: 5;
uint32_t reserved26: 6;
uint32_t reserved21: 11;
};
uint32_t val;
} conf1;
@ -105,7 +103,11 @@ typedef volatile struct {
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t reserved20: 12;
uint32_t ch0_rx_thr_event: 1;
uint32_t ch1_rx_thr_event: 1;
uint32_t ch2_rx_thr_event: 1;
uint32_t ch3_rx_thr_event: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} int_raw;
@ -131,7 +133,11 @@ typedef volatile struct {
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t reserved20: 12;
uint32_t ch0_rx_thr_event: 1;
uint32_t ch1_rx_thr_event: 1;
uint32_t ch2_rx_thr_event: 1;
uint32_t ch3_rx_thr_event: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} int_st;
@ -157,7 +163,11 @@ typedef volatile struct {
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t reserved20: 12;
uint32_t ch0_rx_thr_event: 1;
uint32_t ch1_rx_thr_event: 1;
uint32_t ch2_rx_thr_event: 1;
uint32_t ch3_rx_thr_event: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} int_ena;
@ -183,7 +193,11 @@ typedef volatile struct {
uint32_t ch1_tx_loop: 1;
uint32_t ch2_tx_loop: 1;
uint32_t ch3_tx_loop: 1;
uint32_t reserved20: 12;
uint32_t ch0_rx_thr_event: 1;
uint32_t ch1_rx_thr_event: 1;
uint32_t ch2_rx_thr_event: 1;
uint32_t ch3_rx_thr_event: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} int_clr;
@ -200,15 +214,20 @@ typedef volatile struct {
uint32_t tx_loop_num: 10;
uint32_t tx_loop_cnt_en: 1;
uint32_t loop_count_reset: 1;
uint32_t reserved21: 11;
uint32_t rx_lim: 9;
uint32_t reserved30: 2;
};
uint32_t val;
} tx_lim_ch[4];
union {
struct {
uint32_t fifo_mask: 1;
uint32_t mem_tx_wrap_en: 1;
uint32_t reserved2: 30;
uint32_t fifo_mask: 1;
uint32_t mem_tx_wrap_en: 1;
uint32_t mem_clk_force_on: 1;
uint32_t mem_force_pd: 1;
uint32_t mem_force_pu: 1;
uint32_t reserved5: 26;
uint32_t clk_en: 1;
};
uint32_t val;
} apb_conf;
@ -235,64 +254,15 @@ typedef volatile struct {
} ref_cnt_rst;
union {
struct {
uint32_t carrier_low_num_ch0: 15;
uint32_t carrier_high_num_ch0:15;
uint32_t reserved30: 2;
uint32_t carrier_low_thres_ch: 16;
uint32_t carrier_high_thres_ch:16;
};
uint32_t val;
} ch0_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch0: 16;
uint32_t carrier_high_thres_ch0:16;
};
uint32_t val;
} ch0_rx_carrier_rm;
union {
struct {
uint32_t carrier_low_num_ch1: 15;
uint32_t carrier_high_num_ch1:15;
uint32_t reserved30: 2;
};
uint32_t val;
} ch1_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch1: 16;
uint32_t carrier_high_thres_ch1:16;
};
uint32_t val;
} ch1_rx_carrier_rm;
union {
struct {
uint32_t carrier_low_num_ch2: 15;
uint32_t carrier_high_num_ch2:15;
uint32_t reserved30: 2;
};
uint32_t val;
} ch2_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch2: 16;
uint32_t carrier_high_thres_ch2:16;
};
uint32_t val;
} ch2_rx_carrier_rm;
union {
struct {
uint32_t carrier_low_num_ch3: 15;
uint32_t carrier_high_num_ch3:15;
uint32_t reserved30: 2;
};
uint32_t val;
} ch3_rx_carrier_st;
union {
struct {
uint32_t carrier_low_thres_ch3: 16;
uint32_t carrier_high_thres_ch3:16;
};
uint32_t val;
} ch3_rx_carrier_rm;
} ch_rx_carrier_rm[4];
uint32_t reserved_9c;
uint32_t reserved_a0;
uint32_t reserved_a4;
uint32_t reserved_a8;
uint32_t reserved_ac;
uint32_t reserved_b0;
uint32_t reserved_b4;

101
tools/unit-test-app/components/test_utils/ref_clock.c
View file

@ -31,17 +31,25 @@
*/
#include "test_utils.h"
#include "soc/rmt_periph.h"
#include "soc/pcnt_periph.h"
#include "soc/soc.h"
#include "hal/rmt_hal.h"
#include "hal/rmt_ll.h"
#include "soc/pcnt_caps.h"
#include "hal/pcnt_hal.h"
#include "soc/gpio_periph.h"
#include "soc/dport_reg.h"
#include "esp_intr_alloc.h"
#include "freertos/FreeRTOS.h"
#include "driver/periph_ctrl.h"
#if CONFIG_IDF_TARGET_ESP32
#include "esp32/rom/gpio.h"
#elif CONFIG_IDF_TARGET_ESP32S2
#include "esp32s2/rom/gpio.h"
#endif
#include "sdkconfig.h"
/* Select which RMT and PCNT channels, and GPIO to use */
#define REF_CLOCK_RMT_CHANNEL RMT_CHANNEL_MAX - 1
#define REF_CLOCK_PCNT_UNIT 0
#define REF_CLOCK_GPIO 21
@ -53,23 +61,20 @@ static intr_handle_t s_intr_handle;
static portMUX_TYPE s_lock = portMUX_INITIALIZER_UNLOCKED;
static volatile uint32_t s_milliseconds;
#if CONFIG_IDF_TARGET_ESP32
#define REF_CLOCK_RMT_CHANNEL 7
static int get_pcnt_sig(void)
{
#if CONFIG_IDF_TARGET_ESP32
return (REF_CLOCK_PCNT_UNIT < 5) ?
PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT :
PCNT_SIG_CH0_IN5_IDX + 4 * (REF_CLOCK_PCNT_UNIT - 5);
}
#elif CONFIG_IDF_TARGET_ESP32S2
#define REF_CLOCK_RMT_CHANNEL 3
static int get_pcnt_sig(void)
{
return PCNT_SIG_CH0_IN0_IDX + 4 * REF_CLOCK_PCNT_UNIT;
}
#endif
}
static rmt_hal_context_t s_rmt;
static pcnt_hal_context_t s_pcnt;
void ref_clock_init()
{
@ -78,31 +83,26 @@ void ref_clock_init()
// Route RMT output to GPIO matrix
gpio_matrix_out(REF_CLOCK_GPIO, RMT_SIG_OUT0_IDX + REF_CLOCK_RMT_CHANNEL, false, false);
// Initialize RMT
periph_module_enable(PERIPH_RMT_MODULE);
RMT.apb_conf.fifo_mask = 1;
rmt_hal_init(&s_rmt);
rmt_ll_enable_mem_access(s_rmt.regs, true);
rmt_item32_t data = {
.duration0 = 1,
.level0 = 1,
.duration1 = 0,
.level1 = 0
};
RMTMEM.chan[REF_CLOCK_RMT_CHANNEL].data32[0] = data;
RMTMEM.chan[REF_CLOCK_RMT_CHANNEL].data32[1].val = 0;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.clk_en = 1;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_start = 0;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.mem_owner = 0;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.mem_rd_rst = 1;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.apb_mem_rst = 1;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.carrier_en = 0;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.div_cnt = 1;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.mem_size = 1;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.ref_always_on = 0;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_conti_mode = 1;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_start = 1;
rmt_hal_transmit(&s_rmt, REF_CLOCK_RMT_CHANNEL, &data, 1, 0);
rmt_ll_start_tx(s_rmt.regs, REF_CLOCK_RMT_CHANNEL);
rmt_ll_set_mem_owner(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 0);
rmt_ll_reset_tx_pointer(s_rmt.regs, REF_CLOCK_RMT_CHANNEL);
rmt_ll_enable_tx_carrier(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, false);
rmt_ll_set_counter_clock_div(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 1);
rmt_ll_set_mem_blocks(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 1);
rmt_ll_set_counter_clock_src(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, 0);
rmt_ll_enable_tx_cyclic(s_rmt.regs, REF_CLOCK_RMT_CHANNEL, true);
rmt_ll_start_tx(s_rmt.regs, REF_CLOCK_RMT_CHANNEL);
// Route signal to PCNT
int pcnt_sig_idx = get_pcnt_sig();
@ -115,36 +115,35 @@ void ref_clock_init()
// Initialize PCNT
periph_module_enable(PERIPH_PCNT_MODULE);
pcnt_hal_init(&s_pcnt, REF_CLOCK_PCNT_UNIT);
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_hctrl_mode = 0;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_lctrl_mode = 0;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_pos_mode = 1;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.ch0_neg_mode = 1;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_l_lim_en = 0;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_h_lim_en = 1;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_zero_en = 0;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_thres0_en = 0;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf0.thr_thres1_en = 0;
PCNT.conf_unit[REF_CLOCK_PCNT_UNIT].conf2.cnt_h_lim = REF_CLOCK_PRESCALER_MS * 1000;
pcnt_ll_set_mode(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_CHANNEL_0,
PCNT_COUNT_INC, PCNT_COUNT_INC,
PCNT_MODE_KEEP, PCNT_MODE_KEEP);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_L_LIM);
pcnt_ll_event_enable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_H_LIM);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_ZERO);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_THRES_0);
pcnt_ll_event_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_THRES_1);
pcnt_ll_set_event_value(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, PCNT_EVT_H_LIM, REF_CLOCK_PRESCALER_MS * 1000);
// Enable PCNT and wait for it to start counting
PCNT.ctrl.val &= ~(BIT(REF_CLOCK_PCNT_UNIT * 2 + 1));
PCNT.ctrl.val |= BIT(REF_CLOCK_PCNT_UNIT * 2);
PCNT.ctrl.val &= ~BIT(REF_CLOCK_PCNT_UNIT * 2);
pcnt_ll_counter_resume(s_pcnt.dev, REF_CLOCK_PCNT_UNIT);
pcnt_ll_counter_clear(s_pcnt.dev, REF_CLOCK_PCNT_UNIT);
ets_delay_us(10000);
// Enable interrupt
s_milliseconds = 0;
ESP_ERROR_CHECK(esp_intr_alloc(ETS_PCNT_INTR_SOURCE, ESP_INTR_FLAG_IRAM, pcnt_isr, NULL, &s_intr_handle));
PCNT.int_clr.val = BIT(REF_CLOCK_PCNT_UNIT);
PCNT.int_ena.val = BIT(REF_CLOCK_PCNT_UNIT);
pcnt_ll_clear_intr_status(s_pcnt.dev, BIT(REF_CLOCK_PCNT_UNIT));
pcnt_ll_intr_enable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT);
}
static void IRAM_ATTR pcnt_isr(void* arg)
{
portENTER_CRITICAL_ISR(&s_lock);
PCNT.int_clr.val = BIT(REF_CLOCK_PCNT_UNIT);
pcnt_ll_clear_intr_status(s_pcnt.dev, BIT(REF_CLOCK_PCNT_UNIT));
s_milliseconds += REF_CLOCK_PRESCALER_MS;
portEXIT_CRITICAL_ISR(&s_lock);
}
@ -154,28 +153,30 @@ void ref_clock_deinit()
assert(s_intr_handle && "deinit called without init");
// Disable interrupt
PCNT.int_ena.val &= ~BIT(REF_CLOCK_PCNT_UNIT);
pcnt_ll_intr_disable(s_pcnt.dev, REF_CLOCK_PCNT_UNIT);
esp_intr_free(s_intr_handle);
s_intr_handle = NULL;
// Disable RMT
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf1.tx_start = 0;
RMT.conf_ch[REF_CLOCK_RMT_CHANNEL].conf0.clk_en = 0;
rmt_ll_stop_tx(s_rmt.regs, REF_CLOCK_RMT_CHANNEL);
periph_module_disable(PERIPH_RMT_MODULE);
// Disable PCNT
PCNT.ctrl.val |= ~(BIT(REF_CLOCK_PCNT_UNIT * 2 + 1));
pcnt_ll_counter_pause(s_pcnt.dev, REF_CLOCK_PCNT_UNIT);
periph_module_disable(PERIPH_PCNT_MODULE);
}
uint64_t ref_clock_get()
{
portENTER_CRITICAL(&s_lock);
uint32_t microseconds = PCNT.cnt_unit[REF_CLOCK_PCNT_UNIT].cnt_val;
int16_t microseconds = 0;
pcnt_ll_get_counter_value(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, &microseconds);
uint32_t milliseconds = s_milliseconds;
if (PCNT.int_st.val & BIT(REF_CLOCK_PCNT_UNIT)) {
uint32_t intr_status = 0;
pcnt_ll_get_intr_status(s_pcnt.dev, &intr_status);
if (intr_status & BIT(REF_CLOCK_PCNT_UNIT)) {
// refresh counter value, in case the overflow has happened after reading cnt_val
microseconds = PCNT.cnt_unit[REF_CLOCK_PCNT_UNIT].cnt_val;
pcnt_ll_get_counter_value(s_pcnt.dev, REF_CLOCK_PCNT_UNIT, &microseconds);
milliseconds += REF_CLOCK_PRESCALER_MS;
}
portEXIT_CRITICAL(&s_lock);