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ut: Move tests back from "esp32" subfolder

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DISABLED_FOR_TARGETS macros are used

Partly revert "ci: disable unavailable tests for esp32s2beta"

This partly reverts commit 76a3a5fb48.

Partly revert "ci: disable UTs for esp32s2beta without runners"

This partly reverts commit eb158e9a22.

Partly revert "fix unit test and examples for s2beta"

This partly reverts commit 9baa7826be.

Partly revert "efuse: Add support for esp32s2beta"

This partly reverts commit db84ba868c.
This commit is contained in:
michael 2020-01-02 14:25:33 +08:00
parent bc0eac579c
commit 4220752aed
55 changed files with 735 additions and 831 deletions
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9
components/app_update/test/CMakeLists.txt
View file

@ -1,5 +1,4 @@
if(IDF_TARGET STREQUAL "esp32") idf_component_register(SRC_DIRS "."
idf_component_register(SRC_DIRS "." INCLUDE_DIRS "."
INCLUDE_DIRS "." REQUIRES unity test_utils app_update bootloader_support nvs_flash
REQUIRES unity test_utils app_update bootloader_support nvs_flash) )
endif()

4
components/bootloader_support/test/test_verify_image.c
View file

@ -33,7 +33,8 @@ TEST_CASE("Verify bootloader image in flash", "[bootloader_support]")
TEST_ASSERT_EQUAL(data.image_len, bootloader_length); TEST_ASSERT_EQUAL(data.image_len, bootloader_length);
} }
TEST_CASE_ESP32("Verify unit test app image", "[bootloader_support]") #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
TEST_CASE("Verify unit test app image", "[bootloader_support]")
{ {
esp_image_metadata_t data = { 0 }; esp_image_metadata_t data = { 0 };
const esp_partition_t *running = esp_ota_get_running_partition(); const esp_partition_t *running = esp_ota_get_running_partition();
@ -47,6 +48,7 @@ TEST_CASE_ESP32("Verify unit test app image", "[bootloader_support]")
TEST_ASSERT_NOT_EQUAL(0, data.image_len); TEST_ASSERT_NOT_EQUAL(0, data.image_len);
TEST_ASSERT_TRUE(data.image_len <= running->size); TEST_ASSERT_TRUE(data.image_len <= running->size);
} }
#endif
void check_label_search (int num_test, const char *list, const char *t_label, bool result) void check_label_search (int num_test, const char *list, const char *t_label, bool result)
{ {

9
components/driver/test/CMakeLists.txt
View file

@ -1,9 +1,4 @@
set(srcdirs . param_test) idf_component_register(SRC_DIRS . param_test
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS include param_test/include INCLUDE_DIRS include param_test/include
REQUIRES unity test_utils driver nvs_flash esp_serial_slave_link REQUIRES unity test_utils driver nvs_flash esp_serial_slave_link
) )

1
components/driver/test/component.mk
View file

@ -2,7 +2,6 @@
#Component Makefile #Component Makefile
# #
COMPONENT_SRCDIRS += esp32
COMPONENT_SRCDIRS += param_test COMPONENT_SRCDIRS += param_test
COMPONENT_PRIV_INCLUDEDIRS += param_test/include COMPONENT_PRIV_INCLUDEDIRS += param_test/include

356
components/driver/test/esp32/test_i2c.c
View file

@ -1,356 +0,0 @@
/**
* test environment UT_T2_I2C:
* please prepare two ESP32-WROVER-KIT board.
* Then connect GPIO18 and GPIO18, GPIO19 and GPIO19 between these two boards.
*/
#include <stdio.h>
#include <string.h>
#include "unity.h"
#include "test_utils.h"
#include "unity_config.h"
#include "driver/i2c.h"
#include "esp_attr.h"
#include "esp_log.h"
#include "soc/gpio_periph.h"
#include "soc/i2c_periph.h"
#include "esp_system.h"
#include "driver/pcnt.h"
#define DATA_LENGTH 512 /*!<Data buffer length for test buffer*/
#define RW_TEST_LENGTH 129 /*!<Data length for r/w test, any value from 0-DATA_LENGTH*/
#define DELAY_TIME_BETWEEN_ITEMS_MS 1234 /*!< delay time between different test items */
#define I2C_SLAVE_SCL_IO 19 /*!<gpio number for i2c slave clock */
#define I2C_SLAVE_SDA_IO 18 /*!<gpio number for i2c slave data */
#define I2C_SLAVE_NUM I2C_NUM_0 /*!<I2C port number for slave dev */
#define I2C_SLAVE_TX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave tx buffer size */
#define I2C_SLAVE_RX_BUF_LEN (2*DATA_LENGTH) /*!<I2C slave rx buffer size */
#define I2C_MASTER_SCL_IO 19 /*!< gpio number for I2C master clock */
#define I2C_MASTER_SDA_IO 18 /*!< gpio number for I2C master data */
#define I2C_MASTER_NUM I2C_NUM_1 /*!< I2C port number for master dev */
#define I2C_MASTER_TX_BUF_DISABLE 0 /*!< I2C master do not need buffer */
#define I2C_MASTER_RX_BUF_DISABLE 0 /*!< I2C master do not need buffer */
#define I2C_MASTER_FREQ_HZ 100000 /*!< I2C master clock frequency */
#define ESP_SLAVE_ADDR 0x28 /*!< ESP32 slave address, you can set any 7bit value */
#define WRITE_BIT I2C_MASTER_WRITE /*!< I2C master write */
#define READ_BIT I2C_MASTER_READ /*!< I2C master read */
#define ACK_CHECK_EN 0x1 /*!< I2C master will check ack from slave*/
#define ACK_CHECK_DIS 0x0 /*!< I2C master will not check ack from slave */
#define ACK_VAL 0x0 /*!< I2C ack value */
#define NACK_VAL 0x1 /*!< I2C nack value */
#define PULSE_IO 19
#define PCNT_INPUT_IO 4
#define PCNT_CTRL_FLOATING_IO 5
#define HIGHEST_LIMIT 10000
#define LOWEST_LIMIT -10000
static esp_err_t i2c_master_write_slave(i2c_port_t i2c_num, uint8_t *data_wr, size_t size)
{
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
TEST_ESP_OK(i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | WRITE_BIT, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_write(cmd, data_wr, size, ACK_CHECK_EN));
TEST_ESP_OK(i2c_master_stop(cmd));
esp_err_t ret = i2c_master_cmd_begin(i2c_num, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
return ret;
}
static i2c_config_t i2c_master_init(void)
{
i2c_config_t conf_master = {
.mode = I2C_MODE_MASTER,
.sda_pullup_en = GPIO_PULLUP_ENABLE,
.scl_pullup_en = GPIO_PULLUP_ENABLE,
.master.clk_speed = I2C_MASTER_FREQ_HZ,
.sda_io_num = I2C_MASTER_SDA_IO,
.scl_io_num = I2C_MASTER_SCL_IO,
};
return conf_master;
}
// print the reading buffer
static void disp_buf(uint8_t *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
printf("%02x ", buf[i]);
if (( i + 1 ) % 16 == 0) {
printf("\n");
}
}
printf("\n");
}
static i2c_config_t i2c_slave_init(void)
{
i2c_config_t conf_slave = {
.mode = I2C_MODE_SLAVE,
.sda_io_num = I2C_SLAVE_SDA_IO,
.scl_io_num = I2C_SLAVE_SCL_IO,
.sda_pullup_en = GPIO_PULLUP_ENABLE,
.scl_pullup_en = GPIO_PULLUP_ENABLE,
.slave.addr_10bit_en = 0,
.slave.slave_addr = ESP_SLAVE_ADDR,
};
return conf_slave;
}
static void i2c_master_write_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int i;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
unity_wait_for_signal("i2c slave init finish");
unity_send_signal("master write");
for (i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, DATA_LENGTH / 2);
disp_buf(data_wr, i + 1);
free(data_wr);
unity_wait_for_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_MASTER_NUM));
}
static void i2c_slave_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
int size_rd = 0;
int len = 0;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int i = 0; i < size_rd; i++) {
TEST_ASSERT(data_rd[i] == i);
}
free(data_rd);
unity_send_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_SLAVE_NUM));
}
TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_test, i2c_slave_read_test);
static void master_read_slave_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH-1, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH-1, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("%d\n", data_rd[i]);
TEST_ASSERT(data_rd[i]==i);
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void slave_write_buffer_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read");
unity_wait_for_signal("ready to delete");
free(data_wr);
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", master_read_slave_test, slave_write_buffer_test);
static void i2c_master_write_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read and write");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
disp_buf(data_rd, RW_TEST_LENGTH);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i/2);
}
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = i % 3;
}
vTaskDelay(100 / portTICK_RATE_MS);
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
free(data_wr);
free(data_rd);
unity_send_signal("slave read");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_read_write_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i/2;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read and write");
unity_wait_for_signal("slave read");
size_rd = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 1000 / portTICK_RATE_MS);
printf("slave read data is:\n");
disp_buf(data_rd, size_rd);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i % 3);
}
free(data_wr);
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C read and write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_read_test, i2c_slave_read_write_test);
static void i2c_master_repeat_write(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int times = 3;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
unity_wait_for_signal("i2c slave init finish");
for (int j = 0; j < times; j++) {
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = j + i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
disp_buf(data_wr, RW_TEST_LENGTH);
}
free(data_wr);
unity_send_signal("master write");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_repeat_read(void)
{
int size_rd = 0;
int times = 3;
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH * 3);
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
int len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, RW_TEST_LENGTH * 3, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int j = 0; j < times; j++) {
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("data: %d, %d\n", data_rd[j * RW_TEST_LENGTH + i], (i % 129 + j));
TEST_ASSERT(data_rd[j * RW_TEST_LENGTH + i] == (i % 129 + j));
}
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C repeat write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_repeat_write, i2c_slave_repeat_read);

8
components/driver/test/esp32/test_adc2.c → components/driver/test/test_adc2.c
View file

@ -12,6 +12,8 @@
#include "nvs_flash.h" #include "nvs_flash.h"
#include "test_utils.h" #include "test_utils.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
static const char* TAG = "test_adc2"; static const char* TAG = "test_adc2";
#define DEFAULT_SSID "TEST_SSID" #define DEFAULT_SSID "TEST_SSID"
@ -92,7 +94,7 @@ TEST_CASE("adc2 work with wifi","[adc]")
printf("no free pages or nvs version mismatch, erase..\n"); printf("no free pages or nvs version mismatch, erase..\n");
TEST_ESP_OK(nvs_flash_erase()); TEST_ESP_OK(nvs_flash_erase());
r = nvs_flash_init(); r = nvs_flash_init();
} }
TEST_ESP_OK( r); TEST_ESP_OK( r);
esp_netif_init(); esp_netif_init();
event_init(); event_init();
@ -108,7 +110,7 @@ TEST_CASE("adc2 work with wifi","[adc]")
}; };
TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA)); TEST_ESP_OK(esp_wifi_set_mode(WIFI_MODE_STA));
TEST_ESP_OK(esp_wifi_set_config(ESP_IF_WIFI_STA, &wifi_config)); TEST_ESP_OK(esp_wifi_set_config(ESP_IF_WIFI_STA, &wifi_config));
//test read value //test read value
TEST_ESP_OK( adc2_get_raw( ADC2_CHANNEL_8, ADC_WIDTH_12Bit, &read_raw )); TEST_ESP_OK( adc2_get_raw( ADC2_CHANNEL_8, ADC_WIDTH_12Bit, &read_raw ));
target_value = 30*4096*3/256; //3 = 3.3/1.1 target_value = 30*4096*3/256; //3 = 3.3/1.1
@ -148,3 +150,5 @@ TEST_CASE("adc2 work with wifi","[adc]")
TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop."); TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop.");
} }
#endif

11
components/driver/test/esp32/test_gpio.c → components/driver/test/test_gpio.c
View file

@ -55,6 +55,8 @@ static gpio_config_t init_io(gpio_num_t num)
return io_conf; return io_conf;
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
// edge interrupt event // edge interrupt event
static void gpio_isr_edge_handler(void* arg) static void gpio_isr_edge_handler(void* arg)
{ {
@ -86,6 +88,7 @@ static void gpio_isr_level_handler2(void* arg)
ets_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", GPIO_OUTPUT_IO, gpio_get_level(GPIO_OUTPUT_IO), level_intr_times); ets_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", GPIO_OUTPUT_IO, gpio_get_level(GPIO_OUTPUT_IO), level_intr_times);
ets_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times); ets_printf("GPIO[%d] intr, val: %d, level_intr_times = %d\n", gpio_num, gpio_get_level(gpio_num), level_intr_times);
} }
#endif
#if !WAKE_UP_IGNORE #if !WAKE_UP_IGNORE
// get result of waking up or not // get result of waking up or not
@ -180,6 +183,8 @@ TEST_CASE("GPIO config parameters test", "[gpio]")
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
TEST_CASE("GPIO rising edge interrupt test", "[gpio][test_env=UT_T1_GPIO]") TEST_CASE("GPIO rising edge interrupt test", "[gpio][test_env=UT_T1_GPIO]")
{ {
edge_intr_times = 0; // set it as 0 prepare to test edge_intr_times = 0; // set it as 0 prepare to test
@ -370,6 +375,7 @@ TEST_CASE("GPIO enable and disable interrupt test", "[gpio][test_env=UT_T1_GPIO]
TEST_ASSERT(gpio_isr_handler_add(GPIO_INPUT_IO, gpio_isr_level_handler, (void*) GPIO_INPUT_IO) == ESP_ERR_INVALID_STATE); TEST_ASSERT(gpio_isr_handler_add(GPIO_INPUT_IO, gpio_isr_level_handler, (void*) GPIO_INPUT_IO) == ESP_ERR_INVALID_STATE);
TEST_ASSERT(gpio_isr_handler_remove(GPIO_INPUT_IO) == ESP_ERR_INVALID_STATE); TEST_ASSERT(gpio_isr_handler_remove(GPIO_INPUT_IO) == ESP_ERR_INVALID_STATE);
} }
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)
// ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO18 with GPIO21 // ESP32 Connect GPIO18 with GPIO19, ESP32-S2 Connect GPIO18 with GPIO21
// use multimeter to test the voltage, so it is ignored in CI // use multimeter to test the voltage, so it is ignored in CI
@ -457,6 +463,8 @@ TEST_CASE("GPIO io pull up/down function", "[gpio]")
TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(GPIO_INPUT_IO), 0, "gpio_pullup_dis error, it can pull up"); TEST_ASSERT_EQUAL_INT_MESSAGE(gpio_get_level(GPIO_INPUT_IO), 0, "gpio_pullup_dis error, it can pull up");
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]") TEST_CASE("GPIO output and input mode test", "[gpio][test_env=UT_T1_GPIO]")
{ {
//ESP32 connect io18 and io19, ESP32-S2 connect io18 and io21 //ESP32 connect io18 and io19, ESP32-S2 connect io18 and io21
@ -529,6 +537,7 @@ TEST_CASE("GPIO repeate call service and isr has no memory leak test","[gpio][te
} }
TEST_ASSERT_INT32_WITHIN(size, esp_get_free_heap_size(), 100); TEST_ASSERT_INT32_WITHIN(size, esp_get_free_heap_size(), 100);
} }
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)
#if !WAKE_UP_IGNORE #if !WAKE_UP_IGNORE
//this function development is not completed yet, set it ignored //this function development is not completed yet, set it ignored
@ -717,7 +726,7 @@ static void gpio_isr_handler(void* arg)
param->isr_cnt++; param->isr_cnt++;
} }
/** The previous GPIO interrupt service routine polls the interrupt raw status register to find the GPIO that triggered the interrupt. /** The previous GPIO interrupt service routine polls the interrupt raw status register to find the GPIO that triggered the interrupt.
* But this will incorrectly handle the interrupt disabled GPIOs, because the raw interrupt status register can still be set when * But this will incorrectly handle the interrupt disabled GPIOs, because the raw interrupt status register can still be set when
* the trigger signal arrives, even if the interrupt is disabled. * the trigger signal arrives, even if the interrupt is disabled.
* First on the core 0: * First on the core 0:

274
components/driver/test/test_i2c.c
View file

@ -242,6 +242,280 @@ TEST_CASE("I2C driver memory leaking check", "[i2c]")
TEST_ASSERT_INT_WITHIN(100, size, esp_get_free_heap_size()); TEST_ASSERT_INT_WITHIN(100, size, esp_get_free_heap_size());
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
// print the reading buffer
static void disp_buf(uint8_t *buf, int len)
{
int i;
for (i = 0; i < len; i++) {
printf("%02x ", buf[i]);
if (( i + 1 ) % 16 == 0) {
printf("\n");
}
}
printf("\n");
}
static void i2c_master_write_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int i;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
unity_send_signal("master write");
for (i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, DATA_LENGTH / 2);
disp_buf(data_wr, i + 1);
free(data_wr);
unity_wait_for_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_MASTER_NUM));
}
static void i2c_slave_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
int size_rd = 0;
int len = 0;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, DATA_LENGTH, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int i = 0; i < size_rd; i++) {
TEST_ASSERT(data_rd[i] == i);
}
free(data_rd);
unity_send_signal("ready to delete");
TEST_ESP_OK(i2c_driver_delete(I2C_SLAVE_NUM));
}
TEST_CASE_MULTIPLE_DEVICES("I2C master write slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_test, i2c_slave_read_test);
static void master_read_slave_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH-1, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH-1, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("%d\n", data_rd[i]);
TEST_ASSERT(data_rd[i]==i);
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void slave_write_buffer_test(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read");
unity_wait_for_signal("ready to delete");
free(data_wr);
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C master read slave test", "[i2c][test_env=UT_T2_I2C][timeout=150]", master_read_slave_test, slave_write_buffer_test);
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA, ESP32)
static void i2c_master_write_read_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
i2c_cmd_handle_t cmd = i2c_cmd_link_create();
i2c_master_start(cmd);
i2c_master_write_byte(cmd, ( ESP_SLAVE_ADDR << 1 ) | READ_BIT, ACK_CHECK_EN);
unity_send_signal("slave write");
unity_wait_for_signal("master read and write");
i2c_master_read(cmd, data_rd, RW_TEST_LENGTH, ACK_VAL);
i2c_master_read_byte(cmd, data_rd + RW_TEST_LENGTH, NACK_VAL);
i2c_master_stop(cmd);
i2c_master_cmd_begin(I2C_MASTER_NUM, cmd, 5000 / portTICK_RATE_MS);
i2c_cmd_link_delete(cmd);
vTaskDelay(100 / portTICK_RATE_MS);
disp_buf(data_rd, RW_TEST_LENGTH);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i/2);
}
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = i % 3;
}
vTaskDelay(100 / portTICK_RATE_MS);
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
free(data_wr);
free(data_rd);
unity_send_signal("slave read");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_read_write_test(void)
{
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH);
memset(data_rd, 0, DATA_LENGTH);
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int size_rd;
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("slave write");
for (int i = 0; i < DATA_LENGTH / 2; i++) {
data_wr[i] = i/2;
}
size_rd = i2c_slave_write_buffer(I2C_SLAVE_NUM, data_wr, RW_TEST_LENGTH, 2000 / portTICK_RATE_MS);
disp_buf(data_wr, size_rd);
unity_send_signal("master read and write");
unity_wait_for_signal("slave read");
size_rd = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd, RW_TEST_LENGTH, 1000 / portTICK_RATE_MS);
printf("slave read data is:\n");
disp_buf(data_rd, size_rd);
for (int i = 0; i < RW_TEST_LENGTH; i++) {
TEST_ASSERT(data_rd[i] == i % 3);
}
free(data_wr);
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C read and write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_write_read_test, i2c_slave_read_write_test);
static void i2c_master_repeat_write(void)
{
uint8_t *data_wr = (uint8_t *) malloc(DATA_LENGTH);
int times = 3;
i2c_config_t conf_master = i2c_master_init();
TEST_ESP_OK(i2c_param_config(I2C_MASTER_NUM, &conf_master));
TEST_ESP_OK(i2c_driver_install(I2C_MASTER_NUM, I2C_MODE_MASTER,
I2C_MASTER_RX_BUF_DISABLE,
I2C_MASTER_TX_BUF_DISABLE, 0));
unity_wait_for_signal("i2c slave init finish");
for (int j = 0; j < times; j++) {
for (int i = 0; i < DATA_LENGTH; i++) {
data_wr[i] = j + i;
}
i2c_master_write_slave(I2C_MASTER_NUM, data_wr, RW_TEST_LENGTH);
disp_buf(data_wr, RW_TEST_LENGTH);
}
free(data_wr);
unity_send_signal("master write");
unity_wait_for_signal("ready to delete");
i2c_driver_delete(I2C_MASTER_NUM);
}
static void i2c_slave_repeat_read(void)
{
int size_rd = 0;
int times = 3;
uint8_t *data_rd = (uint8_t *) malloc(DATA_LENGTH * 3);
i2c_config_t conf_slave = i2c_slave_init();
TEST_ESP_OK(i2c_param_config( I2C_SLAVE_NUM, &conf_slave));
TEST_ESP_OK(i2c_driver_install(I2C_SLAVE_NUM, I2C_MODE_SLAVE,
I2C_SLAVE_RX_BUF_LEN,
I2C_SLAVE_TX_BUF_LEN, 0));
unity_send_signal("i2c slave init finish");
unity_wait_for_signal("master write");
while (1) {
int len = i2c_slave_read_buffer( I2C_SLAVE_NUM, data_rd + size_rd, RW_TEST_LENGTH * 3, 10000 / portTICK_RATE_MS);
if (len == 0) {
break;
}
size_rd += len;
}
disp_buf(data_rd, size_rd);
for (int j = 0; j < times; j++) {
for (int i = 0; i < RW_TEST_LENGTH; i++) {
printf("data: %d, %d\n", data_rd[j * RW_TEST_LENGTH + i], (i % 129 + j));
TEST_ASSERT(data_rd[j * RW_TEST_LENGTH + i] == (i % 129 + j));
}
}
free(data_rd);
unity_send_signal("ready to delete");
i2c_driver_delete(I2C_SLAVE_NUM);
}
TEST_CASE_MULTIPLE_DEVICES("I2C repeat write test", "[i2c][test_env=UT_T2_I2C][timeout=150]", i2c_master_repeat_write, i2c_slave_repeat_read);
#endif //DISABLED_FOR_TARGET(ESP32S2BETA, ESP32)
#endif //DISABLED_FOR_TARGET(ESP32S2BETA)
static volatile bool exit_flag; static volatile bool exit_flag;
static bool test_read_func; static bool test_read_func;

3
components/driver/test/test_i2s.c
View file

@ -76,8 +76,7 @@ TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0)); TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
} }
#if CONFIG_IDF_TARGET_ESP32 #if !DISABLED_FOR_TARGETS(ESP32S2BETA)
/* ESP32S2BETA has only single I2S port and hence following test cases are not applicable */ /* ESP32S2BETA has only single I2S port and hence following test cases are not applicable */
TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s][test_env=UT_T1_I2S]") TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s][test_env=UT_T1_I2S]")

2
components/driver/test/test_ledc.c
View file

@ -262,7 +262,7 @@ TEST_CASE("LEDC normal channel and timer config", "[ledc][test_env=UT_T1_LEDC]")
// set it ignore: need to debug // set it ignore: need to debug
TEST_CASE("LEDC set and get frequency", "[ledc][test_env=UT_T1_LEDC][timeout=60][ignore]") TEST_CASE("LEDC set and get frequency", "[ledc][test_env=UT_T1_LEDC][timeout=60][ignore]")
{ {
#ifdef CONFIG_IDF_TARGET_ESP32 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_0, LEDC_HIGH_SPEED_MODE); timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_0, LEDC_HIGH_SPEED_MODE);
timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_1, LEDC_HIGH_SPEED_MODE); timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_1, LEDC_HIGH_SPEED_MODE);
timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_2, LEDC_HIGH_SPEED_MODE); timer_frequency_test(LEDC_CHANNEL_0, LEDC_TIMER_13_BIT, LEDC_TIMER_2, LEDC_HIGH_SPEED_MODE);

4
components/driver/test/esp32/test_pcnt.c → components/driver/test/test_pcnt.c
View file

@ -23,6 +23,8 @@
#include "soc/gpio_periph.h" #include "soc/gpio_periph.h"
#include "unity.h" #include "unity.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
#define PULSE_IO 18 #define PULSE_IO 18
#define PCNT_INPUT_IO 4 #define PCNT_INPUT_IO 4
#define PCNT_CTRL_FLOATING_IO 5 #define PCNT_CTRL_FLOATING_IO 5
@ -649,3 +651,5 @@ TEST_CASE("PCNT counting mode test", "[pcnt][test_env=UT_T1_PCNT]")
printf("PCNT mode test for negative count\n"); printf("PCNT mode test for negative count\n");
count_mode_test(PCNT_CTRL_GND_IO); count_mode_test(PCNT_CTRL_GND_IO);
} }
#endif

8
components/driver/test/esp32/test_pwm.c → components/driver/test/test_pwm.c
View file

@ -14,17 +14,20 @@
*/ */
#include <stdio.h> #include <stdio.h>
#include "esp_system.h" #include "esp_system.h"
#include "driver/mcpwm.h"
#include "driver/pcnt.h" #include "driver/pcnt.h"
#include "unity.h" #include "unity.h"
#include "test_utils.h" #include "test_utils.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "soc/mcpwm_periph.h"
#include "freertos/queue.h" #include "freertos/queue.h"
#include "esp_attr.h" #include "esp_attr.h"
#include "esp_log.h" #include "esp_log.h"
#include "soc/rtc.h" #include "soc/rtc.h"
#include "soc/soc_caps.h"
#ifdef SOC_MCPWM_SUPPORTED
#include "soc/mcpwm_periph.h"
#include "driver/mcpwm.h"
#define GPIO_PWMA_OUT 4 #define GPIO_PWMA_OUT 4
@ -783,3 +786,4 @@ TEST_CASE("MCPWM unit1, timer2 capture test", "[mcpwm][test_env=UT_T1_MCPWM][tim
capture_test(MCPWM_UNIT_1, MCPWM_TIMER_2, MCPWM_POS_EDGE); capture_test(MCPWM_UNIT_1, MCPWM_TIMER_2, MCPWM_POS_EDGE);
} }
#endif

4
components/driver/test/esp32/test_rmt.c → components/driver/test/test_rmt.c
View file

@ -18,6 +18,8 @@
#include "soc/soc.h" #include "soc/soc.h"
#include "soc/rmt_periph.h" #include "soc/rmt_periph.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
static const char *TAG = "RMT.test"; static const char *TAG = "RMT.test";
#define RMT_RX_ACTIVE_LEVEL 1 /*!< Data bit is active high for self test mode */ #define RMT_RX_ACTIVE_LEVEL 1 /*!< Data bit is active high for self test mode */
@ -761,3 +763,5 @@ TEST_CASE("RMT loop_en test", "[rmt][test_env=UT_T1_RMT][ignore]")
TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL)); TEST_ESP_OK(rmt_driver_uninstall(RMT_TX_CHANNEL));
TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL)); TEST_ESP_OK(rmt_driver_uninstall(RMT_RX_CHANNEL));
} }
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)

5
components/driver/test/esp32/test_rs485.c → components/driver/test/test_rs485.c
View file

@ -29,6 +29,9 @@
// Wait timeout for uart driver // Wait timeout for uart driver
#define PACKET_READ_TICS (1000 / portTICK_RATE_MS) #define PACKET_READ_TICS (1000 / portTICK_RATE_MS)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
// The table for fast CRC16 calculation // The table for fast CRC16 calculation
static const uint8_t crc_hi[] = { static const uint8_t crc_hi[] = {
0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
@ -279,3 +282,5 @@ static void rs485_master(void)
* RS485 bus driver hardware to be connected to boards. * RS485 bus driver hardware to be connected to boards.
*/ */
TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[driver_RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave); TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[driver_RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave);
#endif

8
components/driver/test/esp32/test_sdio.c → components/driver/test/test_sdio.c
View file

@ -14,13 +14,14 @@
#include "unity.h" #include "unity.h"
#include "esp_serial_slave_link/essl_sdio.h" #include "esp_serial_slave_link/essl_sdio.h"
#include "driver/sdio_slave.h"
#include "driver/sdmmc_host.h"
#include "driver/sdspi_host.h" #include "driver/sdspi_host.h"
#include "test_utils.h" #include "test_utils.h"
#include "param_test.h" #include "param_test.h"
#include "esp_log.h" #include "esp_log.h"
#if defined(SOC_SDMMC_HOST_SUPPORTED) && defined(SOC_SDIO_SLAVE_SUPPORTED)
#include "driver/sdio_slave.h"
#include "driver/sdmmc_host.h"
#define TIMEOUT_MAX UINT32_MAX #define TIMEOUT_MAX UINT32_MAX
#define INT_MASK_ALL 0xff #define INT_MASK_ALL 0xff
@ -55,6 +56,7 @@ typedef struct {
bool packet_mode; bool packet_mode;
} sdio_test_config_t; } sdio_test_config_t;
sdio_test_config_t test_cfg_array[] = { sdio_test_config_t test_cfg_array[] = {
//the first item will be the default config used by all tests //the first item will be the default config used by all tests
{ {
@ -767,3 +769,5 @@ ptest_func_t tohost_slave = {
}; };
TEST_MASTER_SLAVE(SDIO_TOHOST, test_cfg_array, "[sdio][timeout=180][test_env=UT_SDIO]", &tohost_master, &tohost_slave); TEST_MASTER_SLAVE(SDIO_TOHOST, test_cfg_array, "[sdio][timeout=180][test_env=UT_SDIO]", &tohost_master, &tohost_slave);
#endif

18
components/driver/test/test_spi_param.c
View file

@ -212,7 +212,7 @@ static void local_test_loop(const void* arg1, void* arg2)
//TODO: esp32s2beta has better timing performance //TODO: esp32s2beta has better timing performance
static spitest_param_set_t timing_pgroup[] = { static spitest_param_set_t timing_pgroup[] = {
//signals are not fed to peripherals through iomux if the functions are not selected to iomux //signals are not fed to peripherals through iomux if the functions are not selected to iomux
#ifdef CONFIG_IDF_TARGET_ESP32 #if !DISABLED_FOR_TARGETS(ESP32S2BETA)
{ .pset_name = "FULL_DUP, MASTER IOMUX", { .pset_name = "FULL_DUP, MASTER IOMUX",
.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
.master_limit = SPI_MASTER_FREQ_13M, .master_limit = SPI_MASTER_FREQ_13M,
@ -239,7 +239,7 @@ static spitest_param_set_t timing_pgroup[] = {
.slave_tv_ns = TV_INT_CONNECT_GPIO, .slave_tv_ns = TV_INT_CONNECT_GPIO,
}, },
//signals are not fed to peripherals through iomux if the functions are not selected to iomux //signals are not fed to peripherals through iomux if the functions are not selected to iomux
#ifdef CONFIG_IDF_TARGET_ESP32 #if !DISABLED_FOR_TARGETS(ESP32S2BETA)
{ .pset_name = "MISO_DUP, MASTER IOMUX", { .pset_name = "MISO_DUP, MASTER IOMUX",
.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
.master_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, .master_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
@ -266,7 +266,7 @@ static spitest_param_set_t timing_pgroup[] = {
.slave_tv_ns = TV_INT_CONNECT_GPIO, .slave_tv_ns = TV_INT_CONNECT_GPIO,
}, },
//signals are not fed to peripherals through iomux if the functions are not selected to iomux //signals are not fed to peripherals through iomux if the functions are not selected to iomux
#ifdef CONFIG_IDF_TARGET_ESP32 #if !DISABLED_FOR_TARGETS(ESP32S2BETA)
{ .pset_name = "MOSI_DUP, MASTER IOMUX", { .pset_name = "MOSI_DUP, MASTER IOMUX",
.freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC, .freq_limit = ESP_SPI_SLAVE_MAX_FREQ_SYNC,
//.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC, //.freq_limit = ESP_SPI_SLAVE_MAX_READ_FREQ, //ESP_SPI_SLAVE_MAX_FREQ_SYNC,
@ -496,7 +496,7 @@ static spitest_param_set_t mode_pgroup[] = {
}; };
TEST_SPI_LOCAL(MODE, mode_pgroup) TEST_SPI_LOCAL(MODE, mode_pgroup)
#ifdef CONFIG_IDF_TARGET_ESP32 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//These tests are ESP32 only due to lack of runners //These tests are ESP32 only due to lack of runners
/******************************************************************************** /********************************************************************************
* Test By Master & Slave (2 boards) * Test By Master & Slave (2 boards)
@ -533,13 +533,9 @@ static const ptest_func_t slave_test_func = {
.def_param = spitest_def_param, .def_param = spitest_def_param,
}; };
#ifdef CONFIG_IDF_TARGET_ESP32 #define TEST_SPI_MASTER_SLAVE(name, param_group, extra_tag) \
#define TEST_SPI_MASTER_SLAVE_ESP32(name, param_group, extra_tag) \
PARAM_GROUP_DECLARE(name, param_group) \ PARAM_GROUP_DECLARE(name, param_group) \
TEST_MASTER_SLAVE(name, param_group, "[spi_ms][test_env=Example_SPI_Multi_device][timeout=120]"#extra_tag, &master_test_func, &slave_test_func) TEST_MASTER_SLAVE(name, param_group, "[spi_ms][test_env=Example_SPI_Multi_device][timeout=120]"#extra_tag, &master_test_func, &slave_test_func)
#else
#define TEST_SPI_MASTER_SLAVE_ESP32(name, param_group, extra_tag)
#endif
/************ Master Code ***********************************************/ /************ Master Code ***********************************************/
static void test_master_init(void** arg) static void test_master_init(void** arg)
@ -861,7 +857,7 @@ static spitest_param_set_t timing_conf[] = {
.slave_tv_ns = TV_WITH_ESP_SLAVE_GPIO, .slave_tv_ns = TV_WITH_ESP_SLAVE_GPIO,
}, },
}; };
TEST_SPI_MASTER_SLAVE_ESP32(TIMING, timing_conf, "") TEST_SPI_MASTER_SLAVE(TIMING, timing_conf, "")
/************ Mode Test ***********************************************/ /************ Mode Test ***********************************************/
#define FREQ_LIMIT_MODE SPI_MASTER_FREQ_16M #define FREQ_LIMIT_MODE SPI_MASTER_FREQ_16M
@ -1048,6 +1044,6 @@ spitest_param_set_t mode_conf[] = {
.slave_dma_chan = 1, .slave_dma_chan = 1,
}, },
}; };
TEST_SPI_MASTER_SLAVE_ESP32(MODE, mode_conf, "") TEST_SPI_MASTER_SLAVE(MODE, mode_conf, "")
#endif #endif

4
components/driver/test/test_spi_sio.c
View file

@ -107,7 +107,7 @@ TEST_CASE("local test sio", "[spi]")
master_free_device_bus(spi); master_free_device_bus(spi);
} }
#ifdef CONFIG_IDF_TARGET_ESP32 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//These tests are ESP32 only due to lack of runners //These tests are ESP32 only due to lack of runners
/******************************************************************************** /********************************************************************************
* Test SIO Master & Slave * Test SIO Master & Slave
@ -224,5 +224,5 @@ void test_sio_slave(void)
test_sio_slave_round(false); test_sio_slave_round(false);
} }
TEST_CASE_MULTIPLE_DEVICES_ESP32("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave); TEST_CASE_MULTIPLE_DEVICES("sio mode", "[spi][test_env=Example_SPI_Multi_device]", test_sio_master, test_sio_slave);
#endif #endif

2
components/efuse/test/CMakeLists.txt
View file

@ -1,4 +1,4 @@
idf_component_register(SRC_DIRS "." ${IDF_TARGET} idf_component_register(SRC_DIRS "."
INCLUDE_DIRS "." "include" INCLUDE_DIRS "." "include"
PRIV_INCLUDE_DIRS "../private_include" PRIV_INCLUDE_DIRS "../private_include"
REQUIRES unity test_utils efuse bootloader_support REQUIRES unity test_utils efuse bootloader_support

67
components/efuse/test/esp32/test_efuse.c
View file

@ -1,67 +0,0 @@
#include <stdio.h>
#include <ctype.h>
#include <errno.h>
#include <stdlib.h>
#include <stdio.h>
#include "unity.h"
#include "esp_log.h"
#include <string.h>
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_efuse_utility.h"
#include "esp_efuse_test_table.h"
#include "esp32/rom/efuse.h"
#include "bootloader_random.h"
#include "sdkconfig.h"
#ifdef CONFIG_EFUSE_VIRTUAL
TEST_CASE("Test a write/read protection", "[efuse]")
{
esp_efuse_utility_reset();
esp_efuse_utility_erase_virt_blocks();
esp_efuse_utility_debug_dump_blocks();
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_write_protect(EFUSE_BLK0));
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_read_protect(EFUSE_BLK0));
size_t out_cnt;
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(0, out_cnt);
TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK1));
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_write_protect(EFUSE_BLK1));
TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK2));
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK2, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK3));
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK3, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
esp_efuse_utility_debug_dump_blocks();
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(0, out_cnt);
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK1));
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_read_protect(EFUSE_BLK1));
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK2));
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK2, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK3));
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_BLK3, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
esp_efuse_utility_debug_dump_blocks();
esp_efuse_utility_reset();
esp_efuse_utility_erase_virt_blocks();
}
#endif // #ifdef CONFIG_EFUSE_VIRTUAL

130
components/efuse/test/esp32s2beta/test_efuse.c
View file

@ -1,130 +0,0 @@
#include <stdio.h>
#include <ctype.h>
#include <errno.h>
#include <stdlib.h>
#include <stdio.h>
#include "unity.h"
#include "esp_log.h"
#include <string.h>
#include "esp_efuse.h"
#include "esp_efuse_table.h"
#include "esp_efuse_utility.h"
#include "esp_efuse_test_table.h"
#include "esp32/rom/efuse.h"
#include "bootloader_random.h"
#include "sdkconfig.h"
//#define MANUAL_FPGA_TEST
#if defined(MANUAL_FPGA_TEST) && defined(CONFIG_IDF_TARGET_ESP32S2BETA) && !defined(CONFIG_EFUSE_VIRTUAL)
TEST_CASE("Test a real write (FPGA)", "[efuse]")
{
ESP_LOGI(TAG, "1. Write MAC address");
esp_efuse_utility_debug_dump_blocks();
uint8_t mac[6];
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY, &mac, sizeof(mac) * 8));
ESP_LOGI(TAG, "MAC: %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
uint8_t new_mac[6];
if (mac[0] == 0) {
new_mac[0] = 0x71;
new_mac[1] = 0x62;
new_mac[2] = 0x53;
new_mac[3] = 0x44;
new_mac[4] = 0x35;
new_mac[5] = 0x26;
TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_MAC_FACTORY, &new_mac, sizeof(new_mac) * 8));
ESP_LOGI(TAG, "new MAC: %02x:%02x:%02x:%02x:%02x:%02x", new_mac[0], new_mac[1], new_mac[2], new_mac[3], new_mac[4], new_mac[5]);
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY, &mac, sizeof(mac) * 8));
TEST_ASSERT_EQUAL_HEX8_ARRAY(new_mac, mac, sizeof(new_mac));
esp_efuse_utility_debug_dump_blocks();
}
ESP_LOGI(TAG, "2. Write KEY3");
uint8_t key[32] = {0};
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
for (int i = 0; i < sizeof(key); ++i) {
TEST_ASSERT_EQUAL_INT(0, key[i]);
}
uint8_t new_key[32] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 12, 14, 15, 16, 17, 18, 19,
20, 21, 22, 22, 24, 25, 26, 27, 28, 29,
30, 31};
TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_KEY3, &new_key, 256));
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
TEST_ASSERT_EQUAL_HEX8_ARRAY(new_key, key, sizeof(new_mac));
esp_efuse_utility_debug_dump_blocks();
ESP_LOGI(TAG, "3. Set a read protection for KEY3");
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK7));
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
for (int i = 0; i < sizeof(key); ++i) {
TEST_ASSERT_EQUAL_INT(0, key[i]);
}
esp_efuse_utility_debug_dump_blocks();
ESP_LOGI(TAG, "4. Write SECURE_VERSION");
int max_bits = esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION);
size_t read_sec_version;
esp_efuse_utility_debug_dump_blocks();
for (int i = 0; i < max_bits; ++i) {
ESP_LOGI(TAG, "# %d", i);
TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_SECURE_VERSION, 1));
TEST_ESP_OK(esp_efuse_read_field_cnt(ESP_EFUSE_SECURE_VERSION, &read_sec_version));
esp_efuse_utility_debug_dump_blocks();
TEST_ASSERT_EQUAL_INT(i + 1, read_sec_version);
}
}
#endif
#ifdef CONFIG_EFUSE_VIRTUAL
TEST_CASE("Test a write/read protection", "[efuse]")
{
esp_efuse_utility_reset();
esp_efuse_utility_erase_virt_blocks();
esp_efuse_utility_debug_dump_blocks();
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_write_protect(EFUSE_BLK0));
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_read_protect(EFUSE_BLK0));
size_t out_cnt;
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(0, out_cnt);
TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK1));
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_write_protect(EFUSE_BLK1));
TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK2));
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_SYS_DATA_PART1, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK3));
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_USER_DATA, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
esp_efuse_utility_debug_dump_blocks();
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY0, &out_cnt);
TEST_ASSERT_EQUAL_INT(0, out_cnt);
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK4));
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY0, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_read_protect(EFUSE_BLK4));
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK5));
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY1, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK6));
esp_efuse_read_field_cnt(ESP_EFUSE_RD_DIS_KEY2, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
esp_efuse_utility_debug_dump_blocks();
esp_efuse_utility_reset();
esp_efuse_utility_erase_virt_blocks();
}
#endif // #ifdef CONFIG_EFUSE_VIRTUAL

0
components/efuse/test/esp32s2beta/test_efuse_coding_scheme.c
View file

133
components/efuse/test/test_efuse.c
View file

@ -18,6 +18,7 @@
#include "test_utils.h" #include "test_utils.h"
#include "sdkconfig.h" #include "sdkconfig.h"
//#define MANUAL_FPGA_TEST
static const char* TAG = "efuse_test"; static const char* TAG = "efuse_test";
static void test_read_blob(void) static void test_read_blob(void)
@ -33,7 +34,7 @@ static void test_read_blob(void)
TEST_ASSERT_EQUAL_INT(sizeof(mac) * 8, esp_efuse_get_field_size(ESP_EFUSE_MAC_FACTORY)); TEST_ASSERT_EQUAL_INT(sizeof(mac) * 8, esp_efuse_get_field_size(ESP_EFUSE_MAC_FACTORY));
ESP_LOGI(TAG, "MAC: %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); ESP_LOGI(TAG, "MAC: %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
#if CONFIG_IDF_TARGET_ESP32 #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
ESP_LOGI(TAG, "2. Check CRC by MAC"); ESP_LOGI(TAG, "2. Check CRC by MAC");
uint8_t crc; uint8_t crc;
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &crc, 8)); TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY_CRC, &crc, 8));
@ -690,4 +691,134 @@ TEST_CASE("Batch mode is thread-safe", "[efuse]")
} }
#endif // #ifndef CONFIG_FREERTOS_UNICORE #endif // #ifndef CONFIG_FREERTOS_UNICORE
static void test_wp(esp_efuse_block_t blk, const esp_efuse_desc_t* field[])
{
size_t out_cnt;
TEST_ESP_OK(esp_efuse_set_write_protect(blk));
esp_efuse_read_field_cnt(field, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
}
static void test_rp(esp_efuse_block_t blk, const esp_efuse_desc_t* field[], bool read_first)
{
size_t out_cnt;
if (read_first) {
esp_efuse_read_field_cnt(field, &out_cnt);
TEST_ASSERT_EQUAL_INT(0, out_cnt);
}
TEST_ESP_OK(esp_efuse_set_read_protect(blk));
esp_efuse_read_field_cnt(field, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
if (read_first) {
TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_read_protect(blk));
}
}
TEST_CASE("Test a write/read protection", "[efuse]")
{
esp_efuse_utility_reset();
esp_efuse_utility_erase_virt_blocks();
esp_efuse_utility_debug_dump_blocks();
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_write_protect(EFUSE_BLK0));
TEST_ESP_ERR(ESP_ERR_NOT_SUPPORTED, esp_efuse_set_read_protect(EFUSE_BLK0));
size_t out_cnt;
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(0, out_cnt);
TEST_ESP_OK(esp_efuse_set_write_protect(EFUSE_BLK1));
esp_efuse_read_field_cnt(ESP_EFUSE_WR_DIS_BLK1, &out_cnt);
TEST_ASSERT_EQUAL_INT(1, out_cnt);
TEST_ESP_ERR(ESP_ERR_EFUSE_CNT_IS_FULL, esp_efuse_set_write_protect(EFUSE_BLK1));
#ifdef CONFIG_IDF_TARGET_ESP32
test_wp(EFUSE_BLK2, ESP_EFUSE_WR_DIS_BLK2);
test_wp(EFUSE_BLK3, ESP_EFUSE_WR_DIS_BLK3);
esp_efuse_utility_debug_dump_blocks();
test_rp(EFUSE_BLK1, ESP_EFUSE_RD_DIS_BLK1, true);
test_rp(EFUSE_BLK2, ESP_EFUSE_RD_DIS_BLK2, false);
test_rp(EFUSE_BLK3, ESP_EFUSE_RD_DIS_BLK3, false);
#elif defined(CONFIG_IDF_TARGET_ESP32S2BETA)
test_wp(EFUSE_BLK2, ESP_EFUSE_WR_DIS_SYS_DATA_PART1);
test_wp(EFUSE_BLK3, ESP_EFUSE_WR_DIS_USER_DATA);
esp_efuse_utility_debug_dump_blocks();
test_rp(EFUSE_BLK4, ESP_EFUSE_RD_DIS_KEY0, true);
test_rp(EFUSE_BLK5, ESP_EFUSE_RD_DIS_KEY1, false);
test_rp(EFUSE_BLK6, ESP_EFUSE_RD_DIS_KEY2, false);
#else
#error New chip not supported!
#endif
esp_efuse_utility_debug_dump_blocks();
esp_efuse_utility_reset();
esp_efuse_utility_erase_virt_blocks();
}
#endif // #ifdef CONFIG_EFUSE_VIRTUAL #endif // #ifdef CONFIG_EFUSE_VIRTUAL
#if defined(MANUAL_FPGA_TEST) && !defined(CONFIG_EFUSE_VIRTUAL)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32)
TEST_CASE("Test a real write (FPGA)", "[efuse]")
{
ESP_LOGI(TAG, "1. Write MAC address");
esp_efuse_utility_debug_dump_blocks();
uint8_t mac[6];
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY, &mac, sizeof(mac) * 8));
ESP_LOGI(TAG, "MAC: %02x:%02x:%02x:%02x:%02x:%02x", mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
uint8_t new_mac[6];
if (mac[0] == 0) {
new_mac[0] = 0x71;
new_mac[1] = 0x62;
new_mac[2] = 0x53;
new_mac[3] = 0x44;
new_mac[4] = 0x35;
new_mac[5] = 0x26;
TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_MAC_FACTORY, &new_mac, sizeof(new_mac) * 8));
ESP_LOGI(TAG, "new MAC: %02x:%02x:%02x:%02x:%02x:%02x", new_mac[0], new_mac[1], new_mac[2], new_mac[3], new_mac[4], new_mac[5]);
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_MAC_FACTORY, &mac, sizeof(mac) * 8));
TEST_ASSERT_EQUAL_HEX8_ARRAY(new_mac, mac, sizeof(new_mac));
esp_efuse_utility_debug_dump_blocks();
}
ESP_LOGI(TAG, "2. Write KEY3");
uint8_t key[32] = {0};
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
for (int i = 0; i < sizeof(key); ++i) {
TEST_ASSERT_EQUAL_INT(0, key[i]);
}
uint8_t new_key[32] = { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9,
10, 11, 12, 12, 14, 15, 16, 17, 18, 19,
20, 21, 22, 22, 24, 25, 26, 27, 28, 29,
30, 31};
TEST_ESP_OK(esp_efuse_write_field_blob(ESP_EFUSE_KEY3, &new_key, 256));
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
TEST_ASSERT_EQUAL_HEX8_ARRAY(new_key, key, sizeof(new_mac));
esp_efuse_utility_debug_dump_blocks();
ESP_LOGI(TAG, "3. Set a read protection for KEY3");
TEST_ESP_OK(esp_efuse_set_read_protect(EFUSE_BLK7));
TEST_ESP_OK(esp_efuse_read_field_blob(ESP_EFUSE_KEY3, &key, 256));
for (int i = 0; i < sizeof(key); ++i) {
TEST_ASSERT_EQUAL_INT(0, key[i]);
}
esp_efuse_utility_debug_dump_blocks();
ESP_LOGI(TAG, "4. Write SECURE_VERSION");
int max_bits = esp_efuse_get_field_size(ESP_EFUSE_SECURE_VERSION);
size_t read_sec_version;
esp_efuse_utility_debug_dump_blocks();
for (int i = 0; i < max_bits; ++i) {
ESP_LOGI(TAG, "# %d", i);
TEST_ESP_OK(esp_efuse_write_field_cnt(ESP_EFUSE_SECURE_VERSION, 1));
TEST_ESP_OK(esp_efuse_read_field_cnt(ESP_EFUSE_SECURE_VERSION, &read_sec_version));
esp_efuse_utility_debug_dump_blocks();
TEST_ASSERT_EQUAL_INT(i + 1, read_sec_version);
}
}
#endif // DISABLED_FOR_TARGETS(ESP32)
#endif // FPGA_TEST

6
components/efuse/test/esp32/test_efuse_coding_scheme.c → components/efuse/test/test_efuse_coding_scheme.c
View file

@ -11,6 +11,7 @@ typedef struct {
uint32_t encoded[8]; uint32_t encoded[8];
} coding_scheme_test_t; } coding_scheme_test_t;
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
/* Randomly generated byte strings, encoded and written to ESP32 /* Randomly generated byte strings, encoded and written to ESP32
using espefuse algorithm, then verified to have no encoding errors using espefuse algorithm, then verified to have no encoding errors
and correct readback. and correct readback.
@ -96,7 +97,6 @@ TEST_CASE("Test 3/4 Coding Scheme Algorithm", "[efuse]")
} }
} }
#if CONFIG_IDF_TARGET_ESP32
TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]") TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]")
{ {
int count_useful_reg = 0; int count_useful_reg = 0;
@ -174,9 +174,7 @@ TEST_CASE("Test Coding Scheme for efuse manager", "[efuse]")
esp_efuse_utility_reset(); esp_efuse_utility_reset();
bootloader_random_disable(); bootloader_random_disable();
} }
#endif
#if CONFIG_IDF_TARGET_ESP32
TEST_CASE("Test data does not match the coding scheme", "[efuse]") TEST_CASE("Test data does not match the coding scheme", "[efuse]")
{ {
int count_useful_reg = 0; int count_useful_reg = 0;
@ -206,4 +204,4 @@ TEST_CASE("Test data does not match the coding scheme", "[efuse]")
esp_efuse_utility_reset(); esp_efuse_utility_reset();
} }
#endif #endif

11
components/esp_eth/test/CMakeLists.txt
View file

@ -1,7 +1,4 @@
idf_build_get_property(target IDF_TARGET) idf_component_register(SRC_DIRS .
# Currently we only have unit test for esp32 INCLUDE_DIRS .
if(${target} STREQUAL "esp32") PRIV_REQUIRES unity test_utils esp_eth esp_http_client
idf_component_register(SRC_DIRS . )
INCLUDE_DIRS .
PRIV_REQUIRES unity test_utils esp_eth esp_http_client)
endif()

4
components/esp_eth/test/test_dm9051.c
View file

@ -11,6 +11,8 @@
#include "esp_log.h" #include "esp_log.h"
#include "driver/gpio.h" #include "driver/gpio.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
static const char *TAG = "dm9051_test"; static const char *TAG = "dm9051_test";
#define ETH_START_BIT BIT(0) #define ETH_START_BIT BIT(0)
@ -128,3 +130,5 @@ TEST_CASE("dm9051 io test", "[ethernet][dm9051][ignore]")
TEST_ESP_OK(spi_bus_free(HSPI_HOST)); TEST_ESP_OK(spi_bus_free(HSPI_HOST));
} }
#endif #endif
#endif

4
components/esp_eth/test/test_emac.c
View file

@ -15,6 +15,8 @@
#include "ping/ping_sock.h" #include "ping/ping_sock.h"
#include "esp32/rom/md5_hash.h" #include "esp32/rom/md5_hash.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
static const char *TAG = "esp32_eth_test"; static const char *TAG = "esp32_eth_test";
#define ETH_START_BIT BIT(0) #define ETH_START_BIT BIT(0)
@ -500,3 +502,5 @@ TEST_CASE("esp32 ethernet download test", "[ethernet][test_env=UT_T2_Ethernet][t
TEST_ESP_OK(esp_event_loop_delete_default()); TEST_ESP_OK(esp_event_loop_delete_default());
vEventGroupDelete(eth_event_group); vEventGroupDelete(eth_event_group);
} }
#endif

69
components/esp_event/test/test_event.c
View file

@ -288,39 +288,6 @@ static void test_teardown(void)
#define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) // convert counter value to seconds #define TIMER_SCALE (TIMER_BASE_CLK / TIMER_DIVIDER) // convert counter value to seconds
#define TIMER_INTERVAL0_SEC (2.0) // sample test interval for the first timer #define TIMER_INTERVAL0_SEC (2.0) // sample test interval for the first timer
#if CONFIG_ESP_EVENT_POST_FROM_ISR
static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data)
{
SemaphoreHandle_t *sem = (SemaphoreHandle_t*) event_handler_arg;
// Event data is just the address value (maybe have been truncated due to casting).
int *data = (int*) event_data;
TEST_ASSERT_EQUAL(*data, (int) (*sem));
xSemaphoreGive(*sem);
}
void IRAM_ATTR test_event_on_timer_alarm(void* para)
{
/* Retrieve the interrupt status and the counter value
from the timer that reported the interrupt */
uint64_t timer_counter_value =
timer_group_get_counter_value_in_isr(TIMER_GROUP_0, TIMER_0);
timer_group_clr_intr_status_in_isr(TIMER_GROUP_0, TIMER_0);
timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE);
timer_group_set_alarm_value_in_isr(TIMER_GROUP_0, TIMER_0, timer_counter_value);
int data = (int) para;
// Posting events with data more than 4 bytes should fail.
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, 5, NULL));
// This should succeedd, as data is int-sized. The handler for the event checks that the passed event data
// is correct.
BaseType_t task_unblocked;
TEST_ASSERT_EQUAL(ESP_OK, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, sizeof(data), &task_unblocked));
if (task_unblocked == pdTRUE) {
portYIELD_FROM_ISR();
}
}
#endif //CONFIG_ESP_EVENT_POST_FROM_ISR
TEST_CASE("can create and delete event loops", "[event]") TEST_CASE("can create and delete event loops", "[event]")
{ {
/* this test aims to verify that: /* this test aims to verify that:
@ -492,8 +459,8 @@ TEST_CASE("handler can unregister itself", "[event]")
/* /*
* s_test_base1, ev1 = 1 * s_test_base1, ev1 = 1
* s_test_base1, ev2 = 2 * s_test_base1, ev2 = 2
* s_test_base2, ev1 = 11 * s_test_base2, ev1 = 11
* s_test_base2, ev2 = 12 * s_test_base2, ev2 = 12
*/ */
int expected_unregistered = 0; int expected_unregistered = 0;
@ -1247,6 +1214,37 @@ TEST_CASE("can properly prepare event data posted to loop", "[event]")
TEST_TEARDOWN(); TEST_TEARDOWN();
} }
static void test_handler_post_from_isr(void* event_handler_arg, esp_event_base_t event_base, int32_t event_id, void* event_data)
{
SemaphoreHandle_t *sem = (SemaphoreHandle_t*) event_handler_arg;
// Event data is just the address value (maybe have been truncated due to casting).
int *data = (int*) event_data;
TEST_ASSERT_EQUAL(*data, (int) (*sem));
xSemaphoreGive(*sem);
}
void IRAM_ATTR test_event_on_timer_alarm(void* para)
{
/* Retrieve the interrupt status and the counter value
from the timer that reported the interrupt */
uint64_t timer_counter_value =
timer_group_get_counter_value_in_isr(TIMER_GROUP_0, TIMER_0);
timer_group_clr_intr_status_in_isr(TIMER_GROUP_0, TIMER_0);
timer_counter_value += (uint64_t) (TIMER_INTERVAL0_SEC * TIMER_SCALE);
timer_group_set_alarm_value_in_isr(TIMER_GROUP_0, TIMER_0, timer_counter_value);
int data = (int) para;
// Posting events with data more than 4 bytes should fail.
TEST_ASSERT_EQUAL(ESP_ERR_INVALID_ARG, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, 5, NULL));
// This should succeedd, as data is int-sized. The handler for the event checks that the passed event data
// is correct.
BaseType_t task_unblocked;
TEST_ASSERT_EQUAL(ESP_OK, esp_event_isr_post(s_test_base1, TEST_EVENT_BASE1_EV1, &data, sizeof(data), &task_unblocked));
if (task_unblocked == pdTRUE) {
portYIELD_FROM_ISR();
}
}
TEST_CASE("can post events from interrupt handler", "[event]") TEST_CASE("can post events from interrupt handler", "[event]")
{ {
SemaphoreHandle_t sem = xSemaphoreCreateBinary(); SemaphoreHandle_t sem = xSemaphoreCreateBinary();
@ -1282,4 +1280,5 @@ TEST_CASE("can post events from interrupt handler", "[event]")
TEST_TEARDOWN(); TEST_TEARDOWN();
} }
#endif // CONFIG_ESP_EVENT_POST_FROM_ISR #endif // CONFIG_ESP_EVENT_POST_FROM_ISR

7
components/esp_wifi/test/CMakeLists.txt
View file

@ -1,9 +1,4 @@
set(srcdirs ".") idf_component_register(SRC_DIRS .
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR} INCLUDE_DIRS . ${CMAKE_CURRENT_BINARY_DIR}
REQUIRES unity test_utils nvs_flash ulp esp_common REQUIRES unity test_utils nvs_flash ulp esp_common
) )

1
components/esp_wifi/test/component.mk
View file

@ -5,4 +5,3 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_SRCDIRS := . COMPONENT_SRCDIRS := .
COMPONENT_SRCDIRS += esp32

3
components/esp_wifi/test/esp32/test_phy_rtc.c → components/esp_wifi/test/test_phy_rtc.c
View file

@ -13,6 +13,7 @@
#include <freertos/semphr.h> #include <freertos/semphr.h>
#include "soc/soc_caps.h" #include "soc/soc_caps.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//Function just extern, need not test //Function just extern, need not test
#ifdef SOC_BT_SUPPORTED #ifdef SOC_BT_SUPPORTED
@ -98,3 +99,5 @@ TEST_CASE("Test PHY/RTC functions called when cache is disabled", "[phy_rtc][cac
vSemaphoreDelete(semphr_done); vSemaphoreDelete(semphr_done);
} }
#endif

4
components/esp_wifi/test/esp32/test_wifi.c → components/esp_wifi/test/test_wifi.c
View file

@ -169,6 +169,8 @@ TEST_CASE("wifi stop and deinit","[wifi]")
TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop."); TEST_IGNORE_MESSAGE("this test case is ignored due to the critical memory leak of esp_netif and event_loop.");
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
static void start_wifi_as_softap(void) static void start_wifi_as_softap(void)
{ {
wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT(); wifi_init_config_t cfg = WIFI_INIT_CONFIG_DEFAULT();
@ -340,3 +342,5 @@ static void test_wifi_connection_softap(void)
} }
TEST_CASE_MULTIPLE_DEVICES("test wifi retain connection for 60s", "[wifi][test_env=UT_T2_1][timeout=90]", test_wifi_connection_sta, test_wifi_connection_softap); TEST_CASE_MULTIPLE_DEVICES("test wifi retain connection for 60s", "[wifi][test_env=UT_T2_1][timeout=90]", test_wifi_connection_sta, test_wifi_connection_softap);
#endif

7
components/fatfs/test/CMakeLists.txt
View file

@ -1,9 +1,4 @@
set(srcdirs ".") idf_component_register(SRC_DIRS .
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs "esp32")
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS . INCLUDE_DIRS .
REQUIRES unity test_utils vfs fatfs REQUIRES unity test_utils vfs fatfs
EMBED_TXTFILES fatfs.img EMBED_TXTFILES fatfs.img

1
components/fatfs/test/component.mk
View file

@ -1,3 +1,2 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_EMBED_TXTFILES := fatfs.img COMPONENT_EMBED_TXTFILES := fatfs.img
COMPONENT_SRCDIRS += esp32

8
components/fatfs/test/esp32/test_fatfs_sdmmc.c → components/fatfs/test/test_fatfs_sdmmc.c
View file

@ -25,12 +25,14 @@
#include "esp_vfs_fat.h" #include "esp_vfs_fat.h"
#include "freertos/FreeRTOS.h" #include "freertos/FreeRTOS.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "driver/sdmmc_host.h"
#include "driver/sdmmc_defs.h" #include "driver/sdmmc_defs.h"
#include "sdmmc_cmd.h" #include "sdmmc_cmd.h"
#include "ff.h" #include "ff.h"
#include "../test_fatfs_common.h" #include "test_fatfs_common.h"
#include "soc/soc_caps.h"
#ifdef SOC_SDMMC_HOST_SUPPORTED
#include "driver/sdmmc_host.h"
static void test_setup(void) static void test_setup(void)
{ {
@ -294,3 +296,5 @@ TEST_CASE("(SD) opendir, readdir, rewinddir, seekdir work as expected using UTF-
test_teardown(); test_teardown();
} }
#endif // CONFIG_FATFS_API_ENCODING_UTF_8 && CONFIG_FATFS_CODEPAGE == 936 #endif // CONFIG_FATFS_API_ENCODING_UTF_8 && CONFIG_FATFS_CODEPAGE == 936
#endif

9
components/freertos/test/CMakeLists.txt
View file

@ -1,11 +1,4 @@
set(srcdirs .) idf_component_register(SRC_DIRS .
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs esp32)
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS . INCLUDE_DIRS .
REQUIRES unity test_utils REQUIRES unity test_utils
) )

1
components/freertos/test/component.mk
View file

@ -2,5 +2,4 @@
#Component Makefile #Component Makefile
# #
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive

4
components/freertos/test/esp32/test_freertos_task_delay_until.c → components/freertos/test/test_freertos_task_delay_until.c
View file

@ -25,6 +25,8 @@
#define TICKS_TO_MS(x) (((x)*1000)/TICK_RATE) #define TICKS_TO_MS(x) (((x)*1000)/TICK_RATE)
#define REF_TO_ROUND_MS(x) (((x)+500)/1000) #define REF_TO_ROUND_MS(x) (((x)+500)/1000)
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
static SemaphoreHandle_t task_delete_semphr; static SemaphoreHandle_t task_delete_semphr;
static void delaying_task(void* arg) static void delaying_task(void* arg)
@ -72,3 +74,5 @@ TEST_CASE("Test vTaskDelayUntil", "[freertos]")
vSemaphoreDelete(task_delete_semphr); vSemaphoreDelete(task_delete_semphr);
ref_clock_deinit(); ref_clock_deinit();
} }
#endif // CONFIG_IDF_TARGET_ESP32S2BETA

5
components/freertos/test/test_thread_local.c
View file

@ -11,6 +11,8 @@
#include "test_utils.h" #include "test_utils.h"
#include "sdkconfig.h" #include "sdkconfig.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
static __thread int tl_test_var1; static __thread int tl_test_var1;
static __thread uint8_t tl_test_var2 = 55; static __thread uint8_t tl_test_var2 = 55;
static __thread uint16_t tl_test_var3 = 44; static __thread uint16_t tl_test_var3 = 44;
@ -86,7 +88,7 @@ static void task_test_tls(void *arg)
} }
} }
TEST_CASE_ESP32("TLS test", "[freertos]") TEST_CASE("TLS test", "[freertos]")
{ {
const size_t stack_size = 3072; const size_t stack_size = 3072;
StackType_t s_stack[stack_size]; /* with 8KB test task stack (default) this test still has ~3KB headroom */ StackType_t s_stack[stack_size]; /* with 8KB test task stack (default) this test still has ~3KB headroom */
@ -107,4 +109,5 @@ TEST_CASE_ESP32("TLS test", "[freertos]")
} }
vTaskDelay(10); /* Make sure idle task can clean up s_task, before it goes out of scope */ vTaskDelay(10); /* Make sure idle task can clean up s_task, before it goes out of scope */
} }
#endif

4
components/heap/test/test_malloc_caps.c
View file

@ -81,14 +81,14 @@ TEST_CASE("Capabilities allocator test", "[heap]")
} }
printf("Test if allocating executable code still gives IRAM, even with dedicated IRAM region depleted\n"); printf("Test if allocating executable code still gives IRAM, even with dedicated IRAM region depleted\n");
if(free_iram) { if(free_iram) {
// (the allocation should come from D/IRAM) // (the allocation should come from D/IRAM)
free_iram = heap_caps_get_free_size(MALLOC_CAP_EXEC); free_iram = heap_caps_get_free_size(MALLOC_CAP_EXEC);
m1= heap_caps_malloc(MIN(free_iram / 2, 10*1024), MALLOC_CAP_EXEC); m1= heap_caps_malloc(MIN(free_iram / 2, 10*1024), MALLOC_CAP_EXEC);
printf("--> %p\n", m1); printf("--> %p\n", m1);
TEST_ASSERT((((int)m1)&0xFF000000)==0x40000000); TEST_ASSERT((((int)m1)&0xFF000000)==0x40000000);
for (x=0; x<10; x++) free(m2[x]); for (x=0; x<10; x++) free(m2[x]);
} else { } else {
// (the allocation should come from D/IRAM) // (the allocation should come from D/IRAM)
free_iram = heap_caps_get_free_size(MALLOC_CAP_EXEC); free_iram = heap_caps_get_free_size(MALLOC_CAP_EXEC);

4
components/heap/test/test_realloc.c
View file

@ -34,7 +34,7 @@ TEST_CASE("realloc shrink buffer with EXEC CAPS", "[heap]")
//y needs to fall in a compatible memory area of IRAM: //y needs to fall in a compatible memory area of IRAM:
TEST_ASSERT(esp_ptr_executable(y)); TEST_ASSERT(esp_ptr_executable(y));
free(y); free(y);
} }
@ -55,7 +55,7 @@ TEST_CASE("realloc move data to a new heap type", "[heap]")
TEST_ASSERT_EQUAL_HEX32_ARRAY(buf, b, 64/sizeof(uint32_t)); TEST_ASSERT_EQUAL_HEX32_ARRAY(buf, b, 64/sizeof(uint32_t));
// Move data back to DRAM // Move data back to DRAM
char *c = heap_caps_realloc(b, 48, MALLOC_CAP_8BIT); char *c = heap_caps_realloc(b, 48, MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(c); TEST_ASSERT_NOT_NULL(c);
TEST_ASSERT_NOT_EQUAL(b, c); TEST_ASSERT_NOT_EQUAL(b, c);
TEST_ASSERT(heap_caps_check_integrity(MALLOC_CAP_INVALID, true)); TEST_ASSERT(heap_caps_check_integrity(MALLOC_CAP_INVALID, true));

4
components/libsodium/test/test_sodium.c
View file

@ -37,13 +37,15 @@ TEST_CASE("box tests", "[libsodium]")
TEST_ASSERT_EQUAL(0, box2_xmain()); TEST_ASSERT_EQUAL(0, box2_xmain());
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
extern int ed25519_convert_xmain(void); extern int ed25519_convert_xmain(void);
TEST_CASE_ESP32("ed25519_convert tests", "[libsodium][timeout=60]") TEST_CASE("ed25519_convert tests", "[libsodium][timeout=60]")
{ {
printf("Running ed25519_convert\n"); printf("Running ed25519_convert\n");
TEST_ASSERT_EQUAL(0, ed25519_convert_xmain() ); TEST_ASSERT_EQUAL(0, ed25519_convert_xmain() );
} }
#endif
extern int sign_xmain(void); extern int sign_xmain(void);

4
components/mbedtls/test/test_mbedtls_sha.c
View file

@ -256,6 +256,7 @@ TEST_CASE("mbedtls SHA256 clone", "[mbedtls]")
TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha256_thousand_as, sha256, 32, "SHA256 cloned calculation"); TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha256_thousand_as, sha256, 32, "SHA256 cloned calculation");
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
typedef struct { typedef struct {
mbedtls_sha256_context ctx; mbedtls_sha256_context ctx;
uint8_t result[32]; uint8_t result[32];
@ -277,7 +278,7 @@ static void tskFinaliseSha(void *v_param)
} }
// No concurrent SHA sessions in esp32s2, only has one engine // No concurrent SHA sessions in esp32s2, only has one engine
TEST_CASE_ESP32("mbedtls SHA session passed between tasks" , "[mbedtls]") TEST_CASE("mbedtls SHA session passed between tasks" , "[mbedtls]")
{ {
finalise_sha_param_t param = { 0 }; finalise_sha_param_t param = { 0 };
@ -300,3 +301,4 @@ TEST_CASE_ESP32("mbedtls SHA session passed between tasks" , "[mbedtls]")
TEST_ASSERT_EQUAL(0, param.ret); TEST_ASSERT_EQUAL(0, param.ret);
TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha256_thousand_as, param.result, 32, "SHA256 result from other task"); TEST_ASSERT_EQUAL_MEMORY_MESSAGE(sha256_thousand_as, param.result, 32, "SHA256 result from other task");
} }
#endif

9
components/sdmmc/test/CMakeLists.txt
View file

@ -1,5 +1,4 @@
if(IDF_TARGET STREQUAL "esp32") idf_component_register(SRC_DIRS "."
idf_component_register(SRC_DIRS "." INCLUDE_DIRS "."
INCLUDE_DIRS "." REQUIRES unity sdmmc
REQUIRES unity sdmmc) )
endif()

87
components/sdmmc/test/test_sd.c
View file

@ -17,7 +17,10 @@
#include <string.h> #include <string.h>
#include "unity.h" #include "unity.h"
#include "driver/gpio.h" #include "driver/gpio.h"
#include "soc/soc_caps.h"
#ifdef SOC_SDMMC_HOST_SUPPORTED
#include "driver/sdmmc_host.h" #include "driver/sdmmc_host.h"
#endif
#include "driver/sdspi_host.h" #include "driver/sdspi_host.h"
#include "driver/sdmmc_defs.h" #include "driver/sdmmc_defs.h"
#include "sdmmc_cmd.h" #include "sdmmc_cmd.h"
@ -48,7 +51,7 @@
#define CD_WP_TEST_GPIO 18 #define CD_WP_TEST_GPIO 18
static void sd_test_board_power_on(void) __attribute__((unused)) static void sd_test_board_power_on(void)
{ {
gpio_set_direction(SD_TEST_BOARD_VSEL_GPIO, GPIO_MODE_OUTPUT); gpio_set_direction(SD_TEST_BOARD_VSEL_GPIO, GPIO_MODE_OUTPUT);
gpio_set_level(SD_TEST_BOARD_VSEL_GPIO, SD_TEST_BOARD_VSEL_3V3); gpio_set_level(SD_TEST_BOARD_VSEL_GPIO, SD_TEST_BOARD_VSEL_3V3);
@ -59,7 +62,7 @@ static void sd_test_board_power_on(void)
usleep(SD_TEST_BOARD_PWR_ON_DELAY_MS * 1000); usleep(SD_TEST_BOARD_PWR_ON_DELAY_MS * 1000);
} }
static void sd_test_board_power_off(void) __attribute__((unused)) static void sd_test_board_power_off(void)
{ {
gpio_set_level(SD_TEST_BOARD_VSEL_EN_GPIO, 0); gpio_set_level(SD_TEST_BOARD_VSEL_EN_GPIO, 0);
gpio_set_direction(SD_TEST_BOARD_VSEL_GPIO, GPIO_MODE_INPUT); gpio_set_direction(SD_TEST_BOARD_VSEL_GPIO, GPIO_MODE_INPUT);
@ -67,7 +70,6 @@ static void sd_test_board_power_off(void)
gpio_set_direction(SD_TEST_BOARD_VSEL_EN_GPIO, GPIO_MODE_INPUT); gpio_set_direction(SD_TEST_BOARD_VSEL_EN_GPIO, GPIO_MODE_INPUT);
} }
TEST_CASE("MMC_RSP_BITS", "[sd]") TEST_CASE("MMC_RSP_BITS", "[sd]")
{ {
uint32_t data[2] = { 0x01234567, 0x89abcdef }; uint32_t data[2] = { 0x01234567, 0x89abcdef };
@ -78,6 +80,8 @@ TEST_CASE("MMC_RSP_BITS", "[sd]")
TEST_ASSERT_EQUAL_HEX32(0x11, MMC_RSP_BITS(data, 59, 5)); TEST_ASSERT_EQUAL_HEX32(0x11, MMC_RSP_BITS(data, 59, 5));
} }
#ifdef SOC_SDMMC_HOST_SUPPORTED
static void probe_sd(int slot, int width, int freq_khz, int ddr) static void probe_sd(int slot, int width, int freq_khz, int ddr)
{ {
sd_test_board_power_on(); sd_test_board_power_on();
@ -111,28 +115,6 @@ static void probe_sd(int slot, int width, int freq_khz, int ddr)
sd_test_board_power_off(); sd_test_board_power_off();
} }
static void probe_spi(int freq_khz, int pin_miso, int pin_mosi, int pin_sck, int pin_cs)
{
sd_test_board_power_on();
sdmmc_host_t config = SDSPI_HOST_DEFAULT();
sdspi_slot_config_t slot_config = SDSPI_SLOT_CONFIG_DEFAULT();
slot_config.gpio_miso = pin_miso;
slot_config.gpio_mosi = pin_mosi;
slot_config.gpio_sck = pin_sck;
slot_config.gpio_cs = pin_cs;
TEST_ESP_OK(sdspi_host_init());
TEST_ESP_OK(sdspi_host_init_slot(config.slot, &slot_config));
sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t));
TEST_ASSERT_NOT_NULL(card);
TEST_ESP_OK(sdmmc_card_init(&config, card));
sdmmc_card_print_info(stdout, card);
TEST_ESP_OK(sdspi_host_deinit());
free(card);
sd_test_board_power_off();
}
TEST_CASE("probe SD, slot 1, 4-bit", "[sd][test_env=UT_T1_SDMODE]") TEST_CASE("probe SD, slot 1, 4-bit", "[sd][test_env=UT_T1_SDMODE]")
{ {
probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_PROBING, 0); probe_sd(SDMMC_HOST_SLOT_1, 4, SDMMC_FREQ_PROBING, 0);
@ -175,6 +157,31 @@ TEST_CASE("probe SD, slot 0, 1-bit", "[sd][test_env=UT_T1_SDCARD][ignore]")
probe_sd(SDMMC_HOST_SLOT_0, 1, SDMMC_FREQ_HIGHSPEED, 0); probe_sd(SDMMC_HOST_SLOT_0, 1, SDMMC_FREQ_HIGHSPEED, 0);
} }
#endif
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
static void probe_spi(int freq_khz, int pin_miso, int pin_mosi, int pin_sck, int pin_cs)
{
sd_test_board_power_on();
sdmmc_host_t config = SDSPI_HOST_DEFAULT();
sdspi_slot_config_t slot_config = SDSPI_SLOT_CONFIG_DEFAULT();
slot_config.gpio_miso = pin_miso;
slot_config.gpio_mosi = pin_mosi;
slot_config.gpio_sck = pin_sck;
slot_config.gpio_cs = pin_cs;
TEST_ESP_OK(sdspi_host_init());
TEST_ESP_OK(sdspi_host_init_slot(config.slot, &slot_config));
sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t));
TEST_ASSERT_NOT_NULL(card);
TEST_ESP_OK(sdmmc_card_init(&config, card));
sdmmc_card_print_info(stdout, card);
TEST_ESP_OK(sdspi_host_deinit());
free(card);
sd_test_board_power_off();
}
TEST_CASE("probe SD in SPI mode, slot 1", "[sd][test_env=UT_T1_SPIMODE]") TEST_CASE("probe SD in SPI mode, slot 1", "[sd][test_env=UT_T1_SPIMODE]")
{ {
probe_spi(SDMMC_FREQ_DEFAULT, 2, 15, 14, 13); probe_spi(SDMMC_FREQ_DEFAULT, 2, 15, 14, 13);
@ -185,10 +192,11 @@ TEST_CASE("probe SD in SPI mode, slot 0", "[sd][test_env=UT_T1_SDCARD][ignore]")
probe_spi(SDMMC_FREQ_DEFAULT, 7, 11, 6, 10); probe_spi(SDMMC_FREQ_DEFAULT, 7, 11, 6, 10);
} }
#endif //DISABLED(ESP32S2BETA)
// Fill buffer pointed to by 'dst' with 'count' 32-bit ints generated // Fill buffer pointed to by 'dst' with 'count' 32-bit ints generated
// from 'rand' with the starting value of 'seed' // from 'rand' with the starting value of 'seed'
static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) { __attribute__((unused)) static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) {
srand(seed); srand(seed);
for (size_t i = 0; i < count; ++i) { for (size_t i = 0; i < count; ++i) {
uint32_t val = rand(); uint32_t val = rand();
@ -198,7 +206,7 @@ static void fill_buffer(uint32_t seed, uint8_t* dst, size_t count) {
// Check if the buffer pointed to by 'dst' contains 'count' 32-bit // Check if the buffer pointed to by 'dst' contains 'count' 32-bit
// ints generated from 'rand' with the starting value of 'seed' // ints generated from 'rand' with the starting value of 'seed'
static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) { __attribute__((unused)) static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) {
srand(seed); srand(seed);
for (size_t i = 0; i < count; ++i) { for (size_t i = 0; i < count; ++i) {
uint32_t val; uint32_t val;
@ -207,7 +215,7 @@ static void check_buffer(uint32_t seed, const uint8_t* src, size_t count) {
} }
} }
static void do_single_write_read_test(sdmmc_card_t* card, __attribute__((unused)) static void do_single_write_read_test(sdmmc_card_t* card,
size_t start_block, size_t block_count, size_t alignment) size_t start_block, size_t block_count, size_t alignment)
{ {
size_t block_size = card->csd.sector_size; size_t block_size = card->csd.sector_size;
@ -242,7 +250,7 @@ static void do_single_write_read_test(sdmmc_card_t* card,
free(buffer); free(buffer);
} }
static void read_write_test(sdmmc_card_t* card) __attribute__((unused)) static void read_write_test(sdmmc_card_t* card)
{ {
sdmmc_card_print_info(stdout, card); sdmmc_card_print_info(stdout, card);
printf(" sector | count | align | size(kB) | wr_time(ms) | wr_speed(MB/s) | rd_time(ms) | rd_speed(MB/s)\n"); printf(" sector | count | align | size(kB) | wr_time(ms) | wr_speed(MB/s) | rd_time(ms) | rd_speed(MB/s)\n");
@ -267,6 +275,7 @@ static void read_write_test(sdmmc_card_t* card)
do_single_write_read_test(card, card->csd.capacity/2, 128, 1); do_single_write_read_test(card, card->csd.capacity/2, 128, 1);
} }
#ifdef SOC_SDMMC_HOST_SUPPORTED
void test_sd_rw_blocks(int slot, int width) void test_sd_rw_blocks(int slot, int width)
{ {
sdmmc_host_t config = SDMMC_HOST_DEFAULT(); sdmmc_host_t config = SDMMC_HOST_DEFAULT();
@ -311,7 +320,10 @@ TEST_CASE("SDMMC read/write test (eMMC slot 0, 8 line)", "[sd][test_env=EMMC]")
sd_test_board_power_off(); sd_test_board_power_off();
} }
#endif // WITH_EMMC_TEST #endif // WITH_EMMC_TEST
#endif // SDMMC_HOST_SUPPORTED
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
TEST_CASE("SDMMC read/write test (SD slot 1, in SPI mode)", "[sdspi][test_env=UT_T1_SPIMODE]") TEST_CASE("SDMMC read/write test (SD slot 1, in SPI mode)", "[sdspi][test_env=UT_T1_SPIMODE]")
{ {
sd_test_board_power_on(); sd_test_board_power_on();
@ -327,7 +339,9 @@ TEST_CASE("SDMMC read/write test (SD slot 1, in SPI mode)", "[sdspi][test_env=UT
TEST_ESP_OK(sdspi_host_deinit()); TEST_ESP_OK(sdspi_host_deinit());
sd_test_board_power_off(); sd_test_board_power_off();
} }
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)
#ifdef SOC_SDMMC_HOST_SUPPORTED
TEST_CASE("reads and writes with an unaligned buffer", "[sd][test_env=UT_T1_SDMODE]") TEST_CASE("reads and writes with an unaligned buffer", "[sd][test_env=UT_T1_SDMODE]")
{ {
sd_test_board_power_on(); sd_test_board_power_on();
@ -365,8 +379,9 @@ TEST_CASE("reads and writes with an unaligned buffer", "[sd][test_env=UT_T1_SDMO
TEST_ESP_OK(sdmmc_host_deinit()); TEST_ESP_OK(sdmmc_host_deinit());
sd_test_board_power_off(); sd_test_board_power_off();
} }
#endif
static void test_cd_input(int gpio_cd_num, const sdmmc_host_t* config) __attribute__((unused)) static void test_cd_input(int gpio_cd_num, const sdmmc_host_t* config)
{ {
sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t));
TEST_ASSERT_NOT_NULL(card); TEST_ASSERT_NOT_NULL(card);
@ -390,6 +405,7 @@ static void test_cd_input(int gpio_cd_num, const sdmmc_host_t* config)
free(card); free(card);
} }
#ifdef SOC_SDMMC_HOST_SUPPORTED
TEST_CASE("CD input works in SD mode", "[sd][test_env=UT_T1_SDMODE]") TEST_CASE("CD input works in SD mode", "[sd][test_env=UT_T1_SDMODE]")
{ {
sd_test_board_power_on(); sd_test_board_power_on();
@ -404,7 +420,10 @@ TEST_CASE("CD input works in SD mode", "[sd][test_env=UT_T1_SDMODE]")
TEST_ESP_OK(sdmmc_host_deinit()); TEST_ESP_OK(sdmmc_host_deinit());
sd_test_board_power_off(); sd_test_board_power_off();
} }
#endif
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
TEST_CASE("CD input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]") TEST_CASE("CD input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]")
{ {
sd_test_board_power_on(); sd_test_board_power_on();
@ -419,8 +438,9 @@ TEST_CASE("CD input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]")
TEST_ESP_OK(sdspi_host_deinit()); TEST_ESP_OK(sdspi_host_deinit());
sd_test_board_power_off(); sd_test_board_power_off();
} }
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)
static void test_wp_input(int gpio_wp_num, const sdmmc_host_t* config) __attribute__((unused)) static void test_wp_input(int gpio_wp_num, const sdmmc_host_t* config)
{ {
sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t)); sdmmc_card_t* card = malloc(sizeof(sdmmc_card_t));
TEST_ASSERT_NOT_NULL(card); TEST_ASSERT_NOT_NULL(card);
@ -453,6 +473,7 @@ static void test_wp_input(int gpio_wp_num, const sdmmc_host_t* config)
free(card); free(card);
} }
#ifdef SOC_SDMMC_HOST_SUPPORTED
TEST_CASE("WP input works in SD mode", "[sd][test_env=UT_T1_SDMODE]") TEST_CASE("WP input works in SD mode", "[sd][test_env=UT_T1_SDMODE]")
{ {
sd_test_board_power_on(); sd_test_board_power_on();
@ -467,7 +488,10 @@ TEST_CASE("WP input works in SD mode", "[sd][test_env=UT_T1_SDMODE]")
TEST_ESP_OK(sdmmc_host_deinit()); TEST_ESP_OK(sdmmc_host_deinit());
sd_test_board_power_off(); sd_test_board_power_off();
} }
#endif
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
//No runners
TEST_CASE("WP input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]") TEST_CASE("WP input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]")
{ {
sd_test_board_power_on(); sd_test_board_power_on();
@ -482,3 +506,4 @@ TEST_CASE("WP input works in SPI mode", "[sd][test_env=UT_T1_SPIMODE]")
TEST_ESP_OK(sdspi_host_deinit()); TEST_ESP_OK(sdspi_host_deinit());
sd_test_board_power_off(); sd_test_board_power_off();
} }
#endif //DISABLED_FOR_TARGETS(ESP32S2BETA)

4
components/sdmmc/test/test_sdio.c
View file

@ -12,6 +12,9 @@
// See the License for the specific language governing permissions and // See the License for the specific language governing permissions and
// limitations under the License. // limitations under the License.
#include "soc/soc_caps.h"
#ifdef SOC_SDMMC_HOST_SUPPORTED
#include <stdio.h> #include <stdio.h>
#include <stdlib.h> #include <stdlib.h>
#include <string.h> #include <string.h>
@ -382,3 +385,4 @@ TEST_CASE("can probe and talk to ESP32 SDIO slave", "[sdio][ignore]")
free(card); free(card);
} }
#endif

1
components/spi_flash/test/component.mk
View file

@ -2,7 +2,6 @@
#Component Makefile #Component Makefile
# #
COMPONENT_SRCDIRS += esp32
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
ifdef CONFIG_SPI_FLASH_USE_LEGACY_IMPL ifdef CONFIG_SPI_FLASH_USE_LEGACY_IMPL

34
components/spi_flash/test/test_esp_flash.c
View file

@ -73,12 +73,12 @@ typedef void (*flash_test_func_t)(esp_flash_t* chip);
#define FLASH_TEST_CASE(STR, FUNC_TO_RUN) \ #define FLASH_TEST_CASE(STR, FUNC_TO_RUN) \
TEST_CASE(STR, "[esp_flash]") {flash_test_func(FUNC_TO_RUN, 1);} TEST_CASE(STR, "[esp_flash]") {flash_test_func(FUNC_TO_RUN, 1);}
#ifdef CONFIG_ESP32_SPIRAM_SUPPORT #if defined(CONFIG_SPIRAM_SUPPORT) || TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
// These tests needs external flash, right on the place of psram // These tests needs external flash, right on the place of psram
#define FLASH_TEST_CASE_3(STR, FUNCT_TO_RUN) #define FLASH_TEST_CASE_3(STR, FUNCT_TO_RUN)
#else #else
#define FLASH_TEST_CASE_3(STR, FUNC_TO_RUN) \ #define FLASH_TEST_CASE_3(STR, FUNC_TO_RUN) \
TEST_CASE_ESP32(STR", 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]") {flash_test_func(FUNC_TO_RUN, ALL_TEST_NUM);} TEST_CASE(STR", 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]") {flash_test_func(FUNC_TO_RUN, ALL_TEST_NUM);}
#endif #endif
//currently all the configs are the same with esp_flash_spi_device_config_t, no more information required //currently all the configs are the same with esp_flash_spi_device_config_t, no more information required
@ -100,7 +100,7 @@ static const char TAG[] = "test_esp_flash";
/* the pin which is usually used by the PSRAM */ \ /* the pin which is usually used by the PSRAM */ \
.cs_io_num = 16, \ .cs_io_num = 16, \
.input_delay_ns = 0, \ .input_delay_ns = 0, \
} }
#if CONFIG_IDF_TARGET_ESP32 #if CONFIG_IDF_TARGET_ESP32
flashtest_config_t config_list[] = { flashtest_config_t config_list[] = {
@ -112,7 +112,7 @@ flashtest_config_t config_list[] = {
// .host_id = HSPI_HOST, // .host_id = HSPI_HOST,
// .cs_id = 0, // .cs_id = 0,
// // uses GPIO matrix on esp32s2beta regardles if FORCE_GPIO_MATRIX // // uses GPIO matrix on esp32s2beta regardles if FORCE_GPIO_MATRIX
// .cs_io_num = HSPI_PIN_NUM_CS, // .cs_io_num = HSPI_PIN_NUM_CS,
// .input_delay_ns = 20, // .input_delay_ns = 20,
// }, // },
{ {
@ -120,7 +120,7 @@ flashtest_config_t config_list[] = {
.speed = TEST_SPI_SPEED, .speed = TEST_SPI_SPEED,
.host_id = VSPI_HOST, .host_id = VSPI_HOST,
.cs_id = 0, .cs_id = 0,
.cs_io_num = VSPI_PIN_NUM_CS, .cs_io_num = VSPI_PIN_NUM_CS,
.input_delay_ns = 0, .input_delay_ns = 0,
}, },
}; };
@ -143,7 +143,7 @@ flashtest_config_t config_list[] = {
// .host_id = HSPI_HOST, // .host_id = HSPI_HOST,
// .cs_id = 0, // .cs_id = 0,
// // uses GPIO matrix on esp32s2beta regardles if FORCE_GPIO_MATRIX // // uses GPIO matrix on esp32s2beta regardles if FORCE_GPIO_MATRIX
// .cs_io_num = HSPI_PIN_NUM_CS, // .cs_io_num = HSPI_PIN_NUM_CS,
// .input_delay_ns = 20, // .input_delay_ns = 20,
// }, // },
}; };
@ -157,7 +157,7 @@ static void setup_bus(spi_host_device_t host_id)
#ifdef EXTRA_SPI1_CLK_IO #ifdef EXTRA_SPI1_CLK_IO
gpio_matrix_out(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0); gpio_matrix_out(EXTRA_SPI1_CLK_IO, SPICLK_OUT_IDX, 0, 0);
#endif #endif
#if CONFIG_IDF_TARGET_ESP32S2BETA #if !DISABLED_FOR_TARGETS(ESP32)
} else if (host_id == FSPI_HOST) { } else if (host_id == FSPI_HOST) {
ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1); ESP_LOGI(TAG, "setup flash on SPI%d (FSPI) CS0...\n", host_id + 1);
spi_bus_config_t fspi_bus_cfg = { spi_bus_config_t fspi_bus_cfg = {
@ -185,7 +185,7 @@ static void setup_bus(spi_host_device_t host_id)
.quadwp_io_num = HSPI_PIN_NUM_WP, .quadwp_io_num = HSPI_PIN_NUM_WP,
.max_transfer_sz = 64, .max_transfer_sz = 64,
}; };
#ifdef CONFIG_IDF_TARGET_ESP32 #if !DISABLED_FOR_TARGETS(ESP32S2BETA)
#ifdef FORCE_GPIO_MATRIX #ifdef FORCE_GPIO_MATRIX
hspi_bus_cfg.quadhd_io_num = 23; hspi_bus_cfg.quadhd_io_num = 23;
#endif #endif
@ -193,7 +193,7 @@ static void setup_bus(spi_host_device_t host_id)
esp_err_t ret = spi_bus_initialize(host_id, &hspi_bus_cfg, 0); esp_err_t ret = spi_bus_initialize(host_id, &hspi_bus_cfg, 0);
TEST_ESP_OK(ret); TEST_ESP_OK(ret);
#ifdef CONFIG_IDF_TARGET_ESP32S2BETA #if !DISABLED_FOR_TARGETS(ESP32)
// HSPI have no multiline mode, use GPIO to pull those pins up // HSPI have no multiline mode, use GPIO to pull those pins up
gpio_set_direction(HSPI_PIN_NUM_HD, GPIO_MODE_OUTPUT); gpio_set_direction(HSPI_PIN_NUM_HD, GPIO_MODE_OUTPUT);
gpio_set_level(HSPI_PIN_NUM_HD, 1); gpio_set_level(HSPI_PIN_NUM_HD, 1);
@ -201,8 +201,8 @@ static void setup_bus(spi_host_device_t host_id)
gpio_set_direction(HSPI_PIN_NUM_WP, GPIO_MODE_OUTPUT); gpio_set_direction(HSPI_PIN_NUM_WP, GPIO_MODE_OUTPUT);
gpio_set_level(HSPI_PIN_NUM_WP, 1); gpio_set_level(HSPI_PIN_NUM_WP, 1);
#endif #endif
} }
#if CONFIG_IDF_TARGET_ESP32 #if !DISABLED_FOR_TARGETS(ESP32S2BETA)
else if (host_id == VSPI_HOST) { else if (host_id == VSPI_HOST) {
ESP_LOGI(TAG, "setup flash on SPI%d (VSPI) CS0...\n", host_id + 1); ESP_LOGI(TAG, "setup flash on SPI%d (VSPI) CS0...\n", host_id + 1);
spi_bus_config_t vspi_bus_cfg = { spi_bus_config_t vspi_bus_cfg = {
@ -218,8 +218,8 @@ static void setup_bus(spi_host_device_t host_id)
#endif #endif
esp_err_t ret = spi_bus_initialize(host_id, &vspi_bus_cfg, 0); esp_err_t ret = spi_bus_initialize(host_id, &vspi_bus_cfg, 0);
TEST_ESP_OK(ret); TEST_ESP_OK(ret);
} }
#endif // CONFIG_IDF_TARGET_ESP32 #endif // disabled for esp32s2beta
else { else {
ESP_LOGE(TAG, "invalid bus"); ESP_LOGE(TAG, "invalid bus");
} }
@ -584,7 +584,7 @@ void test_permutations(flashtest_config_t* config)
cfg->speed = speed; cfg->speed = speed;
setup_new_chip(cfg, &chip); setup_new_chip(cfg, &chip);
if (io_mode > SPI_FLASH_FASTRD if (io_mode > SPI_FLASH_FASTRD
&& !SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(((spi_flash_memspi_data_t *)chip->host->driver_data)->spi)) { && !SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(((spi_flash_memspi_data_t *)chip->host->driver_data)->spi)) {
continue; continue;
} }
@ -611,14 +611,16 @@ TEST_CASE("SPI flash test reading with all speed/mode permutations", "[esp_flash
test_permutations(&config_list[0]); test_permutations(&config_list[0]);
} }
#ifndef CONFIG_ESP32_SPIRAM_SUPPORT #ifndef CONFIG_SPIRAM_SUPPORT
TEST_CASE_ESP32("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]") #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
TEST_CASE("SPI flash test reading with all speed/mode permutations, 3 chips", "[esp_flash][test_env=UT_T1_ESP_FLASH]")
{ {
for (int i = 0; i < ALL_TEST_NUM; i++) { for (int i = 0; i < ALL_TEST_NUM; i++) {
test_permutations(&config_list[i]); test_permutations(&config_list[i]);
} }
} }
#endif #endif
#endif
static void test_write_large_const_buffer(esp_flash_t* chip) static void test_write_large_const_buffer(esp_flash_t* chip)
{ {

16
components/spi_flash/test/test_mmap.c
View file

@ -93,7 +93,8 @@ static void setup_mmap_tests(void)
} }
} }
TEST_CASE_ESP32("Can mmap into data address space", "[spi_flash][mmap]") #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
TEST_CASE("Can mmap into data address space", "[spi_flash][mmap]")
{ {
setup_mmap_tests(); setup_mmap_tests();
@ -153,7 +154,7 @@ TEST_CASE_ESP32("Can mmap into data address space", "[spi_flash][mmap]")
TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA)); TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA));
} }
TEST_CASE_ESP32("Can mmap into instruction address space", "[spi_flash][mmap]") TEST_CASE("Can mmap into instruction address space", "[spi_flash][mmap]")
{ {
setup_mmap_tests(); setup_mmap_tests();
@ -209,7 +210,7 @@ TEST_CASE_ESP32("Can mmap into instruction address space", "[spi_flash][mmap]")
} }
TEST_CASE_ESP32("Can mmap unordered pages into contiguous memory", "[spi_flash][mmap]") TEST_CASE("Can mmap unordered pages into contiguous memory", "[spi_flash][mmap]")
{ {
int nopages; int nopages;
int *pages; int *pages;
@ -250,6 +251,7 @@ TEST_CASE_ESP32("Can mmap unordered pages into contiguous memory", "[spi_flash][
spi_flash_munmap(handle1); spi_flash_munmap(handle1);
spi_flash_mmap_dump(); spi_flash_mmap_dump();
} }
#endif
TEST_CASE("flash_mmap invalidates just-written data", "[spi_flash][mmap]") TEST_CASE("flash_mmap invalidates just-written data", "[spi_flash][mmap]")
@ -350,7 +352,8 @@ TEST_CASE("flash_mmap can mmap after get enough free MMU pages", "[spi_flash][mm
TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA)); TEST_ASSERT_EQUAL_PTR(NULL, spi_flash_phys2cache(start, SPI_FLASH_MMAP_DATA));
} }
TEST_CASE_ESP32("phys2cache/cache2phys basic checks", "[spi_flash][mmap]") #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
TEST_CASE("phys2cache/cache2phys basic checks", "[spi_flash][mmap]")
{ {
uint8_t buf[64]; uint8_t buf[64];
@ -382,6 +385,7 @@ TEST_CASE_ESP32("phys2cache/cache2phys basic checks", "[spi_flash][mmap]")
spi_flash_read_maybe_encrypted(phys, buf, sizeof(constant_data)); spi_flash_read_maybe_encrypted(phys, buf, sizeof(constant_data));
TEST_ASSERT_EQUAL_HEX8_ARRAY(constant_data, buf, sizeof(constant_data)); TEST_ASSERT_EQUAL_HEX8_ARRAY(constant_data, buf, sizeof(constant_data));
} }
#endif
TEST_CASE("mmap consistent with phys2cache/cache2phys", "[spi_flash][mmap]") TEST_CASE("mmap consistent with phys2cache/cache2phys", "[spi_flash][mmap]")
{ {
@ -427,7 +431,8 @@ TEST_CASE("munmap followed by mmap flushes cache", "[spi_flash][mmap]")
TEST_ASSERT_NOT_EQUAL(0, memcmp(buf, data, sizeof(buf))); TEST_ASSERT_NOT_EQUAL(0, memcmp(buf, data, sizeof(buf)));
} }
TEST_CASE_ESP32("no stale data read post mmap and write partition", "[spi_flash][mmap]") #if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
TEST_CASE("no stale data read post mmap and write partition", "[spi_flash][mmap]")
{ {
/* Buffer size is set to 32 to allow encrypted flash writes */ /* Buffer size is set to 32 to allow encrypted flash writes */
const char buf[32] = "Test buffer data for partition"; const char buf[32] = "Test buffer data for partition";
@ -451,3 +456,4 @@ TEST_CASE_ESP32("no stale data read post mmap and write partition", "[spi_flash]
spi_flash_munmap(handle); spi_flash_munmap(handle);
TEST_ASSERT_EQUAL(0, memcmp(buf, read_data, sizeof(buf))); TEST_ASSERT_EQUAL(0, memcmp(buf, read_data, sizeof(buf)));
} }
#endif

5
components/spi_flash/test/test_partition_ext.c
View file

@ -2,8 +2,8 @@
#include "esp_partition.h" #include "esp_partition.h"
#include "unity.h" #include "unity.h"
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
TEST_CASE_ESP32("Basic handling of a partition in external flash", "[partition]") TEST_CASE("Basic handling of a partition in external flash", "[partition]")
{ {
esp_flash_t flash = { esp_flash_t flash = {
.size = 1 * 1024 * 1024, .size = 1 * 1024 * 1024,
@ -45,3 +45,4 @@ TEST_CASE_ESP32("Basic handling of a partition in external flash", "[partition]"
"p2", t, st, NULL)); "p2", t, st, NULL));
TEST_ESP_OK(esp_partition_deregister_external(ext_partition)); TEST_ESP_OK(esp_partition_deregister_external(ext_partition));
} }
#endif

4
components/spi_flash/test/test_read_write.c
View file

@ -139,6 +139,7 @@ TEST_CASE("Test spi_flash_read", "[spi_flash][esp_flash]")
#endif #endif
} }
#if !TEMPORARY_DISABLED_FOR_TARGETS(ESP32S2BETA)
static void IRAM_ATTR test_write(int dst_off, int src_off, int len) static void IRAM_ATTR test_write(int dst_off, int src_off, int len)
{ {
char src_buf[64], dst_gold[64]; char src_buf[64], dst_gold[64];
@ -168,7 +169,7 @@ static void IRAM_ATTR test_write(int dst_off, int src_off, int len)
TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0); TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
} }
TEST_CASE_ESP32("Test spi_flash_write", "[spi_flash][esp_flash]") TEST_CASE("Test spi_flash_write", "[spi_flash][esp_flash]")
{ {
setup_tests(); setup_tests();
#if CONFIG_SPI_FLASH_MINIMAL_TEST #if CONFIG_SPI_FLASH_MINIMAL_TEST
@ -239,6 +240,7 @@ TEST_CASE_ESP32("Test spi_flash_write", "[spi_flash][esp_flash]")
ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40080000, 16)); ESP_ERROR_CHECK(spi_flash_write(start, (char *) 0x40080000, 16));
#endif #endif
} }
#endif
#ifdef CONFIG_SPIRAM #ifdef CONFIG_SPIRAM

10
components/wear_levelling/test/CMakeLists.txt
View file

@ -1,11 +1,5 @@
set(srcdirs .) idf_component_register(SRC_DIRS .
if(IDF_TARGET STREQUAL "esp32")
list(APPEND srcdirs esp32)
endif()
idf_component_register(SRC_DIRS ${srcdirs}
INCLUDE_DIRS . INCLUDE_DIRS .
REQUIRES unity test_utils wear_levelling REQUIRES unity test_utils wear_levelling
EMBED_FILES test_partition_v1.bin EMBED_FILES test_partition_v1.bin
) )

1
components/wear_levelling/test/component.mk
View file

@ -1,3 +1,2 @@
COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive COMPONENT_ADD_LDFLAGS = -Wl,--whole-archive -l$(COMPONENT_NAME) -Wl,--no-whole-archive
COMPONENT_EMBED_FILES := test_partition_v1.bin COMPONENT_EMBED_FILES := test_partition_v1.bin
COMPONENT_SRCDIRS += esp32

88
components/wear_levelling/test/esp32/test_wl.c
View file

@ -1,88 +0,0 @@
#include <string.h>
#include "unity.h"
#include "wear_levelling.h"
#include "test_utils.h"
#include "freertos/FreeRTOS.h"
#include "freertos/portable.h"
#include "freertos/task.h"
#include "freertos/semphr.h"
#include "soc/cpu.h"
#include "esp32/clk.h"
#define TEST_SECTORS_COUNT 8
static void check_mem_data(wl_handle_t handle, uint32_t init_val, uint32_t* buff)
{
size_t sector_size = wl_sector_size(handle);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
TEST_ESP_OK(wl_read(handle, sector_size * m, buff, sector_size));
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
uint32_t compare_val = init_val + i + m*sector_size;
TEST_ASSERT_EQUAL( buff[i], compare_val);
}
}
}
// We write complete memory with defined data
// And then write one sector many times.
// A data in other secors should be the same.
// We do this also with unmount
TEST_CASE("multiple write is correct", "[wear_levelling]")
{
const esp_partition_t *partition = get_test_data_partition();
esp_partition_t fake_partition;
memcpy(&fake_partition, partition, sizeof(fake_partition));
fake_partition.size = SPI_FLASH_SEC_SIZE*(4 + TEST_SECTORS_COUNT);
wl_handle_t handle;
TEST_ESP_OK(wl_mount(&fake_partition, &handle));
size_t sector_size = wl_sector_size(handle);
// Erase 8 sectors
TEST_ESP_OK(wl_erase_range(handle, 0, sector_size * TEST_SECTORS_COUNT));
// Write data to all sectors
printf("Check 1 sector_size=0x%08x\n", sector_size);
// Set initial random value
uint32_t init_val = rand();
uint32_t* buff = (uint32_t*)malloc(sector_size);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + m*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*m, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*m, buff, sector_size));
}
check_mem_data(handle, init_val, buff);
uint32_t start;
RSR(CCOUNT, start);
for (int m=0 ; m< 100000 ; m++) {
uint32_t sector = m % TEST_SECTORS_COUNT;
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + sector*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*sector, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*sector, buff, sector_size));
check_mem_data(handle, init_val, buff);
uint32_t end;
RSR(CCOUNT, end);
uint32_t ms = (end - start) / (esp_clk_cpu_freq() / 1000);
printf("loop %4i pass, time= %ims\n", m, ms);
if (ms > 10000) {
break;
}
}
free(buff);
wl_unmount(handle);
}

81
components/wear_levelling/test/test_wl.c
View file

@ -1,3 +1,4 @@
#include "sdkconfig.h"
#include <string.h> #include <string.h>
#include "unity.h" #include "unity.h"
#include "wear_levelling.h" #include "wear_levelling.h"
@ -6,6 +7,11 @@
#include "freertos/portable.h" #include "freertos/portable.h"
#include "freertos/task.h" #include "freertos/task.h"
#include "freertos/semphr.h" #include "freertos/semphr.h"
#ifdef CONFIG_IDF_TARGET_ESP32
#include "esp32/clk.h"
#elif defined(CONFIG_IDF_TARGET_ESP32S2BETA)
#include "esp32s2beta/clk.h"
#endif
#include "soc/cpu.h" #include "soc/cpu.h"
TEST_CASE("wl_unmount doesn't leak memory", "[wear_levelling]") TEST_CASE("wl_unmount doesn't leak memory", "[wear_levelling]")
@ -176,6 +182,81 @@ TEST_CASE("multiple tasks can access wl handle simultaneously", "[wear_levelling
wl_unmount(handle); wl_unmount(handle);
} }
#define TEST_SECTORS_COUNT 8
static void check_mem_data(wl_handle_t handle, uint32_t init_val, uint32_t* buff)
{
size_t sector_size = wl_sector_size(handle);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
TEST_ESP_OK(wl_read(handle, sector_size * m, buff, sector_size));
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
uint32_t compare_val = init_val + i + m*sector_size;
TEST_ASSERT_EQUAL( buff[i], compare_val);
}
}
}
// We write complete memory with defined data
// And then write one sector many times.
// A data in other secors should be the same.
// We do this also with unmount
TEST_CASE("multiple write is correct", "[wear_levelling]")
{
const esp_partition_t *partition = get_test_data_partition();
esp_partition_t fake_partition;
memcpy(&fake_partition, partition, sizeof(fake_partition));
fake_partition.size = SPI_FLASH_SEC_SIZE*(4 + TEST_SECTORS_COUNT);
wl_handle_t handle;
TEST_ESP_OK(wl_mount(&fake_partition, &handle));
size_t sector_size = wl_sector_size(handle);
// Erase 8 sectors
TEST_ESP_OK(wl_erase_range(handle, 0, sector_size * TEST_SECTORS_COUNT));
// Write data to all sectors
printf("Check 1 sector_size=0x%08x\n", sector_size);
// Set initial random value
uint32_t init_val = rand();
uint32_t* buff = (uint32_t*)malloc(sector_size);
for (int m=0 ; m < TEST_SECTORS_COUNT ; m++) {
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + m*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*m, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*m, buff, sector_size));
}
check_mem_data(handle, init_val, buff);
uint32_t start;
RSR(CCOUNT, start);
for (int m=0 ; m< 100000 ; m++) {
uint32_t sector = m % TEST_SECTORS_COUNT;
for (int i=0 ; i< sector_size/sizeof(uint32_t) ; i++) {
buff[i] = init_val + i + sector*sector_size;
}
TEST_ESP_OK(wl_erase_range(handle, sector_size*sector, sector_size));
TEST_ESP_OK(wl_write(handle, sector_size*sector, buff, sector_size));
check_mem_data(handle, init_val, buff);
uint32_t end;
RSR(CCOUNT, end);
uint32_t ms = (end - start) / (esp_clk_cpu_freq() / 1000);
printf("loop %4i pass, time= %ims\n", m, ms);
if (ms > 10000) {
break;
}
}
free(buff);
wl_unmount(handle);
}
extern const uint8_t test_partition_v1_bin_start[] asm("_binary_test_partition_v1_bin_start"); extern const uint8_t test_partition_v1_bin_start[] asm("_binary_test_partition_v1_bin_start");
extern const uint8_t test_partition_v1_bin_end[] asm("_binary_test_partition_v1_bin_end"); extern const uint8_t test_partition_v1_bin_end[] asm("_binary_test_partition_v1_bin_end");

6
tools/unit-test-app/components/test_utils/test/ccomp_timer_test_inst.c
View file

@ -62,7 +62,7 @@ __aligned(CACHE_SIZE / CACHE_WAYS) static void test_func3(void)
FUNC(); FUNC();
} }
#if CONFIG_IDF_TARGET_ESP32S2BETA #if TEMPORARY_DISABLED_FOR_TARGETS(ESP32)
__aligned(CACHE_SIZE / CACHE_WAYS) static void test_func4(void) __aligned(CACHE_SIZE / CACHE_WAYS) static void test_func4(void)
{ {
FUNC(); FUNC();
@ -154,7 +154,7 @@ static ccomp_test_time_t IRAM_ATTR perform_test_at_hit_rate(int hit_rate)
static portMUX_TYPE m = portMUX_INITIALIZER_UNLOCKED; static portMUX_TYPE m = portMUX_INITIALIZER_UNLOCKED;
ccomp_test_call_t calls; ccomp_test_call_t calls;
ccomp_test_func_t alts[] = {test_func1, test_func2, test_func3, ccomp_test_func_t alts[] = {test_func1, test_func2, test_func3,
#if CONFIG_IDF_TARGET_ESP32S2BETA #if TEMPORARY_DISABLED_FOR_TARGETS(ESP32)
test_func4, test_func5, test_func6, test_func7, test_func8, test_func9, test_func4, test_func5, test_func6, test_func7, test_func8, test_func9,
#endif #endif
}; };
@ -222,7 +222,7 @@ TEST_CASE("instruction cache hit rate sweep test", "[test_utils][ccomp_timer]")
ESP_LOGI(TAG, "Hit Rate(%%): %d Wall Time(us): %lld Compensated Time(us): %lld Error(%%): %f", i, (long long)t_hr.wall, (long long)t_hr.ccomp, error); ESP_LOGI(TAG, "Hit Rate(%%): %d Wall Time(us): %lld Compensated Time(us): %lld Error(%%): %f", i, (long long)t_hr.wall, (long long)t_hr.ccomp, error);
// Check if the measured time is at least within some percent of the // Check if the measured time is at least within some percent of the
// reference. // reference.
TEST_ASSERT(error <= 5.0f); TEST_ASSERT(error <= 5.0f);
} }