linker script: Add some comments about significance of 0x18 byte offset
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1 changed files with 11 additions and 1 deletions
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@ -25,9 +25,17 @@ MEMORY
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash */
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/* Even though the segment name is iram, it is actually mapped to flash
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*/
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
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/*
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(0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
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which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
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cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
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*/
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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@ -39,6 +47,8 @@ MEMORY
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/* Flash mapped constant data */
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
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drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
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/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
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/* RTC fast memory (executable). Persists over deep sleep.
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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