diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld
index 8648021cb..b27a49eeb 100644
--- a/components/esp32/ld/esp32.ld
+++ b/components/esp32/ld/esp32.ld
@@ -25,9 +25,17 @@ MEMORY
   /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
   iram0_0_seg (RX) :                 org = 0x40080000, len = 0x20000
 
-  /* Even though the segment name is iram, it is actually mapped to flash */
+  /* Even though the segment name is iram, it is actually mapped to flash
+  */
   iram0_2_seg (RX) :                 org = 0x400D0018, len = 0x330000-0x18
 
+  /*
+    (0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
+    which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
+    cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
+  */
+
+
   /* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
 
      Enabling Bluetooth & Trace Memory features in menuconfig will decrease
@@ -39,6 +47,8 @@ MEMORY
   /* Flash mapped constant data */
   drom0_0_seg (R) :                  org = 0x3F400018, len = 0x400000-0x18
 
+  /* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
+
   /* RTC fast memory (executable). Persists over deep sleep.
    */
   rtc_iram_seg(RWX) :                org = 0x400C0000, len = 0x2000