esp32: Pass memory layout linker script through C preprocessor
C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
This commit is contained in:
Angus Gratton
Wu Jian Gang
parent
5f45cbc16a
commit
2c6ab8579a
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@ -21,3 +21,9 @@ config BT_ENABLED
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# This enables classic BT support
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endmenu
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# Memory reserved at start of DRAM for Bluetooth stack
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config BT_RESERVE_DRAM
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hex
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default 0x10000 if MEMMAP_BT
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default 0
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@ -12,21 +12,7 @@ COMPONENT_SRCDIRS := . hwcrypto
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LIBS := crypto core net80211 phy rtc pp wpa wps
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ifeq ($(CONFIG_MEMMAP_BT),y)
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ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
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LINKER_SCRIPTS = -T esp32.bt.trace.ld
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else
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LINKER_SCRIPTS = -T esp32.bt.ld
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endif
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else
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ifeq ($(CONFIG_MEMMAP_TRACEMEM),y)
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LINKER_SCRIPTS = -T esp32.trace.ld
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else
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LINKER_SCRIPTS = -T esp32.ld
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endif
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endif
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LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld
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LINKER_SCRIPTS += -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld
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COMPONENT_ADD_LDFLAGS := -lesp32 \
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$(abspath libhal.a) \
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@ -51,3 +37,14 @@ $(eval $(call SubmoduleRequiredForFiles,$(ALL_LIB_FILES)))
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# It would be better for components to be able to expose any of these
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# non-standard dependencies via get_variable, but this will do for now.
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$(COMPONENT_LIBRARY): $(ALL_LIB_FILES)
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# Preprocess esp32.ld linker script into esp32_out.ld
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#
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# The library doesn't really depend on esp32_out.ld, but it
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# saves us from having to add the target to a Makefile.projbuild
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$(COMPONENT_LIBRARY): esp32_out.ld
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esp32_out.ld: $(COMPONENT_PATH)/ld/esp32.ld ../include/sdkconfig.h
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$(CC) -I ../include -C -P -x c -E $< -o $@
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COMPONENT_EXTRA_CLEAN := esp32_out.ld
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@ -1,20 +0,0 @@
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x40000 /* Shared RAM, minus rom bss/data/stack.*/
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000
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}
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_heap_end = 0x40000000;
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@ -1,20 +0,0 @@
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x38000 /* Shared RAM, minus rom bss/data/stack.*/
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000
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}
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_heap_end = 0x3FFF8000;
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@ -1,20 +1,51 @@
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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/* ESP32 Linker Script Memory Layout
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This file describes the memory layout (memory blocks) as virtual
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memory addresses.
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esp32.common.ld contains output sections to link compiler output
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into these memory blocks.
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***
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This linker script is passed through the C preprocessor to include
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configuration options.
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Please use preprocessor features sparingly! Restrict
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to simple macros with numeric values, and/or #if/#endif blocks.
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*/
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#include "sdkconfig.h"
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x50000 /* Shared RAM, minus rom bss/data/stack.*/
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/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
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/* Even though the segment name is iram, it is actually mapped to flash */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000
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/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
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Enabling Bluetooth & Trace Memory features in menuconfig will decrease
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the amount of RAM available.
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*/
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dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
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len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM
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/* Flash mapped constant data */
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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/* RTC fast memory (executable). Persists over deep sleep.
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*/
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rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
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/* RTC slow memory (data accessible). Persists over deep sleep. */
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rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000
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}
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_heap_end = 0x40000000;
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/* Heap ends at top of dram0_0_seg */
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_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
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@ -1,14 +0,0 @@
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/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */
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/* The load addresses are defined later using the AT statements. */
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MEMORY
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{
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/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
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of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
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are connected to the data port of the CPU and eg allow bytewise access. */
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iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
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iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */
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dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x48000 /* Shared RAM, minus rom bss/data/stack.*/
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drom0_0_seg (R) : org = 0x3F400010, len = 0x800000
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}
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_heap_end = 0x3FFF8000;
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