From 2c6ab8579a2415eb31ee2be65fc887ca0c1b75aa Mon Sep 17 00:00:00 2001 From: Angus Gratton Date: Wed, 21 Sep 2016 11:04:16 +1000 Subject: [PATCH] esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many! --- components/bt/Kconfig | 6 ++++ components/esp32/component.mk | 27 ++++++++--------- components/esp32/ld/esp32.bt.ld | 20 ------------- components/esp32/ld/esp32.bt.trace.ld | 20 ------------- components/esp32/ld/esp32.ld | 43 +++++++++++++++++++++++---- components/esp32/ld/esp32.trace.ld | 14 --------- 6 files changed, 55 insertions(+), 75 deletions(-) delete mode 100644 components/esp32/ld/esp32.bt.ld delete mode 100644 components/esp32/ld/esp32.bt.trace.ld delete mode 100644 components/esp32/ld/esp32.trace.ld diff --git a/components/bt/Kconfig b/components/bt/Kconfig index ab163efc6..e397214d2 100644 --- a/components/bt/Kconfig +++ b/components/bt/Kconfig @@ -21,3 +21,9 @@ config BT_ENABLED # This enables classic BT support endmenu + +# Memory reserved at start of DRAM for Bluetooth stack +config BT_RESERVE_DRAM + hex + default 0x10000 if MEMMAP_BT + default 0 diff --git a/components/esp32/component.mk b/components/esp32/component.mk index d275898db..223c955d5 100644 --- a/components/esp32/component.mk +++ b/components/esp32/component.mk @@ -12,21 +12,7 @@ COMPONENT_SRCDIRS := . hwcrypto LIBS := crypto core net80211 phy rtc pp wpa wps -ifeq ($(CONFIG_MEMMAP_BT),y) - ifeq ($(CONFIG_MEMMAP_TRACEMEM),y) - LINKER_SCRIPTS = -T esp32.bt.trace.ld - else - LINKER_SCRIPTS = -T esp32.bt.ld - endif -else - ifeq ($(CONFIG_MEMMAP_TRACEMEM),y) - LINKER_SCRIPTS = -T esp32.trace.ld - else - LINKER_SCRIPTS = -T esp32.ld - endif -endif - -LINKER_SCRIPTS += -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld +LINKER_SCRIPTS += -T esp32_out.ld -T esp32.common.ld -T esp32.rom.ld -T esp32.peripherals.ld COMPONENT_ADD_LDFLAGS := -lesp32 \ $(abspath libhal.a) \ @@ -51,3 +37,14 @@ $(eval $(call SubmoduleRequiredForFiles,$(ALL_LIB_FILES))) # It would be better for components to be able to expose any of these # non-standard dependencies via get_variable, but this will do for now. $(COMPONENT_LIBRARY): $(ALL_LIB_FILES) + +# Preprocess esp32.ld linker script into esp32_out.ld +# +# The library doesn't really depend on esp32_out.ld, but it +# saves us from having to add the target to a Makefile.projbuild +$(COMPONENT_LIBRARY): esp32_out.ld + +esp32_out.ld: $(COMPONENT_PATH)/ld/esp32.ld ../include/sdkconfig.h + $(CC) -I ../include -C -P -x c -E $< -o $@ + +COMPONENT_EXTRA_CLEAN := esp32_out.ld diff --git a/components/esp32/ld/esp32.bt.ld b/components/esp32/ld/esp32.bt.ld deleted file mode 100644 index ccf0821ae..000000000 --- a/components/esp32/ld/esp32.bt.ld +++ /dev/null @@ -1,20 +0,0 @@ -/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ -/* The load addresses are defined later using the AT statements. */ -MEMORY -{ - /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length - of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but - are connected to the data port of the CPU and eg allow bytewise access. */ - iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ - iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ - dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x40000 /* Shared RAM, minus rom bss/data/stack.*/ - drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 - - /* RTC fast memory (executable). Persists over deep sleep. - */ - rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 - /* RTC slow memory (data accessible). Persists over deep sleep. */ - rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000 -} - -_heap_end = 0x40000000; diff --git a/components/esp32/ld/esp32.bt.trace.ld b/components/esp32/ld/esp32.bt.trace.ld deleted file mode 100644 index 78cedeb29..000000000 --- a/components/esp32/ld/esp32.bt.trace.ld +++ /dev/null @@ -1,20 +0,0 @@ -/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ -/* The load addresses are defined later using the AT statements. */ -MEMORY -{ - /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length - of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but - are connected to the data port of the CPU and eg allow bytewise access. */ - iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ - iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ - dram0_0_seg (RW) : org = 0x3FFC0000, len = 0x38000 /* Shared RAM, minus rom bss/data/stack.*/ - drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 - - /* RTC fast memory (executable). Persists over deep sleep. - */ - rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 - /* RTC slow memory (data accessible). Persists over deep sleep. */ - rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000 -} - -_heap_end = 0x3FFF8000; diff --git a/components/esp32/ld/esp32.ld b/components/esp32/ld/esp32.ld index 6c67c7d79..c44b2e42a 100644 --- a/components/esp32/ld/esp32.ld +++ b/components/esp32/ld/esp32.ld @@ -1,20 +1,51 @@ -/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ -/* The load addresses are defined later using the AT statements. */ +/* ESP32 Linker Script Memory Layout + + This file describes the memory layout (memory blocks) as virtual + memory addresses. + + esp32.common.ld contains output sections to link compiler output + into these memory blocks. + + *** + + This linker script is passed through the C preprocessor to include + configuration options. + + Please use preprocessor features sparingly! Restrict + to simple macros with numeric values, and/or #if/#endif blocks. +*/ +#include "sdkconfig.h" + MEMORY { /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but are connected to the data port of the CPU and eg allow bytewise access. */ - iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ - iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ - dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x50000 /* Shared RAM, minus rom bss/data/stack.*/ + + /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ + iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 + + /* Even though the segment name is iram, it is actually mapped to flash */ + iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 + + /* Shared data RAM, excluding memory reserved for ROM bss/data/stack. + + Enabling Bluetooth & Trace Memory features in menuconfig will decrease + the amount of RAM available. + */ + dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM, + len = 0x50000 - CONFIG_TRACEMEM_RESERVE_DRAM - CONFIG_BT_RESERVE_DRAM + + /* Flash mapped constant data */ drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 /* RTC fast memory (executable). Persists over deep sleep. */ rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000 + /* RTC slow memory (data accessible). Persists over deep sleep. */ rtc_slow_seg(RW) : org = 0x50000000, len = 0x2000 } -_heap_end = 0x40000000; +/* Heap ends at top of dram0_0_seg */ +_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM; diff --git a/components/esp32/ld/esp32.trace.ld b/components/esp32/ld/esp32.trace.ld deleted file mode 100644 index f619f8d98..000000000 --- a/components/esp32/ld/esp32.trace.ld +++ /dev/null @@ -1,14 +0,0 @@ -/* THESE ARE THE VIRTUAL RUNTIME ADDRESSES */ -/* The load addresses are defined later using the AT statements. */ -MEMORY -{ - /* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length - of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but - are connected to the data port of the CPU and eg allow bytewise access. */ - iram0_0_seg (RX) : org = 0x40080000, len = 0x20000 /* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */ - iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000 /* Even though the segment name is iram, it is actually mapped to flash */ - dram0_0_seg (RW) : org = 0x3FFB0000, len = 0x48000 /* Shared RAM, minus rom bss/data/stack.*/ - drom0_0_seg (R) : org = 0x3F400010, len = 0x800000 -} - -_heap_end = 0x3FFF8000;