Merge branch 'bugfix/soc_register_struct_names' into 'master'

soc:Added names to anonymous register structs

See merge request idf/esp-idf!4668

components/soc/esp32/include/soc/apb_ctrl_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef struct {
+typedef struct apb_ctrl_dev_s {
     union {
         struct {
             volatile uint32_t pre_div:       10;

components/soc/esp32/include/soc/can_struct.h

@@ -139,7 +139,7 @@ typedef union {
     uint32_t val;
 } can_err_code_cap_reg_t;
 
-typedef struct {
+typedef struct can_acc_filter_s {
     can_reg_t code_reg[4];
     can_reg_t mask_reg[4];
     uint32_t reserved32[5];
@@ -166,7 +166,7 @@ typedef union {
 
 /* ---------------------------- Register Layout ------------------------------ */
 
-typedef volatile struct {
+typedef volatile struct can_dev_s {
     //Configuration and Control Registers
     can_mode_reg_t mode_reg;                                /* Address 0 */
     can_cmd_reg_t command_reg;                              /* Address 1 */

components/soc/esp32/include/soc/gpio_sd_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_sd_dev_s {
     union {
         struct {
             uint32_t duty:        8;

components/soc/esp32/include/soc/gpio_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct gpio_dev_s {
     uint32_t bt_select;                             /*NA*/
     uint32_t out;                                   /*GPIO0~31 output value*/
     uint32_t out_w1ts;                              /*GPIO0~31 output value write 1 to set*/

components/soc/esp32/include/soc/hinf_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct hinf_dev_s {
     union {
         struct {
             uint32_t user_id_fn1:  16;

components/soc/esp32/include/soc/host_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct host_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     uint32_t reserved_8;

components/soc/esp32/include/soc/i2c_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct i2c_dev_s {
     union {
         struct {
             uint32_t period:14;             /*This register is used to configure the  low level width of SCL clock.*/

components/soc/esp32/include/soc/i2s_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct i2s_dev_s {
     uint32_t reserved_0;
     uint32_t reserved_4;
     union {

components/soc/esp32/include/soc/ledc_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct ledc_dev_s {
     struct {
         struct {
             union {

components/soc/esp32/include/soc/mcpwm_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct mcpwm_dev_s {
     union {
         struct {
             uint32_t prescale: 8;                  /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/

components/soc/esp32/include/soc/pcnt_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct pcnt_dev_s {
     struct{
         union {
             struct {

components/soc/esp32/include/soc/rmt_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rmt_dev_s {
     uint32_t data_ch[8];                                /*The R/W ram address for channel0-7 by apb fifo access.
                                                         Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
                                                         and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
@@ -235,7 +235,7 @@ typedef volatile struct {
 } rmt_dev_t;
 extern rmt_dev_t RMT;
 
-typedef struct {
+typedef struct rmt_item32_s {
     union {
         struct {
             uint32_t duration0 :15;
@@ -248,7 +248,7 @@ typedef struct {
 } rmt_item32_t;
 
 //Allow access to RMT memory using RMTMEM.chan[0].data32[8]
-typedef volatile struct {
+typedef volatile struct rmt_mem_s {
     struct {
         union {
             rmt_item32_t data32[64];

components/soc/esp32/include/soc/rtc.h

@@ -88,7 +88,7 @@ typedef enum {
 /**
  * @brief CPU clock configuration structure
  */
-typedef struct {
+typedef struct rtc_cpu_freq_config_s {
     rtc_cpu_freq_src_t source;      //!< The clock from which CPU clock is derived
     uint32_t source_freq_mhz;       //!< Source clock frequency
     uint32_t div;                   //!< Divider, freq_mhz = source_freq_mhz / div
@@ -127,7 +127,7 @@ typedef enum {
 /**
  * Initialization parameters for rtc_clk_init
  */
-typedef struct {
+typedef struct rtc_clk_config_s {
     rtc_xtal_freq_t xtal_freq : 8;      //!< Main XTAL frequency
     rtc_cpu_freq_t cpu_freq_mhz : 10;   //!< CPU frequency to set, in MHz
     rtc_fast_freq_t fast_freq : 1;      //!< RTC_FAST_CLK frequency to set
@@ -535,7 +535,7 @@ void rtc_clk_wait_for_slow_cycle();
 /**
  * @brief sleep configuration for rtc_sleep_init function
  */
-typedef struct {
+typedef struct rtc_sleep_config_s {
     uint32_t lslp_mem_inf_fpu : 1;      //!< force normal voltage in sleep mode (digital domain memory)
     uint32_t rtc_mem_inf_fpu : 1;       //!< force normal voltage in sleep mode (RTC memory)
     uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
@@ -657,7 +657,7 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
 /**
  * RTC power and clock control initialization settings
  */
-typedef struct {
+typedef struct rtc_config_s {
     uint32_t ck8m_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
     uint32_t xtal_wait : 8;         //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
     uint32_t pll_wait : 8;          //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
@@ -693,7 +693,7 @@ void rtc_init(rtc_config_t cfg);
 /**
  * Structure describing vddsdio configuration
  */
-typedef struct {
+typedef struct rtc_vddsdio_config_s {
     uint32_t force : 1;     //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
     uint32_t enable : 1;    //!< Enable VDDSDIO regulator
     uint32_t tieh  : 1;     //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V

components/soc/esp32/include/soc/rtc_cntl_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_cntl_dev_s {
     union {
         struct {
             uint32_t sw_stall_appcpu_c0:  2;             /*{reg_sw_stall_appcpu_c1[5:0]   reg_sw_stall_appcpu_c0[1:0]}  == 0x86 will stall APP CPU*/

components/soc/esp32/include/soc/rtc_io_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct rtc_io_dev_s {
     union {
         struct {
             uint32_t reserved0:        14;

components/soc/esp32/include/soc/sdmmc_struct.h

@@ -22,7 +22,7 @@
 extern "C" {
 #endif
 
-typedef struct {
+typedef struct sdmmc_desc_s {
     uint32_t reserved1: 1;
     uint32_t disable_int_on_completion: 1;
     uint32_t last_descriptor: 1;
@@ -47,7 +47,7 @@ typedef struct {
 _Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
 
 
-typedef struct {
+typedef struct sdmmc_hw_cmd_s {
     uint32_t cmd_index: 6;          ///< Command index
     uint32_t response_expect: 1;    ///< set if response is expected
     uint32_t response_long: 1;      ///< 0: short response expected, 1: long response expected
@@ -76,7 +76,7 @@ typedef struct {
 _Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
 
 
-typedef volatile struct {
+typedef volatile struct sdmmc_dev_s {
     union {
         struct {
             uint32_t controller_reset: 1;

components/soc/esp32/include/soc/sens_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct sens_dev_s {
     union {
         struct {
             uint32_t sar1_clk_div:      8;

components/soc/esp32/include/soc/slc_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct slc_dev_s {
     union {
         struct {
             uint32_t slc0_tx_rst:         1;

components/soc/esp32/include/soc/spi_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct spi_dev_s {
     union {
         struct {
             uint32_t reserved0: 16;                         /*reserved*/

components/soc/esp32/include/soc/syscon_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct syscon_dev_s {
     union {
         struct {
             uint32_t pre_div:       10;

components/soc/esp32/include/soc/timer_group_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct timg_dev_s {
     struct{
         union {
             struct {

components/soc/esp32/include/soc/uart_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uart_dev_s {
     union {
         struct {
             uint8_t rw_byte;                 /*This register stores one byte data  read by rx fifo.*/

components/soc/esp32/include/soc/uhci_struct.h

@@ -20,7 +20,7 @@
 extern "C" {
 #endif
 
-typedef volatile struct {
+typedef volatile struct uhci_dev_s {
     union {
         struct {
             uint32_t in_rst:             1;                /*Set this bit to reset in link operations.*/