soc:Added names to anonymous register structs
For typedef volatile struct in components/soc/esp32/include/soc Merges https://github.com/espressif/esp-idf/pull/3199
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef struct {
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typedef struct apb_ctrl_dev_s {
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union {
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struct {
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volatile uint32_t pre_div: 10;
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@ -139,7 +139,7 @@ typedef union {
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uint32_t val;
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} can_err_code_cap_reg_t;
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typedef struct {
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typedef struct can_acc_filter_s {
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can_reg_t code_reg[4];
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can_reg_t mask_reg[4];
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uint32_t reserved32[5];
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@ -166,7 +166,7 @@ typedef union {
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/* ---------------------------- Register Layout ------------------------------ */
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typedef volatile struct {
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typedef volatile struct can_dev_s {
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//Configuration and Control Registers
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can_mode_reg_t mode_reg; /* Address 0 */
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can_cmd_reg_t command_reg; /* Address 1 */
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct gpio_sd_dev_s {
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union {
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struct {
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uint32_t duty: 8;
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct gpio_dev_s {
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uint32_t bt_select; /*NA*/
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uint32_t out; /*GPIO0~31 output value*/
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uint32_t out_w1ts; /*GPIO0~31 output value write 1 to set*/
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct hinf_dev_s {
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union {
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struct {
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uint32_t user_id_fn1: 16;
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct host_dev_s {
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uint32_t reserved_0;
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uint32_t reserved_4;
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uint32_t reserved_8;
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct i2c_dev_s {
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union {
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struct {
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uint32_t period:14; /*This register is used to configure the low level width of SCL clock.*/
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct i2s_dev_s {
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uint32_t reserved_0;
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uint32_t reserved_4;
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union {
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct ledc_dev_s {
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struct {
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struct {
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union {
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct mcpwm_dev_s {
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union {
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struct {
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uint32_t prescale: 8; /*Period of PWM_clk = 6.25ns * (PWM_CLK_PRESCALE + 1)*/
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct pcnt_dev_s {
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struct{
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union {
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struct {
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct rmt_dev_s {
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uint32_t data_ch[8]; /*The R/W ram address for channel0-7 by apb fifo access.
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Note that in some circumstances, data read from the FIFO may get lost. As RMT memory area accesses using the RMTMEM method do not have this issue
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and provide all the functionality that the FIFO register has, it is encouraged to use that instead.*/
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@ -235,7 +235,7 @@ typedef volatile struct {
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} rmt_dev_t;
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extern rmt_dev_t RMT;
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typedef struct {
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typedef struct rmt_item32_s {
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union {
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struct {
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uint32_t duration0 :15;
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@ -248,7 +248,7 @@ typedef struct {
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} rmt_item32_t;
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//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
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typedef volatile struct {
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typedef volatile struct rmt_mem_s {
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struct {
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union {
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rmt_item32_t data32[64];
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@ -88,7 +88,7 @@ typedef enum {
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/**
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* @brief CPU clock configuration structure
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*/
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typedef struct {
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typedef struct rtc_cpu_freq_config_s {
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rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived
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uint32_t source_freq_mhz; //!< Source clock frequency
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uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
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@ -127,7 +127,7 @@ typedef enum {
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/**
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* Initialization parameters for rtc_clk_init
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*/
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typedef struct {
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typedef struct rtc_clk_config_s {
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rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
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rtc_cpu_freq_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
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rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
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@ -535,7 +535,7 @@ void rtc_clk_wait_for_slow_cycle();
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/**
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* @brief sleep configuration for rtc_sleep_init function
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*/
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typedef struct {
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typedef struct rtc_sleep_config_s {
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uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
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uint32_t rtc_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (RTC memory)
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uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
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@ -657,7 +657,7 @@ uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt);
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/**
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* RTC power and clock control initialization settings
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*/
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typedef struct {
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typedef struct rtc_config_s {
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uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
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uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
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uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
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@ -693,7 +693,7 @@ void rtc_init(rtc_config_t cfg);
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/**
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* Structure describing vddsdio configuration
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*/
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typedef struct {
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typedef struct rtc_vddsdio_config_s {
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uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
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uint32_t enable : 1; //!< Enable VDDSDIO regulator
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uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct rtc_cntl_dev_s {
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union {
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struct {
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uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct rtc_io_dev_s {
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union {
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struct {
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uint32_t reserved0: 14;
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@ -22,7 +22,7 @@
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extern "C" {
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#endif
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typedef struct {
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typedef struct sdmmc_desc_s {
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uint32_t reserved1: 1;
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uint32_t disable_int_on_completion: 1;
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uint32_t last_descriptor: 1;
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@ -47,7 +47,7 @@ typedef struct {
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_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
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typedef struct {
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typedef struct sdmmc_hw_cmd_s {
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uint32_t cmd_index: 6; ///< Command index
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uint32_t response_expect: 1; ///< set if response is expected
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uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
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@ -76,7 +76,7 @@ typedef struct {
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_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
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typedef volatile struct {
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typedef volatile struct sdmmc_dev_s {
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union {
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struct {
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uint32_t controller_reset: 1;
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct sens_dev_s {
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union {
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struct {
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uint32_t sar1_clk_div: 8;
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct slc_dev_s {
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union {
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struct {
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uint32_t slc0_tx_rst: 1;
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct spi_dev_s {
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union {
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struct {
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uint32_t reserved0: 16; /*reserved*/
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct syscon_dev_s {
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union {
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struct {
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uint32_t pre_div: 10;
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@ -20,7 +20,7 @@
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct timg_dev_s {
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struct{
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union {
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struct {
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct uart_dev_s {
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union {
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struct {
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uint8_t rw_byte; /*This register stores one byte data read by rx fifo.*/
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extern "C" {
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#endif
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typedef volatile struct {
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typedef volatile struct uhci_dev_s {
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union {
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struct {
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uint32_t in_rst: 1; /*Set this bit to reset in link operations.*/
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