Merge branch 'feature/add_esp32s3_soc_description_files' into 'master'
soc: add soc descriptions for esp32s3 See merge request espressif/esp-idf!9238
This commit is contained in:
Ivan Grokhotkov
commit
16a9252d4b
17
components/soc/soc/esp32s3/CMakeLists.txt
Normal file
17
components/soc/soc/esp32s3/CMakeLists.txt
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
add_library(soc_esp32s3 STATIC
|
||||
"adc_periph.c"
|
||||
"dac_periph.c"
|
||||
"gpio_periph.c"
|
||||
"i2c_periph.c"
|
||||
"i2s_periph.c"
|
||||
"interrupts.c"
|
||||
"ledc_periph.c"
|
||||
"rtc_io_periph.c"
|
||||
"rtc_periph.c"
|
||||
"sdio_slave_periph.c"
|
||||
"sdmmc_periph.c"
|
||||
"spi_periph.c"
|
||||
"touch_sensor_periph.c"
|
||||
"uart_periph.c")
|
||||
|
||||
target_include_directories(soc_esp32s3 PUBLIC . include ../include)
|
||||
29
components/soc/soc/esp32s3/adc_periph.c
Normal file
29
components/soc/soc/esp32s3/adc_periph.c
Normal file
|
|
@ -0,0 +1,29 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/adc_periph.h"
|
||||
|
||||
/* Store IO number corresponding to the ADC channel number. */
|
||||
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
|
||||
/* ADC1 */
|
||||
{
|
||||
ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM,
|
||||
ADC1_CHANNEL_5_GPIO_NUM, ADC1_CHANNEL_6_GPIO_NUM, ADC1_CHANNEL_7_GPIO_NUM, -1, -1
|
||||
},
|
||||
/* ADC2 */
|
||||
{
|
||||
ADC2_CHANNEL_0_GPIO_NUM, ADC2_CHANNEL_1_GPIO_NUM, ADC2_CHANNEL_2_GPIO_NUM, ADC2_CHANNEL_3_GPIO_NUM, ADC2_CHANNEL_4_GPIO_NUM,
|
||||
ADC2_CHANNEL_5_GPIO_NUM, ADC2_CHANNEL_6_GPIO_NUM, ADC2_CHANNEL_7_GPIO_NUM, ADC2_CHANNEL_8_GPIO_NUM, ADC2_CHANNEL_9_GPIO_NUM
|
||||
}
|
||||
};
|
||||
23
components/soc/soc/esp32s3/dac_periph.c
Normal file
23
components/soc/soc/esp32s3/dac_periph.c
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
// Copyright 2019 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/dac_periph.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for DAC peripheral: GPIO number
|
||||
*/
|
||||
const dac_signal_conn_t dac_periph_signal = {
|
||||
.dac_channel_io_num[0] = DAC_CHANNEL_1_GPIO_NUM,
|
||||
.dac_channel_io_num[1] = DAC_CHANNEL_2_GPIO_NUM,
|
||||
};
|
||||
117
components/soc/soc/esp32s3/gpio_periph.c
Normal file
117
components/soc/soc/esp32s3/gpio_periph.c
Normal file
|
|
@ -0,0 +1,117 @@
|
|||
// Copyright 2018 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/gpio_periph.h"
|
||||
|
||||
const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = {
|
||||
IO_MUX_GPIO0_REG,
|
||||
IO_MUX_GPIO1_REG,
|
||||
IO_MUX_GPIO2_REG,
|
||||
IO_MUX_GPIO3_REG,
|
||||
IO_MUX_GPIO4_REG,
|
||||
IO_MUX_GPIO5_REG,
|
||||
IO_MUX_GPIO6_REG,
|
||||
IO_MUX_GPIO7_REG,
|
||||
IO_MUX_GPIO8_REG,
|
||||
IO_MUX_GPIO9_REG,
|
||||
IO_MUX_GPIO10_REG,
|
||||
IO_MUX_GPIO11_REG,
|
||||
IO_MUX_GPIO12_REG,
|
||||
IO_MUX_GPIO13_REG,
|
||||
IO_MUX_GPIO14_REG,
|
||||
IO_MUX_GPIO15_REG,
|
||||
IO_MUX_GPIO16_REG,
|
||||
IO_MUX_GPIO17_REG,
|
||||
IO_MUX_GPIO18_REG,
|
||||
IO_MUX_GPIO19_REG,
|
||||
IO_MUX_GPIO20_REG,
|
||||
IO_MUX_GPIO21_REG,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
IO_MUX_GPIO26_REG,
|
||||
IO_MUX_GPIO27_REG,
|
||||
IO_MUX_GPIO28_REG,
|
||||
IO_MUX_GPIO29_REG,
|
||||
IO_MUX_GPIO30_REG,
|
||||
IO_MUX_GPIO31_REG,
|
||||
IO_MUX_GPIO32_REG,
|
||||
IO_MUX_GPIO33_REG,
|
||||
IO_MUX_GPIO34_REG,
|
||||
IO_MUX_GPIO35_REG,
|
||||
IO_MUX_GPIO36_REG,
|
||||
IO_MUX_GPIO37_REG,
|
||||
IO_MUX_GPIO38_REG,
|
||||
IO_MUX_GPIO39_REG,
|
||||
IO_MUX_GPIO40_REG,
|
||||
IO_MUX_GPIO41_REG,
|
||||
IO_MUX_GPIO42_REG,
|
||||
IO_MUX_GPIO43_REG,
|
||||
IO_MUX_GPIO44_REG,
|
||||
IO_MUX_GPIO45_REG,
|
||||
IO_MUX_GPIO46_REG,
|
||||
0,
|
||||
};
|
||||
|
||||
const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = {
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
0,
|
||||
BIT(1),
|
||||
BIT(2),
|
||||
BIT(3),
|
||||
BIT(4),
|
||||
BIT(5),
|
||||
BIT(6),
|
||||
BIT(7),
|
||||
BIT(8),
|
||||
BIT(9),
|
||||
BIT(10),
|
||||
BIT(11),
|
||||
BIT(12),
|
||||
BIT(13),
|
||||
BIT(14),
|
||||
BIT(15),
|
||||
BIT(16),
|
||||
BIT(17),
|
||||
BIT(18),
|
||||
BIT(19),
|
||||
BIT(20),
|
||||
BIT(21),
|
||||
BIT(22),
|
||||
BIT(23),
|
||||
BIT(24),
|
||||
BIT(25),
|
||||
BIT(26),
|
||||
};
|
||||
184
components/soc/soc/esp32s3/i2c_bbpll.h
Normal file
184
components/soc/soc/esp32s3/i2c_bbpll.h
Normal file
|
|
@ -0,0 +1,184 @@
|
|||
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file i2c_apll.h
|
||||
* @brief Register definitions for digital PLL (BBPLL)
|
||||
*
|
||||
* This file lists register fields of BBPLL, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
|
||||
* rtc_clk_cpu_freq_set function in rtc_clk.c.
|
||||
*/
|
||||
|
||||
#define I2C_BBPLL 0x66
|
||||
#define I2C_BBPLL_HOSTID 1
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_DELAY 0
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_DELAY_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV 0
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3
|
||||
#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP 1
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4
|
||||
#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_RSTB 1
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_MSB 5
|
||||
#define I2C_BBPLL_IR_CAL_RSTB_LSB 5
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_START 1
|
||||
#define I2C_BBPLL_IR_CAL_START_MSB 6
|
||||
#define I2C_BBPLL_IR_CAL_START_LSB 6
|
||||
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP 1
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7
|
||||
#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_REF_DIV 2
|
||||
#define I2C_BBPLL_OC_REF_DIV_MSB 3
|
||||
#define I2C_BBPLL_OC_REF_DIV_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DCHGP 2
|
||||
#define I2C_BBPLL_OC_DCHGP_MSB 6
|
||||
#define I2C_BBPLL_OC_DCHGP_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_FCAL 2
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_MSB 7
|
||||
#define I2C_BBPLL_OC_ENB_FCAL_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DIV_7_0 3
|
||||
#define I2C_BBPLL_OC_DIV_7_0_MSB 7
|
||||
#define I2C_BBPLL_OC_DIV_7_0_LSB 0
|
||||
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC 4
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0
|
||||
#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0
|
||||
|
||||
#define I2C_BBPLL_MODE_HF 4
|
||||
#define I2C_BBPLL_MODE_HF_MSB 1
|
||||
#define I2C_BBPLL_MODE_HF_LSB 1
|
||||
|
||||
#define I2C_BBPLL_DIV_ADC 4
|
||||
#define I2C_BBPLL_DIV_ADC_MSB 3
|
||||
#define I2C_BBPLL_DIV_ADC_LSB 2
|
||||
|
||||
#define I2C_BBPLL_DIV_DAC 4
|
||||
#define I2C_BBPLL_DIV_DAC_MSB 4
|
||||
#define I2C_BBPLL_DIV_DAC_LSB 4
|
||||
|
||||
#define I2C_BBPLL_DIV_CPU 4
|
||||
#define I2C_BBPLL_DIV_CPU_MSB 5
|
||||
#define I2C_BBPLL_DIV_CPU_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OC_ENB_VCON 4
|
||||
#define I2C_BBPLL_OC_ENB_VCON_MSB 6
|
||||
#define I2C_BBPLL_OC_ENB_VCON_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OC_TSCHGP 4
|
||||
#define I2C_BBPLL_OC_TSCHGP_MSB 7
|
||||
#define I2C_BBPLL_OC_TSCHGP_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DR1 5
|
||||
#define I2C_BBPLL_OC_DR1_MSB 2
|
||||
#define I2C_BBPLL_OC_DR1_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OC_DR3 5
|
||||
#define I2C_BBPLL_OC_DR3_MSB 6
|
||||
#define I2C_BBPLL_OC_DR3_LSB 4
|
||||
|
||||
#define I2C_BBPLL_EN_USB 5
|
||||
#define I2C_BBPLL_EN_USB_MSB 7
|
||||
#define I2C_BBPLL_EN_USB_LSB 7
|
||||
|
||||
#define I2C_BBPLL_OC_DCUR 6
|
||||
#define I2C_BBPLL_OC_DCUR_MSB 2
|
||||
#define I2C_BBPLL_OC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_INC_CUR 6
|
||||
#define I2C_BBPLL_INC_CUR_MSB 3
|
||||
#define I2C_BBPLL_INC_CUR_LSB 3
|
||||
|
||||
#define I2C_BBPLL_OC_DHREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_MSB 5
|
||||
#define I2C_BBPLL_OC_DHREF_SEL_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OC_DLREF_SEL 6
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_MSB 7
|
||||
#define I2C_BBPLL_OC_DLREF_SEL_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_CAP 8
|
||||
#define I2C_BBPLL_OR_CAL_CAP_MSB 3
|
||||
#define I2C_BBPLL_OR_CAL_CAP_LSB 0
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_UDF 8
|
||||
#define I2C_BBPLL_OR_CAL_UDF_MSB 4
|
||||
#define I2C_BBPLL_OR_CAL_UDF_LSB 4
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_OVF 8
|
||||
#define I2C_BBPLL_OR_CAL_OVF_MSB 5
|
||||
#define I2C_BBPLL_OR_CAL_OVF_LSB 5
|
||||
|
||||
#define I2C_BBPLL_OR_CAL_END 8
|
||||
#define I2C_BBPLL_OR_CAL_END_MSB 6
|
||||
#define I2C_BBPLL_OR_CAL_END_LSB 6
|
||||
|
||||
#define I2C_BBPLL_OR_LOCK 8
|
||||
#define I2C_BBPLL_OR_LOCK_MSB 7
|
||||
#define I2C_BBPLL_OR_LOCK_LSB 7
|
||||
|
||||
#define I2C_BBPLL_BBADC_DELAY1 9
|
||||
#define I2C_BBPLL_BBADC_DELAY1_MSB 1
|
||||
#define I2C_BBPLL_BBADC_DELAY1_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_DELAY2 9
|
||||
#define I2C_BBPLL_BBADC_DELAY2_MSB 3
|
||||
#define I2C_BBPLL_BBADC_DELAY2_LSB 2
|
||||
|
||||
#define I2C_BBPLL_BBADC_DVDD 9
|
||||
#define I2C_BBPLL_BBADC_DVDD_MSB 5
|
||||
#define I2C_BBPLL_BBADC_DVDD_LSB 4
|
||||
|
||||
#define I2C_BBPLL_BBADC_DREF 9
|
||||
#define I2C_BBPLL_BBADC_DREF_MSB 7
|
||||
#define I2C_BBPLL_BBADC_DREF_LSB 6
|
||||
|
||||
#define I2C_BBPLL_BBADC_DCUR 10
|
||||
#define I2C_BBPLL_BBADC_DCUR_MSB 1
|
||||
#define I2C_BBPLL_BBADC_DCUR_LSB 0
|
||||
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT 10
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2
|
||||
#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2
|
||||
|
||||
#define I2C_BBPLL_ENT_PLL 10
|
||||
#define I2C_BBPLL_ENT_PLL_MSB 3
|
||||
#define I2C_BBPLL_ENT_PLL_LSB 3
|
||||
|
||||
#define I2C_BBPLL_DTEST 10
|
||||
#define I2C_BBPLL_DTEST_MSB 5
|
||||
#define I2C_BBPLL_DTEST_LSB 4
|
||||
|
||||
#define I2C_BBPLL_ENT_ADC 10
|
||||
#define I2C_BBPLL_ENT_ADC_MSB 7
|
||||
#define I2C_BBPLL_ENT_ADC_LSB 6
|
||||
|
||||
38
components/soc/soc/esp32s3/i2c_periph.c
Normal file
38
components/soc/soc/esp32s3/i2c_periph.c
Normal file
|
|
@ -0,0 +1,38 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/i2c_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc
|
||||
*/
|
||||
const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = {
|
||||
{
|
||||
.sda_out_sig = I2CEXT0_SDA_OUT_IDX,
|
||||
.sda_in_sig = I2CEXT0_SDA_IN_IDX,
|
||||
.scl_out_sig = I2CEXT0_SCL_OUT_IDX,
|
||||
.scl_in_sig = I2CEXT0_SCL_IN_IDX,
|
||||
.irq = ETS_I2C_EXT0_INTR_SOURCE,
|
||||
.module = PERIPH_I2C0_MODULE,
|
||||
},
|
||||
{
|
||||
.sda_out_sig = I2CEXT1_SDA_OUT_IDX,
|
||||
.sda_in_sig = I2CEXT1_SDA_IN_IDX,
|
||||
.scl_out_sig = I2CEXT1_SCL_OUT_IDX,
|
||||
.scl_in_sig = I2CEXT1_SCL_IN_IDX,
|
||||
.irq = ETS_I2C_EXT1_INTR_SOURCE,
|
||||
.module = PERIPH_I2C1_MODULE,
|
||||
},
|
||||
};
|
||||
39
components/soc/soc/esp32s3/i2c_ulp.h
Normal file
39
components/soc/soc/esp32s3/i2c_ulp.h
Normal file
|
|
@ -0,0 +1,39 @@
|
|||
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
/**
|
||||
* @file i2c_ulp.h
|
||||
* @brief Register definitions for analog to calibrate o_code for getting a more precise voltage.
|
||||
*
|
||||
* This file lists register fields of ULP, located on an internal configuration
|
||||
* bus. These definitions are used via macros defined in i2c_rtc_clk.h, by
|
||||
* rtc_init function in rtc_init.c.
|
||||
*/
|
||||
|
||||
#define I2C_ULP 0x61
|
||||
#define I2C_ULP_HOSTID 1
|
||||
|
||||
#define I2C_ULP_IR_RESETB 0
|
||||
#define I2C_ULP_IR_RESETB_MSB 0
|
||||
#define I2C_ULP_IR_RESETB_LSB 0
|
||||
|
||||
#define I2C_ULP_O_DONE_FLAG 3
|
||||
#define I2C_ULP_O_DONE_FLAG_MSB 0
|
||||
#define I2C_ULP_O_DONE_FLAG_LSB 0
|
||||
|
||||
#define I2C_ULP_BG_O_DONE_FLAG 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_MSB 3
|
||||
#define I2C_ULP_BG_O_DONE_FLAG_LSB 3
|
||||
36
components/soc/soc/esp32s3/i2s_periph.c
Normal file
36
components/soc/soc/esp32s3/i2s_periph.c
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#include "soc/i2s_periph.h"
|
||||
#include "soc/gpio_sig_map.h"
|
||||
|
||||
/*
|
||||
Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc
|
||||
*/
|
||||
const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = {
|
||||
{
|
||||
.o_bck_in_sig = I2S0O_BCK_IN_IDX,
|
||||
.o_ws_in_sig = I2S0O_WS_IN_IDX,
|
||||
.o_bck_out_sig = I2S0O_BCK_OUT_IDX,
|
||||
.o_ws_out_sig = I2S0O_WS_OUT_IDX,
|
||||
.o_data_out_sig = I2S0O_SD_OUT_IDX,
|
||||
.i_bck_in_sig = I2S0I_BCK_OUT_IDX,
|
||||
.i_ws_in_sig = I2S0I_WS_OUT_IDX,
|
||||
.i_bck_out_sig = I2S0I_BCK_IN_IDX,
|
||||
.i_ws_out_sig = I2S0I_WS_IN_IDX,
|
||||
.i_data_in_sig = I2S0I_SD_IN_IDX,
|
||||
.irq = ETS_I2S0_INTR_SOURCE,
|
||||
.module = PERIPH_I2S0_MODULE,
|
||||
}
|
||||
};
|
||||
44
components/soc/soc/esp32s3/include/soc/adc_caps.h
Normal file
44
components/soc/soc/esp32s3/include/soc/adc_caps.h
Normal file
|
|
@ -0,0 +1,44 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#define SOC_ADC_PERIPH_NUM (2)
|
||||
#define SOC_ADC_PATT_LEN_MAX (16)
|
||||
|
||||
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10)
|
||||
#define SOC_ADC_MAX_CHANNEL_NUM (10)
|
||||
|
||||
#define SOC_ADC1_DATA_INVERT_DEFAULT (0)
|
||||
#define SOC_ADC2_DATA_INVERT_DEFAULT (0)
|
||||
|
||||
#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0)
|
||||
|
||||
#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8)
|
||||
#define SOC_ADC_FSM_START_WAIT_DEFAULT (5)
|
||||
#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100)
|
||||
#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2)
|
||||
|
||||
/**
|
||||
* Check if adc support digital controller (DMA) mode.
|
||||
* @value
|
||||
* - 1 : support;
|
||||
* - 0 : not support;
|
||||
*/
|
||||
#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1)
|
||||
|
||||
#define SOC_ADC_PWDET_CCT_DEFAULT (4)
|
||||
|
||||
#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1)
|
||||
|
||||
#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1)
|
||||
78
components/soc/soc/esp32s3/include/soc/adc_channel.h
Normal file
78
components/soc/soc/esp32s3/include/soc/adc_channel.h
Normal file
|
|
@ -0,0 +1,78 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_ADC_CHANNEL_H
|
||||
#define _SOC_ADC_CHANNEL_H
|
||||
|
||||
#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0
|
||||
#define ADC1_CHANNEL_0_GPIO_NUM 1
|
||||
|
||||
#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1
|
||||
#define ADC1_CHANNEL_1_GPIO_NUM 2
|
||||
|
||||
#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2
|
||||
#define ADC1_CHANNEL_2_GPIO_NUM 3
|
||||
|
||||
#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3
|
||||
#define ADC1_CHANNEL_3_GPIO_NUM 4
|
||||
|
||||
#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4
|
||||
#define ADC1_CHANNEL_4_GPIO_NUM 5
|
||||
|
||||
#define ADC1_GPIO6_CHANNEL ADC1_CHANNEL_5
|
||||
#define ADC1_CHANNEL_5_GPIO_NUM 6
|
||||
|
||||
#define ADC1_GPIO7_CHANNEL ADC1_CHANNEL_6
|
||||
#define ADC1_CHANNEL_6_GPIO_NUM 7
|
||||
|
||||
#define ADC1_GPIO8_CHANNEL ADC1_CHANNEL_7
|
||||
#define ADC1_CHANNEL_7_GPIO_NUM 8
|
||||
|
||||
#define ADC1_GPIO9_CHANNEL ADC1_CHANNEL_8
|
||||
#define ADC1_CHANNEL_8_GPIO_NUM 9
|
||||
|
||||
#define ADC1_GPIO10_CHANNEL ADC1_CHANNEL_9
|
||||
#define ADC1_CHANNEL_9_GPIO_NUM 10
|
||||
|
||||
#define ADC2_GPIO11_CHANNEL ADC2_CHANNEL_0
|
||||
#define ADC2_CHANNEL_0_GPIO_NUM 11
|
||||
|
||||
#define ADC2_GPIO12_CHANNEL ADC2_CHANNEL_1
|
||||
#define ADC2_CHANNEL_1_GPIO_NUM 12
|
||||
|
||||
#define ADC2_GPIO13_CHANNEL ADC2_CHANNEL_2
|
||||
#define ADC2_CHANNEL_2_GPIO_NUM 13
|
||||
|
||||
#define ADC2_GPIO14_CHANNEL ADC2_CHANNEL_3
|
||||
#define ADC2_CHANNEL_3_GPIO_NUM 14
|
||||
|
||||
#define ADC2_GPIO15_CHANNEL ADC2_CHANNEL_4
|
||||
#define ADC2_CHANNEL_4_GPIO_NUM 15
|
||||
|
||||
#define ADC2_GPIO16_CHANNEL ADC2_CHANNEL_5
|
||||
#define ADC2_CHANNEL_5_GPIO_NUM 16
|
||||
|
||||
#define ADC2_GPIO17_CHANNEL ADC2_CHANNEL_6
|
||||
#define ADC2_CHANNEL_6_GPIO_NUM 17
|
||||
|
||||
#define ADC2_GPIO18_CHANNEL ADC2_CHANNEL_7
|
||||
#define ADC2_CHANNEL_7_GPIO_NUM 18
|
||||
|
||||
#define ADC2_GPIO19_CHANNEL ADC2_CHANNEL_8
|
||||
#define ADC2_CHANNEL_8_GPIO_NUM 19
|
||||
|
||||
#define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9
|
||||
#define ADC2_CHANNEL_9_GPIO_NUM 20
|
||||
|
||||
#endif
|
||||
546
components/soc/soc/esp32s3/include/soc/apb_ctrl_reg.h
Normal file
546
components/soc/soc/esp32s3/include/soc/apb_ctrl_reg.h
Normal file
|
|
@ -0,0 +1,546 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000)
|
||||
/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_RST_TICK_CNT (BIT(12))
|
||||
#define APB_CTRL_RST_TICK_CNT_M (BIT(12))
|
||||
#define APB_CTRL_RST_TICK_CNT_V 0x1
|
||||
#define APB_CTRL_RST_TICK_CNT_S 12
|
||||
/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_EN (BIT(11))
|
||||
#define APB_CTRL_CLK_EN_M (BIT(11))
|
||||
#define APB_CTRL_CLK_EN_V 0x1
|
||||
#define APB_CTRL_CLK_EN_S 11
|
||||
/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_320M_EN (BIT(10))
|
||||
#define APB_CTRL_CLK_320M_EN_M (BIT(10))
|
||||
#define APB_CTRL_CLK_320M_EN_V 0x1
|
||||
#define APB_CTRL_CLK_320M_EN_S 10
|
||||
/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PRE_DIV_CNT 0x000003FF
|
||||
#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << (APB_CTRL_PRE_DIV_CNT_S))
|
||||
#define APB_CTRL_PRE_DIV_CNT_V 0x3FF
|
||||
#define APB_CTRL_PRE_DIV_CNT_S 0
|
||||
|
||||
#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004)
|
||||
/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_TICK_ENABLE (BIT(16))
|
||||
#define APB_CTRL_TICK_ENABLE_M (BIT(16))
|
||||
#define APB_CTRL_TICK_ENABLE_V 0x1
|
||||
#define APB_CTRL_TICK_ENABLE_S 16
|
||||
/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CK8M_TICK_NUM 0x000000FF
|
||||
#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V) << (APB_CTRL_CK8M_TICK_NUM_S))
|
||||
#define APB_CTRL_CK8M_TICK_NUM_V 0xFF
|
||||
#define APB_CTRL_CK8M_TICK_NUM_S 8
|
||||
/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_XTAL_TICK_NUM 0x000000FF
|
||||
#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V) << (APB_CTRL_XTAL_TICK_NUM_S))
|
||||
#define APB_CTRL_XTAL_TICK_NUM_V 0xFF
|
||||
#define APB_CTRL_XTAL_TICK_NUM_S 0
|
||||
|
||||
#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008)
|
||||
/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_XTAL_OEN (BIT(10))
|
||||
#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10))
|
||||
#define APB_CTRL_CLK_XTAL_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_XTAL_OEN_S 10
|
||||
/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK40X_BB_OEN (BIT(9))
|
||||
#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9))
|
||||
#define APB_CTRL_CLK40X_BB_OEN_V 0x1
|
||||
#define APB_CTRL_CLK40X_BB_OEN_S 9
|
||||
/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8))
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8))
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_DAC_CPU_OEN_S 8
|
||||
/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7))
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7))
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_ADC_INF_OEN_S 7
|
||||
/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_320M_OEN (BIT(6))
|
||||
#define APB_CTRL_CLK_320M_OEN_M (BIT(6))
|
||||
#define APB_CTRL_CLK_320M_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_320M_OEN_S 6
|
||||
/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK160_OEN (BIT(5))
|
||||
#define APB_CTRL_CLK160_OEN_M (BIT(5))
|
||||
#define APB_CTRL_CLK160_OEN_V 0x1
|
||||
#define APB_CTRL_CLK160_OEN_S 5
|
||||
/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK80_OEN (BIT(4))
|
||||
#define APB_CTRL_CLK80_OEN_M (BIT(4))
|
||||
#define APB_CTRL_CLK80_OEN_V 0x1
|
||||
#define APB_CTRL_CLK80_OEN_S 4
|
||||
/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK_BB_OEN (BIT(3))
|
||||
#define APB_CTRL_CLK_BB_OEN_M (BIT(3))
|
||||
#define APB_CTRL_CLK_BB_OEN_V 0x1
|
||||
#define APB_CTRL_CLK_BB_OEN_S 3
|
||||
/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK44_OEN (BIT(2))
|
||||
#define APB_CTRL_CLK44_OEN_M (BIT(2))
|
||||
#define APB_CTRL_CLK44_OEN_V 0x1
|
||||
#define APB_CTRL_CLK44_OEN_S 2
|
||||
/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK22_OEN (BIT(1))
|
||||
#define APB_CTRL_CLK22_OEN_M (BIT(1))
|
||||
#define APB_CTRL_CLK22_OEN_V 0x1
|
||||
#define APB_CTRL_CLK22_OEN_S 1
|
||||
/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_CLK20_OEN (BIT(0))
|
||||
#define APB_CTRL_CLK20_OEN_M (BIT(0))
|
||||
#define APB_CTRL_CLK20_OEN_V 0x1
|
||||
#define APB_CTRL_CLK20_OEN_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C)
|
||||
/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V) << (APB_CTRL_WIFI_BB_CFG_S))
|
||||
#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010)
|
||||
/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V) << (APB_CTRL_WIFI_BB_CFG_2_S))
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_BB_CFG_2_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014)
|
||||
/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V) << (APB_CTRL_WIFI_CLK_EN_S))
|
||||
#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_CLK_EN_S 0
|
||||
|
||||
#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018)
|
||||
/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_WIFI_RST 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V) << (APB_CTRL_WIFI_RST_S))
|
||||
#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF
|
||||
#define APB_CTRL_WIFI_RST_S 0
|
||||
|
||||
#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C)
|
||||
/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PERI_IO_SWAP 0x000000FF
|
||||
#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V) << (APB_CTRL_PERI_IO_SWAP_S))
|
||||
#define APB_CTRL_PERI_IO_SWAP_V 0xFF
|
||||
#define APB_CTRL_PERI_IO_SWAP_S 0
|
||||
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020)
|
||||
/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0))
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0))
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1
|
||||
#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0
|
||||
|
||||
#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x024)
|
||||
/* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set 1 to bypass cache writeback request to external memory so
|
||||
that spi will not check its attribute.*/
|
||||
#define APB_CTRL_WRITEBACK_BYPASS (BIT(0))
|
||||
#define APB_CTRL_WRITEBACK_BYPASS_M (BIT(0))
|
||||
#define APB_CTRL_WRITEBACK_BYPASS_V 0x1
|
||||
#define APB_CTRL_WRITEBACK_BYPASS_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028)
|
||||
/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR 0x000001FF
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V) << (APB_CTRL_FLASH_ACE0_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_V 0x1FF
|
||||
#define APB_CTRL_FLASH_ACE0_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C)
|
||||
/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V) << (APB_CTRL_FLASH_ACE1_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF
|
||||
#define APB_CTRL_FLASH_ACE1_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030)
|
||||
/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR 0x000001FF
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V) << (APB_CTRL_FLASH_ACE2_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_V 0x1FF
|
||||
#define APB_CTRL_FLASH_ACE2_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034)
|
||||
/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR 0x000001FF
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V) << (APB_CTRL_FLASH_ACE3_ATTR_S))
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_V 0x1FF
|
||||
#define APB_CTRL_FLASH_ACE3_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038)
|
||||
/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V) << (APB_CTRL_FLASH_ACE0_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C)
|
||||
/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V) << (APB_CTRL_FLASH_ACE1_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040)
|
||||
/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V) << (APB_CTRL_FLASH_ACE2_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044)
|
||||
/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V) << (APB_CTRL_FLASH_ACE3_ADDR_S_S))
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048)
|
||||
/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V) << (APB_CTRL_FLASH_ACE0_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_FLASH_ACE0_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C)
|
||||
/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V) << (APB_CTRL_FLASH_ACE1_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_FLASH_ACE1_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050)
|
||||
/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V) << (APB_CTRL_FLASH_ACE2_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_FLASH_ACE2_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054)
|
||||
/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V) << (APB_CTRL_FLASH_ACE3_SIZE_S))
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_FLASH_ACE3_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x058)
|
||||
/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V) << (APB_CTRL_SRAM_ACE0_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE0_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x05C)
|
||||
/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V) << (APB_CTRL_SRAM_ACE1_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE1_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x060)
|
||||
/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V) << (APB_CTRL_SRAM_ACE2_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE2_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x064)
|
||||
/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR 0x000001FF
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V) << (APB_CTRL_SRAM_ACE3_ATTR_S))
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_V 0x1FF
|
||||
#define APB_CTRL_SRAM_ACE3_ATTR_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x068)
|
||||
/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V) << (APB_CTRL_SRAM_ACE0_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x06C)
|
||||
/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V) << (APB_CTRL_SRAM_ACE1_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x070)
|
||||
/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V) << (APB_CTRL_SRAM_ACE2_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x074)
|
||||
/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V) << (APB_CTRL_SRAM_ACE3_ADDR_S_S))
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x078)
|
||||
/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V) << (APB_CTRL_SRAM_ACE0_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE0_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x07C)
|
||||
/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V) << (APB_CTRL_SRAM_ACE1_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE1_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x080)
|
||||
/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V) << (APB_CTRL_SRAM_ACE2_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE2_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x084)
|
||||
/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V) << (APB_CTRL_SRAM_ACE3_SIZE_S))
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF
|
||||
#define APB_CTRL_SRAM_ACE3_SIZE_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088)
|
||||
/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V) << (APB_CTRL_SPI_MEM_REJECT_CDE_S))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2
|
||||
/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1
|
||||
/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1
|
||||
#define APB_CTRL_SPI_MEM_REJECT_INT_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C)
|
||||
/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V) << (APB_CTRL_SPI_MEM_REJECT_ADDR_S))
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090)
|
||||
/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0))
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1
|
||||
#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094)
|
||||
/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_ANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_ANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_ANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V) << (APB_CTRL_REDCY_SIG0_S))
|
||||
#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG0_S 0
|
||||
|
||||
#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098)
|
||||
/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_NANDOR (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_M (BIT(31))
|
||||
#define APB_CTRL_REDCY_NANDOR_V 0x1
|
||||
#define APB_CTRL_REDCY_NANDOR_S 31
|
||||
/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V) << (APB_CTRL_REDCY_SIG1_S))
|
||||
#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF
|
||||
#define APB_CTRL_REDCY_SIG1_S 0
|
||||
|
||||
#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C)
|
||||
/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PD_S 5
|
||||
/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4))
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_DC_MEM_FORCE_PU_S 4
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3
|
||||
/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2))
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PD_S 1
|
||||
/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0))
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1
|
||||
#define APB_CTRL_AGC_MEM_FORCE_PU_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0)
|
||||
/* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */
|
||||
/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes.
|
||||
1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE 0x00000003
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE_M ((APB_CTRL_SRAM_PAGE_SIZE_V) << (APB_CTRL_SRAM_PAGE_SIZE_S))
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE_V 0x3
|
||||
#define APB_CTRL_SRAM_PAGE_SIZE_S 20
|
||||
/* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
||||
/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512
|
||||
bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE 0x00000003
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE_M ((APB_CTRL_FLASH_PAGE_SIZE_V) << (APB_CTRL_FLASH_PAGE_SIZE_S))
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE_V 0x3
|
||||
#define APB_CTRL_FLASH_PAGE_SIZE_S 18
|
||||
/* APB_CTRL_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable MSPI interrupt when the error times of
|
||||
MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/
|
||||
#define APB_CTRL_ECC_ERR_INT_EN (BIT(17))
|
||||
#define APB_CTRL_ECC_ERR_INT_EN_M (BIT(17))
|
||||
#define APB_CTRL_ECC_ERR_INT_EN_V 0x1
|
||||
#define APB_CTRL_ECC_ERR_INT_EN_S 17
|
||||
/* APB_CTRL_ECC_ERR_INT_NUM : R/W ;bitpos:[16:9] ;default: 8'd10 ; */
|
||||
/*description: Set the error times of MSPI ECC read to generate MSPI interrupt.*/
|
||||
#define APB_CTRL_ECC_ERR_INT_NUM 0x000000FF
|
||||
#define APB_CTRL_ECC_ERR_INT_NUM_M ((APB_CTRL_ECC_ERR_INT_NUM_V) << (APB_CTRL_ECC_ERR_INT_NUM_S))
|
||||
#define APB_CTRL_ECC_ERR_INT_NUM_V 0xFF
|
||||
#define APB_CTRL_ECC_ERR_INT_NUM_S 9
|
||||
/* APB_CTRL_ECC_ERR_CNT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */
|
||||
/*description: Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/
|
||||
#define APB_CTRL_ECC_ERR_CNT_CLR (BIT(8))
|
||||
#define APB_CTRL_ECC_ERR_CNT_CLR_M (BIT(8))
|
||||
#define APB_CTRL_ECC_ERR_CNT_CLR_V 0x1
|
||||
#define APB_CTRL_ECC_ERR_CNT_CLR_S 8
|
||||
/* APB_CTRL_ECC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */
|
||||
/*description: This bits show the error times of MSPI ECC read.*/
|
||||
#define APB_CTRL_ECC_ERR_CNT 0x000000FF
|
||||
#define APB_CTRL_ECC_ERR_CNT_M ((APB_CTRL_ECC_ERR_CNT_V) << (APB_CTRL_ECC_ERR_CNT_S))
|
||||
#define APB_CTRL_ECC_ERR_CNT_V 0xFF
|
||||
#define APB_CTRL_ECC_ERR_CNT_S 0
|
||||
|
||||
#define APB_CTRL_SPI_MEM_ECC_ERR_AADR_REG (DR_REG_APB_CTRL_BASE + 0x0A4)
|
||||
/* APB_CTRL_ECC_ERR_ADDR : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: This bits show the latest MSPI ECC error address.*/
|
||||
#define APB_CTRL_ECC_ERR_ADDR 0xFFFFFFFF
|
||||
#define APB_CTRL_ECC_ERR_ADDR_M ((APB_CTRL_ECC_ERR_ADDR_V) << (APB_CTRL_ECC_ERR_ADDR_S))
|
||||
#define APB_CTRL_ECC_ERR_ADDR_V 0xFFFFFFFF
|
||||
#define APB_CTRL_ECC_ERR_ADDR_S 0
|
||||
|
||||
#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC)
|
||||
/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h20032301 ; */
|
||||
/*description: Version control*/
|
||||
#define APB_CTRL_DATE 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V) << (APB_CTRL_DATE_S))
|
||||
#define APB_CTRL_DATE_V 0xFFFFFFFF
|
||||
#define APB_CTRL_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
480
components/soc/soc/esp32s3/include/soc/apb_ctrl_struct.h
Normal file
480
components/soc/soc/esp32s3/include/soc/apb_ctrl_struct.h
Normal file
|
|
@ -0,0 +1,480 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t pre_div: 10;
|
||||
uint32_t clk_320m_en: 1;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t rst_tick: 1;
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal_tick: 8;
|
||||
uint32_t ck8m_tick: 8;
|
||||
uint32_t tick_enable: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} tick_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk20_oen: 1;
|
||||
uint32_t clk22_oen: 1;
|
||||
uint32_t clk44_oen: 1;
|
||||
uint32_t clk_bb_oen: 1;
|
||||
uint32_t clk80_oen: 1;
|
||||
uint32_t clk160_oen: 1;
|
||||
uint32_t clk_320m_oen: 1;
|
||||
uint32_t clk_adc_inf_oen: 1;
|
||||
uint32_t clk_dac_cpu_oen: 1;
|
||||
uint32_t clk40x_bb_oen: 1;
|
||||
uint32_t clk_xtal_oen: 1;
|
||||
uint32_t reserved11: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_out_en;
|
||||
uint32_t wifi_bb_cfg; /**/
|
||||
uint32_t wifi_bb_cfg_2; /**/
|
||||
uint32_t wifi_clk_en; /**/
|
||||
uint32_t wifi_rst_en; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t peri_io_swap: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} host_inf_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ext_mem_pms_lock: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_pms_lock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_mem_writeback_bypass;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_attr;
|
||||
uint32_t flash_ace0_addr; /**/
|
||||
uint32_t flash_ace1_addr; /**/
|
||||
uint32_t flash_ace2_addr; /**/
|
||||
uint32_t flash_ace3_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace0_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace1_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace2_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t flash_ace3_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} flash_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_attr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_attr: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_attr;
|
||||
uint32_t sram_ace0_addr; /**/
|
||||
uint32_t sram_ace1_addr; /**/
|
||||
uint32_t sram_ace2_addr; /**/
|
||||
uint32_t sram_ace3_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace0_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace0_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace1_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace2_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace2_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sram_ace3_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_ace3_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_mem_reject_int: 1;
|
||||
uint32_t spi_mem_reject_clr: 1;
|
||||
uint32_t spi_mem_reject_cde: 5;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_pms_ctrl;
|
||||
uint32_t spi_mem_reject_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_win_access_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig0: 31;
|
||||
uint32_t redcy_andor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t redcy_sig1: 31;
|
||||
uint32_t redcy_nandor: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} redcy_sig1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t agc_mem_force_pu: 1;
|
||||
uint32_t agc_mem_force_pd: 1;
|
||||
uint32_t pbus_mem_force_pu: 1;
|
||||
uint32_t pbus_mem_force_pd: 1;
|
||||
uint32_t dc_mem_force_pu: 1;
|
||||
uint32_t dc_mem_force_pd: 1;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} front_end_mem_pd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ecc_err: 8; /*This bits show the error times of MSPI ECC read.*/
|
||||
uint32_t ecc_err_clr: 1; /*Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/
|
||||
uint32_t ecc_err_int_num: 8; /*Set the error times of MSPI ECC read to generate MSPI interrupt.*/
|
||||
uint32_t ecc_err_int_en: 1; /*Set this bit to enable MSPI interrupt when the error times of MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/
|
||||
uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/
|
||||
uint32_t reserved22: 10; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_mem_ecc_ctrl;
|
||||
uint32_t spi_mem_ecc_err_aadr; /*This bits show the latest MSPI ECC error address.*/
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t date; /*Version control*/
|
||||
} apb_ctrl_dev_t;
|
||||
|
||||
extern apb_ctrl_dev_t APB_CTRL;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
698
components/soc/soc/esp32s3/include/soc/apb_saradc_reg.h
Normal file
698
components/soc/soc/esp32s3/include/soc/apb_saradc_reg.h
Normal file
|
|
@ -0,0 +1,698 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000)
|
||||
/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */
|
||||
/*description: wait arbit signal stable after sar_done*/
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V) << (APB_SARADC_WAIT_ARB_CYCLE_S))
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3
|
||||
#define APB_SARADC_WAIT_ARB_CYCLE_S 30
|
||||
/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */
|
||||
/*description: force option to xpd sar blocks*/
|
||||
#define APB_SARADC_XPD_SAR_FORCE 0x00000003
|
||||
#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V) << (APB_SARADC_XPD_SAR_FORCE_S))
|
||||
#define APB_SARADC_XPD_SAR_FORCE_V 0x3
|
||||
#define APB_SARADC_XPD_SAR_FORCE_S 27
|
||||
/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data
|
||||
is from GPIO matrix*/
|
||||
#define APB_SARADC_DATA_TO_I2S (BIT(26))
|
||||
#define APB_SARADC_DATA_TO_I2S_M (BIT(26))
|
||||
#define APB_SARADC_DATA_TO_I2S_V 0x1
|
||||
#define APB_SARADC_DATA_TO_I2S_S 26
|
||||
/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */
|
||||
/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data
|
||||
in this case the resolution should not be larger than 11 bits.*/
|
||||
#define APB_SARADC_DATA_SAR_SEL (BIT(25))
|
||||
#define APB_SARADC_DATA_SAR_SEL_M (BIT(25))
|
||||
#define APB_SARADC_DATA_SAR_SEL_V 0x1
|
||||
#define APB_SARADC_DATA_SAR_SEL_S 25
|
||||
/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */
|
||||
/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24))
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24))
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1
|
||||
#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24
|
||||
/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */
|
||||
/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23))
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23))
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1
|
||||
#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23
|
||||
/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */
|
||||
/*description: 0 ~ 15 means length 1 ~ 16*/
|
||||
#define APB_SARADC_SAR2_PATT_LEN 0x0000000F
|
||||
#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V) << (APB_SARADC_SAR2_PATT_LEN_S))
|
||||
#define APB_SARADC_SAR2_PATT_LEN_V 0xF
|
||||
#define APB_SARADC_SAR2_PATT_LEN_S 19
|
||||
/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */
|
||||
/*description: 0 ~ 15 means length 1 ~ 16*/
|
||||
#define APB_SARADC_SAR1_PATT_LEN 0x0000000F
|
||||
#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V) << (APB_SARADC_SAR1_PATT_LEN_S))
|
||||
#define APB_SARADC_SAR1_PATT_LEN_V 0xF
|
||||
#define APB_SARADC_SAR1_PATT_LEN_S 15
|
||||
/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */
|
||||
/*description: SAR clock divider*/
|
||||
#define APB_SARADC_SAR_CLK_DIV 0x000000FF
|
||||
#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V) << (APB_SARADC_SAR_CLK_DIV_S))
|
||||
#define APB_SARADC_SAR_CLK_DIV_V 0xFF
|
||||
#define APB_SARADC_SAR_CLK_DIV_S 7
|
||||
/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_SAR_CLK_GATED (BIT(6))
|
||||
#define APB_SARADC_SAR_CLK_GATED_M (BIT(6))
|
||||
#define APB_SARADC_SAR_CLK_GATED_V 0x1
|
||||
#define APB_SARADC_SAR_CLK_GATED_S 6
|
||||
/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */
|
||||
/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/
|
||||
#define APB_SARADC_SAR_SEL (BIT(5))
|
||||
#define APB_SARADC_SAR_SEL_M (BIT(5))
|
||||
#define APB_SARADC_SAR_SEL_V 0x1
|
||||
#define APB_SARADC_SAR_SEL_S 5
|
||||
/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */
|
||||
/*description: 0: single mode 1: double mode 2: alternate mode*/
|
||||
#define APB_SARADC_WORK_MODE 0x00000003
|
||||
#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V) << (APB_SARADC_WORK_MODE_S))
|
||||
#define APB_SARADC_WORK_MODE_V 0x3
|
||||
#define APB_SARADC_WORK_MODE_S 3
|
||||
/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_START (BIT(1))
|
||||
#define APB_SARADC_START_M (BIT(1))
|
||||
#define APB_SARADC_START_V 0x1
|
||||
#define APB_SARADC_START_S 1
|
||||
/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_START_FORCE (BIT(0))
|
||||
#define APB_SARADC_START_FORCE_M (BIT(0))
|
||||
#define APB_SARADC_START_FORCE_V 0x1
|
||||
#define APB_SARADC_START_FORCE_S 0
|
||||
|
||||
#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004)
|
||||
/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */
|
||||
/*description: to enable saradc timer trigger*/
|
||||
#define APB_SARADC_TIMER_EN (BIT(24))
|
||||
#define APB_SARADC_TIMER_EN_M (BIT(24))
|
||||
#define APB_SARADC_TIMER_EN_V 0x1
|
||||
#define APB_SARADC_TIMER_EN_S 24
|
||||
/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */
|
||||
/*description: to set saradc timer target*/
|
||||
#define APB_SARADC_TIMER_TARGET 0x00000FFF
|
||||
#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V) << (APB_SARADC_TIMER_TARGET_S))
|
||||
#define APB_SARADC_TIMER_TARGET_V 0xFFF
|
||||
#define APB_SARADC_TIMER_TARGET_S 12
|
||||
/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */
|
||||
/*description: 1: select saradc timer 0: i2s_ws trigger*/
|
||||
#define APB_SARADC_TIMER_SEL (BIT(11))
|
||||
#define APB_SARADC_TIMER_SEL_M (BIT(11))
|
||||
#define APB_SARADC_TIMER_SEL_V 0x1
|
||||
#define APB_SARADC_TIMER_SEL_S 11
|
||||
/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */
|
||||
/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/
|
||||
#define APB_SARADC_SAR2_INV (BIT(10))
|
||||
#define APB_SARADC_SAR2_INV_M (BIT(10))
|
||||
#define APB_SARADC_SAR2_INV_V 0x1
|
||||
#define APB_SARADC_SAR2_INV_S 10
|
||||
/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */
|
||||
/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/
|
||||
#define APB_SARADC_SAR1_INV (BIT(9))
|
||||
#define APB_SARADC_SAR1_INV_M (BIT(9))
|
||||
#define APB_SARADC_SAR1_INV_V 0x1
|
||||
#define APB_SARADC_SAR1_INV_S 9
|
||||
/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */
|
||||
/*description: max conversion number*/
|
||||
#define APB_SARADC_MAX_MEAS_NUM 0x000000FF
|
||||
#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V) << (APB_SARADC_MAX_MEAS_NUM_S))
|
||||
#define APB_SARADC_MAX_MEAS_NUM_V 0xFF
|
||||
#define APB_SARADC_MAX_MEAS_NUM_S 1
|
||||
/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0))
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0))
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1
|
||||
#define APB_SARADC_MEAS_NUM_LIMIT_S 0
|
||||
|
||||
#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008)
|
||||
/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_FILTER_FACTOR0 0x00000007
|
||||
#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V) << (APB_SARADC_FILTER_FACTOR0_S))
|
||||
#define APB_SARADC_FILTER_FACTOR0_V 0x7
|
||||
#define APB_SARADC_FILTER_FACTOR0_S 29
|
||||
/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_FILTER_FACTOR1 0x00000007
|
||||
#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V) << (APB_SARADC_FILTER_FACTOR1_S))
|
||||
#define APB_SARADC_FILTER_FACTOR1_V 0x7
|
||||
#define APB_SARADC_FILTER_FACTOR1_S 26
|
||||
|
||||
#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C)
|
||||
/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_STANDBY_WAIT 0x000000FF
|
||||
#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V) << (APB_SARADC_STANDBY_WAIT_S))
|
||||
#define APB_SARADC_STANDBY_WAIT_V 0xFF
|
||||
#define APB_SARADC_STANDBY_WAIT_S 16
|
||||
/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_RSTB_WAIT 0x000000FF
|
||||
#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V) << (APB_SARADC_RSTB_WAIT_S))
|
||||
#define APB_SARADC_RSTB_WAIT_V 0xFF
|
||||
#define APB_SARADC_RSTB_WAIT_S 8
|
||||
/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_XPD_WAIT 0x000000FF
|
||||
#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V) << (APB_SARADC_XPD_WAIT_S))
|
||||
#define APB_SARADC_XPD_WAIT_V 0xFF
|
||||
#define APB_SARADC_XPD_WAIT_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010)
|
||||
/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V) << (APB_SARADC_SAR1_STATUS_S))
|
||||
#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR1_STATUS_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014)
|
||||
/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V) << (APB_SARADC_SAR2_STATUS_S))
|
||||
#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF
|
||||
#define APB_SARADC_SAR2_STATUS_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018)
|
||||
/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB1 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V) << (APB_SARADC_SAR1_PATT_TAB1_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB1_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C)
|
||||
/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB2 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V) << (APB_SARADC_SAR1_PATT_TAB2_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB2_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020)
|
||||
/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB3 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V) << (APB_SARADC_SAR1_PATT_TAB3_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB3_S 0
|
||||
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024)
|
||||
/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/
|
||||
#define APB_SARADC_SAR1_PATT_TAB4 0x00FFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V) << (APB_SARADC_SAR1_PATT_TAB4_S))
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR1_PATT_TAB4_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028)
|
||||
/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB1 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V) << (APB_SARADC_SAR2_PATT_TAB1_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB1_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C)
|
||||
/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB2 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V) << (APB_SARADC_SAR2_PATT_TAB2_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB2_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030)
|
||||
/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB3 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V) << (APB_SARADC_SAR2_PATT_TAB3_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB3_S 0
|
||||
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034)
|
||||
/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */
|
||||
/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/
|
||||
#define APB_SARADC_SAR2_PATT_TAB4 0x00FFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V) << (APB_SARADC_SAR2_PATT_TAB4_S))
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFF
|
||||
#define APB_SARADC_SAR2_PATT_TAB4_S 0
|
||||
|
||||
#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038)
|
||||
/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter uses fixed priority*/
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12))
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12))
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12
|
||||
/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */
|
||||
/*description: Set adc2 arbiter wifi priority*/
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V) << (APB_SARADC_ADC_ARB_WIFI_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10
|
||||
/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */
|
||||
/*description: Set adc2 arbiter rtc priority*/
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V) << (APB_SARADC_ADC_ARB_RTC_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8
|
||||
/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */
|
||||
/*description: Set adc2 arbiterapb priority*/
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V) << (APB_SARADC_ADC_ARB_APB_PRIORITY_S))
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3
|
||||
#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6
|
||||
/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force grant*/
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5))
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5))
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5
|
||||
/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enable wifi controller*/
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4))
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4
|
||||
/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enable rtc controller*/
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3))
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3))
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3
|
||||
/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: adc2 arbiter force to enableapb controller*/
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2))
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2))
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1
|
||||
#define APB_SARADC_ADC_ARB_APB_FORCE_S 2
|
||||
|
||||
#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x03C)
|
||||
/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: enable apb_adc1_filter*/
|
||||
#define APB_SARADC_FILTER_RESET (BIT(31))
|
||||
#define APB_SARADC_FILTER_RESET_M (BIT(31))
|
||||
#define APB_SARADC_FILTER_RESET_V 0x1
|
||||
#define APB_SARADC_FILTER_RESET_S 31
|
||||
/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[23:19] ;default: 5'hd ; */
|
||||
/*description: apb_adc1_filter_factor*/
|
||||
#define APB_SARADC_FILTER_CHANNEL0 0x0000001F
|
||||
#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V) << (APB_SARADC_FILTER_CHANNEL0_S))
|
||||
#define APB_SARADC_FILTER_CHANNEL0_V 0x1F
|
||||
#define APB_SARADC_FILTER_CHANNEL0_S 19
|
||||
/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[18:14] ;default: 5'hd ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_FILTER_CHANNEL1 0x0000001F
|
||||
#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V) << (APB_SARADC_FILTER_CHANNEL1_S))
|
||||
#define APB_SARADC_FILTER_CHANNEL1_V 0x1F
|
||||
#define APB_SARADC_FILTER_CHANNEL1_S 14
|
||||
|
||||
#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040)
|
||||
/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DATA 0x0001FFFF
|
||||
#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V) << (APB_SARADC_ADC1_DATA_S))
|
||||
#define APB_SARADC_ADC1_DATA_V 0x1FFFF
|
||||
#define APB_SARADC_ADC1_DATA_S 0
|
||||
|
||||
#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044)
|
||||
/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES0_LOW 0x00001FFF
|
||||
#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V) << (APB_SARADC_THRES0_LOW_S))
|
||||
#define APB_SARADC_THRES0_LOW_V 0x1FFF
|
||||
#define APB_SARADC_THRES0_LOW_S 18
|
||||
/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES0_HIGH 0x00001FFF
|
||||
#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V) << (APB_SARADC_THRES0_HIGH_S))
|
||||
#define APB_SARADC_THRES0_HIGH_V 0x1FFF
|
||||
#define APB_SARADC_THRES0_HIGH_S 5
|
||||
/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_CHANNEL 0x0000001F
|
||||
#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V) << (APB_SARADC_THRES0_CHANNEL_S))
|
||||
#define APB_SARADC_THRES0_CHANNEL_V 0x1F
|
||||
#define APB_SARADC_THRES0_CHANNEL_S 0
|
||||
|
||||
#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x048)
|
||||
/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES1_LOW 0x00001FFF
|
||||
#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V) << (APB_SARADC_THRES1_LOW_S))
|
||||
#define APB_SARADC_THRES1_LOW_V 0x1FFF
|
||||
#define APB_SARADC_THRES1_LOW_S 18
|
||||
/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */
|
||||
/*description: saradc1's thres0 monitor thres*/
|
||||
#define APB_SARADC_THRES1_HIGH 0x00001FFF
|
||||
#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V) << (APB_SARADC_THRES1_HIGH_S))
|
||||
#define APB_SARADC_THRES1_HIGH_V 0x1FFF
|
||||
#define APB_SARADC_THRES1_HIGH_S 5
|
||||
/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_CHANNEL 0x0000001F
|
||||
#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V) << (APB_SARADC_THRES1_CHANNEL_S))
|
||||
#define APB_SARADC_THRES1_CHANNEL_V 0x1F
|
||||
#define APB_SARADC_THRES1_CHANNEL_S 0
|
||||
|
||||
#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058)
|
||||
/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_EN (BIT(31))
|
||||
#define APB_SARADC_THRES0_EN_M (BIT(31))
|
||||
#define APB_SARADC_THRES0_EN_V 0x1
|
||||
#define APB_SARADC_THRES0_EN_S 31
|
||||
/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_EN (BIT(30))
|
||||
#define APB_SARADC_THRES1_EN_M (BIT(30))
|
||||
#define APB_SARADC_THRES1_EN_V 0x1
|
||||
#define APB_SARADC_THRES1_EN_S 30
|
||||
/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES2_EN (BIT(29))
|
||||
#define APB_SARADC_THRES2_EN_M (BIT(29))
|
||||
#define APB_SARADC_THRES2_EN_V 0x1
|
||||
#define APB_SARADC_THRES2_EN_S 29
|
||||
/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES3_EN (BIT(28))
|
||||
#define APB_SARADC_THRES3_EN_M (BIT(28))
|
||||
#define APB_SARADC_THRES3_EN_V 0x1
|
||||
#define APB_SARADC_THRES3_EN_S 28
|
||||
/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES_ALL_EN (BIT(27))
|
||||
#define APB_SARADC_THRES_ALL_EN_M (BIT(27))
|
||||
#define APB_SARADC_THRES_ALL_EN_V 0x1
|
||||
#define APB_SARADC_THRES_ALL_EN_S 27
|
||||
|
||||
#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x05C)
|
||||
/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_ENA_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_ENA_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_ENA_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_ENA_S 26
|
||||
|
||||
#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x060)
|
||||
/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_RAW_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_RAW_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_RAW_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_RAW_S 26
|
||||
|
||||
#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x064)
|
||||
/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_ST_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_ST_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_ST_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_ST_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_ST_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_ST_S 26
|
||||
|
||||
#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x068)
|
||||
/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31))
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1
|
||||
#define APB_SARADC_ADC1_DONE_INT_CLR_S 31
|
||||
/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30))
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1
|
||||
#define APB_SARADC_ADC2_DONE_INT_CLR_S 30
|
||||
/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29))
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29
|
||||
/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28))
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28
|
||||
/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27))
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES0_LOW_INT_CLR_S 27
|
||||
/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26))
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1
|
||||
#define APB_SARADC_THRES1_LOW_INT_CLR_S 26
|
||||
|
||||
#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x06c)
|
||||
/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */
|
||||
/*description: enable apb_adc use spi_dma*/
|
||||
#define APB_SARADC_APB_ADC_TRANS (BIT(31))
|
||||
#define APB_SARADC_APB_ADC_TRANS_M (BIT(31))
|
||||
#define APB_SARADC_APB_ADC_TRANS_V 0x1
|
||||
#define APB_SARADC_APB_ADC_TRANS_S 31
|
||||
/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: reset_apb_adc_state*/
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30))
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30))
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1
|
||||
#define APB_SARADC_APB_ADC_RESET_FSM_S 30
|
||||
/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */
|
||||
/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V) << (APB_SARADC_APB_ADC_EOF_NUM_S))
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF
|
||||
#define APB_SARADC_APB_ADC_EOF_NUM_S 0
|
||||
|
||||
#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x070)
|
||||
/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */
|
||||
/*description: Set this bit to enable clk_apll*/
|
||||
#define APB_SARADC_CLK_SEL 0x00000003
|
||||
#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V) << (APB_SARADC_CLK_SEL_S))
|
||||
#define APB_SARADC_CLK_SEL_V 0x3
|
||||
#define APB_SARADC_CLK_SEL_S 21
|
||||
/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_CLK_EN (BIT(20))
|
||||
#define APB_SARADC_CLK_EN_M (BIT(20))
|
||||
#define APB_SARADC_CLK_EN_V 0x1
|
||||
#define APB_SARADC_CLK_EN_S 20
|
||||
/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider denominator value*/
|
||||
#define APB_SARADC_CLKM_DIV_A 0x0000003F
|
||||
#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V) << (APB_SARADC_CLKM_DIV_A_S))
|
||||
#define APB_SARADC_CLKM_DIV_A_V 0x3F
|
||||
#define APB_SARADC_CLKM_DIV_A_S 14
|
||||
/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider numerator value*/
|
||||
#define APB_SARADC_CLKM_DIV_B 0x0000003F
|
||||
#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V) << (APB_SARADC_CLKM_DIV_B_S))
|
||||
#define APB_SARADC_CLKM_DIV_B_V 0x3F
|
||||
#define APB_SARADC_CLKM_DIV_B_S 8
|
||||
/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */
|
||||
/*description: Integral I2S clock divider value*/
|
||||
#define APB_SARADC_CLKM_DIV_NUM 0x000000FF
|
||||
#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V) << (APB_SARADC_CLKM_DIV_NUM_S))
|
||||
#define APB_SARADC_CLKM_DIV_NUM_V 0xFF
|
||||
#define APB_SARADC_CLKM_DIV_NUM_S 0
|
||||
|
||||
#define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x074)
|
||||
/* APB_SARADC_DAC_CLK_GATE_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_DAC_CLK_GATE_EN (BIT(18))
|
||||
#define APB_SARADC_DAC_CLK_GATE_EN_M (BIT(18))
|
||||
#define APB_SARADC_DAC_CLK_GATE_EN_V 0x1
|
||||
#define APB_SARADC_DAC_CLK_GATE_EN_S 18
|
||||
/* APB_SARADC_DAC_CLK_FO : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_DAC_CLK_FO (BIT(17))
|
||||
#define APB_SARADC_DAC_CLK_FO_M (BIT(17))
|
||||
#define APB_SARADC_DAC_CLK_FO_V 0x1
|
||||
#define APB_SARADC_DAC_CLK_FO_S 17
|
||||
/* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_APB_DAC_RST (BIT(16))
|
||||
#define APB_SARADC_APB_DAC_RST_M (BIT(16))
|
||||
#define APB_SARADC_APB_DAC_RST_V 0x1
|
||||
#define APB_SARADC_APB_DAC_RST_S 16
|
||||
/* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_DAC_RESET_FIFO (BIT(15))
|
||||
#define APB_SARADC_DAC_RESET_FIFO_M (BIT(15))
|
||||
#define APB_SARADC_DAC_RESET_FIFO_V 0x1
|
||||
#define APB_SARADC_DAC_RESET_FIFO_S 15
|
||||
/* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
||||
/*description: enable dma_dac*/
|
||||
#define APB_SARADC_APB_DAC_TRANS (BIT(14))
|
||||
#define APB_SARADC_APB_DAC_TRANS_M (BIT(14))
|
||||
#define APB_SARADC_APB_DAC_TRANS_V 0x1
|
||||
#define APB_SARADC_APB_DAC_TRANS_S 14
|
||||
/* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */
|
||||
/*description: enable dac alter mode*/
|
||||
#define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13))
|
||||
#define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13))
|
||||
#define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1
|
||||
#define APB_SARADC_APB_DAC_ALTER_MODE_S 13
|
||||
/* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */
|
||||
/*description: enable read dac data*/
|
||||
#define APB_SARADC_DAC_TIMER_EN (BIT(12))
|
||||
#define APB_SARADC_DAC_TIMER_EN_M (BIT(12))
|
||||
#define APB_SARADC_DAC_TIMER_EN_V 0x1
|
||||
#define APB_SARADC_DAC_TIMER_EN_S 12
|
||||
/* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */
|
||||
/*description: dac_timer target*/
|
||||
#define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF
|
||||
#define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V) << (APB_SARADC_DAC_TIMER_TARGET_S))
|
||||
#define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF
|
||||
#define APB_SARADC_DAC_TIMER_TARGET_S 0
|
||||
|
||||
#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x078)
|
||||
/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_ADC2_DATA 0x0001FFFF
|
||||
#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V) << (APB_SARADC_ADC2_DATA_S))
|
||||
#define APB_SARADC_ADC2_DATA_V 0x1FFFF
|
||||
#define APB_SARADC_ADC2_DATA_S 0
|
||||
|
||||
#define APB_SARADC_APB_DAC_CLK_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x07c)
|
||||
/* APB_SARADC_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_DAC_CLK_DIV 0x000000FF
|
||||
#define APB_SARADC_DAC_CLK_DIV_M ((APB_SARADC_DAC_CLK_DIV_V) << (APB_SARADC_DAC_CLK_DIV_S))
|
||||
#define APB_SARADC_DAC_CLK_DIV_V 0xFF
|
||||
#define APB_SARADC_DAC_CLK_DIV_S 0
|
||||
|
||||
#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC)
|
||||
/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02003060 ; */
|
||||
/*description: */
|
||||
#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF
|
||||
#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V) << (APB_SARADC_APB_CTRL_DATE_S))
|
||||
#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF
|
||||
#define APB_SARADC_APB_CTRL_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
521
components/soc/soc/esp32s3/include/soc/apb_saradc_struct.h
Normal file
521
components/soc/soc/esp32s3/include/soc/apb_saradc_struct.h
Normal file
|
|
@ -0,0 +1,521 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t start_force: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t reserved2: 1;
|
||||
uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/
|
||||
uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/
|
||||
uint32_t sar_clk_gated: 1;
|
||||
uint32_t sar_clk_div: 8; /*SAR clock divider*/
|
||||
uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
|
||||
uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/
|
||||
uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/
|
||||
uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/
|
||||
uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/
|
||||
uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/
|
||||
uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/
|
||||
uint32_t reserved29: 1;
|
||||
uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas_num_limit: 1;
|
||||
uint32_t max_meas_num: 8; /*max conversion number*/
|
||||
uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/
|
||||
uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/
|
||||
uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/
|
||||
uint32_t timer_target: 12; /*to set saradc timer target*/
|
||||
uint32_t timer_en: 1; /*to enable saradc timer trigger*/
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t filter_factor1: 3;
|
||||
uint32_t filter_factor0: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} filter_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t xpd_wait: 8;
|
||||
uint32_t rstb_wait: 8;
|
||||
uint32_t standby_wait: 8;
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} fsm_wait;
|
||||
uint32_t sar1_status; /**/
|
||||
uint32_t sar2_status; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar1_patt_tab1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar1_patt_tab2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar1_patt_tab3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar1_patt_tab4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_patt_tab1: 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar2_patt_tab1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar2_patt_tab2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar2_patt_tab3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar2_patt_tab4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 2;
|
||||
uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/
|
||||
uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/
|
||||
uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/
|
||||
uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/
|
||||
uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/
|
||||
uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/
|
||||
uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/
|
||||
uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_adc_arb_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 14;
|
||||
uint32_t filter_channel1: 5;
|
||||
uint32_t filter_channel0: 5; /*apb_adc1_filter_factor*/
|
||||
uint32_t reserved24: 7;
|
||||
uint32_t filter_reset: 1; /*enable apb_adc1_filter*/
|
||||
};
|
||||
uint32_t val;
|
||||
} filter_ctrl0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t adc1_data: 17;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc1_data_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres0_channel: 5;
|
||||
uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/
|
||||
};
|
||||
uint32_t val;
|
||||
} thres0_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres1_channel: 5;
|
||||
uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres1_ctrl;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t thres_all_en: 1;
|
||||
uint32_t thres3_en: 1;
|
||||
uint32_t thres2_en: 1;
|
||||
uint32_t thres1_en: 1;
|
||||
uint32_t thres0_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} thres_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t thres1_low: 1;
|
||||
uint32_t thres0_low: 1;
|
||||
uint32_t thres1_high: 1;
|
||||
uint32_t thres0_high: 1;
|
||||
uint32_t adc2_done: 1;
|
||||
uint32_t adc1_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/
|
||||
uint32_t reserved16: 14;
|
||||
uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/
|
||||
uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dma_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/
|
||||
uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/
|
||||
uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_adc_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dac_timer_target: 12; /*dac_timer target*/
|
||||
uint32_t dac_timer_en: 1; /*enable read dac data*/
|
||||
uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/
|
||||
uint32_t apb_dac_trans: 1; /*enable dma_dac*/
|
||||
uint32_t dac_reset_fifo: 1;
|
||||
uint32_t apb_dac_rst: 1;
|
||||
uint32_t dac_clk_fo: 1;
|
||||
uint32_t dac_clk_gate_en: 1;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_dac_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t adc2_data: 17;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_saradc2_data_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dac_clk_div: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} apb_dac_clk_ctrl;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
uint32_t apb_ctrl_date; /**/
|
||||
} apb_saradc_dev_t;
|
||||
|
||||
extern apb_saradc_dev_t APB_SARADC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1332
components/soc/soc/esp32s3/include/soc/assist_debug_reg.h
Normal file
1332
components/soc/soc/esp32s3/include/soc/assist_debug_reg.h
Normal file
File diff suppressed because it is too large
Load diff
463
components/soc/soc/esp32s3/include/soc/assist_debug_struct.h
Normal file
463
components/soc/soc/esp32s3/include/soc/assist_debug_struct.h
Normal file
|
|
@ -0,0 +1,463 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd_ena: 1;
|
||||
uint32_t core_0_area_dram0_0_wr_ena: 1;
|
||||
uint32_t core_0_area_dram0_1_rd_ena: 1;
|
||||
uint32_t core_0_area_dram0_1_wr_ena: 1;
|
||||
uint32_t core_0_area_pif_0_rd_ena: 1;
|
||||
uint32_t core_0_area_pif_0_wr_ena: 1;
|
||||
uint32_t core_0_area_pif_1_rd_ena: 1;
|
||||
uint32_t core_0_area_pif_1_wr_ena: 1;
|
||||
uint32_t core_0_sp_spill_min_ena: 1;
|
||||
uint32_t core_0_sp_spill_max_ena: 1;
|
||||
uint32_t core_0_iram0_exception_monitor_ena: 1;
|
||||
uint32_t core_0_dram0_exception_monitor_ena: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd_raw: 1;
|
||||
uint32_t core_0_area_dram0_0_wr_raw: 1;
|
||||
uint32_t core_0_area_dram0_1_rd_raw: 1;
|
||||
uint32_t core_0_area_dram0_1_wr_raw: 1;
|
||||
uint32_t core_0_area_pif_0_rd_raw: 1;
|
||||
uint32_t core_0_area_pif_0_wr_raw: 1;
|
||||
uint32_t core_0_area_pif_1_rd_raw: 1;
|
||||
uint32_t core_0_area_pif_1_wr_raw: 1;
|
||||
uint32_t core_0_sp_spill_min_raw: 1;
|
||||
uint32_t core_0_sp_spill_max_raw: 1;
|
||||
uint32_t core_0_iram0_exception_monitor_raw: 1;
|
||||
uint32_t core_0_dram0_exception_monitor_raw: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd_rls: 1;
|
||||
uint32_t core_0_area_dram0_0_wr_rls: 1;
|
||||
uint32_t core_0_area_dram0_1_rd_rls: 1;
|
||||
uint32_t core_0_area_dram0_1_wr_rls: 1;
|
||||
uint32_t core_0_area_pif_0_rd_rls: 1;
|
||||
uint32_t core_0_area_pif_0_wr_rls: 1;
|
||||
uint32_t core_0_area_pif_1_rd_rls: 1;
|
||||
uint32_t core_0_area_pif_1_wr_rls: 1;
|
||||
uint32_t core_0_sp_spill_min_rls: 1;
|
||||
uint32_t core_0_sp_spill_max_rls: 1;
|
||||
uint32_t core_0_iram0_exception_monitor_rls: 1;
|
||||
uint32_t core_0_dram0_exception_monitor_rls: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_rls;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_area_dram0_0_rd_clr: 1;
|
||||
uint32_t core_0_area_dram0_0_wr_clr: 1;
|
||||
uint32_t core_0_area_dram0_1_rd_clr: 1;
|
||||
uint32_t core_0_area_dram0_1_wr_clr: 1;
|
||||
uint32_t core_0_area_pif_0_rd_clr: 1;
|
||||
uint32_t core_0_area_pif_0_wr_clr: 1;
|
||||
uint32_t core_0_area_pif_1_rd_clr: 1;
|
||||
uint32_t core_0_area_pif_1_wr_clr: 1;
|
||||
uint32_t core_0_sp_spill_min_clr: 1;
|
||||
uint32_t core_0_sp_spill_max_clr: 1;
|
||||
uint32_t core_0_iram0_exception_monitor_clr: 1;
|
||||
uint32_t core_0_dram0_exception_monitor_clr: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_interrupt_clr;
|
||||
uint32_t core_0_area_dram0_0_min; /**/
|
||||
uint32_t core_0_area_dram0_0_max; /**/
|
||||
uint32_t core_0_area_dram0_1_min; /**/
|
||||
uint32_t core_0_area_dram0_1_max; /**/
|
||||
uint32_t core_0_area_pif_0_min; /**/
|
||||
uint32_t core_0_area_pif_0_max; /**/
|
||||
uint32_t core_0_area_pif_1_min; /**/
|
||||
uint32_t core_0_area_pif_1_max; /**/
|
||||
uint32_t core_0_area_sp; /**/
|
||||
uint32_t core_0_area_pc; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_sp_unstable: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_sp_unstable;
|
||||
uint32_t core_0_sp_min; /**/
|
||||
uint32_t core_0_sp_max; /**/
|
||||
uint32_t core_0_sp_pc; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_rcd_pdebugenable: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_rcd_pdebugenable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_rcd_recording: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_rcd_recording;
|
||||
uint32_t core_0_rcd_pdebuginst; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_rcd_pdebugstatus: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_rcd_pdebugstatus;
|
||||
uint32_t core_0_rcd_pdebugdata; /**/
|
||||
uint32_t core_0_rcd_pdebugpc; /**/
|
||||
uint32_t core_0_rcd_pdebugls0stat; /**/
|
||||
uint32_t core_0_rcd_pdebugls0addr; /**/
|
||||
uint32_t core_0_rcd_pdebugls0data; /**/
|
||||
uint32_t core_0_rcd_sp; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_iram0_recording_addr_0: 24;
|
||||
uint32_t core_0_iram0_recording_wr_0: 1;
|
||||
uint32_t core_0_iram0_recording_loadstore_0: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_iram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_iram0_recording_addr_1: 24;
|
||||
uint32_t core_0_iram0_recording_wr_1: 1;
|
||||
uint32_t core_0_iram0_recording_loadstore_1: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_iram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_addr_0: 22;
|
||||
uint32_t core_0_dram0_recording_wr_0: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_byteen_0: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_1;
|
||||
uint32_t core_0_dram0_exception_monitor_2; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_addr_1: 22;
|
||||
uint32_t core_0_dram0_recording_wr_1: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_0_dram0_recording_byteen_1: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_0_dram0_exception_monitor_4;
|
||||
uint32_t core_0_dram0_exception_monitor_5; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd_ena: 1;
|
||||
uint32_t core_1_area_dram0_0_wr_ena: 1;
|
||||
uint32_t core_1_area_dram0_1_rd_ena: 1;
|
||||
uint32_t core_1_area_dram0_1_wr_ena: 1;
|
||||
uint32_t core_1_area_pif_0_rd_ena: 1;
|
||||
uint32_t core_1_area_pif_0_wr_ena: 1;
|
||||
uint32_t core_1_area_pif_1_rd_ena: 1;
|
||||
uint32_t core_1_area_pif_1_wr_ena: 1;
|
||||
uint32_t core_1_sp_spill_min_ena: 1;
|
||||
uint32_t core_1_sp_spill_max_ena: 1;
|
||||
uint32_t core_1_iram0_exception_monitor_ena: 1;
|
||||
uint32_t core_1_dram0_exception_monitor_ena: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd_raw: 1;
|
||||
uint32_t core_1_area_dram0_0_wr_raw: 1;
|
||||
uint32_t core_1_area_dram0_1_rd_raw: 1;
|
||||
uint32_t core_1_area_dram0_1_wr_raw: 1;
|
||||
uint32_t core_1_area_pif_0_rd_raw: 1;
|
||||
uint32_t core_1_area_pif_0_wr_raw: 1;
|
||||
uint32_t core_1_area_pif_1_rd_raw: 1;
|
||||
uint32_t core_1_area_pif_1_wr_raw: 1;
|
||||
uint32_t core_1_sp_spill_min_raw: 1;
|
||||
uint32_t core_1_sp_spill_max_raw: 1;
|
||||
uint32_t core_1_iram0_exception_monitor_raw: 1;
|
||||
uint32_t core_1_dram0_exception_monitor_raw: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd_rls: 1;
|
||||
uint32_t core_1_area_dram0_0_wr_rls: 1;
|
||||
uint32_t core_1_area_dram0_1_rd_rls: 1;
|
||||
uint32_t core_1_area_dram0_1_wr_rls: 1;
|
||||
uint32_t core_1_area_pif_0_rd_rls: 1;
|
||||
uint32_t core_1_area_pif_0_wr_rls: 1;
|
||||
uint32_t core_1_area_pif_1_rd_rls: 1;
|
||||
uint32_t core_1_area_pif_1_wr_rls: 1;
|
||||
uint32_t core_1_sp_spill_min_rls: 1;
|
||||
uint32_t core_1_sp_spill_max_rls: 1;
|
||||
uint32_t core_1_iram0_exception_monitor_rls: 1;
|
||||
uint32_t core_1_dram0_exception_monitor_rls: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_rls;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_area_dram0_0_rd_clr: 1;
|
||||
uint32_t core_1_area_dram0_0_wr_clr: 1;
|
||||
uint32_t core_1_area_dram0_1_rd_clr: 1;
|
||||
uint32_t core_1_area_dram0_1_wr_clr: 1;
|
||||
uint32_t core_1_area_pif_0_rd_clr: 1;
|
||||
uint32_t core_1_area_pif_0_wr_clr: 1;
|
||||
uint32_t core_1_area_pif_1_rd_clr: 1;
|
||||
uint32_t core_1_area_pif_1_wr_clr: 1;
|
||||
uint32_t core_1_sp_spill_min_clr: 1;
|
||||
uint32_t core_1_sp_spill_max_clr: 1;
|
||||
uint32_t core_1_iram0_exception_monitor_clr: 1;
|
||||
uint32_t core_1_dram0_exception_monitor_clr: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_interrupt_clr;
|
||||
uint32_t core_1_area_dram0_0_min; /**/
|
||||
uint32_t core_1_area_dram0_0_max; /**/
|
||||
uint32_t core_1_area_dram0_1_min; /**/
|
||||
uint32_t core_1_area_dram0_1_max; /**/
|
||||
uint32_t core_1_area_pif_0_min; /**/
|
||||
uint32_t core_1_area_pif_0_max; /**/
|
||||
uint32_t core_1_area_pif_1_min; /**/
|
||||
uint32_t core_1_area_pif_1_max; /**/
|
||||
uint32_t core_1_area_pc; /**/
|
||||
uint32_t core_1_area_sp; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_sp_unstable: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_sp_unstable;
|
||||
uint32_t core_1_sp_min; /**/
|
||||
uint32_t core_1_sp_max; /**/
|
||||
uint32_t core_1_sp_pc; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_pdebugenable: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_pdebugenable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_recording: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_recording;
|
||||
uint32_t core_1_rcd_pdebuginst; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_rcd_pdebugstatus: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_rcd_pdebugstatus;
|
||||
uint32_t core_1_rcd_pdebugdata; /**/
|
||||
uint32_t core_1_rcd_pdebugpc; /**/
|
||||
uint32_t core_1_rcd_pdebugls0stat; /**/
|
||||
uint32_t core_1_rcd_pdebugls0addr; /**/
|
||||
uint32_t core_1_rcd_pdebugls0data; /**/
|
||||
uint32_t core_1_rcd_sp; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_iram0_recording_addr_0: 24;
|
||||
uint32_t core_1_iram0_recording_wr_0: 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_0: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_iram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_iram0_recording_addr_1: 24;
|
||||
uint32_t core_1_iram0_recording_wr_1: 1;
|
||||
uint32_t core_1_iram0_recording_loadstore_1: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_iram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_addr_0: 22;
|
||||
uint32_t core_1_dram0_recording_wr_0: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_byteen_0: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_1;
|
||||
uint32_t core_1_dram0_exception_monitor_2; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_addr_1: 22;
|
||||
uint32_t core_1_dram0_recording_wr_1: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_1_dram0_recording_byteen_1: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_1_dram0_exception_monitor_4;
|
||||
uint32_t core_1_dram0_exception_monitor_5; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_0: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_x_iram0_dram0_exception_monitor_0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core_x_iram0_dram0_limit_cycle_1: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} core_x_iram0_dram0_exception_monitor_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_ena: 3;
|
||||
uint32_t log_mode: 3;
|
||||
uint32_t log_mem_loop_enable: 1;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_setting;
|
||||
uint32_t log_data_0; /**/
|
||||
uint32_t log_data_1; /**/
|
||||
uint32_t log_data_2; /**/
|
||||
uint32_t log_data_3; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_data_size: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_data_mask;
|
||||
uint32_t log_min; /**/
|
||||
uint32_t log_max; /**/
|
||||
uint32_t log_mem_start; /**/
|
||||
uint32_t log_mem_end; /**/
|
||||
uint32_t log_mem_writing_addr; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t log_mem_full_flag: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} log_mem_full_flag;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} assist_debug_dev_t;
|
||||
|
||||
extern assist_debug_dev_t ASSIST_DEBUG;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
37
components/soc/soc/esp32s3/include/soc/bb_reg.h
Normal file
37
components/soc/soc/esp32s3/include/soc/bb_reg.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
/* Some of the baseband control registers.
|
||||
* PU/PD fields defined here are used in sleep related functions.
|
||||
*/
|
||||
|
||||
#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054)
|
||||
#define BB_FFT_FORCE_PU (BIT(3))
|
||||
#define BB_FFT_FORCE_PU_M (BIT(3))
|
||||
#define BB_FFT_FORCE_PU_V 1
|
||||
#define BB_FFT_FORCE_PU_S 3
|
||||
#define BB_FFT_FORCE_PD (BIT(2))
|
||||
#define BB_FFT_FORCE_PD_M (BIT(2))
|
||||
#define BB_FFT_FORCE_PD_V 1
|
||||
#define BB_FFT_FORCE_PD_S 2
|
||||
#define BB_DC_EST_FORCE_PU (BIT(1))
|
||||
#define BB_DC_EST_FORCE_PU_M (BIT(1))
|
||||
#define BB_DC_EST_FORCE_PU_V 1
|
||||
#define BB_DC_EST_FORCE_PU_S 1
|
||||
#define BB_DC_EST_FORCE_PD (BIT(0))
|
||||
#define BB_DC_EST_FORCE_PD_M (BIT(0))
|
||||
#define BB_DC_EST_FORCE_PD_V 1
|
||||
#define BB_DC_EST_FORCE_PD_S 0
|
||||
98
components/soc/soc/esp32s3/include/soc/boot_mode.h
Normal file
98
components/soc/soc/esp32s3/include/soc/boot_mode.h
Normal file
|
|
@ -0,0 +1,98 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/*SPI Boot*/
|
||||
#define IS_1XXX(v) (((v)&0x08)==0x08)
|
||||
|
||||
/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/
|
||||
#define IS_00XX(v) (((v)&0x0c)==0x00)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/
|
||||
#define IS_0000(v) (((v)&0x0f)==0x00)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/
|
||||
#define IS_0001(v) (((v)&0x0f)==0x01)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/
|
||||
#define IS_0010(v) (((v)&0x0f)==0x02)
|
||||
|
||||
/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/
|
||||
#define IS_0011(v) (((v)&0x0f)==0x03)
|
||||
|
||||
/*legacy SPI Boot*/
|
||||
#define IS_0100(v) (((v)&0x0f)==0x04)
|
||||
|
||||
/*ATE/ANALOG Mode*/
|
||||
#define IS_0101(v) (((v)&0x0f)==0x05)
|
||||
|
||||
/*SPI(or SDIO_V1) download Mode*/
|
||||
#define IS_0110(v) (((v)&0x0f)==0x06)
|
||||
|
||||
/*Diagnostic Mode+UART0 download Mode*/
|
||||
#define IS_0111(v) (((v)&0x0f)==0x07)
|
||||
|
||||
|
||||
|
||||
#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG))
|
||||
|
||||
/*do not include download mode*/
|
||||
#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET())
|
||||
|
||||
/*all spi boot including spi/legacy*/
|
||||
#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET()))
|
||||
|
||||
/*all faster spi boot including spi*/
|
||||
#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET())
|
||||
|
||||
#if SUPPORT_SDIO_DOWNLOAD
|
||||
|
||||
/*all sdio V2 of failing edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of failing edge input, raising edge output*/
|
||||
#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of raising edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V2 of raising edge input, raising edge output*/
|
||||
#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET())
|
||||
|
||||
/*all sdio V1 of raising edge input, failing edge output*/
|
||||
#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
|
||||
/*do not include joint download mode*/
|
||||
#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
#else
|
||||
|
||||
/*do not include joint download mode*/
|
||||
#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET())
|
||||
|
||||
#endif
|
||||
|
||||
/*joint download boot*/
|
||||
#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET())
|
||||
|
||||
/*ATE mode*/
|
||||
#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET())
|
||||
|
||||
/*used by ETS_IS_SDIO_UART_BOOT*/
|
||||
#define SEL_NO_BOOT 0
|
||||
#define SEL_SDIO_BOOT BIT0
|
||||
#define SEL_UART_BOOT BIT1
|
||||
#define SEL_SPI_SLAVE_BOOT BIT2
|
||||
25
components/soc/soc/esp32s3/include/soc/brownout_caps.h
Normal file
25
components/soc/soc/esp32s3/include/soc/brownout_caps.h
Normal file
|
|
@ -0,0 +1,25 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SOC_BROWNOUT_RESET_SUPPORTED 1
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
103
components/soc/soc/esp32s3/include/soc/cache_memory.h
Normal file
103
components/soc/soc/esp32s3/include/soc/cache_memory.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/*IRAM0 is connected with Cache IBUS0*/
|
||||
#define IRAM0_ADDRESS_LOW 0x40000000
|
||||
#define IRAM0_ADDRESS_HIGH 0x44000000
|
||||
#define IRAM0_CACHE_ADDRESS_LOW 0x42000000
|
||||
#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000
|
||||
|
||||
/*DRAM0 is connected with Cache DBUS0*/
|
||||
#define DRAM0_ADDRESS_LOW 0x3C000000
|
||||
#define DRAM0_ADDRESS_HIGH 0x40000000
|
||||
#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000
|
||||
#define DRAM0_CACHE_ADDRESS_HIGH 0x3E000000
|
||||
#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH
|
||||
#define ESP_CACHE_TEMP_ADDR 0x3C800000
|
||||
|
||||
#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
|
||||
#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
|
||||
|
||||
#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr)
|
||||
#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr)
|
||||
#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr)
|
||||
#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr)
|
||||
|
||||
#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE)
|
||||
#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE)
|
||||
|
||||
#define CACHE_IBUS 0
|
||||
#define CACHE_IBUS_MMU_START 0
|
||||
#define CACHE_IBUS_MMU_END 0x800
|
||||
|
||||
#define CACHE_DBUS 1
|
||||
#define CACHE_DBUS_MMU_START 0
|
||||
#define CACHE_DBUS_MMU_END 0x800
|
||||
|
||||
#define CACHE_IROM_MMU_START 0
|
||||
#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
|
||||
#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
|
||||
#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
|
||||
#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
|
||||
|
||||
#define CACHE_DROM_MMU_MAX_END 0x400
|
||||
|
||||
#define MMU_SIZE 0x800
|
||||
#define ICACHE_MMU_SIZE 0x800
|
||||
#define DCACHE_MMU_SIZE 0x800
|
||||
|
||||
#define MMU_BUS_START(i) 0
|
||||
#define MMU_BUS_SIZE(i) 0x800
|
||||
|
||||
#define MMU_INVALID BIT(14)
|
||||
#define MMU_TYPE BIT(15)
|
||||
#define MMU_ACCESS_FLASH 0
|
||||
#define MMU_ACCESS_SPIRAM BIT(15)
|
||||
|
||||
#define CACHE_MAX_SYNC_NUM 0x400000
|
||||
#define CACHE_MAX_LOCK_NUM 0x8000
|
||||
|
||||
#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE)
|
||||
#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t))
|
||||
|
||||
#define MMU_TABLE_INVALID_VAL 0x4000
|
||||
#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL
|
||||
#define MMU_ADDRESS_MASK 0x3fff
|
||||
#define MMU_PAGE_SIZE 0x10000
|
||||
#define INVALID_PHY_PAGE 0xffff
|
||||
|
||||
#define BUS_ADDR_SIZE 0x2000000
|
||||
#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1)
|
||||
|
||||
#define CACHE_ICACHE_LOW_SHIFT 0
|
||||
#define CACHE_ICACHE_HIGH_SHIFT 2
|
||||
#define CACHE_DCACHE_LOW_SHIFT 4
|
||||
#define CACHE_DCACHE_HIGH_SHIFT 6
|
||||
|
||||
#define CACHE_MEMORY_IBANK0_ADDR 0x40370000
|
||||
#define CACHE_MEMORY_IBANK1_ADDR 0x40374000
|
||||
|
||||
#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000
|
||||
#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
23
components/soc/soc/esp32s3/include/soc/clkout_channel.h
Normal file
23
components/soc/soc/esp32s3/include/soc/clkout_channel.h
Normal file
|
|
@ -0,0 +1,23 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
//CLKOUT channels
|
||||
#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1
|
||||
#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20
|
||||
#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2
|
||||
#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19
|
||||
#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3
|
||||
#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18
|
||||
131
components/soc/soc/esp32s3/include/soc/cpu.h
Normal file
131
components/soc/soc/esp32s3/include/soc/cpu.h
Normal file
|
|
@ -0,0 +1,131 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include "xtensa/corebits.h"
|
||||
|
||||
/* C macros for xtensa special register read/write/exchange */
|
||||
|
||||
#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval));
|
||||
#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval));
|
||||
#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval));
|
||||
|
||||
/** @brief Read current stack pointer address
|
||||
*
|
||||
*/
|
||||
static inline void *get_sp(void)
|
||||
{
|
||||
void *sp;
|
||||
asm volatile ("mov %0, sp;" : "=r" (sp));
|
||||
return sp;
|
||||
}
|
||||
|
||||
/* Functions to set page attributes for Region Protection option in the CPU.
|
||||
* See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2).
|
||||
*/
|
||||
|
||||
static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr)
|
||||
{
|
||||
asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr));
|
||||
}
|
||||
|
||||
|
||||
static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
|
||||
{
|
||||
asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr));
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure memory region protection
|
||||
*
|
||||
* Make page 0 access raise an exception.
|
||||
* Also protect some other unused pages so we can catch weirdness.
|
||||
* Useful attribute values:
|
||||
* 0 — cached, RW
|
||||
* 2 — bypass cache, RWX (default value after CPU reset)
|
||||
* 15 — no access, raise exception
|
||||
*/
|
||||
|
||||
static inline void cpu_configure_region_protection(void)
|
||||
{
|
||||
const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000};
|
||||
for (int i = 0; i < sizeof(pages_to_protect) / sizeof(pages_to_protect[0]); ++i) {
|
||||
cpu_write_dtlb(pages_to_protect[i], 0xf);
|
||||
cpu_write_itlb(pages_to_protect[i], 0xf);
|
||||
}
|
||||
cpu_write_dtlb(0x20000000, 0);
|
||||
cpu_write_itlb(0x20000000, 0);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Stall CPU using RTC controller
|
||||
* @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP)
|
||||
*/
|
||||
void esp_cpu_stall(int cpu_id);
|
||||
|
||||
/**
|
||||
* @brief Un-stall CPU using RTC controller
|
||||
* @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP)
|
||||
*/
|
||||
void esp_cpu_unstall(int cpu_id);
|
||||
|
||||
/**
|
||||
* @brief Reset CPU using RTC controller
|
||||
* @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP)
|
||||
*/
|
||||
void esp_cpu_reset(int cpu_id);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Returns true if a JTAG debugger is attached to CPU
|
||||
* OCD (on chip debug) port.
|
||||
*
|
||||
* @note If "Make exception and panic handlers JTAG/OCD aware"
|
||||
* is disabled, this function always returns false.
|
||||
*/
|
||||
bool esp_cpu_in_ocd_debug_mode(void);
|
||||
|
||||
/**
|
||||
* @brief Convert the PC register value to its true address
|
||||
*
|
||||
* The address of the current instruction is not stored as an exact uint32_t
|
||||
* representation in PC register. This function will convert the value stored in
|
||||
* the PC register to a uint32_t address.
|
||||
*
|
||||
* @param pc_raw The PC as stored in register format.
|
||||
*
|
||||
* @return Address in uint32_t format
|
||||
*/
|
||||
static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc)
|
||||
{
|
||||
if (pc & 0x80000000) {
|
||||
//Top two bits of a0 (return address) specify window increment. Overwrite to map to address space.
|
||||
pc = (pc & 0x3fffffff) | 0x40000000;
|
||||
}
|
||||
//Minus 3 to get PC of previous instruction (i.e. instruction executed before return address)
|
||||
return pc - 3;
|
||||
}
|
||||
|
||||
typedef uint32_t esp_cpu_ccount_t;
|
||||
|
||||
static inline esp_cpu_ccount_t esp_cpu_get_ccount(void)
|
||||
{
|
||||
uint32_t result;
|
||||
RSR(CCOUNT, result);
|
||||
return result;
|
||||
}
|
||||
20
components/soc/soc/esp32s3/include/soc/cpu_caps.h
Normal file
20
components/soc/soc/esp32s3/include/soc/cpu_caps.h
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define SOC_CPU_BREAKPOINTS_NUM 2
|
||||
#define SOC_CPU_WATCHPOINTS_NUM 2
|
||||
|
||||
#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes
|
||||
22
components/soc/soc/esp32s3/include/soc/dac_caps.h
Normal file
22
components/soc/soc/esp32s3/include/soc/dac_caps.h
Normal file
|
|
@ -0,0 +1,22 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_RTC_DAC_CAPS_H_
|
||||
#define _SOC_RTC_DAC_CAPS_H_
|
||||
|
||||
#define SOC_DAC_PERIPH_NUM 2
|
||||
|
||||
#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit
|
||||
|
||||
#endif
|
||||
24
components/soc/soc/esp32s3/include/soc/dac_channel.h
Normal file
24
components/soc/soc/esp32s3/include/soc/dac_channel.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#ifndef _SOC_DAC_CHANNEL_H
|
||||
#define _SOC_DAC_CHANNEL_H
|
||||
|
||||
#define DAC_GPIO17_CHANNEL DAC_CHANNEL_1
|
||||
#define DAC_CHANNEL_1_GPIO_NUM 17
|
||||
|
||||
#define DAC_GPIO18_CHANNEL DAC_CHANNEL_2
|
||||
#define DAC_CHANNEL_2_GPIO_NUM 18
|
||||
|
||||
#endif
|
||||
5168
components/soc/soc/esp32s3/include/soc/dma_reg.h
Normal file
5168
components/soc/soc/esp32s3/include/soc/dma_reg.h
Normal file
File diff suppressed because it is too large
Load diff
1365
components/soc/soc/esp32s3/include/soc/dma_struct.h
Normal file
1365
components/soc/soc/esp32s3/include/soc/dma_struct.h
Normal file
File diff suppressed because it is too large
Load diff
109
components/soc/soc/esp32s3/include/soc/dport_access.h
Normal file
109
components/soc/soc/esp32s3/include/soc/dport_access.h
Normal file
|
|
@ -0,0 +1,109 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
#include "esp_attr.h"
|
||||
#include "esp_attr.h"
|
||||
#include "esp32s3/dport_access.h"
|
||||
#include "soc.h"
|
||||
#include "uart_reg.h"
|
||||
#include "xtensa/xtruntime.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// ESP32S3 does not have DPORT bus, so these macros are all same as the non-DPORT versions
|
||||
|
||||
// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent.
|
||||
#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r))
|
||||
#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v)
|
||||
|
||||
// Write value to DPORT register (does not require protecting)
|
||||
#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v))
|
||||
|
||||
#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r)
|
||||
|
||||
//get bit or get bits from register
|
||||
#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b))
|
||||
|
||||
//set bit or set bits to register
|
||||
#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b)))
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m))))
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V))
|
||||
|
||||
//set field to register, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S))))
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe.
|
||||
#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr)))
|
||||
#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val)
|
||||
#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b)))
|
||||
#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b))))
|
||||
|
||||
#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr)
|
||||
|
||||
//write value to register
|
||||
#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val))
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask))))
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask)))
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask))
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1))
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift))))
|
||||
|
||||
//get field of register
|
||||
#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask))
|
||||
//}}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
33
components/soc/soc/esp32s3/include/soc/dport_reg.h
Normal file
33
components/soc/soc/esp32s3/include/soc/dport_reg.h
Normal file
|
|
@ -0,0 +1,33 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "interrupt_reg.h"
|
||||
#include "system_reg.h"
|
||||
#include "sensitive_reg.h"
|
||||
#include "soc.h"
|
||||
|
||||
#define DPORT_DATE_REG SYSTEM_DATE_REG
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include "dport_access.h"
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
421
components/soc/soc/esp32s3/include/soc/efuse_reg.h
Normal file
421
components/soc/soc/esp32s3/include/soc/efuse_reg.h
Normal file
|
|
@ -0,0 +1,421 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0)
|
||||
/* EFUSE_RD_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of key$n is reliable 1:
|
||||
Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_KEY4_FAIL (BIT(31))
|
||||
#define EFUSE_RD_KEY4_FAIL_M (BIT(31))
|
||||
#define EFUSE_RD_KEY4_FAIL_V 0x1
|
||||
#define EFUSE_RD_KEY4_FAIL_S 31
|
||||
/* EFUSE_RD_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_KEY4_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_KEY4_ERR_NUM_M ((EFUSE_RD_KEY4_ERR_NUM_V) << (EFUSE_RD_KEY4_ERR_NUM_S))
|
||||
#define EFUSE_RD_KEY4_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_KEY4_ERR_NUM_S 28
|
||||
/* EFUSE_RD_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of key$n is reliable 1:
|
||||
Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_KEY3_FAIL (BIT(27))
|
||||
#define EFUSE_RD_KEY3_FAIL_M (BIT(27))
|
||||
#define EFUSE_RD_KEY3_FAIL_V 0x1
|
||||
#define EFUSE_RD_KEY3_FAIL_S 27
|
||||
/* EFUSE_RD_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_KEY3_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_KEY3_ERR_NUM_M ((EFUSE_RD_KEY3_ERR_NUM_V) << (EFUSE_RD_KEY3_ERR_NUM_S))
|
||||
#define EFUSE_RD_KEY3_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_KEY3_ERR_NUM_S 24
|
||||
/* EFUSE_RD_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of key$n is reliable 1:
|
||||
Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_KEY2_FAIL (BIT(23))
|
||||
#define EFUSE_RD_KEY2_FAIL_M (BIT(23))
|
||||
#define EFUSE_RD_KEY2_FAIL_V 0x1
|
||||
#define EFUSE_RD_KEY2_FAIL_S 23
|
||||
/* EFUSE_RD_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_KEY2_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_KEY2_ERR_NUM_M ((EFUSE_RD_KEY2_ERR_NUM_V) << (EFUSE_RD_KEY2_ERR_NUM_S))
|
||||
#define EFUSE_RD_KEY2_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_KEY2_ERR_NUM_S 20
|
||||
/* EFUSE_RD_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of key$n is reliable 1:
|
||||
Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_KEY1_FAIL (BIT(19))
|
||||
#define EFUSE_RD_KEY1_FAIL_M (BIT(19))
|
||||
#define EFUSE_RD_KEY1_FAIL_V 0x1
|
||||
#define EFUSE_RD_KEY1_FAIL_S 19
|
||||
/* EFUSE_RD_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_KEY1_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_KEY1_ERR_NUM_M ((EFUSE_RD_KEY1_ERR_NUM_V) << (EFUSE_RD_KEY1_ERR_NUM_S))
|
||||
#define EFUSE_RD_KEY1_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_KEY1_ERR_NUM_S 16
|
||||
/* EFUSE_RD_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of key$n is reliable 1:
|
||||
Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_KEY0_FAIL (BIT(15))
|
||||
#define EFUSE_RD_KEY0_FAIL_M (BIT(15))
|
||||
#define EFUSE_RD_KEY0_FAIL_V 0x1
|
||||
#define EFUSE_RD_KEY0_FAIL_S 15
|
||||
/* EFUSE_RD_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_KEY0_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_KEY0_ERR_NUM_M ((EFUSE_RD_KEY0_ERR_NUM_V) << (EFUSE_RD_KEY0_ERR_NUM_S))
|
||||
#define EFUSE_RD_KEY0_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_KEY0_ERR_NUM_S 12
|
||||
/* EFUSE_RD_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the user data is reliable 1: Means
|
||||
that programming user data failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_USR_DATA_FAIL (BIT(11))
|
||||
#define EFUSE_RD_USR_DATA_FAIL_M (BIT(11))
|
||||
#define EFUSE_RD_USR_DATA_FAIL_V 0x1
|
||||
#define EFUSE_RD_USR_DATA_FAIL_S 11
|
||||
/* EFUSE_RD_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_USR_DATA_ERR_NUM_M ((EFUSE_RD_USR_DATA_ERR_NUM_V) << (EFUSE_RD_USR_DATA_ERR_NUM_S))
|
||||
#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_USR_DATA_ERR_NUM_S 8
|
||||
/* EFUSE_RD_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of system part1 is reliable
|
||||
1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_SYS_PART1_FAIL (BIT(7))
|
||||
#define EFUSE_RD_SYS_PART1_FAIL_M (BIT(7))
|
||||
#define EFUSE_RD_SYS_PART1_FAIL_V 0x1
|
||||
#define EFUSE_RD_SYS_PART1_FAIL_S 7
|
||||
/* EFUSE_RD_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_SYS_PART1_NUM 0x00000007
|
||||
#define EFUSE_RD_SYS_PART1_NUM_M ((EFUSE_RD_SYS_PART1_NUM_V) << (EFUSE_RD_SYS_PART1_NUM_S))
|
||||
#define EFUSE_RD_SYS_PART1_NUM_V 0x7
|
||||
#define EFUSE_RD_SYS_PART1_NUM_S 4
|
||||
/* EFUSE_RD_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable
|
||||
1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_MAC_SPI_8M_FAIL (BIT(3))
|
||||
#define EFUSE_RD_MAC_SPI_8M_FAIL_M (BIT(3))
|
||||
#define EFUSE_RD_MAC_SPI_8M_FAIL_V 0x1
|
||||
#define EFUSE_RD_MAC_SPI_8M_FAIL_S 3
|
||||
/* EFUSE_RD_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_MAC_SPI_8M_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_M ((EFUSE_RD_MAC_SPI_8M_ERR_NUM_V) << (EFUSE_RD_MAC_SPI_8M_ERR_NUM_S))
|
||||
#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_S 0
|
||||
|
||||
#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4)
|
||||
/* EFUSE_RD_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of system part2 is reliable
|
||||
1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_SYS_PART2_FAIL (BIT(7))
|
||||
#define EFUSE_RD_SYS_PART2_FAIL_M (BIT(7))
|
||||
#define EFUSE_RD_SYS_PART2_FAIL_V 0x1
|
||||
#define EFUSE_RD_SYS_PART2_FAIL_S 7
|
||||
/* EFUSE_RD_SYS_PART2_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_SYS_PART2_NUM 0x00000007
|
||||
#define EFUSE_RD_SYS_PART2_NUM_M ((EFUSE_RD_SYS_PART2_NUM_V) << (EFUSE_RD_SYS_PART2_NUM_S))
|
||||
#define EFUSE_RD_SYS_PART2_NUM_V 0x7
|
||||
#define EFUSE_RD_SYS_PART2_NUM_S 4
|
||||
/* EFUSE_RD_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: 0: Means no failure and that the data of KEY5 is reliable 1:
|
||||
Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
#define EFUSE_RD_KEY5_FAIL (BIT(3))
|
||||
#define EFUSE_RD_KEY5_FAIL_M (BIT(3))
|
||||
#define EFUSE_RD_KEY5_FAIL_V 0x1
|
||||
#define EFUSE_RD_KEY5_FAIL_S 3
|
||||
/* EFUSE_RD_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */
|
||||
/*description: The value of this signal means the number of error bytes.*/
|
||||
#define EFUSE_RD_KEY5_ERR_NUM 0x00000007
|
||||
#define EFUSE_RD_KEY5_ERR_NUM_M ((EFUSE_RD_KEY5_ERR_NUM_V) << (EFUSE_RD_KEY5_ERR_NUM_S))
|
||||
#define EFUSE_RD_KEY5_ERR_NUM_V 0x7
|
||||
#define EFUSE_RD_KEY5_ERR_NUM_S 0
|
||||
|
||||
#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8)
|
||||
/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: Set this bit and force to enable clock signal of eFuse memory.*/
|
||||
#define EFUSE_CLK_EN (BIT(16))
|
||||
#define EFUSE_CLK_EN_M (BIT(16))
|
||||
#define EFUSE_CLK_EN_V 0x1
|
||||
#define EFUSE_CLK_EN_S 16
|
||||
/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to force eFuse SRAM into working mode.*/
|
||||
#define EFUSE_MEM_FORCE_PU (BIT(2))
|
||||
#define EFUSE_MEM_FORCE_PU_M (BIT(2))
|
||||
#define EFUSE_MEM_FORCE_PU_V 0x1
|
||||
#define EFUSE_MEM_FORCE_PU_S 2
|
||||
/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */
|
||||
/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/
|
||||
#define EFUSE_MEM_CLK_FORCE_ON (BIT(1))
|
||||
#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1))
|
||||
#define EFUSE_MEM_CLK_FORCE_ON_V 0x1
|
||||
#define EFUSE_MEM_CLK_FORCE_ON_S 1
|
||||
/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to force eFuse SRAM into power-saving mode.*/
|
||||
#define EFUSE_MEM_FORCE_PD (BIT(0))
|
||||
#define EFUSE_MEM_FORCE_PD_M (BIT(0))
|
||||
#define EFUSE_MEM_FORCE_PD_V 0x1
|
||||
#define EFUSE_MEM_FORCE_PD_S 0
|
||||
|
||||
#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc)
|
||||
/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
|
||||
#define EFUSE_OP_CODE 0x0000FFFF
|
||||
#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V) << (EFUSE_OP_CODE_S))
|
||||
#define EFUSE_OP_CODE_V 0xFFFF
|
||||
#define EFUSE_OP_CODE_S 0
|
||||
|
||||
#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0)
|
||||
/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */
|
||||
/*description: Indicates the number of error bits during programming BLOCK0.*/
|
||||
#define EFUSE_REPEAT_ERR_CNT 0x000000FF
|
||||
#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V) << (EFUSE_REPEAT_ERR_CNT_S))
|
||||
#define EFUSE_REPEAT_ERR_CNT_V 0xFF
|
||||
#define EFUSE_REPEAT_ERR_CNT_S 10
|
||||
/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: The value of OTP_VDDQ_IS_SW.*/
|
||||
#define EFUSE_OTP_VDDQ_IS_SW (BIT(9))
|
||||
#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9))
|
||||
#define EFUSE_OTP_VDDQ_IS_SW_V 0x1
|
||||
#define EFUSE_OTP_VDDQ_IS_SW_S 9
|
||||
/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: The value of OTP_PGENB_SW.*/
|
||||
#define EFUSE_OTP_PGENB_SW (BIT(8))
|
||||
#define EFUSE_OTP_PGENB_SW_M (BIT(8))
|
||||
#define EFUSE_OTP_PGENB_SW_V 0x1
|
||||
#define EFUSE_OTP_PGENB_SW_S 8
|
||||
/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: The value of OTP_CSB_SW.*/
|
||||
#define EFUSE_OTP_CSB_SW (BIT(7))
|
||||
#define EFUSE_OTP_CSB_SW_M (BIT(7))
|
||||
#define EFUSE_OTP_CSB_SW_V 0x1
|
||||
#define EFUSE_OTP_CSB_SW_S 7
|
||||
/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: The value of OTP_STROBE_SW.*/
|
||||
#define EFUSE_OTP_STROBE_SW (BIT(6))
|
||||
#define EFUSE_OTP_STROBE_SW_M (BIT(6))
|
||||
#define EFUSE_OTP_STROBE_SW_V 0x1
|
||||
#define EFUSE_OTP_STROBE_SW_S 6
|
||||
/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: The value of OTP_VDDQ_C_SYNC2.*/
|
||||
#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5))
|
||||
#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5))
|
||||
#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1
|
||||
#define EFUSE_OTP_VDDQ_C_SYNC2_S 5
|
||||
/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: The value of OTP_LOAD_SW.*/
|
||||
#define EFUSE_OTP_LOAD_SW (BIT(4))
|
||||
#define EFUSE_OTP_LOAD_SW_M (BIT(4))
|
||||
#define EFUSE_OTP_LOAD_SW_V 0x1
|
||||
#define EFUSE_OTP_LOAD_SW_S 4
|
||||
/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */
|
||||
/*description: Indicates the state of the eFuse state machine.*/
|
||||
#define EFUSE_STATE 0x0000000F
|
||||
#define EFUSE_STATE_M ((EFUSE_STATE_V) << (EFUSE_STATE_S))
|
||||
#define EFUSE_STATE_V 0xF
|
||||
#define EFUSE_STATE_S 0
|
||||
|
||||
#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4)
|
||||
/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */
|
||||
/*description: The serial number of the block to be programmed. Value 0-10 corresponds
|
||||
to block number 0-10 respectively.*/
|
||||
#define EFUSE_BLK_NUM 0x0000000F
|
||||
#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V) << (EFUSE_BLK_NUM_S))
|
||||
#define EFUSE_BLK_NUM_V 0xF
|
||||
#define EFUSE_BLK_NUM_S 2
|
||||
/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to send programming command.*/
|
||||
#define EFUSE_PGM_CMD (BIT(1))
|
||||
#define EFUSE_PGM_CMD_M (BIT(1))
|
||||
#define EFUSE_PGM_CMD_V 0x1
|
||||
#define EFUSE_PGM_CMD_S 1
|
||||
/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to send read command.*/
|
||||
#define EFUSE_READ_CMD (BIT(0))
|
||||
#define EFUSE_READ_CMD_M (BIT(0))
|
||||
#define EFUSE_READ_CMD_V 0x1
|
||||
#define EFUSE_READ_CMD_S 0
|
||||
|
||||
#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8)
|
||||
/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The raw bit signal for pgm_done interrupt.*/
|
||||
#define EFUSE_PGM_DONE_INT_RAW (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_RAW_V 0x1
|
||||
#define EFUSE_PGM_DONE_INT_RAW_S 1
|
||||
/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The raw bit signal for read_done interrupt.*/
|
||||
#define EFUSE_READ_DONE_INT_RAW (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_RAW_M (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_RAW_V 0x1
|
||||
#define EFUSE_READ_DONE_INT_RAW_S 0
|
||||
|
||||
#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc)
|
||||
/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The status signal for pgm_done interrupt.*/
|
||||
#define EFUSE_PGM_DONE_INT_ST (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_ST_M (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_ST_V 0x1
|
||||
#define EFUSE_PGM_DONE_INT_ST_S 1
|
||||
/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The status signal for read_done interrupt.*/
|
||||
#define EFUSE_READ_DONE_INT_ST (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_ST_M (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_ST_V 0x1
|
||||
#define EFUSE_READ_DONE_INT_ST_S 0
|
||||
|
||||
#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0)
|
||||
/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The enable signal for pgm_done interrupt.*/
|
||||
#define EFUSE_PGM_DONE_INT_ENA (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_ENA_V 0x1
|
||||
#define EFUSE_PGM_DONE_INT_ENA_S 1
|
||||
/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The enable signal for read_done interrupt.*/
|
||||
#define EFUSE_READ_DONE_INT_ENA (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_ENA_M (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_ENA_V 0x1
|
||||
#define EFUSE_READ_DONE_INT_ENA_S 0
|
||||
|
||||
#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4)
|
||||
/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The clear signal for pgm_done interrupt.*/
|
||||
#define EFUSE_PGM_DONE_INT_CLR (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1))
|
||||
#define EFUSE_PGM_DONE_INT_CLR_V 0x1
|
||||
#define EFUSE_PGM_DONE_INT_CLR_S 1
|
||||
/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The clear signal for read_done interrupt.*/
|
||||
#define EFUSE_READ_DONE_INT_CLR (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_CLR_M (BIT(0))
|
||||
#define EFUSE_READ_DONE_INT_CLR_V 0x1
|
||||
#define EFUSE_READ_DONE_INT_CLR_S 0
|
||||
|
||||
#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8)
|
||||
/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */
|
||||
/*description: Reduces the power supply of the programming voltage.*/
|
||||
#define EFUSE_OE_CLR (BIT(17))
|
||||
#define EFUSE_OE_CLR_M (BIT(17))
|
||||
#define EFUSE_OE_CLR_V 0x1
|
||||
#define EFUSE_OE_CLR_S 17
|
||||
/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */
|
||||
/*description: Controls the rising period of the programming voltage.*/
|
||||
#define EFUSE_DAC_NUM 0x000000FF
|
||||
#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V) << (EFUSE_DAC_NUM_S))
|
||||
#define EFUSE_DAC_NUM_V 0xFF
|
||||
#define EFUSE_DAC_NUM_S 9
|
||||
/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Don't care.*/
|
||||
#define EFUSE_DAC_CLK_PAD_SEL (BIT(8))
|
||||
#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8))
|
||||
#define EFUSE_DAC_CLK_PAD_SEL_V 0x1
|
||||
#define EFUSE_DAC_CLK_PAD_SEL_S 8
|
||||
/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'h28 ; */
|
||||
/*description: Controls the division factor of the rising clock of the programming voltage.*/
|
||||
#define EFUSE_DAC_CLK_DIV 0x000000FF
|
||||
#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V) << (EFUSE_DAC_CLK_DIV_S))
|
||||
#define EFUSE_DAC_CLK_DIV_V 0xFF
|
||||
#define EFUSE_DAC_CLK_DIV_S 0
|
||||
|
||||
#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec)
|
||||
/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */
|
||||
/*description: Configures the initial read time of eFuse.*/
|
||||
#define EFUSE_READ_INIT_NUM 0x000000FF
|
||||
#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V) << (EFUSE_READ_INIT_NUM_S))
|
||||
#define EFUSE_READ_INIT_NUM_V 0xFF
|
||||
#define EFUSE_READ_INIT_NUM_S 24
|
||||
/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */
|
||||
/*description: Configures the setup time of read operation.*/
|
||||
#define EFUSE_TSUR_A 0x000000FF
|
||||
#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V) << (EFUSE_TSUR_A_S))
|
||||
#define EFUSE_TSUR_A_V 0xFF
|
||||
#define EFUSE_TSUR_A_S 16
|
||||
/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
|
||||
/*description: Configures the length of pulse of read operation.*/
|
||||
#define EFUSE_TRD 0x000000FF
|
||||
#define EFUSE_TRD_M ((EFUSE_TRD_V) << (EFUSE_TRD_S))
|
||||
#define EFUSE_TRD_V 0xFF
|
||||
#define EFUSE_TRD_S 8
|
||||
/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
|
||||
/*description: Configures the hold time of read operation.*/
|
||||
#define EFUSE_THR_A 0x000000FF
|
||||
#define EFUSE_THR_A_M ((EFUSE_THR_A_V) << (EFUSE_THR_A_S))
|
||||
#define EFUSE_THR_A_V 0xFF
|
||||
#define EFUSE_THR_A_S 0
|
||||
|
||||
#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0)
|
||||
/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */
|
||||
/*description: Configures the length of pulse during programming 1 to eFuse.*/
|
||||
#define EFUSE_TPGM 0x0000FFFF
|
||||
#define EFUSE_TPGM_M ((EFUSE_TPGM_V) << (EFUSE_TPGM_S))
|
||||
#define EFUSE_TPGM_V 0xFFFF
|
||||
#define EFUSE_TPGM_S 16
|
||||
/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */
|
||||
/*description: Configures the length of pulse during programming 0 to eFuse.*/
|
||||
#define EFUSE_TPGM_INACTIVE 0x000000FF
|
||||
#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V) << (EFUSE_TPGM_INACTIVE_S))
|
||||
#define EFUSE_TPGM_INACTIVE_V 0xFF
|
||||
#define EFUSE_TPGM_INACTIVE_S 8
|
||||
/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
|
||||
/*description: Configures the hold time of programming operation.*/
|
||||
#define EFUSE_THP_A 0x000000FF
|
||||
#define EFUSE_THP_A_M ((EFUSE_THP_A_V) << (EFUSE_THP_A_S))
|
||||
#define EFUSE_THP_A_V 0xFF
|
||||
#define EFUSE_THP_A_S 0
|
||||
|
||||
#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4)
|
||||
/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */
|
||||
/*description: Configures the power up time for VDDQ.*/
|
||||
#define EFUSE_PWR_ON_NUM 0x0000FFFF
|
||||
#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V) << (EFUSE_PWR_ON_NUM_S))
|
||||
#define EFUSE_PWR_ON_NUM_V 0xFFFF
|
||||
#define EFUSE_PWR_ON_NUM_S 8
|
||||
/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */
|
||||
/*description: Configures the setup time of programming operation.*/
|
||||
#define EFUSE_TSUP_A 0x000000FF
|
||||
#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V) << (EFUSE_TSUP_A_S))
|
||||
#define EFUSE_TSUP_A_V 0xFF
|
||||
#define EFUSE_TSUP_A_S 0
|
||||
|
||||
#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8)
|
||||
/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */
|
||||
/*description: Configures the power outage time for VDDQ.*/
|
||||
#define EFUSE_PWR_OFF_NUM 0x0000FFFF
|
||||
#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V) << (EFUSE_PWR_OFF_NUM_S))
|
||||
#define EFUSE_PWR_OFF_NUM_V 0xFFFF
|
||||
#define EFUSE_PWR_OFF_NUM_S 0
|
||||
|
||||
#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC)
|
||||
/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003310 ; */
|
||||
/*description: Stores eFuse version.*/
|
||||
#define EFUSE_DATE 0x0FFFFFFF
|
||||
#define EFUSE_DATE_M ((EFUSE_DATE_V) << (EFUSE_DATE_S))
|
||||
#define EFUSE_DATE_V 0xFFFFFFF
|
||||
#define EFUSE_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
294
components/soc/soc/esp32s3/include/soc/efuse_struct.h
Normal file
294
components/soc/soc/esp32s3/include/soc/efuse_struct.h
Normal file
|
|
@ -0,0 +1,294 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
uint32_t reserved_c;
|
||||
uint32_t reserved_10;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
uint32_t reserved_1c;
|
||||
uint32_t reserved_20;
|
||||
uint32_t reserved_24;
|
||||
uint32_t reserved_28;
|
||||
uint32_t reserved_2c;
|
||||
uint32_t reserved_30;
|
||||
uint32_t reserved_34;
|
||||
uint32_t reserved_38;
|
||||
uint32_t reserved_3c;
|
||||
uint32_t reserved_40;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rd_mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_key0_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_key1_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_key2_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_key3_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_key4_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rd_rs_err0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rd_key5_err_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
uint32_t rd_sys_part2_num: 3; /*The value of this signal means the number of error bytes.*/
|
||||
uint32_t rd_sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/
|
||||
uint32_t reserved8: 24; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rd_rs_err1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/
|
||||
uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/
|
||||
uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/
|
||||
uint32_t reserved3: 13; /*Reserved.*/
|
||||
uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/
|
||||
uint32_t reserved17: 15; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clk;
|
||||
union {
|
||||
struct {
|
||||
uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/
|
||||
uint32_t reserved16: 16; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/
|
||||
uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/
|
||||
uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/
|
||||
uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/
|
||||
uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/
|
||||
uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/
|
||||
uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/
|
||||
uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/
|
||||
uint32_t reserved18: 14; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t read_cmd: 1; /*Set this bit to send read command.*/
|
||||
uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/
|
||||
uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/
|
||||
uint32_t reserved6: 26; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/
|
||||
uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/
|
||||
uint32_t reserved2: 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t read_done: 1; /*The status signal for read_done interrupt.*/
|
||||
uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/
|
||||
uint32_t reserved2: 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/
|
||||
uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/
|
||||
uint32_t reserved2: 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/
|
||||
uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/
|
||||
uint32_t reserved2: 30; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/
|
||||
uint32_t dac_clk_pad_sel: 1; /*Don't care.*/
|
||||
uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/
|
||||
uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/
|
||||
uint32_t reserved18: 14; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dac_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thr_a: 8; /*Configures the hold time of read operation.*/
|
||||
uint32_t trd: 8; /*Configures the length of pulse of read operation.*/
|
||||
uint32_t tsur_a: 8; /*Configures the setup time of read operation.*/
|
||||
uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rd_tim_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thp_a: 8; /*Configures the hold time of programming operation.*/
|
||||
uint32_t tpgm_inactive: 8; /*Configures the length of pulse during programming 0 to eFuse.*/
|
||||
uint32_t tpgm: 16; /*Configures the length of pulse during programming 1 to eFuse.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} wr_tim_conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/
|
||||
uint32_t pwr_on_num: 16; /*Configures the power up time for VDDQ.*/
|
||||
uint32_t reserved24: 8; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} wr_tim_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pwr_off_num: 16; /*Configures the power outage time for VDDQ.*/
|
||||
uint32_t reserved16: 16; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} wr_tim_conf2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28; /*Stores eFuse version.*/
|
||||
uint32_t reserved28: 4; /*Reserved.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} efuse_dev_t;
|
||||
|
||||
extern efuse_dev_t EFUSE;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1609
components/soc/soc/esp32s3/include/soc/extmem_reg.h
Normal file
1609
components/soc/soc/esp32s3/include/soc/extmem_reg.h
Normal file
File diff suppressed because it is too large
Load diff
780
components/soc/soc/esp32s3/include/soc/extmem_struct.h
Normal file
780
components/soc/soc/esp32s3/include/soc/extmem_struct.h
Normal file
|
|
@ -0,0 +1,780 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_enable: 1; /*The bit is used to activate the data cache. 0: disable 1: enable*/
|
||||
uint32_t reserved1: 1; /*Reserved*/
|
||||
uint32_t dcache_size_mode: 1; /*The bit is used to configure cache memory size.0: 32KB 1: 64KB*/
|
||||
uint32_t dcache_blocksize_mode: 1; /*The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_shut_core0_bus: 1; /*The bit is used to disable core0 dbus 0: enable 1: disable*/
|
||||
uint32_t dcache_shut_core1_bus: 1; /*The bit is used to disable core1 dbus 0: enable 1: disable*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_tag_mem_force_on: 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating 0: open clock gating.*/
|
||||
uint32_t dcache_tag_mem_force_pd: 1; /*The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd 1: power down*/
|
||||
uint32_t dcache_tag_mem_force_pu: 1; /*The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd 1: power up*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_tag_power_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_prelock_sct0_en: 1; /*The bit is used to enable the first section of prelock function.*/
|
||||
uint32_t dcache_prelock_sct1_en: 1; /*The bit is used to enable the second section of prelock function.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_prelock_ctrl;
|
||||
uint32_t dcache_prelock_sct0_addr; /*The bits are used to configure the first start virtual address of data prelock which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG*/
|
||||
uint32_t dcache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/
|
||||
uint32_t dcache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_prelock_sct_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_lock_ena: 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
|
||||
uint32_t dcache_unlock_ena: 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
|
||||
uint32_t dcache_lock_done: 1; /*The bit is used to indicate unlock/lock operation is finished.*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_lock_ctrl;
|
||||
uint32_t dcache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_lock_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_invalidate_ena: 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
|
||||
uint32_t dcache_writeback_ena: 1; /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/
|
||||
uint32_t dcache_clean_ena: 1; /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/
|
||||
uint32_t dcache_sync_done: 1; /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_sync_ctrl;
|
||||
uint32_t dcache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_sync_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_occupy_ena: 1; /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/
|
||||
uint32_t dcache_occupy_done: 1; /*The bit is used to indicate occupy operation is finished.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_occupy_ctrl;
|
||||
uint32_t dcache_occupy_addr; /*The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_occupy_size: 16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_occupy_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_preload_ena: 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
|
||||
uint32_t dcache_preload_done: 1; /*The bit is used to indicate preload operation is finished.*/
|
||||
uint32_t dcache_preload_order: 1; /*The bit is used to configure the direction of preload operation. 1: descending 0: ascending.*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_preload_ctrl;
|
||||
uint32_t dcache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_preload_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/
|
||||
uint32_t dcache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/
|
||||
uint32_t dcache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/
|
||||
uint32_t dcache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/
|
||||
uint32_t dcache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
|
||||
uint32_t dcache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
|
||||
uint32_t dcache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_autoload_ctrl;
|
||||
uint32_t dcache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_autoload_sct0_size;
|
||||
uint32_t dcache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_autoload_sct1_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_enable: 1; /*The bit is used to activate the data cache. 0: disable 1: enable*/
|
||||
uint32_t icache_way_mode: 1; /*The bit is used to configure cache way mode.0: 4-way 1: 8-way*/
|
||||
uint32_t icache_size_mode: 1; /*The bit is used to configure cache memory size.0: 16KB 1: 32KB*/
|
||||
uint32_t icache_blocksize_mode: 1; /*The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_shut_core0_bus: 1; /*The bit is used to disable core0 ibus 0: enable 1: disable*/
|
||||
uint32_t icache_shut_core1_bus: 1; /*The bit is used to disable core1 ibus 0: enable 1: disable*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_tag_mem_force_on: 1; /*The bit is used to close clock gating of icache tag memory. 1: close gating 0: open clock gating.*/
|
||||
uint32_t icache_tag_mem_force_pd: 1; /*The bit is used to power icache tag memory down 0: follow rtc_lslp 1: power down*/
|
||||
uint32_t icache_tag_mem_force_pu: 1; /*The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_tag_power_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_prelock_sct0_en: 1; /*The bit is used to enable the first section of prelock function.*/
|
||||
uint32_t icache_prelock_sct1_en: 1; /*The bit is used to enable the second section of prelock function.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_prelock_ctrl;
|
||||
uint32_t icache_prelock_sct0_addr; /*The bits are used to configure the first start virtual address of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/
|
||||
uint32_t icache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/
|
||||
uint32_t icache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_prelock_sct_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_lock_ena: 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/
|
||||
uint32_t icache_unlock_ena: 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/
|
||||
uint32_t icache_lock_done: 1; /*The bit is used to indicate unlock/lock operation is finished.*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_lock_ctrl;
|
||||
uint32_t icache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_lock_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_invalidate_ena: 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/
|
||||
uint32_t icache_sync_done: 1; /*The bit is used to indicate invalidate operation is finished.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_sync_ctrl;
|
||||
uint32_t icache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_sync_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_preload_ena: 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/
|
||||
uint32_t icache_preload_done: 1; /*The bit is used to indicate preload operation is finished.*/
|
||||
uint32_t icache_preload_order: 1; /*The bit is used to configure the direction of preload operation. 1: descending 0: ascending.*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_preload_ctrl;
|
||||
uint32_t icache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_preload_size;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/
|
||||
uint32_t icache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/
|
||||
uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/
|
||||
uint32_t icache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/
|
||||
uint32_t icache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/
|
||||
uint32_t icache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/
|
||||
uint32_t icache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_autoload_ctrl;
|
||||
uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_autoload_sct0_size;
|
||||
uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_autoload_sct1_size;
|
||||
uint32_t ibus_to_flash_start_vaddr; /*The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.*/
|
||||
uint32_t ibus_to_flash_end_vaddr; /*The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.*/
|
||||
uint32_t dbus_to_flash_start_vaddr; /*The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.*/
|
||||
uint32_t dbus_to_flash_end_vaddr; /*The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_acs_cnt_clr: 1; /*The bit is used to clear dcache counter.*/
|
||||
uint32_t icache_acs_cnt_clr: 1; /*The bit is used to clear icache counter.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_acs_cnt_clr;
|
||||
uint32_t ibus_acs_miss_cnt; /*The bits are used to count the number of the cache miss caused by ibus access flash/spiram.*/
|
||||
uint32_t ibus_acs_cnt; /*The bits are used to count the number of ibus access flash/spiram through icache.*/
|
||||
uint32_t dbus_acs_flash_miss_cnt; /*The bits are used to count the number of the cache miss caused by dbus access flash.*/
|
||||
uint32_t dbus_acs_spiram_miss_cnt; /*The bits are used to count the number of the cache miss caused by dbus access spiram.*/
|
||||
uint32_t dbus_acs_cnt; /*The bits are used to count the number of dbus access flash/spiram through dcache.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_op_fault: 1; /*The bit is used to enable interrupt by sync configurations fault.*/
|
||||
uint32_t icache_preload_op_fault: 1; /*The bit is used to enable interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_sync_op_fault: 1; /*The bit is used to enable interrupt by sync configurations fault.*/
|
||||
uint32_t dcache_preload_op_fault: 1; /*The bit is used to enable interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_write_flash: 1; /*The bit is used to enable interrupt by dcache trying to write flash.*/
|
||||
uint32_t mmu_entry_fault: 1; /*The bit is used to enable interrupt by mmu entry fault.*/
|
||||
uint32_t dcache_occupy_exc: 1; /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
|
||||
uint32_t ibus_cnt_ovf: 1; /*The bit is used to enable interrupt by ibus counter overflow.*/
|
||||
uint32_t dbus_cnt_ovf: 1; /*The bit is used to enable interrupt by dbus counter overflow.*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_ilg_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_op_fault: 1; /*The bit is used to clear interrupt by sync configurations fault.*/
|
||||
uint32_t icache_preload_op_fault: 1; /*The bit is used to clear interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_sync_op_fault: 1; /*The bit is used to clear interrupt by sync configurations fault.*/
|
||||
uint32_t dcache_preload_op_fault: 1; /*The bit is used to clear interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_write_flash: 1; /*The bit is used to clear interrupt by dcache trying to write flash.*/
|
||||
uint32_t mmu_entry_fault: 1; /*The bit is used to clear interrupt by mmu entry fault.*/
|
||||
uint32_t dcache_occupy_exc: 1; /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
|
||||
uint32_t ibus_cnt_ovf: 1; /*The bit is used to clear interrupt by ibus counter overflow.*/
|
||||
uint32_t dbus_cnt_ovf: 1; /*The bit is used to clear interrupt by dbus counter overflow.*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_ilg_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync_op_fault_st: 1; /*The bit is used to indicate interrupt by sync configurations fault.*/
|
||||
uint32_t icache_preload_op_fault_st: 1; /*The bit is used to indicate interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_sync_op_fault_st: 1; /*The bit is used to indicate interrupt by sync configurations fault.*/
|
||||
uint32_t dcache_preload_op_fault_st: 1; /*The bit is used to indicate interrupt by preload configurations fault.*/
|
||||
uint32_t dcache_write_flash_st: 1; /*The bit is used to indicate interrupt by dcache trying to write flash.*/
|
||||
uint32_t mmu_entry_fault_st: 1; /*The bit is used to indicate interrupt by mmu entry fault.*/
|
||||
uint32_t dcache_occupy_exc_st: 1; /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/
|
||||
uint32_t ibus_acs_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/
|
||||
uint32_t ibus_acs_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/
|
||||
uint32_t dbus_acs_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/
|
||||
uint32_t dbus_acs_flash_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/
|
||||
uint32_t dbus_acs_spiram_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_ilg_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_acs_msk_ic: 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
|
||||
uint32_t core0_ibus_wr_ic: 1; /*The bit is used to enable interrupt by ibus trying to write icache*/
|
||||
uint32_t core0_ibus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t core0_dbus_acs_msk_dc: 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
|
||||
uint32_t core0_dbus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_acs_cache_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_acs_msk_ic: 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core0_ibus_wr_ic: 1; /*The bit is used to clear interrupt by ibus trying to write icache*/
|
||||
uint32_t core0_ibus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t core0_dbus_acs_msk_dc: 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core0_dbus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_acs_cache_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_acs_msk_icache_st: 1; /*The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core0_ibus_wr_icache_st: 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/
|
||||
uint32_t core0_ibus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t core0_dbus_acs_msk_dcache_st: 1; /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core0_dbus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_acs_cache_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_acs_msk_ic: 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/
|
||||
uint32_t core1_ibus_wr_ic: 1; /*The bit is used to enable interrupt by ibus trying to write icache*/
|
||||
uint32_t core1_ibus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t core1_dbus_acs_msk_dc: 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/
|
||||
uint32_t core1_dbus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_acs_cache_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_acs_msk_ic: 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core1_ibus_wr_ic: 1; /*The bit is used to clear interrupt by ibus trying to write icache*/
|
||||
uint32_t core1_ibus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t core1_dbus_acs_msk_dc: 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core1_dbus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_acs_cache_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_acs_msk_icache_st: 1; /*The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access.*/
|
||||
uint32_t core1_ibus_wr_icache_st: 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/
|
||||
uint32_t core1_ibus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t core1_dbus_acs_msk_dcache_st: 1; /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/
|
||||
uint32_t core1_dbus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_acs_cache_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_dbus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/
|
||||
uint32_t core0_dbus_attr: 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/
|
||||
uint32_t core0_dbus_world: 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0 1: WORLD1*/
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_dbus_reject_st;
|
||||
uint32_t core0_dbus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access dbus when authentication fail.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core0_ibus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/
|
||||
uint32_t core0_ibus_attr: 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate 1: execute-able 2: read-able*/
|
||||
uint32_t core0_ibus_world: 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0 1: WORLD1*/
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core0_ibus_reject_st;
|
||||
uint32_t core0_ibus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access ibus when authentication fail.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_dbus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/
|
||||
uint32_t core1_dbus_attr: 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/
|
||||
uint32_t core1_dbus_world: 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0 1: WORLD1*/
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_dbus_reject_st;
|
||||
uint32_t core1_dbus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access dbus when authentication fail.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t core1_ibus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/
|
||||
uint32_t core1_ibus_attr: 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate 1: execute-able 2: read-able*/
|
||||
uint32_t core1_ibus_world: 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0 1: WORLD1*/
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} core1_ibus_reject_st;
|
||||
uint32_t core1_ibus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access ibus when authentication fail.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_mmu_fault_content: 16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/
|
||||
uint32_t cache_mmu_fault_code: 4; /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_mmu_fault_content;
|
||||
uint32_t cache_mmu_fault_vaddr; /*The bits are used to indicate the virtual address which cause mmu fault..*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_flash_wrap_around: 1; /*The bit is used to enable wrap around mode when read data from flash.*/
|
||||
uint32_t cache_sram_rd_wrap_around: 1; /*The bit is used to enable wrap around mode when read data from spiram.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_wrap_around_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_mmu_mem_force_on: 1; /*The bit is used to enable clock gating to save power when access mmu memory 0: enable 1: disable*/
|
||||
uint32_t cache_mmu_mem_force_pd: 1; /*The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/
|
||||
uint32_t cache_mmu_mem_force_pu: 1; /*The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_mmu_power_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_state: 12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/
|
||||
uint32_t dcache_state: 12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t record_disable_db_encrypt: 1; /*Reserved.*/
|
||||
uint32_t record_disable_g0cb_decrypt: 1; /*Reserved.*/
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_encrypt_decrypt_record_disable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_force_on_manual_crypt: 1; /*The bit is used to close clock gating of manual crypt clock. 1: close gating 0: open clock gating.*/
|
||||
uint32_t clk_force_on_auto_crypt: 1; /*The bit is used to close clock gating of automatic crypt clock. 1: close gating 0: open clock gating.*/
|
||||
uint32_t clk_force_on_crypt: 1; /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating 0: open clock gating.*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_encrypt_decrypt_clk_force_on;
|
||||
union {
|
||||
struct {
|
||||
uint32_t alloc_wb_hold_arbiter: 1; /*Reserved.*/
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_bridge_arbiter_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_preload: 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/
|
||||
uint32_t icache_preload: 1; /*The bit is used to enable the interrupt by icache pre-load done.*/
|
||||
uint32_t icache_preload: 1; /*The bit is used to clear the interrupt by icache pre-load done.*/
|
||||
uint32_t dcache_preload: 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/
|
||||
uint32_t dcache_preload: 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/
|
||||
uint32_t dcache_preload: 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_preload_int_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_sync: 1; /*The bit is used to indicate the interrupt by icache sync done.*/
|
||||
uint32_t icache_sync: 1; /*The bit is used to enable the interrupt by icache sync done.*/
|
||||
uint32_t icache_sync: 1; /*The bit is used to clear the interrupt by icache sync done.*/
|
||||
uint32_t dcache_sync: 1; /*The bit is used to indicate the interrupt by dcache sync done.*/
|
||||
uint32_t dcache_sync: 1; /*The bit is used to enable the interrupt by dcache sync done.*/
|
||||
uint32_t dcache_sync: 1; /*The bit is used to clear the interrupt by dcache sync done.*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_sync_int_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_mmu_owner: 24; /*The bits are used to specify the owner of MMU.bit0: icache bit1: dcache bit2: dma bit3: reserved.*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_mmu_owner;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_ignore_preload_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by preload operation.*/
|
||||
uint32_t cache_ignore_sync_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by sync operation.*/
|
||||
uint32_t cache_trace_ena: 1; /*The bit is used to enable cache trace function.*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_conf_misc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_freeze_ena: 1; /*The bit is used to enable dcache freeze mode*/
|
||||
uint32_t dcache_freeze_mode: 1; /*The bit is used to configure freeze mode 0: assert busy if CPU miss 1: assert hit if CPU miss*/
|
||||
uint32_t dcache_freeze_done: 1; /*The bit is used to indicate dcache freeze success*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_freeze;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_freeze_ena: 1; /*The bit is used to enable icache freeze mode*/
|
||||
uint32_t icache_freeze_mode: 1; /*The bit is used to configure freeze mode 0: assert busy if CPU miss 1: assert hit if CPU miss*/
|
||||
uint32_t icache_freeze_done: 1; /*The bit is used to indicate icache freeze success*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_freeze;
|
||||
union {
|
||||
struct {
|
||||
uint32_t icache_atomic_operate_ena: 1; /*The bit is used to activate icache atomic operation protection. In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} icache_atomic_operate_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dcache_atomic_operate_ena: 1; /*The bit is used to activate dcache atomic operation protection. In this case sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} dcache_atomic_operate_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cache_request_bypass: 1; /*The bit is used to disable request recording which could cause performance issue*/
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_request;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1; /*Reserved.*/
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28; /*Reserved.*/
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} extmem_dev_t;
|
||||
|
||||
extern extmem_dev_t EXTMEM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
41
components/soc/soc/esp32s3/include/soc/fe_reg.h
Normal file
41
components/soc/soc/esp32s3/include/soc/fe_reg.h
Normal file
|
|
@ -0,0 +1,41 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
|
||||
/* Some of the RF frontend control registers.
|
||||
* PU/PD fields defined here are used in sleep related functions.
|
||||
*/
|
||||
|
||||
#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090)
|
||||
#define FE_IQ_EST_FORCE_PU (BIT(5))
|
||||
#define FE_IQ_EST_FORCE_PU_M (BIT(5))
|
||||
#define FE_IQ_EST_FORCE_PU_V 1
|
||||
#define FE_IQ_EST_FORCE_PU_S 5
|
||||
#define FE_IQ_EST_FORCE_PD (BIT(4))
|
||||
#define FE_IQ_EST_FORCE_PD_M (BIT(4))
|
||||
#define FE_IQ_EST_FORCE_PD_V 1
|
||||
#define FE_IQ_EST_FORCE_PD_S 4
|
||||
|
||||
#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0)
|
||||
#define FE2_TX_INF_FORCE_PU (BIT(10))
|
||||
#define FE2_TX_INF_FORCE_PU_M (BIT(10))
|
||||
#define FE2_TX_INF_FORCE_PU_V 1
|
||||
#define FE2_TX_INF_FORCE_PU_S 10
|
||||
#define FE2_TX_INF_FORCE_PD (BIT(9))
|
||||
#define FE2_TX_INF_FORCE_PD_M (BIT(9))
|
||||
#define FE2_TX_INF_FORCE_PD_V 1
|
||||
#define FE2_TX_INF_FORCE_PD_S 9
|
||||
45
components/soc/soc/esp32s3/include/soc/gpio_caps.h
Normal file
45
components/soc/soc/esp32s3/include/soc/gpio_caps.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// ESP32-S3 has 1 GPIO peripheral
|
||||
#define SOC_GPIO_PORT (1)
|
||||
#define GPIO_PIN_COUNT (48)
|
||||
|
||||
// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register.
|
||||
// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers.
|
||||
#define GPIO_SUPPORTS_RTC_INDEPENDENT (1)
|
||||
// Force hold is a new function of ESP32-S3
|
||||
#define GPIO_SUPPORTS_FORCE_HOLD (1)
|
||||
|
||||
#define GPIO_PRO_CPU_INTR_ENA (BIT(0))
|
||||
#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1))
|
||||
|
||||
#define GPIO_MODE_DEF_DISABLE (0)
|
||||
#define GPIO_MODE_DEF_INPUT (BIT0)
|
||||
#define GPIO_MODE_DEF_OUTPUT (BIT1)
|
||||
#define GPIO_MODE_DEF_OD (BIT2)
|
||||
|
||||
#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */
|
||||
#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */
|
||||
#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
9216
components/soc/soc/esp32s3/include/soc/gpio_reg.h
Normal file
9216
components/soc/soc/esp32s3/include/soc/gpio_reg.h
Normal file
File diff suppressed because it is too large
Load diff
166
components/soc/soc/esp32s3/include/soc/gpio_sd_reg.h
Normal file
166
components/soc/soc/esp32s3/include/soc/gpio_sd_reg.h
Normal file
|
|
@ -0,0 +1,166 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000)
|
||||
/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD0_PRESCALE 0x000000FF
|
||||
#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V) << (GPIO_SD0_PRESCALE_S))
|
||||
#define GPIO_SD0_PRESCALE_V 0xFF
|
||||
#define GPIO_SD0_PRESCALE_S 8
|
||||
/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD0_IN 0x000000FF
|
||||
#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V) << (GPIO_SD0_IN_S))
|
||||
#define GPIO_SD0_IN_V 0xFF
|
||||
#define GPIO_SD0_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004)
|
||||
/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD1_PRESCALE 0x000000FF
|
||||
#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V) << (GPIO_SD1_PRESCALE_S))
|
||||
#define GPIO_SD1_PRESCALE_V 0xFF
|
||||
#define GPIO_SD1_PRESCALE_S 8
|
||||
/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD1_IN 0x000000FF
|
||||
#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V) << (GPIO_SD1_IN_S))
|
||||
#define GPIO_SD1_IN_V 0xFF
|
||||
#define GPIO_SD1_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008)
|
||||
/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD2_PRESCALE 0x000000FF
|
||||
#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V) << (GPIO_SD2_PRESCALE_S))
|
||||
#define GPIO_SD2_PRESCALE_V 0xFF
|
||||
#define GPIO_SD2_PRESCALE_S 8
|
||||
/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD2_IN 0x000000FF
|
||||
#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V) << (GPIO_SD2_IN_S))
|
||||
#define GPIO_SD2_IN_V 0xFF
|
||||
#define GPIO_SD2_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c)
|
||||
/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD3_PRESCALE 0x000000FF
|
||||
#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V) << (GPIO_SD3_PRESCALE_S))
|
||||
#define GPIO_SD3_PRESCALE_V 0xFF
|
||||
#define GPIO_SD3_PRESCALE_S 8
|
||||
/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD3_IN 0x000000FF
|
||||
#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V) << (GPIO_SD3_IN_S))
|
||||
#define GPIO_SD3_IN_V 0xFF
|
||||
#define GPIO_SD3_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010)
|
||||
/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD4_PRESCALE 0x000000FF
|
||||
#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V) << (GPIO_SD4_PRESCALE_S))
|
||||
#define GPIO_SD4_PRESCALE_V 0xFF
|
||||
#define GPIO_SD4_PRESCALE_S 8
|
||||
/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD4_IN 0x000000FF
|
||||
#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V) << (GPIO_SD4_IN_S))
|
||||
#define GPIO_SD4_IN_V 0xFF
|
||||
#define GPIO_SD4_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014)
|
||||
/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD5_PRESCALE 0x000000FF
|
||||
#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V) << (GPIO_SD5_PRESCALE_S))
|
||||
#define GPIO_SD5_PRESCALE_V 0xFF
|
||||
#define GPIO_SD5_PRESCALE_S 8
|
||||
/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD5_IN 0x000000FF
|
||||
#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V) << (GPIO_SD5_IN_S))
|
||||
#define GPIO_SD5_IN_V 0xFF
|
||||
#define GPIO_SD5_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018)
|
||||
/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD6_PRESCALE 0x000000FF
|
||||
#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V) << (GPIO_SD6_PRESCALE_S))
|
||||
#define GPIO_SD6_PRESCALE_V 0xFF
|
||||
#define GPIO_SD6_PRESCALE_S 8
|
||||
/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD6_IN 0x000000FF
|
||||
#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V) << (GPIO_SD6_IN_S))
|
||||
#define GPIO_SD6_IN_V 0xFF
|
||||
#define GPIO_SD6_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c)
|
||||
/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */
|
||||
/*description: */
|
||||
#define GPIO_SD7_PRESCALE 0x000000FF
|
||||
#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V) << (GPIO_SD7_PRESCALE_S))
|
||||
#define GPIO_SD7_PRESCALE_V 0xFF
|
||||
#define GPIO_SD7_PRESCALE_S 8
|
||||
/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD7_IN 0x000000FF
|
||||
#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V) << (GPIO_SD7_IN_S))
|
||||
#define GPIO_SD7_IN_V 0xFF
|
||||
#define GPIO_SD7_IN_S 0
|
||||
|
||||
#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020)
|
||||
/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD_CLK_EN (BIT(31))
|
||||
#define GPIO_SD_CLK_EN_M (BIT(31))
|
||||
#define GPIO_SD_CLK_EN_V 0x1
|
||||
#define GPIO_SD_CLK_EN_S 31
|
||||
|
||||
#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024)
|
||||
/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define GPIO_SPI_SWAP (BIT(31))
|
||||
#define GPIO_SPI_SWAP_M (BIT(31))
|
||||
#define GPIO_SPI_SWAP_V 0x1
|
||||
#define GPIO_SPI_SWAP_S 31
|
||||
/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */
|
||||
/*description: */
|
||||
#define GPIO_FUNCTION_CLK_EN (BIT(30))
|
||||
#define GPIO_FUNCTION_CLK_EN_M (BIT(30))
|
||||
#define GPIO_FUNCTION_CLK_EN_V 0x1
|
||||
#define GPIO_FUNCTION_CLK_EN_S 30
|
||||
|
||||
#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028)
|
||||
/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */
|
||||
/*description: */
|
||||
#define GPIO_SD_DATE 0x0FFFFFFF
|
||||
#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V) << (GPIO_SD_DATE_S))
|
||||
#define GPIO_SD_DATE_V 0xFFFFFFF
|
||||
#define GPIO_SD_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
59
components/soc/soc/esp32s3/include/soc/gpio_sd_struct.h
Normal file
59
components/soc/soc/esp32s3/include/soc/gpio_sd_struct.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty: 8;
|
||||
uint32_t prescale: 8;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} channel[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} cg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 30;
|
||||
uint32_t function_clk_en: 1;
|
||||
uint32_t spi_swap: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} version;
|
||||
} gpio_sd_dev_t;
|
||||
|
||||
extern gpio_sd_dev_t SIGMADELTA;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
433
components/soc/soc/esp32s3/include/soc/gpio_sig_map.h
Normal file
433
components/soc/soc/esp32s3/include/soc/gpio_sig_map.h
Normal file
|
|
@ -0,0 +1,433 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#define SPIQ_IN_IDX 0
|
||||
#define SPIQ_OUT_IDX 0
|
||||
#define SPID_IN_IDX 1
|
||||
#define SPID_OUT_IDX 1
|
||||
#define SPIHD_IN_IDX 2
|
||||
#define SPIHD_OUT_IDX 2
|
||||
#define SPIWP_IN_IDX 3
|
||||
#define SPIWP_OUT_IDX 3
|
||||
#define SPICLK_OUT_IDX 4
|
||||
#define SPICS0_OUT_IDX 5
|
||||
#define SPICS1_OUT_IDX 6
|
||||
#define SPID4_IN_IDX 7
|
||||
#define SPID4_OUT_IDX 7
|
||||
#define SPID5_IN_IDX 8
|
||||
#define SPID5_OUT_IDX 8
|
||||
#define SPID6_IN_IDX 9
|
||||
#define SPID6_OUT_IDX 9
|
||||
#define SPID7_IN_IDX 10
|
||||
#define SPID7_OUT_IDX 10
|
||||
#define SPIDQS_IN_IDX 11
|
||||
#define SPIDQS_OUT_IDX 11
|
||||
#define U0RXD_IN_IDX 12
|
||||
#define U0TXD_OUT_IDX 12
|
||||
#define U0CTS_IN_IDX 13
|
||||
#define U0RTS_OUT_IDX 13
|
||||
#define U0DSR_IN_IDX 14
|
||||
#define U0DTR_OUT_IDX 14
|
||||
#define U1RXD_IN_IDX 15
|
||||
#define U1TXD_OUT_IDX 15
|
||||
#define U1CTS_IN_IDX 16
|
||||
#define U1RTS_OUT_IDX 16
|
||||
#define U1DSR_IN_IDX 17
|
||||
#define U1DTR_OUT_IDX 17
|
||||
#define U2RXD_IN_IDX 18
|
||||
#define U2TXD_OUT_IDX 18
|
||||
#define U2CTS_IN_IDX 19
|
||||
#define U2RTS_OUT_IDX 19
|
||||
#define U2DSR_IN_IDX 20
|
||||
#define U2DTR_OUT_IDX 20
|
||||
#define I2S1_MCLK_IN_IDX 21
|
||||
#define I2S1_MCLK_OUT_IDX 21
|
||||
#define I2S0O_BCK_IN_IDX 22
|
||||
#define I2S0O_BCK_OUT_IDX 22
|
||||
#define I2S0_MCLK_IN_IDX 23
|
||||
#define I2S0_MCLK_OUT_IDX 23
|
||||
#define I2S0O_WS_IN_IDX 24
|
||||
#define I2S0O_WS_OUT_IDX 24
|
||||
#define I2S0I_SD_IN_IDX 25
|
||||
#define I2S0O_SD_OUT_IDX 25
|
||||
#define I2S0I_BCK_IN_IDX 26
|
||||
#define I2S0I_BCK_OUT_IDX 26
|
||||
#define I2S0I_WS_IN_IDX 27
|
||||
#define I2S0I_WS_OUT_IDX 27
|
||||
#define I2S1O_BCK_IN_IDX 28
|
||||
#define I2S1O_BCK_OUT_IDX 28
|
||||
#define I2S1O_WS_IN_IDX 29
|
||||
#define I2S1O_WS_OUT_IDX 29
|
||||
#define I2S1I_SD_IN_IDX 30
|
||||
#define I2S1O_SD_OUT_IDX 30
|
||||
#define I2S1I_BCK_IN_IDX 31
|
||||
#define I2S1I_BCK_OUT_IDX 31
|
||||
#define I2S1I_WS_IN_IDX 32
|
||||
#define I2S1I_WS_OUT_IDX 32
|
||||
#define PCNT_SIG_CH0_IN0_IDX 33
|
||||
#define GPIO_WLAN_PRIO_IDX 33
|
||||
#define PCNT_SIG_CH1_IN0_IDX 34
|
||||
#define GPIO_WLAN_ACTIVE_IDX 34
|
||||
#define PCNT_CTRL_CH0_IN0_IDX 35
|
||||
#define BB_DIAG0_IDX 35
|
||||
#define PCNT_CTRL_CH1_IN0_IDX 36
|
||||
#define BB_DIAG1_IDX 36
|
||||
#define PCNT_SIG_CH0_IN1_IDX 37
|
||||
#define BB_DIAG2_IDX 37
|
||||
#define PCNT_SIG_CH1_IN1_IDX 38
|
||||
#define BB_DIAG3_IDX 38
|
||||
#define PCNT_CTRL_CH0_IN1_IDX 39
|
||||
#define BB_DIAG4_IDX 39
|
||||
#define PCNT_CTRL_CH1_IN1_IDX 40
|
||||
#define BB_DIAG5_IDX 40
|
||||
#define PCNT_SIG_CH0_IN2_IDX 41
|
||||
#define BB_DIAG6_IDX 41
|
||||
#define PCNT_SIG_CH1_IN2_IDX 42
|
||||
#define BB_DIAG7_IDX 42
|
||||
#define PCNT_CTRL_CH0_IN2_IDX 43
|
||||
#define BB_DIAG8_IDX 43
|
||||
#define PCNT_CTRL_CH1_IN2_IDX 44
|
||||
#define BB_DIAG9_IDX 44
|
||||
#define PCNT_SIG_CH0_IN3_IDX 45
|
||||
#define BB_DIAG10_IDX 45
|
||||
#define PCNT_SIG_CH1_IN3_IDX 46
|
||||
#define BB_DIAG11_IDX 46
|
||||
#define PCNT_CTRL_CH0_IN3_IDX 47
|
||||
#define BB_DIAG12_IDX 47
|
||||
#define PCNT_CTRL_CH1_IN3_IDX 48
|
||||
#define BB_DIAG13_IDX 48
|
||||
#define GPIO_BT_ACTIVE_IDX 49
|
||||
#define BB_DIAG14_IDX 49
|
||||
#define GPIO_BT_PRIORITY_IDX 50
|
||||
#define BB_DIAG15_IDX 50
|
||||
#define I2S0I_SD1_IN_IDX 51
|
||||
#define BB_DIAG16_IDX 51
|
||||
#define I2S0I_SD2_IN_IDX 52
|
||||
#define BB_DIAG17_IDX 52
|
||||
#define I2S0I_SD3_IN_IDX 53
|
||||
#define BB_DIAG18_IDX 53
|
||||
#define BB_DIAG19_IDX 54
|
||||
#define USB_EXTPHY_VP_IDX 55
|
||||
#define USB_EXTPHY_OEN_IDX 55
|
||||
#define USB_EXTPHY_VM_IDX 56
|
||||
#define USB_EXTPHY_SPEED_IDX 56
|
||||
#define USB_EXTPHY_RCV_IDX 57
|
||||
#define USB_EXTPHY_VPO_IDX 57
|
||||
#define USB_OTG_IDDIG_IN_IDX 58
|
||||
#define USB_EXTPHY_VMO_IDX 58
|
||||
#define USB_OTG_AVALID_IN_IDX 59
|
||||
#define USB_EXTPHY_SUSPND_IDX 59
|
||||
#define USB_SRP_BVALID_IN_IDX 60
|
||||
#define USB_OTG_IDPULLUP_IDX 60
|
||||
#define USB_OTG_VBUSVALID_IN_IDX 61
|
||||
#define USB_OTG_DPPULLDOWN_IDX 61
|
||||
#define USB_SRP_SESSEND_IN_IDX 62
|
||||
#define USB_OTG_DMPULLDOWN_IDX 62
|
||||
#define USB_OTG_DRVVBUS_IDX 63
|
||||
#define USB_SRP_CHRGVBUS_IDX 64
|
||||
#define USB_SRP_DISCHRGVBUS_IDX 65
|
||||
#define SPI3_CLK_IN_IDX 66
|
||||
#define SPI3_CLK_OUT_IDX 66
|
||||
#define SPI3_Q_IN_IDX 67
|
||||
#define SPI3_Q_OUT_IDX 67
|
||||
#define SPI3_D_IN_IDX 68
|
||||
#define SPI3_D_OUT_IDX 68
|
||||
#define SPI3_HD_IN_IDX 69
|
||||
#define SPI3_HD_OUT_IDX 69
|
||||
#define SPI3_WP_IN_IDX 70
|
||||
#define SPI3_WP_OUT_IDX 70
|
||||
#define SPI3_CS0_IN_IDX 71
|
||||
#define SPI3_CS0_OUT_IDX 71
|
||||
#define SPI3_CS1_OUT_IDX 72
|
||||
#define EXT_ADC_START_IDX 73
|
||||
#define LEDC_LS_SIG_OUT0_IDX 73
|
||||
#define LEDC_LS_SIG_OUT1_IDX 74
|
||||
#define LEDC_LS_SIG_OUT2_IDX 75
|
||||
#define LEDC_LS_SIG_OUT3_IDX 76
|
||||
#define LEDC_LS_SIG_OUT4_IDX 77
|
||||
#define LEDC_LS_SIG_OUT5_IDX 78
|
||||
#define LEDC_LS_SIG_OUT6_IDX 79
|
||||
#define LEDC_LS_SIG_OUT7_IDX 80
|
||||
#define RMT_SIG_IN0_IDX 81
|
||||
#define RMT_SIG_OUT0_IDX 81
|
||||
#define RMT_SIG_IN1_IDX 82
|
||||
#define RMT_SIG_OUT1_IDX 82
|
||||
#define RMT_SIG_IN2_IDX 83
|
||||
#define RMT_SIG_OUT2_IDX 83
|
||||
#define RMT_SIG_IN3_IDX 84
|
||||
#define RMT_SIG_OUT3_IDX 84
|
||||
#define I2CEXT0_SCL_IN_IDX 89
|
||||
#define I2CEXT0_SCL_OUT_IDX 89
|
||||
#define I2CEXT0_SDA_IN_IDX 90
|
||||
#define I2CEXT0_SDA_OUT_IDX 90
|
||||
#define I2CEXT1_SCL_IN_IDX 91
|
||||
#define I2CEXT1_SCL_OUT_IDX 91
|
||||
#define I2CEXT1_SDA_IN_IDX 92
|
||||
#define I2CEXT1_SDA_OUT_IDX 92
|
||||
#define GPIO_SD0_OUT_IDX 93
|
||||
#define GPIO_SD1_OUT_IDX 94
|
||||
#define GPIO_SD2_OUT_IDX 95
|
||||
#define GPIO_SD3_OUT_IDX 96
|
||||
#define GPIO_SD4_OUT_IDX 97
|
||||
#define GPIO_SD5_OUT_IDX 98
|
||||
#define GPIO_SD6_OUT_IDX 99
|
||||
#define GPIO_SD7_OUT_IDX 100
|
||||
#define FSPICLK_IN_IDX 101
|
||||
#define FSPICLK_OUT_IDX 101
|
||||
#define FSPIQ_IN_IDX 102
|
||||
#define FSPIQ_OUT_IDX 102
|
||||
#define FSPID_IN_IDX 103
|
||||
#define FSPID_OUT_IDX 103
|
||||
#define FSPIHD_IN_IDX 104
|
||||
#define FSPIHD_OUT_IDX 104
|
||||
#define FSPIWP_IN_IDX 105
|
||||
#define FSPIWP_OUT_IDX 105
|
||||
#define FSPIIO4_IN_IDX 106
|
||||
#define FSPIIO4_OUT_IDX 106
|
||||
#define FSPIIO5_IN_IDX 107
|
||||
#define FSPIIO5_OUT_IDX 107
|
||||
#define FSPIIO6_IN_IDX 108
|
||||
#define FSPIIO6_OUT_IDX 108
|
||||
#define FSPIIO7_IN_IDX 109
|
||||
#define FSPIIO7_OUT_IDX 109
|
||||
#define FSPICS0_IN_IDX 110
|
||||
#define FSPICS0_OUT_IDX 110
|
||||
#define FSPICS1_OUT_IDX 111
|
||||
#define FSPICS2_OUT_IDX 112
|
||||
#define FSPICS3_OUT_IDX 113
|
||||
#define FSPICS4_OUT_IDX 114
|
||||
#define FSPICS5_OUT_IDX 115
|
||||
#define TWAI_RX_IDX 116
|
||||
#define TWAI_TX_IDX 116
|
||||
#define TWAI_BUS_OFF_ON_IDX 117
|
||||
#define TWAI_CLKOUT_IDX 118
|
||||
#define SUBSPICLK_OUT_IDX 119
|
||||
#define SUBSPIQ_IN_IDX 120
|
||||
#define SUBSPIQ_OUT_IDX 120
|
||||
#define SUBSPID_IN_IDX 121
|
||||
#define SUBSPID_OUT_IDX 121
|
||||
#define SUBSPIHD_IN_IDX 122
|
||||
#define SUBSPIHD_OUT_IDX 122
|
||||
#define SUBSPIWP_IN_IDX 123
|
||||
#define SUBSPIWP_OUT_IDX 123
|
||||
#define SUBSPICS0_OUT_IDX 124
|
||||
#define SUBSPICS1_OUT_IDX 125
|
||||
#define FSPIDQS_OUT_IDX 126
|
||||
#define SPI3_CS2_OUT_IDX 127
|
||||
#define LCD_CS_IDX 132
|
||||
#define CAM_DATA_IN0_IDX 133
|
||||
#define LCD_DATA_OUT0_IDX 133
|
||||
#define CAM_DATA_IN1_IDX 134
|
||||
#define LCD_DATA_OUT1_IDX 134
|
||||
#define CAM_DATA_IN2_IDX 135
|
||||
#define LCD_DATA_OUT2_IDX 135
|
||||
#define CAM_DATA_IN3_IDX 136
|
||||
#define LCD_DATA_OUT3_IDX 136
|
||||
#define CAM_DATA_IN4_IDX 137
|
||||
#define LCD_DATA_OUT4_IDX 137
|
||||
#define CAM_DATA_IN5_IDX 138
|
||||
#define LCD_DATA_OUT5_IDX 138
|
||||
#define CAM_DATA_IN6_IDX 139
|
||||
#define LCD_DATA_OUT6_IDX 139
|
||||
#define CAM_DATA_IN7_IDX 140
|
||||
#define LCD_DATA_OUT7_IDX 140
|
||||
#define CAM_DATA_IN8_IDX 141
|
||||
#define LCD_DATA_OUT8_IDX 141
|
||||
#define CAM_DATA_IN9_IDX 142
|
||||
#define LCD_DATA_OUT9_IDX 142
|
||||
#define CAM_DATA_IN10_IDX 143
|
||||
#define LCD_DATA_OUT10_IDX 143
|
||||
#define CAM_DATA_IN11_IDX 144
|
||||
#define LCD_DATA_OUT11_IDX 144
|
||||
#define CAM_DATA_IN12_IDX 145
|
||||
#define LCD_DATA_OUT12_IDX 145
|
||||
#define CAM_DATA_IN13_IDX 146
|
||||
#define LCD_DATA_OUT13_IDX 146
|
||||
#define CAM_DATA_IN14_IDX 147
|
||||
#define LCD_DATA_OUT14_IDX 147
|
||||
#define CAM_DATA_IN15_IDX 148
|
||||
#define LCD_DATA_OUT15_IDX 148
|
||||
#define CAM_PCLK_IDX 149
|
||||
#define CAM_CLK_IDX 149
|
||||
#define CAM_H_ENABLE_IDX 150
|
||||
#define LCD_H_ENABLE_IDX 150
|
||||
#define CAM_H_SYNC_IDX 151
|
||||
#define LCD_H_SYNC_IDX 151
|
||||
#define CAM_V_SYNC_IDX 152
|
||||
#define LCD_V_SYNC_IDX 152
|
||||
#define LCD_DC_IDX 153
|
||||
#define LCD_PCLK_IDX 154
|
||||
#define SUBSPID4_IN_IDX 155
|
||||
#define SUBSPID4_OUT_IDX 155
|
||||
#define SUBSPID5_IN_IDX 156
|
||||
#define SUBSPID5_OUT_IDX 156
|
||||
#define SUBSPID6_IN_IDX 157
|
||||
#define SUBSPID6_OUT_IDX 157
|
||||
#define SUBSPID7_IN_IDX 158
|
||||
#define SUBSPID7_OUT_IDX 158
|
||||
#define SUBSPIDQS_IN_IDX 159
|
||||
#define SUBSPIDQS_OUT_IDX 159
|
||||
#define PWM0_SYNC0_IN_IDX 160
|
||||
#define PWM0_OUT0A_IDX 160
|
||||
#define PWM0_SYNC1_IN_IDX 161
|
||||
#define PWM0_OUT0B_IDX 161
|
||||
#define PWM0_SYNC2_IN_IDX 162
|
||||
#define PWM0_OUT1A_IDX 162
|
||||
#define PWM0_F0_IN_IDX 163
|
||||
#define PWM0_OUT1B_IDX 163
|
||||
#define PWM0_F1_IN_IDX 164
|
||||
#define PWM0_OUT2A_IDX 164
|
||||
#define PWM0_F2_IN_IDX 165
|
||||
#define PWM0_OUT2B_IDX 165
|
||||
#define PWM0_CAP0_IN_IDX 166
|
||||
#define PWM1_OUT0A_IDX 166
|
||||
#define PWM0_CAP1_IN_IDX 167
|
||||
#define PWM1_OUT0B_IDX 167
|
||||
#define PWM0_CAP2_IN_IDX 168
|
||||
#define PWM1_OUT1A_IDX 168
|
||||
#define PWM1_SYNC0_IN_IDX 169
|
||||
#define PWM1_OUT1B_IDX 169
|
||||
#define PWM1_SYNC1_IN_IDX 170
|
||||
#define PWM1_OUT2A_IDX 170
|
||||
#define PWM1_SYNC2_IN_IDX 171
|
||||
#define PWM1_OUT2B_IDX 171
|
||||
#define PWM1_F0_IN_IDX 172
|
||||
#define SDHOST_CCLK_OUT_1_IDX 172
|
||||
#define PWM1_F1_IN_IDX 173
|
||||
#define SDHOST_CCLK_OUT_2_IDX 173
|
||||
#define PWM1_F2_IN_IDX 174
|
||||
#define SDHOST_RST_N_1_IDX 174
|
||||
#define PWM1_CAP0_IN_IDX 175
|
||||
#define SDHOST_RST_N_2_IDX 175
|
||||
#define PWM1_CAP1_IN_IDX 176
|
||||
#define SDHOST_CCMD_OD_PULLUP_EN_N_IDX176
|
||||
#define PWM1_CAP2_IN_IDX 177
|
||||
#define SDIO_TOHOST_INT_OUT_IDX 177
|
||||
#define SDHOST_CCMD_IN_1_IDX 178
|
||||
#define SDHOST_CCMD_OUT_1_IDX 178
|
||||
#define SDHOST_CCMD_IN_2_IDX 179
|
||||
#define SDHOST_CCMD_OUT_2_IDX 179
|
||||
#define SDHOST_CDATA_IN_10_IDX 180
|
||||
#define SDHOST_CDATA_OUT_10_IDX 180
|
||||
#define SDHOST_CDATA_IN_11_IDX 181
|
||||
#define SDHOST_CDATA_OUT_11_IDX 181
|
||||
#define SDHOST_CDATA_IN_12_IDX 182
|
||||
#define SDHOST_CDATA_OUT_12_IDX 182
|
||||
#define SDHOST_CDATA_IN_13_IDX 183
|
||||
#define SDHOST_CDATA_OUT_13_IDX 183
|
||||
#define SDHOST_CDATA_IN_14_IDX 184
|
||||
#define SDHOST_CDATA_OUT_14_IDX 184
|
||||
#define SDHOST_CDATA_IN_15_IDX 185
|
||||
#define SDHOST_CDATA_OUT_15_IDX 185
|
||||
#define SDHOST_CDATA_IN_16_IDX 186
|
||||
#define SDHOST_CDATA_OUT_16_IDX 186
|
||||
#define SDHOST_CDATA_IN_17_IDX 187
|
||||
#define SDHOST_CDATA_OUT_17_IDX 187
|
||||
#define PCMFSYNC_IN_IDX 188
|
||||
#define BT_AUDIO0_IRQ_IDX 188
|
||||
#define PCMCLK_IN_IDX 189
|
||||
#define BT_AUDIO1_IRQ_IDX 189
|
||||
#define PCMDIN_IDX 190
|
||||
#define BT_AUDIO2_IRQ_IDX 190
|
||||
#define RW_WAKEUP_REQ_IDX 191
|
||||
#define BLE_AUDIO0_IRQ_IDX 191
|
||||
#define SDHOST_DATA_STROBE_1_IDX 192
|
||||
#define BLE_AUDIO1_IRQ_IDX 192
|
||||
#define SDHOST_DATA_STROBE_2_IDX 193
|
||||
#define BLE_AUDIO2_IRQ_IDX 193
|
||||
#define SDHOST_CARD_DETECT_N_1_IDX 194
|
||||
#define PCMFSYNC_OUT_IDX 194
|
||||
#define SDHOST_CARD_DETECT_N_2_IDX 195
|
||||
#define PCMCLK_OUT_IDX 195
|
||||
#define SDHOST_CARD_WRITE_PRT_1_IDX 196
|
||||
#define PCMDOUT_IDX 196
|
||||
#define SDHOST_CARD_WRITE_PRT_2_IDX 197
|
||||
#define BLE_AUDIO_SYNC0_P_IDX 197
|
||||
#define SDHOST_CARD_INT_N_1_IDX 198
|
||||
#define BLE_AUDIO_SYNC1_P_IDX 198
|
||||
#define SDHOST_CARD_INT_N_2_IDX 199
|
||||
#define BLE_AUDIO_SYNC2_P_IDX 199
|
||||
#define ANT_SEL0_IDX 200
|
||||
#define ANT_SEL1_IDX 201
|
||||
#define ANT_SEL2_IDX 202
|
||||
#define ANT_SEL3_IDX 203
|
||||
#define ANT_SEL4_IDX 204
|
||||
#define ANT_SEL5_IDX 205
|
||||
#define ANT_SEL6_IDX 206
|
||||
#define ANT_SEL7_IDX 207
|
||||
#define SIG_IN_FUNC_223_IDX 208
|
||||
#define SIG_IN_FUNC223_IDX 208
|
||||
#define SIG_IN_FUNC_224_IDX 209
|
||||
#define SIG_IN_FUNC224_IDX 209
|
||||
#define SIG_IN_FUNC_225_IDX 210
|
||||
#define SIG_IN_FUNC225_IDX 210
|
||||
#define SIG_IN_FUNC_226_IDX 211
|
||||
#define SIG_IN_FUNC226_IDX 211
|
||||
#define SIG_IN_FUNC_227_IDX 212
|
||||
#define SIG_IN_FUNC227_IDX 212
|
||||
#define SDHOST_CDATA_IN_20_IDX 213
|
||||
#define SDHOST_CDATA_OUT_20_IDX 213
|
||||
#define SDHOST_CDATA_IN_21_IDX 214
|
||||
#define SDHOST_CDATA_OUT_21_IDX 214
|
||||
#define SDHOST_CDATA_IN_22_IDX 215
|
||||
#define SDHOST_CDATA_OUT_22_IDX 215
|
||||
#define SDHOST_CDATA_IN_23_IDX 216
|
||||
#define SDHOST_CDATA_OUT_23_IDX 216
|
||||
#define SDHOST_CDATA_IN_24_IDX 217
|
||||
#define SDHOST_CDATA_OUT_24_IDX 217
|
||||
#define SDHOST_CDATA_IN_25_IDX 218
|
||||
#define SDHOST_CDATA_OUT_25_IDX 218
|
||||
#define SDHOST_CDATA_IN_26_IDX 219
|
||||
#define SDHOST_CDATA_OUT_26_IDX 219
|
||||
#define SDHOST_CDATA_IN_27_IDX 220
|
||||
#define SDHOST_CDATA_OUT_27_IDX 220
|
||||
#define PRO_ALONEGPIO_IN0_IDX 221
|
||||
#define PRO_ALONEGPIO_OUT0_IDX 221
|
||||
#define PRO_ALONEGPIO_IN1_IDX 222
|
||||
#define PRO_ALONEGPIO_OUT1_IDX 222
|
||||
#define PRO_ALONEGPIO_IN2_IDX 223
|
||||
#define PRO_ALONEGPIO_OUT2_IDX 223
|
||||
#define PRO_ALONEGPIO_IN3_IDX 224
|
||||
#define PRO_ALONEGPIO_OUT3_IDX 224
|
||||
#define PRO_ALONEGPIO_IN4_IDX 225
|
||||
#define PRO_ALONEGPIO_OUT4_IDX 225
|
||||
#define PRO_ALONEGPIO_IN5_IDX 226
|
||||
#define PRO_ALONEGPIO_OUT5_IDX 226
|
||||
#define PRO_ALONEGPIO_IN6_IDX 227
|
||||
#define PRO_ALONEGPIO_OUT6_IDX 227
|
||||
#define PRO_ALONEGPIO_IN7_IDX 228
|
||||
#define PRO_ALONEGPIO_OUT7_IDX 228
|
||||
#define SYNCERR_IDX 229
|
||||
#define SYNCFOUND_FLAG_IDX 230
|
||||
#define EVT_CNTL_IMMEDIATE_ABORT_IDX 231
|
||||
#define LINKLBL_IDX 232
|
||||
#define DATA_EN_IDX 233
|
||||
#define DATA_IDX 234
|
||||
#define PKT_TX_ON_IDX 235
|
||||
#define PKT_RX_ON_IDX 236
|
||||
#define RW_TX_ON_IDX 237
|
||||
#define RW_RX_ON_IDX 238
|
||||
#define EVT_REQ_P_IDX 239
|
||||
#define EVT_STOP_P_IDX 240
|
||||
#define BT_MODE_ON_IDX 241
|
||||
#define GPIO_LC_DIAG0_IDX 242
|
||||
#define GPIO_LC_DIAG1_IDX 243
|
||||
#define GPIO_LC_DIAG2_IDX 244
|
||||
#define CH_IDX_IDX 245
|
||||
#define RX_WINDOW_IDX 246
|
||||
#define UPDATE_RX_IDX 247
|
||||
#define RX_STATUS_IDX 248
|
||||
#define CLK_GPIO_IDX 249
|
||||
#define NBT_BLE_IDX 250
|
||||
254
components/soc/soc/esp32s3/include/soc/gpio_struct.h
Normal file
254
components/soc/soc/esp32s3/include/soc/gpio_struct.h
Normal file
|
|
@ -0,0 +1,254 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t bt_select; /**/
|
||||
uint32_t out; /**/
|
||||
uint32_t out_w1ts; /**/
|
||||
uint32_t out_w1tc; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} out1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} out1_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} out1_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_select;
|
||||
uint32_t enable; /**/
|
||||
uint32_t enable_w1ts; /**/
|
||||
uint32_t enable_w1tc; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable1_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} enable1_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t strapping: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} strap;
|
||||
uint32_t in; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t data: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} in1;
|
||||
uint32_t status; /**/
|
||||
uint32_t status_w1ts; /**/
|
||||
uint32_t status_w1tc; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status1_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status1_w1tc;
|
||||
uint32_t pcpu_int; /**/
|
||||
uint32_t pcpu_nmi_int; /**/
|
||||
uint32_t cpusdio_int; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcpu_int1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} pcpu_nmi_int1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpusdio_int1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sync2_bypass: 2;
|
||||
uint32_t pad_driver: 1;
|
||||
uint32_t sync1_bypass: 2;
|
||||
uint32_t reserved5: 2;
|
||||
uint32_t int_type: 3;
|
||||
uint32_t wakeup_enable: 1;
|
||||
uint32_t config: 2;
|
||||
uint32_t int_ena: 5;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} pin[54];
|
||||
uint32_t status_next; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t intr_st_next: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_next1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func_sel: 6;
|
||||
uint32_t sig_in_inv: 1;
|
||||
uint32_t sig_in_sel: 1;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} func_in_sel_cfg[256];
|
||||
union {
|
||||
struct {
|
||||
uint32_t func_sel: 9;
|
||||
uint32_t inv_sel: 1;
|
||||
uint32_t oen_sel: 1;
|
||||
uint32_t oen_inv_sel: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} func_out_sel_cfg[54];
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
uint32_t reserved_630;
|
||||
uint32_t reserved_634;
|
||||
uint32_t reserved_638;
|
||||
uint32_t reserved_63c;
|
||||
uint32_t reserved_640;
|
||||
uint32_t reserved_644;
|
||||
uint32_t reserved_648;
|
||||
uint32_t reserved_64c;
|
||||
uint32_t reserved_650;
|
||||
uint32_t reserved_654;
|
||||
uint32_t reserved_658;
|
||||
uint32_t reserved_65c;
|
||||
uint32_t reserved_660;
|
||||
uint32_t reserved_664;
|
||||
uint32_t reserved_668;
|
||||
uint32_t reserved_66c;
|
||||
uint32_t reserved_670;
|
||||
uint32_t reserved_674;
|
||||
uint32_t reserved_678;
|
||||
uint32_t reserved_67c;
|
||||
uint32_t reserved_680;
|
||||
uint32_t reserved_684;
|
||||
uint32_t reserved_688;
|
||||
uint32_t reserved_68c;
|
||||
uint32_t reserved_690;
|
||||
uint32_t reserved_694;
|
||||
uint32_t reserved_698;
|
||||
uint32_t reserved_69c;
|
||||
uint32_t reserved_6a0;
|
||||
uint32_t reserved_6a4;
|
||||
uint32_t reserved_6a8;
|
||||
uint32_t reserved_6ac;
|
||||
uint32_t reserved_6b0;
|
||||
uint32_t reserved_6b4;
|
||||
uint32_t reserved_6b8;
|
||||
uint32_t reserved_6bc;
|
||||
uint32_t reserved_6c0;
|
||||
uint32_t reserved_6c4;
|
||||
uint32_t reserved_6c8;
|
||||
uint32_t reserved_6cc;
|
||||
uint32_t reserved_6d0;
|
||||
uint32_t reserved_6d4;
|
||||
uint32_t reserved_6d8;
|
||||
uint32_t reserved_6dc;
|
||||
uint32_t reserved_6e0;
|
||||
uint32_t reserved_6e4;
|
||||
uint32_t reserved_6e8;
|
||||
uint32_t reserved_6ec;
|
||||
uint32_t reserved_6f0;
|
||||
uint32_t reserved_6f4;
|
||||
uint32_t reserved_6f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} gpio_dev_t;
|
||||
|
||||
extern gpio_dev_t GPIO;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
240
components/soc/soc/esp32s3/include/soc/hinf_reg.h
Normal file
240
components/soc/soc/esp32s3/include/soc/hinf_reg.h
Normal file
|
|
@ -0,0 +1,240 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0)
|
||||
/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */
|
||||
/*description: */
|
||||
#define HINF_DEVICE_ID_FN1 0x0000FFFF
|
||||
#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V) << (HINF_DEVICE_ID_FN1_S))
|
||||
#define HINF_DEVICE_ID_FN1_V 0xFFFF
|
||||
#define HINF_DEVICE_ID_FN1_S 16
|
||||
/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
|
||||
/*description: */
|
||||
#define HINF_USER_ID_FN1 0x0000FFFF
|
||||
#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V) << (HINF_USER_ID_FN1_S))
|
||||
#define HINF_USER_ID_FN1_V 0xFFFF
|
||||
#define HINF_USER_ID_FN1_S 0
|
||||
|
||||
#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4)
|
||||
/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO20_CONF1 0x00000007
|
||||
#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V) << (HINF_SDIO20_CONF1_S))
|
||||
#define HINF_SDIO20_CONF1_V 0x7
|
||||
#define HINF_SDIO20_CONF1_S 29
|
||||
/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_FUNC2_EPS (BIT(28))
|
||||
#define HINF_FUNC2_EPS_M (BIT(28))
|
||||
#define HINF_FUNC2_EPS_V 0x1
|
||||
#define HINF_FUNC2_EPS_S 28
|
||||
/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_VER 0x00000FFF
|
||||
#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V) << (HINF_SDIO_VER_S))
|
||||
#define HINF_SDIO_VER_V 0xFFF
|
||||
#define HINF_SDIO_VER_S 16
|
||||
/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO20_CONF0 0x0000000F
|
||||
#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V) << (HINF_SDIO20_CONF0_S))
|
||||
#define HINF_SDIO20_CONF0_V 0xF
|
||||
#define HINF_SDIO20_CONF0_S 12
|
||||
/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_IOENABLE1 (BIT(11))
|
||||
#define HINF_IOENABLE1_M (BIT(11))
|
||||
#define HINF_IOENABLE1_V 0x1
|
||||
#define HINF_IOENABLE1_S 11
|
||||
/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_EMP (BIT(10))
|
||||
#define HINF_EMP_M (BIT(10))
|
||||
#define HINF_EMP_V 0x1
|
||||
#define HINF_EMP_S 10
|
||||
/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_FUNC1_EPS (BIT(9))
|
||||
#define HINF_FUNC1_EPS_M (BIT(9))
|
||||
#define HINF_FUNC1_EPS_V 0x1
|
||||
#define HINF_FUNC1_EPS_S 9
|
||||
/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_CD_DISABLE (BIT(8))
|
||||
#define HINF_CD_DISABLE_M (BIT(8))
|
||||
#define HINF_CD_DISABLE_V 0x1
|
||||
#define HINF_CD_DISABLE_S 8
|
||||
/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_IOENABLE2 (BIT(7))
|
||||
#define HINF_IOENABLE2_M (BIT(7))
|
||||
#define HINF_IOENABLE2_V 0x1
|
||||
#define HINF_IOENABLE2_S 7
|
||||
/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_INT_MASK (BIT(6))
|
||||
#define HINF_SDIO_INT_MASK_M (BIT(6))
|
||||
#define HINF_SDIO_INT_MASK_V 0x1
|
||||
#define HINF_SDIO_INT_MASK_S 6
|
||||
/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_IOREADY2 (BIT(5))
|
||||
#define HINF_SDIO_IOREADY2_M (BIT(5))
|
||||
#define HINF_SDIO_IOREADY2_V 0x1
|
||||
#define HINF_SDIO_IOREADY2_S 5
|
||||
/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_CD_ENABLE (BIT(4))
|
||||
#define HINF_SDIO_CD_ENABLE_M (BIT(4))
|
||||
#define HINF_SDIO_CD_ENABLE_V 0x1
|
||||
#define HINF_SDIO_CD_ENABLE_S 4
|
||||
/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_HIGHSPEED_MODE (BIT(3))
|
||||
#define HINF_HIGHSPEED_MODE_M (BIT(3))
|
||||
#define HINF_HIGHSPEED_MODE_V 0x1
|
||||
#define HINF_HIGHSPEED_MODE_S 3
|
||||
/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_HIGHSPEED_ENABLE (BIT(2))
|
||||
#define HINF_HIGHSPEED_ENABLE_M (BIT(2))
|
||||
#define HINF_HIGHSPEED_ENABLE_V 0x1
|
||||
#define HINF_HIGHSPEED_ENABLE_S 2
|
||||
/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_IOREADY1 (BIT(1))
|
||||
#define HINF_SDIO_IOREADY1_M (BIT(1))
|
||||
#define HINF_SDIO_IOREADY1_V 0x1
|
||||
#define HINF_SDIO_IOREADY1_S 1
|
||||
/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_ENABLE (BIT(0))
|
||||
#define HINF_SDIO_ENABLE_M (BIT(0))
|
||||
#define HINF_SDIO_ENABLE_V 0x1
|
||||
#define HINF_SDIO_ENABLE_S 0
|
||||
|
||||
#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C)
|
||||
/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_IOREADY0 (BIT(17))
|
||||
#define HINF_SDIO_IOREADY0_M (BIT(17))
|
||||
#define HINF_SDIO_IOREADY0_V 0x1
|
||||
#define HINF_SDIO_IOREADY0_S 17
|
||||
/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_RST (BIT(16))
|
||||
#define HINF_SDIO_RST_M (BIT(16))
|
||||
#define HINF_SDIO_RST_V 0x1
|
||||
#define HINF_SDIO_RST_S 16
|
||||
/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_CHIP_STATE 0x000000FF
|
||||
#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V) << (HINF_CHIP_STATE_S))
|
||||
#define HINF_CHIP_STATE_V 0xFF
|
||||
#define HINF_CHIP_STATE_S 8
|
||||
/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */
|
||||
/*description: */
|
||||
#define HINF_PIN_STATE 0x000000FF
|
||||
#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V) << (HINF_PIN_STATE_S))
|
||||
#define HINF_PIN_STATE_V 0xFF
|
||||
#define HINF_PIN_STATE_S 0
|
||||
|
||||
#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20)
|
||||
/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W0 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V) << (HINF_CIS_CONF_W0_S))
|
||||
#define HINF_CIS_CONF_W0_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W0_S 0
|
||||
|
||||
#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24)
|
||||
/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W1 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V) << (HINF_CIS_CONF_W1_S))
|
||||
#define HINF_CIS_CONF_W1_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W1_S 0
|
||||
|
||||
#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28)
|
||||
/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W2 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V) << (HINF_CIS_CONF_W2_S))
|
||||
#define HINF_CIS_CONF_W2_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W2_S 0
|
||||
|
||||
#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C)
|
||||
/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W3 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V) << (HINF_CIS_CONF_W3_S))
|
||||
#define HINF_CIS_CONF_W3_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W3_S 0
|
||||
|
||||
#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30)
|
||||
/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W4 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V) << (HINF_CIS_CONF_W4_S))
|
||||
#define HINF_CIS_CONF_W4_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W4_S 0
|
||||
|
||||
#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34)
|
||||
/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W5 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V) << (HINF_CIS_CONF_W5_S))
|
||||
#define HINF_CIS_CONF_W5_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W5_S 0
|
||||
|
||||
#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38)
|
||||
/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W6 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V) << (HINF_CIS_CONF_W6_S))
|
||||
#define HINF_CIS_CONF_W6_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W6_S 0
|
||||
|
||||
#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C)
|
||||
/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */
|
||||
/*description: */
|
||||
#define HINF_CIS_CONF_W7 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V) << (HINF_CIS_CONF_W7_S))
|
||||
#define HINF_CIS_CONF_W7_V 0xFFFFFFFF
|
||||
#define HINF_CIS_CONF_W7_S 0
|
||||
|
||||
#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40)
|
||||
/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */
|
||||
/*description: */
|
||||
#define HINF_DEVICE_ID_FN2 0x0000FFFF
|
||||
#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V) << (HINF_DEVICE_ID_FN2_S))
|
||||
#define HINF_DEVICE_ID_FN2_V 0xFFFF
|
||||
#define HINF_DEVICE_ID_FN2_S 16
|
||||
/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */
|
||||
/*description: */
|
||||
#define HINF_USER_ID_FN2 0x0000FFFF
|
||||
#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V) << (HINF_USER_ID_FN2_S))
|
||||
#define HINF_USER_ID_FN2_V 0xFFFF
|
||||
#define HINF_USER_ID_FN2_S 0
|
||||
|
||||
#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC)
|
||||
/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */
|
||||
/*description: */
|
||||
#define HINF_SDIO_DATE 0xFFFFFFFF
|
||||
#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V) << (HINF_SDIO_DATE_S))
|
||||
#define HINF_SDIO_DATE_V 0xFFFFFFFF
|
||||
#define HINF_SDIO_DATE_S 0
|
||||
134
components/soc/soc/esp32s3/include/soc/hinf_struct.h
Normal file
134
components/soc/soc/esp32s3/include/soc/hinf_struct.h
Normal file
|
|
@ -0,0 +1,134 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t user_id_fn1: 16;
|
||||
uint32_t device_id_fn1: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_enable: 1;
|
||||
uint32_t sdio_ioready1: 1;
|
||||
uint32_t highspeed_enable: 1;
|
||||
uint32_t highspeed_mode: 1;
|
||||
uint32_t sdio_cd_enable: 1;
|
||||
uint32_t sdio_ioready2: 1;
|
||||
uint32_t sdio_int_mask: 1;
|
||||
uint32_t ioenable2: 1;
|
||||
uint32_t cd_disable: 1;
|
||||
uint32_t func1_eps: 1;
|
||||
uint32_t emp: 1;
|
||||
uint32_t ioenable1: 1;
|
||||
uint32_t sdio20_conf0: 4;
|
||||
uint32_t sdio_ver: 12;
|
||||
uint32_t func2_eps: 1;
|
||||
uint32_t sdio20_conf1: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data1;
|
||||
uint32_t reserved_8;
|
||||
uint32_t reserved_c;
|
||||
uint32_t reserved_10;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pin_state: 8;
|
||||
uint32_t chip_state: 8;
|
||||
uint32_t sdio_rst: 1;
|
||||
uint32_t sdio_ioready0: 1;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data7;
|
||||
uint32_t cis_conf0; /**/
|
||||
uint32_t cis_conf1; /**/
|
||||
uint32_t cis_conf2; /**/
|
||||
uint32_t cis_conf3; /**/
|
||||
uint32_t cis_conf4; /**/
|
||||
uint32_t cis_conf5; /**/
|
||||
uint32_t cis_conf6; /**/
|
||||
uint32_t cis_conf7; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t user_id_fn2: 16;
|
||||
uint32_t device_id_fn2: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} cfg_data16;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t date; /**/
|
||||
} hinf_dev_t;
|
||||
|
||||
extern hinf_dev_t HINF;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1798
components/soc/soc/esp32s3/include/soc/host_reg.h
Normal file
1798
components/soc/soc/esp32s3/include/soc/host_reg.h
Normal file
File diff suppressed because it is too large
Load diff
604
components/soc/soc/esp32s3/include/soc/host_struct.h
Normal file
604
components/soc/soc/esp32s3/include/soc/host_struct.h
Normal file
|
|
@ -0,0 +1,604 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
uint32_t reserved_c;
|
||||
uint32_t reserved_10;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
uint32_t reserved_1c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t func1_mdstat: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} func2_2;
|
||||
uint32_t reserved_24;
|
||||
uint32_t reserved_28;
|
||||
uint32_t reserved_2c;
|
||||
uint32_t reserved_30;
|
||||
uint32_t gpio_status0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_int1: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_status1;
|
||||
uint32_t gpio_in0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_in1: 22;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} gpio_in1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0: 12;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t reserved13: 3;
|
||||
uint32_t reg_token1: 12;
|
||||
uint32_t rx_pf_eof: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token_rdata;
|
||||
uint32_t slc0_pf; /**/
|
||||
uint32_t reserved_4c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_raw;
|
||||
uint32_t reserved_54;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st;
|
||||
uint32_t reserved_5c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len: 20;
|
||||
uint32_t reg_slc0_len_check: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len;
|
||||
union {
|
||||
struct {
|
||||
uint32_t state0: 8;
|
||||
uint32_t state1: 8;
|
||||
uint32_t state2: 8;
|
||||
uint32_t state3: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} state_w0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t state4: 8;
|
||||
uint32_t state5: 8;
|
||||
uint32_t state6: 8;
|
||||
uint32_t state7: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} state_w1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf0: 8;
|
||||
uint32_t conf1: 8;
|
||||
uint32_t conf2: 8;
|
||||
uint32_t conf3: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf4: 8;
|
||||
uint32_t conf5: 8;
|
||||
uint32_t conf6: 8;
|
||||
uint32_t conf7: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf8: 8;
|
||||
uint32_t conf9: 8;
|
||||
uint32_t conf10: 8;
|
||||
uint32_t conf11: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf12: 8;
|
||||
uint32_t conf13: 8;
|
||||
uint32_t conf14: 8;
|
||||
uint32_t conf15: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf16: 8; /*SLC timeout value*/
|
||||
uint32_t conf17: 8; /*SLC timeout enable*/
|
||||
uint32_t conf18: 8;
|
||||
uint32_t conf19: 8; /*Interrupt to target CPU*/
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf20: 8;
|
||||
uint32_t conf21: 8;
|
||||
uint32_t conf22: 8;
|
||||
uint32_t conf23: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w5;
|
||||
union {
|
||||
struct {
|
||||
uint32_t win_cmd: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} win_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf24: 8;
|
||||
uint32_t conf25: 8;
|
||||
uint32_t conf26: 8;
|
||||
uint32_t conf27: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w6;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf28: 8;
|
||||
uint32_t conf29: 8;
|
||||
uint32_t conf30: 8;
|
||||
uint32_t conf31: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w7;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len0: 20;
|
||||
uint32_t reg_slc0_len0_check: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len1: 20;
|
||||
uint32_t reg_slc0_len1_check: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reg_slc0_len2: 20;
|
||||
uint32_t reg_slc0_len2_check: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} pkt_len2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf32: 8;
|
||||
uint32_t conf33: 8;
|
||||
uint32_t conf34: 8;
|
||||
uint32_t conf35: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf36: 8;
|
||||
uint32_t conf37: 8;
|
||||
uint32_t conf38: 8;
|
||||
uint32_t conf39: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w9;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf40: 8;
|
||||
uint32_t conf41: 8;
|
||||
uint32_t conf42: 8;
|
||||
uint32_t conf43: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w10;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf44: 8;
|
||||
uint32_t conf45: 8;
|
||||
uint32_t conf46: 8;
|
||||
uint32_t conf47: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w11;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf48: 8;
|
||||
uint32_t conf49: 8;
|
||||
uint32_t conf50: 8;
|
||||
uint32_t conf51: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w12;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf52: 8;
|
||||
uint32_t conf53: 8;
|
||||
uint32_t conf54: 8;
|
||||
uint32_t conf55: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w13;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf56: 8;
|
||||
uint32_t conf57: 8;
|
||||
uint32_t conf58: 8;
|
||||
uint32_t conf59: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w14;
|
||||
union {
|
||||
struct {
|
||||
uint32_t conf60: 8;
|
||||
uint32_t conf61: 8;
|
||||
uint32_t conf62: 8;
|
||||
uint32_t conf63: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf_w15;
|
||||
uint32_t check_sum0; /**/
|
||||
uint32_t check_sum1; /**/
|
||||
uint32_t reserved_c4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t token0_wd: 12;
|
||||
uint32_t reserved12: 4;
|
||||
uint32_t token1_wd: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token_wdata;
|
||||
uint32_t reserved_cc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_token0_dec: 1;
|
||||
uint32_t slc0_token1_dec: 1;
|
||||
uint32_t slc0_token0_wr: 1;
|
||||
uint32_t slc0_token1_wr: 1;
|
||||
uint32_t reserved4: 4;
|
||||
uint32_t slc0_len_wr: 1;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} token_con;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_clr;
|
||||
uint32_t reserved_d8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_func1_int_ena;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit0: 1;
|
||||
uint32_t tohost_bit1: 1;
|
||||
uint32_t tohost_bit2: 1;
|
||||
uint32_t tohost_bit3: 1;
|
||||
uint32_t tohost_bit4: 1;
|
||||
uint32_t tohost_bit5: 1;
|
||||
uint32_t tohost_bit6: 1;
|
||||
uint32_t tohost_bit7: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t token0_0to1: 1;
|
||||
uint32_t token1_0to1: 1;
|
||||
uint32_t rx_sof: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t rx_pf_valid: 1;
|
||||
uint32_t ext_bit0: 1;
|
||||
uint32_t ext_bit1: 1;
|
||||
uint32_t ext_bit2: 1;
|
||||
uint32_t ext_bit3: 1;
|
||||
uint32_t rx_new_packet: 1;
|
||||
uint32_t rd_retry: 1;
|
||||
uint32_t gpio_sdio: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena;
|
||||
uint32_t reserved_f0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t infor: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rx_infor;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t slc0_len_wd; /**/
|
||||
uint32_t apbwin_wdata; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 28;
|
||||
uint32_t wr: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t bus: 1;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} apbwin_conf;
|
||||
uint32_t apbwin_rdata; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t bit7_clraddr: 9;
|
||||
uint32_t bit6_clraddr: 9;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rdclr;
|
||||
uint32_t reserved_110;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tohost_bit01: 1;
|
||||
uint32_t tohost_bit11: 1;
|
||||
uint32_t tohost_bit21: 1;
|
||||
uint32_t tohost_bit31: 1;
|
||||
uint32_t tohost_bit41: 1;
|
||||
uint32_t tohost_bit51: 1;
|
||||
uint32_t tohost_bit61: 1;
|
||||
uint32_t tohost_bit71: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t token0_0to11: 1;
|
||||
uint32_t token1_0to11: 1;
|
||||
uint32_t rx_sof1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t rx_pf_valid1: 1;
|
||||
uint32_t ext_bit01: 1;
|
||||
uint32_t ext_bit11: 1;
|
||||
uint32_t ext_bit21: 1;
|
||||
uint32_t ext_bit31: 1;
|
||||
uint32_t rx_new_packet1: 1;
|
||||
uint32_t rd_retry1: 1;
|
||||
uint32_t gpio_sdio1: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena1;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t date; /**/
|
||||
uint32_t id; /**/
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frc_sdio11: 5;
|
||||
uint32_t frc_sdio20: 5;
|
||||
uint32_t frc_neg_samp: 5;
|
||||
uint32_t frc_pos_samp: 5;
|
||||
uint32_t frc_quick_in: 5;
|
||||
uint32_t sdio20_int_delay: 1;
|
||||
uint32_t sdio_pad_pullup: 1;
|
||||
uint32_t hspeed_con_en: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio20_mode: 5;
|
||||
uint32_t sdio_neg_samp: 5;
|
||||
uint32_t sdio_quick_in: 5;
|
||||
uint32_t reserved15: 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} inf_st;
|
||||
} host_dev_t;
|
||||
|
||||
extern host_dev_t HOST;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
238
components/soc/soc/esp32s3/include/soc/hwcrypto_reg.h
Normal file
238
components/soc/soc/esp32s3/include/soc/hwcrypto_reg.h
Normal file
|
|
@ -0,0 +1,238 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/* registers for RSA acceleration via Multiple Precision Integer ops */
|
||||
#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000)
|
||||
/* RB & Z use the same memory block, depending on phase of operation */
|
||||
#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
|
||||
#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200)
|
||||
#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400)
|
||||
#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600)
|
||||
|
||||
/* Configuration registers */
|
||||
#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800)
|
||||
#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804)
|
||||
#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820)
|
||||
#define RSA_SEARCH_OPEN_REG (DR_REG_RSA_BASE + 0x824)
|
||||
#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828)
|
||||
|
||||
/* Initialization registers */
|
||||
#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808)
|
||||
|
||||
/* Calculation start registers */
|
||||
#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c)
|
||||
#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810)
|
||||
#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814)
|
||||
|
||||
/* Interrupt registers */
|
||||
#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818)
|
||||
#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C)
|
||||
#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C)
|
||||
|
||||
#define SHA_MODE_SHA1 0
|
||||
#define SHA_MODE_SHA224 1
|
||||
#define SHA_MODE_SHA256 2
|
||||
#define SHA_MODE_SHA384 3
|
||||
#define SHA_MODE_SHA512 4
|
||||
#define SHA_MODE_SHA512_224 5
|
||||
#define SHA_MODE_SHA512_256 6
|
||||
#define SHA_MODE_SHA512_T 7
|
||||
|
||||
/* SHA acceleration registers */
|
||||
#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00)
|
||||
#define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04)
|
||||
#define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08)
|
||||
#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C)
|
||||
#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10)
|
||||
#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14)
|
||||
#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18)
|
||||
#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C)
|
||||
#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20)
|
||||
#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24)
|
||||
#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28)
|
||||
|
||||
#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40)
|
||||
#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80)
|
||||
|
||||
/* AES Block operation modes */
|
||||
#define AES_BLOCK_MODE_ECB 0
|
||||
#define AES_BLOCK_MODE_CBC 1
|
||||
#define AES_BLOCK_MODE_OFB 2
|
||||
#define AES_BLOCK_MODE_CTR 3
|
||||
#define AES_BLOCK_MODE_CFB8 4
|
||||
#define AES_BLOCK_MODE_CFB128 5
|
||||
#define AES_BLOCK_MODE_GCM 6
|
||||
|
||||
/* AES Block operation modes (used with DMA) */
|
||||
#define AES_BLOCK_MODE_ECB 0
|
||||
#define AES_BLOCK_MODE_CBC 1
|
||||
#define AES_BLOCK_MODE_OFB 2
|
||||
#define AES_BLOCK_MODE_CTR 3
|
||||
#define AES_BLOCK_MODE_CFB8 4
|
||||
#define AES_BLOCK_MODE_CFB128 5
|
||||
#define AES_BLOCK_MODE_GCM 6
|
||||
|
||||
/* AES acceleration registers */
|
||||
#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40)
|
||||
#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44)
|
||||
#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48)
|
||||
#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c)
|
||||
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
|
||||
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
|
||||
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
|
||||
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
|
||||
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
|
||||
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
|
||||
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
|
||||
#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC)
|
||||
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
|
||||
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
|
||||
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
|
||||
|
||||
#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90)
|
||||
#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94)
|
||||
#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98)
|
||||
#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C)
|
||||
#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0)
|
||||
#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4)
|
||||
#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8)
|
||||
|
||||
#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00)
|
||||
#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20)
|
||||
#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30)
|
||||
#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50)
|
||||
#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60)
|
||||
#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70)
|
||||
#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80)
|
||||
|
||||
#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC)
|
||||
#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0)
|
||||
#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4)
|
||||
#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8)
|
||||
|
||||
/* AES_STATE_REG values */
|
||||
#define AES_STATE_IDLE 0
|
||||
#define AES_STATE_BUSY 1
|
||||
#define AES_STATE_DONE 2
|
||||
|
||||
|
||||
/* Crypto DMA */
|
||||
#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00)
|
||||
#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04)
|
||||
#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08)
|
||||
#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C)
|
||||
#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10)
|
||||
#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14)
|
||||
#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18)
|
||||
#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C)
|
||||
#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20)
|
||||
#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24)
|
||||
#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28)
|
||||
#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C)
|
||||
#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30)
|
||||
#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34)
|
||||
#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38)
|
||||
#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C)
|
||||
#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40)
|
||||
#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44)
|
||||
#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48)
|
||||
#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C)
|
||||
#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50)
|
||||
#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54)
|
||||
#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58)
|
||||
#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C)
|
||||
#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60)
|
||||
#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64)
|
||||
#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC)
|
||||
|
||||
/* HMAC Module */
|
||||
#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40)
|
||||
#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44)
|
||||
#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48)
|
||||
#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c)
|
||||
#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50)
|
||||
#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54)
|
||||
#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58)
|
||||
#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c)
|
||||
#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60)
|
||||
#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64)
|
||||
#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68)
|
||||
#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c)
|
||||
|
||||
#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80)
|
||||
#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0)
|
||||
#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0)
|
||||
#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4)
|
||||
|
||||
/* AES-XTS registers */
|
||||
#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x100)
|
||||
#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0x140)
|
||||
#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0x144)
|
||||
#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0x148)
|
||||
|
||||
#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0x14C)
|
||||
#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0x150)
|
||||
#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0x154)
|
||||
#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0x158)
|
||||
|
||||
/* Digital Signature registers*/
|
||||
#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 )
|
||||
#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 )
|
||||
#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 )
|
||||
#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 )
|
||||
|
||||
#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00)
|
||||
#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04)
|
||||
#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08)
|
||||
|
||||
#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C)
|
||||
#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10)
|
||||
#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14)
|
||||
|
||||
#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0)
|
||||
#define DS_QUERY_CHECK_INVALID_PADDING (1<<1)
|
||||
|
||||
#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20)
|
||||
|
||||
/* Crypto DMA */
|
||||
#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00)
|
||||
#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04)
|
||||
#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08)
|
||||
#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C)
|
||||
#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10)
|
||||
#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14)
|
||||
#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18)
|
||||
#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C)
|
||||
#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20)
|
||||
#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24)
|
||||
#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28)
|
||||
#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C)
|
||||
#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30)
|
||||
#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34)
|
||||
#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38)
|
||||
#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C)
|
||||
#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40)
|
||||
#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44)
|
||||
#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48)
|
||||
#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C)
|
||||
#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50)
|
||||
#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54)
|
||||
#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58)
|
||||
#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C)
|
||||
#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60)
|
||||
#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64)
|
||||
#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC)
|
||||
36
components/soc/soc/esp32s3/include/soc/i2c_caps.h
Normal file
36
components/soc/soc/esp32s3/include/soc/i2c_caps.h
Normal file
|
|
@ -0,0 +1,36 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// ESP32-S3 have 2 I2C.
|
||||
#define SOC_I2C_NUM (2)
|
||||
|
||||
#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */
|
||||
#define I2C_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */
|
||||
|
||||
//ESP32-S3 support hardware FSM reset
|
||||
#define I2C_SUPPORT_HW_FSM_RST (1)
|
||||
//ESP32-S3 support hardware clear bus
|
||||
#define I2C_SUPPORT_HW_CLR_BUS (1)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
|
||||
1070
components/soc/soc/esp32s3/include/soc/i2c_reg.h
Normal file
1070
components/soc/soc/esp32s3/include/soc/i2c_reg.h
Normal file
File diff suppressed because it is too large
Load diff
340
components/soc/soc/esp32s3/include/soc/i2c_struct.h
Normal file
340
components/soc/soc/esp32s3/include/soc/i2c_struct.h
Normal file
|
|
@ -0,0 +1,340 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_low_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_force_out: 1;
|
||||
uint32_t scl_force_out: 1;
|
||||
uint32_t sample_scl_level: 1;
|
||||
uint32_t ack_level: 1;
|
||||
uint32_t ms_mode: 1;
|
||||
uint32_t trans_start: 1;
|
||||
uint32_t tx_lsb_first: 1;
|
||||
uint32_t rx_lsb_first: 1;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t arbitration_en: 1;
|
||||
uint32_t fsm_rst: 1;
|
||||
uint32_t ref_always_on: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ack_rec: 1;
|
||||
uint32_t slave_rw: 1;
|
||||
uint32_t time_out: 1;
|
||||
uint32_t arb_lost: 1;
|
||||
uint32_t bus_busy: 1;
|
||||
uint32_t slave_addressed: 1;
|
||||
uint32_t byte_trans: 1;
|
||||
uint32_t reserved7: 1;
|
||||
uint32_t rx_fifo_cnt: 6;
|
||||
uint32_t reserved14: 4;
|
||||
uint32_t tx_fifo_cnt: 6;
|
||||
uint32_t scl_main_state_last: 3;
|
||||
uint32_t reserved27: 1;
|
||||
uint32_t scl_state_last: 3;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_reg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tout: 24;
|
||||
uint32_t time_out_en: 1;
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timeout;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 15;
|
||||
uint32_t reserved15: 16;
|
||||
uint32_t en_10bit: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slave_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_start_addr: 5;
|
||||
uint32_t rx_fifo_end_addr: 5;
|
||||
uint32_t tx_fifo_start_addr: 5;
|
||||
uint32_t tx_fifo_end_addr: 5;
|
||||
uint32_t rx_update: 1;
|
||||
uint32_t tx_update: 1;
|
||||
uint32_t tx_fifo_init_raddr: 5;
|
||||
uint32_t rx_fifo_init_waddr: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full_thrhd: 5;
|
||||
uint32_t tx_fifo_empty_thrhd: 5;
|
||||
uint32_t nonfifo_en: 1;
|
||||
uint32_t fifo_addr_cfg_en: 1;
|
||||
uint32_t rx_fifo_rst: 1;
|
||||
uint32_t tx_fifo_rst: 1;
|
||||
uint32_t nonfifo_rx_thres: 6;
|
||||
uint32_t nonfifo_tx_thres: 6;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_conf;
|
||||
union {
|
||||
struct {
|
||||
uint8_t data;
|
||||
uint8_t reserved[3];
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_data;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full: 1;
|
||||
uint32_t tx_fifo_empty: 1;
|
||||
uint32_t rx_fifo_ovf: 1;
|
||||
uint32_t end_detect: 1;
|
||||
uint32_t slave_tran_comp: 1;
|
||||
uint32_t arbitration_lost: 1;
|
||||
uint32_t master_tran_comp: 1;
|
||||
uint32_t trans_complete: 1;
|
||||
uint32_t time_out: 1;
|
||||
uint32_t trans_start: 1;
|
||||
uint32_t ack_err: 1;
|
||||
uint32_t rx_rec_full: 1;
|
||||
uint32_t tx_send_empty: 1;
|
||||
uint32_t scl_st_to: 1;
|
||||
uint32_t scl_main_st_to: 1;
|
||||
uint32_t det_start: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full: 1;
|
||||
uint32_t tx_fifo_empty: 1;
|
||||
uint32_t rx_fifo_ovf: 1;
|
||||
uint32_t end_detect: 1;
|
||||
uint32_t slave_tran_comp: 1;
|
||||
uint32_t arbitration_lost: 1;
|
||||
uint32_t master_tran_comp: 1;
|
||||
uint32_t trans_complete: 1;
|
||||
uint32_t time_out: 1;
|
||||
uint32_t trans_start: 1;
|
||||
uint32_t ack_err: 1;
|
||||
uint32_t rx_rec_full: 1;
|
||||
uint32_t tx_send_empty: 1;
|
||||
uint32_t scl_st_to: 1;
|
||||
uint32_t scl_main_st_to: 1;
|
||||
uint32_t det_start: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full: 1;
|
||||
uint32_t tx_fifo_empty: 1;
|
||||
uint32_t rx_fifo_ovf: 1;
|
||||
uint32_t end_detect: 1;
|
||||
uint32_t slave_tran_comp: 1;
|
||||
uint32_t arbitration_lost: 1;
|
||||
uint32_t master_tran_comp: 1;
|
||||
uint32_t trans_complete: 1;
|
||||
uint32_t time_out: 1;
|
||||
uint32_t trans_start: 1;
|
||||
uint32_t ack_err: 1;
|
||||
uint32_t rx_rec_full: 1;
|
||||
uint32_t tx_send_empty: 1;
|
||||
uint32_t scl_st_to: 1;
|
||||
uint32_t scl_main_st_to: 1;
|
||||
uint32_t det_start: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_fifo_full: 1;
|
||||
uint32_t tx_fifo_empty: 1;
|
||||
uint32_t rx_fifo_ovf: 1;
|
||||
uint32_t end_detect: 1;
|
||||
uint32_t slave_tran_comp: 1;
|
||||
uint32_t arbitration_lost: 1;
|
||||
uint32_t master_tran_comp: 1;
|
||||
uint32_t trans_complete: 1;
|
||||
uint32_t time_out: 1;
|
||||
uint32_t trans_start: 1;
|
||||
uint32_t ack_err: 1;
|
||||
uint32_t rx_rec_full: 1;
|
||||
uint32_t tx_send_empty: 1;
|
||||
uint32_t scl_st_to: 1;
|
||||
uint32_t scl_main_st_to: 1;
|
||||
uint32_t det_start: 1;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time: 10;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time: 10;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_sample;
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 14;
|
||||
uint32_t scl_wait_high_period: 14;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_high_period;
|
||||
uint32_t reserved_3c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time: 10;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_start_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time: 10;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_rstart_setup;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stop_hold;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time: 10;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stop_setup;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres: 3;
|
||||
uint32_t en: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_filter_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thres: 3;
|
||||
uint32_t en: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_filter_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
|
||||
uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
|
||||
uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
|
||||
uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
|
||||
uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
|
||||
uint32_t reserved14: 17;
|
||||
uint32_t done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} command[16];
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_st_to: 24;
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_st_time_out;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_main_st_to: 24;
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_main_st_time_out;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_rst_slv_en: 1;
|
||||
uint32_t scl_rst_slv_num: 5;
|
||||
uint32_t scl_pd_en: 1;
|
||||
uint32_t sda_pd_en: 1;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_sp_conf;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t date; /**/
|
||||
uint32_t reserved_fc;
|
||||
uint32_t ram_data[32]; /**/
|
||||
} i2c_dev_t;
|
||||
|
||||
extern i2c_dev_t I2C0;
|
||||
extern i2c_dev_t I2C1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
28
components/soc/soc/esp32s3/include/soc/i2s_caps.h
Normal file
28
components/soc/soc/esp32s3/include/soc/i2s_caps.h
Normal file
|
|
@ -0,0 +1,28 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define APLL_MIN_FREQ (250000000)
|
||||
#define APLL_MAX_FREQ (500000000)
|
||||
#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware
|
||||
#define I2S_AD_BCK_FACTOR (2)
|
||||
#define I2S_PDM_BCK_FACTOR (64)
|
||||
#define I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated
|
||||
#define I2S_BASE_CLK (2*APB_CLK_FREQ)
|
||||
|
||||
// ESP32-S3 have 1 I2S
|
||||
#define SOC_I2S_NUM (1)
|
||||
|
||||
#define SOC_I2S_SUPPORT_PDM (0) // ESP32-S3 do not support PDM
|
||||
971
components/soc/soc/esp32s3/include/soc/i2s_reg.h
Normal file
971
components/soc/soc/esp32s3/include/soc/i2s_reg.h
Normal file
|
|
@ -0,0 +1,971 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c)
|
||||
/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
#define I2S_TX_HUNG_INT_RAW (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_RAW_M (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_RAW_V 0x1
|
||||
#define I2S_TX_HUNG_INT_RAW_S 3
|
||||
/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
#define I2S_RX_HUNG_INT_RAW (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_RAW_M (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_RAW_V 0x1
|
||||
#define I2S_RX_HUNG_INT_RAW_S 2
|
||||
/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
#define I2S_TX_DONE_INT_RAW (BIT(1))
|
||||
#define I2S_TX_DONE_INT_RAW_M (BIT(1))
|
||||
#define I2S_TX_DONE_INT_RAW_V 0x1
|
||||
#define I2S_TX_DONE_INT_RAW_S 1
|
||||
/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The raw interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
#define I2S_RX_DONE_INT_RAW (BIT(0))
|
||||
#define I2S_RX_DONE_INT_RAW_M (BIT(0))
|
||||
#define I2S_RX_DONE_INT_RAW_V 0x1
|
||||
#define I2S_RX_DONE_INT_RAW_S 0
|
||||
|
||||
#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010)
|
||||
/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
#define I2S_TX_HUNG_INT_ST (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_ST_M (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_ST_V 0x1
|
||||
#define I2S_TX_HUNG_INT_ST_S 3
|
||||
/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
#define I2S_RX_HUNG_INT_ST (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_ST_M (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_ST_V 0x1
|
||||
#define I2S_RX_HUNG_INT_ST_S 2
|
||||
/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The masked interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
#define I2S_TX_DONE_INT_ST (BIT(1))
|
||||
#define I2S_TX_DONE_INT_ST_M (BIT(1))
|
||||
#define I2S_TX_DONE_INT_ST_V 0x1
|
||||
#define I2S_TX_DONE_INT_ST_S 1
|
||||
/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
#define I2S_RX_DONE_INT_ST (BIT(0))
|
||||
#define I2S_RX_DONE_INT_ST_M (BIT(0))
|
||||
#define I2S_RX_DONE_INT_ST_V 0x1
|
||||
#define I2S_RX_DONE_INT_ST_S 0
|
||||
|
||||
#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014)
|
||||
/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the i2s_tx_hung_int interrupt*/
|
||||
#define I2S_TX_HUNG_INT_ENA (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_ENA_M (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_ENA_V 0x1
|
||||
#define I2S_TX_HUNG_INT_ENA_S 3
|
||||
/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the i2s_rx_hung_int interrupt*/
|
||||
#define I2S_RX_HUNG_INT_ENA (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_ENA_M (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_ENA_V 0x1
|
||||
#define I2S_RX_HUNG_INT_ENA_S 2
|
||||
/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the i2s_tx_done_int interrupt*/
|
||||
#define I2S_TX_DONE_INT_ENA (BIT(1))
|
||||
#define I2S_TX_DONE_INT_ENA_M (BIT(1))
|
||||
#define I2S_TX_DONE_INT_ENA_V 0x1
|
||||
#define I2S_TX_DONE_INT_ENA_S 1
|
||||
/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The interrupt enable bit for the i2s_rx_done_int interrupt*/
|
||||
#define I2S_RX_DONE_INT_ENA (BIT(0))
|
||||
#define I2S_RX_DONE_INT_ENA_M (BIT(0))
|
||||
#define I2S_RX_DONE_INT_ENA_V 0x1
|
||||
#define I2S_RX_DONE_INT_ENA_S 0
|
||||
|
||||
#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018)
|
||||
/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/
|
||||
#define I2S_TX_HUNG_INT_CLR (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_CLR_M (BIT(3))
|
||||
#define I2S_TX_HUNG_INT_CLR_V 0x1
|
||||
#define I2S_TX_HUNG_INT_CLR_S 3
|
||||
/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/
|
||||
#define I2S_RX_HUNG_INT_CLR (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_CLR_M (BIT(2))
|
||||
#define I2S_RX_HUNG_INT_CLR_V 0x1
|
||||
#define I2S_RX_HUNG_INT_CLR_S 2
|
||||
/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the i2s_tx_done_int interrupt*/
|
||||
#define I2S_TX_DONE_INT_CLR (BIT(1))
|
||||
#define I2S_TX_DONE_INT_CLR_M (BIT(1))
|
||||
#define I2S_TX_DONE_INT_CLR_V 0x1
|
||||
#define I2S_TX_DONE_INT_CLR_S 1
|
||||
/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to clear the i2s_rx_done_int interrupt*/
|
||||
#define I2S_RX_DONE_INT_CLR (BIT(0))
|
||||
#define I2S_RX_DONE_INT_CLR_M (BIT(0))
|
||||
#define I2S_RX_DONE_INT_CLR_V 0x1
|
||||
#define I2S_RX_DONE_INT_CLR_S 0
|
||||
|
||||
#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020)
|
||||
/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(22))
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(22))
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1
|
||||
#define I2S_RX_PDM_SINC_DSR_16_EN_S 22
|
||||
/* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable PDM2PCM RX mode. 0: DIsable.*/
|
||||
#define I2S_RX_PDM2PCM_EN (BIT(21))
|
||||
#define I2S_RX_PDM2PCM_EN_M (BIT(21))
|
||||
#define I2S_RX_PDM2PCM_EN_V 0x1
|
||||
#define I2S_RX_PDM2PCM_EN_S 21
|
||||
/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/
|
||||
#define I2S_RX_PDM_EN (BIT(20))
|
||||
#define I2S_RX_PDM_EN_M (BIT(20))
|
||||
#define I2S_RX_PDM_EN_V 0x1
|
||||
#define I2S_RX_PDM_EN_S 20
|
||||
/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/
|
||||
#define I2S_RX_TDM_EN (BIT(19))
|
||||
#define I2S_RX_TDM_EN_M (BIT(19))
|
||||
#define I2S_RX_TDM_EN_V 0x1
|
||||
#define I2S_RX_TDM_EN_S 19
|
||||
/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
|
||||
/*description: I2S Rx bit endian. 1:small endian the LSB is received first.
|
||||
0:big endian the MSB is received first.*/
|
||||
#define I2S_RX_BIT_ORDER (BIT(18))
|
||||
#define I2S_RX_BIT_ORDER_M (BIT(18))
|
||||
#define I2S_RX_BIT_ORDER_V 0x1
|
||||
#define I2S_RX_BIT_ORDER_S 18
|
||||
/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
|
||||
/*description: 0: WS should be 0 when receiving left channel data and WS is
|
||||
1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/
|
||||
#define I2S_RX_WS_IDLE_POL (BIT(17))
|
||||
#define I2S_RX_WS_IDLE_POL_M (BIT(17))
|
||||
#define I2S_RX_WS_IDLE_POL_V 0x1
|
||||
#define I2S_RX_WS_IDLE_POL_S 17
|
||||
/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
|
||||
/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
|
||||
#define I2S_RX_24_FILL_EN (BIT(16))
|
||||
#define I2S_RX_24_FILL_EN_M (BIT(16))
|
||||
#define I2S_RX_24_FILL_EN_V 0x1
|
||||
#define I2S_RX_24_FILL_EN_S 16
|
||||
/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */
|
||||
/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
|
||||
#define I2S_RX_LEFT_ALIGN (BIT(15))
|
||||
#define I2S_RX_LEFT_ALIGN_M (BIT(15))
|
||||
#define I2S_RX_LEFT_ALIGN_V 0x1
|
||||
#define I2S_RX_LEFT_ALIGN_S 15
|
||||
/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */
|
||||
/*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop
|
||||
when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
|
||||
#define I2S_RX_STOP_MODE 0x00000003
|
||||
#define I2S_RX_STOP_MODE_M ((I2S_RX_STOP_MODE_V) << (I2S_RX_STOP_MODE_S))
|
||||
#define I2S_RX_STOP_MODE_V 0x3
|
||||
#define I2S_RX_STOP_MODE_S 13
|
||||
/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
|
||||
/*description: Set this bit to bypass Compress/Decompress module for received data.*/
|
||||
#define I2S_RX_PCM_BYPASS (BIT(12))
|
||||
#define I2S_RX_PCM_BYPASS_M (BIT(12))
|
||||
#define I2S_RX_PCM_BYPASS_V 0x1
|
||||
#define I2S_RX_PCM_BYPASS_S 12
|
||||
/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */
|
||||
/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law
|
||||
decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
|
||||
#define I2S_RX_PCM_CONF 0x00000003
|
||||
#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V) << (I2S_RX_PCM_CONF_S))
|
||||
#define I2S_RX_PCM_CONF_V 0x3
|
||||
#define I2S_RX_PCM_CONF_S 10
|
||||
/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: 1: The first channel data value is valid in I2S RX mono mode.
|
||||
0: The second channel data value is valid in I2S RX mono mode.*/
|
||||
#define I2S_RX_MONO_FST_VLD (BIT(9))
|
||||
#define I2S_RX_MONO_FST_VLD_M (BIT(9))
|
||||
#define I2S_RX_MONO_FST_VLD_V 0x1
|
||||
#define I2S_RX_MONO_FST_VLD_S 9
|
||||
/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Set 1 to update I2S RX registers from APB clock domain to I2S
|
||||
RX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
#define I2S_RX_UPDATE (BIT(8))
|
||||
#define I2S_RX_UPDATE_M (BIT(8))
|
||||
#define I2S_RX_UPDATE_V 0x1
|
||||
#define I2S_RX_UPDATE_S 8
|
||||
/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: I2S Rx byte endian 1: low addr value to high addr. 0: low addr
|
||||
with low addr value.*/
|
||||
#define I2S_RX_BIG_ENDIAN (BIT(7))
|
||||
#define I2S_RX_BIG_ENDIAN_M (BIT(7))
|
||||
#define I2S_RX_BIG_ENDIAN_V 0x1
|
||||
#define I2S_RX_BIG_ENDIAN_S 7
|
||||
/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable receiver in mono mode*/
|
||||
#define I2S_RX_MONO (BIT(5))
|
||||
#define I2S_RX_MONO_M (BIT(5))
|
||||
#define I2S_RX_MONO_V 0x1
|
||||
#define I2S_RX_MONO_S 5
|
||||
/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable slave receiver mode*/
|
||||
#define I2S_RX_SLAVE_MOD (BIT(3))
|
||||
#define I2S_RX_SLAVE_MOD_M (BIT(3))
|
||||
#define I2S_RX_SLAVE_MOD_V 0x1
|
||||
#define I2S_RX_SLAVE_MOD_S 3
|
||||
/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to start receiving data*/
|
||||
#define I2S_RX_START (BIT(2))
|
||||
#define I2S_RX_START_M (BIT(2))
|
||||
#define I2S_RX_START_V 0x1
|
||||
#define I2S_RX_START_S 2
|
||||
/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to reset Rx AFIFO*/
|
||||
#define I2S_RX_FIFO_RESET (BIT(1))
|
||||
#define I2S_RX_FIFO_RESET_M (BIT(1))
|
||||
#define I2S_RX_FIFO_RESET_V 0x1
|
||||
#define I2S_RX_FIFO_RESET_S 1
|
||||
/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to reset receiver*/
|
||||
#define I2S_RX_RESET (BIT(0))
|
||||
#define I2S_RX_RESET_M (BIT(0))
|
||||
#define I2S_RX_RESET_V 0x1
|
||||
#define I2S_RX_RESET_S 0
|
||||
|
||||
#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0024)
|
||||
/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: Enable signal loop back mode with transmitter module and receiver
|
||||
module sharing the same WS and BCK signals.*/
|
||||
#define I2S_SIG_LOOPBACK (BIT(27))
|
||||
#define I2S_SIG_LOOPBACK_M (BIT(27))
|
||||
#define I2S_SIG_LOOPBACK_V 0x1
|
||||
#define I2S_SIG_LOOPBACK_S 27
|
||||
/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */
|
||||
/*description: I2S transmitter channel mode configuration bits.*/
|
||||
#define I2S_TX_CHAN_MOD 0x00000007
|
||||
#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V) << (I2S_TX_CHAN_MOD_S))
|
||||
#define I2S_TX_CHAN_MOD_V 0x7
|
||||
#define I2S_TX_CHAN_MOD_S 24
|
||||
/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/
|
||||
#define I2S_TX_PDM_EN (BIT(20))
|
||||
#define I2S_TX_PDM_EN_M (BIT(20))
|
||||
#define I2S_TX_PDM_EN_V 0x1
|
||||
#define I2S_TX_PDM_EN_S 20
|
||||
/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/
|
||||
#define I2S_TX_TDM_EN (BIT(19))
|
||||
#define I2S_TX_TDM_EN_M (BIT(19))
|
||||
#define I2S_TX_TDM_EN_V 0x1
|
||||
#define I2S_TX_TDM_EN_S 19
|
||||
/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */
|
||||
/*description: I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big
|
||||
endian the MSB is sent first.*/
|
||||
#define I2S_TX_BIT_ORDER (BIT(18))
|
||||
#define I2S_TX_BIT_ORDER_M (BIT(18))
|
||||
#define I2S_TX_BIT_ORDER_V 0x1
|
||||
#define I2S_TX_BIT_ORDER_S 18
|
||||
/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */
|
||||
/*description: 0: WS should be 0 when sending left channel data and WS is 1in
|
||||
right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/
|
||||
#define I2S_TX_WS_IDLE_POL (BIT(17))
|
||||
#define I2S_TX_WS_IDLE_POL_M (BIT(17))
|
||||
#define I2S_TX_WS_IDLE_POL_V 0x1
|
||||
#define I2S_TX_WS_IDLE_POL_S 17
|
||||
/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */
|
||||
/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
|
||||
#define I2S_TX_24_FILL_EN (BIT(16))
|
||||
#define I2S_TX_24_FILL_EN_M (BIT(16))
|
||||
#define I2S_TX_24_FILL_EN_V 0x1
|
||||
#define I2S_TX_24_FILL_EN_S 16
|
||||
/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */
|
||||
/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
|
||||
#define I2S_TX_LEFT_ALIGN (BIT(15))
|
||||
#define I2S_TX_LEFT_ALIGN_M (BIT(15))
|
||||
#define I2S_TX_LEFT_ALIGN_V 0x1
|
||||
#define I2S_TX_LEFT_ALIGN_S 15
|
||||
/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
|
||||
/*description: Set this bit to stop disable output BCK signal and WS signal
|
||||
when tx FIFO is emtpy*/
|
||||
#define I2S_TX_STOP_EN (BIT(13))
|
||||
#define I2S_TX_STOP_EN_M (BIT(13))
|
||||
#define I2S_TX_STOP_EN_V 0x1
|
||||
#define I2S_TX_STOP_EN_S 13
|
||||
/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */
|
||||
/*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/
|
||||
#define I2S_TX_PCM_BYPASS (BIT(12))
|
||||
#define I2S_TX_PCM_BYPASS_M (BIT(12))
|
||||
#define I2S_TX_PCM_BYPASS_V 0x1
|
||||
#define I2S_TX_PCM_BYPASS_S 12
|
||||
/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
|
||||
/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law
|
||||
decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
|
||||
#define I2S_TX_PCM_CONF 0x00000003
|
||||
#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V) << (I2S_TX_PCM_CONF_S))
|
||||
#define I2S_TX_PCM_CONF_V 0x3
|
||||
#define I2S_TX_PCM_CONF_S 10
|
||||
/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */
|
||||
/*description: 1: The first channel data value is valid in I2S TX mono mode.
|
||||
0: The second channel data value is valid in I2S TX mono mode.*/
|
||||
#define I2S_TX_MONO_FST_VLD (BIT(9))
|
||||
#define I2S_TX_MONO_FST_VLD_M (BIT(9))
|
||||
#define I2S_TX_MONO_FST_VLD_V 0x1
|
||||
#define I2S_TX_MONO_FST_VLD_S 9
|
||||
/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: Set 1 to update I2S TX registers from APB clock domain to I2S
|
||||
TX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
#define I2S_TX_UPDATE (BIT(8))
|
||||
#define I2S_TX_UPDATE_M (BIT(8))
|
||||
#define I2S_TX_UPDATE_V 0x1
|
||||
#define I2S_TX_UPDATE_S 8
|
||||
/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: I2S Tx byte endian 1: low addr value to high addr. 0: low addr
|
||||
with low addr value.*/
|
||||
#define I2S_TX_BIG_ENDIAN (BIT(7))
|
||||
#define I2S_TX_BIG_ENDIAN_M (BIT(7))
|
||||
#define I2S_TX_BIG_ENDIAN_V 0x1
|
||||
#define I2S_TX_BIG_ENDIAN_S 7
|
||||
/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: 1: The value of Left channel data is equal to the value of right
|
||||
channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
|
||||
#define I2S_TX_CHAN_EQUAL (BIT(6))
|
||||
#define I2S_TX_CHAN_EQUAL_M (BIT(6))
|
||||
#define I2S_TX_CHAN_EQUAL_V 0x1
|
||||
#define I2S_TX_CHAN_EQUAL_S 6
|
||||
/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable transmitter in mono mode*/
|
||||
#define I2S_TX_MONO (BIT(5))
|
||||
#define I2S_TX_MONO_M (BIT(5))
|
||||
#define I2S_TX_MONO_V 0x1
|
||||
#define I2S_TX_MONO_S 5
|
||||
/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable slave transmitter mode*/
|
||||
#define I2S_TX_SLAVE_MOD (BIT(3))
|
||||
#define I2S_TX_SLAVE_MOD_M (BIT(3))
|
||||
#define I2S_TX_SLAVE_MOD_V 0x1
|
||||
#define I2S_TX_SLAVE_MOD_S 3
|
||||
/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to start transmitting data*/
|
||||
#define I2S_TX_START (BIT(2))
|
||||
#define I2S_TX_START_M (BIT(2))
|
||||
#define I2S_TX_START_V 0x1
|
||||
#define I2S_TX_START_S 2
|
||||
/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to reset Tx AFIFO*/
|
||||
#define I2S_TX_FIFO_RESET (BIT(1))
|
||||
#define I2S_TX_FIFO_RESET_M (BIT(1))
|
||||
#define I2S_TX_FIFO_RESET_V 0x1
|
||||
#define I2S_TX_FIFO_RESET_S 1
|
||||
/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to reset transmitter*/
|
||||
#define I2S_TX_RESET (BIT(0))
|
||||
#define I2S_TX_RESET_M (BIT(0))
|
||||
#define I2S_TX_RESET_V 0x1
|
||||
#define I2S_TX_RESET_S 0
|
||||
|
||||
#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0028)
|
||||
/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
|
||||
/*description: Set this bit to enable receiver in Phillips standard mode*/
|
||||
#define I2S_RX_MSB_SHIFT (BIT(29))
|
||||
#define I2S_RX_MSB_SHIFT_M (BIT(29))
|
||||
#define I2S_RX_MSB_SHIFT_V 0x1
|
||||
#define I2S_RX_MSB_SHIFT_S 29
|
||||
/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
|
||||
/*description: The Rx bit number for each channel minus 1in TDM mode.*/
|
||||
#define I2S_RX_TDM_CHAN_BITS 0x0000001F
|
||||
#define I2S_RX_TDM_CHAN_BITS_M ((I2S_RX_TDM_CHAN_BITS_V) << (I2S_RX_TDM_CHAN_BITS_S))
|
||||
#define I2S_RX_TDM_CHAN_BITS_V 0x1F
|
||||
#define I2S_RX_TDM_CHAN_BITS_S 24
|
||||
/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
|
||||
/*description: I2S Rx half sample bits -1.*/
|
||||
#define I2S_RX_HALF_SAMPLE_BITS 0x0000003F
|
||||
#define I2S_RX_HALF_SAMPLE_BITS_M ((I2S_RX_HALF_SAMPLE_BITS_V) << (I2S_RX_HALF_SAMPLE_BITS_S))
|
||||
#define I2S_RX_HALF_SAMPLE_BITS_V 0x3F
|
||||
#define I2S_RX_HALF_SAMPLE_BITS_S 18
|
||||
/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
|
||||
/*description: Set the bits to configure bit length of I2S receiver channel.*/
|
||||
#define I2S_RX_BITS_MOD 0x0000001F
|
||||
#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V) << (I2S_RX_BITS_MOD_S))
|
||||
#define I2S_RX_BITS_MOD_V 0x1F
|
||||
#define I2S_RX_BITS_MOD_S 13
|
||||
/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
|
||||
/*description: Bit clock configuration bits in receiver mode.*/
|
||||
#define I2S_RX_BCK_DIV_NUM 0x0000003F
|
||||
#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V) << (I2S_RX_BCK_DIV_NUM_S))
|
||||
#define I2S_RX_BCK_DIV_NUM_V 0x3F
|
||||
#define I2S_RX_BCK_DIV_NUM_S 7
|
||||
/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
|
||||
/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
|
||||
#define I2S_RX_TDM_WS_WIDTH 0x0000007F
|
||||
#define I2S_RX_TDM_WS_WIDTH_M ((I2S_RX_TDM_WS_WIDTH_V) << (I2S_RX_TDM_WS_WIDTH_S))
|
||||
#define I2S_RX_TDM_WS_WIDTH_V 0x7F
|
||||
#define I2S_RX_TDM_WS_WIDTH_S 0
|
||||
|
||||
#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x002C)
|
||||
/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */
|
||||
/*description: Set this bit to enable transmitter in Phillips standard mode*/
|
||||
#define I2S_TX_MSB_SHIFT (BIT(29))
|
||||
#define I2S_TX_MSB_SHIFT_M (BIT(29))
|
||||
#define I2S_TX_MSB_SHIFT_V 0x1
|
||||
#define I2S_TX_MSB_SHIFT_S 29
|
||||
/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */
|
||||
/*description: The Tx bit number for each channel minus 1in TDM mode.*/
|
||||
#define I2S_TX_TDM_CHAN_BITS 0x0000001F
|
||||
#define I2S_TX_TDM_CHAN_BITS_M ((I2S_TX_TDM_CHAN_BITS_V) << (I2S_TX_TDM_CHAN_BITS_S))
|
||||
#define I2S_TX_TDM_CHAN_BITS_V 0x1F
|
||||
#define I2S_TX_TDM_CHAN_BITS_S 24
|
||||
/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */
|
||||
/*description: I2S Tx half sample bits -1.*/
|
||||
#define I2S_TX_HALF_SAMPLE_BITS 0x0000003F
|
||||
#define I2S_TX_HALF_SAMPLE_BITS_M ((I2S_TX_HALF_SAMPLE_BITS_V) << (I2S_TX_HALF_SAMPLE_BITS_S))
|
||||
#define I2S_TX_HALF_SAMPLE_BITS_V 0x3F
|
||||
#define I2S_TX_HALF_SAMPLE_BITS_S 18
|
||||
/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */
|
||||
/*description: Set the bits to configure bit length of I2S transmitter channel.*/
|
||||
#define I2S_TX_BITS_MOD 0x0000001F
|
||||
#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V) << (I2S_TX_BITS_MOD_S))
|
||||
#define I2S_TX_BITS_MOD_V 0x1F
|
||||
#define I2S_TX_BITS_MOD_S 13
|
||||
/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */
|
||||
/*description: Bit clock configuration bits in transmitter mode.*/
|
||||
#define I2S_TX_BCK_DIV_NUM 0x0000003F
|
||||
#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V) << (I2S_TX_BCK_DIV_NUM_S))
|
||||
#define I2S_TX_BCK_DIV_NUM_V 0x3F
|
||||
#define I2S_TX_BCK_DIV_NUM_S 7
|
||||
/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */
|
||||
/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
|
||||
#define I2S_TX_TDM_WS_WIDTH 0x0000007F
|
||||
#define I2S_TX_TDM_WS_WIDTH_M ((I2S_TX_TDM_WS_WIDTH_V) << (I2S_TX_TDM_WS_WIDTH_S))
|
||||
#define I2S_TX_TDM_WS_WIDTH_V 0x7F
|
||||
#define I2S_TX_TDM_WS_WIDTH_S 0
|
||||
|
||||
#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0030)
|
||||
/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module
|
||||
clock as I2S_MCLK_OUT.*/
|
||||
#define I2S_MCLK_SEL (BIT(29))
|
||||
#define I2S_MCLK_SEL_M (BIT(29))
|
||||
#define I2S_MCLK_SEL_V 0x1
|
||||
#define I2S_MCLK_SEL_S 29
|
||||
/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
|
||||
/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160.
|
||||
3: I2S_MCLK_in.*/
|
||||
#define I2S_RX_CLK_SEL 0x00000003
|
||||
#define I2S_RX_CLK_SEL_M ((I2S_RX_CLK_SEL_V) << (I2S_RX_CLK_SEL_S))
|
||||
#define I2S_RX_CLK_SEL_V 0x3
|
||||
#define I2S_RX_CLK_SEL_S 27
|
||||
/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: I2S Rx module clock enable signal.*/
|
||||
#define I2S_RX_CLK_ACTIVE (BIT(26))
|
||||
#define I2S_RX_CLK_ACTIVE_M (BIT(26))
|
||||
#define I2S_RX_CLK_ACTIVE_V 0x1
|
||||
#define I2S_RX_CLK_ACTIVE_S 26
|
||||
/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
|
||||
/*description: Integral I2S clock divider value*/
|
||||
#define I2S_RX_CLKM_DIV_NUM 0x000000FF
|
||||
#define I2S_RX_CLKM_DIV_NUM_M ((I2S_RX_CLKM_DIV_NUM_V) << (I2S_RX_CLKM_DIV_NUM_S))
|
||||
#define I2S_RX_CLKM_DIV_NUM_V 0xFF
|
||||
#define I2S_RX_CLKM_DIV_NUM_S 0
|
||||
|
||||
#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0034)
|
||||
/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable clk gate*/
|
||||
#define I2S_CLK_EN (BIT(29))
|
||||
#define I2S_CLK_EN_M (BIT(29))
|
||||
#define I2S_CLK_EN_V 0x1
|
||||
#define I2S_CLK_EN_S 29
|
||||
/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */
|
||||
/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2:
|
||||
CLK160. 3: I2S_MCLK_in.*/
|
||||
#define I2S_TX_CLK_SEL 0x00000003
|
||||
#define I2S_TX_CLK_SEL_M ((I2S_TX_CLK_SEL_V) << (I2S_TX_CLK_SEL_S))
|
||||
#define I2S_TX_CLK_SEL_V 0x3
|
||||
#define I2S_TX_CLK_SEL_S 27
|
||||
/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: I2S Tx module clock enable signal.*/
|
||||
#define I2S_TX_CLK_ACTIVE (BIT(26))
|
||||
#define I2S_TX_CLK_ACTIVE_M (BIT(26))
|
||||
#define I2S_TX_CLK_ACTIVE_V 0x1
|
||||
#define I2S_TX_CLK_ACTIVE_S 26
|
||||
/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */
|
||||
/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a).
|
||||
There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
|
||||
#define I2S_TX_CLKM_DIV_NUM 0x000000FF
|
||||
#define I2S_TX_CLKM_DIV_NUM_M ((I2S_TX_CLKM_DIV_NUM_V) << (I2S_TX_CLKM_DIV_NUM_S))
|
||||
#define I2S_TX_CLKM_DIV_NUM_V 0xFF
|
||||
#define I2S_TX_CLKM_DIV_NUM_S 0
|
||||
|
||||
#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x0038)
|
||||
/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b >
|
||||
a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
|
||||
#define I2S_RX_CLKM_DIV_YN1 (BIT(27))
|
||||
#define I2S_RX_CLKM_DIV_YN1_M (BIT(27))
|
||||
#define I2S_RX_CLKM_DIV_YN1_V 0x1
|
||||
#define I2S_RX_CLKM_DIV_YN1_S 27
|
||||
/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
|
||||
/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For
|
||||
b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
|
||||
#define I2S_RX_CLKM_DIV_X 0x000001FF
|
||||
#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V) << (I2S_RX_CLKM_DIV_X_S))
|
||||
#define I2S_RX_CLKM_DIV_X_V 0x1FF
|
||||
#define I2S_RX_CLKM_DIV_X_S 18
|
||||
/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
|
||||
/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b
|
||||
> a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
|
||||
#define I2S_RX_CLKM_DIV_Y 0x000001FF
|
||||
#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V) << (I2S_RX_CLKM_DIV_Y_S))
|
||||
#define I2S_RX_CLKM_DIV_Y_V 0x1FF
|
||||
#define I2S_RX_CLKM_DIV_Y_S 9
|
||||
/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
|
||||
/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2
|
||||
the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
|
||||
#define I2S_RX_CLKM_DIV_Z 0x000001FF
|
||||
#define I2S_RX_CLKM_DIV_Z_M ((I2S_RX_CLKM_DIV_Z_V) << (I2S_RX_CLKM_DIV_Z_S))
|
||||
#define I2S_RX_CLKM_DIV_Z_V 0x1FF
|
||||
#define I2S_RX_CLKM_DIV_Z_S 0
|
||||
|
||||
#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x003C)
|
||||
/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b >
|
||||
a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
|
||||
#define I2S_TX_CLKM_DIV_YN1 (BIT(27))
|
||||
#define I2S_TX_CLKM_DIV_YN1_M (BIT(27))
|
||||
#define I2S_TX_CLKM_DIV_YN1_V 0x1
|
||||
#define I2S_TX_CLKM_DIV_YN1_S 27
|
||||
/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */
|
||||
/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For
|
||||
b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
|
||||
#define I2S_TX_CLKM_DIV_X 0x000001FF
|
||||
#define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V) << (I2S_TX_CLKM_DIV_X_S))
|
||||
#define I2S_TX_CLKM_DIV_X_V 0x1FF
|
||||
#define I2S_TX_CLKM_DIV_X_S 18
|
||||
/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */
|
||||
/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b
|
||||
> a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
|
||||
#define I2S_TX_CLKM_DIV_Y 0x000001FF
|
||||
#define I2S_TX_CLKM_DIV_Y_M ((I2S_TX_CLKM_DIV_Y_V) << (I2S_TX_CLKM_DIV_Y_S))
|
||||
#define I2S_TX_CLKM_DIV_Y_V 0x1FF
|
||||
#define I2S_TX_CLKM_DIV_Y_S 9
|
||||
/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */
|
||||
/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2
|
||||
the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
|
||||
#define I2S_TX_CLKM_DIV_Z 0x000001FF
|
||||
#define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V) << (I2S_TX_CLKM_DIV_Z_S))
|
||||
#define I2S_TX_CLKM_DIV_Z_V 0x1FF
|
||||
#define I2S_TX_CLKM_DIV_Z_S 0
|
||||
|
||||
#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0050)
|
||||
/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
|
||||
/*description: The total channel number of I2S TX TDM mode.*/
|
||||
#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000F
|
||||
#define I2S_RX_TDM_TOT_CHAN_NUM_M ((I2S_RX_TDM_TOT_CHAN_NUM_V) << (I2S_RX_TDM_TOT_CHAN_NUM_S))
|
||||
#define I2S_RX_TDM_TOT_CHAN_NUM_V 0xF
|
||||
#define I2S_RX_TDM_TOT_CHAN_NUM_S 16
|
||||
/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN15_EN (BIT(15))
|
||||
#define I2S_RX_TDM_CHAN15_EN_M (BIT(15))
|
||||
#define I2S_RX_TDM_CHAN15_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN15_EN_S 15
|
||||
/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN14_EN (BIT(14))
|
||||
#define I2S_RX_TDM_CHAN14_EN_M (BIT(14))
|
||||
#define I2S_RX_TDM_CHAN14_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN14_EN_S 14
|
||||
/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN13_EN (BIT(13))
|
||||
#define I2S_RX_TDM_CHAN13_EN_M (BIT(13))
|
||||
#define I2S_RX_TDM_CHAN13_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN13_EN_S 13
|
||||
/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN12_EN (BIT(12))
|
||||
#define I2S_RX_TDM_CHAN12_EN_M (BIT(12))
|
||||
#define I2S_RX_TDM_CHAN12_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN12_EN_S 12
|
||||
/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN11_EN (BIT(11))
|
||||
#define I2S_RX_TDM_CHAN11_EN_M (BIT(11))
|
||||
#define I2S_RX_TDM_CHAN11_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN11_EN_S 11
|
||||
/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN10_EN (BIT(10))
|
||||
#define I2S_RX_TDM_CHAN10_EN_M (BIT(10))
|
||||
#define I2S_RX_TDM_CHAN10_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN10_EN_S 10
|
||||
/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN9_EN (BIT(9))
|
||||
#define I2S_RX_TDM_CHAN9_EN_M (BIT(9))
|
||||
#define I2S_RX_TDM_CHAN9_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN9_EN_S 9
|
||||
/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0:
|
||||
Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_CHAN8_EN (BIT(8))
|
||||
#define I2S_RX_TDM_CHAN8_EN_M (BIT(8))
|
||||
#define I2S_RX_TDM_CHAN8_EN_V 0x1
|
||||
#define I2S_RX_TDM_CHAN8_EN_S 8
|
||||
/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7))
|
||||
#define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7))
|
||||
#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN7_EN_S 7
|
||||
/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6))
|
||||
#define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6))
|
||||
#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN6_EN_S 6
|
||||
/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5))
|
||||
#define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5))
|
||||
#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN5_EN_S 5
|
||||
/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4))
|
||||
#define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4))
|
||||
#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN4_EN_S 4
|
||||
/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3))
|
||||
#define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3))
|
||||
#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN3_EN_S 3
|
||||
/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2))
|
||||
#define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2))
|
||||
#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN2_EN_S 2
|
||||
/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1))
|
||||
#define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1))
|
||||
#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN1_EN_S 1
|
||||
/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n.
|
||||
0: Disable just input 0 in this channel.*/
|
||||
#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0))
|
||||
#define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0))
|
||||
#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x1
|
||||
#define I2S_RX_TDM_PDM_CHAN0_EN_S 0
|
||||
|
||||
#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0054)
|
||||
/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */
|
||||
/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM
|
||||
+ 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
|
||||
#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20))
|
||||
#define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20))
|
||||
#define I2S_TX_TDM_SKIP_MSK_EN_V 0x1
|
||||
#define I2S_TX_TDM_SKIP_MSK_EN_S 20
|
||||
/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */
|
||||
/*description: The total channel number minus 1 of I2S TX TDM mode.*/
|
||||
#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000F
|
||||
#define I2S_TX_TDM_TOT_CHAN_NUM_M ((I2S_TX_TDM_TOT_CHAN_NUM_V) << (I2S_TX_TDM_TOT_CHAN_NUM_S))
|
||||
#define I2S_TX_TDM_TOT_CHAN_NUM_V 0xF
|
||||
#define I2S_TX_TDM_TOT_CHAN_NUM_S 16
|
||||
/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN15_EN (BIT(15))
|
||||
#define I2S_TX_TDM_CHAN15_EN_M (BIT(15))
|
||||
#define I2S_TX_TDM_CHAN15_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN15_EN_S 15
|
||||
/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN14_EN (BIT(14))
|
||||
#define I2S_TX_TDM_CHAN14_EN_M (BIT(14))
|
||||
#define I2S_TX_TDM_CHAN14_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN14_EN_S 14
|
||||
/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN13_EN (BIT(13))
|
||||
#define I2S_TX_TDM_CHAN13_EN_M (BIT(13))
|
||||
#define I2S_TX_TDM_CHAN13_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN13_EN_S 13
|
||||
/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN12_EN (BIT(12))
|
||||
#define I2S_TX_TDM_CHAN12_EN_M (BIT(12))
|
||||
#define I2S_TX_TDM_CHAN12_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN12_EN_S 12
|
||||
/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN11_EN (BIT(11))
|
||||
#define I2S_TX_TDM_CHAN11_EN_M (BIT(11))
|
||||
#define I2S_TX_TDM_CHAN11_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN11_EN_S 11
|
||||
/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN10_EN (BIT(10))
|
||||
#define I2S_TX_TDM_CHAN10_EN_M (BIT(10))
|
||||
#define I2S_TX_TDM_CHAN10_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN10_EN_S 10
|
||||
/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN9_EN (BIT(9))
|
||||
#define I2S_TX_TDM_CHAN9_EN_M (BIT(9))
|
||||
#define I2S_TX_TDM_CHAN9_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN9_EN_S 9
|
||||
/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN8_EN (BIT(8))
|
||||
#define I2S_TX_TDM_CHAN8_EN_M (BIT(8))
|
||||
#define I2S_TX_TDM_CHAN8_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN8_EN_S 8
|
||||
/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN7_EN (BIT(7))
|
||||
#define I2S_TX_TDM_CHAN7_EN_M (BIT(7))
|
||||
#define I2S_TX_TDM_CHAN7_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN7_EN_S 7
|
||||
/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN6_EN (BIT(6))
|
||||
#define I2S_TX_TDM_CHAN6_EN_M (BIT(6))
|
||||
#define I2S_TX_TDM_CHAN6_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN6_EN_S 6
|
||||
/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN5_EN (BIT(5))
|
||||
#define I2S_TX_TDM_CHAN5_EN_M (BIT(5))
|
||||
#define I2S_TX_TDM_CHAN5_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN5_EN_S 5
|
||||
/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN4_EN (BIT(4))
|
||||
#define I2S_TX_TDM_CHAN4_EN_M (BIT(4))
|
||||
#define I2S_TX_TDM_CHAN4_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN4_EN_S 4
|
||||
/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN3_EN (BIT(3))
|
||||
#define I2S_TX_TDM_CHAN3_EN_M (BIT(3))
|
||||
#define I2S_TX_TDM_CHAN3_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN3_EN_S 3
|
||||
/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN2_EN (BIT(2))
|
||||
#define I2S_TX_TDM_CHAN2_EN_M (BIT(2))
|
||||
#define I2S_TX_TDM_CHAN2_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN2_EN_S 2
|
||||
/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN1_EN (BIT(1))
|
||||
#define I2S_TX_TDM_CHAN1_EN_M (BIT(1))
|
||||
#define I2S_TX_TDM_CHAN1_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN1_EN_S 1
|
||||
/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */
|
||||
/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0:
|
||||
Disable just output 0 in this channel.*/
|
||||
#define I2S_TX_TDM_CHAN0_EN (BIT(0))
|
||||
#define I2S_TX_TDM_CHAN0_EN_M (BIT(0))
|
||||
#define I2S_TX_TDM_CHAN0_EN_V 0x1
|
||||
#define I2S_TX_TDM_CHAN0_EN_S 0
|
||||
|
||||
#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x0058)
|
||||
/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_BCK_IN_DM 0x00000003
|
||||
#define I2S_RX_BCK_IN_DM_M ((I2S_RX_BCK_IN_DM_V) << (I2S_RX_BCK_IN_DM_S))
|
||||
#define I2S_RX_BCK_IN_DM_V 0x3
|
||||
#define I2S_RX_BCK_IN_DM_S 28
|
||||
/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_WS_IN_DM 0x00000003
|
||||
#define I2S_RX_WS_IN_DM_M ((I2S_RX_WS_IN_DM_V) << (I2S_RX_WS_IN_DM_S))
|
||||
#define I2S_RX_WS_IN_DM_V 0x3
|
||||
#define I2S_RX_WS_IN_DM_S 24
|
||||
/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_BCK_OUT_DM 0x00000003
|
||||
#define I2S_RX_BCK_OUT_DM_M ((I2S_RX_BCK_OUT_DM_V) << (I2S_RX_BCK_OUT_DM_S))
|
||||
#define I2S_RX_BCK_OUT_DM_V 0x3
|
||||
#define I2S_RX_BCK_OUT_DM_S 20
|
||||
/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_WS_OUT_DM 0x00000003
|
||||
#define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V) << (I2S_RX_WS_OUT_DM_S))
|
||||
#define I2S_RX_WS_OUT_DM_V 0x3
|
||||
#define I2S_RX_WS_OUT_DM_S 16
|
||||
/* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_SD3_IN_DM 0x00000003
|
||||
#define I2S_RX_SD3_IN_DM_M ((I2S_RX_SD3_IN_DM_V) << (I2S_RX_SD3_IN_DM_S))
|
||||
#define I2S_RX_SD3_IN_DM_V 0x3
|
||||
#define I2S_RX_SD3_IN_DM_S 12
|
||||
/* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_SD2_IN_DM 0x00000003
|
||||
#define I2S_RX_SD2_IN_DM_M ((I2S_RX_SD2_IN_DM_V) << (I2S_RX_SD2_IN_DM_S))
|
||||
#define I2S_RX_SD2_IN_DM_V 0x3
|
||||
#define I2S_RX_SD2_IN_DM_S 8
|
||||
/* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_SD1_IN_DM 0x00000003
|
||||
#define I2S_RX_SD1_IN_DM_M ((I2S_RX_SD1_IN_DM_V) << (I2S_RX_SD1_IN_DM_S))
|
||||
#define I2S_RX_SD1_IN_DM_V 0x3
|
||||
#define I2S_RX_SD1_IN_DM_S 4
|
||||
/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_RX_SD_IN_DM 0x00000003
|
||||
#define I2S_RX_SD_IN_DM_M ((I2S_RX_SD_IN_DM_V) << (I2S_RX_SD_IN_DM_S))
|
||||
#define I2S_RX_SD_IN_DM_V 0x3
|
||||
#define I2S_RX_SD_IN_DM_S 0
|
||||
|
||||
#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x005C)
|
||||
/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_TX_BCK_IN_DM 0x00000003
|
||||
#define I2S_TX_BCK_IN_DM_M ((I2S_TX_BCK_IN_DM_V) << (I2S_TX_BCK_IN_DM_S))
|
||||
#define I2S_TX_BCK_IN_DM_V 0x3
|
||||
#define I2S_TX_BCK_IN_DM_S 28
|
||||
/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_TX_WS_IN_DM 0x00000003
|
||||
#define I2S_TX_WS_IN_DM_M ((I2S_TX_WS_IN_DM_V) << (I2S_TX_WS_IN_DM_S))
|
||||
#define I2S_TX_WS_IN_DM_V 0x3
|
||||
#define I2S_TX_WS_IN_DM_S 24
|
||||
/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_TX_BCK_OUT_DM 0x00000003
|
||||
#define I2S_TX_BCK_OUT_DM_M ((I2S_TX_BCK_OUT_DM_V) << (I2S_TX_BCK_OUT_DM_S))
|
||||
#define I2S_TX_BCK_OUT_DM_V 0x3
|
||||
#define I2S_TX_BCK_OUT_DM_S 20
|
||||
/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_TX_WS_OUT_DM 0x00000003
|
||||
#define I2S_TX_WS_OUT_DM_M ((I2S_TX_WS_OUT_DM_V) << (I2S_TX_WS_OUT_DM_S))
|
||||
#define I2S_TX_WS_OUT_DM_V 0x3
|
||||
#define I2S_TX_WS_OUT_DM_S 16
|
||||
/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay
|
||||
by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
#define I2S_TX_SD_OUT_DM 0x00000003
|
||||
#define I2S_TX_SD_OUT_DM_M ((I2S_TX_SD_OUT_DM_V) << (I2S_TX_SD_OUT_DM_S))
|
||||
#define I2S_TX_SD_OUT_DM_V 0x3
|
||||
#define I2S_TX_SD_OUT_DM_S 0
|
||||
|
||||
#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060)
|
||||
/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: The enable bit for FIFO timeout*/
|
||||
#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11))
|
||||
#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11))
|
||||
#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1
|
||||
#define I2S_LC_FIFO_TIMEOUT_ENA_S 11
|
||||
/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */
|
||||
/*description: The bits are used to scale tick counter threshold. The tick counter
|
||||
is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
|
||||
#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007
|
||||
#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V) << (I2S_LC_FIFO_TIMEOUT_SHIFT_S))
|
||||
#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7
|
||||
#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8
|
||||
/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */
|
||||
/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt
|
||||
will be triggered when fifo hung counter is equal to this value*/
|
||||
#define I2S_LC_FIFO_TIMEOUT 0x000000FF
|
||||
#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V) << (I2S_LC_FIFO_TIMEOUT_S))
|
||||
#define I2S_LC_FIFO_TIMEOUT_V 0xFF
|
||||
#define I2S_LC_FIFO_TIMEOUT_S 0
|
||||
|
||||
#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0064)
|
||||
/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */
|
||||
/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
|
||||
#define I2S_RX_EOF_NUM 0x00000FFF
|
||||
#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V) << (I2S_RX_EOF_NUM_S))
|
||||
#define I2S_RX_EOF_NUM_V 0xFFF
|
||||
#define I2S_RX_EOF_NUM_S 0
|
||||
|
||||
#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0068)
|
||||
/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */
|
||||
/*description: the right channel or left channel put out constant value stored
|
||||
in this register according to tx_chan_mod and reg_tx_msb_right*/
|
||||
#define I2S_SINGLE_DATA 0xFFFFFFFF
|
||||
#define I2S_SINGLE_DATA_M ((I2S_SINGLE_DATA_V) << (I2S_SINGLE_DATA_S))
|
||||
#define I2S_SINGLE_DATA_V 0xFFFFFFFF
|
||||
#define I2S_SINGLE_DATA_S 0
|
||||
|
||||
#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x006C)
|
||||
/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/
|
||||
#define I2S_TX_IDLE (BIT(0))
|
||||
#define I2S_TX_IDLE_M (BIT(0))
|
||||
#define I2S_TX_IDLE_V 0x1
|
||||
#define I2S_TX_IDLE_S 0
|
||||
|
||||
#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x0080)
|
||||
/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */
|
||||
/*description: Version control register*/
|
||||
#define I2S_DATE 0x0FFFFFFF
|
||||
#define I2S_DATE_M ((I2S_DATE_V) << (I2S_DATE_S))
|
||||
#define I2S_DATE_V 0xFFFFFFF
|
||||
#define I2S_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
318
components/soc/soc/esp32s3/include/soc/i2s_struct.h
Normal file
318
components/soc/soc/esp32s3/include/soc/i2s_struct.h
Normal file
|
|
@ -0,0 +1,318 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t reserved_0;
|
||||
uint32_t reserved_4;
|
||||
uint32_t reserved_8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_done: 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/
|
||||
uint32_t tx_done: 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/
|
||||
uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/
|
||||
uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/
|
||||
uint32_t reserved4: 28; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
uint32_t reserved_1c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_reset: 1; /*Set this bit to reset receiver*/
|
||||
uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/
|
||||
uint32_t rx_start: 1; /*Set this bit to start receiving data*/
|
||||
uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/
|
||||
uint32_t reserved4: 1; /*Reserved*/
|
||||
uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/
|
||||
uint32_t reserved6: 1;
|
||||
uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
|
||||
uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
uint32_t rx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/
|
||||
uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
|
||||
uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/
|
||||
uint32_t rx_stop_mode: 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/
|
||||
uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/
|
||||
uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/
|
||||
uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/
|
||||
uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/
|
||||
uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/
|
||||
uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/
|
||||
uint32_t rx_pdm2pcm_en: 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/
|
||||
uint32_t rx_sinc_dsr_16_en: 1;
|
||||
uint32_t reserved23: 9; /*Reserve*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/
|
||||
uint32_t tx_fifo_reset: 1; /*Set this bit to reset Tx AFIFO*/
|
||||
uint32_t tx_start: 1; /*Set this bit to start transmitting data*/
|
||||
uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/
|
||||
uint32_t reserved4: 1; /*Reserved*/
|
||||
uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/
|
||||
uint32_t tx_chan_equal: 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/
|
||||
uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/
|
||||
uint32_t tx_update: 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/
|
||||
uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/
|
||||
uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/
|
||||
uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/
|
||||
uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/
|
||||
uint32_t reserved14: 1;
|
||||
uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/
|
||||
uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/
|
||||
uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/
|
||||
uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/
|
||||
uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/
|
||||
uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/
|
||||
uint32_t reserved21: 3; /*Reserved*/
|
||||
uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/
|
||||
uint32_t sig_loopback: 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/
|
||||
uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/
|
||||
uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/
|
||||
uint32_t rx_half_sample_bits: 6; /*I2S Rx half sample bits -1.*/
|
||||
uint32_t rx_tdm_chan_bits: 5; /*The Rx bit number for each channel minus 1in TDM mode.*/
|
||||
uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/
|
||||
uint32_t reserved30: 2; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/
|
||||
uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/
|
||||
uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/
|
||||
uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/
|
||||
uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/
|
||||
uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/
|
||||
uint32_t reserved30: 2; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/
|
||||
uint32_t reserved8: 18; /*Reserved*/
|
||||
uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/
|
||||
uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
|
||||
uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/
|
||||
uint32_t reserved30: 2; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/
|
||||
uint32_t reserved8: 18; /*Reserved*/
|
||||
uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/
|
||||
uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/
|
||||
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
|
||||
uint32_t reserved30: 2; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_clkm_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/
|
||||
uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/
|
||||
uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/
|
||||
uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_clkm_div_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/
|
||||
uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/
|
||||
uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/
|
||||
uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_clkm_div_conf;
|
||||
uint32_t reserved_40;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_tdm_chan0_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan1_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan2_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan3_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan4_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan5_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan6_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan7_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan8_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan9_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan10_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan11_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan12_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan13_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan14_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_chan15_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/
|
||||
uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/
|
||||
uint32_t reserved20: 12; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_tdm_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/
|
||||
uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/
|
||||
uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/
|
||||
uint32_t reserved21: 11; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_tdm_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved6: 2;
|
||||
uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved10: 2;
|
||||
uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved14: 2;
|
||||
uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved18: 2;
|
||||
uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved22: 2;
|
||||
uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved26: 2;
|
||||
uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_timing;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved2: 14; /*Reserved*/
|
||||
uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved18: 2;
|
||||
uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved22: 2;
|
||||
uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved26: 2;
|
||||
uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_timing;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/
|
||||
uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/
|
||||
uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/
|
||||
uint32_t reserved12: 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_hung_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_eof_num: 12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/
|
||||
uint32_t reserved12: 20; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_eof_num;
|
||||
uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/
|
||||
uint32_t reserved1: 31; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28; /*Version control register*/
|
||||
uint32_t reserved28: 4; /*Reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} i2s_dev_t;
|
||||
|
||||
extern i2s_dev_t I2S0;
|
||||
extern i2s_dev_t I2S1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
784
components/soc/soc/esp32s3/include/soc/interrupt_core0_reg.h
Normal file
784
components/soc/soc/esp32s3/include/soc/interrupt_core0_reg.h
Normal file
|
|
@ -0,0 +1,784 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000)
|
||||
/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V) << (INTERRUPT_CORE0_MAC_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004)
|
||||
/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V) << (INTERRUPT_CORE0_MAC_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008)
|
||||
/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V) << (INTERRUPT_CORE0_PWR_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C)
|
||||
/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V) << (INTERRUPT_CORE0_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010)
|
||||
/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V) << (INTERRUPT_CORE0_BT_MAC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014)
|
||||
/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V) << (INTERRUPT_CORE0_BT_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018)
|
||||
/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V) << (INTERRUPT_CORE0_BT_BB_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C)
|
||||
/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V) << (INTERRUPT_CORE0_RWBT_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020)
|
||||
/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V) << (INTERRUPT_CORE0_RWBLE_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024)
|
||||
/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V) << (INTERRUPT_CORE0_RWBT_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028)
|
||||
/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V) << (INTERRUPT_CORE0_RWBLE_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C)
|
||||
/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V) << (INTERRUPT_CORE0_I2C_MST_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030)
|
||||
/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V) << (INTERRUPT_CORE0_SLC0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034)
|
||||
/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V) << (INTERRUPT_CORE0_SLC1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038)
|
||||
/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V) << (INTERRUPT_CORE0_UHCI0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C)
|
||||
/* INTERRUPT_CORE0_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_M ((INTERRUPT_CORE0_UHCI1_INTR_MAP_V) << (INTERRUPT_CORE0_UHCI1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UHCI1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C)
|
||||
/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_1_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_2_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_M ((INTERRUPT_CORE0_SPI_INTR_3_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_3_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C)
|
||||
/* INTERRUPT_CORE0_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_M ((INTERRUPT_CORE0_SPI_INTR_4_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_4_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_INTR_4_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060)
|
||||
/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V) << (INTERRUPT_CORE0_LCD_CAM_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064)
|
||||
/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_M ((INTERRUPT_CORE0_I2S0_INT_MAP_V) << (INTERRUPT_CORE0_I2S0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2S0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068)
|
||||
/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V) << (INTERRUPT_CORE0_I2S1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C)
|
||||
/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V) << (INTERRUPT_CORE0_UART_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070)
|
||||
/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V) << (INTERRUPT_CORE0_UART1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074)
|
||||
/* INTERRUPT_CORE0_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_M ((INTERRUPT_CORE0_UART2_INTR_MAP_V) << (INTERRUPT_CORE0_UART2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_UART2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078)
|
||||
/* INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V) << (INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C)
|
||||
/* INTERRUPT_CORE0_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_M ((INTERRUPT_CORE0_PWM0_INTR_MAP_V) << (INTERRUPT_CORE0_PWM0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080)
|
||||
/* INTERRUPT_CORE0_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_M ((INTERRUPT_CORE0_PWM1_INTR_MAP_V) << (INTERRUPT_CORE0_PWM1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084)
|
||||
/* INTERRUPT_CORE0_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_M ((INTERRUPT_CORE0_PWM2_INTR_MAP_V) << (INTERRUPT_CORE0_PWM2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088)
|
||||
/* INTERRUPT_CORE0_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_M ((INTERRUPT_CORE0_PWM3_INTR_MAP_V) << (INTERRUPT_CORE0_PWM3_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PWM3_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C)
|
||||
/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V) << (INTERRUPT_CORE0_LEDC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090)
|
||||
/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V) << (INTERRUPT_CORE0_EFUSE_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094)
|
||||
/* INTERRUPT_CORE0_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TWAI_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TWAI_INT_MAP_M ((INTERRUPT_CORE0_TWAI_INT_MAP_V) << (INTERRUPT_CORE0_TWAI_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TWAI_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TWAI_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098)
|
||||
/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V) << (INTERRUPT_CORE0_USB_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_USB_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C)
|
||||
/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V) << (INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0)
|
||||
/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V) << (INTERRUPT_CORE0_RMT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4)
|
||||
/* INTERRUPT_CORE0_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_M ((INTERRUPT_CORE0_PCNT_INTR_MAP_V) << (INTERRUPT_CORE0_PCNT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8)
|
||||
/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V) << (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC)
|
||||
/* INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V) << (INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0)
|
||||
/* INTERRUPT_CORE0_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4)
|
||||
/* INTERRUPT_CORE0_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8)
|
||||
/* INTERRUPT_CORE0_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC)
|
||||
/* INTERRUPT_CORE0_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_M ((INTERRUPT_CORE0_WDG_INT_MAP_V) << (INTERRUPT_CORE0_WDG_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_WDG_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0)
|
||||
/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V) << (INTERRUPT_CORE0_TIMER_INT1_MAP_S))
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4)
|
||||
/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V) << (INTERRUPT_CORE0_TIMER_INT2_MAP_S))
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8)
|
||||
/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V) << (INTERRUPT_CORE0_TG_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC)
|
||||
/* INTERRUPT_CORE0_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_M ((INTERRUPT_CORE0_TG_T1_INT_MAP_V) << (INTERRUPT_CORE0_TG_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0)
|
||||
/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V) << (INTERRUPT_CORE0_TG_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4)
|
||||
/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V) << (INTERRUPT_CORE0_TG1_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8)
|
||||
/* INTERRUPT_CORE0_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_M ((INTERRUPT_CORE0_TG1_T1_INT_MAP_V) << (INTERRUPT_CORE0_TG1_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC)
|
||||
/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V) << (INTERRUPT_CORE0_TG1_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0)
|
||||
/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_IA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC)
|
||||
/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0)
|
||||
/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V) << (INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4)
|
||||
/* INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8)
|
||||
/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC)
|
||||
/* INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100)
|
||||
/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104)
|
||||
/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V) << (INTERRUPT_CORE0_APB_ADC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108)
|
||||
/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C)
|
||||
/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110)
|
||||
/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114)
|
||||
/* INTERRUPT_CORE0_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH3_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118)
|
||||
/* INTERRUPT_CORE0_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH4_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C)
|
||||
/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V) << (INTERRUPT_CORE0_RSA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_RSA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120)
|
||||
/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V) << (INTERRUPT_CORE0_AES_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_AES_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124)
|
||||
/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V) << (INTERRUPT_CORE0_SHA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_SHA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134)
|
||||
/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S))
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138)
|
||||
/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V) << (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C)
|
||||
/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140)
|
||||
/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144)
|
||||
/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148)
|
||||
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C)
|
||||
/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150)
|
||||
/* INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154)
|
||||
/* INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158)
|
||||
/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C)
|
||||
/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160)
|
||||
/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164)
|
||||
/* INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V) << (INTERRUPT_CORE0_INTR_STATUS_0_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_0_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V) << (INTERRUPT_CORE0_INTR_STATUS_1_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_1_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170)
|
||||
/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V) << (INTERRUPT_CORE0_INTR_STATUS_2_S))
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTR_STATUS_2_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174)
|
||||
/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_CLK_EN (BIT(0))
|
||||
#define INTERRUPT_CORE0_CLK_EN_M (BIT(0))
|
||||
#define INTERRUPT_CORE0_CLK_EN_V 0x1
|
||||
#define INTERRUPT_CORE0_CLK_EN_S 0
|
||||
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC)
|
||||
/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V) << (INTERRUPT_CORE0_INTERRUPT_DATE_S))
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF
|
||||
#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1093
components/soc/soc/esp32s3/include/soc/interrupt_core0_struct.h
Normal file
1093
components/soc/soc/esp32s3/include/soc/interrupt_core0_struct.h
Normal file
File diff suppressed because it is too large
Load diff
784
components/soc/soc/esp32s3/include/soc/interrupt_core1_reg.h
Normal file
784
components/soc/soc/esp32s3/include/soc/interrupt_core1_reg.h
Normal file
|
|
@ -0,0 +1,784 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x800)
|
||||
/* INTERRUPT_CORE1_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_M ((INTERRUPT_CORE1_MAC_INTR_MAP_V) << (INTERRUPT_CORE1_MAC_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_MAC_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x804)
|
||||
/* INTERRUPT_CORE1_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_M ((INTERRUPT_CORE1_MAC_NMI_MAP_V) << (INTERRUPT_CORE1_MAC_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_MAC_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x808)
|
||||
/* INTERRUPT_CORE1_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_M ((INTERRUPT_CORE1_PWR_INTR_MAP_V) << (INTERRUPT_CORE1_PWR_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWR_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80C)
|
||||
/* INTERRUPT_CORE1_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_M ((INTERRUPT_CORE1_BB_INT_MAP_V) << (INTERRUPT_CORE1_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x810)
|
||||
/* INTERRUPT_CORE1_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_M ((INTERRUPT_CORE1_BT_MAC_INT_MAP_V) << (INTERRUPT_CORE1_BT_MAC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BT_MAC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x814)
|
||||
/* INTERRUPT_CORE1_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_M ((INTERRUPT_CORE1_BT_BB_INT_MAP_V) << (INTERRUPT_CORE1_BT_BB_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BT_BB_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x818)
|
||||
/* INTERRUPT_CORE1_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_M ((INTERRUPT_CORE1_BT_BB_NMI_MAP_V) << (INTERRUPT_CORE1_BT_BB_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_BT_BB_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x81C)
|
||||
/* INTERRUPT_CORE1_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_M ((INTERRUPT_CORE1_RWBT_IRQ_MAP_V) << (INTERRUPT_CORE1_RWBT_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBT_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x820)
|
||||
/* INTERRUPT_CORE1_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE1_RWBLE_IRQ_MAP_V) << (INTERRUPT_CORE1_RWBLE_IRQ_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x824)
|
||||
/* INTERRUPT_CORE1_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_M ((INTERRUPT_CORE1_RWBT_NMI_MAP_V) << (INTERRUPT_CORE1_RWBT_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBT_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x828)
|
||||
/* INTERRUPT_CORE1_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_M ((INTERRUPT_CORE1_RWBLE_NMI_MAP_V) << (INTERRUPT_CORE1_RWBLE_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RWBLE_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x82C)
|
||||
/* INTERRUPT_CORE1_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_M ((INTERRUPT_CORE1_I2C_MST_INT_MAP_V) << (INTERRUPT_CORE1_I2C_MST_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2C_MST_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x830)
|
||||
/* INTERRUPT_CORE1_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_M ((INTERRUPT_CORE1_SLC0_INTR_MAP_V) << (INTERRUPT_CORE1_SLC0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SLC0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x834)
|
||||
/* INTERRUPT_CORE1_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_M ((INTERRUPT_CORE1_SLC1_INTR_MAP_V) << (INTERRUPT_CORE1_SLC1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SLC1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x838)
|
||||
/* INTERRUPT_CORE1_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_M ((INTERRUPT_CORE1_UHCI0_INTR_MAP_V) << (INTERRUPT_CORE1_UHCI0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UHCI0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x83C)
|
||||
/* INTERRUPT_CORE1_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_M ((INTERRUPT_CORE1_UHCI1_INTR_MAP_V) << (INTERRUPT_CORE1_UHCI1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UHCI1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x840)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x844)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x848)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84C)
|
||||
/* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S))
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x850)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_M ((INTERRUPT_CORE1_SPI_INTR_1_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_1_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x854)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_M ((INTERRUPT_CORE1_SPI_INTR_2_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_2_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x858)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_M ((INTERRUPT_CORE1_SPI_INTR_3_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_3_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x85C)
|
||||
/* INTERRUPT_CORE1_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_M ((INTERRUPT_CORE1_SPI_INTR_4_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_4_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_INTR_4_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x860)
|
||||
/* INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V) << (INTERRUPT_CORE1_LCD_CAM_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x864)
|
||||
/* INTERRUPT_CORE1_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_M ((INTERRUPT_CORE1_I2S0_INT_MAP_V) << (INTERRUPT_CORE1_I2S0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2S0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x868)
|
||||
/* INTERRUPT_CORE1_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_M ((INTERRUPT_CORE1_I2S1_INT_MAP_V) << (INTERRUPT_CORE1_I2S1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2S1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x86C)
|
||||
/* INTERRUPT_CORE1_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_M ((INTERRUPT_CORE1_UART_INTR_MAP_V) << (INTERRUPT_CORE1_UART_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UART_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x870)
|
||||
/* INTERRUPT_CORE1_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_M ((INTERRUPT_CORE1_UART1_INTR_MAP_V) << (INTERRUPT_CORE1_UART1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UART1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x874)
|
||||
/* INTERRUPT_CORE1_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_M ((INTERRUPT_CORE1_UART2_INTR_MAP_V) << (INTERRUPT_CORE1_UART2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_UART2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x878)
|
||||
/* INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V) << (INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x87C)
|
||||
/* INTERRUPT_CORE1_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_M ((INTERRUPT_CORE1_PWM0_INTR_MAP_V) << (INTERRUPT_CORE1_PWM0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x880)
|
||||
/* INTERRUPT_CORE1_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_M ((INTERRUPT_CORE1_PWM1_INTR_MAP_V) << (INTERRUPT_CORE1_PWM1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x884)
|
||||
/* INTERRUPT_CORE1_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_M ((INTERRUPT_CORE1_PWM2_INTR_MAP_V) << (INTERRUPT_CORE1_PWM2_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM2_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x888)
|
||||
/* INTERRUPT_CORE1_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_M ((INTERRUPT_CORE1_PWM3_INTR_MAP_V) << (INTERRUPT_CORE1_PWM3_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PWM3_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88C)
|
||||
/* INTERRUPT_CORE1_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_M ((INTERRUPT_CORE1_LEDC_INT_MAP_V) << (INTERRUPT_CORE1_LEDC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_LEDC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x890)
|
||||
/* INTERRUPT_CORE1_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_M ((INTERRUPT_CORE1_EFUSE_INT_MAP_V) << (INTERRUPT_CORE1_EFUSE_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_EFUSE_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x894)
|
||||
/* INTERRUPT_CORE1_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TWAI_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TWAI_INT_MAP_M ((INTERRUPT_CORE1_TWAI_INT_MAP_V) << (INTERRUPT_CORE1_TWAI_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TWAI_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TWAI_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x898)
|
||||
/* INTERRUPT_CORE1_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_M ((INTERRUPT_CORE1_USB_INTR_MAP_V) << (INTERRUPT_CORE1_USB_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_USB_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x89C)
|
||||
/* INTERRUPT_CORE1_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V) << (INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A0)
|
||||
/* INTERRUPT_CORE1_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_M ((INTERRUPT_CORE1_RMT_INTR_MAP_V) << (INTERRUPT_CORE1_RMT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RMT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A4)
|
||||
/* INTERRUPT_CORE1_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_M ((INTERRUPT_CORE1_PCNT_INTR_MAP_V) << (INTERRUPT_CORE1_PCNT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_PCNT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A8)
|
||||
/* INTERRUPT_CORE1_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V) << (INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8AC)
|
||||
/* INTERRUPT_CORE1_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V) << (INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B0)
|
||||
/* INTERRUPT_CORE1_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B4)
|
||||
/* INTERRUPT_CORE1_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B8)
|
||||
/* INTERRUPT_CORE1_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8BC)
|
||||
/* INTERRUPT_CORE1_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_M ((INTERRUPT_CORE1_WDG_INT_MAP_V) << (INTERRUPT_CORE1_WDG_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_WDG_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C0)
|
||||
/* INTERRUPT_CORE1_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_M ((INTERRUPT_CORE1_TIMER_INT1_MAP_V) << (INTERRUPT_CORE1_TIMER_INT1_MAP_S))
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TIMER_INT1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C4)
|
||||
/* INTERRUPT_CORE1_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_M ((INTERRUPT_CORE1_TIMER_INT2_MAP_V) << (INTERRUPT_CORE1_TIMER_INT2_MAP_S))
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TIMER_INT2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C8)
|
||||
/* INTERRUPT_CORE1_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_M ((INTERRUPT_CORE1_TG_T0_INT_MAP_V) << (INTERRUPT_CORE1_TG_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8CC)
|
||||
/* INTERRUPT_CORE1_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_M ((INTERRUPT_CORE1_TG_T1_INT_MAP_V) << (INTERRUPT_CORE1_TG_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D0)
|
||||
/* INTERRUPT_CORE1_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG_WDT_INT_MAP_V) << (INTERRUPT_CORE1_TG_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D4)
|
||||
/* INTERRUPT_CORE1_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_M ((INTERRUPT_CORE1_TG1_T0_INT_MAP_V) << (INTERRUPT_CORE1_TG1_T0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG1_T0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D8)
|
||||
/* INTERRUPT_CORE1_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_M ((INTERRUPT_CORE1_TG1_T1_INT_MAP_V) << (INTERRUPT_CORE1_TG1_T1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG1_T1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8DC)
|
||||
/* INTERRUPT_CORE1_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG1_WDT_INT_MAP_V) << (INTERRUPT_CORE1_TG1_WDT_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E0)
|
||||
/* INTERRUPT_CORE1_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE1_CACHE_IA_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_IA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E4)
|
||||
/* INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E8)
|
||||
/* INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8EC)
|
||||
/* INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F0)
|
||||
/* INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V) << (INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F4)
|
||||
/* INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F8)
|
||||
/* INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8FC)
|
||||
/* INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x900)
|
||||
/* INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x904)
|
||||
/* INTERRUPT_CORE1_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_M ((INTERRUPT_CORE1_APB_ADC_INT_MAP_V) << (INTERRUPT_CORE1_APB_ADC_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_APB_ADC_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x908)
|
||||
/* INTERRUPT_CORE1_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH0_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90C)
|
||||
/* INTERRUPT_CORE1_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH1_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x910)
|
||||
/* INTERRUPT_CORE1_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH2_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x914)
|
||||
/* INTERRUPT_CORE1_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH3_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x918)
|
||||
/* INTERRUPT_CORE1_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH4_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x91C)
|
||||
/* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_M ((INTERRUPT_CORE1_RSA_INT_MAP_V) << (INTERRUPT_CORE1_RSA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_RSA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x920)
|
||||
/* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_M ((INTERRUPT_CORE1_AES_INT_MAP_V) << (INTERRUPT_CORE1_AES_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_AES_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x924)
|
||||
/* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_M ((INTERRUPT_CORE1_SHA_INT_MAP_V) << (INTERRUPT_CORE1_SHA_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_SHA_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x928)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x92C)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x930)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x934)
|
||||
/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S))
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x938)
|
||||
/* INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V) << (INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x93C)
|
||||
/* INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x940)
|
||||
/* INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x944)
|
||||
/* INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x948)
|
||||
/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94C)
|
||||
/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x950)
|
||||
/* INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x954)
|
||||
/* INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x958)
|
||||
/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x95C)
|
||||
/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S))
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x960)
|
||||
/* INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x964)
|
||||
/* INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP 0x0000001F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S))
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V 0x1F
|
||||
#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x968)
|
||||
/* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_M ((INTERRUPT_CORE1_INTR_STATUS_0_V) << (INTERRUPT_CORE1_INTR_STATUS_0_S))
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_0_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x96C)
|
||||
/* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_M ((INTERRUPT_CORE1_INTR_STATUS_1_V) << (INTERRUPT_CORE1_INTR_STATUS_1_S))
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_1_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x970)
|
||||
/* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_M ((INTERRUPT_CORE1_INTR_STATUS_2_V) << (INTERRUPT_CORE1_INTR_STATUS_2_S))
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTR_STATUS_2_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x974)
|
||||
/* INTERRUPT_CORE1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_CLK_EN (BIT(0))
|
||||
#define INTERRUPT_CORE1_CLK_EN_M (BIT(0))
|
||||
#define INTERRUPT_CORE1_CLK_EN_V 0x1
|
||||
#define INTERRUPT_CORE1_CLK_EN_S 0
|
||||
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xFFC)
|
||||
/* INTERRUPT_CORE1_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
|
||||
/*description: */
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE 0x0FFFFFFF
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_M ((INTERRUPT_CORE1_INTERRUPT_DATE_V) << (INTERRUPT_CORE1_INTERRUPT_DATE_S))
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_V 0xFFFFFFF
|
||||
#define INTERRUPT_CORE1_INTERRUPT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1605
components/soc/soc/esp32s3/include/soc/interrupt_core1_struct.h
Normal file
1605
components/soc/soc/esp32s3/include/soc/interrupt_core1_struct.h
Normal file
File diff suppressed because it is too large
Load diff
17
components/soc/soc/esp32s3/include/soc/interrupt_reg.h
Normal file
17
components/soc/soc/esp32s3/include/soc/interrupt_reg.h
Normal file
|
|
@ -0,0 +1,17 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "interrupt_core0_reg.h"
|
||||
#include "interrupt_core1_reg.h"
|
||||
427
components/soc/soc/esp32s3/include/soc/io_mux_reg.h
Normal file
427
components/soc/soc/esp32s3/include/soc/io_mux_reg.h
Normal file
|
|
@ -0,0 +1,427 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */
|
||||
/* Output enable in sleep mode */
|
||||
#define SLP_OE (BIT(0))
|
||||
#define SLP_OE_M (BIT(0))
|
||||
#define SLP_OE_V 1
|
||||
#define SLP_OE_S 0
|
||||
/* Pin used for wakeup from sleep */
|
||||
#define SLP_SEL (BIT(1))
|
||||
#define SLP_SEL_M (BIT(1))
|
||||
#define SLP_SEL_V 1
|
||||
#define SLP_SEL_S 1
|
||||
/* Pulldown enable in sleep mode */
|
||||
#define SLP_PD (BIT(2))
|
||||
#define SLP_PD_M (BIT(2))
|
||||
#define SLP_PD_V 1
|
||||
#define SLP_PD_S 2
|
||||
/* Pullup enable in sleep mode */
|
||||
#define SLP_PU (BIT(3))
|
||||
#define SLP_PU_M (BIT(3))
|
||||
#define SLP_PU_V 1
|
||||
#define SLP_PU_S 3
|
||||
/* Input enable in sleep mode */
|
||||
#define SLP_IE (BIT(4))
|
||||
#define SLP_IE_M (BIT(4))
|
||||
#define SLP_IE_V 1
|
||||
#define SLP_IE_S 4
|
||||
/* Drive strength in sleep mode */
|
||||
#define SLP_DRV 0x3
|
||||
#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S)
|
||||
#define SLP_DRV_V 0x3
|
||||
#define SLP_DRV_S 5
|
||||
/* Pulldown enable */
|
||||
#define FUN_PD (BIT(7))
|
||||
#define FUN_PD_M (BIT(7))
|
||||
#define FUN_PD_V 1
|
||||
#define FUN_PD_S 7
|
||||
/* Pullup enable */
|
||||
#define FUN_PU (BIT(8))
|
||||
#define FUN_PU_M (BIT(8))
|
||||
#define FUN_PU_V 1
|
||||
#define FUN_PU_S 8
|
||||
/* Input enable */
|
||||
#define FUN_IE (BIT(9))
|
||||
#define FUN_IE_M (FUN_IE_V << FUN_IE_S)
|
||||
#define FUN_IE_V 1
|
||||
#define FUN_IE_S 9
|
||||
/* Drive strength */
|
||||
#define FUN_DRV 0x3
|
||||
#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S)
|
||||
#define FUN_DRV_V 0x3
|
||||
#define FUN_DRV_S 10
|
||||
/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */
|
||||
#define MCU_SEL 0x7
|
||||
#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S)
|
||||
#define MCU_SEL_V 0x7
|
||||
#define MCU_SEL_S 12
|
||||
|
||||
#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE)
|
||||
#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv));
|
||||
#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU)
|
||||
#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD)
|
||||
#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC)
|
||||
|
||||
#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U
|
||||
#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U
|
||||
#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U
|
||||
#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U
|
||||
#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U
|
||||
#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U
|
||||
#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U
|
||||
#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U
|
||||
#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U
|
||||
#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U
|
||||
#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U
|
||||
#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U
|
||||
#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U
|
||||
#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U
|
||||
#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U
|
||||
#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U
|
||||
#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U
|
||||
#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U
|
||||
#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U
|
||||
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U
|
||||
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U
|
||||
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U
|
||||
#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U
|
||||
#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U
|
||||
#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U
|
||||
#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U
|
||||
#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U
|
||||
#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U
|
||||
#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U
|
||||
#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U
|
||||
#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U
|
||||
#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U
|
||||
#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U
|
||||
#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U
|
||||
#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U
|
||||
#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U
|
||||
#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U
|
||||
#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U
|
||||
#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U
|
||||
#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U
|
||||
#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U
|
||||
#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U
|
||||
#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U
|
||||
#define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_SPICLK_P_U
|
||||
#define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_SPICLK_N_U
|
||||
|
||||
#define FUNC_GPIO_GPIO 1
|
||||
#define PIN_FUNC_GPIO 1
|
||||
|
||||
#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0)
|
||||
#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv)
|
||||
|
||||
#define U1RXD_GPIO_NUM 18
|
||||
#define U1TXD_GPIO_NUM 17
|
||||
#define U0RXD_GPIO_NUM 44
|
||||
#define U0TXD_GPIO_NUM 43
|
||||
|
||||
#define SPI_HD_GPIO_NUM 27
|
||||
#define SPI_WP_GPIO_NUM 28
|
||||
#define SPI_CS0_GPIO_NUM 29
|
||||
#define SPI_CLK_GPIO_NUM 30
|
||||
#define SPI_Q_GPIO_NUM 31
|
||||
#define SPI_D_GPIO_NUM 32
|
||||
#define SPI_D4_GPIO_NUM 33
|
||||
#define SPI_D5_GPIO_NUM 34
|
||||
#define SPI_D6_GPIO_NUM 35
|
||||
#define SPI_D7_GPIO_NUM 36
|
||||
#define SPI_DQS_GPIO_NUM 37
|
||||
#define SD_CLK_GPIO_NUM 12
|
||||
#define SD_CMD_GPIO_NUM 11
|
||||
#define SD_DATA0_GPIO_NUM 13
|
||||
#define SD_DATA1_GPIO_NUM 14
|
||||
#define SD_DATA2_GPIO_NUM 9
|
||||
#define SD_DATA3_GPIO_NUM 10
|
||||
|
||||
#define MAX_RTC_GPIO_NUM 21
|
||||
#define MAX_PAD_GPIO_NUM 48
|
||||
#define MAX_GPIO_NUM 53
|
||||
|
||||
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
|
||||
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
|
||||
#define PAD_POWER_SEL BIT(15)
|
||||
#define PAD_POWER_SEL_V 0x1
|
||||
#define PAD_POWER_SEL_M BIT(15)
|
||||
#define PAD_POWER_SEL_S 15
|
||||
|
||||
|
||||
#define PAD_POWER_SWITCH_DELAY 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_V 0x7
|
||||
#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S)
|
||||
#define PAD_POWER_SWITCH_DELAY_S 12
|
||||
|
||||
|
||||
#define CLK_OUT3 0xf
|
||||
#define CLK_OUT3_V CLK_OUT3
|
||||
#define CLK_OUT3_S 8
|
||||
#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S)
|
||||
#define CLK_OUT2 0xf
|
||||
#define CLK_OUT2_V CLK_OUT2
|
||||
#define CLK_OUT2_S 4
|
||||
#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S)
|
||||
#define CLK_OUT1 0xf
|
||||
#define CLK_OUT1_V CLK_OUT1
|
||||
#define CLK_OUT1_S 0
|
||||
#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S)
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04)
|
||||
#define FUNC_GPIO0_GPIO0 1
|
||||
#define FUNC_GPIO0_GPIO0_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08)
|
||||
#define FUNC_GPIO1_GPIO1 1
|
||||
#define FUNC_GPIO1_GPIO1_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c)
|
||||
#define FUNC_GPIO2_GPIO2 1
|
||||
#define FUNC_GPIO2_GPIO2_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10)
|
||||
#define FUNC_GPIO3_GPIO3 1
|
||||
#define FUNC_GPIO3_GPIO3_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14)
|
||||
#define FUNC_GPIO4_GPIO4 1
|
||||
#define FUNC_GPIO4_GPIO4_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18)
|
||||
#define FUNC_GPIO5_GPIO5 1
|
||||
#define FUNC_GPIO5_GPIO5_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c)
|
||||
#define FUNC_GPIO6_GPIO6 1
|
||||
#define FUNC_GPIO6_GPIO6_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20)
|
||||
#define FUNC_GPIO7_GPIO7 1
|
||||
#define FUNC_GPIO7_GPIO7_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24)
|
||||
#define FUNC_GPIO8_SUBSPICS1 3
|
||||
#define FUNC_GPIO8_GPIO8 1
|
||||
#define FUNC_GPIO8_GPIO8_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28)
|
||||
#define FUNC_GPIO9_FSPIHD 4
|
||||
#define FUNC_GPIO9_SUBSPIHD 3
|
||||
#define FUNC_GPIO9_GPIO9 1
|
||||
#define FUNC_GPIO9_GPIO9_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c)
|
||||
#define FUNC_GPIO10_FSPICS0 4
|
||||
#define FUNC_GPIO10_SUBSPICS0 3
|
||||
#define FUNC_GPIO10_FSPIIO4 2
|
||||
#define FUNC_GPIO10_GPIO10 1
|
||||
#define FUNC_GPIO10_GPIO10_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30)
|
||||
#define FUNC_GPIO11_FSPID 4
|
||||
#define FUNC_GPIO11_SUBSPID 3
|
||||
#define FUNC_GPIO11_FSPIIO5 2
|
||||
#define FUNC_GPIO11_GPIO11 1
|
||||
#define FUNC_GPIO11_GPIO11_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34)
|
||||
#define FUNC_GPIO12_FSPICLK 4
|
||||
#define FUNC_GPIO12_SUBSPICLK 3
|
||||
#define FUNC_GPIO12_FSPIIO6 2
|
||||
#define FUNC_GPIO12_GPIO12 1
|
||||
#define FUNC_GPIO12_GPIO12_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38)
|
||||
#define FUNC_GPIO13_FSPIQ 4
|
||||
#define FUNC_GPIO13_SUBSPIQ 3
|
||||
#define FUNC_GPIO13_FSPIIO7 2
|
||||
#define FUNC_GPIO13_GPIO13 1
|
||||
#define FUNC_GPIO13_GPIO13_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c)
|
||||
#define FUNC_GPIO14_FSPIWP 4
|
||||
#define FUNC_GPIO14_SUBSPIWP 3
|
||||
#define FUNC_GPIO14_FSPIDQS 2
|
||||
#define FUNC_GPIO14_GPIO14 1
|
||||
#define FUNC_GPIO14_GPIO14_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40)
|
||||
#define FUNC_XTAL_32K_P_U0RTS 2
|
||||
#define FUNC_XTAL_32K_P_GPIO15 1
|
||||
#define FUNC_XTAL_32K_P_GPIO15_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44)
|
||||
#define FUNC_XTAL_32K_N_U0CTS 2
|
||||
#define FUNC_XTAL_32K_N_GPIO16 1
|
||||
#define FUNC_XTAL_32K_N_GPIO16_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48)
|
||||
#define FUNC_DAC_1_U1TXD 2
|
||||
#define FUNC_DAC_1_GPIO17 1
|
||||
#define FUNC_DAC_1_GPIO17_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c)
|
||||
#define FUNC_DAC_2_CLK_OUT3 3
|
||||
#define FUNC_DAC_2_U1RXD 2
|
||||
#define FUNC_DAC_2_GPIO18 1
|
||||
#define FUNC_DAC_2_GPIO18_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50)
|
||||
#define FUNC_GPIO19_CLK_OUT2 3
|
||||
#define FUNC_GPIO19_U1RTS 2
|
||||
#define FUNC_GPIO19_GPIO19 1
|
||||
#define FUNC_GPIO19_GPIO19_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54)
|
||||
#define FUNC_GPIO20_CLK_OUT1 3
|
||||
#define FUNC_GPIO20_U1CTS 2
|
||||
#define FUNC_GPIO20_GPIO20 1
|
||||
#define FUNC_GPIO20_GPIO20_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58)
|
||||
#define FUNC_GPIO21_GPIO21 1
|
||||
#define FUNC_GPIO21_GPIO21_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c)
|
||||
#define FUNC_SPICS1_GPIO26 1
|
||||
#define FUNC_SPICS1_SPICS1 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70)
|
||||
#define FUNC_SPIHD_GPIO27 1
|
||||
#define FUNC_SPIHD_SPIHD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74)
|
||||
#define FUNC_SPIWP_GPIO28 1
|
||||
#define FUNC_SPIWP_SPIWP 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78)
|
||||
#define FUNC_SPICS0_GPIO29 1
|
||||
#define FUNC_SPICS0_SPICS0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c)
|
||||
#define FUNC_SPICLK_GPIO30 1
|
||||
#define FUNC_SPICLK_SPICLK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80)
|
||||
#define FUNC_SPIQ_GPIO31 1
|
||||
#define FUNC_SPIQ_SPIQ 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84)
|
||||
#define FUNC_SPID_GPIO32 1
|
||||
#define FUNC_SPID_SPID 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88)
|
||||
#define FUNC_GPIO33_SPIIO4 4
|
||||
#define FUNC_GPIO33_SUBSPIHD 3
|
||||
#define FUNC_GPIO33_FSPIHD 2
|
||||
#define FUNC_GPIO33_GPIO33 1
|
||||
#define FUNC_GPIO33_GPIO33_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c)
|
||||
#define FUNC_GPIO34_SPIIO5 4
|
||||
#define FUNC_GPIO34_SUBSPICS0 3
|
||||
#define FUNC_GPIO34_FSPICS0 2
|
||||
#define FUNC_GPIO34_GPIO34 1
|
||||
#define FUNC_GPIO34_GPIO34_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90)
|
||||
#define FUNC_GPIO35_SPIIO6 4
|
||||
#define FUNC_GPIO35_SUBSPID 3
|
||||
#define FUNC_GPIO35_FSPID 2
|
||||
#define FUNC_GPIO35_GPIO35 1
|
||||
#define FUNC_GPIO35_GPIO35_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94)
|
||||
#define FUNC_GPIO36_SPIIO7 4
|
||||
#define FUNC_GPIO36_SUBSPICLK 3
|
||||
#define FUNC_GPIO36_FSPICLK 2
|
||||
#define FUNC_GPIO36_GPIO36 1
|
||||
#define FUNC_GPIO36_GPIO36_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98)
|
||||
#define FUNC_GPIO37_SPIDQS 4
|
||||
#define FUNC_GPIO37_SUBSPIQ 3
|
||||
#define FUNC_GPIO37_FSPIQ 2
|
||||
#define FUNC_GPIO37_GPIO37 1
|
||||
#define FUNC_GPIO37_GPIO37_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c)
|
||||
#define FUNC_GPIO38_SUBSPIWP 3
|
||||
#define FUNC_GPIO38_FSPIWP 2
|
||||
#define FUNC_GPIO38_GPIO38 1
|
||||
#define FUNC_GPIO38_GPIO38_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0)
|
||||
#define FUNC_MTCK_SUBSPICS1 3
|
||||
#define FUNC_MTCK_CLK_OUT3 2
|
||||
#define FUNC_MTCK_GPIO39 1
|
||||
#define FUNC_MTCK_MTCK 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4)
|
||||
#define FUNC_MTDO_CLK_OUT2 2
|
||||
#define FUNC_MTDO_GPIO40 1
|
||||
#define FUNC_MTDO_MTDO 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8)
|
||||
#define FUNC_MTDI_CLK_OUT1 2
|
||||
#define FUNC_MTDI_GPIO41 1
|
||||
#define FUNC_MTDI_MTDI 0
|
||||
|
||||
#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac)
|
||||
#define FUNC_MTMS_GPIO42 1
|
||||
#define FUNC_MTMS_MTMS 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0)
|
||||
#define FUNC_U0TXD_CLK_OUT1 2
|
||||
#define FUNC_U0TXD_GPIO43 1
|
||||
#define FUNC_U0TXD_U0TXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4)
|
||||
#define FUNC_U0RXD_CLK_OUT2 2
|
||||
#define FUNC_U0RXD_GPIO44 1
|
||||
#define FUNC_U0RXD_U0RXD 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8)
|
||||
#define FUNC_GPIO45_GPIO45 1
|
||||
#define FUNC_GPIO45_GPIO45_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc)
|
||||
#define FUNC_GPIO46_GPIO46 1
|
||||
#define FUNC_GPIO46_GPIO46_0 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICLK_P_U (REG_IO_MUX_BASE +0xc0)
|
||||
#define FUNC_SPICLK_P_SUBSPICLK_DIFF 2
|
||||
#define FUNC_SPICLK_P_GPIO47 1
|
||||
#define FUNC_SPICLK_P_SPICLK_DIFF 0
|
||||
|
||||
#define PERIPHS_IO_MUX_SPICLK_N_U (REG_IO_MUX_BASE +0xc4)
|
||||
#define FUNC_SPICLK_N_SUBSPICLK_DIFF 2
|
||||
#define FUNC_SPICLK_N_GPIO48 1
|
||||
#define FUNC_SPICLK_N_SPICLK_DIFF 0
|
||||
|
||||
|
||||
#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc)
|
||||
#define IO_MUX_DATE 0xFFFFFFFF
|
||||
#define IO_MUX_DATE_S 0
|
||||
#define IO_MUX_DATE_VERSION 0x1907160
|
||||
840
components/soc/soc/esp32s3/include/soc/lcd_cam_reg.h
Normal file
840
components/soc/soc/esp32s3/include/soc/lcd_cam_reg.h
Normal file
|
|
@ -0,0 +1,840 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x000)
|
||||
/* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: Set this bit to enable clk gate*/
|
||||
#define LCD_CAM_CLK_EN (BIT(31))
|
||||
#define LCD_CAM_CLK_EN_M (BIT(31))
|
||||
#define LCD_CAM_CLK_EN_V 0x1
|
||||
#define LCD_CAM_CLK_EN_S 31
|
||||
/* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
|
||||
/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
|
||||
#define LCD_CAM_LCD_CLK_SEL 0x00000003
|
||||
#define LCD_CAM_LCD_CLK_SEL_M ((LCD_CAM_LCD_CLK_SEL_V) << (LCD_CAM_LCD_CLK_SEL_S))
|
||||
#define LCD_CAM_LCD_CLK_SEL_V 0x3
|
||||
#define LCD_CAM_LCD_CLK_SEL_S 29
|
||||
/* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider denominator value*/
|
||||
#define LCD_CAM_LCD_CLKM_DIV_A 0x0000003F
|
||||
#define LCD_CAM_LCD_CLKM_DIV_A_M ((LCD_CAM_LCD_CLKM_DIV_A_V) << (LCD_CAM_LCD_CLKM_DIV_A_S))
|
||||
#define LCD_CAM_LCD_CLKM_DIV_A_V 0x3F
|
||||
#define LCD_CAM_LCD_CLKM_DIV_A_S 23
|
||||
/* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider numerator value*/
|
||||
#define LCD_CAM_LCD_CLKM_DIV_B 0x0000003F
|
||||
#define LCD_CAM_LCD_CLKM_DIV_B_M ((LCD_CAM_LCD_CLKM_DIV_B_V) << (LCD_CAM_LCD_CLKM_DIV_B_S))
|
||||
#define LCD_CAM_LCD_CLKM_DIV_B_V 0x3F
|
||||
#define LCD_CAM_LCD_CLKM_DIV_B_S 17
|
||||
/* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
|
||||
/*description: Integral LCD clock divider value*/
|
||||
#define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FF
|
||||
#define LCD_CAM_LCD_CLKM_DIV_NUM_M ((LCD_CAM_LCD_CLKM_DIV_NUM_V) << (LCD_CAM_LCD_CLKM_DIV_NUM_S))
|
||||
#define LCD_CAM_LCD_CLKM_DIV_NUM_V 0xFF
|
||||
#define LCD_CAM_LCD_CLKM_DIV_NUM_S 9
|
||||
/* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */
|
||||
/*description: */
|
||||
#define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8))
|
||||
#define LCD_CAM_LCD_CK_OUT_EDGE_M (BIT(8))
|
||||
#define LCD_CAM_LCD_CK_OUT_EDGE_V 0x1
|
||||
#define LCD_CAM_LCD_CK_OUT_EDGE_S 8
|
||||
/* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.*/
|
||||
#define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7))
|
||||
#define LCD_CAM_LCD_CK_IDLE_EDGE_M (BIT(7))
|
||||
#define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x1
|
||||
#define LCD_CAM_LCD_CK_IDLE_EDGE_S 7
|
||||
/* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */
|
||||
/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
|
||||
#define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6))
|
||||
#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (BIT(6))
|
||||
#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x1
|
||||
#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6
|
||||
/* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */
|
||||
/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
|
||||
#define LCD_CAM_LCD_CLKCNT_N 0x0000003F
|
||||
#define LCD_CAM_LCD_CLKCNT_N_M ((LCD_CAM_LCD_CLKCNT_N_V) << (LCD_CAM_LCD_CLKCNT_N_S))
|
||||
#define LCD_CAM_LCD_CLKCNT_N_V 0x3F
|
||||
#define LCD_CAM_LCD_CLKCNT_N_S 0
|
||||
|
||||
#define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x004)
|
||||
/* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
|
||||
/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
|
||||
#define LCD_CAM_CAM_CLK_SEL 0x00000003
|
||||
#define LCD_CAM_CAM_CLK_SEL_M ((LCD_CAM_CAM_CLK_SEL_V) << (LCD_CAM_CAM_CLK_SEL_S))
|
||||
#define LCD_CAM_CAM_CLK_SEL_V 0x3
|
||||
#define LCD_CAM_CAM_CLK_SEL_S 29
|
||||
/* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider denominator value*/
|
||||
#define LCD_CAM_CAM_CLKM_DIV_A 0x0000003F
|
||||
#define LCD_CAM_CAM_CLKM_DIV_A_M ((LCD_CAM_CAM_CLKM_DIV_A_V) << (LCD_CAM_CAM_CLKM_DIV_A_S))
|
||||
#define LCD_CAM_CAM_CLKM_DIV_A_V 0x3F
|
||||
#define LCD_CAM_CAM_CLKM_DIV_A_S 23
|
||||
/* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */
|
||||
/*description: Fractional clock divider numerator value*/
|
||||
#define LCD_CAM_CAM_CLKM_DIV_B 0x0000003F
|
||||
#define LCD_CAM_CAM_CLKM_DIV_B_M ((LCD_CAM_CAM_CLKM_DIV_B_V) << (LCD_CAM_CAM_CLKM_DIV_B_S))
|
||||
#define LCD_CAM_CAM_CLKM_DIV_B_V 0x3F
|
||||
#define LCD_CAM_CAM_CLKM_DIV_B_S 17
|
||||
/* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */
|
||||
/*description: Integral Camera clock divider value*/
|
||||
#define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FF
|
||||
#define LCD_CAM_CAM_CLKM_DIV_NUM_M ((LCD_CAM_CAM_CLKM_DIV_NUM_V) << (LCD_CAM_CAM_CLKM_DIV_NUM_S))
|
||||
#define LCD_CAM_CAM_CLKM_DIV_NUM_V 0xFF
|
||||
#define LCD_CAM_CAM_CLKM_DIV_NUM_S 9
|
||||
/* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */
|
||||
/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled
|
||||
by reg_cam_rec_data_cyclelen.*/
|
||||
#define LCD_CAM_CAM_VS_EOF_EN (BIT(8))
|
||||
#define LCD_CAM_CAM_VS_EOF_EN_M (BIT(8))
|
||||
#define LCD_CAM_CAM_VS_EOF_EN_V 0x1
|
||||
#define LCD_CAM_CAM_VS_EOF_EN_S 8
|
||||
/* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable to generate CAM_HS_INT. 0: Disable.*/
|
||||
#define LCD_CAM_CAM_LINE_INT_EN (BIT(7))
|
||||
#define LCD_CAM_CAM_LINE_INT_EN_M (BIT(7))
|
||||
#define LCD_CAM_CAM_LINE_INT_EN_V 0x1
|
||||
#define LCD_CAM_CAM_LINE_INT_EN_S 7
|
||||
/* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */
|
||||
/*description: 1: invert data byte order only valid in 2 byte mode. 0: Not change.*/
|
||||
#define LCD_CAM_CAM_BIT_ORDER (BIT(6))
|
||||
#define LCD_CAM_CAM_BIT_ORDER_M (BIT(6))
|
||||
#define LCD_CAM_CAM_BIT_ORDER_V 0x1
|
||||
#define LCD_CAM_CAM_BIT_ORDER_S 6
|
||||
/* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */
|
||||
/*description: 1: Change data bit order change CAM_DATA_in[7:0] to CAM_DATA_in[0:7]
|
||||
in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/
|
||||
#define LCD_CAM_CAM_BYTE_ORDER (BIT(5))
|
||||
#define LCD_CAM_CAM_BYTE_ORDER_M (BIT(5))
|
||||
#define LCD_CAM_CAM_BYTE_ORDER_V 0x1
|
||||
#define LCD_CAM_CAM_BYTE_ORDER_S 5
|
||||
/* LCD_CAM_CAM_UPDATE_REG : R/W ;bitpos:[4] ;default: 1'h0 ; */
|
||||
/*description: 1: Update Camera registers will be cleared by hardware. 0 : Not care.*/
|
||||
#define LCD_CAM_CAM_UPDATE_REG (BIT(4))
|
||||
#define LCD_CAM_CAM_UPDATE_REG_M (BIT(4))
|
||||
#define LCD_CAM_CAM_UPDATE_REG_V 0x1
|
||||
#define LCD_CAM_CAM_UPDATE_REG_S 4
|
||||
/* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */
|
||||
/*description: Filter threshold value for CAM_VSYNC signal.*/
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_THRES 0x00000007
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V) << (LCD_CAM_CAM_VSYNC_FILTER_THRES_S))
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x7
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1
|
||||
/* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */
|
||||
/*description: Camera stop enable signal 1: camera stops when DMA Rx FIFO is
|
||||
full. 0: Not stop.*/
|
||||
#define LCD_CAM_CAM_STOP_EN (BIT(0))
|
||||
#define LCD_CAM_CAM_STOP_EN_M (BIT(0))
|
||||
#define LCD_CAM_CAM_STOP_EN_V 0x1
|
||||
#define LCD_CAM_CAM_STOP_EN_S 0
|
||||
|
||||
#define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x008)
|
||||
/* LCD_CAM_CAM_AFIFO_RESET : WO ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: Camera AFIFO reset signal.*/
|
||||
#define LCD_CAM_CAM_AFIFO_RESET (BIT(31))
|
||||
#define LCD_CAM_CAM_AFIFO_RESET_M (BIT(31))
|
||||
#define LCD_CAM_CAM_AFIFO_RESET_V 0x1
|
||||
#define LCD_CAM_CAM_AFIFO_RESET_S 31
|
||||
/* LCD_CAM_CAM_RESET : WO ;bitpos:[30] ;default: 1'h0 ; */
|
||||
/*description: Camera module reset signal.*/
|
||||
#define LCD_CAM_CAM_RESET (BIT(30))
|
||||
#define LCD_CAM_CAM_RESET_M (BIT(30))
|
||||
#define LCD_CAM_CAM_RESET_V 0x1
|
||||
#define LCD_CAM_CAM_RESET_S 30
|
||||
/* LCD_CAM_CAM_START : R/W ;bitpos:[29] ;default: 1'h0 ; */
|
||||
/*description: Camera module start signal.*/
|
||||
#define LCD_CAM_CAM_START (BIT(29))
|
||||
#define LCD_CAM_CAM_START_M (BIT(29))
|
||||
#define LCD_CAM_CAM_START_V 0x1
|
||||
#define LCD_CAM_CAM_START_S 29
|
||||
/* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */
|
||||
/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is
|
||||
1. 0: Input control signals are CAM_DE and CAM_VSYNC*/
|
||||
#define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28))
|
||||
#define LCD_CAM_CAM_VH_DE_MODE_EN_M (BIT(28))
|
||||
#define LCD_CAM_CAM_VH_DE_MODE_EN_V 0x1
|
||||
#define LCD_CAM_CAM_VH_DE_MODE_EN_S 28
|
||||
/* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */
|
||||
/*description: CAM_VSYNC invert enable signal valid in high level.*/
|
||||
#define LCD_CAM_CAM_VSYNC_INV (BIT(27))
|
||||
#define LCD_CAM_CAM_VSYNC_INV_M (BIT(27))
|
||||
#define LCD_CAM_CAM_VSYNC_INV_V 0x1
|
||||
#define LCD_CAM_CAM_VSYNC_INV_S 27
|
||||
/* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */
|
||||
/*description: CAM_HSYNC invert enable signal valid in high level.*/
|
||||
#define LCD_CAM_CAM_HSYNC_INV (BIT(26))
|
||||
#define LCD_CAM_CAM_HSYNC_INV_M (BIT(26))
|
||||
#define LCD_CAM_CAM_HSYNC_INV_V 0x1
|
||||
#define LCD_CAM_CAM_HSYNC_INV_S 26
|
||||
/* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: CAM_DE invert enable signal valid in high level.*/
|
||||
#define LCD_CAM_CAM_DE_INV (BIT(25))
|
||||
#define LCD_CAM_CAM_DE_INV_M (BIT(25))
|
||||
#define LCD_CAM_CAM_DE_INV_V 0x1
|
||||
#define LCD_CAM_CAM_DE_INV_S 25
|
||||
/* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */
|
||||
/*description: 1: The bit number of input data is 9~16. 0: The bit number of
|
||||
input data is 0~8.*/
|
||||
#define LCD_CAM_CAM_2BYTE_EN (BIT(24))
|
||||
#define LCD_CAM_CAM_2BYTE_EN_M (BIT(24))
|
||||
#define LCD_CAM_CAM_2BYTE_EN_V 0x1
|
||||
#define LCD_CAM_CAM_2BYTE_EN_S 24
|
||||
/* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable CAM_VSYNC filter function. 0: bypass.*/
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23))
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_EN_M (BIT(23))
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x1
|
||||
#define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23
|
||||
/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */
|
||||
/*description: 1: Invert the input signal CAM_PCLK. 0: Not invert.*/
|
||||
#define LCD_CAM_CAM_CLK_INV (BIT(21))
|
||||
#define LCD_CAM_CAM_CLK_INV_M (BIT(21))
|
||||
#define LCD_CAM_CAM_CLK_INV_V 0x1
|
||||
#define LCD_CAM_CAM_CLK_INV_S 21
|
||||
/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[20:14] ;default: 7'h0 ; */
|
||||
/*description: The line number minus 1 to generate cam_hs_int.*/
|
||||
#define LCD_CAM_CAM_LINE_INT_NUM 0x0000007F
|
||||
#define LCD_CAM_CAM_LINE_INT_NUM_M ((LCD_CAM_CAM_LINE_INT_NUM_V) << (LCD_CAM_CAM_LINE_INT_NUM_S))
|
||||
#define LCD_CAM_CAM_LINE_INT_NUM_V 0x7F
|
||||
#define LCD_CAM_CAM_LINE_INT_NUM_S 14
|
||||
/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
|
||||
/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
|
||||
#define LCD_CAM_CAM_REC_DATA_BYTELEN 0x00003FFF
|
||||
#define LCD_CAM_CAM_REC_DATA_BYTELEN_M ((LCD_CAM_CAM_REC_DATA_BYTELEN_V) << (LCD_CAM_CAM_REC_DATA_BYTELEN_S))
|
||||
#define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0x3FFF
|
||||
#define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0
|
||||
|
||||
#define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x00C)
|
||||
/* LCD_CAM_CAM_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: 0: Bypass converter. 1: Enable converter.*/
|
||||
#define LCD_CAM_CAM_CONV_BYPASS (BIT(31))
|
||||
#define LCD_CAM_CAM_CONV_BYPASS_M (BIT(31))
|
||||
#define LCD_CAM_CAM_CONV_BYPASS_V 0x1
|
||||
#define LCD_CAM_CAM_CONV_BYPASS_S 31
|
||||
/* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: 0: YUV to RGB. 1: RGB to YUV.*/
|
||||
#define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30))
|
||||
#define LCD_CAM_CAM_CONV_TRANS_MODE_M (BIT(30))
|
||||
#define LCD_CAM_CAM_CONV_TRANS_MODE_V 0x1
|
||||
#define LCD_CAM_CAM_CONV_TRANS_MODE_S 30
|
||||
/* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: 0: 16bits mode. 1: 8bits mode.*/
|
||||
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29))
|
||||
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (BIT(29))
|
||||
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x1
|
||||
#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29
|
||||
/* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full*/
|
||||
#define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28))
|
||||
#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (BIT(28))
|
||||
#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x1
|
||||
#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28
|
||||
/* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full*/
|
||||
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27))
|
||||
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (BIT(27))
|
||||
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x1
|
||||
#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27
|
||||
/* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: 0:BT601. 1:BT709.*/
|
||||
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26))
|
||||
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (BIT(26))
|
||||
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x1
|
||||
#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26
|
||||
/* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
|
||||
/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode
|
||||
decides the yuv mode of Data_in*/
|
||||
#define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003
|
||||
#define LCD_CAM_CAM_CONV_YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV_MODE_V) << (LCD_CAM_CAM_CONV_YUV_MODE_S))
|
||||
#define LCD_CAM_CAM_CONV_YUV_MODE_V 0x3
|
||||
#define LCD_CAM_CAM_CONV_YUV_MODE_S 24
|
||||
/* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
|
||||
/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable
|
||||
yuv2yuv mode trans_mode must be set to 1.*/
|
||||
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003
|
||||
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V) << (LCD_CAM_CAM_CONV_YUV2YUV_MODE_S))
|
||||
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x3
|
||||
#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22
|
||||
/* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */
|
||||
/*description: 1:invert every two 8bits input data. 2. disabled.*/
|
||||
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21))
|
||||
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (BIT(21))
|
||||
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x1
|
||||
#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21
|
||||
|
||||
#define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x010)
|
||||
/* LCD_CAM_LCD_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: 0: Bypass converter. 1: Enable converter.*/
|
||||
#define LCD_CAM_LCD_CONV_BYPASS (BIT(31))
|
||||
#define LCD_CAM_LCD_CONV_BYPASS_M (BIT(31))
|
||||
#define LCD_CAM_LCD_CONV_BYPASS_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_BYPASS_S 31
|
||||
/* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: 0: YUV to RGB. 1: RGB to YUV.*/
|
||||
#define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30))
|
||||
#define LCD_CAM_LCD_CONV_TRANS_MODE_M (BIT(30))
|
||||
#define LCD_CAM_LCD_CONV_TRANS_MODE_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_TRANS_MODE_S 30
|
||||
/* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: 0: 16bits mode. 1: 8bits mode.*/
|
||||
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29))
|
||||
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (BIT(29))
|
||||
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29
|
||||
/* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full*/
|
||||
#define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28))
|
||||
#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (BIT(28))
|
||||
#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28
|
||||
/* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full*/
|
||||
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27))
|
||||
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (BIT(27))
|
||||
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27
|
||||
/* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: 0:BT601. 1:BT709.*/
|
||||
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26))
|
||||
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (BIT(26))
|
||||
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26
|
||||
/* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */
|
||||
/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode
|
||||
decides the yuv mode of Data_in*/
|
||||
#define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003
|
||||
#define LCD_CAM_LCD_CONV_YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV_MODE_V) << (LCD_CAM_LCD_CONV_YUV_MODE_S))
|
||||
#define LCD_CAM_LCD_CONV_YUV_MODE_V 0x3
|
||||
#define LCD_CAM_LCD_CONV_YUV_MODE_S 24
|
||||
/* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */
|
||||
/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable
|
||||
yuv2yuv mode trans_mode must be set to 1.*/
|
||||
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003
|
||||
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V) << (LCD_CAM_LCD_CONV_YUV2YUV_MODE_S))
|
||||
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x3
|
||||
#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22
|
||||
/* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */
|
||||
/*description: 0: txtorx mode off. 1: txtorx mode on.*/
|
||||
#define LCD_CAM_LCD_CONV_TXTORX (BIT(21))
|
||||
#define LCD_CAM_LCD_CONV_TXTORX_M (BIT(21))
|
||||
#define LCD_CAM_LCD_CONV_TXTORX_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_TXTORX_S 21
|
||||
/* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */
|
||||
/*description: 1:invert every two 8bits input data. 2. disabled.*/
|
||||
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20))
|
||||
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (BIT(20))
|
||||
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V 0x1
|
||||
#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S 20
|
||||
|
||||
#define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x014)
|
||||
/* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */
|
||||
/*description: The cycle length of command phase*/
|
||||
#define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31))
|
||||
#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (BIT(31))
|
||||
#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V 0x1
|
||||
#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31
|
||||
/* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */
|
||||
/*description: The dummy cycle length minus 1.*/
|
||||
#define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003
|
||||
#define LCD_CAM_LCD_DUMMY_CYCLELEN_M ((LCD_CAM_LCD_DUMMY_CYCLELEN_V) << (LCD_CAM_LCD_DUMMY_CYCLELEN_S))
|
||||
#define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x3
|
||||
#define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29
|
||||
/* LCD_CAM_LCD_RESET : WO ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: The value of command.*/
|
||||
#define LCD_CAM_LCD_RESET (BIT(28))
|
||||
#define LCD_CAM_LCD_RESET_M (BIT(28))
|
||||
#define LCD_CAM_LCD_RESET_V 0x1
|
||||
#define LCD_CAM_LCD_RESET_S 28
|
||||
/* LCD_CAM_LCD_START : R/W ;bitpos:[27] ;default: 1'h0 ; */
|
||||
/*description: LCD start sending data enable signal valid in high level.*/
|
||||
#define LCD_CAM_LCD_START (BIT(27))
|
||||
#define LCD_CAM_LCD_START_M (BIT(27))
|
||||
#define LCD_CAM_LCD_START_V 0x1
|
||||
#define LCD_CAM_LCD_START_S 27
|
||||
/* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */
|
||||
/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
|
||||
#define LCD_CAM_LCD_CMD (BIT(26))
|
||||
#define LCD_CAM_LCD_CMD_M (BIT(26))
|
||||
#define LCD_CAM_LCD_CMD_V 0x1
|
||||
#define LCD_CAM_LCD_CMD_S 26
|
||||
/* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */
|
||||
/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
|
||||
#define LCD_CAM_LCD_DUMMY (BIT(25))
|
||||
#define LCD_CAM_LCD_DUMMY_M (BIT(25))
|
||||
#define LCD_CAM_LCD_DUMMY_V 0x1
|
||||
#define LCD_CAM_LCD_DUMMY_S 25
|
||||
/* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */
|
||||
/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
|
||||
#define LCD_CAM_LCD_DOUT (BIT(24))
|
||||
#define LCD_CAM_LCD_DOUT_M (BIT(24))
|
||||
#define LCD_CAM_LCD_DOUT_V 0x1
|
||||
#define LCD_CAM_LCD_DOUT_S 24
|
||||
/* LCD_CAM_LCD_2BYTE_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */
|
||||
/*description: 1: The bit number of output LCD data is 9~16. 0: The bit number
|
||||
of output LCD data is 0~8.*/
|
||||
#define LCD_CAM_LCD_2BYTE_EN (BIT(23))
|
||||
#define LCD_CAM_LCD_2BYTE_EN_M (BIT(23))
|
||||
#define LCD_CAM_LCD_2BYTE_EN_V 0x1
|
||||
#define LCD_CAM_LCD_2BYTE_EN_S 23
|
||||
/* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */
|
||||
/*description: 1: invert data byte order only valid in 2 byte mode. 0: Not change.*/
|
||||
#define LCD_CAM_LCD_BYTE_ORDER (BIT(22))
|
||||
#define LCD_CAM_LCD_BYTE_ORDER_M (BIT(22))
|
||||
#define LCD_CAM_LCD_BYTE_ORDER_V 0x1
|
||||
#define LCD_CAM_LCD_BYTE_ORDER_S 22
|
||||
/* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[21] ;default: 1'h0 ; */
|
||||
/*description: 1: Change data bit order change LCD_DATA_out[7:0] to LCD_DATA_out[0:7]
|
||||
in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/
|
||||
#define LCD_CAM_LCD_BIT_ORDER (BIT(21))
|
||||
#define LCD_CAM_LCD_BIT_ORDER_M (BIT(21))
|
||||
#define LCD_CAM_LCD_BIT_ORDER_V 0x1
|
||||
#define LCD_CAM_LCD_BIT_ORDER_S 21
|
||||
/* LCD_CAM_LCD_UPDATE_REG : R/W ;bitpos:[20] ;default: 1'h0 ; */
|
||||
/*description: 1: Update LCD registers will be cleared by hardware. 0 : Not care.*/
|
||||
#define LCD_CAM_LCD_UPDATE_REG (BIT(20))
|
||||
#define LCD_CAM_LCD_UPDATE_REG_M (BIT(20))
|
||||
#define LCD_CAM_LCD_UPDATE_REG_V 0x1
|
||||
#define LCD_CAM_LCD_UPDATE_REG_S 20
|
||||
/* LCD_CAM_LCD_8BITS_ORDER : R/W ;bitpos:[19] ;default: 1'h0 ; */
|
||||
/*description: 1: invert every two data byte valid in 1 byte mode. 0: Not change.*/
|
||||
#define LCD_CAM_LCD_8BITS_ORDER (BIT(19))
|
||||
#define LCD_CAM_LCD_8BITS_ORDER_M (BIT(19))
|
||||
#define LCD_CAM_LCD_8BITS_ORDER_V 0x1
|
||||
#define LCD_CAM_LCD_8BITS_ORDER_S 19
|
||||
/* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */
|
||||
/*description: LCD always output when LCD is in LCD_DOUT state unless reg_lcd_start
|
||||
is cleared or reg_lcd_reset is set.*/
|
||||
#define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13))
|
||||
#define LCD_CAM_LCD_ALWAYS_OUT_EN_M (BIT(13))
|
||||
#define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x1
|
||||
#define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13
|
||||
/* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */
|
||||
/*description: The output data cycles minus 1 of LCD module.*/
|
||||
#define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFF
|
||||
#define LCD_CAM_LCD_DOUT_CYCLELEN_M ((LCD_CAM_LCD_DOUT_CYCLELEN_V) << (LCD_CAM_LCD_DOUT_CYCLELEN_S))
|
||||
#define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x1FFF
|
||||
#define LCD_CAM_LCD_DOUT_CYCLELEN_S 0
|
||||
|
||||
#define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x018)
|
||||
/* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */
|
||||
/*description: The default value of LCD_CD.*/
|
||||
#define LCD_CAM_LCD_CD_IDLE_EDGE (BIT(31))
|
||||
#define LCD_CAM_LCD_CD_IDLE_EDGE_M (BIT(31))
|
||||
#define LCD_CAM_LCD_CD_IDLE_EDGE_V 0x1
|
||||
#define LCD_CAM_LCD_CD_IDLE_EDGE_S 31
|
||||
/* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD
|
||||
state. 0: LCD_CD = reg_cd_idle_edge.*/
|
||||
#define LCD_CAM_LCD_CD_CMD_SET (BIT(30))
|
||||
#define LCD_CAM_LCD_CD_CMD_SET_M (BIT(30))
|
||||
#define LCD_CAM_LCD_CD_CMD_SET_V 0x1
|
||||
#define LCD_CAM_LCD_CD_CMD_SET_S 30
|
||||
/* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */
|
||||
/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY
|
||||
state. 0: LCD_CD = reg_cd_idle_edge.*/
|
||||
#define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29))
|
||||
#define LCD_CAM_LCD_CD_DUMMY_SET_M (BIT(29))
|
||||
#define LCD_CAM_LCD_CD_DUMMY_SET_V 0x1
|
||||
#define LCD_CAM_LCD_CD_DUMMY_SET_S 29
|
||||
/* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */
|
||||
/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT
|
||||
state. 0: LCD_CD = reg_cd_idle_edge.*/
|
||||
#define LCD_CAM_LCD_CD_DATA_SET (BIT(28))
|
||||
#define LCD_CAM_LCD_CD_DATA_SET_M (BIT(28))
|
||||
#define LCD_CAM_LCD_CD_DATA_SET_V 0x1
|
||||
#define LCD_CAM_LCD_CD_DATA_SET_S 28
|
||||
/* LCD_CAM_LCD_AFIFO_RESET : WO ;bitpos:[27] ;default: 1'b0 ; */
|
||||
/*description: LCD AFIFO reset signal.*/
|
||||
#define LCD_CAM_LCD_AFIFO_RESET (BIT(27))
|
||||
#define LCD_CAM_LCD_AFIFO_RESET_M (BIT(27))
|
||||
#define LCD_CAM_LCD_AFIFO_RESET_V 0x1
|
||||
#define LCD_CAM_LCD_AFIFO_RESET_S 27
|
||||
/* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */
|
||||
/*description: 1: Enable blank region when LCD sends data out. 0: No blank region.*/
|
||||
#define LCD_CAM_LCD_BK_EN (BIT(26))
|
||||
#define LCD_CAM_LCD_BK_EN_M (BIT(26))
|
||||
#define LCD_CAM_LCD_BK_EN_V 0x1
|
||||
#define LCD_CAM_LCD_BK_EN_S 26
|
||||
/* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */
|
||||
/*description: 1: Send the next frame data when the current frame is sent out.
|
||||
0: LCD stops when the current frame is sent out.*/
|
||||
#define LCD_CAM_LCD_NEXT_FRAME_EN (BIT(25))
|
||||
#define LCD_CAM_LCD_NEXT_FRAME_EN_M (BIT(25))
|
||||
#define LCD_CAM_LCD_NEXT_FRAME_EN_V 0x1
|
||||
#define LCD_CAM_LCD_NEXT_FRAME_EN_S 25
|
||||
/* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */
|
||||
/*description: The vertical back blank region cycle length minus 1 in LCD RGB
|
||||
mode or the hold time cycle length in LCD non-RGB mode.*/
|
||||
#define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFF
|
||||
#define LCD_CAM_LCD_VBK_CYCLELEN_M ((LCD_CAM_LCD_VBK_CYCLELEN_V) << (LCD_CAM_LCD_VBK_CYCLELEN_S))
|
||||
#define LCD_CAM_LCD_VBK_CYCLELEN_V 0x1FFF
|
||||
#define LCD_CAM_LCD_VBK_CYCLELEN_S 12
|
||||
/* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */
|
||||
/*description: The setup cycle length minus 1 in LCD non-RGB mode.*/
|
||||
#define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003F
|
||||
#define LCD_CAM_LCD_VFK_CYCLELEN_M ((LCD_CAM_LCD_VFK_CYCLELEN_V) << (LCD_CAM_LCD_VFK_CYCLELEN_S))
|
||||
#define LCD_CAM_LCD_VFK_CYCLELEN_V 0x3F
|
||||
#define LCD_CAM_LCD_VFK_CYCLELEN_S 6
|
||||
/* LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W ;bitpos:[5:1] ;default: 5'd11 ; */
|
||||
/*description: The awfull threshold number of lcd_afifo.*/
|
||||
#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM 0x0000001F
|
||||
#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M ((LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V) << (LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S))
|
||||
#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V 0x1F
|
||||
#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S 1
|
||||
|
||||
#define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x01C)
|
||||
/* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: 1: Enable reg mode input vsync*/
|
||||
#define LCD_CAM_LCD_RGB_MODE_EN (BIT(31))
|
||||
#define LCD_CAM_LCD_RGB_MODE_EN_M (BIT(31))
|
||||
#define LCD_CAM_LCD_RGB_MODE_EN_V 0x1
|
||||
#define LCD_CAM_LCD_RGB_MODE_EN_S 31
|
||||
/* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */
|
||||
/*description: It is the vertical total height of a frame.*/
|
||||
#define LCD_CAM_LCD_VT_HEIGHT 0x000003FF
|
||||
#define LCD_CAM_LCD_VT_HEIGHT_M ((LCD_CAM_LCD_VT_HEIGHT_V) << (LCD_CAM_LCD_VT_HEIGHT_S))
|
||||
#define LCD_CAM_LCD_VT_HEIGHT_V 0x3FF
|
||||
#define LCD_CAM_LCD_VT_HEIGHT_S 21
|
||||
/* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */
|
||||
/*description: It is the vertical active height of a frame.*/
|
||||
#define LCD_CAM_LCD_VA_HEIGHT 0x000003FF
|
||||
#define LCD_CAM_LCD_VA_HEIGHT_M ((LCD_CAM_LCD_VA_HEIGHT_V) << (LCD_CAM_LCD_VA_HEIGHT_S))
|
||||
#define LCD_CAM_LCD_VA_HEIGHT_V 0x3FF
|
||||
#define LCD_CAM_LCD_VA_HEIGHT_S 11
|
||||
/* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */
|
||||
/*description: It is the horizontal blank front porch of a frame.*/
|
||||
#define LCD_CAM_LCD_HB_FRONT 0x000007FF
|
||||
#define LCD_CAM_LCD_HB_FRONT_M ((LCD_CAM_LCD_HB_FRONT_V) << (LCD_CAM_LCD_HB_FRONT_S))
|
||||
#define LCD_CAM_LCD_HB_FRONT_V 0x7FF
|
||||
#define LCD_CAM_LCD_HB_FRONT_S 0
|
||||
|
||||
#define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x020)
|
||||
/* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */
|
||||
/*description: It is the horizontal total width of a frame.*/
|
||||
#define LCD_CAM_LCD_HT_WIDTH 0x00000FFF
|
||||
#define LCD_CAM_LCD_HT_WIDTH_M ((LCD_CAM_LCD_HT_WIDTH_V) << (LCD_CAM_LCD_HT_WIDTH_S))
|
||||
#define LCD_CAM_LCD_HT_WIDTH_V 0xFFF
|
||||
#define LCD_CAM_LCD_HT_WIDTH_S 20
|
||||
/* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */
|
||||
/*description: It is the horizontal active width of a frame.*/
|
||||
#define LCD_CAM_LCD_HA_WIDTH 0x00000FFF
|
||||
#define LCD_CAM_LCD_HA_WIDTH_M ((LCD_CAM_LCD_HA_WIDTH_V) << (LCD_CAM_LCD_HA_WIDTH_S))
|
||||
#define LCD_CAM_LCD_HA_WIDTH_V 0xFFF
|
||||
#define LCD_CAM_LCD_HA_WIDTH_S 8
|
||||
/* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */
|
||||
/*description: It is the vertical blank front porch of a frame.*/
|
||||
#define LCD_CAM_LCD_VB_FRONT 0x000000FF
|
||||
#define LCD_CAM_LCD_VB_FRONT_M ((LCD_CAM_LCD_VB_FRONT_V) << (LCD_CAM_LCD_VB_FRONT_S))
|
||||
#define LCD_CAM_LCD_VB_FRONT_V 0xFF
|
||||
#define LCD_CAM_LCD_VB_FRONT_S 0
|
||||
|
||||
#define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x024)
|
||||
/* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */
|
||||
/*description: It is the position of LCD_HSYNC active pulse in a line.*/
|
||||
#define LCD_CAM_LCD_HSYNC_POSITION 0x000000FF
|
||||
#define LCD_CAM_LCD_HSYNC_POSITION_M ((LCD_CAM_LCD_HSYNC_POSITION_V) << (LCD_CAM_LCD_HSYNC_POSITION_S))
|
||||
#define LCD_CAM_LCD_HSYNC_POSITION_V 0xFF
|
||||
#define LCD_CAM_LCD_HSYNC_POSITION_S 24
|
||||
/* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */
|
||||
/*description: It is the idle value of LCD_HSYNC.*/
|
||||
#define LCD_CAM_LCD_HSYNC_IDLE_POL (BIT(23))
|
||||
#define LCD_CAM_LCD_HSYNC_IDLE_POL_M (BIT(23))
|
||||
#define LCD_CAM_LCD_HSYNC_IDLE_POL_V 0x1
|
||||
#define LCD_CAM_LCD_HSYNC_IDLE_POL_S 23
|
||||
/* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */
|
||||
/*description: It is the position of LCD_HSYNC active pulse in a line.*/
|
||||
#define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007F
|
||||
#define LCD_CAM_LCD_HSYNC_WIDTH_M ((LCD_CAM_LCD_HSYNC_WIDTH_V) << (LCD_CAM_LCD_HSYNC_WIDTH_S))
|
||||
#define LCD_CAM_LCD_HSYNC_WIDTH_V 0x7F
|
||||
#define LCD_CAM_LCD_HSYNC_WIDTH_S 16
|
||||
/* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */
|
||||
/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB
|
||||
mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode.*/
|
||||
#define LCD_CAM_LCD_HS_BLANK_EN (BIT(9))
|
||||
#define LCD_CAM_LCD_HS_BLANK_EN_M (BIT(9))
|
||||
#define LCD_CAM_LCD_HS_BLANK_EN_V 0x1
|
||||
#define LCD_CAM_LCD_HS_BLANK_EN_S 9
|
||||
/* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */
|
||||
/*description: It is the idle value of LCD_DE.*/
|
||||
#define LCD_CAM_LCD_DE_IDLE_POL (BIT(8))
|
||||
#define LCD_CAM_LCD_DE_IDLE_POL_M (BIT(8))
|
||||
#define LCD_CAM_LCD_DE_IDLE_POL_V 0x1
|
||||
#define LCD_CAM_LCD_DE_IDLE_POL_S 8
|
||||
/* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */
|
||||
/*description: It is the idle value of LCD_VSYNC.*/
|
||||
#define LCD_CAM_LCD_VSYNC_IDLE_POL (BIT(7))
|
||||
#define LCD_CAM_LCD_VSYNC_IDLE_POL_M (BIT(7))
|
||||
#define LCD_CAM_LCD_VSYNC_IDLE_POL_V 0x1
|
||||
#define LCD_CAM_LCD_VSYNC_IDLE_POL_S 7
|
||||
/* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */
|
||||
/*description: It is the position of LCD_VSYNC active pulse in a line.*/
|
||||
#define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007F
|
||||
#define LCD_CAM_LCD_VSYNC_WIDTH_M ((LCD_CAM_LCD_VSYNC_WIDTH_V) << (LCD_CAM_LCD_VSYNC_WIDTH_S))
|
||||
#define LCD_CAM_LCD_VSYNC_WIDTH_V 0x7F
|
||||
#define LCD_CAM_LCD_VSYNC_WIDTH_S 0
|
||||
|
||||
#define LCD_CAM_LCD_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x028)
|
||||
/* LCD_CAM_LCD_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
|
||||
/*description: The LCD write command value.*/
|
||||
#define LCD_CAM_LCD_CMD_VALUE 0xFFFFFFFF
|
||||
#define LCD_CAM_LCD_CMD_VALUE_M ((LCD_CAM_LCD_CMD_VALUE_V) << (LCD_CAM_LCD_CMD_VALUE_S))
|
||||
#define LCD_CAM_LCD_CMD_VALUE_V 0xFFFFFFFF
|
||||
#define LCD_CAM_LCD_CMD_VALUE_S 0
|
||||
|
||||
#define LCD_CAM_LCD_DLY_MODE_REG (DR_REG_LCD_CAM_BASE + 0x030)
|
||||
/* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
|
||||
/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_LCD_VSYNC_MODE 0x00000003
|
||||
#define LCD_CAM_LCD_VSYNC_MODE_M ((LCD_CAM_LCD_VSYNC_MODE_V) << (LCD_CAM_LCD_VSYNC_MODE_S))
|
||||
#define LCD_CAM_LCD_VSYNC_MODE_V 0x3
|
||||
#define LCD_CAM_LCD_VSYNC_MODE_S 6
|
||||
/* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
|
||||
/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_LCD_HSYNC_MODE 0x00000003
|
||||
#define LCD_CAM_LCD_HSYNC_MODE_M ((LCD_CAM_LCD_HSYNC_MODE_V) << (LCD_CAM_LCD_HSYNC_MODE_S))
|
||||
#define LCD_CAM_LCD_HSYNC_MODE_V 0x3
|
||||
#define LCD_CAM_LCD_HSYNC_MODE_S 4
|
||||
/* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
|
||||
/*description: The output LCD_DE is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_LCD_DE_MODE 0x00000003
|
||||
#define LCD_CAM_LCD_DE_MODE_M ((LCD_CAM_LCD_DE_MODE_V) << (LCD_CAM_LCD_DE_MODE_S))
|
||||
#define LCD_CAM_LCD_DE_MODE_V 0x3
|
||||
#define LCD_CAM_LCD_DE_MODE_S 2
|
||||
/* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: The output LCD_CD is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_LCD_CD_MODE 0x00000003
|
||||
#define LCD_CAM_LCD_CD_MODE_M ((LCD_CAM_LCD_CD_MODE_V) << (LCD_CAM_LCD_CD_MODE_S))
|
||||
#define LCD_CAM_LCD_CD_MODE_V 0x3
|
||||
#define LCD_CAM_LCD_CD_MODE_S 0
|
||||
|
||||
#define LCD_CAM_LCD_DATA_DOUT_MODE_REG (DR_REG_LCD_CAM_BASE + 0x038)
|
||||
/* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT15_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT15_MODE_M ((LCD_CAM_DOUT15_MODE_V) << (LCD_CAM_DOUT15_MODE_S))
|
||||
#define LCD_CAM_DOUT15_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT15_MODE_S 30
|
||||
/* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT14_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT14_MODE_M ((LCD_CAM_DOUT14_MODE_V) << (LCD_CAM_DOUT14_MODE_S))
|
||||
#define LCD_CAM_DOUT14_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT14_MODE_S 28
|
||||
/* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT13_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT13_MODE_M ((LCD_CAM_DOUT13_MODE_V) << (LCD_CAM_DOUT13_MODE_S))
|
||||
#define LCD_CAM_DOUT13_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT13_MODE_S 26
|
||||
/* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT12_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT12_MODE_M ((LCD_CAM_DOUT12_MODE_V) << (LCD_CAM_DOUT12_MODE_S))
|
||||
#define LCD_CAM_DOUT12_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT12_MODE_S 24
|
||||
/* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT11_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT11_MODE_M ((LCD_CAM_DOUT11_MODE_V) << (LCD_CAM_DOUT11_MODE_S))
|
||||
#define LCD_CAM_DOUT11_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT11_MODE_S 22
|
||||
/* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT10_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT10_MODE_M ((LCD_CAM_DOUT10_MODE_V) << (LCD_CAM_DOUT10_MODE_S))
|
||||
#define LCD_CAM_DOUT10_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT10_MODE_S 20
|
||||
/* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT9_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT9_MODE_M ((LCD_CAM_DOUT9_MODE_V) << (LCD_CAM_DOUT9_MODE_S))
|
||||
#define LCD_CAM_DOUT9_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT9_MODE_S 18
|
||||
/* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT8_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT8_MODE_M ((LCD_CAM_DOUT8_MODE_V) << (LCD_CAM_DOUT8_MODE_S))
|
||||
#define LCD_CAM_DOUT8_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT8_MODE_S 16
|
||||
/* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT7_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT7_MODE_M ((LCD_CAM_DOUT7_MODE_V) << (LCD_CAM_DOUT7_MODE_S))
|
||||
#define LCD_CAM_DOUT7_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT7_MODE_S 14
|
||||
/* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT6_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT6_MODE_M ((LCD_CAM_DOUT6_MODE_V) << (LCD_CAM_DOUT6_MODE_S))
|
||||
#define LCD_CAM_DOUT6_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT6_MODE_S 12
|
||||
/* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT5_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT5_MODE_M ((LCD_CAM_DOUT5_MODE_V) << (LCD_CAM_DOUT5_MODE_S))
|
||||
#define LCD_CAM_DOUT5_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT5_MODE_S 10
|
||||
/* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT4_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT4_MODE_M ((LCD_CAM_DOUT4_MODE_V) << (LCD_CAM_DOUT4_MODE_S))
|
||||
#define LCD_CAM_DOUT4_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT4_MODE_S 8
|
||||
/* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT3_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT3_MODE_M ((LCD_CAM_DOUT3_MODE_V) << (LCD_CAM_DOUT3_MODE_S))
|
||||
#define LCD_CAM_DOUT3_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT3_MODE_S 6
|
||||
/* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT2_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT2_MODE_M ((LCD_CAM_DOUT2_MODE_V) << (LCD_CAM_DOUT2_MODE_S))
|
||||
#define LCD_CAM_DOUT2_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT2_MODE_S 4
|
||||
/* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT1_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT1_MODE_M ((LCD_CAM_DOUT1_MODE_V) << (LCD_CAM_DOUT1_MODE_S))
|
||||
#define LCD_CAM_DOUT1_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT1_MODE_S 2
|
||||
/* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */
|
||||
/*description: The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
#define LCD_CAM_DOUT0_MODE 0x00000003
|
||||
#define LCD_CAM_DOUT0_MODE_M ((LCD_CAM_DOUT0_MODE_V) << (LCD_CAM_DOUT0_MODE_S))
|
||||
#define LCD_CAM_DOUT0_MODE_V 0x3
|
||||
#define LCD_CAM_DOUT0_MODE_S 0
|
||||
|
||||
#define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x064)
|
||||
/* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The enable bit for Camera line interrupt.*/
|
||||
#define LCD_CAM_CAM_HS_INT_ENA (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_ENA_M (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_ENA_V 0x1
|
||||
#define LCD_CAM_CAM_HS_INT_ENA_S 3
|
||||
/* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The enable bit for Camera frame end interrupt.*/
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ENA_M (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x1
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ENA_S 2
|
||||
/* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The enable bit for lcd transfer end interrupt.*/
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x1
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1
|
||||
/* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The enable bit for LCD frame end interrupt.*/
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ENA_M (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x1
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ENA_S 0
|
||||
|
||||
#define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x068)
|
||||
/* LCD_CAM_CAM_HS_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The raw bit for Camera line interrupt.*/
|
||||
#define LCD_CAM_CAM_HS_INT_RAW (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_RAW_M (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_RAW_V 0x1
|
||||
#define LCD_CAM_CAM_HS_INT_RAW_S 3
|
||||
/* LCD_CAM_CAM_VSYNC_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The raw bit for Camera frame end interrupt.*/
|
||||
#define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_RAW_M (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x1
|
||||
#define LCD_CAM_CAM_VSYNC_INT_RAW_S 2
|
||||
/* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The raw bit for lcd transfer end interrupt.*/
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x1
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1
|
||||
/* LCD_CAM_LCD_VSYNC_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The raw bit for LCD frame end interrupt.*/
|
||||
#define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_RAW_M (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x1
|
||||
#define LCD_CAM_LCD_VSYNC_INT_RAW_S 0
|
||||
|
||||
#define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x06C)
|
||||
/* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The status bit for Camera transfer end interrupt.*/
|
||||
#define LCD_CAM_CAM_HS_INT_ST (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_ST_M (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_ST_V 0x1
|
||||
#define LCD_CAM_CAM_HS_INT_ST_S 3
|
||||
/* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The status bit for Camera frame end interrupt.*/
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ST_M (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ST_V 0x1
|
||||
#define LCD_CAM_CAM_VSYNC_INT_ST_S 2
|
||||
/* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The status bit for lcd transfer end interrupt.*/
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x1
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1
|
||||
/* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The status bit for LCD frame end interrupt.*/
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ST_M (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ST_V 0x1
|
||||
#define LCD_CAM_LCD_VSYNC_INT_ST_S 0
|
||||
|
||||
#define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x070)
|
||||
/* LCD_CAM_CAM_HS_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: The clear bit for Camera line interrupt.*/
|
||||
#define LCD_CAM_CAM_HS_INT_CLR (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_CLR_M (BIT(3))
|
||||
#define LCD_CAM_CAM_HS_INT_CLR_V 0x1
|
||||
#define LCD_CAM_CAM_HS_INT_CLR_S 3
|
||||
/* LCD_CAM_CAM_VSYNC_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: The clear bit for Camera frame end interrupt.*/
|
||||
#define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_CLR_M (BIT(2))
|
||||
#define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x1
|
||||
#define LCD_CAM_CAM_VSYNC_INT_CLR_S 2
|
||||
/* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: The clear bit for lcd transfer end interrupt.*/
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (BIT(1))
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x1
|
||||
#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1
|
||||
/* LCD_CAM_LCD_VSYNC_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: The clear bit for LCD frame end interrupt.*/
|
||||
#define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_CLR_M (BIT(0))
|
||||
#define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x1
|
||||
#define LCD_CAM_LCD_VSYNC_INT_CLR_S 0
|
||||
|
||||
#define LCD_CAM_LC_DATE_REG (DR_REG_LCD_CAM_BASE + 0x0FC)
|
||||
/* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */
|
||||
/*description: LCD_CAM version control register*/
|
||||
#define LCD_CAM_LC_DATE 0x0FFFFFFF
|
||||
#define LCD_CAM_LC_DATE_M ((LCD_CAM_LC_DATE_V) << (LCD_CAM_LC_DATE_S))
|
||||
#define LCD_CAM_LC_DATE_V 0xFFFFFFF
|
||||
#define LCD_CAM_LC_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
300
components/soc/soc/esp32s3/include/soc/lcd_cam_struct.h
Normal file
300
components/soc/soc/esp32s3/include/soc/lcd_cam_struct.h
Normal file
|
|
@ -0,0 +1,300 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_clkcnt_n: 6; /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/
|
||||
uint32_t lcd_clk_equ_sysclk: 1; /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/
|
||||
uint32_t lcd_ck_idle_edge: 1; /*1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.*/
|
||||
uint32_t lcd_ck_out_edge: 1;
|
||||
uint32_t lcd_clkm_div_num: 8; /*Integral LCD clock divider value*/
|
||||
uint32_t lcd_clkm_div_b: 6; /*Fractional clock divider numerator value*/
|
||||
uint32_t lcd_clkm_div_a: 6; /*Fractional clock divider denominator value*/
|
||||
uint32_t lcd_clk_sel: 2; /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
|
||||
uint32_t clk_en: 1; /*Set this bit to enable clk gate*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_clock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cam_stop_en: 1; /*Camera stop enable signal 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/
|
||||
uint32_t cam_vsync_filter_thres: 3; /*Filter threshold value for CAM_VSYNC signal.*/
|
||||
uint32_t cam_update: 1; /*1: Update Camera registers will be cleared by hardware. 0 : Not care.*/
|
||||
uint32_t cam_byte_order: 1; /*1: Change data bit order change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/
|
||||
uint32_t cam_bit_order: 1; /*1: invert data byte order only valid in 2 byte mode. 0: Not change.*/
|
||||
uint32_t cam_line_int_en: 1; /*1: Enable to generate CAM_HS_INT. 0: Disable.*/
|
||||
uint32_t cam_vs_eof_en: 1; /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/
|
||||
uint32_t cam_clkm_div_num: 8; /*Integral Camera clock divider value*/
|
||||
uint32_t cam_clkm_div_b: 6; /*Fractional clock divider numerator value*/
|
||||
uint32_t cam_clkm_div_a: 6; /*Fractional clock divider denominator value*/
|
||||
uint32_t cam_clk_sel: 2; /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cam_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cam_rec_data_bytelen: 14; /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/
|
||||
uint32_t cam_line_int_num: 7; /*The line number minus 1 to generate cam_hs_int.*/
|
||||
uint32_t cam_clk_inv: 1; /*1: Invert the input signal CAM_PCLK. 0: Not invert.*/
|
||||
uint32_t reserved22: 1;
|
||||
uint32_t cam_vsync_filter_en: 1; /*1: Enable CAM_VSYNC filter function. 0: bypass.*/
|
||||
uint32_t cam_2byte_en: 1; /*1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8.*/
|
||||
uint32_t cam_de_inv: 1; /*CAM_DE invert enable signal valid in high level.*/
|
||||
uint32_t cam_hsync_inv: 1; /*CAM_HSYNC invert enable signal valid in high level.*/
|
||||
uint32_t cam_vsync_inv: 1; /*CAM_VSYNC invert enable signal valid in high level.*/
|
||||
uint32_t cam_vh_de_mode_en: 1; /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC*/
|
||||
uint32_t cam_start: 1; /*Camera module start signal.*/
|
||||
uint32_t cam_reset: 1; /*Camera module reset signal.*/
|
||||
uint32_t cam_afifo_reset: 1; /*Camera AFIFO reset signal.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cam_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 21; /*reserved*/
|
||||
uint32_t cam_conv_8bits_data_inv: 1; /*1:invert every two 8bits input data. 2. disabled.*/
|
||||
uint32_t cam_conv_yuv2yuv_mode: 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode trans_mode must be set to 1.*/
|
||||
uint32_t cam_conv_yuv_mode: 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode decides the yuv mode of Data_in*/
|
||||
uint32_t cam_conv_protocol_mode: 1; /*0:BT601. 1:BT709.*/
|
||||
uint32_t cam_conv_data_out_mode: 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
|
||||
uint32_t cam_conv_data_in_mode: 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
|
||||
uint32_t cam_conv_mode_8bits_on: 1; /*0: 16bits mode. 1: 8bits mode.*/
|
||||
uint32_t cam_conv_trans_mode: 1; /*0: YUV to RGB. 1: RGB to YUV.*/
|
||||
uint32_t cam_conv_bypass: 1; /*0: Bypass converter. 1: Enable converter.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cam_rgb_yuv;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 20; /*reserved*/
|
||||
uint32_t lcd_conv_8bits_data_inv: 1; /*1:invert every two 8bits input data. 2. disabled.*/
|
||||
uint32_t lcd_conv_txtorx: 1; /*0: txtorx mode off. 1: txtorx mode on.*/
|
||||
uint32_t lcd_conv_yuv2yuv_mode: 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode trans_mode must be set to 1.*/
|
||||
uint32_t lcd_conv_yuv_mode: 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode decides the yuv mode of Data_in*/
|
||||
uint32_t lcd_conv_protocol_mode: 1; /*0:BT601. 1:BT709.*/
|
||||
uint32_t lcd_conv_data_out_mode: 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/
|
||||
uint32_t lcd_conv_data_in_mode: 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/
|
||||
uint32_t lcd_conv_mode_8bits_on: 1; /*0: 16bits mode. 1: 8bits mode.*/
|
||||
uint32_t lcd_conv_trans_mode: 1; /*0: YUV to RGB. 1: RGB to YUV.*/
|
||||
uint32_t lcd_conv_bypass: 1; /*0: Bypass converter. 1: Enable converter.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_rgb_yuv;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_dout_cyclelen: 13; /*The output data cycles minus 1 of LCD module.*/
|
||||
uint32_t lcd_always_out_en: 1; /*LCD always output when LCD is in LCD_DOUT state unless reg_lcd_start is cleared or reg_lcd_reset is set.*/
|
||||
uint32_t reserved14: 5; /*reserved*/
|
||||
uint32_t lcd_8bits_order: 1; /*1: invert every two data byte valid in 1 byte mode. 0: Not change.*/
|
||||
uint32_t lcd_update: 1; /*1: Update LCD registers will be cleared by hardware. 0 : Not care.*/
|
||||
uint32_t lcd_bit_order: 1; /*1: Change data bit order change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/
|
||||
uint32_t lcd_byte_order: 1; /*1: invert data byte order only valid in 2 byte mode. 0: Not change.*/
|
||||
uint32_t lcd_2byte_en: 1; /*1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8.*/
|
||||
uint32_t lcd_dout: 1; /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/
|
||||
uint32_t lcd_dummy: 1; /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/
|
||||
uint32_t lcd_cmd: 1; /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/
|
||||
uint32_t lcd_start: 1; /*LCD start sending data enable signal valid in high level.*/
|
||||
uint32_t lcd_reset: 1; /*The value of command.*/
|
||||
uint32_t lcd_dummy_cyclelen: 2; /*The dummy cycle length minus 1.*/
|
||||
uint32_t lcd_cmd_2_cycle_en: 1; /*The cycle length of command phase*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_user;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 1; /*reserved*/
|
||||
uint32_t lcd_afifo_threshold_num: 5; /*The awfull threshold number of lcd_afifo.*/
|
||||
uint32_t lcd_vfk_cyclelen: 6; /*The setup cycle length minus 1 in LCD non-RGB mode.*/
|
||||
uint32_t lcd_vbk_cyclelen: 13; /*The vertical back blank region cycle length minus 1 in LCD RGB mode or the hold time cycle length in LCD non-RGB mode.*/
|
||||
uint32_t lcd_next_frame_en: 1; /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/
|
||||
uint32_t lcd_bk_en: 1; /*1: Enable blank region when LCD sends data out. 0: No blank region.*/
|
||||
uint32_t lcd_afifo_reset: 1; /*LCD AFIFO reset signal.*/
|
||||
uint32_t lcd_cd_data_set: 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge.*/
|
||||
uint32_t lcd_cd_dummy_set: 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge.*/
|
||||
uint32_t lcd_cd_cmd_set: 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge.*/
|
||||
uint32_t lcd_cd_idle_edge: 1; /*The default value of LCD_CD.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_misc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_hb_front: 11; /*It is the horizontal blank front porch of a frame.*/
|
||||
uint32_t lcd_va_height: 10; /*It is the vertical active height of a frame.*/
|
||||
uint32_t lcd_vt_height: 10; /*It is the vertical total height of a frame.*/
|
||||
uint32_t lcd_rgb_mode_en: 1; /*1: Enable reg mode input vsync*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_vb_front: 8; /*It is the vertical blank front porch of a frame.*/
|
||||
uint32_t lcd_ha_width: 12; /*It is the horizontal active width of a frame.*/
|
||||
uint32_t lcd_ht_width: 12; /*It is the horizontal total width of a frame.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_vsync_width: 7; /*It is the position of LCD_VSYNC active pulse in a line.*/
|
||||
uint32_t lcd_vsync_idle_pol: 1; /*It is the idle value of LCD_VSYNC.*/
|
||||
uint32_t lcd_de_idle_pol: 1; /*It is the idle value of LCD_DE.*/
|
||||
uint32_t lcd_hs_blank_en: 1; /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode.*/
|
||||
uint32_t reserved10: 6; /*reserved*/
|
||||
uint32_t lcd_hsync_width: 7; /*It is the position of LCD_HSYNC active pulse in a line.*/
|
||||
uint32_t lcd_hsync_idle_pol: 1; /*It is the idle value of LCD_HSYNC.*/
|
||||
uint32_t lcd_hsync_position: 8; /*It is the position of LCD_HSYNC active pulse in a line.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_ctrl2;
|
||||
uint32_t lcd_cmd_val; /*The LCD write command value.*/
|
||||
uint32_t reserved_2c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_cd_mode: 2; /*The output LCD_CD is delayed by module clock LCD_CLK*/
|
||||
uint32_t lcd_de_mode: 2; /*The output LCD_DE is delayed by module clock LCD_CLK*/
|
||||
uint32_t lcd_hsync_mode: 2; /*The output LCD_HSYNC is delayed by module clock LCD_CLK*/
|
||||
uint32_t lcd_vsync_mode: 2; /*The output LCD_VSYNC is delayed by module clock LCD_CLK*/
|
||||
uint32_t reserved8: 24; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_dly_mode;
|
||||
uint32_t reserved_34;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dout0_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout1_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout2_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout3_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout4_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout5_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout6_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout7_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout8_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout9_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout10_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout11_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout12_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout13_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout14_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
uint32_t dout15_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lcd_data_dout_mode;
|
||||
uint32_t reserved_3c;
|
||||
uint32_t reserved_40;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
uint32_t reserved_4c;
|
||||
uint32_t reserved_50;
|
||||
uint32_t reserved_54;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_vsync: 1; /*The enable bit for LCD frame end interrupt.*/
|
||||
uint32_t lcd_trans_done: 1; /*The enable bit for lcd transfer end interrupt.*/
|
||||
uint32_t cam_vsync: 1; /*The enable bit for Camera frame end interrupt.*/
|
||||
uint32_t cam_hs: 1; /*The enable bit for Camera line interrupt.*/
|
||||
uint32_t reserved4: 28; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_dma_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_vsync: 1; /*The raw bit for LCD frame end interrupt.*/
|
||||
uint32_t lcd_trans_done: 1; /*The raw bit for lcd transfer end interrupt.*/
|
||||
uint32_t cam_vsync: 1; /*The raw bit for Camera frame end interrupt.*/
|
||||
uint32_t cam_hs: 1; /*The raw bit for Camera line interrupt.*/
|
||||
uint32_t reserved4: 28; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_dma_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_vsync: 1; /*The status bit for LCD frame end interrupt.*/
|
||||
uint32_t lcd_trans_done: 1; /*The status bit for lcd transfer end interrupt.*/
|
||||
uint32_t cam_vsync: 1; /*The status bit for Camera frame end interrupt.*/
|
||||
uint32_t cam_hs: 1; /*The status bit for Camera transfer end interrupt.*/
|
||||
uint32_t reserved4: 28; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_dma_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lcd_vsync: 1; /*The clear bit for LCD frame end interrupt.*/
|
||||
uint32_t lcd_trans_done: 1; /*The clear bit for lcd transfer end interrupt.*/
|
||||
uint32_t cam_vsync: 1; /*The clear bit for Camera frame end interrupt.*/
|
||||
uint32_t cam_hs: 1; /*The clear bit for Camera line interrupt.*/
|
||||
uint32_t reserved4: 28; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_dma_int_clr;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lc_date: 28; /*LCD_CAM version control register*/
|
||||
uint32_t reserved28: 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} lc_date;
|
||||
} lcd_cam_dev_t;
|
||||
|
||||
extern lcd_cam_dev_t LCD_CAM;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
24
components/soc/soc/esp32s3/include/soc/ledc_caps.h
Normal file
24
components/soc/soc/esp32s3/include/soc/ledc_caps.h
Normal file
|
|
@ -0,0 +1,24 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1566
components/soc/soc/esp32s3/include/soc/ledc_reg.h
Normal file
1566
components/soc/soc/esp32s3/include/soc/ledc_reg.h
Normal file
File diff suppressed because it is too large
Load diff
224
components/soc/soc/esp32s3/include/soc/ledc_struct.h
Normal file
224
components/soc/soc/esp32s3/include/soc/ledc_struct.h
Normal file
|
|
@ -0,0 +1,224 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_sel: 2;
|
||||
uint32_t sig_out_en: 1;
|
||||
uint32_t idle_lv: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t ovf_num: 10;
|
||||
uint32_t ovf_cnt_en: 1;
|
||||
uint32_t ovf_cnt_rst: 1;
|
||||
uint32_t ovf_cnt_rst_st: 1;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t hpoint: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} hpoint;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty: 19;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} duty;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_scale: 10;
|
||||
uint32_t duty_cycle: 10;
|
||||
uint32_t duty_num: 10;
|
||||
uint32_t duty_inc: 1;
|
||||
uint32_t duty_start: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_read: 19;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} duty_rd;
|
||||
} channel[8];
|
||||
} channel_group[1];
|
||||
struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t duty_resolution: 4;
|
||||
uint32_t clock_divider: 18;
|
||||
uint32_t pause: 1;
|
||||
uint32_t rst: 1;
|
||||
uint32_t tick_sel: 1;
|
||||
uint32_t low_speed_update: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_cnt: 14;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} value;
|
||||
} timer[4];
|
||||
} timer_group[1];
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t lstimer0_ovf: 1;
|
||||
uint32_t lstimer1_ovf: 1;
|
||||
uint32_t lstimer2_ovf: 1;
|
||||
uint32_t lstimer3_ovf: 1;
|
||||
uint32_t duty_chng_end_lsch0: 1;
|
||||
uint32_t duty_chng_end_lsch1: 1;
|
||||
uint32_t duty_chng_end_lsch2: 1;
|
||||
uint32_t duty_chng_end_lsch3: 1;
|
||||
uint32_t duty_chng_end_lsch4: 1;
|
||||
uint32_t duty_chng_end_lsch5: 1;
|
||||
uint32_t duty_chng_end_lsch6: 1;
|
||||
uint32_t duty_chng_end_lsch7: 1;
|
||||
uint32_t ovf_cnt_lsch0: 1;
|
||||
uint32_t ovf_cnt_lsch1: 1;
|
||||
uint32_t ovf_cnt_lsch2: 1;
|
||||
uint32_t ovf_cnt_lsch3: 1;
|
||||
uint32_t ovf_cnt_lsch4: 1;
|
||||
uint32_t ovf_cnt_lsch5: 1;
|
||||
uint32_t ovf_cnt_lsch6: 1;
|
||||
uint32_t ovf_cnt_lsch7: 1;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t apb_clk_sel: 2;
|
||||
uint32_t reserved2: 29;
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t date; /**/
|
||||
} ledc_dev_t;
|
||||
|
||||
extern ledc_dev_t LEDC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
2902
components/soc/soc/esp32s3/include/soc/mcpwm_reg.h
Normal file
2902
components/soc/soc/esp32s3/include/soc/mcpwm_reg.h
Normal file
File diff suppressed because it is too large
Load diff
457
components/soc/soc/esp32s3/include/soc/mcpwm_struct.h
Normal file
457
components/soc/soc/esp32s3/include/soc/mcpwm_struct.h
Normal file
|
|
@ -0,0 +1,457 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t prescale: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_cfg;
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t prescale: 8;
|
||||
uint32_t period: 16;
|
||||
uint32_t upmethod: 2; /*0: immediate 1: eqz 2: sync 3: eqz | sync*/
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t start: 3; /*0: stop @ eqz 1: stop @ eqp 2: free run 3: start and stop @ next eqz 4: start and stop @ next eqp*/
|
||||
uint32_t mode: 2; /*0: freeze 1: inc 2: dec 3: up-down*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t in_en: 1;
|
||||
uint32_t sync_sw: 1; /*write the negate value will trigger a sw sync*/
|
||||
uint32_t out_sel: 2;
|
||||
uint32_t timer_phase: 17;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} sync;
|
||||
union {
|
||||
struct {
|
||||
uint32_t value: 16;
|
||||
uint32_t direction: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
} timer[3];
|
||||
union {
|
||||
struct {
|
||||
uint32_t t0_in_sel: 3;
|
||||
uint32_t t1_in_sel: 3;
|
||||
uint32_t t2_in_sel: 3;
|
||||
uint32_t ext_in0_inv: 1;
|
||||
uint32_t ext_in1_inv: 1;
|
||||
uint32_t ext_in2_inv: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer_synci_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t operator0_sel: 2; /*0: timer0 1: timer1 2: timer2*/
|
||||
uint32_t operator1_sel: 2; /*0: timer0 1: timer1 2: timer2*/
|
||||
uint32_t operator2_sel: 2; /*0: timer0 1: timer1 2: timer2*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer_sel;
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t a_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
|
||||
uint32_t b_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
|
||||
uint32_t a_shdw_full: 1;
|
||||
uint32_t b_shdw_full: 1;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} cmpr_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmpr_val: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} cmpr_value[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/
|
||||
uint32_t t0_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/
|
||||
uint32_t t1_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} gen_cfg0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cntu_force_upmethod: 6; /*0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: sync bit5: freeze*/
|
||||
uint32_t a_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t b_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t a_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/
|
||||
uint32_t a_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t b_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/
|
||||
uint32_t b_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} gen_force;
|
||||
union {
|
||||
struct {
|
||||
uint32_t utez: 2;
|
||||
uint32_t utep: 2;
|
||||
uint32_t utea: 2;
|
||||
uint32_t uteb: 2;
|
||||
uint32_t ut0: 2;
|
||||
uint32_t ut1: 2;
|
||||
uint32_t dtez: 2;
|
||||
uint32_t dtep: 2;
|
||||
uint32_t dtea: 2;
|
||||
uint32_t dteb: 2;
|
||||
uint32_t dt0: 2;
|
||||
uint32_t dt1: 2; /*0: no change 1: low 2: high 3: toggle*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} generator[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t fed_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
|
||||
uint32_t red_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/
|
||||
uint32_t deb_mode: 1; /*immediate dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/
|
||||
uint32_t a_outswap: 1;
|
||||
uint32_t b_outswap: 1;
|
||||
uint32_t red_insel: 1;
|
||||
uint32_t fed_insel: 1;
|
||||
uint32_t red_outinvert: 1;
|
||||
uint32_t fed_outinvert: 1;
|
||||
uint32_t a_outbypass: 1;
|
||||
uint32_t b_outbypass: 1;
|
||||
uint32_t clk_sel: 1;
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} db_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fed: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} db_fed_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t red: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} db_red_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t en: 1;
|
||||
uint32_t prescale: 4;
|
||||
uint32_t duty: 3;
|
||||
uint32_t oshtwth: 4;
|
||||
uint32_t out_invert: 1;
|
||||
uint32_t in_invert: 1;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} carrier_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_cbc: 1; /*0: disable 1: enable*/
|
||||
uint32_t f2_cbc: 1; /*0: disable 1: enable*/
|
||||
uint32_t f1_cbc: 1; /*0: disable 1: enable*/
|
||||
uint32_t f0_cbc: 1; /*0: disable 1: enable*/
|
||||
uint32_t sw_ost: 1; /*0: disable 1: enable*/
|
||||
uint32_t f2_ost: 1; /*0: disable 1: enable*/
|
||||
uint32_t f1_ost: 1; /*0: disable 1: enable*/
|
||||
uint32_t f0_ost: 1; /*0: disable 1: enable*/
|
||||
uint32_t a_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t a_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t a_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t a_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t b_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/
|
||||
uint32_t reserved24: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} tz_cfg0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clr_ost: 1; /*a toggle will clear oneshot tripping*/
|
||||
uint32_t cbcpulse: 2; /*bit0: tez bit1: tep*/
|
||||
uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping*/
|
||||
uint32_t force_ost: 1; /*a toggle trigger a oneshot tripping*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} tz_cfg1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cbc_on: 1;
|
||||
uint32_t ost_on: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} tz_status;
|
||||
} channel[3];
|
||||
union {
|
||||
struct {
|
||||
uint32_t f0_en: 1;
|
||||
uint32_t f1_en: 1;
|
||||
uint32_t f2_en: 1;
|
||||
uint32_t f0_pole: 1;
|
||||
uint32_t f1_pole: 1;
|
||||
uint32_t f2_pole: 1;
|
||||
uint32_t event_f0: 1;
|
||||
uint32_t event_f1: 1;
|
||||
uint32_t event_f2: 1;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} fault_detect;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer_en: 1;
|
||||
uint32_t synci_en: 1;
|
||||
uint32_t synci_sel: 3;
|
||||
uint32_t sync_sw: 1; /*Write 1 will force a timer sync*/
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} cap_timer_cfg;
|
||||
uint32_t cap_timer_phase; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t en: 1;
|
||||
uint32_t mode: 2; /*bit0: negedge cap en bit1: posedge cap en*/
|
||||
uint32_t prescale: 8;
|
||||
uint32_t in_invert: 1;
|
||||
uint32_t sw: 1; /*Write 1 will trigger a sw capture*/
|
||||
uint32_t reserved13: 19;
|
||||
};
|
||||
uint32_t val;
|
||||
} cap_cfg_ch[3];
|
||||
uint32_t cap_val_ch[3]; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t cap0_edge: 1;
|
||||
uint32_t cap1_edge: 1;
|
||||
uint32_t cap2_edge: 1; /*cap trigger's edge 0: posedge 1: negedge*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} cap_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t global_up_en: 1;
|
||||
uint32_t global_force_up: 1; /*a toggle will trigger a force update all timers and operators will update their active regs*/
|
||||
uint32_t op0_up_en: 1;
|
||||
uint32_t op0_force_up: 1; /*a toggle will trigger a force update*/
|
||||
uint32_t op1_up_en: 1;
|
||||
uint32_t op1_force_up: 1; /*a toggle will trigger a force update*/
|
||||
uint32_t op2_up_en: 1; /*reg update local enable*/
|
||||
uint32_t op2_force_up: 1; /*a toggle will trigger a force update*/
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} update_cfg;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop: 1;
|
||||
uint32_t timer1_stop: 1;
|
||||
uint32_t timer2_stop: 1;
|
||||
uint32_t timer0_tez: 1;
|
||||
uint32_t timer1_tez: 1;
|
||||
uint32_t timer2_tez: 1;
|
||||
uint32_t timer0_tep: 1;
|
||||
uint32_t timer1_tep: 1;
|
||||
uint32_t timer2_tep: 1;
|
||||
uint32_t fault0: 1;
|
||||
uint32_t fault1: 1;
|
||||
uint32_t fault2: 1;
|
||||
uint32_t fault0_clr: 1;
|
||||
uint32_t fault1_clr: 1;
|
||||
uint32_t fault2_clr: 1;
|
||||
uint32_t cmpr0_tea: 1;
|
||||
uint32_t cmpr1_tea: 1;
|
||||
uint32_t cmpr2_tea: 1;
|
||||
uint32_t cmpr0_teb: 1;
|
||||
uint32_t cmpr1_teb: 1;
|
||||
uint32_t cmpr2_teb: 1;
|
||||
uint32_t tz0_cbc: 1;
|
||||
uint32_t tz1_cbc: 1;
|
||||
uint32_t tz2_cbc: 1;
|
||||
uint32_t tz0_ost: 1;
|
||||
uint32_t tz1_ost: 1;
|
||||
uint32_t tz2_ost: 1;
|
||||
uint32_t cap0: 1;
|
||||
uint32_t cap1: 1;
|
||||
uint32_t cap2: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop: 1;
|
||||
uint32_t timer1_stop: 1;
|
||||
uint32_t timer2_stop: 1;
|
||||
uint32_t timer0_tez: 1;
|
||||
uint32_t timer1_tez: 1;
|
||||
uint32_t timer2_tez: 1;
|
||||
uint32_t timer0_tep: 1;
|
||||
uint32_t timer1_tep: 1;
|
||||
uint32_t timer2_tep: 1;
|
||||
uint32_t fault0: 1;
|
||||
uint32_t fault1: 1;
|
||||
uint32_t fault2: 1;
|
||||
uint32_t fault0_clr: 1;
|
||||
uint32_t fault1_clr: 1;
|
||||
uint32_t fault2_clr: 1;
|
||||
uint32_t cmpr0_tea: 1;
|
||||
uint32_t cmpr1_tea: 1;
|
||||
uint32_t cmpr2_tea: 1;
|
||||
uint32_t cmpr0_teb: 1;
|
||||
uint32_t cmpr1_teb: 1;
|
||||
uint32_t cmpr2_teb: 1;
|
||||
uint32_t tz0_cbc: 1;
|
||||
uint32_t tz1_cbc: 1;
|
||||
uint32_t tz2_cbc: 1;
|
||||
uint32_t tz0_ost: 1;
|
||||
uint32_t tz1_ost: 1;
|
||||
uint32_t tz2_ost: 1;
|
||||
uint32_t cap0: 1;
|
||||
uint32_t cap1: 1;
|
||||
uint32_t cap2: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop: 1;
|
||||
uint32_t timer1_stop: 1;
|
||||
uint32_t timer2_stop: 1;
|
||||
uint32_t timer0_tez: 1;
|
||||
uint32_t timer1_tez: 1;
|
||||
uint32_t timer2_tez: 1;
|
||||
uint32_t timer0_tep: 1;
|
||||
uint32_t timer1_tep: 1;
|
||||
uint32_t timer2_tep: 1;
|
||||
uint32_t fault0: 1;
|
||||
uint32_t fault1: 1;
|
||||
uint32_t fault2: 1;
|
||||
uint32_t fault0_clr: 1;
|
||||
uint32_t fault1_clr: 1;
|
||||
uint32_t fault2_clr: 1;
|
||||
uint32_t cmpr0_tea: 1;
|
||||
uint32_t cmpr1_tea: 1;
|
||||
uint32_t cmpr2_tea: 1;
|
||||
uint32_t cmpr0_teb: 1;
|
||||
uint32_t cmpr1_teb: 1;
|
||||
uint32_t cmpr2_teb: 1;
|
||||
uint32_t tz0_cbc: 1;
|
||||
uint32_t tz1_cbc: 1;
|
||||
uint32_t tz2_cbc: 1;
|
||||
uint32_t tz0_ost: 1;
|
||||
uint32_t tz1_ost: 1;
|
||||
uint32_t tz2_ost: 1;
|
||||
uint32_t cap0: 1;
|
||||
uint32_t cap1: 1;
|
||||
uint32_t cap2: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timer0_stop: 1;
|
||||
uint32_t timer1_stop: 1;
|
||||
uint32_t timer2_stop: 1;
|
||||
uint32_t timer0_tez: 1;
|
||||
uint32_t timer1_tez: 1;
|
||||
uint32_t timer2_tez: 1;
|
||||
uint32_t timer0_tep: 1;
|
||||
uint32_t timer1_tep: 1;
|
||||
uint32_t timer2_tep: 1;
|
||||
uint32_t fault0: 1;
|
||||
uint32_t fault1: 1;
|
||||
uint32_t fault2: 1;
|
||||
uint32_t fault0_clr: 1;
|
||||
uint32_t fault1_clr: 1;
|
||||
uint32_t fault2_clr: 1;
|
||||
uint32_t cmpr0_tea: 1;
|
||||
uint32_t cmpr1_tea: 1;
|
||||
uint32_t cmpr2_tea: 1;
|
||||
uint32_t cmpr0_teb: 1;
|
||||
uint32_t cmpr1_teb: 1;
|
||||
uint32_t cmpr2_teb: 1;
|
||||
uint32_t tz0_cbc: 1;
|
||||
uint32_t tz1_cbc: 1;
|
||||
uint32_t tz2_cbc: 1;
|
||||
uint32_t tz0_ost: 1;
|
||||
uint32_t tz1_ost: 1;
|
||||
uint32_t tz2_ost: 1;
|
||||
uint32_t cap0: 1;
|
||||
uint32_t cap1: 1;
|
||||
uint32_t cap2: 1;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} reg_clk;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} version;
|
||||
} mcpwm_dev_t;
|
||||
|
||||
extern mcpwm_dev_t MCPWM0;
|
||||
extern mcpwm_dev_t MCPWM1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
21
components/soc/soc/esp32s3/include/soc/mpu_caps.h
Normal file
21
components/soc/soc/esp32s3/include/soc/mpu_caps.h
Normal file
|
|
@ -0,0 +1,21 @@
|
|||
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0
|
||||
#define SOC_MPU_MIN_REGION_SIZE 0x20000000
|
||||
#define SOC_MPU_REGIONS_MAX_NUM 8
|
||||
#define SOC_MPU_REGION_RO_SUPPORTED 0
|
||||
#define SOC_MPU_REGION_WO_SUPPORTED 0
|
||||
55
components/soc/soc/esp32s3/include/soc/nrx_reg.h
Normal file
55
components/soc/soc/esp32s3/include/soc/nrx_reg.h
Normal file
|
|
@ -0,0 +1,55 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#include "soc/soc.h"
|
||||
|
||||
/* Some of the WiFi RX control registers.
|
||||
* PU/PD fields defined here are used in sleep related functions.
|
||||
*/
|
||||
|
||||
#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4)
|
||||
#define NRX_CHAN_EST_FORCE_PU (BIT(7))
|
||||
#define NRX_CHAN_EST_FORCE_PU_M (BIT(7))
|
||||
#define NRX_CHAN_EST_FORCE_PU_V 1
|
||||
#define NRX_CHAN_EST_FORCE_PU_S 7
|
||||
#define NRX_CHAN_EST_FORCE_PD (BIT(6))
|
||||
#define NRX_CHAN_EST_FORCE_PD_M (BIT(6))
|
||||
#define NRX_CHAN_EST_FORCE_PD_V 1
|
||||
#define NRX_CHAN_EST_FORCE_PD_S 6
|
||||
#define NRX_RX_ROT_FORCE_PU (BIT(5))
|
||||
#define NRX_RX_ROT_FORCE_PU_M (BIT(5))
|
||||
#define NRX_RX_ROT_FORCE_PU_V 1
|
||||
#define NRX_RX_ROT_FORCE_PU_S 5
|
||||
#define NRX_RX_ROT_FORCE_PD (BIT(4))
|
||||
#define NRX_RX_ROT_FORCE_PD_M (BIT(4))
|
||||
#define NRX_RX_ROT_FORCE_PD_V 1
|
||||
#define NRX_RX_ROT_FORCE_PD_S 4
|
||||
#define NRX_VIT_FORCE_PU (BIT(3))
|
||||
#define NRX_VIT_FORCE_PU_M (BIT(3))
|
||||
#define NRX_VIT_FORCE_PU_V 1
|
||||
#define NRX_VIT_FORCE_PU_S 3
|
||||
#define NRX_VIT_FORCE_PD (BIT(2))
|
||||
#define NRX_VIT_FORCE_PD_M (BIT(2))
|
||||
#define NRX_VIT_FORCE_PD_V 1
|
||||
#define NRX_VIT_FORCE_PD_S 2
|
||||
#define NRX_DEMAP_FORCE_PU (BIT(1))
|
||||
#define NRX_DEMAP_FORCE_PU_M (BIT(1))
|
||||
#define NRX_DEMAP_FORCE_PU_V 1
|
||||
#define NRX_DEMAP_FORCE_PU_S 1
|
||||
#define NRX_DEMAP_FORCE_PD (BIT(0))
|
||||
#define NRX_DEMAP_FORCE_PD_M (BIT(0))
|
||||
#define NRX_DEMAP_FORCE_PD_V 1
|
||||
#define NRX_DEMAP_FORCE_PD_S 0
|
||||
26
components/soc/soc/esp32s3/include/soc/pcnt_caps.h
Normal file
26
components/soc/soc/esp32s3/include/soc/pcnt_caps.h
Normal file
|
|
@ -0,0 +1,26 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SOC_PCNT_PORT_NUM (1)
|
||||
#define SOC_PCNT_UNIT_NUM (4)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
856
components/soc/soc/esp32s3/include/soc/pcnt_reg.h
Normal file
856
components/soc/soc/esp32s3/include/soc/pcnt_reg.h
Normal file
|
|
@ -0,0 +1,856 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000)
|
||||
/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_LCTRL_MODE_U0 0x00000003
|
||||
#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V) << (PCNT_CH1_LCTRL_MODE_U0_S))
|
||||
#define PCNT_CH1_LCTRL_MODE_U0_V 0x3
|
||||
#define PCNT_CH1_LCTRL_MODE_U0_S 30
|
||||
/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_HCTRL_MODE_U0 0x00000003
|
||||
#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V) << (PCNT_CH1_HCTRL_MODE_U0_S))
|
||||
#define PCNT_CH1_HCTRL_MODE_U0_V 0x3
|
||||
#define PCNT_CH1_HCTRL_MODE_U0_S 28
|
||||
/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_POS_MODE_U0 0x00000003
|
||||
#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V) << (PCNT_CH1_POS_MODE_U0_S))
|
||||
#define PCNT_CH1_POS_MODE_U0_V 0x3
|
||||
#define PCNT_CH1_POS_MODE_U0_S 26
|
||||
/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_NEG_MODE_U0 0x00000003
|
||||
#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V) << (PCNT_CH1_NEG_MODE_U0_S))
|
||||
#define PCNT_CH1_NEG_MODE_U0_V 0x3
|
||||
#define PCNT_CH1_NEG_MODE_U0_S 24
|
||||
/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_LCTRL_MODE_U0 0x00000003
|
||||
#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V) << (PCNT_CH0_LCTRL_MODE_U0_S))
|
||||
#define PCNT_CH0_LCTRL_MODE_U0_V 0x3
|
||||
#define PCNT_CH0_LCTRL_MODE_U0_S 22
|
||||
/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_HCTRL_MODE_U0 0x00000003
|
||||
#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V) << (PCNT_CH0_HCTRL_MODE_U0_S))
|
||||
#define PCNT_CH0_HCTRL_MODE_U0_V 0x3
|
||||
#define PCNT_CH0_HCTRL_MODE_U0_S 20
|
||||
/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_POS_MODE_U0 0x00000003
|
||||
#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V) << (PCNT_CH0_POS_MODE_U0_S))
|
||||
#define PCNT_CH0_POS_MODE_U0_V 0x3
|
||||
#define PCNT_CH0_POS_MODE_U0_S 18
|
||||
/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_NEG_MODE_U0 0x00000003
|
||||
#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V) << (PCNT_CH0_NEG_MODE_U0_S))
|
||||
#define PCNT_CH0_NEG_MODE_U0_V 0x3
|
||||
#define PCNT_CH0_NEG_MODE_U0_S 16
|
||||
/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES1_EN_U0 (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U0_M (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U0_V 0x1
|
||||
#define PCNT_THR_THRES1_EN_U0_S 15
|
||||
/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES0_EN_U0 (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U0_M (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U0_V 0x1
|
||||
#define PCNT_THR_THRES0_EN_U0_S 14
|
||||
/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_L_LIM_EN_U0 (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U0_M (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U0_V 0x1
|
||||
#define PCNT_THR_L_LIM_EN_U0_S 13
|
||||
/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_H_LIM_EN_U0 (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U0_M (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U0_V 0x1
|
||||
#define PCNT_THR_H_LIM_EN_U0_S 12
|
||||
/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_ZERO_EN_U0 (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U0_M (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U0_V 0x1
|
||||
#define PCNT_THR_ZERO_EN_U0_S 11
|
||||
/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_EN_U0 (BIT(10))
|
||||
#define PCNT_FILTER_EN_U0_M (BIT(10))
|
||||
#define PCNT_FILTER_EN_U0_V 0x1
|
||||
#define PCNT_FILTER_EN_U0_S 10
|
||||
/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_THRES_U0 0x000003FF
|
||||
#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V) << (PCNT_FILTER_THRES_U0_S))
|
||||
#define PCNT_FILTER_THRES_U0_V 0x3FF
|
||||
#define PCNT_FILTER_THRES_U0_S 0
|
||||
|
||||
#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004)
|
||||
/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES1_U0 0x0000FFFF
|
||||
#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V) << (PCNT_CNT_THRES1_U0_S))
|
||||
#define PCNT_CNT_THRES1_U0_V 0xFFFF
|
||||
#define PCNT_CNT_THRES1_U0_S 16
|
||||
/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES0_U0 0x0000FFFF
|
||||
#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V) << (PCNT_CNT_THRES0_U0_S))
|
||||
#define PCNT_CNT_THRES0_U0_V 0xFFFF
|
||||
#define PCNT_CNT_THRES0_U0_S 0
|
||||
|
||||
#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008)
|
||||
/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_L_LIM_U0 0x0000FFFF
|
||||
#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V) << (PCNT_CNT_L_LIM_U0_S))
|
||||
#define PCNT_CNT_L_LIM_U0_V 0xFFFF
|
||||
#define PCNT_CNT_L_LIM_U0_S 16
|
||||
/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_H_LIM_U0 0x0000FFFF
|
||||
#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V) << (PCNT_CNT_H_LIM_U0_S))
|
||||
#define PCNT_CNT_H_LIM_U0_V 0xFFFF
|
||||
#define PCNT_CNT_H_LIM_U0_S 0
|
||||
|
||||
#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c)
|
||||
/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_LCTRL_MODE_U1 0x00000003
|
||||
#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V) << (PCNT_CH1_LCTRL_MODE_U1_S))
|
||||
#define PCNT_CH1_LCTRL_MODE_U1_V 0x3
|
||||
#define PCNT_CH1_LCTRL_MODE_U1_S 30
|
||||
/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_HCTRL_MODE_U1 0x00000003
|
||||
#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V) << (PCNT_CH1_HCTRL_MODE_U1_S))
|
||||
#define PCNT_CH1_HCTRL_MODE_U1_V 0x3
|
||||
#define PCNT_CH1_HCTRL_MODE_U1_S 28
|
||||
/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_POS_MODE_U1 0x00000003
|
||||
#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V) << (PCNT_CH1_POS_MODE_U1_S))
|
||||
#define PCNT_CH1_POS_MODE_U1_V 0x3
|
||||
#define PCNT_CH1_POS_MODE_U1_S 26
|
||||
/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_NEG_MODE_U1 0x00000003
|
||||
#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V) << (PCNT_CH1_NEG_MODE_U1_S))
|
||||
#define PCNT_CH1_NEG_MODE_U1_V 0x3
|
||||
#define PCNT_CH1_NEG_MODE_U1_S 24
|
||||
/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_LCTRL_MODE_U1 0x00000003
|
||||
#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V) << (PCNT_CH0_LCTRL_MODE_U1_S))
|
||||
#define PCNT_CH0_LCTRL_MODE_U1_V 0x3
|
||||
#define PCNT_CH0_LCTRL_MODE_U1_S 22
|
||||
/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_HCTRL_MODE_U1 0x00000003
|
||||
#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V) << (PCNT_CH0_HCTRL_MODE_U1_S))
|
||||
#define PCNT_CH0_HCTRL_MODE_U1_V 0x3
|
||||
#define PCNT_CH0_HCTRL_MODE_U1_S 20
|
||||
/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_POS_MODE_U1 0x00000003
|
||||
#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V) << (PCNT_CH0_POS_MODE_U1_S))
|
||||
#define PCNT_CH0_POS_MODE_U1_V 0x3
|
||||
#define PCNT_CH0_POS_MODE_U1_S 18
|
||||
/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_NEG_MODE_U1 0x00000003
|
||||
#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V) << (PCNT_CH0_NEG_MODE_U1_S))
|
||||
#define PCNT_CH0_NEG_MODE_U1_V 0x3
|
||||
#define PCNT_CH0_NEG_MODE_U1_S 16
|
||||
/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES1_EN_U1 (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U1_M (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U1_V 0x1
|
||||
#define PCNT_THR_THRES1_EN_U1_S 15
|
||||
/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES0_EN_U1 (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U1_M (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U1_V 0x1
|
||||
#define PCNT_THR_THRES0_EN_U1_S 14
|
||||
/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_L_LIM_EN_U1 (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U1_M (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U1_V 0x1
|
||||
#define PCNT_THR_L_LIM_EN_U1_S 13
|
||||
/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_H_LIM_EN_U1 (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U1_M (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U1_V 0x1
|
||||
#define PCNT_THR_H_LIM_EN_U1_S 12
|
||||
/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_ZERO_EN_U1 (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U1_M (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U1_V 0x1
|
||||
#define PCNT_THR_ZERO_EN_U1_S 11
|
||||
/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_EN_U1 (BIT(10))
|
||||
#define PCNT_FILTER_EN_U1_M (BIT(10))
|
||||
#define PCNT_FILTER_EN_U1_V 0x1
|
||||
#define PCNT_FILTER_EN_U1_S 10
|
||||
/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_THRES_U1 0x000003FF
|
||||
#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V) << (PCNT_FILTER_THRES_U1_S))
|
||||
#define PCNT_FILTER_THRES_U1_V 0x3FF
|
||||
#define PCNT_FILTER_THRES_U1_S 0
|
||||
|
||||
#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010)
|
||||
/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES1_U1 0x0000FFFF
|
||||
#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V) << (PCNT_CNT_THRES1_U1_S))
|
||||
#define PCNT_CNT_THRES1_U1_V 0xFFFF
|
||||
#define PCNT_CNT_THRES1_U1_S 16
|
||||
/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES0_U1 0x0000FFFF
|
||||
#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V) << (PCNT_CNT_THRES0_U1_S))
|
||||
#define PCNT_CNT_THRES0_U1_V 0xFFFF
|
||||
#define PCNT_CNT_THRES0_U1_S 0
|
||||
|
||||
#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014)
|
||||
/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_L_LIM_U1 0x0000FFFF
|
||||
#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V) << (PCNT_CNT_L_LIM_U1_S))
|
||||
#define PCNT_CNT_L_LIM_U1_V 0xFFFF
|
||||
#define PCNT_CNT_L_LIM_U1_S 16
|
||||
/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_H_LIM_U1 0x0000FFFF
|
||||
#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V) << (PCNT_CNT_H_LIM_U1_S))
|
||||
#define PCNT_CNT_H_LIM_U1_V 0xFFFF
|
||||
#define PCNT_CNT_H_LIM_U1_S 0
|
||||
|
||||
#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018)
|
||||
/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_LCTRL_MODE_U2 0x00000003
|
||||
#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V) << (PCNT_CH1_LCTRL_MODE_U2_S))
|
||||
#define PCNT_CH1_LCTRL_MODE_U2_V 0x3
|
||||
#define PCNT_CH1_LCTRL_MODE_U2_S 30
|
||||
/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_HCTRL_MODE_U2 0x00000003
|
||||
#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V) << (PCNT_CH1_HCTRL_MODE_U2_S))
|
||||
#define PCNT_CH1_HCTRL_MODE_U2_V 0x3
|
||||
#define PCNT_CH1_HCTRL_MODE_U2_S 28
|
||||
/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_POS_MODE_U2 0x00000003
|
||||
#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V) << (PCNT_CH1_POS_MODE_U2_S))
|
||||
#define PCNT_CH1_POS_MODE_U2_V 0x3
|
||||
#define PCNT_CH1_POS_MODE_U2_S 26
|
||||
/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_NEG_MODE_U2 0x00000003
|
||||
#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V) << (PCNT_CH1_NEG_MODE_U2_S))
|
||||
#define PCNT_CH1_NEG_MODE_U2_V 0x3
|
||||
#define PCNT_CH1_NEG_MODE_U2_S 24
|
||||
/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_LCTRL_MODE_U2 0x00000003
|
||||
#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V) << (PCNT_CH0_LCTRL_MODE_U2_S))
|
||||
#define PCNT_CH0_LCTRL_MODE_U2_V 0x3
|
||||
#define PCNT_CH0_LCTRL_MODE_U2_S 22
|
||||
/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_HCTRL_MODE_U2 0x00000003
|
||||
#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V) << (PCNT_CH0_HCTRL_MODE_U2_S))
|
||||
#define PCNT_CH0_HCTRL_MODE_U2_V 0x3
|
||||
#define PCNT_CH0_HCTRL_MODE_U2_S 20
|
||||
/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_POS_MODE_U2 0x00000003
|
||||
#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V) << (PCNT_CH0_POS_MODE_U2_S))
|
||||
#define PCNT_CH0_POS_MODE_U2_V 0x3
|
||||
#define PCNT_CH0_POS_MODE_U2_S 18
|
||||
/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_NEG_MODE_U2 0x00000003
|
||||
#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V) << (PCNT_CH0_NEG_MODE_U2_S))
|
||||
#define PCNT_CH0_NEG_MODE_U2_V 0x3
|
||||
#define PCNT_CH0_NEG_MODE_U2_S 16
|
||||
/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES1_EN_U2 (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U2_M (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U2_V 0x1
|
||||
#define PCNT_THR_THRES1_EN_U2_S 15
|
||||
/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES0_EN_U2 (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U2_M (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U2_V 0x1
|
||||
#define PCNT_THR_THRES0_EN_U2_S 14
|
||||
/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_L_LIM_EN_U2 (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U2_M (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U2_V 0x1
|
||||
#define PCNT_THR_L_LIM_EN_U2_S 13
|
||||
/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_H_LIM_EN_U2 (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U2_M (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U2_V 0x1
|
||||
#define PCNT_THR_H_LIM_EN_U2_S 12
|
||||
/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_ZERO_EN_U2 (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U2_M (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U2_V 0x1
|
||||
#define PCNT_THR_ZERO_EN_U2_S 11
|
||||
/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_EN_U2 (BIT(10))
|
||||
#define PCNT_FILTER_EN_U2_M (BIT(10))
|
||||
#define PCNT_FILTER_EN_U2_V 0x1
|
||||
#define PCNT_FILTER_EN_U2_S 10
|
||||
/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_THRES_U2 0x000003FF
|
||||
#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V) << (PCNT_FILTER_THRES_U2_S))
|
||||
#define PCNT_FILTER_THRES_U2_V 0x3FF
|
||||
#define PCNT_FILTER_THRES_U2_S 0
|
||||
|
||||
#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c)
|
||||
/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES1_U2 0x0000FFFF
|
||||
#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V) << (PCNT_CNT_THRES1_U2_S))
|
||||
#define PCNT_CNT_THRES1_U2_V 0xFFFF
|
||||
#define PCNT_CNT_THRES1_U2_S 16
|
||||
/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES0_U2 0x0000FFFF
|
||||
#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V) << (PCNT_CNT_THRES0_U2_S))
|
||||
#define PCNT_CNT_THRES0_U2_V 0xFFFF
|
||||
#define PCNT_CNT_THRES0_U2_S 0
|
||||
|
||||
#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020)
|
||||
/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_L_LIM_U2 0x0000FFFF
|
||||
#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V) << (PCNT_CNT_L_LIM_U2_S))
|
||||
#define PCNT_CNT_L_LIM_U2_V 0xFFFF
|
||||
#define PCNT_CNT_L_LIM_U2_S 16
|
||||
/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_H_LIM_U2 0x0000FFFF
|
||||
#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V) << (PCNT_CNT_H_LIM_U2_S))
|
||||
#define PCNT_CNT_H_LIM_U2_V 0xFFFF
|
||||
#define PCNT_CNT_H_LIM_U2_S 0
|
||||
|
||||
#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024)
|
||||
/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_LCTRL_MODE_U3 0x00000003
|
||||
#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V) << (PCNT_CH1_LCTRL_MODE_U3_S))
|
||||
#define PCNT_CH1_LCTRL_MODE_U3_V 0x3
|
||||
#define PCNT_CH1_LCTRL_MODE_U3_S 30
|
||||
/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_HCTRL_MODE_U3 0x00000003
|
||||
#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V) << (PCNT_CH1_HCTRL_MODE_U3_S))
|
||||
#define PCNT_CH1_HCTRL_MODE_U3_V 0x3
|
||||
#define PCNT_CH1_HCTRL_MODE_U3_S 28
|
||||
/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_POS_MODE_U3 0x00000003
|
||||
#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V) << (PCNT_CH1_POS_MODE_U3_S))
|
||||
#define PCNT_CH1_POS_MODE_U3_V 0x3
|
||||
#define PCNT_CH1_POS_MODE_U3_S 26
|
||||
/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH1_NEG_MODE_U3 0x00000003
|
||||
#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V) << (PCNT_CH1_NEG_MODE_U3_S))
|
||||
#define PCNT_CH1_NEG_MODE_U3_V 0x3
|
||||
#define PCNT_CH1_NEG_MODE_U3_S 24
|
||||
/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_LCTRL_MODE_U3 0x00000003
|
||||
#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V) << (PCNT_CH0_LCTRL_MODE_U3_S))
|
||||
#define PCNT_CH0_LCTRL_MODE_U3_V 0x3
|
||||
#define PCNT_CH0_LCTRL_MODE_U3_S 22
|
||||
/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_HCTRL_MODE_U3 0x00000003
|
||||
#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V) << (PCNT_CH0_HCTRL_MODE_U3_S))
|
||||
#define PCNT_CH0_HCTRL_MODE_U3_V 0x3
|
||||
#define PCNT_CH0_HCTRL_MODE_U3_S 20
|
||||
/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_POS_MODE_U3 0x00000003
|
||||
#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V) << (PCNT_CH0_POS_MODE_U3_S))
|
||||
#define PCNT_CH0_POS_MODE_U3_V 0x3
|
||||
#define PCNT_CH0_POS_MODE_U3_S 18
|
||||
/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CH0_NEG_MODE_U3 0x00000003
|
||||
#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V) << (PCNT_CH0_NEG_MODE_U3_S))
|
||||
#define PCNT_CH0_NEG_MODE_U3_V 0x3
|
||||
#define PCNT_CH0_NEG_MODE_U3_S 16
|
||||
/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES1_EN_U3 (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U3_M (BIT(15))
|
||||
#define PCNT_THR_THRES1_EN_U3_V 0x1
|
||||
#define PCNT_THR_THRES1_EN_U3_S 15
|
||||
/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_THRES0_EN_U3 (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U3_M (BIT(14))
|
||||
#define PCNT_THR_THRES0_EN_U3_V 0x1
|
||||
#define PCNT_THR_THRES0_EN_U3_S 14
|
||||
/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_L_LIM_EN_U3 (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U3_M (BIT(13))
|
||||
#define PCNT_THR_L_LIM_EN_U3_V 0x1
|
||||
#define PCNT_THR_L_LIM_EN_U3_S 13
|
||||
/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_H_LIM_EN_U3 (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U3_M (BIT(12))
|
||||
#define PCNT_THR_H_LIM_EN_U3_V 0x1
|
||||
#define PCNT_THR_H_LIM_EN_U3_S 12
|
||||
/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_THR_ZERO_EN_U3 (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U3_M (BIT(11))
|
||||
#define PCNT_THR_ZERO_EN_U3_V 0x1
|
||||
#define PCNT_THR_ZERO_EN_U3_S 11
|
||||
/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_EN_U3 (BIT(10))
|
||||
#define PCNT_FILTER_EN_U3_M (BIT(10))
|
||||
#define PCNT_FILTER_EN_U3_V 0x1
|
||||
#define PCNT_FILTER_EN_U3_S 10
|
||||
/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */
|
||||
/*description: */
|
||||
#define PCNT_FILTER_THRES_U3 0x000003FF
|
||||
#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V) << (PCNT_FILTER_THRES_U3_S))
|
||||
#define PCNT_FILTER_THRES_U3_V 0x3FF
|
||||
#define PCNT_FILTER_THRES_U3_S 0
|
||||
|
||||
#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028)
|
||||
/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES1_U3 0x0000FFFF
|
||||
#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V) << (PCNT_CNT_THRES1_U3_S))
|
||||
#define PCNT_CNT_THRES1_U3_V 0xFFFF
|
||||
#define PCNT_CNT_THRES1_U3_S 16
|
||||
/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THRES0_U3 0x0000FFFF
|
||||
#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V) << (PCNT_CNT_THRES0_U3_S))
|
||||
#define PCNT_CNT_THRES0_U3_V 0xFFFF
|
||||
#define PCNT_CNT_THRES0_U3_S 0
|
||||
|
||||
#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c)
|
||||
/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_L_LIM_U3 0x0000FFFF
|
||||
#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V) << (PCNT_CNT_L_LIM_U3_S))
|
||||
#define PCNT_CNT_L_LIM_U3_V 0xFFFF
|
||||
#define PCNT_CNT_L_LIM_U3_S 16
|
||||
/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_H_LIM_U3 0x0000FFFF
|
||||
#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V) << (PCNT_CNT_H_LIM_U3_S))
|
||||
#define PCNT_CNT_H_LIM_U3_V 0xFFFF
|
||||
#define PCNT_CNT_H_LIM_U3_S 0
|
||||
|
||||
#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0030)
|
||||
/* PCNT_PULSE_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_U0 0x0000FFFF
|
||||
#define PCNT_PULSE_CNT_U0_M ((PCNT_PULSE_CNT_U0_V) << (PCNT_PULSE_CNT_U0_S))
|
||||
#define PCNT_PULSE_CNT_U0_V 0xFFFF
|
||||
#define PCNT_PULSE_CNT_U0_S 0
|
||||
|
||||
#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0034)
|
||||
/* PCNT_PULSE_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_U1 0x0000FFFF
|
||||
#define PCNT_PULSE_CNT_U1_M ((PCNT_PULSE_CNT_U1_V) << (PCNT_PULSE_CNT_U1_S))
|
||||
#define PCNT_PULSE_CNT_U1_V 0xFFFF
|
||||
#define PCNT_PULSE_CNT_U1_S 0
|
||||
|
||||
#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0038)
|
||||
/* PCNT_PULSE_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_U2 0x0000FFFF
|
||||
#define PCNT_PULSE_CNT_U2_M ((PCNT_PULSE_CNT_U2_V) << (PCNT_PULSE_CNT_U2_S))
|
||||
#define PCNT_PULSE_CNT_U2_V 0xFFFF
|
||||
#define PCNT_PULSE_CNT_U2_S 0
|
||||
|
||||
#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x003c)
|
||||
/* PCNT_PULSE_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_U3 0x0000FFFF
|
||||
#define PCNT_PULSE_CNT_U3_M ((PCNT_PULSE_CNT_U3_V) << (PCNT_PULSE_CNT_U3_S))
|
||||
#define PCNT_PULSE_CNT_U3_V 0xFFFF
|
||||
#define PCNT_PULSE_CNT_U3_S 0
|
||||
|
||||
#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0040)
|
||||
/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3
|
||||
/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2
|
||||
/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1
|
||||
/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0
|
||||
|
||||
#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0044)
|
||||
/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3
|
||||
/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2
|
||||
/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1
|
||||
/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0
|
||||
|
||||
#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0048)
|
||||
/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3
|
||||
/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2
|
||||
/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1
|
||||
/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0
|
||||
|
||||
#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x004c)
|
||||
/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3))
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3
|
||||
/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2))
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2
|
||||
/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1))
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1
|
||||
/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0))
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1
|
||||
#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0
|
||||
|
||||
#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0050)
|
||||
/* PCNT_CNT_THR_ZERO_LAT_U0 : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U0_M (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x1
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U0_S 6
|
||||
/* PCNT_CNT_THR_H_LIM_LAT_U0 : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U0_M (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x1
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5
|
||||
/* PCNT_CNT_THR_L_LIM_LAT_U0 : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U0_M (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x1
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4
|
||||
/* PCNT_CNT_THR_THRES0_LAT_U0 : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U0_M (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x1
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U0_S 3
|
||||
/* PCNT_CNT_THR_THRES1_LAT_U0 : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U0_M (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x1
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U0_S 2
|
||||
/* PCNT_CNT_THR_ZERO_MODE_U0 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U0_M ((PCNT_CNT_THR_ZERO_MODE_U0_V) << (PCNT_CNT_THR_ZERO_MODE_U0_S))
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x3
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U0_S 0
|
||||
|
||||
#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0054)
|
||||
/* PCNT_CNT_THR_ZERO_LAT_U1 : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U1_M (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x1
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U1_S 6
|
||||
/* PCNT_CNT_THR_H_LIM_LAT_U1 : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U1_M (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x1
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5
|
||||
/* PCNT_CNT_THR_L_LIM_LAT_U1 : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U1_M (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x1
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4
|
||||
/* PCNT_CNT_THR_THRES0_LAT_U1 : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U1_M (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x1
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U1_S 3
|
||||
/* PCNT_CNT_THR_THRES1_LAT_U1 : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U1_M (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x1
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U1_S 2
|
||||
/* PCNT_CNT_THR_ZERO_MODE_U1 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U1_M ((PCNT_CNT_THR_ZERO_MODE_U1_V) << (PCNT_CNT_THR_ZERO_MODE_U1_S))
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x3
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U1_S 0
|
||||
|
||||
#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0058)
|
||||
/* PCNT_CNT_THR_ZERO_LAT_U2 : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U2_M (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x1
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U2_S 6
|
||||
/* PCNT_CNT_THR_H_LIM_LAT_U2 : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U2_M (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x1
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5
|
||||
/* PCNT_CNT_THR_L_LIM_LAT_U2 : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U2_M (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x1
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4
|
||||
/* PCNT_CNT_THR_THRES0_LAT_U2 : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U2_M (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x1
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U2_S 3
|
||||
/* PCNT_CNT_THR_THRES1_LAT_U2 : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U2_M (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x1
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U2_S 2
|
||||
/* PCNT_CNT_THR_ZERO_MODE_U2 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U2_M ((PCNT_CNT_THR_ZERO_MODE_U2_V) << (PCNT_CNT_THR_ZERO_MODE_U2_S))
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x3
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U2_S 0
|
||||
|
||||
#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x005c)
|
||||
/* PCNT_CNT_THR_ZERO_LAT_U3 : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U3_M (BIT(6))
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x1
|
||||
#define PCNT_CNT_THR_ZERO_LAT_U3_S 6
|
||||
/* PCNT_CNT_THR_H_LIM_LAT_U3 : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U3_M (BIT(5))
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x1
|
||||
#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5
|
||||
/* PCNT_CNT_THR_L_LIM_LAT_U3 : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U3_M (BIT(4))
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x1
|
||||
#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4
|
||||
/* PCNT_CNT_THR_THRES0_LAT_U3 : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U3_M (BIT(3))
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x1
|
||||
#define PCNT_CNT_THR_THRES0_LAT_U3_S 3
|
||||
/* PCNT_CNT_THR_THRES1_LAT_U3 : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U3_M (BIT(2))
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x1
|
||||
#define PCNT_CNT_THR_THRES1_LAT_U3_S 2
|
||||
/* PCNT_CNT_THR_ZERO_MODE_U3 : RO ;bitpos:[1:0] ;default: 2'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U3_M ((PCNT_CNT_THR_ZERO_MODE_U3_V) << (PCNT_CNT_THR_ZERO_MODE_U3_S))
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x3
|
||||
#define PCNT_CNT_THR_ZERO_MODE_U3_S 0
|
||||
|
||||
#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x0060)
|
||||
/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CLK_EN (BIT(16))
|
||||
#define PCNT_CLK_EN_M (BIT(16))
|
||||
#define PCNT_CLK_EN_V 0x1
|
||||
#define PCNT_CLK_EN_S 16
|
||||
/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_PAUSE_U3 (BIT(7))
|
||||
#define PCNT_CNT_PAUSE_U3_M (BIT(7))
|
||||
#define PCNT_CNT_PAUSE_U3_V 0x1
|
||||
#define PCNT_CNT_PAUSE_U3_S 7
|
||||
/* PCNT_PULSE_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_RST_U3 (BIT(6))
|
||||
#define PCNT_PULSE_CNT_RST_U3_M (BIT(6))
|
||||
#define PCNT_PULSE_CNT_RST_U3_V 0x1
|
||||
#define PCNT_PULSE_CNT_RST_U3_S 6
|
||||
/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_PAUSE_U2 (BIT(5))
|
||||
#define PCNT_CNT_PAUSE_U2_M (BIT(5))
|
||||
#define PCNT_CNT_PAUSE_U2_V 0x1
|
||||
#define PCNT_CNT_PAUSE_U2_S 5
|
||||
/* PCNT_PULSE_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_RST_U2 (BIT(4))
|
||||
#define PCNT_PULSE_CNT_RST_U2_M (BIT(4))
|
||||
#define PCNT_PULSE_CNT_RST_U2_V 0x1
|
||||
#define PCNT_PULSE_CNT_RST_U2_S 4
|
||||
/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_PAUSE_U1 (BIT(3))
|
||||
#define PCNT_CNT_PAUSE_U1_M (BIT(3))
|
||||
#define PCNT_CNT_PAUSE_U1_V 0x1
|
||||
#define PCNT_CNT_PAUSE_U1_S 3
|
||||
/* PCNT_PULSE_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_RST_U1 (BIT(2))
|
||||
#define PCNT_PULSE_CNT_RST_U1_M (BIT(2))
|
||||
#define PCNT_PULSE_CNT_RST_U1_V 0x1
|
||||
#define PCNT_PULSE_CNT_RST_U1_S 2
|
||||
/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define PCNT_CNT_PAUSE_U0 (BIT(1))
|
||||
#define PCNT_CNT_PAUSE_U0_M (BIT(1))
|
||||
#define PCNT_CNT_PAUSE_U0_V 0x1
|
||||
#define PCNT_CNT_PAUSE_U0_S 1
|
||||
/* PCNT_PULSE_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */
|
||||
/*description: */
|
||||
#define PCNT_PULSE_CNT_RST_U0 (BIT(0))
|
||||
#define PCNT_PULSE_CNT_RST_U0_M (BIT(0))
|
||||
#define PCNT_PULSE_CNT_RST_U0_V 0x1
|
||||
#define PCNT_PULSE_CNT_RST_U0_S 0
|
||||
|
||||
#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc)
|
||||
/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */
|
||||
/*description: */
|
||||
#define PCNT_DATE 0xFFFFFFFF
|
||||
#define PCNT_DATE_M ((PCNT_DATE_V) << (PCNT_DATE_S))
|
||||
#define PCNT_DATE_V 0xFFFFFFFF
|
||||
#define PCNT_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
179
components/soc/soc/esp32s3/include/soc/pcnt_struct.h
Normal file
179
components/soc/soc/esp32s3/include/soc/pcnt_struct.h
Normal file
|
|
@ -0,0 +1,179 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t filter_thres: 10;
|
||||
uint32_t filter_en: 1;
|
||||
uint32_t thr_zero_en: 1;
|
||||
uint32_t thr_h_lim_en: 1;
|
||||
uint32_t thr_l_lim_en: 1;
|
||||
uint32_t thr_thres0_en: 1;
|
||||
uint32_t thr_thres1_en: 1;
|
||||
uint32_t ch0_neg_mode: 2;
|
||||
uint32_t ch0_pos_mode: 2;
|
||||
uint32_t ch0_hctrl_mode: 2;
|
||||
uint32_t ch0_lctrl_mode: 2;
|
||||
uint32_t ch1_neg_mode: 2;
|
||||
uint32_t ch1_pos_mode: 2;
|
||||
uint32_t ch1_hctrl_mode: 2;
|
||||
uint32_t ch1_lctrl_mode: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thres0: 16;
|
||||
uint32_t cnt_thres1: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_h_lim: 16;
|
||||
uint32_t cnt_l_lim: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf2;
|
||||
} conf_unit[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_val: 16;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} cnt_unit[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0: 1;
|
||||
uint32_t cnt_thr_event_u1: 1;
|
||||
uint32_t cnt_thr_event_u2: 1;
|
||||
uint32_t cnt_thr_event_u3: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0: 1;
|
||||
uint32_t cnt_thr_event_u1: 1;
|
||||
uint32_t cnt_thr_event_u2: 1;
|
||||
uint32_t cnt_thr_event_u3: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0: 1;
|
||||
uint32_t cnt_thr_event_u1: 1;
|
||||
uint32_t cnt_thr_event_u2: 1;
|
||||
uint32_t cnt_thr_event_u3: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_thr_event_u0: 1;
|
||||
uint32_t cnt_thr_event_u1: 1;
|
||||
uint32_t cnt_thr_event_u2: 1;
|
||||
uint32_t cnt_thr_event_u3: 1;
|
||||
uint32_t reserved4: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_mode: 2;
|
||||
uint32_t thres1_lat: 1;
|
||||
uint32_t thres0_lat: 1;
|
||||
uint32_t l_lim_lat: 1;
|
||||
uint32_t h_lim_lat: 1;
|
||||
uint32_t zero_lat: 1;
|
||||
uint32_t reserved7: 25;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_unit[4];
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_rst_u0: 1;
|
||||
uint32_t cnt_pause_u0: 1;
|
||||
uint32_t cnt_rst_u1: 1;
|
||||
uint32_t cnt_pause_u1: 1;
|
||||
uint32_t cnt_rst_u2: 1;
|
||||
uint32_t cnt_pause_u2: 1;
|
||||
uint32_t cnt_rst_u3: 1;
|
||||
uint32_t cnt_pause_u3: 1;
|
||||
uint32_t reserved8: 8;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t date; /**/
|
||||
} pcnt_dev_t;
|
||||
|
||||
extern pcnt_dev_t PCNT;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
169
components/soc/soc/esp32s3/include/soc/periph_defs.h
Normal file
169
components/soc/soc/esp32s3/include/soc/periph_defs.h
Normal file
|
|
@ -0,0 +1,169 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef enum {
|
||||
PERIPH_LEDC_MODULE = 0,
|
||||
PERIPH_UART0_MODULE,
|
||||
PERIPH_UART1_MODULE,
|
||||
PERIPH_UART2_MODULE,
|
||||
PERIPH_USB_MODULE,
|
||||
PERIPH_I2C0_MODULE,
|
||||
PERIPH_I2C1_MODULE,
|
||||
PERIPH_I2S0_MODULE,
|
||||
PERIPH_I2S1_MODULE,
|
||||
PERIPH_TIMG0_MODULE,
|
||||
PERIPH_TIMG1_MODULE,
|
||||
PERIPH_PWM0_MODULE,
|
||||
PERIPH_PWM1_MODULE,
|
||||
PERIPH_PWM2_MODULE,
|
||||
PERIPH_PWM3_MODULE,
|
||||
PERIPH_UHCI0_MODULE,
|
||||
PERIPH_UHCI1_MODULE,
|
||||
PERIPH_RMT_MODULE,
|
||||
PERIPH_PCNT_MODULE,
|
||||
PERIPH_SPI_MODULE, //SPI1
|
||||
PERIPH_FSPI_MODULE, //SPI2
|
||||
PERIPH_HSPI_MODULE, //SPI3
|
||||
PERIPH_VSPI_MODULE, //SPI4
|
||||
PERIPH_SPI2_DMA_MODULE,
|
||||
PERIPH_SPI3_DMA_MODULE,
|
||||
PERIPH_SPI_SHARED_DMA_MODULE, //this DMA is shared by SPI1 and SPI4
|
||||
PERIPH_SDMMC_MODULE,
|
||||
PERIPH_TWAI_MODULE,
|
||||
PERIPH_RNG_MODULE,
|
||||
PERIPH_WIFI_MODULE,
|
||||
PERIPH_BT_MODULE,
|
||||
PERIPH_WIFI_BT_COMMON_MODULE,
|
||||
PERIPH_BT_BASEBAND_MODULE,
|
||||
PERIPH_BT_LC_MODULE,
|
||||
PERIPH_AES_MODULE,
|
||||
PERIPH_SHA_MODULE,
|
||||
PERIPH_RSA_MODULE,
|
||||
PERIPH_CRYPTO_DMA_MODULE, //this DMA is shared between AES and SHA
|
||||
PERIPH_AES_DMA_MODULE,
|
||||
PERIPH_SHA_DMA_MODULE,
|
||||
PERIPH_MODULE_MAX
|
||||
} periph_module_t;
|
||||
|
||||
typedef enum {
|
||||
ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/
|
||||
ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/
|
||||
ETS_WIFI_PWR_INTR_SOURCE, /**< */
|
||||
ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/
|
||||
ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/
|
||||
ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/
|
||||
ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/
|
||||
ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/
|
||||
ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/
|
||||
ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/
|
||||
ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/
|
||||
ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/
|
||||
ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/
|
||||
ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/
|
||||
ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/
|
||||
ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/
|
||||
|
||||
ETS_TG0_T0_LEVEL_INTR_SOURCE = 16, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/
|
||||
ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/
|
||||
ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/
|
||||
ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/
|
||||
ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/
|
||||
ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/
|
||||
ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/
|
||||
ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/
|
||||
ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/
|
||||
ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/
|
||||
ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/
|
||||
ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/
|
||||
ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/
|
||||
ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/
|
||||
ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/
|
||||
ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, level*/
|
||||
|
||||
ETS_LCD_CAM_INTR_SOURCE = 32, /**< interrupt of LCD camera, level*/
|
||||
ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/
|
||||
ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/
|
||||
ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/
|
||||
ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/
|
||||
ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/
|
||||
ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/
|
||||
ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/
|
||||
ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/
|
||||
ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/
|
||||
ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/
|
||||
ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/
|
||||
ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/
|
||||
ETS_TWAI_INTR_SOURCE, /**< interrupt of TWAI, level*/
|
||||
ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/
|
||||
ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/
|
||||
|
||||
ETS_RMT_INTR_SOURCE = 48, /**< interrupt of remote controller, level*/
|
||||
ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/
|
||||
ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/
|
||||
ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/
|
||||
ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/
|
||||
ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/
|
||||
ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, level*/
|
||||
ETS_WDT_INTR_SOURCE, /**< will be cancelled*/
|
||||
ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/
|
||||
ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/
|
||||
ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/
|
||||
ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/
|
||||
ETS_TG0_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/
|
||||
ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
|
||||
ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/
|
||||
ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/
|
||||
|
||||
ETS_TG1_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/
|
||||
ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/
|
||||
ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/
|
||||
ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/
|
||||
ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/
|
||||
ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/
|
||||
ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/
|
||||
ETS_DCACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/
|
||||
ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/
|
||||
ETS_DCACHE_SYNC0_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/
|
||||
ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
|
||||
ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/
|
||||
ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/
|
||||
ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/
|
||||
ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/
|
||||
ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/
|
||||
|
||||
ETS_FROM_CPU_INTR0_SOURCE = 80, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */
|
||||
ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */
|
||||
ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */
|
||||
ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */
|
||||
ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/
|
||||
ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/
|
||||
ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/
|
||||
ETS_DCACHE_PRELOAD1_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/
|
||||
ETS_ICACHE_PRELOAD1_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/
|
||||
ETS_DCACHE_SYNC1_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/
|
||||
ETS_ICACHE_SYNC1_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/
|
||||
|
||||
ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */
|
||||
|
||||
} periph_interrput_t;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
30
components/soc/soc/esp32s3/include/soc/rmt_caps.h
Normal file
30
components/soc/soc/esp32s3/include/soc/rmt_caps.h
Normal file
|
|
@ -0,0 +1,30 @@
|
|||
// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */
|
||||
#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */
|
||||
#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */
|
||||
#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */
|
||||
#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */
|
||||
#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
2120
components/soc/soc/esp32s3/include/soc/rmt_reg.h
Normal file
2120
components/soc/soc/esp32s3/include/soc/rmt_reg.h
Normal file
File diff suppressed because it is too large
Load diff
300
components/soc/soc/esp32s3/include/soc/rmt_struct.h
Normal file
300
components/soc/soc/esp32s3/include/soc/rmt_struct.h
Normal file
|
|
@ -0,0 +1,300 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t data_ch[8]; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t mem_raddr_ex: 10;
|
||||
uint32_t reserved10: 1;
|
||||
uint32_t waddr: 10;
|
||||
uint32_t reserved21: 1;
|
||||
uint32_t state: 3;
|
||||
uint32_t mem_empty: 1;
|
||||
uint32_t apb_mem_wr_err: 1;
|
||||
uint32_t reserved27: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} status_ch[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_tx_end: 1;
|
||||
uint32_t ch3_tx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_tx_thr_event: 1;
|
||||
uint32_t ch3_tx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_rx_end: 1;
|
||||
uint32_t ch5_rx_end: 1;
|
||||
uint32_t ch6_rx_end: 1;
|
||||
uint32_t ch7_rx_end: 1;
|
||||
uint32_t ch4_err: 1;
|
||||
uint32_t ch5_err: 1;
|
||||
uint32_t ch6_err: 1;
|
||||
uint32_t ch7_err: 1;
|
||||
uint32_t ch4_rx_thr_event: 1;
|
||||
uint32_t ch5_rx_thr_event: 1;
|
||||
uint32_t ch6_rx_thr_event: 1;
|
||||
uint32_t ch7_rx_thr_event: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_tx_end: 1;
|
||||
uint32_t ch3_tx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_tx_thr_event: 1;
|
||||
uint32_t ch3_tx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_rx_end: 1;
|
||||
uint32_t ch5_rx_end: 1;
|
||||
uint32_t ch6_rx_end: 1;
|
||||
uint32_t ch7_rx_end: 1;
|
||||
uint32_t ch4_err: 1;
|
||||
uint32_t ch5_err: 1;
|
||||
uint32_t ch6_err: 1;
|
||||
uint32_t ch7_err: 1;
|
||||
uint32_t ch4_rx_thr_event: 1;
|
||||
uint32_t ch5_rx_thr_event: 1;
|
||||
uint32_t ch6_rx_thr_event: 1;
|
||||
uint32_t ch7_rx_thr_event: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_tx_end: 1;
|
||||
uint32_t ch3_tx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_tx_thr_event: 1;
|
||||
uint32_t ch3_tx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_rx_end: 1;
|
||||
uint32_t ch5_rx_end: 1;
|
||||
uint32_t ch6_rx_end: 1;
|
||||
uint32_t ch7_rx_end: 1;
|
||||
uint32_t ch4_err: 1;
|
||||
uint32_t ch5_err: 1;
|
||||
uint32_t ch6_err: 1;
|
||||
uint32_t ch7_err: 1;
|
||||
uint32_t ch4_rx_thr_event: 1;
|
||||
uint32_t ch5_rx_thr_event: 1;
|
||||
uint32_t ch6_rx_thr_event: 1;
|
||||
uint32_t ch7_rx_thr_event: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0_tx_end: 1;
|
||||
uint32_t ch1_tx_end: 1;
|
||||
uint32_t ch2_tx_end: 1;
|
||||
uint32_t ch3_tx_end: 1;
|
||||
uint32_t ch0_err: 1;
|
||||
uint32_t ch1_err: 1;
|
||||
uint32_t ch2_err: 1;
|
||||
uint32_t ch3_err: 1;
|
||||
uint32_t ch0_tx_thr_event: 1;
|
||||
uint32_t ch1_tx_thr_event: 1;
|
||||
uint32_t ch2_tx_thr_event: 1;
|
||||
uint32_t ch3_tx_thr_event: 1;
|
||||
uint32_t ch0_tx_loop: 1;
|
||||
uint32_t ch1_tx_loop: 1;
|
||||
uint32_t ch2_tx_loop: 1;
|
||||
uint32_t ch3_tx_loop: 1;
|
||||
uint32_t ch4_rx_end: 1;
|
||||
uint32_t ch5_rx_end: 1;
|
||||
uint32_t ch6_rx_end: 1;
|
||||
uint32_t ch7_rx_end: 1;
|
||||
uint32_t ch4_err: 1;
|
||||
uint32_t ch5_err: 1;
|
||||
uint32_t ch6_err: 1;
|
||||
uint32_t ch7_err: 1;
|
||||
uint32_t ch4_rx_thr_event: 1;
|
||||
uint32_t ch5_rx_thr_event: 1;
|
||||
uint32_t ch6_rx_thr_event: 1;
|
||||
uint32_t ch7_rx_thr_event: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t low: 16;
|
||||
uint32_t high: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} carrier_duty_ch[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t carrier_low_thres_ch4: 16;
|
||||
uint32_t carrier_high_thres_ch4: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch4_rx_carrier_rm;
|
||||
union {
|
||||
struct {
|
||||
uint32_t carrier_low_thres_ch5: 16;
|
||||
uint32_t carrier_high_thres_ch5: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch5_rx_carrier_rm;
|
||||
union {
|
||||
struct {
|
||||
uint32_t carrier_low_thres_ch6: 16;
|
||||
uint32_t carrier_high_thres_ch6: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch6_rx_carrier_rm;
|
||||
union {
|
||||
struct {
|
||||
uint32_t carrier_low_thres_ch7: 16;
|
||||
uint32_t carrier_high_thres_ch7: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch7_rx_carrier_rm;
|
||||
union {
|
||||
struct {
|
||||
uint32_t limit: 9;
|
||||
uint32_t tx_loop_num: 10;
|
||||
uint32_t tx_loop_cnt_en: 1;
|
||||
uint32_t loop_count_reset: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_lim_ch[8];
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_lim_ch4: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch4_rx_lim;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_lim_ch5: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch5_rx_lim;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_lim_ch6: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch6_rx_lim;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_lim_ch7: 9;
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} ch7_rx_lim;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_mask: 1;
|
||||
uint32_t mem_clk_force_on: 1;
|
||||
uint32_t mem_force_pd: 1;
|
||||
uint32_t mem_force_pu: 1;
|
||||
uint32_t sclk_div_num: 8;
|
||||
uint32_t sclk_div_a: 6;
|
||||
uint32_t sclk_div_b: 6;
|
||||
uint32_t sclk_sel: 2;
|
||||
uint32_t sclk_active: 1;
|
||||
uint32_t reserved27: 4;
|
||||
uint32_t clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sys_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0: 1;
|
||||
uint32_t ch1: 1;
|
||||
uint32_t ch2: 1;
|
||||
uint32_t ch3: 1;
|
||||
uint32_t en: 1;
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_sim;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ch0: 1;
|
||||
uint32_t ch1: 1;
|
||||
uint32_t ch2: 1;
|
||||
uint32_t ch3: 1;
|
||||
uint32_t ch4: 1;
|
||||
uint32_t ch5: 1;
|
||||
uint32_t ch6: 1;
|
||||
uint32_t ch7: 1;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} ref_cnt_rst;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rmt_dev_t;
|
||||
|
||||
extern rmt_dev_t RMT;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
819
components/soc/soc/esp32s3/include/soc/rtc.h
Normal file
819
components/soc/soc/esp32s3/include/soc/rtc.h
Normal file
|
|
@ -0,0 +1,819 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h>
|
||||
#include <stdint.h>
|
||||
#include "soc/soc.h"
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @file rtc.h
|
||||
* @brief Low-level RTC power, clock, and sleep functions.
|
||||
*
|
||||
* Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral.
|
||||
* RTC_CNTL peripheral handles many functions:
|
||||
* - enables/disables clocks and power to various parts of the chip; this is
|
||||
* done using direct register access (forcing power up or power down) or by
|
||||
* allowing state machines to control power and clocks automatically
|
||||
* - handles sleep and wakeup functions
|
||||
* - maintains a 48-bit counter which can be used for timekeeping
|
||||
*
|
||||
* These functions are not thread safe, and should not be viewed as high level
|
||||
* APIs. For example, while this file provides a function which can switch
|
||||
* CPU frequency, this function is on its own is not sufficient to implement
|
||||
* frequency switching in ESP-IDF context: some coordination with RTOS,
|
||||
* peripheral drivers, and WiFi/BT stacks is also required.
|
||||
*
|
||||
* These functions will normally not be used in applications directly.
|
||||
* ESP-IDF provides, or will provide, drivers and other facilities to use
|
||||
* RTC subsystem functionality.
|
||||
*
|
||||
* The functions are loosely split into the following groups:
|
||||
* - rtc_clk: clock switching, calibration
|
||||
* - rtc_time: reading RTC counter, conversion between counter values and time
|
||||
* - rtc_sleep: entry into sleep modes
|
||||
* - rtc_init: initialization
|
||||
*/
|
||||
|
||||
#define MHZ (1000000)
|
||||
|
||||
#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12)
|
||||
#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10)
|
||||
|
||||
#define RTC_SLOW_CLK_FREQ_90K 90000
|
||||
#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256)
|
||||
#define RTC_SLOW_CLK_FREQ_32K 32768
|
||||
|
||||
#define OTHER_BLOCKS_POWERUP 1
|
||||
#define OTHER_BLOCKS_WAIT 1
|
||||
|
||||
/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP,
|
||||
* RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values.
|
||||
* Valid if RTC_CNTL_DBG_ATTEN is 0.
|
||||
*/
|
||||
#define RTC_CNTL_DBIAS_0V90 0
|
||||
#define RTC_CNTL_DBIAS_0V95 1
|
||||
#define RTC_CNTL_DBIAS_1V00 2
|
||||
#define RTC_CNTL_DBIAS_1V05 3
|
||||
#define RTC_CNTL_DBIAS_1V10 4
|
||||
#define RTC_CNTL_DBIAS_1V15 5
|
||||
#define RTC_CNTL_DBIAS_1V20 6
|
||||
#define RTC_CNTL_DBIAS_1V25 7
|
||||
|
||||
#define DELAY_FAST_CLK_SWITCH 3
|
||||
#define DELAY_SLOW_CLK_SWITCH 300
|
||||
#define DELAY_8M_ENABLE 50
|
||||
|
||||
/* Number of 8M/256 clock cycles to use for XTAL frequency estimation.
|
||||
* 10 cycles will take approximately 300 microseconds.
|
||||
*/
|
||||
#define XTAL_FREQ_EST_CYCLES 10
|
||||
|
||||
/* Core voltage needs to be increased in two cases:
|
||||
* 1. running at 240 MHz
|
||||
* 2. running with 80MHz Flash frequency
|
||||
*/
|
||||
#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M
|
||||
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25
|
||||
#else
|
||||
#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10
|
||||
#endif
|
||||
#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25
|
||||
#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10
|
||||
#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00
|
||||
|
||||
#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20
|
||||
#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100
|
||||
#define RTC_CNTL_CK8M_WAIT_DEFAULT 20
|
||||
#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1
|
||||
|
||||
#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172
|
||||
#define RTC_CNTL_SCK_DCAP_DEFAULT 255
|
||||
|
||||
/*
|
||||
set sleep_init default param
|
||||
*/
|
||||
#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6
|
||||
#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15
|
||||
#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1
|
||||
#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0
|
||||
#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1
|
||||
|
||||
#define APLL_SDM_STOP_VAL_1 0x09
|
||||
#define APLL_SDM_STOP_VAL_2_REV0 0x69
|
||||
#define APLL_SDM_STOP_VAL_2_REV1 0x49
|
||||
#define APLL_CAL_DELAY_1 0x0f
|
||||
#define APLL_CAL_DELAY_2 0x3f
|
||||
#define APLL_CAL_DELAY_3 0x1f
|
||||
|
||||
#define i2c_ulp_block 0x61
|
||||
#define i2c_ulp_hostid 0x1
|
||||
#define i2c_ulp_ir_resetb 0
|
||||
#define i2c_ulp_ir_resetb_msb 0
|
||||
#define i2c_ulp_ir_resetb_lsb 0
|
||||
|
||||
/**
|
||||
* @brief Possible main XTAL frequency values.
|
||||
*
|
||||
* Enum values should be equal to frequency in MHz.
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL
|
||||
} rtc_xtal_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU frequency values
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency
|
||||
RTC_CPU_FREQ_80M = 1, //!< 80 MHz
|
||||
RTC_CPU_FREQ_160M = 2, //!< 160 MHz
|
||||
RTC_CPU_FREQ_240M = 3, //!< 240 MHz
|
||||
RTC_CPU_FREQ_2M = 4, //!< 2 MHz
|
||||
RTC_CPU_320M_80M = 5, //!< for test
|
||||
RTC_CPU_320M_160M = 6, //!< for test
|
||||
RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset
|
||||
} rtc_cpu_freq_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock source
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_CPU_FREQ_SRC_XTAL, //!< XTAL
|
||||
RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M)
|
||||
RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator
|
||||
RTC_CPU_FREQ_SRC_APLL //!< APLL
|
||||
} rtc_cpu_freq_src_t;
|
||||
|
||||
/**
|
||||
* @brief CPU clock configuration structure
|
||||
*/
|
||||
typedef struct rtc_cpu_freq_config_s {
|
||||
rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived
|
||||
uint32_t source_freq_mhz; //!< Source clock frequency
|
||||
uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div
|
||||
uint32_t freq_mhz; //!< CPU clock frequency
|
||||
} rtc_cpu_freq_config_t;
|
||||
|
||||
/**
|
||||
* @brief RTC SLOW_CLK frequency values
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator
|
||||
RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL
|
||||
RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256
|
||||
} rtc_slow_freq_t;
|
||||
|
||||
/**
|
||||
* @brief RTC FAST_CLK frequency values
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4
|
||||
RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator
|
||||
} rtc_fast_freq_t;
|
||||
|
||||
/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */
|
||||
#define RTC_FAST_CLK_FREQ_APPROX 8500000
|
||||
|
||||
#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal
|
||||
|
||||
#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO
|
||||
#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO
|
||||
|
||||
/**
|
||||
* @brief Clock source to be calibrated using rtc_clk_cal function
|
||||
*/
|
||||
typedef enum {
|
||||
RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK
|
||||
RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256
|
||||
RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL
|
||||
} rtc_cal_sel_t;
|
||||
|
||||
/**
|
||||
* Initialization parameters for rtc_clk_init
|
||||
*/
|
||||
typedef struct {
|
||||
rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency
|
||||
uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz
|
||||
rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set
|
||||
rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set
|
||||
uint32_t clk_rtc_clk_div : 8;
|
||||
uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency)
|
||||
uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency)
|
||||
uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency)
|
||||
} rtc_clk_config_t;
|
||||
|
||||
/**
|
||||
* Default initializer for rtc_clk_config_t
|
||||
*/
|
||||
#define RTC_CLK_CONFIG_DEFAULT() { \
|
||||
.xtal_freq = RTC_XTAL_FREQ_40M, \
|
||||
.cpu_freq_mhz = 80, \
|
||||
.fast_freq = RTC_FAST_FREQ_8M, \
|
||||
.slow_freq = RTC_SLOW_FREQ_RTC, \
|
||||
.clk_rtc_clk_div = 0, \
|
||||
.clk_8m_clk_div = 0, \
|
||||
.slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \
|
||||
.clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
uint32_t dac : 6;
|
||||
uint32_t dres : 3;
|
||||
uint32_t dgm : 3;
|
||||
uint32_t dbuf: 1;
|
||||
} x32k_config_t;
|
||||
|
||||
#define X32K_CONFIG_DEFAULT() { \
|
||||
.dac = 1, \
|
||||
.dres = 3, \
|
||||
.dgm = 0, \
|
||||
.dbuf = 1, \
|
||||
}
|
||||
|
||||
#if 0
|
||||
#define X32K_CONFIG_BOOTSTRAP_DEFAULT() { \
|
||||
.dac = 3, \
|
||||
.dres = 3, \
|
||||
.dgm = 0, \
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
x32k_config_t x32k_cfg;
|
||||
uint32_t bt_lpck_div_num : 12;
|
||||
uint32_t bt_lpck_div_a : 12;
|
||||
uint32_t bt_lpck_div_b : 12;
|
||||
} x32k_bootstrap_config_t;
|
||||
|
||||
#define X32K_BOOTSTRAP_CONFIG_DEFAULT() { \
|
||||
.x32k_cfg = X32K_CONFIG_BOOTSTRAP_DEFAULT(), \
|
||||
.bt_lpck_div_num = 2441, \
|
||||
.bt_lpck_div_a = 32, \
|
||||
.bt_lpck_div_b = 13, \
|
||||
}
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint16_t wifi_powerup_cycles : 7;
|
||||
uint16_t wifi_wait_cycles : 9;
|
||||
uint16_t rtc_powerup_cycles : 7;
|
||||
uint16_t rtc_wait_cycles : 9;
|
||||
uint16_t dg_wrap_powerup_cycles : 7;
|
||||
uint16_t dg_wrap_wait_cycles : 9;
|
||||
uint16_t rtc_mem_powerup_cycles : 7;
|
||||
uint16_t rtc_mem_wait_cycles : 9;
|
||||
} rtc_init_config_t;
|
||||
|
||||
#define RTC_INIT_CONFIG_DEFAULT() { \
|
||||
.wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.wifi_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.rtc_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
.rtc_mem_powerup_cycles = OTHER_BLOCKS_POWERUP, \
|
||||
.rtc_mem_wait_cycles = OTHER_BLOCKS_WAIT, \
|
||||
}
|
||||
|
||||
void rtc_clk_divider_set(uint32_t div);
|
||||
|
||||
void rtc_clk_8m_divider_set(uint32_t div);
|
||||
|
||||
/**
|
||||
* Initialize clocks and set CPU frequency
|
||||
*
|
||||
* @param cfg clock configuration as rtc_clk_config_t
|
||||
*/
|
||||
void rtc_clk_init(rtc_clk_config_t cfg);
|
||||
|
||||
/**
|
||||
* @brief Get main XTAL frequency
|
||||
*
|
||||
* This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to
|
||||
* rtc_clk_init function
|
||||
*
|
||||
* @return XTAL frequency, one of rtc_xtal_freq_t
|
||||
*/
|
||||
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Update XTAL frequency
|
||||
*
|
||||
* Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored
|
||||
* after startup.
|
||||
*
|
||||
* @param xtal_freq New frequency value
|
||||
*/
|
||||
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 32 kHz XTAL oscillator
|
||||
* @param en true to enable, false to disable
|
||||
*/
|
||||
void rtc_clk_32k_enable(bool en);
|
||||
|
||||
/**
|
||||
* @brief Configure 32 kHz XTAL oscillator to accept external clock signal
|
||||
*/
|
||||
void rtc_clk_32k_enable_external(void);
|
||||
|
||||
/**
|
||||
* @brief Get the state of 32k XTAL oscillator
|
||||
* @return true if 32k XTAL oscillator has been enabled
|
||||
*/
|
||||
bool rtc_clk_32k_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Enable 32k oscillator, configuring it for fast startup time.
|
||||
* Note: to achieve higher frequency stability, rtc_clk_32k_enable function
|
||||
* must be called one the 32k XTAL oscillator has started up. This function
|
||||
* will initially disable the 32k XTAL oscillator, so it should not be called
|
||||
* when the system is using 32k XTAL as RTC_SLOW_CLK.
|
||||
*
|
||||
* @param cycle Number of 32kHz cycles to bootstrap external crystal.
|
||||
* If 0, no square wave will be used to bootstrap crystal oscillation.
|
||||
*/
|
||||
void rtc_clk_32k_bootstrap(uint32_t cycle);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable 8 MHz internal oscillator
|
||||
*
|
||||
* Output from 8 MHz internal oscillator is passed into a configurable
|
||||
* divider, which by default divides the input clock frequency by 256.
|
||||
* Output of the divider may be used as RTC_SLOW_CLK source.
|
||||
* Output of the divider is referred to in register descriptions and code as
|
||||
* 8md256 or simply d256. Divider values other than 256 may be configured, but
|
||||
* this facility is not currently needed, so is not exposed in the code.
|
||||
*
|
||||
* When 8MHz/256 divided output is not needed, the divider should be disabled
|
||||
* to reduce power consumption.
|
||||
*
|
||||
* @param clk_8m_en true to enable 8MHz generator
|
||||
* @param d256_en true to enable /256 divider
|
||||
*/
|
||||
void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en);
|
||||
|
||||
/**
|
||||
* @brief Get the state of 8 MHz internal oscillator
|
||||
* @return true if the oscillator is enabled
|
||||
*/
|
||||
bool rtc_clk_8m_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Get the state of /256 divider which is applied to 8MHz clock
|
||||
* @return true if the divided output is enabled
|
||||
*/
|
||||
bool rtc_clk_8md256_enabled(void);
|
||||
|
||||
/**
|
||||
* @brief Enable or disable APLL
|
||||
*
|
||||
* Output frequency is given by the formula:
|
||||
* apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2)
|
||||
*
|
||||
* The dividend in this expression should be in the range of 240 - 600 MHz.
|
||||
*
|
||||
* In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0.
|
||||
*
|
||||
* @param enable true to enable, false to disable
|
||||
* @param sdm0 frequency adjustment parameter, 0..255
|
||||
* @param sdm1 frequency adjustment parameter, 0..255
|
||||
* @param sdm2 frequency adjustment parameter, 0..63
|
||||
* @param o_div frequency divider, 0..31
|
||||
*/
|
||||
void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div);
|
||||
|
||||
/**
|
||||
* @brief Set XTAL wait cycles by RTC slow clock's period
|
||||
*/
|
||||
void rtc_clk_set_xtal_wait(void);
|
||||
|
||||
/**
|
||||
* @brief Select source for RTC_SLOW_CLK
|
||||
* @param slow_freq clock source (one of rtc_slow_freq_t values)
|
||||
*/
|
||||
void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq);
|
||||
|
||||
/**
|
||||
* @brief Get the RTC_SLOW_CLK source
|
||||
* @return currently selected clock source (one of rtc_slow_freq_t values)
|
||||
*/
|
||||
rtc_slow_freq_t rtc_clk_slow_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz
|
||||
*
|
||||
* - if RTC_SLOW_FREQ_RTC is selected, returns ~150000
|
||||
* - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768
|
||||
* - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000
|
||||
*
|
||||
* rtc_clk_cal function can be used to get more precise value by comparing
|
||||
* RTC_SLOW_CLK frequency to the frequency of main XTAL.
|
||||
*
|
||||
* @return RTC_SLOW_CLK frequency, in Hz
|
||||
*/
|
||||
uint32_t rtc_clk_slow_freq_get_hz(void);
|
||||
|
||||
/**
|
||||
* @brief Select source for RTC_FAST_CLK
|
||||
* @param fast_freq clock source (one of rtc_fast_freq_t values)
|
||||
*/
|
||||
void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq);
|
||||
|
||||
/**
|
||||
* @brief Get the RTC_FAST_CLK source
|
||||
* @return currently selected clock source (one of rtc_fast_freq_t values)
|
||||
*/
|
||||
rtc_fast_freq_t rtc_clk_fast_freq_get(void);
|
||||
|
||||
/**
|
||||
* @brief Get CPU frequency config for a given frequency
|
||||
* @param freq_mhz Frequency in MHz
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
* @return true if frequency can be obtained, false otherwise
|
||||
*/
|
||||
bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency
|
||||
*
|
||||
* This function sets CPU frequency according to the given configuration
|
||||
* structure. It enables PLLs, if necessary.
|
||||
*
|
||||
* @note This function in not intended to be called by applications in FreeRTOS
|
||||
* environment. This is because it does not adjust various timers based on the
|
||||
* new CPU frequency.
|
||||
*
|
||||
* @param config CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU frequency (optimized for speed)
|
||||
*
|
||||
* This function is a faster equivalent of rtc_clk_cpu_freq_set_config.
|
||||
* It works faster because it does not disable PLLs when switching from PLL to
|
||||
* XTAL and does not enabled them when switching back. If PLL is not already
|
||||
* enabled when this function is called to switch from XTAL to PLL frequency,
|
||||
* or the PLL which is enabled is the wrong one, this function will fall back
|
||||
* to calling rtc_clk_cpu_freq_set_config.
|
||||
*
|
||||
* Unlike rtc_clk_cpu_freq_set_config, this function relies on static data,
|
||||
* so it is less safe to use it e.g. from a panic handler (when memory might
|
||||
* be corrupted).
|
||||
*
|
||||
* @note This function in not intended to be called by applications in FreeRTOS
|
||||
* environment. This is because it does not adjust various timers based on the
|
||||
* new CPU frequency.
|
||||
*
|
||||
* @param config CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config);
|
||||
|
||||
/**
|
||||
* @brief Get the currently used CPU frequency configuration
|
||||
* @param[out] out_config Output, CPU frequency configuration structure
|
||||
*/
|
||||
void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config);
|
||||
|
||||
/**
|
||||
* @brief Switch CPU clock source to XTAL
|
||||
*
|
||||
* Short form for filling in rtc_cpu_freq_config_t structure and calling
|
||||
* rtc_clk_cpu_freq_set_config when a switch to XTAL is needed.
|
||||
* Assumes that XTAL frequency has been determined — don't call in startup code.
|
||||
*/
|
||||
void rtc_clk_cpu_freq_set_xtal(void);
|
||||
|
||||
/**
|
||||
* @brief Store new APB frequency value into RTC_APB_FREQ_REG
|
||||
*
|
||||
* This function doesn't change any hardware clocks.
|
||||
*
|
||||
* Functions which perform frequency switching and change APB frequency call
|
||||
* this function to update the value of APB frequency stored in RTC_APB_FREQ_REG
|
||||
* (one of RTC general purpose retention registers). This should not normally
|
||||
* be called from application code.
|
||||
*
|
||||
* @param apb_freq new APB frequency, in Hz
|
||||
*/
|
||||
void rtc_clk_apb_freq_update(uint32_t apb_freq);
|
||||
|
||||
/**
|
||||
* @brief Get the current stored APB frequency.
|
||||
* @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz.
|
||||
*/
|
||||
uint32_t rtc_clk_apb_freq_get(void);
|
||||
|
||||
uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Measure RTC slow clock's period, based on main XTAL frequency
|
||||
*
|
||||
* This function will time out and return 0 if the time for the given number
|
||||
* of cycles to be counted exceeds the expected time twice. This may happen if
|
||||
* 32k XTAL is being calibrated, but the oscillator has not started up (due to
|
||||
* incorrect loading capacitance, board design issue, or lack of 32 XTAL on board).
|
||||
*
|
||||
* @param cal_clk clock to be measured
|
||||
* @param slow_clk_cycles number of slow clock cycles to average
|
||||
* @return average slow clock period in microseconds, Q13.19 fixed point format,
|
||||
* or 0 if calibration has timed out
|
||||
*/
|
||||
uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Measure ratio between XTAL frequency and RTC slow clock frequency
|
||||
* @param cal_clk slow clock to be measured
|
||||
* @param slow_clk_cycles number of slow clock cycles to average
|
||||
* @return average ratio between XTAL frequency and slow clock frequency,
|
||||
* Q13.19 fixed point format, or 0 if calibration has timed out.
|
||||
*/
|
||||
uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles);
|
||||
|
||||
/**
|
||||
* @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles
|
||||
* @param time_in_us Time interval in microseconds
|
||||
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
|
||||
* fixed point format (as returned by rtc_slowck_cali).
|
||||
* @return number of slow clock cycles
|
||||
*/
|
||||
uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period);
|
||||
|
||||
/**
|
||||
* @brief Convert time interval from RTC_SLOW_CLK to microseconds
|
||||
* @param time_in_us Time interval in RTC_SLOW_CLK cycles
|
||||
* @param slow_clk_period Period of slow clock in microseconds, Q13.19
|
||||
* fixed point format (as returned by rtc_slowck_cali).
|
||||
* @return time interval in microseconds
|
||||
*/
|
||||
uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period);
|
||||
|
||||
/**
|
||||
* @brief Get current value of RTC counter
|
||||
*
|
||||
* RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK
|
||||
* cycles. Counter value is not writable by software. The value is not adjusted
|
||||
* when switching to a different RTC_SLOW_CLK source.
|
||||
*
|
||||
* Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute
|
||||
*
|
||||
* @return current value of RTC counter
|
||||
*/
|
||||
uint64_t rtc_time_get(void);
|
||||
|
||||
uint64_t rtc_light_slp_time_get(void);
|
||||
|
||||
uint64_t rtc_deep_slp_time_get(void);
|
||||
|
||||
/**
|
||||
* @brief Busy loop until next RTC_SLOW_CLK cycle
|
||||
*
|
||||
* This function returns not earlier than the next RTC_SLOW_CLK clock cycle.
|
||||
* In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return
|
||||
* one RTC_SLOW_CLK cycle later.
|
||||
*/
|
||||
void rtc_clk_wait_for_slow_cycle(void);
|
||||
|
||||
/**
|
||||
* @brief Power down flags for rtc_sleep_pd function
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep
|
||||
uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep
|
||||
uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep
|
||||
uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep
|
||||
uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep
|
||||
uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep
|
||||
uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep
|
||||
} rtc_sleep_pd_config_t;
|
||||
|
||||
/**
|
||||
* Initializer for rtc_sleep_pd_config_t which sets all flags to the same value
|
||||
*/
|
||||
#define RTC_SLEEP_PD_CONFIG_ALL(val) {\
|
||||
.dig_fpu = (val), \
|
||||
.rtc_fpu = (val), \
|
||||
.cpu_fpu = (val), \
|
||||
.i2s_fpu = (val), \
|
||||
.bb_fpu = (val), \
|
||||
.nrx_fpu = (val), \
|
||||
.fe_fpu = (val), \
|
||||
}
|
||||
|
||||
void rtc_sleep_pd(rtc_sleep_pd_config_t cfg);
|
||||
|
||||
/**
|
||||
* @brief sleep configuration for rtc_sleep_init function
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory)
|
||||
uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used)
|
||||
uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory
|
||||
uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory
|
||||
uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals
|
||||
uint32_t wifi_pd_en : 1; //!< power down WiFi
|
||||
uint32_t deep_slp : 1; //!< power down digital domain
|
||||
uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode
|
||||
uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode
|
||||
uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode
|
||||
uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode
|
||||
uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode
|
||||
uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator
|
||||
uint32_t deep_slp_reject : 1;
|
||||
uint32_t light_slp_reject : 1;
|
||||
} rtc_sleep_config_t;
|
||||
|
||||
/**
|
||||
* Default initializer for rtc_sleep_config_t
|
||||
*
|
||||
* This initializer sets all fields to "reasonable" values (e.g. suggested for
|
||||
* production use) based on a combination of RTC_SLEEP_PD_x flags.
|
||||
*
|
||||
* @param RTC_SLEEP_PD_x flags combined using bitwise OR
|
||||
*/
|
||||
#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \
|
||||
.lslp_mem_inf_fpu = 0, \
|
||||
.rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \
|
||||
.rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \
|
||||
.rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \
|
||||
.rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \
|
||||
.wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \
|
||||
.deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \
|
||||
.wdt_flashboot_mod_en = 0, \
|
||||
.dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \
|
||||
.dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \
|
||||
.rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \
|
||||
.rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \
|
||||
.vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \
|
||||
.deep_slp_reject = 1, \
|
||||
.light_slp_reject = 1 \
|
||||
};
|
||||
|
||||
#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain)
|
||||
#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals
|
||||
#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory
|
||||
#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory
|
||||
#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU
|
||||
#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator
|
||||
#define RTC_SLEEP_PD_WIFI BIT(6)
|
||||
|
||||
/**
|
||||
* @brief Prepare the chip to enter sleep mode
|
||||
*
|
||||
* This function configures various power control state machines to handle
|
||||
* entry into light sleep or deep sleep mode, switches APB and CPU clock source
|
||||
* (usually to XTAL), and sets bias voltages for digital and RTC power domains.
|
||||
*
|
||||
* This function does not actually enter sleep mode; this is done using
|
||||
* rtc_sleep_start function. Software may do some other actions between
|
||||
* rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure
|
||||
* wakeup sources.
|
||||
* @param cfg sleep mode configuration
|
||||
*/
|
||||
void rtc_sleep_init(rtc_sleep_config_t cfg);
|
||||
|
||||
|
||||
/**
|
||||
* @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source
|
||||
* @param t value of RTC counter at which wakeup from sleep will happen;
|
||||
* only the lower 48 bits are used
|
||||
*/
|
||||
void rtc_sleep_set_wakeup_time(uint64_t t);
|
||||
|
||||
|
||||
#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup
|
||||
#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup
|
||||
#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only)
|
||||
#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup
|
||||
#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only)
|
||||
#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only)
|
||||
#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only)
|
||||
#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only)
|
||||
#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup
|
||||
#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup
|
||||
#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only)
|
||||
#define RTC_COCPU_TRIG_EN BIT(11)
|
||||
#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12)
|
||||
#define RTC_COCPU_TRAP_TRIG_EN BIT(13)
|
||||
#define RTC_USB_TRIG_EN BIT(14)
|
||||
|
||||
/**
|
||||
* @brief Enter deep or light sleep mode
|
||||
*
|
||||
* This function enters the sleep mode previously configured using rtc_sleep_init
|
||||
* function. Before entering sleep, software should configure wake up sources
|
||||
* appropriately (set up GPIO wakeup registers, timer wakeup registers,
|
||||
* and so on).
|
||||
*
|
||||
* If deep sleep mode was configured using rtc_sleep_init, and sleep is not
|
||||
* rejected by hardware (based on reject_opt flags), this function never returns.
|
||||
* When the chip wakes up from deep sleep, CPU is reset and execution starts
|
||||
* from ROM bootloader.
|
||||
*
|
||||
* If light sleep mode was configured using rtc_sleep_init, this function
|
||||
* returns on wakeup, or if sleep is rejected by hardware.
|
||||
*
|
||||
* @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags
|
||||
* combined with OR)
|
||||
* @param reject_opt bit mask of sleep reject reasons:
|
||||
* - RTC_CNTL_GPIO_REJECT_EN
|
||||
* - RTC_CNTL_SDIO_REJECT_EN
|
||||
* These flags are used to prevent entering sleep when e.g.
|
||||
* an external host is communicating via SDIO slave
|
||||
* @return non-zero if sleep was rejected by hardware
|
||||
*/
|
||||
uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu);
|
||||
|
||||
/**
|
||||
* RTC power and clock control initialization settings
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready
|
||||
uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready
|
||||
uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready
|
||||
uint32_t clkctl_init : 1; //!< Perform clock control related initialization
|
||||
uint32_t pwrctl_init : 1; //!< Perform power control related initialization
|
||||
uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST
|
||||
uint32_t xtal_fpu : 1;
|
||||
uint32_t bbpll_fpu : 1;
|
||||
uint32_t cpu_waiti_clk_gate : 1;
|
||||
} rtc_config_t;
|
||||
|
||||
/**
|
||||
* Default initializer of rtc_config_t.
|
||||
*
|
||||
* This initializer sets all fields to "reasonable" values (e.g. suggested for
|
||||
* production use).
|
||||
*/
|
||||
#define RTC_CONFIG_DEFAULT() {\
|
||||
.ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \
|
||||
.xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \
|
||||
.pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \
|
||||
.clkctl_init = 1, \
|
||||
.pwrctl_init = 1, \
|
||||
.rtc_dboost_fpd = 1, \
|
||||
.xtal_fpu = 0, \
|
||||
.bbpll_fpu = 0, \
|
||||
.cpu_waiti_clk_gate = 1\
|
||||
}
|
||||
|
||||
/**
|
||||
* Initialize RTC clock and power control related functions
|
||||
* @param cfg configuration options as rtc_config_t
|
||||
*/
|
||||
void rtc_init(rtc_config_t cfg);
|
||||
|
||||
/**
|
||||
* Structure describing vddsdio configuration
|
||||
*/
|
||||
typedef struct {
|
||||
uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins.
|
||||
uint32_t enable : 1; //!< Enable VDDSDIO regulator
|
||||
uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V
|
||||
uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator
|
||||
uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator
|
||||
uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator
|
||||
} rtc_vddsdio_config_t;
|
||||
|
||||
/**
|
||||
* Get current VDDSDIO configuration
|
||||
* If VDDSDIO configuration is overridden by RTC, get values from RTC
|
||||
* Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE
|
||||
* Otherwise, use default values and the level of MTDI bootstrapping pin.
|
||||
* @return currently used VDDSDIO configuration
|
||||
*/
|
||||
rtc_vddsdio_config_t rtc_vddsdio_get_config(void);
|
||||
|
||||
/**
|
||||
* Set new VDDSDIO configuration using RTC registers.
|
||||
* If config.force == 1, this overrides configuration done using bootstrapping
|
||||
* pins and EFUSE.
|
||||
*
|
||||
* @param config new VDDSDIO configuration
|
||||
*/
|
||||
void rtc_vddsdio_set_config(rtc_vddsdio_config_t config);
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
3588
components/soc/soc/esp32s3/include/soc/rtc_cntl_reg.h
Normal file
3588
components/soc/soc/esp32s3/include/soc/rtc_cntl_reg.h
Normal file
File diff suppressed because it is too large
Load diff
967
components/soc/soc/esp32s3/include/soc/rtc_cntl_struct.h
Normal file
967
components/soc/soc/esp32s3/include/soc/rtc_cntl_struct.h
Normal file
|
|
@ -0,0 +1,967 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/
|
||||
uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/
|
||||
uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/
|
||||
uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/
|
||||
uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/
|
||||
uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/
|
||||
uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/
|
||||
uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/
|
||||
uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/
|
||||
uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/
|
||||
uint32_t xtl_force_pd: 1; /*crystall force power down*/
|
||||
uint32_t xtl_force_pu: 1; /*crystall force power up*/
|
||||
uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/
|
||||
uint32_t reserved18: 5;
|
||||
uint32_t xtl_force_iso: 1;
|
||||
uint32_t pll_force_iso: 1;
|
||||
uint32_t analog_force_iso: 1;
|
||||
uint32_t xtl_force_noiso: 1;
|
||||
uint32_t pll_force_noiso: 1;
|
||||
uint32_t analog_force_noiso: 1;
|
||||
uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/
|
||||
uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/
|
||||
uint32_t sw_sys_rst: 1; /*SW system reset*/
|
||||
};
|
||||
uint32_t val;
|
||||
} options0;
|
||||
uint32_t slp_timer0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/
|
||||
uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_timer1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/
|
||||
uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/
|
||||
uint32_t timer_sys_rst: 1; /*enable to record system reset time*/
|
||||
uint32_t reserved30: 1;
|
||||
uint32_t update: 1; /*Set 1: to update register with RTC timer*/
|
||||
};
|
||||
uint32_t val;
|
||||
} time_update;
|
||||
uint32_t time_low0; /*RTC timer low 32 bits*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_timer_value0_high: 16; /*RTC timer high 16 bits*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} time_high0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/
|
||||
uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/
|
||||
uint32_t reserved2: 20;
|
||||
uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/
|
||||
uint32_t reserved23: 5;
|
||||
uint32_t sdio_active_ind: 1; /*SDIO active indication*/
|
||||
uint32_t slp_wakeup: 1; /*leep wakeup bit*/
|
||||
uint32_t slp_reject: 1; /*leep reject bit*/
|
||||
uint32_t sleep_en: 1; /*sleep enable bit*/
|
||||
};
|
||||
uint32_t val;
|
||||
} state0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/
|
||||
uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/
|
||||
uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/
|
||||
uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/
|
||||
uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/
|
||||
};
|
||||
uint32_t val;
|
||||
} timer1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 15;
|
||||
uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/
|
||||
uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/
|
||||
};
|
||||
uint32_t val;
|
||||
} timer2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wifi_wait_timer: 9;
|
||||
uint32_t wifi_powerup_timer: 7;
|
||||
uint32_t rom_ram_wait_timer: 9;
|
||||
uint32_t rom_ram_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_wait_timer: 9;
|
||||
uint32_t rtc_powerup_timer: 7;
|
||||
uint32_t dg_wrap_wait_timer: 9;
|
||||
uint32_t dg_wrap_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 8;
|
||||
uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/
|
||||
uint32_t rtcmem_wait_timer: 9;
|
||||
uint32_t rtcmem_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer5;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 16;
|
||||
uint32_t dg_dcdc_wait_timer: 9;
|
||||
uint32_t dg_dcdc_powerup_timer: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} timer6;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 18;
|
||||
uint32_t i2c_reset_por_force_pd: 1;
|
||||
uint32_t i2c_reset_por_force_pu: 1;
|
||||
uint32_t glitch_rst_en: 1;
|
||||
uint32_t reserved21: 1; /*PLLA force power down*/
|
||||
uint32_t sar_i2c_pu: 1; /*PLLA force power up*/
|
||||
uint32_t plla_force_pd: 1; /*PLLA force power down*/
|
||||
uint32_t plla_force_pu: 1; /*PLLA force power up*/
|
||||
uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/
|
||||
uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/
|
||||
uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/
|
||||
uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/
|
||||
uint32_t reserved29: 1;
|
||||
uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/
|
||||
uint32_t pll_i2c_pu: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ana_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/
|
||||
uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/
|
||||
uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/
|
||||
uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/
|
||||
uint32_t reset_flag_procpu: 1; /*PRO CPU reset_flag*/
|
||||
uint32_t reset_flag_appcpu: 1; /*APP CPU reset flag*/
|
||||
uint32_t reset_flag_procpu_clr: 1; /*clear PRO CPU reset_flag*/
|
||||
uint32_t reset_flag_appcpu_clr: 1; /*clear APP CPU reset flag*/
|
||||
uint32_t appcpu_ocd_halt_on_reset: 1; /*APPCPU OcdHaltOnReset*/
|
||||
uint32_t procpu_ocd_halt_on_reset: 1; /*PROCPU OcdHaltOnReset*/
|
||||
uint32_t reset_flag_jtag_procpu: 1;
|
||||
uint32_t reset_flag_jtag_appcpu: 1;
|
||||
uint32_t reset_flag_jtag_procpu_clr: 1;
|
||||
uint32_t reset_flag_jtag_appcpu_clr: 1;
|
||||
uint32_t rtc_app_dreset_mask: 1;
|
||||
uint32_t rtc_pro_dreset_mask: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} reset_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 15;
|
||||
uint32_t rtc_wakeup_ena: 17; /*wakeup enable bitmap*/
|
||||
};
|
||||
uint32_t val;
|
||||
} wakeup_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/
|
||||
uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t rtc_touch_scan_done: 1; /*enable touch scan done interrupt*/
|
||||
uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/
|
||||
uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/
|
||||
uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/
|
||||
uint32_t rtc_touch_inactive: 1; /*enable touch inactive interrupt*/
|
||||
uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/
|
||||
uint32_t rtc_tsens: 1; /*enable tsens interrupt*/
|
||||
uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/
|
||||
uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/
|
||||
uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/
|
||||
uint32_t rtc_cocpu_trap: 1; /*enable cocpu trap interrupt*/
|
||||
uint32_t rtc_touch_timeout: 1; /*enable touch timeout interrupt*/
|
||||
uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/
|
||||
uint32_t rtc_touch_approach_loop_done: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt raw*/
|
||||
uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/
|
||||
uint32_t rtc_touch_scan_done: 1;
|
||||
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/
|
||||
uint32_t rtc_touch_done: 1; /*touch interrupt raw*/
|
||||
uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/
|
||||
uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt raw*/
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/
|
||||
uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/
|
||||
uint32_t rtc_tsens: 1; /*tsens interrupt raw*/
|
||||
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/
|
||||
uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/
|
||||
uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/
|
||||
uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt raw*/
|
||||
uint32_t rtc_touch_timeout: 1; /*touch timeout interrupt raw*/
|
||||
uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/
|
||||
uint32_t rtc_touch_approach_loop_done: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*sleep reject interrupt state*/
|
||||
uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/
|
||||
uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/
|
||||
uint32_t rtc_touch_scan_done: 1;
|
||||
uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/
|
||||
uint32_t rtc_touch_done: 1; /*touch done interrupt state*/
|
||||
uint32_t rtc_touch_active: 1; /*touch active interrupt state*/
|
||||
uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt state*/
|
||||
uint32_t rtc_brown_out: 1; /*brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/
|
||||
uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/
|
||||
uint32_t rtc_tsens: 1; /*tsens interrupt state*/
|
||||
uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/
|
||||
uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/
|
||||
uint32_t rtc_swd: 1; /*super watch dog interrupt state*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/
|
||||
uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt state*/
|
||||
uint32_t rtc_touch_timeout: 1; /*Touch timeout interrupt state*/
|
||||
uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/
|
||||
uint32_t rtc_touch_approach_loop_done: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/
|
||||
uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/
|
||||
uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/
|
||||
uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t rtc_touch_scan_done: 1;
|
||||
uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/
|
||||
uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/
|
||||
uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/
|
||||
uint32_t rtc_touch_inactive: 1; /*Clear touch inactive interrupt state*/
|
||||
uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/
|
||||
uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/
|
||||
uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/
|
||||
uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/
|
||||
uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/
|
||||
uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/
|
||||
uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/
|
||||
uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/
|
||||
uint32_t rtc_cocpu_trap: 1; /*Clear cocpu trap interrupt state*/
|
||||
uint32_t rtc_touch_timeout: 1; /*Clear touch timeout interrupt state*/
|
||||
uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/
|
||||
uint32_t rtc_touch_approach_loop_done: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
uint32_t store[4]; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/
|
||||
uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/
|
||||
uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/
|
||||
uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/
|
||||
uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/
|
||||
uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/
|
||||
uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/
|
||||
uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/
|
||||
uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/
|
||||
uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/
|
||||
uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/
|
||||
uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/
|
||||
uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/
|
||||
uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/
|
||||
uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/
|
||||
uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/
|
||||
uint32_t reserved24: 6;
|
||||
uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/
|
||||
uint32_t ctr_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_xtl_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 29;
|
||||
uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/
|
||||
uint32_t wakeup0_lv: 1; /*0: external wakeup at low level*/
|
||||
uint32_t wakeup1_lv: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 12;
|
||||
uint32_t rtc_sleep_reject_ena: 18; /*sleep reject enable*/
|
||||
uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/
|
||||
uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_reject_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 29;
|
||||
uint32_t cpusel_conf: 1; /*CPU sel option*/
|
||||
uint32_t cpuperiod_sel: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} cpu_period_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 22;
|
||||
uint32_t sdio_act_dnum: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_act_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 3;
|
||||
uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/
|
||||
uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/
|
||||
uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/
|
||||
uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/
|
||||
uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/
|
||||
uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/
|
||||
uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/
|
||||
uint32_t reserved11: 1;
|
||||
uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/
|
||||
uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/
|
||||
uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/
|
||||
uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/
|
||||
uint32_t ck8m_force_pd: 1; /*CK8M force power down*/
|
||||
uint32_t ck8m_force_pu: 1; /*CK8M force power up*/
|
||||
uint32_t reserved27: 2;
|
||||
uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/
|
||||
uint32_t ana_clk_rtc_sel: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 22;
|
||||
uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/
|
||||
uint32_t rtc_ana_clk_div: 8;
|
||||
uint32_t slow_clk_next_edge: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slow_clk_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/
|
||||
uint32_t reserved8: 1;
|
||||
uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/
|
||||
uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/
|
||||
uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/
|
||||
uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/
|
||||
uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/
|
||||
uint32_t sdio_modecurlim: 1; /*select current limit mode*/
|
||||
uint32_t sdio_encurlim: 1; /*enable current limit*/
|
||||
uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/
|
||||
uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/
|
||||
uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/
|
||||
uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/
|
||||
uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/
|
||||
uint32_t xpd_sdio: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t bias_buf_idle: 1;
|
||||
uint32_t bias_buf_wake: 1;
|
||||
uint32_t bias_buf_deep_slp: 1;
|
||||
uint32_t bias_buf_monitor: 1;
|
||||
uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/
|
||||
uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/
|
||||
uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/
|
||||
uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/
|
||||
uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/
|
||||
uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} bias_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t dig_cal_en: 1;
|
||||
uint32_t reserved8: 6;
|
||||
uint32_t sck_dcap: 8; /*SCK_DCAP*/
|
||||
uint32_t reserved22: 6;
|
||||
uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/
|
||||
uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/
|
||||
uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/
|
||||
uint32_t rtculator_force_pu: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/
|
||||
uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/
|
||||
uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/
|
||||
uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/
|
||||
uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/
|
||||
uint32_t rtc_force_noiso: 1; /*rtc_peri force no ISO*/
|
||||
uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU*/
|
||||
uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/
|
||||
uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/
|
||||
uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU*/
|
||||
uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/
|
||||
uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/
|
||||
uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/
|
||||
uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/
|
||||
uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/
|
||||
uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/
|
||||
uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/
|
||||
uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/
|
||||
uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/
|
||||
uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/
|
||||
uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/
|
||||
uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pwc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 3;
|
||||
uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/
|
||||
uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/
|
||||
uint32_t rom0_force_pd: 1; /*ROM force power down*/
|
||||
uint32_t rom0_force_pu: 1; /*ROM force power up*/
|
||||
uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/
|
||||
uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/
|
||||
uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/
|
||||
uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/
|
||||
uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/
|
||||
uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/
|
||||
uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/
|
||||
uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/
|
||||
uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/
|
||||
uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/
|
||||
uint32_t wifi_force_pd: 1; /*wifi force power down*/
|
||||
uint32_t wifi_force_pu: 1; /*wifi force power up*/
|
||||
uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/
|
||||
uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/
|
||||
uint32_t dg_dcdc_force_pd: 1; /*digital dcdc force power down*/
|
||||
uint32_t dg_dcdc_force_pu: 1; /*digital dcdc force power up*/
|
||||
uint32_t dg_dcdc_pd_en: 1; /*enable power down digital dcdc in sleep*/
|
||||
uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/
|
||||
uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/
|
||||
uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/
|
||||
uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/
|
||||
uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/
|
||||
uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/
|
||||
uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/
|
||||
uint32_t dg_wrap_pd_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dig_pwc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t dig_iso_force_off: 1;
|
||||
uint32_t dig_iso_force_on: 1;
|
||||
uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/
|
||||
uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/
|
||||
uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/
|
||||
uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/
|
||||
uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/
|
||||
uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/
|
||||
uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/
|
||||
uint32_t rom0_force_iso: 1; /*ROM force ISO*/
|
||||
uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/
|
||||
uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/
|
||||
uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/
|
||||
uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/
|
||||
uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/
|
||||
uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/
|
||||
uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/
|
||||
uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/
|
||||
uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/
|
||||
uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/
|
||||
uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/
|
||||
uint32_t wifi_force_iso: 1; /*wifi force ISO*/
|
||||
uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/
|
||||
uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/
|
||||
uint32_t dg_wrap_force_noiso: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} dig_iso;
|
||||
union {
|
||||
struct {
|
||||
uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/
|
||||
uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/
|
||||
uint32_t pause_in_slp: 1; /*pause WDT in sleep*/
|
||||
uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/
|
||||
uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/
|
||||
uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/
|
||||
uint32_t sys_reset_length: 3; /*system reset counter length*/
|
||||
uint32_t cpu_reset_length: 3; /*CPU reset counter length*/
|
||||
uint32_t stg3: 3; /*1: interrupt stage en*/
|
||||
uint32_t stg2: 3; /*1: interrupt stage en*/
|
||||
uint32_t stg1: 3; /*1: interrupt stage en*/
|
||||
uint32_t stg0: 3; /*1: interrupt stage en*/
|
||||
uint32_t en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} wdt_config0;
|
||||
uint32_t wdt_config1; /**/
|
||||
uint32_t wdt_config2; /**/
|
||||
uint32_t wdt_config3; /**/
|
||||
uint32_t wdt_config4; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t feed: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} wdt_feed;
|
||||
uint32_t wdt_wprotect; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t swd_reset_flag: 1; /*swd reset flag*/
|
||||
uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/
|
||||
uint32_t reserved2: 15;
|
||||
uint32_t swd_bypass_rst: 1;
|
||||
uint32_t swd_signal_width: 10; /*adjust signal width send to swd*/
|
||||
uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/
|
||||
uint32_t swd_feed: 1; /*Sw feed swd*/
|
||||
uint32_t swd_disable: 1; /*disabel SWD*/
|
||||
uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/
|
||||
};
|
||||
uint32_t val;
|
||||
} swd_conf;
|
||||
uint32_t swd_wprotect; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 20;
|
||||
uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/
|
||||
uint32_t procpu_c1: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sw_cpu_stall;
|
||||
uint32_t store4; /**/
|
||||
uint32_t store5; /**/
|
||||
uint32_t store6; /**/
|
||||
uint32_t store7; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t xpd_rom0: 1; /*rom0 power down*/
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/
|
||||
uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/
|
||||
uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/
|
||||
uint32_t wifi_iso: 1; /*wifi iso*/
|
||||
uint32_t xpd_wifi: 1; /*wifi wrap power down*/
|
||||
uint32_t dig_iso: 1; /*digital wrap iso*/
|
||||
uint32_t xpd_dig: 1; /*digital wrap power down*/
|
||||
uint32_t rtc_touch_state_start: 1; /*touch should start to work*/
|
||||
uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/
|
||||
uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/
|
||||
uint32_t rtc_touch_state_done: 1; /*touch is done*/
|
||||
uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/
|
||||
uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/
|
||||
uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/
|
||||
uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/
|
||||
uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/
|
||||
uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/
|
||||
uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/
|
||||
uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/
|
||||
uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/
|
||||
uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/
|
||||
uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/
|
||||
uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/
|
||||
uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/
|
||||
uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/
|
||||
uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/
|
||||
uint32_t rtc_main_state: 4; /*rtc main state machine status*/
|
||||
};
|
||||
uint32_t val;
|
||||
} low_power_st;
|
||||
uint32_t diag0; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_pad0_hold: 1;
|
||||
uint32_t touch_pad1_hold: 1;
|
||||
uint32_t touch_pad2_hold: 1;
|
||||
uint32_t touch_pad3_hold: 1;
|
||||
uint32_t touch_pad4_hold: 1;
|
||||
uint32_t touch_pad5_hold: 1;
|
||||
uint32_t touch_pad6_hold: 1;
|
||||
uint32_t touch_pad7_hold: 1;
|
||||
uint32_t touch_pad8_hold: 1;
|
||||
uint32_t touch_pad9_hold: 1;
|
||||
uint32_t touch_pad10_hold: 1;
|
||||
uint32_t touch_pad11_hold: 1;
|
||||
uint32_t touch_pad12_hold: 1;
|
||||
uint32_t touch_pad13_hold: 1;
|
||||
uint32_t touch_pad14_hold: 1;
|
||||
uint32_t x32p_hold: 1;
|
||||
uint32_t x32n_hold: 1;
|
||||
uint32_t pdac1_hold: 1;
|
||||
uint32_t pdac2_hold: 1;
|
||||
uint32_t rtc_pad19_hold: 1;
|
||||
uint32_t rtc_pad20_hold: 1;
|
||||
uint32_t rtc_pad21_hold: 1;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} pad_hold;
|
||||
uint32_t dig_pad_hold; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/
|
||||
uint32_t status_clr: 1; /*clear ext wakeup1 status*/
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t status: 22; /*ext wakeup1 status*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup1_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 4;
|
||||
uint32_t int_wait: 10; /*brown out interrupt wait cycles*/
|
||||
uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/
|
||||
uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/
|
||||
uint32_t rst_wait: 10; /*brown out reset wait cycles*/
|
||||
uint32_t rst_ena: 1; /*enable brown out reset*/
|
||||
uint32_t rst_sel: 1; /*1: 4-pos reset*/
|
||||
uint32_t ana_rst_en: 1;
|
||||
uint32_t cnt_clr: 1; /*clear brown out counter*/
|
||||
uint32_t ena: 1; /*enable brown out*/
|
||||
uint32_t det: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} brown_out;
|
||||
uint32_t time_low1; /*RTC timer low 32 bits*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_timer_value1_high: 16; /*RTC timer high 16 bits*/
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} time_high1;
|
||||
uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/
|
||||
uint32_t xtal32k_restart_wait: 16; /*cycles to wait to repower on xtal 32k*/
|
||||
uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/
|
||||
uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal32k_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ulp_cp_pc_init: 11; /*ULP-coprocessor PC initial address*/
|
||||
uint32_t reserved11: 18;
|
||||
uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/
|
||||
uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/
|
||||
uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ulp_cp_timer;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ulp_cp_mem_addr_init: 11;
|
||||
uint32_t ulp_cp_mem_addr_size: 11;
|
||||
uint32_t ulp_cp_mem_offst_clr: 1;
|
||||
uint32_t reserved23: 5;
|
||||
uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/
|
||||
uint32_t ulp_cp_reset: 1; /*ulp coprocessor clk software reset*/
|
||||
uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW*/
|
||||
uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ulp_cp_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cocpu_clk_fo: 1; /*cocpu clk force on*/
|
||||
uint32_t cocpu_start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/
|
||||
uint32_t cocpu_start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/
|
||||
uint32_t cocpu_shut: 1; /*to shut cocpu*/
|
||||
uint32_t cocpu_shut_2_clk_dis: 8; /*time from shut cocpu to disable clk*/
|
||||
uint32_t cocpu_shut_reset_en: 1; /*to reset cocpu*/
|
||||
uint32_t cocpu_sel: 1; /*1: old ULP 0: new riscV*/
|
||||
uint32_t cocpu_done_force: 1; /*1: select riscv done 0: select ulp done*/
|
||||
uint32_t cocpu_done: 1; /*done signal used by riscv to control timer.*/
|
||||
uint32_t cocpu_sw_int_trigger: 1; /*trigger cocpu register interrupt*/
|
||||
uint32_t cocpu_clkgate_en: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} cocpu_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_sleep_cycles: 16; /*sleep cycles for timer*/
|
||||
uint32_t touch_meas_num: 16; /*the meas length (in 8MHz)*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 2;
|
||||
uint32_t touch_drange: 2; /*TOUCH_DRANGE*/
|
||||
uint32_t touch_drefl: 2; /*TOUCH_DREFL*/
|
||||
uint32_t touch_drefh: 2; /*TOUCH_DREFH*/
|
||||
uint32_t touch_xpd_bias: 1; /*TOUCH_XPD_BIAS*/
|
||||
uint32_t touch_refc: 3; /*TOUCH pad0 reference cap*/
|
||||
uint32_t touch_dbias: 1; /*1:use self bias 0:use bandgap bias*/
|
||||
uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/
|
||||
uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/
|
||||
uint32_t touch_start_en: 1; /*1: start touch fsm*/
|
||||
uint32_t touch_start_force: 1; /*1: to start touch fsm by SW*/
|
||||
uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/
|
||||
uint32_t touch_slp_cyc_div: 2; /*when a touch pad is active*/
|
||||
uint32_t touch_timer_force_done: 2; /*force touch timer done*/
|
||||
uint32_t touch_reset: 1; /*reset upgrade touch*/
|
||||
uint32_t touch_clk_fo: 1; /*touch clock force on*/
|
||||
uint32_t touch_clkgate_en: 1; /*touch clock enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_denoise_res: 2; /*De-noise resolution: 12/10/8/4 bit*/
|
||||
uint32_t touch_denoise_en: 1; /*touch pad0 will be used to de-noise*/
|
||||
uint32_t reserved3: 5;
|
||||
uint32_t touch_inactive_connection: 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/
|
||||
uint32_t touch_shield_pad_en: 1; /*touch pad14 will be used as shield*/
|
||||
uint32_t touch_scan_pad_map: 15; /*touch scan mode pad enable map*/
|
||||
uint32_t touch_bufdrv: 3; /*touch7 buffer driver strength*/
|
||||
uint32_t touch_out_ring: 4; /*select out ring pad*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_scan_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_slp_th: 22; /*the threshold for sleep touch pad*/
|
||||
uint32_t reserved22: 4;
|
||||
uint32_t touch_slp_approach_en: 1; /*sleep pad approach function enable*/
|
||||
uint32_t touch_slp_pad: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_slp_thres;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 23;
|
||||
uint32_t touch_slp_channel_clr: 1; /*clear touch slp channel*/
|
||||
uint32_t touch_approach_meas_time: 8; /*approach pads total meas times*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_approach;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 7;
|
||||
uint32_t touch_bypass_neg_noise_thres: 1;
|
||||
uint32_t touch_bypass_noise_thres: 1;
|
||||
uint32_t touch_smooth_lvl: 2;
|
||||
uint32_t touch_jitter_step: 4; /*touch jitter step*/
|
||||
uint32_t touch_neg_noise_limit: 4; /*negative threshold counter limit*/
|
||||
uint32_t touch_neg_noise_thres: 2;
|
||||
uint32_t touch_noise_thres: 2;
|
||||
uint32_t touch_hysteresis: 2;
|
||||
uint32_t touch_debounce: 3; /*debounce counter*/
|
||||
uint32_t touch_filter_mode: 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/
|
||||
uint32_t touch_filter_en: 1; /*touch filter enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_filter_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usb_vrefh: 2;
|
||||
uint32_t usb_vrefl: 2;
|
||||
uint32_t usb_vref_override: 1;
|
||||
uint32_t usb_pad_pull_override: 1;
|
||||
uint32_t usb_dp_pullup: 1;
|
||||
uint32_t usb_dp_pulldown: 1;
|
||||
uint32_t usb_dm_pullup: 1;
|
||||
uint32_t usb_dm_pulldown: 1;
|
||||
uint32_t usb_pullup_value: 1;
|
||||
uint32_t usb_pad_enable_override: 1;
|
||||
uint32_t usb_pad_enable: 1;
|
||||
uint32_t usb_txm: 1;
|
||||
uint32_t usb_txp: 1;
|
||||
uint32_t usb_tx_en: 1;
|
||||
uint32_t usb_tx_en_override: 1;
|
||||
uint32_t usb_reset_disable: 1;
|
||||
uint32_t io_mux_reset_disable: 1;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} usb_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_timeout_num: 22;
|
||||
uint32_t touch_timeout_en: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_timeout_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reject_cause: 18; /*sleep reject cause*/
|
||||
uint32_t reserved18: 14;
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_reject_cause;
|
||||
union {
|
||||
struct {
|
||||
uint32_t force_download_boot: 1;
|
||||
uint32_t reserved1: 31;
|
||||
};
|
||||
uint32_t val;
|
||||
} option1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wakeup_cause: 17; /*sleep wakeup cause*/
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slp_wakeup_cause;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 8;
|
||||
uint32_t ulp_cp_timer_slp_cycle: 24; /*sleep cycles for ULP-coprocessor timer*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ulp_cp_timer_1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t sdio_idle_w1ts: 1; /*enable SDIO idle interrupt*/
|
||||
uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t rtc_touch_scan_done_w1ts: 1; /*enable touch scan done interrupt*/
|
||||
uint32_t rtc_ulp_cp_w1ts: 1; /*enable ULP-coprocessor interrupt*/
|
||||
uint32_t rtc_touch_done_w1ts: 1; /*enable touch done interrupt*/
|
||||
uint32_t rtc_touch_active_w1ts: 1; /*enable touch active interrupt*/
|
||||
uint32_t rtc_touch_inactive_w1ts: 1; /*enable touch inactive interrupt*/
|
||||
uint32_t w1ts: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t rtc_saradc1_w1ts: 1; /*enable saradc1 interrupt*/
|
||||
uint32_t rtc_tsens_w1ts: 1; /*enable tsens interrupt*/
|
||||
uint32_t rtc_cocpu_w1ts: 1; /*enable riscV cocpu interrupt*/
|
||||
uint32_t rtc_saradc2_w1ts: 1; /*enable saradc2 interrupt*/
|
||||
uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/
|
||||
uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/
|
||||
uint32_t rtc_cocpu_trap_w1ts: 1; /*enable cocpu trap interrupt*/
|
||||
uint32_t rtc_touch_timeout_w1ts: 1; /*enable touch timeout interrupt*/
|
||||
uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/
|
||||
uint32_t rtc_touch_approach_loop_done_w1ts: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/
|
||||
uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/
|
||||
uint32_t sdio_idle_w1tc: 1; /*enable SDIO idle interrupt*/
|
||||
uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/
|
||||
uint32_t rtc_touch_scan_done_w1tc: 1; /*enable touch scan done interrupt*/
|
||||
uint32_t rtc_ulp_cp_w1tc: 1; /*enable ULP-coprocessor interrupt*/
|
||||
uint32_t rtc_touch_done_w1tc: 1; /*enable touch done interrupt*/
|
||||
uint32_t rtc_touch_active_w1tc: 1; /*enable touch active interrupt*/
|
||||
uint32_t rtc_touch_inactive_w1tc: 1; /*enable touch inactive interrupt*/
|
||||
uint32_t w1tc: 1; /*enable brown out interrupt*/
|
||||
uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/
|
||||
uint32_t rtc_saradc1_w1tc: 1; /*enable saradc1 interrupt*/
|
||||
uint32_t rtc_tsens_w1tc: 1; /*enable tsens interrupt*/
|
||||
uint32_t rtc_cocpu_w1tc: 1; /*enable riscV cocpu interrupt*/
|
||||
uint32_t rtc_saradc2_w1tc: 1; /*enable saradc2 interrupt*/
|
||||
uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/
|
||||
uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/
|
||||
uint32_t rtc_cocpu_trap_w1tc: 1; /*enable cocpu trap interrupt*/
|
||||
uint32_t rtc_touch_timeout_w1tc: 1; /*enable touch timeout interrupt*/
|
||||
uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/
|
||||
uint32_t rtc_touch_approach_loop_done_w1tc: 1;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t retention_en: 1;
|
||||
uint32_t retention_wait: 5; /*wait cycles for rention operation*/
|
||||
};
|
||||
uint32_t val;
|
||||
} retention_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/
|
||||
uint32_t reserved3: 29;
|
||||
};
|
||||
uint32_t val;
|
||||
} fib_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_cntl_dev_t;
|
||||
|
||||
extern rtc_cntl_dev_t RTCCNTL;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
70
components/soc/soc/esp32s3/include/soc/rtc_gpio_channel.h
Normal file
70
components/soc/soc/esp32s3/include/soc/rtc_gpio_channel.h
Normal file
|
|
@ -0,0 +1,70 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
//RTC GPIO channels
|
||||
#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0
|
||||
#define RTCIO_CHANNEL_0_GPIO_NUM 36
|
||||
|
||||
#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1
|
||||
#define RTCIO_CHANNEL_1_GPIO_NUM 37
|
||||
|
||||
#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2
|
||||
#define RTCIO_CHANNEL_2_GPIO_NUM 38
|
||||
|
||||
#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3
|
||||
#define RTCIO_CHANNEL_3_GPIO_NUM 39
|
||||
|
||||
#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4
|
||||
#define RTCIO_CHANNEL_4_GPIO_NUM 34
|
||||
|
||||
#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5
|
||||
#define RTCIO_CHANNEL_5_GPIO_NUM 35
|
||||
|
||||
#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6
|
||||
#define RTCIO_CHANNEL_6_GPIO_NUM 25
|
||||
|
||||
#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7
|
||||
#define RTCIO_CHANNEL_7_GPIO_NUM 26
|
||||
|
||||
#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8
|
||||
#define RTCIO_CHANNEL_8_GPIO_NUM 33
|
||||
|
||||
#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9
|
||||
#define RTCIO_CHANNEL_9_GPIO_NUM 32
|
||||
|
||||
#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10
|
||||
#define RTCIO_CHANNEL_10_GPIO_NUM 4
|
||||
|
||||
#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11
|
||||
#define RTCIO_CHANNEL_11_GPIO_NUM 0
|
||||
|
||||
#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12
|
||||
#define RTCIO_CHANNEL_12_GPIO_NUM 2
|
||||
|
||||
#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13
|
||||
#define RTCIO_CHANNEL_13_GPIO_NUM 15
|
||||
|
||||
#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14
|
||||
#define RTCIO_CHANNEL_14_GPIO_NUM 13
|
||||
|
||||
#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15
|
||||
#define RTCIO_CHANNEL_15_GPIO_NUM 12
|
||||
|
||||
#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16
|
||||
#define RTCIO_CHANNEL_16_GPIO_NUM 14
|
||||
|
||||
#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17
|
||||
#define RTCIO_CHANNEL_17_GPIO_NUM 27
|
||||
680
components/soc/soc/esp32s3/include/soc/rtc_i2c_reg.h
Normal file
680
components/soc/soc/esp32s3/include/soc/rtc_i2c_reg.h
Normal file
|
|
@ -0,0 +1,680 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000)
|
||||
/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
|
||||
/*description: time period that scl = 0*/
|
||||
#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V) << (RTC_I2C_SCL_LOW_PERIOD_S))
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_LOW_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004)
|
||||
/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: rtc i2c reg clk gating*/
|
||||
#define RTC_I2C_CLK_EN (BIT(31))
|
||||
#define RTC_I2C_CLK_EN_M (BIT(31))
|
||||
#define RTC_I2C_CLK_EN_V 0x1
|
||||
#define RTC_I2C_CLK_EN_S 31
|
||||
/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */
|
||||
/*description: rtc i2c sw reset*/
|
||||
#define RTC_I2C_RESET (BIT(30))
|
||||
#define RTC_I2C_RESET_M (BIT(30))
|
||||
#define RTC_I2C_RESET_V 0x1
|
||||
#define RTC_I2C_RESET_S 30
|
||||
/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */
|
||||
/*description: */
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29))
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29))
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1
|
||||
#define RTC_I2C_CTRL_CLK_GATE_EN_S 29
|
||||
/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: receive lsb first*/
|
||||
#define RTC_I2C_RX_LSB_FIRST (BIT(5))
|
||||
#define RTC_I2C_RX_LSB_FIRST_M (BIT(5))
|
||||
#define RTC_I2C_RX_LSB_FIRST_V 0x1
|
||||
#define RTC_I2C_RX_LSB_FIRST_S 5
|
||||
/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: transit lsb first*/
|
||||
#define RTC_I2C_TX_LSB_FIRST (BIT(4))
|
||||
#define RTC_I2C_TX_LSB_FIRST_M (BIT(4))
|
||||
#define RTC_I2C_TX_LSB_FIRST_V 0x1
|
||||
#define RTC_I2C_TX_LSB_FIRST_S 4
|
||||
/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: force start*/
|
||||
#define RTC_I2C_TRANS_START (BIT(3))
|
||||
#define RTC_I2C_TRANS_START_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_START_V 0x1
|
||||
#define RTC_I2C_TRANS_START_S 3
|
||||
/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: 1=master 0=slave*/
|
||||
#define RTC_I2C_MS_MODE (BIT(2))
|
||||
#define RTC_I2C_MS_MODE_M (BIT(2))
|
||||
#define RTC_I2C_MS_MODE_V 0x1
|
||||
#define RTC_I2C_MS_MODE_S 2
|
||||
/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: 1=push pull 0=open drain*/
|
||||
#define RTC_I2C_SCL_FORCE_OUT (BIT(1))
|
||||
#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1))
|
||||
#define RTC_I2C_SCL_FORCE_OUT_V 0x1
|
||||
#define RTC_I2C_SCL_FORCE_OUT_S 1
|
||||
/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: 1=push pull 0=open drain*/
|
||||
#define RTC_I2C_SDA_FORCE_OUT (BIT(0))
|
||||
#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0))
|
||||
#define RTC_I2C_SDA_FORCE_OUT_V 0x1
|
||||
#define RTC_I2C_SDA_FORCE_OUT_S 0
|
||||
|
||||
#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008)
|
||||
/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */
|
||||
/*description: scl last status*/
|
||||
#define RTC_I2C_SCL_STATE_LAST 0x00000007
|
||||
#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V) << (RTC_I2C_SCL_STATE_LAST_S))
|
||||
#define RTC_I2C_SCL_STATE_LAST_V 0x7
|
||||
#define RTC_I2C_SCL_STATE_LAST_S 28
|
||||
/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */
|
||||
/*description: i2c last main status*/
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V) << (RTC_I2C_SCL_MAIN_STATE_LAST_S))
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7
|
||||
#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24
|
||||
/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */
|
||||
/*description: shifter content*/
|
||||
#define RTC_I2C_SHIFT 0x000000FF
|
||||
#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V) << (RTC_I2C_SHIFT_S))
|
||||
#define RTC_I2C_SHIFT_V 0xFF
|
||||
#define RTC_I2C_SHIFT_S 16
|
||||
/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */
|
||||
/*description: which operation is working*/
|
||||
#define RTC_I2C_OP_CNT 0x00000003
|
||||
#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V) << (RTC_I2C_OP_CNT_S))
|
||||
#define RTC_I2C_OP_CNT_V 0x3
|
||||
#define RTC_I2C_OP_CNT_S 6
|
||||
/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: One byte transit done*/
|
||||
#define RTC_I2C_BYTE_TRANS (BIT(5))
|
||||
#define RTC_I2C_BYTE_TRANS_M (BIT(5))
|
||||
#define RTC_I2C_BYTE_TRANS_V 0x1
|
||||
#define RTC_I2C_BYTE_TRANS_S 5
|
||||
/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: slave reg sub address*/
|
||||
#define RTC_I2C_SLAVE_ADDRESSED (BIT(4))
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4))
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_V 0x1
|
||||
#define RTC_I2C_SLAVE_ADDRESSED_S 4
|
||||
/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: bus is busy*/
|
||||
#define RTC_I2C_BUS_BUSY (BIT(3))
|
||||
#define RTC_I2C_BUS_BUSY_M (BIT(3))
|
||||
#define RTC_I2C_BUS_BUSY_V 0x1
|
||||
#define RTC_I2C_BUS_BUSY_S 3
|
||||
/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: arbitration is lost*/
|
||||
#define RTC_I2C_ARB_LOST (BIT(2))
|
||||
#define RTC_I2C_ARB_LOST_M (BIT(2))
|
||||
#define RTC_I2C_ARB_LOST_V 0x1
|
||||
#define RTC_I2C_ARB_LOST_S 2
|
||||
/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: slave read or write*/
|
||||
#define RTC_I2C_SLAVE_RW (BIT(1))
|
||||
#define RTC_I2C_SLAVE_RW_M (BIT(1))
|
||||
#define RTC_I2C_SLAVE_RW_V 0x1
|
||||
#define RTC_I2C_SLAVE_RW_S 1
|
||||
/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: ack response*/
|
||||
#define RTC_I2C_ACK_REC (BIT(0))
|
||||
#define RTC_I2C_ACK_REC_M (BIT(0))
|
||||
#define RTC_I2C_ACK_REC_V 0x1
|
||||
#define RTC_I2C_ACK_REC_S 0
|
||||
|
||||
#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c)
|
||||
/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */
|
||||
/*description: time out threshold*/
|
||||
#define RTC_I2C_TIMEOUT 0x000FFFFF
|
||||
#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V) << (RTC_I2C_TIMEOUT_S))
|
||||
#define RTC_I2C_TIMEOUT_V 0xFFFFF
|
||||
#define RTC_I2C_TIMEOUT_S 0
|
||||
|
||||
#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010)
|
||||
/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: i2c 10bit mode enable*/
|
||||
#define RTC_I2C_ADDR_10BIT_EN (BIT(31))
|
||||
#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31))
|
||||
#define RTC_I2C_ADDR_10BIT_EN_V 0x1
|
||||
#define RTC_I2C_ADDR_10BIT_EN_S 31
|
||||
/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */
|
||||
/*description: slave address*/
|
||||
#define RTC_I2C_SLAVE_ADDR 0x00007FFF
|
||||
#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V) << (RTC_I2C_SLAVE_ADDR_S))
|
||||
#define RTC_I2C_SLAVE_ADDR_V 0x7FFF
|
||||
#define RTC_I2C_SLAVE_ADDR_S 0
|
||||
|
||||
#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014)
|
||||
/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */
|
||||
/*description: time period that scl = 1*/
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V) << (RTC_I2C_SCL_HIGH_PERIOD_S))
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_HIGH_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018)
|
||||
/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */
|
||||
/*description: time period for SDA to toggle after SCL goes low*/
|
||||
#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF
|
||||
#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V) << (RTC_I2C_SDA_DUTY_NUM_S))
|
||||
#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF
|
||||
#define RTC_I2C_SDA_DUTY_NUM_S 0
|
||||
|
||||
#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c)
|
||||
/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
|
||||
/*description: time period for SCL to toggle after I2C start is triggered*/
|
||||
#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V) << (RTC_I2C_SCL_START_PERIOD_S))
|
||||
#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_START_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020)
|
||||
/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */
|
||||
/*description: time period for SCL to stop after I2C end is triggered*/
|
||||
#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V) << (RTC_I2C_SCL_STOP_PERIOD_S))
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF
|
||||
#define RTC_I2C_SCL_STOP_PERIOD_S 0
|
||||
|
||||
#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024)
|
||||
/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: clear detect start interrupt*/
|
||||
#define RTC_I2C_DETECT_START_INT_CLR (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_CLR_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: clear transit load data complete interrupt*/
|
||||
#define RTC_I2C_TX_DATA_INT_CLR (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_CLR_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: clear receive data interrupt*/
|
||||
#define RTC_I2C_RX_DATA_INT_CLR (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_CLR_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: clear ack error interrupt*/
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_CLR_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: clear time out interrupt*/
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_CLR_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: clear transit complete interrupt*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: clear master transit complete interrupt*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: clear arbitration lost interrupt*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: clear slave transit complete interrupt*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0
|
||||
|
||||
#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028)
|
||||
/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: detect start interrupt raw*/
|
||||
#define RTC_I2C_DETECT_START_INT_RAW (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_RAW_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: transit data interrupt raw*/
|
||||
#define RTC_I2C_TX_DATA_INT_RAW (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_RAW_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: receive data interrupt raw*/
|
||||
#define RTC_I2C_RX_DATA_INT_RAW (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_RAW_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: ack error interrupt raw*/
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_RAW_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: time out interrupt raw*/
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_RAW_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: transit complete interrupt raw*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: master transit complete interrupt raw*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: arbitration lost interrupt raw*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: slave transit complete interrupt raw*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0
|
||||
|
||||
#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c)
|
||||
/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: detect start interrupt state*/
|
||||
#define RTC_I2C_DETECT_START_INT_ST (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ST_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_ST_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: transit data interrupt state*/
|
||||
#define RTC_I2C_TX_DATA_INT_ST (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ST_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_ST_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: receive data interrupt state*/
|
||||
#define RTC_I2C_RX_DATA_INT_ST (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ST_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_ST_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: ack error interrupt state*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ST (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_ST_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: time out interrupt state*/
|
||||
#define RTC_I2C_TIMEOUT_INT_ST (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_ST_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: transit complete interrupt state*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: master transit complete interrupt state*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: arbitration lost interrupt state*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: slave transit complete interrupt state*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0
|
||||
|
||||
#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030)
|
||||
/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */
|
||||
/*description: enable detect start interrupt*/
|
||||
#define RTC_I2C_DETECT_START_INT_ENA (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8))
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_V 0x1
|
||||
#define RTC_I2C_DETECT_START_INT_ENA_S 8
|
||||
/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */
|
||||
/*description: enable transit data interrupt*/
|
||||
#define RTC_I2C_TX_DATA_INT_ENA (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7))
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TX_DATA_INT_ENA_S 7
|
||||
/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */
|
||||
/*description: enable receive data interrupt*/
|
||||
#define RTC_I2C_RX_DATA_INT_ENA (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6))
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_V 0x1
|
||||
#define RTC_I2C_RX_DATA_INT_ENA_S 6
|
||||
/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */
|
||||
/*description: enable eack error interrupt*/
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5))
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1
|
||||
#define RTC_I2C_ACK_ERR_INT_ENA_S 5
|
||||
/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */
|
||||
/*description: enable time out interrupt*/
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4))
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TIMEOUT_INT_ENA_S 4
|
||||
/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */
|
||||
/*description: enable transit complete interrupt*/
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3))
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1
|
||||
#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3
|
||||
/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */
|
||||
/*description: enable master transit complete interrupt*/
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2))
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1
|
||||
#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2
|
||||
/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */
|
||||
/*description: enable arbitration lost interrupt*/
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1))
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1
|
||||
#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1
|
||||
/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */
|
||||
/*description: enable slave transit complete interrupt*/
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0))
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1
|
||||
#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0
|
||||
|
||||
#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034)
|
||||
/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: i2c done*/
|
||||
#define RTC_I2C_DONE (BIT(31))
|
||||
#define RTC_I2C_DONE_M (BIT(31))
|
||||
#define RTC_I2C_DONE_V 0x1
|
||||
#define RTC_I2C_DONE_S 31
|
||||
/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */
|
||||
/*description: data sent by slave*/
|
||||
#define RTC_I2C_SLAVE_TX_DATA 0x000000FF
|
||||
#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V) << (RTC_I2C_SLAVE_TX_DATA_S))
|
||||
#define RTC_I2C_SLAVE_TX_DATA_V 0xFF
|
||||
#define RTC_I2C_SLAVE_TX_DATA_S 8
|
||||
/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */
|
||||
/*description: data received*/
|
||||
#define RTC_I2C_RDATA 0x000000FF
|
||||
#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V) << (RTC_I2C_RDATA_S))
|
||||
#define RTC_I2C_RDATA_V 0xFF
|
||||
#define RTC_I2C_RDATA_S 0
|
||||
|
||||
#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038)
|
||||
/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command0_done*/
|
||||
#define RTC_I2C_COMMAND0_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND0_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND0_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND0_DONE_S 31
|
||||
/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
|
||||
/*description: command0*/
|
||||
#define RTC_I2C_COMMAND0 0x00003FFF
|
||||
#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V) << (RTC_I2C_COMMAND0_S))
|
||||
#define RTC_I2C_COMMAND0_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND0_S 0
|
||||
|
||||
#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c)
|
||||
/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command1_done*/
|
||||
#define RTC_I2C_COMMAND1_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND1_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND1_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND1_DONE_S 31
|
||||
/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command1*/
|
||||
#define RTC_I2C_COMMAND1 0x00003FFF
|
||||
#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V) << (RTC_I2C_COMMAND1_S))
|
||||
#define RTC_I2C_COMMAND1_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND1_S 0
|
||||
|
||||
#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040)
|
||||
/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command2_done*/
|
||||
#define RTC_I2C_COMMAND2_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND2_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND2_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND2_DONE_S 31
|
||||
/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */
|
||||
/*description: command2*/
|
||||
#define RTC_I2C_COMMAND2 0x00003FFF
|
||||
#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V) << (RTC_I2C_COMMAND2_S))
|
||||
#define RTC_I2C_COMMAND2_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND2_S 0
|
||||
|
||||
#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044)
|
||||
/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command3_done*/
|
||||
#define RTC_I2C_COMMAND3_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND3_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND3_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND3_DONE_S 31
|
||||
/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
|
||||
/*description: command3*/
|
||||
#define RTC_I2C_COMMAND3 0x00003FFF
|
||||
#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V) << (RTC_I2C_COMMAND3_S))
|
||||
#define RTC_I2C_COMMAND3_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND3_S 0
|
||||
|
||||
#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048)
|
||||
/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command4_done*/
|
||||
#define RTC_I2C_COMMAND4_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND4_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND4_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND4_DONE_S 31
|
||||
/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
|
||||
/*description: command4*/
|
||||
#define RTC_I2C_COMMAND4 0x00003FFF
|
||||
#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V) << (RTC_I2C_COMMAND4_S))
|
||||
#define RTC_I2C_COMMAND4_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND4_S 0
|
||||
|
||||
#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c)
|
||||
/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command5_done*/
|
||||
#define RTC_I2C_COMMAND5_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND5_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND5_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND5_DONE_S 31
|
||||
/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
|
||||
/*description: command5*/
|
||||
#define RTC_I2C_COMMAND5 0x00003FFF
|
||||
#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V) << (RTC_I2C_COMMAND5_S))
|
||||
#define RTC_I2C_COMMAND5_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND5_S 0
|
||||
|
||||
#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050)
|
||||
/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command6_done*/
|
||||
#define RTC_I2C_COMMAND6_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND6_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND6_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND6_DONE_S 31
|
||||
/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command6*/
|
||||
#define RTC_I2C_COMMAND6 0x00003FFF
|
||||
#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V) << (RTC_I2C_COMMAND6_S))
|
||||
#define RTC_I2C_COMMAND6_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND6_S 0
|
||||
|
||||
#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054)
|
||||
/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command7_done*/
|
||||
#define RTC_I2C_COMMAND7_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND7_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND7_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND7_DONE_S 31
|
||||
/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */
|
||||
/*description: command7*/
|
||||
#define RTC_I2C_COMMAND7 0x00003FFF
|
||||
#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V) << (RTC_I2C_COMMAND7_S))
|
||||
#define RTC_I2C_COMMAND7_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND7_S 0
|
||||
|
||||
#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058)
|
||||
/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command8_done*/
|
||||
#define RTC_I2C_COMMAND8_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND8_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND8_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND8_DONE_S 31
|
||||
/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command8*/
|
||||
#define RTC_I2C_COMMAND8 0x00003FFF
|
||||
#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V) << (RTC_I2C_COMMAND8_S))
|
||||
#define RTC_I2C_COMMAND8_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND8_S 0
|
||||
|
||||
#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c)
|
||||
/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command9_done*/
|
||||
#define RTC_I2C_COMMAND9_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND9_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND9_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND9_DONE_S 31
|
||||
/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */
|
||||
/*description: command9*/
|
||||
#define RTC_I2C_COMMAND9 0x00003FFF
|
||||
#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V) << (RTC_I2C_COMMAND9_S))
|
||||
#define RTC_I2C_COMMAND9_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND9_S 0
|
||||
|
||||
#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060)
|
||||
/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command10_done*/
|
||||
#define RTC_I2C_COMMAND10_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND10_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND10_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND10_DONE_S 31
|
||||
/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */
|
||||
/*description: command10*/
|
||||
#define RTC_I2C_COMMAND10 0x00003FFF
|
||||
#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V) << (RTC_I2C_COMMAND10_S))
|
||||
#define RTC_I2C_COMMAND10_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND10_S 0
|
||||
|
||||
#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064)
|
||||
/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command11_done*/
|
||||
#define RTC_I2C_COMMAND11_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND11_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND11_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND11_DONE_S 31
|
||||
/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */
|
||||
/*description: command11*/
|
||||
#define RTC_I2C_COMMAND11 0x00003FFF
|
||||
#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V) << (RTC_I2C_COMMAND11_S))
|
||||
#define RTC_I2C_COMMAND11_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND11_S 0
|
||||
|
||||
#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068)
|
||||
/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command12_done*/
|
||||
#define RTC_I2C_COMMAND12_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND12_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND12_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND12_DONE_S 31
|
||||
/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */
|
||||
/*description: command12*/
|
||||
#define RTC_I2C_COMMAND12 0x00003FFF
|
||||
#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V) << (RTC_I2C_COMMAND12_S))
|
||||
#define RTC_I2C_COMMAND12_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND12_S 0
|
||||
|
||||
#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c)
|
||||
/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command13_done*/
|
||||
#define RTC_I2C_COMMAND13_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND13_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND13_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND13_DONE_S 31
|
||||
/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */
|
||||
/*description: command13*/
|
||||
#define RTC_I2C_COMMAND13 0x00003FFF
|
||||
#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V) << (RTC_I2C_COMMAND13_S))
|
||||
#define RTC_I2C_COMMAND13_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND13_S 0
|
||||
|
||||
#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070)
|
||||
/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command14_done*/
|
||||
#define RTC_I2C_COMMAND14_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND14_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND14_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND14_DONE_S 31
|
||||
/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
|
||||
/*description: command14*/
|
||||
#define RTC_I2C_COMMAND14 0x00003FFF
|
||||
#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V) << (RTC_I2C_COMMAND14_S))
|
||||
#define RTC_I2C_COMMAND14_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND14_S 0
|
||||
|
||||
#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074)
|
||||
/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */
|
||||
/*description: command15_done*/
|
||||
#define RTC_I2C_COMMAND15_DONE (BIT(31))
|
||||
#define RTC_I2C_COMMAND15_DONE_M (BIT(31))
|
||||
#define RTC_I2C_COMMAND15_DONE_V 0x1
|
||||
#define RTC_I2C_COMMAND15_DONE_S 31
|
||||
/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */
|
||||
/*description: command15*/
|
||||
#define RTC_I2C_COMMAND15 0x00003FFF
|
||||
#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V) << (RTC_I2C_COMMAND15_S))
|
||||
#define RTC_I2C_COMMAND15_V 0x3FFF
|
||||
#define RTC_I2C_COMMAND15_S 0
|
||||
|
||||
#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC)
|
||||
/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */
|
||||
/*description: */
|
||||
#define RTC_I2C_DATE 0x0FFFFFFF
|
||||
#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V) << (RTC_I2C_DATE_S))
|
||||
#define RTC_I2C_DATE_V 0xFFFFFFF
|
||||
#define RTC_I2C_DATE_S 0
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
229
components/soc/soc/esp32s3/include/soc/rtc_i2c_struct.h
Normal file
229
components/soc/soc/esp32s3/include/soc/rtc_i2c_struct.h
Normal file
|
|
@ -0,0 +1,229 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 20; /*time period that scl = 0*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_low;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/
|
||||
uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/
|
||||
uint32_t ms_mode: 1; /*1=master 0=slave*/
|
||||
uint32_t trans_start: 1; /*force start*/
|
||||
uint32_t tx_lsb_first: 1; /*transit lsb first*/
|
||||
uint32_t rx_lsb_first: 1; /*receive lsb first*/
|
||||
uint32_t reserved6: 23;
|
||||
uint32_t i2c_ctrl_clk_gate_en: 1;
|
||||
uint32_t i2c_reset: 1; /*rtc i2c sw reset*/
|
||||
uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t ack_rec: 1; /*ack response*/
|
||||
uint32_t slave_rw: 1; /*slave read or write*/
|
||||
uint32_t arb_lost: 1; /*arbitration is lost*/
|
||||
uint32_t bus_busy: 1; /*bus is busy*/
|
||||
uint32_t slave_addressed: 1; /*slave reg sub address*/
|
||||
uint32_t byte_trans: 1; /*One byte transit done*/
|
||||
uint32_t op_cnt: 2; /*which operation is working*/
|
||||
uint32_t reserved8: 8;
|
||||
uint32_t shift: 8; /*shifter content*/
|
||||
uint32_t scl_main_state_last: 3; /*i2c last main status*/
|
||||
uint32_t reserved27: 1;
|
||||
uint32_t scl_state_last: 3; /*scl last status*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t time_out: 20; /*time out threshold*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} timeout;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 15; /*slave address*/
|
||||
uint32_t reserved15: 16;
|
||||
uint32_t en_10bit: 1; /*i2c 10bit mode enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} slave_addr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t period: 20; /*time period that scl = 1*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_high;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sda_duty_num: 20; /*time period for SDA to toggle after SCL goes low*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} sda_duty;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_start_period: 20; /*time period for SCL to toggle after I2C start is triggered*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_start_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t scl_stop_period: 20; /*time period for SCL to stop after I2C end is triggered*/
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} scl_stop_period;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/
|
||||
uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/
|
||||
uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/
|
||||
uint32_t trans_complete: 1; /*clear transit complete interrupt*/
|
||||
uint32_t time_out: 1; /*clear time out interrupt*/
|
||||
uint32_t ack_err: 1; /*clear ack error interrupt*/
|
||||
uint32_t rx_data: 1; /*clear receive data interrupt*/
|
||||
uint32_t tx_data: 1; /*clear transit load data complete interrupt*/
|
||||
uint32_t detect_start: 1; /*clear detect start interrupt*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/
|
||||
uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/
|
||||
uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/
|
||||
uint32_t trans_complete: 1; /*transit complete interrupt raw*/
|
||||
uint32_t time_out: 1; /*time out interrupt raw*/
|
||||
uint32_t ack_err: 1; /*ack error interrupt raw*/
|
||||
uint32_t rx_data: 1; /*receive data interrupt raw*/
|
||||
uint32_t tx_data: 1; /*transit data interrupt raw*/
|
||||
uint32_t detect_start: 1; /*detect start interrupt raw*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/
|
||||
uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/
|
||||
uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/
|
||||
uint32_t trans_complete: 1; /*transit complete interrupt state*/
|
||||
uint32_t time_out: 1; /*time out interrupt state*/
|
||||
uint32_t ack_err: 1; /*ack error interrupt state*/
|
||||
uint32_t rx_data: 1; /*receive data interrupt state*/
|
||||
uint32_t tx_data: 1; /*transit data interrupt state*/
|
||||
uint32_t detect_start: 1; /*detect start interrupt state*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/
|
||||
uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/
|
||||
uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/
|
||||
uint32_t trans_complete: 1; /*enable transit complete interrupt*/
|
||||
uint32_t time_out: 1; /*enable time out interrupt*/
|
||||
uint32_t ack_err: 1; /*enable eack error interrupt*/
|
||||
uint32_t rx_data: 1; /*enable receive data interrupt*/
|
||||
uint32_t tx_data: 1; /*enable transit data interrupt*/
|
||||
uint32_t detect_start: 1; /*enable detect start interrupt*/
|
||||
uint32_t reserved9: 23;
|
||||
};
|
||||
uint32_t val;
|
||||
} int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_rdata: 8; /*data received*/
|
||||
uint32_t slave_tx_data: 8; /*data sent by slave*/
|
||||
uint32_t reserved16: 15;
|
||||
uint32_t i2c_done: 1; /*i2c done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} fifo_data;
|
||||
union {
|
||||
struct {
|
||||
uint32_t command0: 14; /*command0*/
|
||||
uint32_t reserved14: 17;
|
||||
uint32_t done: 1; /*command0_done*/
|
||||
};
|
||||
uint32_t val;
|
||||
} command[16];
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
uint32_t reserved_d4;
|
||||
uint32_t reserved_d8;
|
||||
uint32_t reserved_dc;
|
||||
uint32_t reserved_e0;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_i2c_dev_t;
|
||||
|
||||
extern rtc_i2c_dev_t RTC_I2C;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
18
components/soc/soc/esp32s3/include/soc/rtc_io_caps.h
Normal file
18
components/soc/soc/esp32s3/include/soc/rtc_io_caps.h
Normal file
|
|
@ -0,0 +1,18 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define SOC_RTC_IO_PIN_COUNT 22
|
||||
#define SOC_PIN_FUNC_RTC_IO 0
|
||||
84
components/soc/soc/esp32s3/include/soc/rtc_io_channel.h
Normal file
84
components/soc/soc/esp32s3/include/soc/rtc_io_channel.h
Normal file
|
|
@ -0,0 +1,84 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define RTC_GPIO_NUMBER 22
|
||||
|
||||
//RTC GPIO channels
|
||||
#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0
|
||||
#define RTCIO_CHANNEL_0_GPIO_NUM 0
|
||||
|
||||
#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1
|
||||
#define RTCIO_CHANNEL_1_GPIO_NUM 1
|
||||
|
||||
#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2
|
||||
#define RTCIO_CHANNEL_2_GPIO_NUM 2
|
||||
|
||||
#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3
|
||||
#define RTCIO_CHANNEL_3_GPIO_NUM 3
|
||||
|
||||
#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4
|
||||
#define RTCIO_CHANNEL_4_GPIO_NUM 4
|
||||
|
||||
#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5
|
||||
#define RTCIO_CHANNEL_5_GPIO_NUM 5
|
||||
|
||||
#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6
|
||||
#define RTCIO_CHANNEL_6_GPIO_NUM 6
|
||||
|
||||
#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7
|
||||
#define RTCIO_CHANNEL_7_GPIO_NUM 7
|
||||
|
||||
#define RTCIO_GPIO8_CHANNEL 8 //RTCIO_CHANNEL_8
|
||||
#define RTCIO_CHANNEL_8_GPIO_NUM 8
|
||||
|
||||
#define RTCIO_GPIO9_CHANNEL 9 //RTCIO_CHANNEL_9
|
||||
#define RTCIO_CHANNEL_9_GPIO_NUM 9
|
||||
|
||||
#define RTCIO_GPIO10_CHANNEL 10 //RTCIO_CHANNEL_10
|
||||
#define RTCIO_CHANNEL_10_GPIO_NUM 10
|
||||
|
||||
#define RTCIO_GPIO11_CHANNEL 11 //RTCIO_CHANNEL_11
|
||||
#define RTCIO_CHANNEL_11_GPIO_NUM 11
|
||||
|
||||
#define RTCIO_GPIO12_CHANNEL 12 //RTCIO_CHANNEL_12
|
||||
#define RTCIO_CHANNEL_12_GPIO_NUM 12
|
||||
|
||||
#define RTCIO_GPIO13_CHANNEL 13 //RTCIO_CHANNEL_13
|
||||
#define RTCIO_CHANNEL_13_GPIO_NUM 13
|
||||
|
||||
#define RTCIO_GPIO14_CHANNEL 14 //RTCIO_CHANNEL_14
|
||||
#define RTCIO_CHANNEL_14_GPIO_NUM 14
|
||||
|
||||
#define RTCIO_GPIO15_CHANNEL 15 //RTCIO_CHANNEL_15
|
||||
#define RTCIO_CHANNEL_15_GPIO_NUM 15
|
||||
|
||||
#define RTCIO_GPIO16_CHANNEL 16 //RTCIO_CHANNEL_16
|
||||
#define RTCIO_CHANNEL_16_GPIO_NUM 16
|
||||
|
||||
#define RTCIO_GPIO17_CHANNEL 17 //RTCIO_CHANNEL_17
|
||||
#define RTCIO_CHANNEL_17_GPIO_NUM 17
|
||||
|
||||
#define RTCIO_GPIO18_CHANNEL 18 //RTCIO_CHANNEL_18
|
||||
#define RTCIO_CHANNEL_18_GPIO_NUM 18
|
||||
|
||||
#define RTCIO_GPIO19_CHANNEL 19 //RTCIO_CHANNEL_19
|
||||
#define RTCIO_CHANNEL_19_GPIO_NUM 19
|
||||
|
||||
#define RTCIO_GPIO20_CHANNEL 20 //RTCIO_CHANNEL_20
|
||||
#define RTCIO_CHANNEL_20_GPIO_NUM 20
|
||||
|
||||
#define RTCIO_GPIO21_CHANNEL 21 //RTCIO_CHANNEL_21
|
||||
#define RTCIO_CHANNEL_21_GPIO_NUM 21
|
||||
2292
components/soc/soc/esp32s3/include/soc/rtc_io_reg.h
Normal file
2292
components/soc/soc/esp32s3/include/soc/rtc_io_reg.h
Normal file
File diff suppressed because it is too large
Load diff
354
components/soc/soc/esp32s3/include/soc/rtc_io_struct.h
Normal file
354
components/soc/soc/esp32s3/include/soc/rtc_io_struct.h
Normal file
|
|
@ -0,0 +1,354 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t data: 22; /*RTC GPIO 0 ~ 21 output data*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/
|
||||
};
|
||||
uint32_t val;
|
||||
} out_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t enable: 22; /*RTC GPIO 0 ~ 21 enable*/
|
||||
};
|
||||
uint32_t val;
|
||||
} enable;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/
|
||||
};
|
||||
uint32_t val;
|
||||
} enable_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/
|
||||
};
|
||||
uint32_t val;
|
||||
} enable_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t status: 22; /*RTC GPIO 0 ~ 21 interrupt status*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/
|
||||
};
|
||||
uint32_t val;
|
||||
} status_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 10;
|
||||
uint32_t in: 22; /*RTC GPIO input data*/
|
||||
};
|
||||
uint32_t val;
|
||||
} in_val;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 2;
|
||||
uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/
|
||||
uint32_t reserved3: 4;
|
||||
uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/
|
||||
uint32_t wakeup_enable: 1; /*RTC GPIO wakeup enable bit*/
|
||||
uint32_t reserved11: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} pin[22];
|
||||
union {
|
||||
struct {
|
||||
uint32_t sel0: 5;
|
||||
uint32_t sel1: 5;
|
||||
uint32_t sel2: 5;
|
||||
uint32_t sel3: 5;
|
||||
uint32_t sel4: 5;
|
||||
uint32_t no_gating_12m: 1;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} debug_sel;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 13;
|
||||
uint32_t fun_ie: 1; /*input enable in work mode*/
|
||||
uint32_t slp_oe: 1; /*output enable in sleep mode*/
|
||||
uint32_t slp_ie: 1; /*input enable in sleep mode*/
|
||||
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
|
||||
uint32_t fun_sel: 2; /*function sel*/
|
||||
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
|
||||
uint32_t xpd: 1; /*TOUCH_XPD*/
|
||||
uint32_t tie_opt: 1; /*TOUCH_TIE_OPT*/
|
||||
uint32_t start: 1; /*TOUCH_START*/
|
||||
uint32_t dac: 3; /*TOUCH_DAC*/
|
||||
uint32_t reserved26: 1;
|
||||
uint32_t rue: 1; /*RUE*/
|
||||
uint32_t rde: 1; /*RDE*/
|
||||
uint32_t drv: 2; /*DRV*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_pad[15];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 13;
|
||||
uint32_t x32p_fun_ie: 1; /*input enable in work mode*/
|
||||
uint32_t x32p_slp_oe: 1; /*output enable in sleep mode*/
|
||||
uint32_t x32p_slp_ie: 1; /*input enable in sleep mode*/
|
||||
uint32_t x32p_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
|
||||
uint32_t x32p_fun_sel: 2; /*function sel*/
|
||||
uint32_t x32p_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
|
||||
uint32_t reserved20: 7;
|
||||
uint32_t x32p_rue: 1; /*RUE*/
|
||||
uint32_t x32p_rde: 1; /*RDE*/
|
||||
uint32_t x32p_drv: 2; /*DRV*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal_32p_pad;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 13;
|
||||
uint32_t x32n_fun_ie: 1; /*input enable in work mode*/
|
||||
uint32_t x32n_slp_oe: 1; /*output enable in sleep mode*/
|
||||
uint32_t x32n_slp_ie: 1; /*input enable in sleep mode*/
|
||||
uint32_t x32n_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
|
||||
uint32_t x32n_fun_sel: 2; /*function sel*/
|
||||
uint32_t x32n_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
|
||||
uint32_t reserved20: 7;
|
||||
uint32_t x32n_rue: 1; /*RUE*/
|
||||
uint32_t x32n_rde: 1; /*RDE*/
|
||||
uint32_t x32n_drv: 2; /*DRV*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} xtal_32n_pad;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 3;
|
||||
uint32_t dac: 8; /*PDAC1_DAC*/
|
||||
uint32_t xpd_dac: 1; /*PDAC1_XPD_DAC*/
|
||||
uint32_t dac_xpd_force: 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR ADC FSM to control PDAC1_XPD_DAC*/
|
||||
uint32_t fun_ie: 1; /*input enable in work mode*/
|
||||
uint32_t slp_oe: 1; /*output enable in sleep mode*/
|
||||
uint32_t slp_ie: 1; /*input enable in sleep mode*/
|
||||
uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
|
||||
uint32_t fun_sel: 2; /*PDAC1 function sel*/
|
||||
uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
|
||||
uint32_t reserved20: 7;
|
||||
uint32_t rue: 1; /*PDAC1_RUE*/
|
||||
uint32_t rde: 1; /*PDAC1_RDE*/
|
||||
uint32_t drv: 2; /*PDAC1_DRV*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} pad_dac[2];
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 13;
|
||||
uint32_t rtc_pad19_fun_ie: 1; /*input enable in work mode*/
|
||||
uint32_t rtc_pad19_slp_oe: 1; /*output enable in sleep mode*/
|
||||
uint32_t rtc_pad19_slp_ie: 1; /*input enable in sleep mode*/
|
||||
uint32_t rtc_pad19_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
|
||||
uint32_t rtc_pad19_fun_sel: 2; /*function sel*/
|
||||
uint32_t rtc_pad19_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
|
||||
uint32_t reserved20: 7;
|
||||
uint32_t rtc_pad19_rue: 1; /*RUE*/
|
||||
uint32_t rtc_pad19_rde: 1; /*RDE*/
|
||||
uint32_t rtc_pad19_drv: 2; /*DRV*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pad19;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 13;
|
||||
uint32_t rtc_pad20_fun_ie: 1; /*input enable in work mode*/
|
||||
uint32_t rtc_pad20_slp_oe: 1; /*output enable in sleep mode*/
|
||||
uint32_t rtc_pad20_slp_ie: 1; /*input enable in sleep mode*/
|
||||
uint32_t rtc_pad20_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
|
||||
uint32_t rtc_pad20_fun_sel: 2; /*function sel*/
|
||||
uint32_t rtc_pad20_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
|
||||
uint32_t reserved20: 7;
|
||||
uint32_t rtc_pad20_rue: 1; /*RUE*/
|
||||
uint32_t rtc_pad20_rde: 1; /*RDE*/
|
||||
uint32_t rtc_pad20_drv: 2; /*DRV*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pad20;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 13;
|
||||
uint32_t rtc_pad21_fun_ie: 1; /*input enable in work mode*/
|
||||
uint32_t rtc_pad21_slp_oe: 1; /*output enable in sleep mode*/
|
||||
uint32_t rtc_pad21_slp_ie: 1; /*input enable in sleep mode*/
|
||||
uint32_t rtc_pad21_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/
|
||||
uint32_t rtc_pad21_fun_sel: 2; /*function sel*/
|
||||
uint32_t rtc_pad21_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/
|
||||
uint32_t reserved20: 7;
|
||||
uint32_t rtc_pad21_rue: 1; /*RUE*/
|
||||
uint32_t rtc_pad21_rde: 1; /*RDE*/
|
||||
uint32_t rtc_pad21_drv: 2; /*DRV*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} rtc_pad21;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t sel: 5;
|
||||
};
|
||||
uint32_t val;
|
||||
} ext_wakeup0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 27;
|
||||
uint32_t sel: 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/
|
||||
};
|
||||
uint32_t val;
|
||||
} xtl_ext_ctr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 23;
|
||||
uint32_t debug_bit_sel: 5;
|
||||
uint32_t scl_sel: 2;
|
||||
uint32_t sda_sel: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_i2c_io;
|
||||
union {
|
||||
struct {
|
||||
uint32_t io_touch_bufsel: 4; /*BUF_SEL when touch work without fsm*/
|
||||
uint32_t io_touch_bufmode: 1; /*BUF_MODE when touch work without fsm*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_ctrl;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} rtc_io_dev_t;
|
||||
|
||||
extern rtc_io_dev_t RTCIO;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
94
components/soc/soc/esp32s3/include/soc/sdmmc_reg.h
Normal file
94
components/soc/soc/esp32s3/include/soc/sdmmc_reg.h
Normal file
|
|
@ -0,0 +1,94 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include "soc.h"
|
||||
|
||||
#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00)
|
||||
#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04)
|
||||
#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08)
|
||||
#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c)
|
||||
#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10)
|
||||
#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14)
|
||||
#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18)
|
||||
#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c)
|
||||
#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20)
|
||||
#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24)
|
||||
#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28)
|
||||
#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c)
|
||||
#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30)
|
||||
#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34)
|
||||
#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38)
|
||||
#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c)
|
||||
|
||||
#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40)
|
||||
#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44)
|
||||
#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48)
|
||||
#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c)
|
||||
#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50)
|
||||
#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54)
|
||||
#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58)
|
||||
#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c)
|
||||
#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60)
|
||||
#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64)
|
||||
#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68)
|
||||
#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c)
|
||||
#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70)
|
||||
#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74)
|
||||
#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78)
|
||||
#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80)
|
||||
#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84)
|
||||
#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88)
|
||||
#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c)
|
||||
#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c)
|
||||
#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90)
|
||||
#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94)
|
||||
#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98)
|
||||
#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c)
|
||||
#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0)
|
||||
#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4)
|
||||
#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100)
|
||||
#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104)
|
||||
#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108)
|
||||
#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c)
|
||||
#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110)
|
||||
|
||||
#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800)
|
||||
|
||||
#define SDMMC_INTMASK_IO_SLOT1 BIT(17)
|
||||
#define SDMMC_INTMASK_IO_SLOT0 BIT(16)
|
||||
#define SDMMC_INTMASK_EBE BIT(15)
|
||||
#define SDMMC_INTMASK_ACD BIT(14)
|
||||
#define SDMMC_INTMASK_SBE BIT(13)
|
||||
#define SDMMC_INTMASK_HLE BIT(12)
|
||||
#define SDMMC_INTMASK_FRUN BIT(11)
|
||||
#define SDMMC_INTMASK_HTO BIT(10)
|
||||
#define SDMMC_INTMASK_DTO BIT(9)
|
||||
#define SDMMC_INTMASK_RTO BIT(8)
|
||||
#define SDMMC_INTMASK_DCRC BIT(7)
|
||||
#define SDMMC_INTMASK_RCRC BIT(6)
|
||||
#define SDMMC_INTMASK_RXDR BIT(5)
|
||||
#define SDMMC_INTMASK_TXDR BIT(4)
|
||||
#define SDMMC_INTMASK_DATA_OVER BIT(3)
|
||||
#define SDMMC_INTMASK_CMD_DONE BIT(2)
|
||||
#define SDMMC_INTMASK_RESP_ERR BIT(1)
|
||||
#define SDMMC_INTMASK_CD BIT(0)
|
||||
|
||||
#define SDMMC_IDMAC_INTMASK_AI BIT(9)
|
||||
#define SDMMC_IDMAC_INTMASK_NI BIT(8)
|
||||
#define SDMMC_IDMAC_INTMASK_CES BIT(5)
|
||||
#define SDMMC_IDMAC_INTMASK_DU BIT(4)
|
||||
#define SDMMC_IDMAC_INTMASK_FBE BIT(2)
|
||||
#define SDMMC_IDMAC_INTMASK_RI BIT(1)
|
||||
#define SDMMC_IDMAC_INTMASK_TI BIT(0)
|
||||
374
components/soc/soc/esp32s3/include/soc/sdmmc_struct.h
Normal file
374
components/soc/soc/esp32s3/include/soc/sdmmc_struct.h
Normal file
|
|
@ -0,0 +1,374 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
typedef struct {
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t disable_int_on_completion: 1;
|
||||
uint32_t last_descriptor: 1;
|
||||
uint32_t first_descriptor: 1;
|
||||
uint32_t second_address_chained: 1;
|
||||
uint32_t end_of_ring: 1;
|
||||
uint32_t reserved2: 24;
|
||||
uint32_t card_error_summary: 1;
|
||||
uint32_t owned_by_idmac: 1;
|
||||
uint32_t buffer1_size: 13;
|
||||
uint32_t buffer2_size: 13;
|
||||
uint32_t reserved3: 6;
|
||||
void *buffer1_ptr;
|
||||
union {
|
||||
void *buffer2_ptr;
|
||||
void *next_desc_ptr;
|
||||
};
|
||||
} sdmmc_desc_t;
|
||||
|
||||
#define SDMMC_DMA_MAX_BUF_LEN 4096
|
||||
|
||||
_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure");
|
||||
|
||||
|
||||
typedef struct {
|
||||
uint32_t cmd_index: 6; ///< Command index
|
||||
uint32_t response_expect: 1; ///< set if response is expected
|
||||
uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected
|
||||
uint32_t check_response_crc: 1; ///< set if controller should check response CRC
|
||||
uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected
|
||||
uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected)
|
||||
uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected)
|
||||
uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer
|
||||
uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete
|
||||
uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer
|
||||
uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1)
|
||||
uint32_t card_num: 5; ///< card number
|
||||
uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers
|
||||
uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device
|
||||
uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device
|
||||
uint32_t enable_boot: 1; ///< set for mandatory boot mode
|
||||
uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern
|
||||
uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot)
|
||||
uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation
|
||||
uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only)
|
||||
uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register
|
||||
uint32_t reserved: 1;
|
||||
uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared.
|
||||
} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values
|
||||
|
||||
_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure");
|
||||
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t controller_reset: 1;
|
||||
uint32_t fifo_reset: 1;
|
||||
uint32_t dma_reset: 1;
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t int_enable: 1;
|
||||
uint32_t dma_enable: 1;
|
||||
uint32_t read_wait: 1;
|
||||
uint32_t send_irq_response: 1;
|
||||
uint32_t abort_read_data: 1;
|
||||
uint32_t send_ccsd: 1;
|
||||
uint32_t send_auto_stop_ccsd: 1;
|
||||
uint32_t ceata_device_interrupt_status: 1;
|
||||
uint32_t reserved2: 4;
|
||||
uint32_t card_voltage_a: 4;
|
||||
uint32_t card_voltage_b: 4;
|
||||
uint32_t enable_od_pullup: 1;
|
||||
uint32_t use_internal_dma: 1;
|
||||
uint32_t reserved3: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
|
||||
uint32_t pwren; ///< 1: enable power to card, 0: disable power to card
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0).
|
||||
};
|
||||
uint32_t val;
|
||||
} clkdiv;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3
|
||||
uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3
|
||||
uint32_t reserved: 28;
|
||||
};
|
||||
uint32_t val;
|
||||
} clksrc;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock
|
||||
uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating
|
||||
};
|
||||
uint32_t val;
|
||||
} clkena;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t response: 8; ///< response timeout, in card output clock cycles
|
||||
uint32_t data: 24; ///< data read timeout, in card output clock cycles
|
||||
};
|
||||
uint32_t val;
|
||||
} tmout;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode
|
||||
uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored)
|
||||
};
|
||||
uint32_t val;
|
||||
} ctype;
|
||||
|
||||
uint32_t blksiz: 16; ///< block size, default 0x200
|
||||
uint32_t : 16;
|
||||
|
||||
uint32_t bytcnt; ///< number of bytes to be transferred
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cd: 1; ///< Card detect interrupt enable
|
||||
uint32_t re: 1; ///< Response error interrupt enable
|
||||
uint32_t cmd_done: 1; ///< Command done interrupt enable
|
||||
uint32_t dto: 1; ///< Data transfer over interrupt enable
|
||||
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable
|
||||
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable
|
||||
uint32_t rcrc: 1; ///< Response CRC error interrupt enable
|
||||
uint32_t dcrc: 1; ///< Data CRC error interrupt enable
|
||||
uint32_t rto: 1; ///< Response timeout interrupt enable
|
||||
uint32_t drto: 1; ///< Data read timeout interrupt enable
|
||||
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable
|
||||
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable
|
||||
uint32_t hle: 1; ///< Hardware locked write error interrupt enable
|
||||
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable
|
||||
uint32_t acd: 1; ///< Auto command done interrupt enable
|
||||
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable
|
||||
uint32_t sdio: 16; ///< SDIO interrupt enable
|
||||
};
|
||||
uint32_t val;
|
||||
} intmask;
|
||||
|
||||
uint32_t cmdarg; ///< Command argument to be passed to card
|
||||
|
||||
sdmmc_hw_cmd_t cmd;
|
||||
|
||||
uint32_t resp[4]; ///< Response from card
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cd: 1; ///< Card detect interrupt masked status
|
||||
uint32_t re: 1; ///< Response error interrupt masked status
|
||||
uint32_t cmd_done: 1; ///< Command done interrupt masked status
|
||||
uint32_t dto: 1; ///< Data transfer over interrupt masked status
|
||||
uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status
|
||||
uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status
|
||||
uint32_t rcrc: 1; ///< Response CRC error interrupt masked status
|
||||
uint32_t dcrc: 1; ///< Data CRC error interrupt masked status
|
||||
uint32_t rto: 1; ///< Response timeout interrupt masked status
|
||||
uint32_t drto: 1; ///< Data read timeout interrupt masked status
|
||||
uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status
|
||||
uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status
|
||||
uint32_t hle: 1; ///< Hardware locked write error interrupt masked status
|
||||
uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status
|
||||
uint32_t acd: 1; ///< Auto command done interrupt masked status
|
||||
uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status
|
||||
uint32_t sdio: 16; ///< SDIO interrupt masked status
|
||||
};
|
||||
uint32_t val;
|
||||
} mintsts;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cd: 1; ///< Card detect raw interrupt status
|
||||
uint32_t re: 1; ///< Response error raw interrupt status
|
||||
uint32_t cmd_done: 1; ///< Command done raw interrupt status
|
||||
uint32_t dto: 1; ///< Data transfer over raw interrupt status
|
||||
uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status
|
||||
uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status
|
||||
uint32_t rcrc: 1; ///< Response CRC error raw interrupt status
|
||||
uint32_t dcrc: 1; ///< Data CRC error raw interrupt status
|
||||
uint32_t rto: 1; ///< Response timeout raw interrupt status
|
||||
uint32_t drto: 1; ///< Data read timeout raw interrupt status
|
||||
uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status
|
||||
uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status
|
||||
uint32_t hle: 1; ///< Hardware locked write error raw interrupt status
|
||||
uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status
|
||||
uint32_t acd: 1; ///< Auto command done raw interrupt status
|
||||
uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status
|
||||
uint32_t sdio: 16; ///< SDIO raw interrupt status
|
||||
};
|
||||
uint32_t val;
|
||||
} rintsts; ///< interrupts can be cleared by writing this register
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level
|
||||
uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level
|
||||
uint32_t fifo_empty: 1; ///< FIFO is empty
|
||||
uint32_t fifo_full: 1; ///< FIFO is full
|
||||
uint32_t cmd_fsm_state: 4; ///< command FSM state
|
||||
uint32_t data3_status: 1; ///< this bit reads 1 if card is present
|
||||
uint32_t data_busy: 1; ///< this bit reads 1 if card is busy
|
||||
uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy
|
||||
uint32_t response_index: 6; ///< index of the previous response
|
||||
uint32_t fifo_count: 13; ///< number of filled locations in the FIFO
|
||||
uint32_t dma_ack: 1; ///< DMA acknowledge signal
|
||||
uint32_t dma_req: 1; ///< DMA request signal
|
||||
};
|
||||
uint32_t val;
|
||||
} status;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t tx_watermark: 12; ///< FIFO TX watermark level
|
||||
uint32_t reserved1: 4;
|
||||
uint32_t rx_watermark: 12; ///< FIFO RX watermark level
|
||||
uint32_t dw_dma_mts: 3;
|
||||
uint32_t reserved2: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} fifoth;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N reads 0 if card N is present
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} cdetect;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N reads 1 if card N is write protected
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} wrtprt;
|
||||
|
||||
uint32_t gpio; ///< unused
|
||||
uint32_t tcbcnt; ///< transferred (to card) byte count
|
||||
uint32_t tbbcnt; ///< transferred from host to FIFO byte count
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms
|
||||
uint32_t reserved: 8;
|
||||
};
|
||||
} debnce;
|
||||
|
||||
uint32_t usrid; ///< user ID
|
||||
uint32_t verid; ///< IP block version
|
||||
uint32_t hcon; ///< compile-time IP configuration
|
||||
uint32_t uhs; ///< TBD
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t cards: 2; ///< bit N resets card N, active low
|
||||
uint32_t reserved: 30;
|
||||
};
|
||||
} rst_n;
|
||||
|
||||
uint32_t reserved_7c;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_reset: 1; ///< set to reset DMA controller
|
||||
uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers
|
||||
uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors
|
||||
uint32_t enable: 1; ///< set to enable IDMAC
|
||||
uint32_t pbl: 3; ///< programmable burst length
|
||||
uint32_t reserved: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} bmod;
|
||||
|
||||
uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state
|
||||
sdmmc_desc_t *dbaddr; ///< descriptor list base
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t ti: 1; ///< transmit interrupt status
|
||||
uint32_t ri: 1; ///< receive interrupt status
|
||||
uint32_t fbe: 1; ///< fatal bus error
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t du: 1; ///< descriptor unavailable
|
||||
uint32_t ces: 1; ///< card error summary
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t nis: 1; ///< normal interrupt summary
|
||||
uint32_t fbe_code: 3; ///< code of fatal bus error
|
||||
uint32_t fsm: 4; ///< DMAC FSM state
|
||||
uint32_t reserved3: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} idsts;
|
||||
|
||||
union {
|
||||
struct {
|
||||
uint32_t ti: 1; ///< transmit interrupt enable
|
||||
uint32_t ri: 1; ///< receive interrupt enable
|
||||
uint32_t fbe: 1; ///< fatal bus error interrupt enable
|
||||
uint32_t reserved1: 1;
|
||||
uint32_t du: 1; ///< descriptor unavailable interrupt enable
|
||||
uint32_t ces: 1; ///< card error interrupt enable
|
||||
uint32_t reserved2: 2;
|
||||
uint32_t ni: 1; ///< normal interrupt interrupt enable
|
||||
uint32_t ai: 1; ///< abnormal interrupt enable
|
||||
uint32_t reserved3: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} idinten;
|
||||
|
||||
uint32_t dscaddr; ///< current host descriptor address
|
||||
uint32_t dscaddrl; ///< unused
|
||||
uint32_t dscaddru; ///< unused
|
||||
uint32_t bufaddrl; ///< unused
|
||||
uint32_t bufaddru; ///< unused
|
||||
uint32_t reserved_a8[22];
|
||||
uint32_t cardthrctl;
|
||||
uint32_t back_end_power;
|
||||
uint32_t uhs_reg_ext;
|
||||
uint32_t emmc_ddr_reg;
|
||||
uint32_t enable_shift;
|
||||
uint32_t reserved_114[443];
|
||||
union {
|
||||
struct {
|
||||
uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270)
|
||||
uint32_t phase_din: 3; ///< phase of data input clock
|
||||
uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral
|
||||
uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz
|
||||
uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz
|
||||
uint32_t div_factor_m: 4; ///< should be equal to div_factor_p
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
} sdmmc_dev_t;
|
||||
extern sdmmc_dev_t SDMMC;
|
||||
|
||||
_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure");
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1722
components/soc/soc/esp32s3/include/soc/sens_reg.h
Normal file
1722
components/soc/soc/esp32s3/include/soc/sens_reg.h
Normal file
File diff suppressed because it is too large
Load diff
506
components/soc/soc/esp32s3/include/soc/sens_struct.h
Normal file
506
components/soc/soc/esp32s3/include/soc/sens_struct.h
Normal file
|
|
@ -0,0 +1,506 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_clk_div: 8; /*clock divider*/
|
||||
uint32_t reserved8: 10;
|
||||
uint32_t sar1_clk_gated: 1;
|
||||
uint32_t sar1_sample_num: 8;
|
||||
uint32_t reserved27: 1;
|
||||
uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/
|
||||
uint32_t sar1_int_en: 1; /*enable saradc1 to send out interrupt*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_reader1_ctrl;
|
||||
uint32_t sar_reader1_status; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 24;
|
||||
uint32_t force_xpd_amp: 2;
|
||||
uint32_t amp_rst_fb_force: 2;
|
||||
uint32_t amp_short_ref_force: 2;
|
||||
uint32_t amp_short_ref_gnd_force: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/
|
||||
uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/
|
||||
uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion*/
|
||||
uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/
|
||||
uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap*/
|
||||
uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 31;
|
||||
uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas1_mux;
|
||||
uint32_t sar_atten1; /*2-bit attenuation for each pad*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_amp_wait1: 16;
|
||||
uint32_t sar_amp_wait2: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_amp_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_dac_xpd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_amp_fsm_idle: 1;
|
||||
uint32_t amp_rst_fb_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_fsm_idle: 1;
|
||||
uint32_t amp_short_ref_gnd_fsm_idle: 1;
|
||||
uint32_t xpd_sar_fsm_idle: 1;
|
||||
uint32_t sar_rstb_fsm_idle: 1;
|
||||
uint32_t reserved7: 9;
|
||||
uint32_t sar_amp_wait3: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_amp_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar1_dac_xpd_fsm: 4;
|
||||
uint32_t xpd_sar_amp_fsm: 4;
|
||||
uint32_t amp_rst_fb_fsm: 4;
|
||||
uint32_t amp_short_ref_fsm: 4;
|
||||
uint32_t amp_short_ref_gnd_fsm: 4;
|
||||
uint32_t xpd_sar_fsm: 4;
|
||||
uint32_t sar_rstb_fsm: 4;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_amp_ctrl3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_clk_div: 8; /*clock divider*/
|
||||
uint32_t reserved8: 8;
|
||||
uint32_t sar2_wait_arb_cycle: 2; /*wait arbit stable after sar_done*/
|
||||
uint32_t sar2_clk_gated: 1;
|
||||
uint32_t sar2_sample_num: 8;
|
||||
uint32_t reserved27: 2;
|
||||
uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/
|
||||
uint32_t sar2_int_en: 1; /*enable saradc2 to send out interrupt*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_reader2_ctrl;
|
||||
uint32_t sar_reader2_status; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar2_cntl_state: 3; /*saradc2_cntl_fsm*/
|
||||
uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/
|
||||
uint32_t sar2_pkdet_cal_en: 1; /*rtc control pkdet enable*/
|
||||
uint32_t sar2_en_test: 1; /*SAR2_EN_TEST*/
|
||||
uint32_t sar2_rstb_force: 2;
|
||||
uint32_t sar2_standby_wait: 8;
|
||||
uint32_t sar2_rstb_wait: 8;
|
||||
uint32_t sar2_xpd_wait: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/
|
||||
uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/
|
||||
uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion*/
|
||||
uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/
|
||||
uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap*/
|
||||
uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 28;
|
||||
uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/
|
||||
uint32_t sar2_rtc_force: 1; /*in sleep force to use rtc to control ADC*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_meas2_mux;
|
||||
uint32_t sar_atten2; /*2-bit attenuation for each pad*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 29;
|
||||
uint32_t force_xpd_sar: 2;
|
||||
uint32_t sarclk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_power_xpd_sar;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr1: 11;
|
||||
uint32_t i2c_slave_addr0: 11;
|
||||
uint32_t meas_status: 8;
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr3: 11;
|
||||
uint32_t i2c_slave_addr2: 11;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr5: 11;
|
||||
uint32_t i2c_slave_addr4: 11;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr3;
|
||||
union {
|
||||
struct {
|
||||
uint32_t i2c_slave_addr7: 11;
|
||||
uint32_t i2c_slave_addr6: 11;
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_slave_addr4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_out: 8; /*temperature sensor data out*/
|
||||
uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/
|
||||
uint32_t reserved9: 3;
|
||||
uint32_t tsens_int_en: 1; /*enable temperature sensor to send out interrupt*/
|
||||
uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/
|
||||
uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/
|
||||
uint32_t tsens_power_up: 1; /*temperature sensor power up*/
|
||||
uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW*/
|
||||
uint32_t tsens_dump_out: 1; /*temperature sensor dump out*/
|
||||
uint32_t reserved25: 7;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_tctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t tsens_xpd_wait: 12;
|
||||
uint32_t tsens_xpd_force: 2;
|
||||
uint32_t tsens_clk_inv: 1;
|
||||
uint32_t reserved15: 17;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_tctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_i2c_ctrl: 28; /*I2C control data*/
|
||||
uint32_t sar_i2c_start: 1; /*start I2C*/
|
||||
uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW*/
|
||||
uint32_t reserved30: 2;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_i2c_ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_outen: 15; /*touch controller output enable*/
|
||||
uint32_t touch_status_clr: 1; /*clear all touch active status*/
|
||||
uint32_t touch_data_sel: 2; /*3: smooth data 2: baseline 1 0: raw_data*/
|
||||
uint32_t touch_denoise_end: 1; /*touch_denoise_done*/
|
||||
uint32_t touch_unit_end: 1; /*touch_unit_done*/
|
||||
uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/
|
||||
uint32_t touch_approach_pad1: 4; /*indicate which pad is approach pad1*/
|
||||
uint32_t touch_approach_pad0: 4; /*indicate which pad is approach pad0*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t thresh: 22; /*Finger threshold for touch pad 1*/
|
||||
uint32_t reserved22: 10;
|
||||
};
|
||||
uint32_t val;
|
||||
} touch_thresh[14];
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
uint32_t reserved_a8;
|
||||
uint32_t reserved_ac;
|
||||
uint32_t reserved_b0;
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t reserved_cc;
|
||||
uint32_t reserved_d0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_pad_active: 15; /*touch active status*/
|
||||
uint32_t touch_channel_clr: 15; /*Clear touch channel*/
|
||||
uint32_t reserved30: 1;
|
||||
uint32_t touch_meas_done: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_chn_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_denoise_data: 22; /*the counter for touch pad 0*/
|
||||
uint32_t touch_scan_curr: 4;
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_status0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_pad1_data: 22;
|
||||
uint32_t reserved22: 7;
|
||||
uint32_t touch_pad_debounce: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_status[14];
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_slp_data: 22;
|
||||
uint32_t reserved22: 7;
|
||||
uint32_t touch_slp_debounce: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_status15;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_approach_pad2_cnt: 8;
|
||||
uint32_t touch_approach_pad1_cnt: 8;
|
||||
uint32_t touch_approach_pad0_cnt: 8;
|
||||
uint32_t touch_slp_approach_cnt: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_touch_status16;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sw_fstep: 16; /*frequency step for CW generator*/
|
||||
uint32_t sw_tone_en: 1; /*1: enable CW generator*/
|
||||
uint32_t debug_bit_sel: 5;
|
||||
uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA*/
|
||||
uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/
|
||||
uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/
|
||||
uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_dac_ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/
|
||||
uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/
|
||||
uint32_t dac_scale1: 2; /*00: no scale*/
|
||||
uint32_t dac_scale2: 2; /*00: no scale*/
|
||||
uint32_t dac_inv1: 2; /*00: do not invert any bits*/
|
||||
uint32_t dac_inv2: 2; /*00: do not invert any bits*/
|
||||
uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0]*/
|
||||
uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0]*/
|
||||
uint32_t reserved26: 6;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_dac_ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 25;
|
||||
uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/
|
||||
uint32_t clk_en_st: 1; /*check cocpu whether clk on*/
|
||||
uint32_t reset_n: 1; /*check cocpu whether in reset state*/
|
||||
uint32_t eoi: 1; /*check cocpu whether in interrupt state*/
|
||||
uint32_t trap: 1; /*check cocpu whether in trap state*/
|
||||
uint32_t ebreak: 1; /*check cocpu whether in ebreak*/
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_state;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done: 1; /*int from touch done*/
|
||||
uint32_t touch_inactive: 1; /*int from touch inactive*/
|
||||
uint32_t touch_active: 1; /*int from touch active*/
|
||||
uint32_t saradc1: 1; /*int from saradc1*/
|
||||
uint32_t saradc2: 1; /*int from saradc2*/
|
||||
uint32_t tsens: 1; /*int from tsens*/
|
||||
uint32_t start: 1; /*int from start*/
|
||||
uint32_t sw: 1; /*int from software*/
|
||||
uint32_t swd: 1; /*int from super watch dog*/
|
||||
uint32_t touch_timeout: 1;
|
||||
uint32_t touch_approach_loop_done: 1;
|
||||
uint32_t touch_scan_done: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done: 1;
|
||||
uint32_t touch_inactive: 1;
|
||||
uint32_t touch_active: 1;
|
||||
uint32_t saradc1: 1;
|
||||
uint32_t saradc2: 1;
|
||||
uint32_t tsens: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t sw: 1; /*cocpu int enable*/
|
||||
uint32_t swd: 1;
|
||||
uint32_t touch_timeout: 1;
|
||||
uint32_t touch_approach_loop_done: 1;
|
||||
uint32_t touch_scan_done: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done: 1;
|
||||
uint32_t touch_inactive: 1;
|
||||
uint32_t touch_active: 1;
|
||||
uint32_t saradc1: 1;
|
||||
uint32_t saradc2: 1;
|
||||
uint32_t tsens: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t sw: 1; /*cocpu int status*/
|
||||
uint32_t swd: 1;
|
||||
uint32_t touch_timeout: 1;
|
||||
uint32_t touch_approach_loop_done: 1;
|
||||
uint32_t touch_scan_done: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done: 1;
|
||||
uint32_t touch_inactive: 1;
|
||||
uint32_t touch_active: 1;
|
||||
uint32_t saradc1: 1;
|
||||
uint32_t saradc2: 1;
|
||||
uint32_t tsens: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t sw: 1; /*cocpu int clear*/
|
||||
uint32_t swd: 1;
|
||||
uint32_t touch_timeout: 1;
|
||||
uint32_t touch_approach_loop_done: 1;
|
||||
uint32_t touch_scan_done: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_clr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t pc: 13; /*cocpu Program counter*/
|
||||
uint32_t mem_vld: 1; /*cocpu mem valid output*/
|
||||
uint32_t mem_rdy: 1; /*cocpu mem ready input*/
|
||||
uint32_t mem_wen: 4; /*cocpu mem write enable output*/
|
||||
uint32_t mem_addr: 13; /*cocpu mem address output*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_debug;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 28;
|
||||
uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/
|
||||
uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/
|
||||
uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/
|
||||
uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_hall_ctrl;
|
||||
uint32_t sar_nouse; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 26;
|
||||
uint32_t dac_clk_en: 1;
|
||||
uint32_t rtc_i2c_clk_en: 1;
|
||||
uint32_t reserved28: 1;
|
||||
uint32_t tsens_clk_en: 1;
|
||||
uint32_t saradc_clk_en: 1;
|
||||
uint32_t iomux_clk_en: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_peri_clk_gate_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 25;
|
||||
uint32_t reset: 1;
|
||||
uint32_t dac_reset: 1;
|
||||
uint32_t rtc_i2c_reset: 1;
|
||||
uint32_t reserved28: 1;
|
||||
uint32_t tsens_reset: 1;
|
||||
uint32_t saradc_reset: 1;
|
||||
uint32_t reserved31: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_peri_reset_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done_w1ts: 1;
|
||||
uint32_t touch_inactive_w1ts: 1;
|
||||
uint32_t touch_active_w1ts: 1;
|
||||
uint32_t saradc1_w1ts: 1;
|
||||
uint32_t saradc2_w1ts: 1;
|
||||
uint32_t tsens_w1ts: 1;
|
||||
uint32_t start_w1ts: 1;
|
||||
uint32_t sw_w1ts: 1;
|
||||
uint32_t swd_w1ts: 1;
|
||||
uint32_t touch_timeout_w1ts: 1;
|
||||
uint32_t touch_approach_loop_done_w1ts: 1;
|
||||
uint32_t touch_scan_done_w1ts: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_ena_w1ts;
|
||||
union {
|
||||
struct {
|
||||
uint32_t touch_done_w1tc: 1;
|
||||
uint32_t touch_inactive_w1tc: 1;
|
||||
uint32_t touch_active_w1tc: 1;
|
||||
uint32_t saradc1_w1tc: 1;
|
||||
uint32_t saradc2_w1tc: 1;
|
||||
uint32_t tsens_w1tc: 1;
|
||||
uint32_t start_w1tc: 1;
|
||||
uint32_t sw_w1tc: 1;
|
||||
uint32_t swd_w1tc: 1;
|
||||
uint32_t touch_timeout_w1tc: 1;
|
||||
uint32_t touch_approach_loop_done_w1tc: 1;
|
||||
uint32_t touch_scan_done_w1tc: 1;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} sar_cocpu_int_ena_w1tc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sar_date: 28;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} sardate;
|
||||
} sens_dev_t;
|
||||
|
||||
extern sens_dev_t SENS;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
4136
components/soc/soc/esp32s3/include/soc/sensitive_reg.h
Normal file
4136
components/soc/soc/esp32s3/include/soc/sensitive_reg.h
Normal file
File diff suppressed because it is too large
Load diff
2281
components/soc/soc/esp32s3/include/soc/sensitive_struct.h
Normal file
2281
components/soc/soc/esp32s3/include/soc/sensitive_struct.h
Normal file
File diff suppressed because it is too large
Load diff
37
components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h
Normal file
37
components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h
Normal file
|
|
@ -0,0 +1,37 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
// ESP32-S3 have 1 SIGMADELTA peripheral.
|
||||
#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */
|
||||
#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */
|
||||
#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX)
|
||||
|
||||
#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */
|
||||
#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */
|
||||
#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */
|
||||
#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */
|
||||
#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */
|
||||
#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */
|
||||
#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */
|
||||
#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */
|
||||
#define SIGMADELTA_CHANNEL_MAX (8)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
1906
components/soc/soc/esp32s3/include/soc/slc_reg.h
Normal file
1906
components/soc/soc/esp32s3/include/soc/slc_reg.h
Normal file
File diff suppressed because it is too large
Load diff
590
components/soc/soc/esp32s3/include/soc/slc_struct.h
Normal file
590
components/soc/soc/esp32s3/include/soc/slc_struct.h
Normal file
|
|
@ -0,0 +1,590 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_tx_rst: 1;
|
||||
uint32_t slc0_rx_rst: 1;
|
||||
uint32_t ahbm_fifo_rst: 1;
|
||||
uint32_t ahbm_rst: 1;
|
||||
uint32_t slc0_tx_loop_test: 1;
|
||||
uint32_t slc0_rx_loop_test: 1;
|
||||
uint32_t slc0_rx_auto_wrback: 1;
|
||||
uint32_t slc0_rx_no_restart_clr: 1;
|
||||
uint32_t slc0_rxdscr_burst_en: 1;
|
||||
uint32_t slc0_rxdata_burst_en: 1;
|
||||
uint32_t slc0_rxlink_auto_ret: 1;
|
||||
uint32_t slc0_txlink_auto_ret: 1;
|
||||
uint32_t slc0_txdscr_burst_en: 1;
|
||||
uint32_t slc0_txdata_burst_en: 1;
|
||||
uint32_t slc0_token_auto_clr: 1;
|
||||
uint32_t slc0_token_sel: 1;
|
||||
uint32_t reserved16: 2;
|
||||
uint32_t slc0_wr_retry_mask_en: 1;
|
||||
uint32_t reserved19: 13;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t host_pop_eof_err: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_raw;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t host_pop_eof_err: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t host_pop_eof_err: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit0: 1;
|
||||
uint32_t frhost_bit1: 1;
|
||||
uint32_t frhost_bit2: 1;
|
||||
uint32_t frhost_bit3: 1;
|
||||
uint32_t frhost_bit4: 1;
|
||||
uint32_t frhost_bit5: 1;
|
||||
uint32_t frhost_bit6: 1;
|
||||
uint32_t frhost_bit7: 1;
|
||||
uint32_t rx_start: 1;
|
||||
uint32_t tx_start: 1;
|
||||
uint32_t rx_udf: 1;
|
||||
uint32_t tx_ovf: 1;
|
||||
uint32_t token0_1to0: 1;
|
||||
uint32_t token1_1to0: 1;
|
||||
uint32_t tx_done: 1;
|
||||
uint32_t tx_suc_eof: 1;
|
||||
uint32_t rx_done: 1;
|
||||
uint32_t rx_eof: 1;
|
||||
uint32_t tohost: 1;
|
||||
uint32_t tx_dscr_err: 1;
|
||||
uint32_t rx_dscr_err: 1;
|
||||
uint32_t tx_dscr_empty: 1;
|
||||
uint32_t host_rd_ack: 1;
|
||||
uint32_t wr_retry_done: 1;
|
||||
uint32_t tx_err_eof: 1;
|
||||
uint32_t cmd_dtc: 1;
|
||||
uint32_t rx_quick_eof: 1;
|
||||
uint32_t host_pop_eof_err: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_clr;
|
||||
uint32_t reserved_14;
|
||||
uint32_t reserved_18;
|
||||
uint32_t reserved_1c;
|
||||
uint32_t reserved_20;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_rx_full: 1;
|
||||
uint32_t slc0_rx_empty: 1;
|
||||
uint32_t slc0_rx_buf_len: 12;
|
||||
uint32_t reserved14: 18;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rxfifo_wdata: 9;
|
||||
uint32_t reserved9: 7;
|
||||
uint32_t rxfifo_push: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rxfifo_push;
|
||||
uint32_t reserved_2c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_tx_full: 1;
|
||||
uint32_t slc0_tx_empty: 1;
|
||||
uint32_t reserved2: 30;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_status;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txfifo_rdata: 11;
|
||||
uint32_t reserved11: 5;
|
||||
uint32_t txfifo_pop: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_txfifo_pop;
|
||||
uint32_t reserved_38;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_rx_link;
|
||||
union {
|
||||
struct {
|
||||
uint32_t addr: 20;
|
||||
uint32_t reserved20: 8;
|
||||
uint32_t stop: 1;
|
||||
uint32_t start: 1;
|
||||
uint32_t restart: 1;
|
||||
uint32_t park: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_tx_link;
|
||||
uint32_t reserved_44;
|
||||
uint32_t reserved_48;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_intvec: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} intvec_tohost;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata: 12;
|
||||
uint32_t wr: 1;
|
||||
uint32_t inc: 1;
|
||||
uint32_t inc_more: 1;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t token0: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wdata: 12;
|
||||
uint32_t wr: 1;
|
||||
uint32_t inc: 1;
|
||||
uint32_t inc_more: 1;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t token1: 12;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_token1;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_check_owner: 1;
|
||||
uint32_t slc0_tx_check_sum_en: 1;
|
||||
uint32_t slc0_rx_check_sum_en: 1;
|
||||
uint32_t cmd_hold_en: 1;
|
||||
uint32_t slc0_len_auto_clr: 1;
|
||||
uint32_t slc0_tx_stitch_en: 1;
|
||||
uint32_t slc0_rx_stitch_en: 1;
|
||||
uint32_t reserved7: 12;
|
||||
uint32_t host_int_level_sel: 1;
|
||||
uint32_t reserved20: 2;
|
||||
uint32_t clk_en: 1;
|
||||
uint32_t reserved23: 9;
|
||||
};
|
||||
uint32_t val;
|
||||
} conf1;
|
||||
uint32_t slc0_state0; /**/
|
||||
uint32_t slc0_state1; /**/
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
union {
|
||||
struct {
|
||||
uint32_t txeof_ena: 6;
|
||||
uint32_t reserved6: 2;
|
||||
uint32_t fifo_map_ena: 4;
|
||||
uint32_t slc0_tx_dummy_mode: 1;
|
||||
uint32_t hda_map_128k: 1;
|
||||
uint32_t reserved14: 2;
|
||||
uint32_t tx_push_idle_num: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} bridge_conf;
|
||||
uint32_t slc0_to_eof_des_addr; /**/
|
||||
uint32_t slc0_tx_eof_des_addr; /**/
|
||||
uint32_t slc0_to_eof_bfr_des_addr; /**/
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
union {
|
||||
struct {
|
||||
uint32_t mode: 3;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t addr: 2;
|
||||
uint32_t reserved6: 26;
|
||||
};
|
||||
uint32_t val;
|
||||
} ahb_test;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmd_st: 3;
|
||||
uint32_t reserved3: 1;
|
||||
uint32_t func_st: 4;
|
||||
uint32_t sdio_wakeup: 1;
|
||||
uint32_t reserved9: 3;
|
||||
uint32_t bus_st: 3;
|
||||
uint32_t reserved15: 1;
|
||||
uint32_t func1_acc_state: 5;
|
||||
uint32_t reserved21: 11;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_st;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_token_no_replace: 1;
|
||||
uint32_t slc0_infor_no_replace: 1;
|
||||
uint32_t slc0_rx_fill_mode: 1;
|
||||
uint32_t slc0_rx_eof_mode: 1;
|
||||
uint32_t slc0_rx_fill_en: 1;
|
||||
uint32_t slc0_rd_retry_threshold: 11;
|
||||
uint32_t reserved16: 16;
|
||||
};
|
||||
uint32_t val;
|
||||
} rx_dscr_conf;
|
||||
uint32_t slc0_txlink_dscr; /**/
|
||||
uint32_t slc0_txlink_dscr_bf0; /**/
|
||||
uint32_t slc0_txlink_dscr_bf1; /**/
|
||||
uint32_t slc0_rxlink_dscr; /**/
|
||||
uint32_t slc0_rxlink_dscr_bf0; /**/
|
||||
uint32_t slc0_rxlink_dscr_bf1; /**/
|
||||
uint32_t reserved_b4;
|
||||
uint32_t reserved_b8;
|
||||
uint32_t reserved_bc;
|
||||
uint32_t reserved_c0;
|
||||
uint32_t reserved_c4;
|
||||
uint32_t reserved_c8;
|
||||
uint32_t slc0_tx_erreof_des_addr; /**/
|
||||
uint32_t reserved_d0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_token: 12;
|
||||
uint32_t reserved12: 20;
|
||||
};
|
||||
uint32_t val;
|
||||
} token_lat;
|
||||
union {
|
||||
struct {
|
||||
uint32_t wr_retry_threshold: 11;
|
||||
uint32_t reserved11: 21;
|
||||
};
|
||||
uint32_t val;
|
||||
} tx_dscr_conf;
|
||||
uint32_t cmd_infor0; /**/
|
||||
uint32_t cmd_infor1; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t len_wdata: 20;
|
||||
uint32_t len_wr: 1;
|
||||
uint32_t len_inc: 1;
|
||||
uint32_t len_inc_more: 1;
|
||||
uint32_t rx_packet_load_en: 1;
|
||||
uint32_t tx_packet_load_en: 1;
|
||||
uint32_t rx_get_used_dscr: 1;
|
||||
uint32_t tx_get_used_dscr: 1;
|
||||
uint32_t rx_new_pkt_ind: 1;
|
||||
uint32_t tx_new_pkt_ind: 1;
|
||||
uint32_t reserved29: 3;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_len_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t len: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_length;
|
||||
uint32_t slc0_txpkt_h_dscr; /**/
|
||||
uint32_t slc0_txpkt_e_dscr; /**/
|
||||
uint32_t slc0_rxpkt_h_dscr; /**/
|
||||
uint32_t slc0_rxpkt_e_dscr; /**/
|
||||
uint32_t slc0_txpktu_h_dscr; /**/
|
||||
uint32_t slc0_txpktu_e_dscr; /**/
|
||||
uint32_t slc0_rxpktu_h_dscr; /**/
|
||||
uint32_t slc0_rxpktu_e_dscr; /**/
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
union {
|
||||
struct {
|
||||
uint32_t slc0_position: 8;
|
||||
uint32_t reserved8: 24;
|
||||
};
|
||||
uint32_t val;
|
||||
} seq_position;
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_dscr_rec_lim: 10;
|
||||
uint32_t reserved10: 22;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_dscr_rec_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dat0_crc_err_cnt: 8;
|
||||
uint32_t dat1_crc_err_cnt: 8;
|
||||
uint32_t dat2_crc_err_cnt: 8;
|
||||
uint32_t dat3_crc_err_cnt: 8;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_crc_st0;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cmd_crc_err_cnt: 8;
|
||||
uint32_t reserved8: 23;
|
||||
uint32_t err_cnt_clr: 1;
|
||||
};
|
||||
uint32_t val;
|
||||
} sdio_crc_st1;
|
||||
uint32_t slc0_eof_start_des; /**/
|
||||
uint32_t slc0_push_dscr_addr; /**/
|
||||
uint32_t slc0_done_dscr_addr; /**/
|
||||
uint32_t slc0_sub_start_des; /**/
|
||||
union {
|
||||
struct {
|
||||
uint32_t rx_dscr_cnt_lat: 10;
|
||||
uint32_t reserved10: 6;
|
||||
uint32_t rx_get_eof_occ: 1;
|
||||
uint32_t reserved17: 15;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_dscr_cnt;
|
||||
union {
|
||||
struct {
|
||||
uint32_t len_lim: 20;
|
||||
uint32_t reserved20: 12;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_len_lim_conf;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit01: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit21: 1;
|
||||
uint32_t frhost_bit31: 1;
|
||||
uint32_t frhost_bit41: 1;
|
||||
uint32_t frhost_bit51: 1;
|
||||
uint32_t frhost_bit61: 1;
|
||||
uint32_t frhost_bit71: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t tx_done1: 1;
|
||||
uint32_t tx_suc_eof1: 1;
|
||||
uint32_t rx_done1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t tohost1: 1;
|
||||
uint32_t tx_dscr_err1: 1;
|
||||
uint32_t rx_dscr_err1: 1;
|
||||
uint32_t tx_dscr_empty1: 1;
|
||||
uint32_t host_rd_ack1: 1;
|
||||
uint32_t wr_retry_done1: 1;
|
||||
uint32_t tx_err_eof1: 1;
|
||||
uint32_t cmd_dtc1: 1;
|
||||
uint32_t rx_quick_eof1: 1;
|
||||
uint32_t host_pop_eof_err1: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_st1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t frhost_bit01: 1;
|
||||
uint32_t frhost_bit11: 1;
|
||||
uint32_t frhost_bit21: 1;
|
||||
uint32_t frhost_bit31: 1;
|
||||
uint32_t frhost_bit41: 1;
|
||||
uint32_t frhost_bit51: 1;
|
||||
uint32_t frhost_bit61: 1;
|
||||
uint32_t frhost_bit71: 1;
|
||||
uint32_t rx_start1: 1;
|
||||
uint32_t tx_start1: 1;
|
||||
uint32_t rx_udf1: 1;
|
||||
uint32_t tx_ovf1: 1;
|
||||
uint32_t token0_1to01: 1;
|
||||
uint32_t token1_1to01: 1;
|
||||
uint32_t tx_done1: 1;
|
||||
uint32_t tx_suc_eof1: 1;
|
||||
uint32_t rx_done1: 1;
|
||||
uint32_t rx_eof1: 1;
|
||||
uint32_t tohost1: 1;
|
||||
uint32_t tx_dscr_err1: 1;
|
||||
uint32_t rx_dscr_err1: 1;
|
||||
uint32_t tx_dscr_empty1: 1;
|
||||
uint32_t host_rd_ack1: 1;
|
||||
uint32_t wr_retry_done1: 1;
|
||||
uint32_t tx_err_eof1: 1;
|
||||
uint32_t cmd_dtc1: 1;
|
||||
uint32_t rx_quick_eof1: 1;
|
||||
uint32_t host_pop_eof_err1: 1;
|
||||
uint32_t reserved28: 4;
|
||||
};
|
||||
uint32_t val;
|
||||
} slc0_int_ena1;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t date; /**/
|
||||
uint32_t id; /**/
|
||||
} slc_dev_t;
|
||||
|
||||
extern slc_dev_t SLC;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
331
components/soc/soc/esp32s3/include/soc/soc.h
Normal file
331
components/soc/soc/esp32s3/include/soc/soc.h
Normal file
|
|
@ -0,0 +1,331 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <stdint.h>
|
||||
#include "esp_assert.h"
|
||||
#include "esp_bit_defs.h"
|
||||
#endif
|
||||
|
||||
#define PRO_CPU_NUM (0)
|
||||
#define APP_CPU_NUM (1)
|
||||
|
||||
#define PRO_CPUID (0xcdcd)
|
||||
#define APP_CPUID (0xabab)
|
||||
|
||||
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
|
||||
|
||||
#define DR_REG_SYSTEM_BASE 0x600c0000
|
||||
#define DR_REG_SENSITIVE_BASE 0x600c1000
|
||||
#define DR_REG_INTERRUPT_BASE 0x600c2000
|
||||
#define DR_REG_DMA_COPY_BASE 0x600c3000
|
||||
#define DR_REG_EXTMEM_BASE 0x600c4000
|
||||
#define DR_REG_MMU_TABLE 0x600c5000
|
||||
#define DR_REG_ITAG_TABLE 0x600c6000
|
||||
#define DR_REG_DTAG_TABLE 0x600c8000
|
||||
#define DR_REG_AES_BASE 0x6003a000
|
||||
#define DR_REG_SHA_BASE 0x6003b000
|
||||
#define DR_REG_RSA_BASE 0x6003c000
|
||||
#define DR_REG_HMAC_BASE 0x6003e000
|
||||
#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000
|
||||
#define DR_REG_CRYPTO_DMA_BASE 0x6003f000
|
||||
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
|
||||
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
|
||||
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
|
||||
#define DR_REG_DPORT_END 0x600d3FFC
|
||||
#define DR_REG_UART_BASE 0x60000000
|
||||
#define DR_REG_SPI1_BASE 0x60002000
|
||||
#define DR_REG_SPI0_BASE 0x60003000
|
||||
#define DR_REG_GPIO_BASE 0x60004000
|
||||
#define DR_REG_GPIO_SD_BASE 0x60004f00
|
||||
#define DR_REG_FE2_BASE 0x60005000
|
||||
#define DR_REG_FE_BASE 0x60006000
|
||||
#define DR_REG_FRC_TIMER_BASE 0x60007000
|
||||
#define DR_REG_RTCCNTL_BASE 0x60008000
|
||||
#define DR_REG_RTCIO_BASE 0x60008400
|
||||
#define DR_REG_SENS_BASE 0x60008800
|
||||
#define DR_REG_RTC_I2C_BASE 0x60008C00
|
||||
#define DR_REG_IO_MUX_BASE 0x60009000
|
||||
#define DR_REG_HINF_BASE 0x6000B000
|
||||
#define DR_REG_UHCI1_BASE 0x6000C000
|
||||
#define DR_REG_I2S_BASE 0x6000F000
|
||||
#define DR_REG_UART1_BASE 0x60010000
|
||||
#define DR_REG_BT_BASE 0x60011000
|
||||
#define DR_REG_I2C_EXT_BASE 0x60013000
|
||||
#define DR_REG_UHCI0_BASE 0x60014000
|
||||
#define DR_REG_SLCHOST_BASE 0x60015000
|
||||
#define DR_REG_RMT_BASE 0x60016000
|
||||
#define DR_REG_PCNT_BASE 0x60017000
|
||||
#define DR_REG_SLC_BASE 0x60018000
|
||||
#define DR_REG_LEDC_BASE 0x60019000
|
||||
#define DR_REG_EFUSE_BASE 0x6001A000
|
||||
#define DR_REG_NRX_BASE 0x6001CC00
|
||||
#define DR_REG_BB_BASE 0x6001D000
|
||||
#define DR_REG_PWM_BASE 0x6001E000
|
||||
#define DR_REG_TIMERGROUP0_BASE 0x6001F000
|
||||
#define DR_REG_TIMERGROUP1_BASE 0x60020000
|
||||
#define DR_REG_RTC_SLOWMEM_BASE 0x60021000
|
||||
#define DR_REG_SYS_TIMER_BASE 0x60023000
|
||||
#define DR_REG_SPI2_BASE 0x60024000
|
||||
#define DR_REG_SPI3_BASE 0x60025000
|
||||
#define DR_REG_SYSCON_BASE 0x60026000
|
||||
#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */
|
||||
#define DR_REG_I2C1_EXT_BASE 0x60027000
|
||||
#define DR_REG_SDMMC_BASE 0x60028000
|
||||
#define DR_REG_TWAI_BASE 0x6002B000
|
||||
#define DR_REG_PWM1_BASE 0x6002C000
|
||||
#define DR_REG_I2S1_BASE 0x6002D000
|
||||
#define DR_REG_UART2_BASE 0x6002E000
|
||||
#define DR_REG_PWM2_BASE 0x6002F000
|
||||
#define DR_REG_PWM3_BASE 0x60030000
|
||||
#define DR_REG_SPI4_BASE 0x60037000
|
||||
#define DR_REG_USB_WRAP_BASE 0x60039000
|
||||
#define DR_REG_APB_SARADC_BASE 0x60040000
|
||||
#define DR_REG_LCD_CAM_BASE 0x60041000
|
||||
|
||||
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
|
||||
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
|
||||
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
|
||||
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
|
||||
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
|
||||
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
|
||||
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
|
||||
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
|
||||
|
||||
//Registers Operation {{
|
||||
#define ETS_UNCACHED_ADDR(addr) (addr)
|
||||
#define ETS_CACHED_ADDR(addr) (addr)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
//write value to register
|
||||
#define REG_WRITE(_r, _v) ({ \
|
||||
(*(volatile uint32_t *)(_r)) = (_v); \
|
||||
})
|
||||
|
||||
//read value from register
|
||||
#define REG_READ(_r) ({ \
|
||||
(*(volatile uint32_t *)(_r)); \
|
||||
})
|
||||
|
||||
//get bit or get bits from register
|
||||
#define REG_GET_BIT(_r, _b) ({ \
|
||||
(*(volatile uint32_t*)(_r) & (_b)); \
|
||||
})
|
||||
|
||||
//set bit or set bits to register
|
||||
#define REG_SET_BIT(_r, _b) ({ \
|
||||
(*(volatile uint32_t*)(_r) |= (_b)); \
|
||||
})
|
||||
|
||||
//clear bit or clear bits of register
|
||||
#define REG_CLR_BIT(_r, _b) ({ \
|
||||
(*(volatile uint32_t*)(_r) &= ~(_b)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define REG_SET_BITS(_r, _b, _m) ({ \
|
||||
(*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \
|
||||
})
|
||||
|
||||
//get field from register, uses field _S & _V to determine mask
|
||||
#define REG_GET_FIELD(_r, _f) ({ \
|
||||
((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \
|
||||
})
|
||||
|
||||
//set field of a register from variable, uses field _S & _V to determine mask
|
||||
#define REG_SET_FIELD(_r, _f, _v) ({ \
|
||||
(REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \
|
||||
})
|
||||
|
||||
//get field value from a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f))
|
||||
|
||||
//get field value from a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S))
|
||||
|
||||
//set field value to a variable, used when _f is not left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S))))
|
||||
|
||||
//set field value to a variable, used when _f is left shifted by _f##_S
|
||||
#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S))))
|
||||
|
||||
//generate a value from a field value, used when _f is not left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S)
|
||||
|
||||
//generate a value from a field value, used when _f is left shifted by _f##_S
|
||||
#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f))
|
||||
|
||||
//read value from register
|
||||
#define READ_PERI_REG(addr) ({ \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \
|
||||
})
|
||||
|
||||
//write value to register
|
||||
#define WRITE_PERI_REG(addr, val) ({ \
|
||||
(*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \
|
||||
})
|
||||
|
||||
//clear bits of register controlled by mask
|
||||
#define CLEAR_PERI_REG_MASK(reg, mask) ({ \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask
|
||||
#define SET_PERI_REG_MASK(reg, mask) ({ \
|
||||
WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by mask
|
||||
#define GET_PERI_REG_MASK(reg, mask) ({ \
|
||||
(READ_PERI_REG(reg) & (mask)); \
|
||||
})
|
||||
|
||||
//get bits of register controlled by highest bit and lowest bit
|
||||
#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \
|
||||
((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \
|
||||
})
|
||||
|
||||
//set bits of register controlled by mask and shift
|
||||
#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \
|
||||
(WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \
|
||||
})
|
||||
|
||||
//get field of register
|
||||
#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \
|
||||
((READ_PERI_REG(reg)>>(shift))&(mask)); \
|
||||
})
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
//}}
|
||||
|
||||
//Periheral Clock {{
|
||||
#define APB_CLK_FREQ_ROM (40*1000000)
|
||||
#define CPU_CLK_FREQ_ROM (40*1000000)
|
||||
#define UART_CLK_FREQ_ROM (40*1000000)
|
||||
#define EFUSE_CLK_FREQ_ROM (20*1000000)
|
||||
#define CPU_CLK_FREQ APB_CLK_FREQ
|
||||
#define APB_CLK_FREQ (80*1000000)
|
||||
#define REF_CLK_FREQ (1000000)
|
||||
#define UART_CLK_FREQ APB_CLK_FREQ
|
||||
#define WDT_CLK_FREQ APB_CLK_FREQ
|
||||
#define TIMER_CLK_FREQ (80000000>>4)
|
||||
#define SPI_CLK_DIV 4
|
||||
#define TICKS_PER_US_ROM 40
|
||||
#define GPIO_MATRIX_DELAY_NS 0
|
||||
//}}
|
||||
|
||||
/* Overall memory map */
|
||||
#define SOC_DROM_LOW 0x3C000000
|
||||
#define SOC_DROM_HIGH 0x3D000000
|
||||
#define SOC_IROM_LOW 0x42000000
|
||||
#define SOC_IROM_HIGH 0x42800000
|
||||
#define SOC_IRAM_LOW 0x40370000
|
||||
#define SOC_IRAM_HIGH 0x403E0000
|
||||
#define SOC_DRAM_LOW 0x3FC88000
|
||||
#define SOC_DRAM_HIGH 0x3FD00000
|
||||
#define SOC_RTC_IRAM_LOW 0x600FE000
|
||||
#define SOC_RTC_IRAM_HIGH 0x60100000
|
||||
#define SOC_RTC_DRAM_LOW 0x600FE000
|
||||
#define SOC_RTC_DRAM_HIGH 0x60100000
|
||||
#define SOC_RTC_DATA_LOW 0x50000000
|
||||
#define SOC_RTC_DATA_HIGH 0x50002000
|
||||
#define SOC_EXTRAM_DATA_LOW 0x3D000000
|
||||
#define SOC_EXTRAM_DATA_HIGH 0x3E000000
|
||||
|
||||
//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias.
|
||||
#define SOC_DIRAM_IRAM_LOW 0x40378000
|
||||
#define SOC_DIRAM_IRAM_HIGH 0x403E0000
|
||||
#define SOC_DIRAM_DRAM_LOW 0x3FC88000
|
||||
#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000
|
||||
|
||||
// Region of memory accessible via DMA. See esp_ptr_dma_capable().
|
||||
#define SOC_DMA_LOW 0x3FC88000
|
||||
#define SOC_DMA_HIGH 0x3FD00000
|
||||
|
||||
// Region of memory that is byte-accessible. See esp_ptr_byte_accessible().
|
||||
#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000
|
||||
#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000
|
||||
|
||||
//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs
|
||||
//(excluding RTC data region, that's checked separately.) See esp_ptr_internal().
|
||||
#define SOC_MEM_INTERNAL_LOW 0x3FC88000
|
||||
#define SOC_MEM_INTERNAL_HIGH 0x403E2000
|
||||
|
||||
// Start (highest address) of ROM boot stack, only relevant during early boot
|
||||
#define SOC_ROM_STACK_START 0x3fcebf10
|
||||
|
||||
//interrupt cpu using table, Please see the core-isa.h
|
||||
/*************************************************************************************************************
|
||||
* Intr num Level Type PRO CPU usage APP CPU uasge
|
||||
* 0 1 extern level WMAC Reserved
|
||||
* 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA
|
||||
* 2 1 extern level
|
||||
* 3 1 extern level
|
||||
* 4 1 extern level WBB
|
||||
* 5 1 extern level BT/BLE Controller BT/BLE Controller
|
||||
* 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1)
|
||||
* 7 1 software BT/BLE VHCI BT/BLE VHCI
|
||||
* 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX)
|
||||
* 9 1 extern level
|
||||
* 10 1 extern edge
|
||||
* 11 3 profiling
|
||||
* 12 1 extern level
|
||||
* 13 1 extern level
|
||||
* 14 7 nmi Reserved Reserved
|
||||
* 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3)
|
||||
* 16 5 timer
|
||||
* 17 1 extern level
|
||||
* 18 1 extern level
|
||||
* 19 2 extern level
|
||||
* 20 2 extern level
|
||||
* 21 2 extern level
|
||||
* 22 3 extern edge
|
||||
* 23 3 extern level
|
||||
* 24 4 extern level TG1_WDT
|
||||
* 25 4 extern level CACHEERR
|
||||
* 26 5 extern level
|
||||
* 27 3 extern level Reserved Reserved
|
||||
* 28 4 extern edge DPORT ACCESS DPORT ACCESS
|
||||
* 29 3 software Reserved Reserved
|
||||
* 30 4 extern edge Reserved Reserved
|
||||
* 31 5 extern level
|
||||
*************************************************************************************************************
|
||||
*/
|
||||
|
||||
//CPU0 Interrupt number reserved, not touch this.
|
||||
#define ETS_WMAC_INUM 0
|
||||
#define ETS_BT_HOST_INUM 1
|
||||
#define ETS_WBB_INUM 4
|
||||
#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/
|
||||
#define ETS_FRC1_INUM 22
|
||||
#define ETS_T1_WDT_INUM 24
|
||||
#define ETS_CACHEERR_INUM 25
|
||||
#define ETS_DPORT_INUM 28
|
||||
|
||||
//CPU0 Interrupt number used in ROM, should be cancelled in SDK
|
||||
#define ETS_SLC_INUM 1
|
||||
#define ETS_UART0_INUM 5
|
||||
#define ETS_UART1_INUM 5
|
||||
#define ETS_SPI2_INUM 1
|
||||
//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here.
|
||||
#define ETS_FRC_TIMER2_INUM 10 /* use edge*/
|
||||
#define ETS_GPIO_INUM 4
|
||||
|
||||
//Other interrupt number should be managed by the user
|
||||
|
||||
//Invalid interrupt for number interrupt matrix
|
||||
#define ETS_INVALID_INUM 6
|
||||
8
components/soc/soc/esp32s3/include/soc/soc_caps.h
Normal file
8
components/soc/soc/esp32s3/include/soc/soc_caps.h
Normal file
|
|
@ -0,0 +1,8 @@
|
|||
// The long term plan is to have a single soc_caps.h for each peripheral.
|
||||
// During the refactoring and multichip support development process, we
|
||||
// seperate these information into periph_caps.h for each peripheral and
|
||||
// include them here.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define SOC_CPU_CORES_NUM 2
|
||||
45
components/soc/soc/esp32s3/include/soc/soc_ulp.h
Normal file
45
components/soc/soc/esp32s3/include/soc/soc_ulp.h
Normal file
|
|
@ -0,0 +1,45 @@
|
|||
// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
// This file contains various convenience macros to be used in ULP programs.
|
||||
|
||||
// Helper macros to calculate bit field width from mask, using the preprocessor.
|
||||
// Used later in READ_RTC_FIELD and WRITE_RTC_FIELD.
|
||||
#define IS_BIT_SET(m, i) (((m) >> (i)) & 1)
|
||||
#define MASK_TO_WIDTH_HELPER1(m, i) IS_BIT_SET(m, i)
|
||||
#define MASK_TO_WIDTH_HELPER2(m, i) (MASK_TO_WIDTH_HELPER1(m, i) + MASK_TO_WIDTH_HELPER1(m, i + 1))
|
||||
#define MASK_TO_WIDTH_HELPER4(m, i) (MASK_TO_WIDTH_HELPER2(m, i) + MASK_TO_WIDTH_HELPER2(m, i + 2))
|
||||
#define MASK_TO_WIDTH_HELPER8(m, i) (MASK_TO_WIDTH_HELPER4(m, i) + MASK_TO_WIDTH_HELPER4(m, i + 4))
|
||||
#define MASK_TO_WIDTH_HELPER16(m, i) (MASK_TO_WIDTH_HELPER8(m, i) + MASK_TO_WIDTH_HELPER8(m, i + 8))
|
||||
#define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16))
|
||||
|
||||
// Peripheral register access macros, build around REG_RD and REG_WR instructions.
|
||||
// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros.
|
||||
|
||||
// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16
|
||||
#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \
|
||||
REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit)
|
||||
|
||||
// Write immediate value into rtc_reg[low_bit + bit_width - 1 : low_bit], bit_width <= 8
|
||||
#define WRITE_RTC_REG(rtc_reg, low_bit, bit_width, value) \
|
||||
REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value) & 0xff)
|
||||
|
||||
// Read from a field in rtc_reg into R0, up to 16 bits
|
||||
#define READ_RTC_FIELD(rtc_reg, field) \
|
||||
READ_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER16(field ## _V, 0))
|
||||
|
||||
// Write immediate value into a field in rtc_reg, up to 8 bits
|
||||
#define WRITE_RTC_FIELD(rtc_reg, field, value) \
|
||||
WRITE_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER8(field ## _V, 0), ((value) & field ## _V))
|
||||
53
components/soc/soc/esp32s3/include/soc/spi_caps.h
Normal file
53
components/soc/soc/esp32s3/include/soc/spi_caps.h
Normal file
|
|
@ -0,0 +1,53 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define SOC_SPI_PERIPH_NUM 4
|
||||
#define SOC_SPI_DMA_CHAN_NUM 3
|
||||
#define SOC_SPI_PERIPH_CS_NUM(i) 3
|
||||
|
||||
#define SPI_FUNC_NUM 0
|
||||
#define SPI_IOMUX_PIN_NUM_HD 27
|
||||
#define SPI_IOMUX_PIN_NUM_CS 29
|
||||
#define SPI_IOMUX_PIN_NUM_MOSI 32
|
||||
#define SPI_IOMUX_PIN_NUM_CLK 30
|
||||
#define SPI_IOMUX_PIN_NUM_MISO 31
|
||||
#define SPI_IOMUX_PIN_NUM_WP 28
|
||||
//TODO: add the next slot
|
||||
|
||||
#define FSPI_FUNC_NUM 4
|
||||
#define FSPI_IOMUX_PIN_NUM_HD 9
|
||||
#define FSPI_IOMUX_PIN_NUM_CS 10
|
||||
#define FSPI_IOMUX_PIN_NUM_MOSI 11
|
||||
#define FSPI_IOMUX_PIN_NUM_CLK 12
|
||||
#define FSPI_IOMUX_PIN_NUM_MISO 13
|
||||
#define FSPI_IOMUX_PIN_NUM_WP 14
|
||||
//TODO: add the next slot
|
||||
|
||||
//HSPI and VSPI have no iomux pins
|
||||
|
||||
#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72
|
||||
|
||||
//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles
|
||||
#define SOC_SPI_SUPPORT_DDRCLK 1
|
||||
#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1
|
||||
#define SOC_SPI_SUPPORT_CD_SIG 1
|
||||
#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1
|
||||
|
||||
// Peripheral supports DIO, DOUT, QIO, or QOUT
|
||||
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3))
|
||||
|
||||
// Peripheral supports output given level during its "dummy phase"
|
||||
#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) ((void*)spi_dev == (void*)&SPIMEM1)
|
||||
1407
components/soc/soc/esp32s3/include/soc/spi_mem_reg.h
Normal file
1407
components/soc/soc/esp32s3/include/soc/spi_mem_reg.h
Normal file
File diff suppressed because it is too large
Load diff
646
components/soc/soc/esp32s3/include/soc/spi_mem_struct.h
Normal file
646
components/soc/soc/esp32s3/include/soc/spi_mem_struct.h
Normal file
|
|
@ -0,0 +1,646 @@
|
|||
// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
#pragma once
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
typedef volatile struct {
|
||||
uint32_t addr; /*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 3; /*reserved*/
|
||||
uint32_t fdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
|
||||
uint32_t fdout_oct: 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/
|
||||
uint32_t fdin_oct: 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/
|
||||
uint32_t faddr_oct: 1; /*Apply 8 signals during address phase 1:enable 0: disable*/
|
||||
uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/
|
||||
uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/
|
||||
uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable*/
|
||||
uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/
|
||||
uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/
|
||||
uint32_t reserved12: 1; /*reserved*/
|
||||
uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/
|
||||
uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/
|
||||
uint32_t reserved15: 3; /*reserved*/
|
||||
uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/
|
||||
uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/
|
||||
uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/
|
||||
uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/
|
||||
uint32_t reserved22: 1; /*reserved*/
|
||||
uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/
|
||||
uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/
|
||||
uint32_t reserved25: 7; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
|
||||
uint32_t reserved2: 30; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
|
||||
uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
|
||||
uint32_t ecc_cs_hold_time: 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/
|
||||
uint32_t ecc_skip_page_corner: 1; /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/
|
||||
uint32_t ecc_16to18_byte_en: 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/
|
||||
uint32_t reserved15: 10; /*reserved*/
|
||||
uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
|
||||
uint32_t sync_reset: 1; /*The FSM will be reset.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ctrl2;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/
|
||||
uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
|
||||
uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
|
||||
uint32_t reserved24: 7; /*reserved*/
|
||||
uint32_t clk_equ_sysclk: 1; /*Set this bit in 1-division mode.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 6; /*reserved*/
|
||||
uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
|
||||
uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
|
||||
uint32_t reserved8: 1; /*reserved*/
|
||||
uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/
|
||||
uint32_t reserved10: 16; /*reserved*/
|
||||
uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/
|
||||
uint32_t reserved27: 1; /*reserved*/
|
||||
uint32_t reserved28: 1; /*reserved*/
|
||||
uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/
|
||||
uint32_t reserved30: 1; /*reserved*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_dummy_cyclelen: 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/
|
||||
uint32_t reserved6: 20; /*reserved*/
|
||||
uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user1;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_command_value: 16; /*The value of command.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/
|
||||
};
|
||||
uint32_t val;
|
||||
} user2;
|
||||
uint32_t reserved_24;
|
||||
uint32_t reserved_28;
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 16; /*reserved*/
|
||||
uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/
|
||||
uint32_t reserved24: 8; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} rd_status;
|
||||
uint32_t ext_addr; /*The register are the higher 32bits in the 64 bits address mode.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t reserved0: 3; /*reserved*/
|
||||
uint32_t trans_end: 1; /*The bit is used to indicate the transimitting is done.*/
|
||||
uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/
|
||||
uint32_t reserved5: 2; /*reserved*/
|
||||
uint32_t fsub_pin: 1; /*For SPI0 flash is connected to SUBPINs.*/
|
||||
uint32_t ssub_pin: 1; /*For SPI0 sram is connected to SUBPINs.*/
|
||||
uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/
|
||||
uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/
|
||||
uint32_t reserved11: 21; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} misc;
|
||||
uint32_t tx_crc; /*For SPI1 the value of crc32.*/
|
||||
union {
|
||||
struct {
|
||||
uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/
|
||||
uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/
|
||||
uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/
|
||||
uint32_t fdin_dual: 1; /*For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
|
||||
uint32_t fdout_dual: 1; /*For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
|
||||
uint32_t faddr_dual: 1; /*For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/
|
||||
uint32_t fdin_quad: 1; /*For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
|
||||
uint32_t fdout_quad: 1; /*For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
|
||||
uint32_t faddr_quad: 1; /*For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_fctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_scmd_4byte: 1; /*For SPI0 In the spi sram mode cache read flash with 4 bytes command 1: enable 0:disable.*/
|
||||
uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/
|
||||
uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/
|
||||
uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/
|
||||
uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/
|
||||
uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/
|
||||
uint32_t sram_rdummy_cyclelen: 6; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved12: 2; /*reserved*/
|
||||
uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/
|
||||
uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/
|
||||
uint32_t sram_oct: 1; /*reserved*/
|
||||
uint32_t sram_wdummy_cyclelen: 6; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/
|
||||
uint32_t reserved28: 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} cache_sctrl;
|
||||
union {
|
||||
struct {
|
||||
uint32_t sclk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/
|
||||
uint32_t swb_mode: 8; /*Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode bit.*/
|
||||
uint32_t sdin_dual: 1; /*For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
|
||||
uint32_t sdout_dual: 1; /*For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
|
||||
uint32_t saddr_dual: 1; /*For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
|
||||
uint32_t scmd_dual: 1; /*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/
|
||||
uint32_t sdin_quad: 1; /*For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
|
||||
uint32_t sdout_quad: 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
|
||||
uint32_t saddr_quad: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
|
||||
uint32_t scmd_quad: 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/
|
||||
uint32_t sdin_oct: 1; /*For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/
|
||||
uint32_t sdout_oct: 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/
|
||||
uint32_t saddr_oct: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/
|
||||
uint32_t scmd_oct: 1; /*For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/
|
||||
uint32_t sdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/
|
||||
uint32_t reserved23: 9; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_drd_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/
|
||||
uint32_t reserved16: 12; /*reserved*/
|
||||
uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_dwr_cmd;
|
||||
union {
|
||||
struct {
|
||||
uint32_t cnt_l: 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/
|
||||
uint32_t cnt_h: 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/
|
||||
uint32_t cnt_n: 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/
|
||||
uint32_t reserved24: 7; /*reserved*/
|
||||
uint32_t equ_sysclk: 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/
|
||||
};
|
||||
uint32_t val;
|
||||
} sram_clk;
|
||||
union {
|
||||
struct {
|
||||
uint32_t st: 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/
|
||||
uint32_t reserved3: 29; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} fsm;
|
||||
uint32_t reserved_58;
|
||||
uint32_t reserved_5c;
|
||||
uint32_t reserved_60;
|
||||
uint32_t reserved_64;
|
||||
uint32_t reserved_68;
|
||||
uint32_t reserved_6c;
|
||||
uint32_t reserved_70;
|
||||
uint32_t reserved_74;
|
||||
uint32_t reserved_78;
|
||||
uint32_t reserved_7c;
|
||||
uint32_t reserved_80;
|
||||
uint32_t reserved_84;
|
||||
uint32_t reserved_88;
|
||||
uint32_t reserved_8c;
|
||||
uint32_t reserved_90;
|
||||
uint32_t reserved_94;
|
||||
uint32_t reserved_98;
|
||||
uint32_t reserved_9c;
|
||||
uint32_t reserved_a0;
|
||||
uint32_t reserved_a4;
|
||||
union {
|
||||
struct {
|
||||
uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/
|
||||
uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/
|
||||
uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} timing_cali;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
|
||||
uint32_t din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
|
||||
uint32_t din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
|
||||
uint32_t din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
|
||||
uint32_t dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/
|
||||
uint32_t reserved18: 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t dins_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t reserved18: 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} din_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t dout0_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t dout1_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t dout2_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t dout3_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t dout4_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
|
||||
uint32_t dout5_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
|
||||
uint32_t dout6_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
|
||||
uint32_t dout7_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
|
||||
uint32_t douts_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} dout_mode;
|
||||
uint32_t reserved_b8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_smem_timing_clk_ena: 1; /*For sram the bit is used to enable timing adjust clock for all reading operations.*/
|
||||
uint32_t spi_smem_timing_cali: 1; /*For sram the bit is used to enable timing auto-calibration for all reading operations.*/
|
||||
uint32_t spi_smem_extra_dummy_cyclelen: 3; /*For sram add extra dummy spi clock cycle length for spi clock calibration.*/
|
||||
uint32_t reserved5: 27;
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_timing_cali;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_smem_din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t reserved18: 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_din_mode;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_smem_din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/
|
||||
uint32_t spi_smem_dins_num: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/
|
||||
uint32_t reserved18: 14; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_din_num;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_smem_dout0_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dout1_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dout2_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dout3_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dout4_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dout5_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dout6_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_dout7_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t spi_smem_douts_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/
|
||||
uint32_t reserved9: 23; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_dout_mode;
|
||||
uint32_t reserved_cc;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_smem_cs_setup: 1; /*For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/
|
||||
uint32_t spi_smem_cs_hold: 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/
|
||||
uint32_t spi_smem_cs_setup_time: 5; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/
|
||||
uint32_t spi_smem_cs_hold_time: 5; /*For spi0 spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/
|
||||
uint32_t spi_smem_ecc_cs_hold_time: 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accessed external RAM.*/
|
||||
uint32_t spi_smem_ecc_skip_page_corner: 1; /*1: MSPI skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/
|
||||
uint32_t spi_smem_ecc_16to18_byte_en: 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/
|
||||
uint32_t reserved17: 8; /*reserved*/
|
||||
uint32_t spi_smem_cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_ac;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_fmem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/
|
||||
uint32_t spi_fmem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
|
||||
uint32_t spi_fmem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
|
||||
uint32_t spi_fmem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
|
||||
uint32_t spi_fmem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
|
||||
uint32_t spi_fmem_outminbytelen: 7; /*It is the minimum output data length in the panda device.*/
|
||||
uint32_t spi_fmem_tx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to flash.*/
|
||||
uint32_t spi_fmem_rx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to flash.*/
|
||||
uint32_t spi_fmem_usr_ddr_dqs_thd: 7; /*The delay number of data strobe which from memory based on SPI clock.*/
|
||||
uint32_t spi_fmem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/
|
||||
uint32_t spi_fmem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
|
||||
uint32_t spi_fmem_clk_diff_en: 1; /*Set this bit to enable the differential SPI_CLK#.*/
|
||||
uint32_t spi_fmem_hyperbus_mode: 1; /*Set this bit to enable the SPI HyperBus mode.*/
|
||||
uint32_t spi_fmem_dqs_ca_in: 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
|
||||
uint32_t spi_fmem_hyperbus_dummy_2x: 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/
|
||||
uint32_t spi_fmem_clk_diff_inv: 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/
|
||||
uint32_t spi_fmem_octa_ram_addr: 1; /*Set this bit to enable octa_ram address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/
|
||||
uint32_t spi_fmem_hyperbus_ca: 1; /*Set this bit to enable HyperRAM address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} ddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi_smem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/
|
||||
uint32_t spi_smem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/
|
||||
uint32_t spi_smem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/
|
||||
uint32_t spi_smem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/
|
||||
uint32_t spi_smem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/
|
||||
uint32_t spi_smem_outminbytelen: 7; /*It is the minimum output data length in the ddr psram.*/
|
||||
uint32_t spi_smem_tx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to external RAM.*/
|
||||
uint32_t spi_smem_rx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to external RAM.*/
|
||||
uint32_t spi_smem_usr_ddr_dqs_thd: 7; /*The delay number of data strobe which from memory based on SPI clock.*/
|
||||
uint32_t spi_smem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/
|
||||
uint32_t spi_smem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/
|
||||
uint32_t spi_smem_clk_diff_en: 1; /*Set this bit to enable the differential SPI_CLK#.*/
|
||||
uint32_t spi_smem_hyperbus_mode: 1; /*Set this bit to enable the SPI HyperBus mode.*/
|
||||
uint32_t spi_smem_dqs_ca_in: 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/
|
||||
uint32_t spi_smem_hyperbus_dummy_2x: 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/
|
||||
uint32_t spi_smem_clk_diff_inv: 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/
|
||||
uint32_t spi_smem_octa_ram_addr: 1; /*Set this bit to enable octa_ram address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/
|
||||
uint32_t spi_smem_hyperbus_ca: 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/
|
||||
uint32_t reserved31: 1; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} spi_smem_ddr;
|
||||
union {
|
||||
struct {
|
||||
uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/
|
||||
uint32_t reserved1: 31; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} clock_gate;
|
||||
union {
|
||||
struct {
|
||||
uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/
|
||||
uint32_t reserved2: 30; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} core_clk_sel;
|
||||
uint32_t reserved_e4;
|
||||
uint32_t reserved_e8;
|
||||
uint32_t reserved_ec;
|
||||
uint32_t reserved_f0;
|
||||
uint32_t reserved_f4;
|
||||
uint32_t reserved_f8;
|
||||
uint32_t reserved_fc;
|
||||
uint32_t reserved_100;
|
||||
uint32_t reserved_104;
|
||||
uint32_t reserved_108;
|
||||
uint32_t reserved_10c;
|
||||
uint32_t reserved_110;
|
||||
uint32_t reserved_114;
|
||||
uint32_t reserved_118;
|
||||
uint32_t reserved_11c;
|
||||
uint32_t reserved_120;
|
||||
uint32_t reserved_124;
|
||||
uint32_t reserved_128;
|
||||
uint32_t reserved_12c;
|
||||
uint32_t reserved_130;
|
||||
uint32_t reserved_134;
|
||||
uint32_t reserved_138;
|
||||
uint32_t reserved_13c;
|
||||
uint32_t reserved_140;
|
||||
uint32_t reserved_144;
|
||||
uint32_t reserved_148;
|
||||
uint32_t reserved_14c;
|
||||
uint32_t reserved_150;
|
||||
uint32_t reserved_154;
|
||||
uint32_t reserved_158;
|
||||
uint32_t reserved_15c;
|
||||
uint32_t reserved_160;
|
||||
uint32_t reserved_164;
|
||||
uint32_t reserved_168;
|
||||
uint32_t reserved_16c;
|
||||
uint32_t reserved_170;
|
||||
uint32_t reserved_174;
|
||||
uint32_t reserved_178;
|
||||
uint32_t reserved_17c;
|
||||
uint32_t reserved_180;
|
||||
uint32_t reserved_184;
|
||||
uint32_t reserved_188;
|
||||
uint32_t reserved_18c;
|
||||
uint32_t reserved_190;
|
||||
uint32_t reserved_194;
|
||||
uint32_t reserved_198;
|
||||
uint32_t reserved_19c;
|
||||
uint32_t reserved_1a0;
|
||||
uint32_t reserved_1a4;
|
||||
uint32_t reserved_1a8;
|
||||
uint32_t reserved_1ac;
|
||||
uint32_t reserved_1b0;
|
||||
uint32_t reserved_1b4;
|
||||
uint32_t reserved_1b8;
|
||||
uint32_t reserved_1bc;
|
||||
uint32_t reserved_1c0;
|
||||
uint32_t reserved_1c4;
|
||||
uint32_t reserved_1c8;
|
||||
uint32_t reserved_1cc;
|
||||
uint32_t reserved_1d0;
|
||||
uint32_t reserved_1d4;
|
||||
uint32_t reserved_1d8;
|
||||
uint32_t reserved_1dc;
|
||||
uint32_t reserved_1e0;
|
||||
uint32_t reserved_1e4;
|
||||
uint32_t reserved_1e8;
|
||||
uint32_t reserved_1ec;
|
||||
uint32_t reserved_1f0;
|
||||
uint32_t reserved_1f4;
|
||||
uint32_t reserved_1f8;
|
||||
uint32_t reserved_1fc;
|
||||
uint32_t reserved_200;
|
||||
uint32_t reserved_204;
|
||||
uint32_t reserved_208;
|
||||
uint32_t reserved_20c;
|
||||
uint32_t reserved_210;
|
||||
uint32_t reserved_214;
|
||||
uint32_t reserved_218;
|
||||
uint32_t reserved_21c;
|
||||
uint32_t reserved_220;
|
||||
uint32_t reserved_224;
|
||||
uint32_t reserved_228;
|
||||
uint32_t reserved_22c;
|
||||
uint32_t reserved_230;
|
||||
uint32_t reserved_234;
|
||||
uint32_t reserved_238;
|
||||
uint32_t reserved_23c;
|
||||
uint32_t reserved_240;
|
||||
uint32_t reserved_244;
|
||||
uint32_t reserved_248;
|
||||
uint32_t reserved_24c;
|
||||
uint32_t reserved_250;
|
||||
uint32_t reserved_254;
|
||||
uint32_t reserved_258;
|
||||
uint32_t reserved_25c;
|
||||
uint32_t reserved_260;
|
||||
uint32_t reserved_264;
|
||||
uint32_t reserved_268;
|
||||
uint32_t reserved_26c;
|
||||
uint32_t reserved_270;
|
||||
uint32_t reserved_274;
|
||||
uint32_t reserved_278;
|
||||
uint32_t reserved_27c;
|
||||
uint32_t reserved_280;
|
||||
uint32_t reserved_284;
|
||||
uint32_t reserved_288;
|
||||
uint32_t reserved_28c;
|
||||
uint32_t reserved_290;
|
||||
uint32_t reserved_294;
|
||||
uint32_t reserved_298;
|
||||
uint32_t reserved_29c;
|
||||
uint32_t reserved_2a0;
|
||||
uint32_t reserved_2a4;
|
||||
uint32_t reserved_2a8;
|
||||
uint32_t reserved_2ac;
|
||||
uint32_t reserved_2b0;
|
||||
uint32_t reserved_2b4;
|
||||
uint32_t reserved_2b8;
|
||||
uint32_t reserved_2bc;
|
||||
uint32_t reserved_2c0;
|
||||
uint32_t reserved_2c4;
|
||||
uint32_t reserved_2c8;
|
||||
uint32_t reserved_2cc;
|
||||
uint32_t reserved_2d0;
|
||||
uint32_t reserved_2d4;
|
||||
uint32_t reserved_2d8;
|
||||
uint32_t reserved_2dc;
|
||||
uint32_t reserved_2e0;
|
||||
uint32_t reserved_2e4;
|
||||
uint32_t reserved_2e8;
|
||||
uint32_t reserved_2ec;
|
||||
uint32_t reserved_2f0;
|
||||
uint32_t reserved_2f4;
|
||||
uint32_t reserved_2f8;
|
||||
uint32_t reserved_2fc;
|
||||
uint32_t reserved_300;
|
||||
uint32_t reserved_304;
|
||||
uint32_t reserved_308;
|
||||
uint32_t reserved_30c;
|
||||
uint32_t reserved_310;
|
||||
uint32_t reserved_314;
|
||||
uint32_t reserved_318;
|
||||
uint32_t reserved_31c;
|
||||
uint32_t reserved_320;
|
||||
uint32_t reserved_324;
|
||||
uint32_t reserved_328;
|
||||
uint32_t reserved_32c;
|
||||
uint32_t reserved_330;
|
||||
uint32_t reserved_334;
|
||||
uint32_t reserved_338;
|
||||
uint32_t reserved_33c;
|
||||
uint32_t reserved_340;
|
||||
uint32_t reserved_344;
|
||||
uint32_t reserved_348;
|
||||
uint32_t reserved_34c;
|
||||
uint32_t reserved_350;
|
||||
uint32_t reserved_354;
|
||||
uint32_t reserved_358;
|
||||
uint32_t reserved_35c;
|
||||
uint32_t reserved_360;
|
||||
uint32_t reserved_364;
|
||||
uint32_t reserved_368;
|
||||
uint32_t reserved_36c;
|
||||
uint32_t reserved_370;
|
||||
uint32_t reserved_374;
|
||||
uint32_t reserved_378;
|
||||
uint32_t reserved_37c;
|
||||
uint32_t reserved_380;
|
||||
uint32_t reserved_384;
|
||||
uint32_t reserved_388;
|
||||
uint32_t reserved_38c;
|
||||
uint32_t reserved_390;
|
||||
uint32_t reserved_394;
|
||||
uint32_t reserved_398;
|
||||
uint32_t reserved_39c;
|
||||
uint32_t reserved_3a0;
|
||||
uint32_t reserved_3a4;
|
||||
uint32_t reserved_3a8;
|
||||
uint32_t reserved_3ac;
|
||||
uint32_t reserved_3b0;
|
||||
uint32_t reserved_3b4;
|
||||
uint32_t reserved_3b8;
|
||||
uint32_t reserved_3bc;
|
||||
uint32_t reserved_3c0;
|
||||
uint32_t reserved_3c4;
|
||||
uint32_t reserved_3c8;
|
||||
uint32_t reserved_3cc;
|
||||
uint32_t reserved_3d0;
|
||||
uint32_t reserved_3d4;
|
||||
uint32_t reserved_3d8;
|
||||
uint32_t reserved_3dc;
|
||||
uint32_t reserved_3e0;
|
||||
uint32_t reserved_3e4;
|
||||
uint32_t reserved_3e8;
|
||||
uint32_t reserved_3ec;
|
||||
uint32_t reserved_3f0;
|
||||
uint32_t reserved_3f4;
|
||||
uint32_t reserved_3f8;
|
||||
union {
|
||||
struct {
|
||||
uint32_t date: 28; /*SPI register version.*/
|
||||
uint32_t reserved28: 4; /*reserved*/
|
||||
};
|
||||
uint32_t val;
|
||||
} date;
|
||||
} spi_mem_dev_t;
|
||||
|
||||
extern spi_mem_dev_t SPIMEM0;
|
||||
extern spi_mem_dev_t SPIMEM1;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
35
components/soc/soc/esp32s3/include/soc/spi_pins.h
Normal file
35
components/soc/soc/esp32s3/include/soc/spi_pins.h
Normal file
|
|
@ -0,0 +1,35 @@
|
|||
// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
|
||||
#pragma once
|
||||
|
||||
#define SPI_PERIPH_NUM 3
|
||||
|
||||
#define SPI_FUNC_NUM 2
|
||||
#define SPI_IOMUX_PIN_NUM_HD 27
|
||||
#define SPI_IOMUX_PIN_NUM_CS 29
|
||||
#define SPI_IOMUX_PIN_NUM_MOSI 32
|
||||
#define SPI_IOMUX_PIN_NUM_CLK 30
|
||||
#define SPI_IOMUX_PIN_NUM_MISO 31
|
||||
#define SPI_IOMUX_PIN_NUM_WP 28
|
||||
//TODO: add the next slot
|
||||
|
||||
#define FSPI_FUNC_NUM 0
|
||||
#define FSPI_IOMUX_PIN_NUM_HD 9
|
||||
#define FSPI_IOMUX_PIN_NUM_CS 10
|
||||
#define FSPI_IOMUX_PIN_NUM_MOSI 11
|
||||
#define FSPI_IOMUX_PIN_NUM_CLK 12
|
||||
#define FSPI_IOMUX_PIN_NUM_MISO 13
|
||||
#define FSPI_IOMUX_PIN_NUM_WP 14
|
||||
//TODO: add the next slot
|
||||
1588
components/soc/soc/esp32s3/include/soc/spi_reg.h
Normal file
1588
components/soc/soc/esp32s3/include/soc/spi_reg.h
Normal file
File diff suppressed because it is too large
Load diff
Some files were not shown because too many files have changed in this diff Show more
Loading…
Reference in a new issue