From 4857dc5e2b244537adf51fadcb48f7be2cabd2df Mon Sep 17 00:00:00 2001 From: morris Date: Thu, 18 Jun 2020 17:13:19 +0800 Subject: [PATCH] soc: add soc descriptions for esp32s3 --- components/soc/soc/esp32s3/CMakeLists.txt | 17 + components/soc/soc/esp32s3/adc_periph.c | 29 + components/soc/soc/esp32s3/dac_periph.c | 23 + components/soc/soc/esp32s3/gpio_periph.c | 117 + components/soc/soc/esp32s3/i2c_bbpll.h | 184 + components/soc/soc/esp32s3/i2c_periph.c | 38 + components/soc/soc/esp32s3/i2c_ulp.h | 39 + components/soc/soc/esp32s3/i2s_periph.c | 36 + .../soc/soc/esp32s3/include/soc/adc_caps.h | 44 + .../soc/soc/esp32s3/include/soc/adc_channel.h | 78 + .../soc/esp32s3/include/soc/apb_ctrl_reg.h | 546 + .../soc/esp32s3/include/soc/apb_ctrl_struct.h | 480 + .../soc/esp32s3/include/soc/apb_saradc_reg.h | 698 ++ .../esp32s3/include/soc/apb_saradc_struct.h | 521 + .../esp32s3/include/soc/assist_debug_reg.h | 1332 +++ .../esp32s3/include/soc/assist_debug_struct.h | 463 + .../soc/soc/esp32s3/include/soc/bb_reg.h | 37 + .../soc/soc/esp32s3/include/soc/boot_mode.h | 98 + .../soc/esp32s3/include/soc/brownout_caps.h | 25 + .../soc/esp32s3/include/soc/cache_memory.h | 103 + .../soc/esp32s3/include/soc/clkout_channel.h | 23 + components/soc/soc/esp32s3/include/soc/cpu.h | 131 + .../soc/soc/esp32s3/include/soc/cpu_caps.h | 20 + .../soc/soc/esp32s3/include/soc/dac_caps.h | 22 + .../soc/soc/esp32s3/include/soc/dac_channel.h | 24 + .../soc/soc/esp32s3/include/soc/dma_reg.h | 5168 +++++++++ .../soc/soc/esp32s3/include/soc/dma_struct.h | 1365 +++ .../soc/esp32s3/include/soc/dport_access.h | 109 + .../soc/soc/esp32s3/include/soc/dport_reg.h | 33 + .../soc/soc/esp32s3/include/soc/efuse_reg.h | 421 + .../soc/esp32s3/include/soc/efuse_struct.h | 294 + .../soc/soc/esp32s3/include/soc/extmem_reg.h | 1609 +++ .../soc/esp32s3/include/soc/extmem_struct.h | 780 ++ .../soc/soc/esp32s3/include/soc/fe_reg.h | 41 + .../soc/soc/esp32s3/include/soc/gpio_caps.h | 45 + .../soc/soc/esp32s3/include/soc/gpio_reg.h | 9216 +++++++++++++++++ .../soc/soc/esp32s3/include/soc/gpio_sd_reg.h | 166 + .../soc/esp32s3/include/soc/gpio_sd_struct.h | 59 + .../soc/esp32s3/include/soc/gpio_sig_map.h | 433 + .../soc/soc/esp32s3/include/soc/gpio_struct.h | 254 + .../soc/soc/esp32s3/include/soc/hinf_reg.h | 240 + .../soc/soc/esp32s3/include/soc/hinf_struct.h | 134 + .../soc/soc/esp32s3/include/soc/host_reg.h | 1798 ++++ .../soc/soc/esp32s3/include/soc/host_struct.h | 604 ++ .../soc/esp32s3/include/soc/hwcrypto_reg.h | 238 + .../soc/soc/esp32s3/include/soc/i2c_caps.h | 36 + .../soc/soc/esp32s3/include/soc/i2c_reg.h | 1070 ++ .../soc/soc/esp32s3/include/soc/i2c_struct.h | 340 + .../soc/soc/esp32s3/include/soc/i2s_caps.h | 28 + .../soc/soc/esp32s3/include/soc/i2s_reg.h | 971 ++ .../soc/soc/esp32s3/include/soc/i2s_struct.h | 318 + .../esp32s3/include/soc/interrupt_core0_reg.h | 784 ++ .../include/soc/interrupt_core0_struct.h | 1093 ++ .../esp32s3/include/soc/interrupt_core1_reg.h | 784 ++ .../include/soc/interrupt_core1_struct.h | 1605 +++ .../soc/esp32s3/include/soc/interrupt_reg.h | 17 + .../soc/soc/esp32s3/include/soc/io_mux_reg.h | 427 + .../soc/soc/esp32s3/include/soc/lcd_cam_reg.h | 840 ++ .../soc/esp32s3/include/soc/lcd_cam_struct.h | 300 + .../soc/soc/esp32s3/include/soc/ledc_caps.h | 24 + .../soc/soc/esp32s3/include/soc/ledc_reg.h | 1566 +++ .../soc/soc/esp32s3/include/soc/ledc_struct.h | 224 + .../soc/soc/esp32s3/include/soc/mcpwm_reg.h | 2902 ++++++ .../soc/esp32s3/include/soc/mcpwm_struct.h | 457 + .../soc/soc/esp32s3/include/soc/mpu_caps.h | 21 + .../soc/soc/esp32s3/include/soc/nrx_reg.h | 55 + .../soc/soc/esp32s3/include/soc/pcnt_caps.h | 26 + .../soc/soc/esp32s3/include/soc/pcnt_reg.h | 856 ++ .../soc/soc/esp32s3/include/soc/pcnt_struct.h | 179 + .../soc/soc/esp32s3/include/soc/periph_defs.h | 169 + .../soc/soc/esp32s3/include/soc/rmt_caps.h | 30 + .../soc/soc/esp32s3/include/soc/rmt_reg.h | 2120 ++++ .../soc/soc/esp32s3/include/soc/rmt_struct.h | 300 + components/soc/soc/esp32s3/include/soc/rtc.h | 819 ++ .../soc/esp32s3/include/soc/rtc_cntl_reg.h | 3588 +++++++ .../soc/esp32s3/include/soc/rtc_cntl_struct.h | 967 ++ .../esp32s3/include/soc/rtc_gpio_channel.h | 70 + .../soc/soc/esp32s3/include/soc/rtc_i2c_reg.h | 680 ++ .../soc/esp32s3/include/soc/rtc_i2c_struct.h | 229 + .../soc/soc/esp32s3/include/soc/rtc_io_caps.h | 18 + .../soc/esp32s3/include/soc/rtc_io_channel.h | 84 + .../soc/soc/esp32s3/include/soc/rtc_io_reg.h | 2292 ++++ .../soc/esp32s3/include/soc/rtc_io_struct.h | 354 + .../soc/soc/esp32s3/include/soc/sdmmc_reg.h | 94 + .../soc/esp32s3/include/soc/sdmmc_struct.h | 374 + .../soc/soc/esp32s3/include/soc/sens_reg.h | 1722 +++ .../soc/soc/esp32s3/include/soc/sens_struct.h | 506 + .../soc/esp32s3/include/soc/sensitive_reg.h | 4136 ++++++++ .../esp32s3/include/soc/sensitive_struct.h | 2281 ++++ .../soc/esp32s3/include/soc/sigmadelta_caps.h | 37 + .../soc/soc/esp32s3/include/soc/slc_reg.h | 1906 ++++ .../soc/soc/esp32s3/include/soc/slc_struct.h | 590 ++ components/soc/soc/esp32s3/include/soc/soc.h | 331 + .../soc/soc/esp32s3/include/soc/soc_caps.h | 8 + .../soc/soc/esp32s3/include/soc/soc_ulp.h | 45 + .../soc/soc/esp32s3/include/soc/spi_caps.h | 53 + .../soc/soc/esp32s3/include/soc/spi_mem_reg.h | 1407 +++ .../soc/esp32s3/include/soc/spi_mem_struct.h | 646 ++ .../soc/soc/esp32s3/include/soc/spi_pins.h | 35 + .../soc/soc/esp32s3/include/soc/spi_reg.h | 1588 +++ .../soc/soc/esp32s3/include/soc/spi_struct.h | 398 + .../soc/esp32s3/include/soc/sys_timer_reg.h | 420 + .../esp32s3/include/soc/sys_timer_struct.h | 253 + .../soc/soc/esp32s3/include/soc/syscon_reg.h | 548 + .../soc/esp32s3/include/soc/syscon_struct.h | 467 + .../soc/soc/esp32s3/include/soc/system_reg.h | 1062 ++ .../soc/esp32s3/include/soc/system_struct.h | 1364 +++ .../soc/esp32s3/include/soc/systimer_caps.h | 21 + .../esp32s3/include/soc/timer_group_caps.h | 17 + .../soc/esp32s3/include/soc/timer_group_reg.h | 508 + .../esp32s3/include/soc/timer_group_struct.h | 216 + .../soc/esp32s3/include/soc/touch_channel.h | 46 + .../esp32s3/include/soc/touch_sensor_caps.h | 33 + .../include/soc/touch_sensor_channel.h | 44 + .../soc/soc/esp32s3/include/soc/uart_caps.h | 32 + .../soc/esp32s3/include/soc/uart_channel.h | 58 + .../soc/soc/esp32s3/include/soc/uart_reg.h | 1180 +++ .../soc/soc/esp32s3/include/soc/uart_struct.h | 402 + .../soc/soc/esp32s3/include/soc/uhci_reg.h | 660 ++ .../soc/soc/esp32s3/include/soc/uhci_struct.h | 213 + .../soc/soc/esp32s3/include/soc/wdev_reg.h | 20 + components/soc/soc/esp32s3/interrupts.c | 87 + components/soc/soc/esp32s3/ledc_periph.c | 25 + components/soc/soc/esp32s3/rtc_io_periph.c | 93 + components/soc/soc/esp32s3/rtc_periph.c | 0 .../soc/soc/esp32s3/sdio_slave_periph.c | 42 + components/soc/soc/esp32s3/sdmmc_periph.c | 50 + components/soc/soc/esp32s3/spi_periph.c | 97 + .../soc/soc/esp32s3/touch_sensor_periph.c | 29 + components/soc/soc/esp32s3/uart_periph.c | 37 + 130 files changed, 78959 insertions(+) create mode 100644 components/soc/soc/esp32s3/CMakeLists.txt create mode 100644 components/soc/soc/esp32s3/adc_periph.c create mode 100644 components/soc/soc/esp32s3/dac_periph.c create mode 100644 components/soc/soc/esp32s3/gpio_periph.c create mode 100644 components/soc/soc/esp32s3/i2c_bbpll.h create mode 100644 components/soc/soc/esp32s3/i2c_periph.c create mode 100644 components/soc/soc/esp32s3/i2c_ulp.h create mode 100644 components/soc/soc/esp32s3/i2s_periph.c create mode 100644 components/soc/soc/esp32s3/include/soc/adc_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/adc_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/apb_ctrl_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/apb_ctrl_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/apb_saradc_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/apb_saradc_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/assist_debug_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/assist_debug_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/bb_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/boot_mode.h create mode 100644 components/soc/soc/esp32s3/include/soc/brownout_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/cache_memory.h create mode 100644 components/soc/soc/esp32s3/include/soc/clkout_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/cpu.h create mode 100644 components/soc/soc/esp32s3/include/soc/cpu_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/dac_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/dac_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/dma_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/dma_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/dport_access.h create mode 100644 components/soc/soc/esp32s3/include/soc/dport_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/efuse_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/efuse_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/extmem_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/extmem_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/fe_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/gpio_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/gpio_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/gpio_sd_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/gpio_sd_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/gpio_sig_map.h create mode 100644 components/soc/soc/esp32s3/include/soc/gpio_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/hinf_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/hinf_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/host_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/host_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/hwcrypto_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/i2c_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/i2c_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/i2c_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/i2s_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/i2s_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/i2s_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/interrupt_core0_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/interrupt_core0_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/interrupt_core1_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/interrupt_core1_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/interrupt_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/io_mux_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/lcd_cam_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/lcd_cam_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/ledc_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/ledc_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/ledc_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/mcpwm_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/mcpwm_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/mpu_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/nrx_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/pcnt_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/pcnt_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/pcnt_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/periph_defs.h create mode 100644 components/soc/soc/esp32s3/include/soc/rmt_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/rmt_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/rmt_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_cntl_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_cntl_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_gpio_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_i2c_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_i2c_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_io_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_io_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_io_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/rtc_io_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/sdmmc_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/sdmmc_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/sens_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/sens_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/sensitive_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/sensitive_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/slc_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/slc_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/soc.h create mode 100644 components/soc/soc/esp32s3/include/soc/soc_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/soc_ulp.h create mode 100644 components/soc/soc/esp32s3/include/soc/spi_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/spi_mem_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/spi_mem_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/spi_pins.h create mode 100644 components/soc/soc/esp32s3/include/soc/spi_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/spi_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/sys_timer_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/sys_timer_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/syscon_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/syscon_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/system_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/system_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/systimer_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/timer_group_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/timer_group_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/timer_group_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/touch_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/touch_sensor_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/uart_caps.h create mode 100644 components/soc/soc/esp32s3/include/soc/uart_channel.h create mode 100644 components/soc/soc/esp32s3/include/soc/uart_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/uart_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/uhci_reg.h create mode 100644 components/soc/soc/esp32s3/include/soc/uhci_struct.h create mode 100644 components/soc/soc/esp32s3/include/soc/wdev_reg.h create mode 100644 components/soc/soc/esp32s3/interrupts.c create mode 100644 components/soc/soc/esp32s3/ledc_periph.c create mode 100644 components/soc/soc/esp32s3/rtc_io_periph.c create mode 100644 components/soc/soc/esp32s3/rtc_periph.c create mode 100644 components/soc/soc/esp32s3/sdio_slave_periph.c create mode 100644 components/soc/soc/esp32s3/sdmmc_periph.c create mode 100644 components/soc/soc/esp32s3/spi_periph.c create mode 100644 components/soc/soc/esp32s3/touch_sensor_periph.c create mode 100644 components/soc/soc/esp32s3/uart_periph.c diff --git a/components/soc/soc/esp32s3/CMakeLists.txt b/components/soc/soc/esp32s3/CMakeLists.txt new file mode 100644 index 000000000..0d345201b --- /dev/null +++ b/components/soc/soc/esp32s3/CMakeLists.txt @@ -0,0 +1,17 @@ +add_library(soc_esp32s3 STATIC + "adc_periph.c" + "dac_periph.c" + "gpio_periph.c" + "i2c_periph.c" + "i2s_periph.c" + "interrupts.c" + "ledc_periph.c" + "rtc_io_periph.c" + "rtc_periph.c" + "sdio_slave_periph.c" + "sdmmc_periph.c" + "spi_periph.c" + "touch_sensor_periph.c" + "uart_periph.c") + +target_include_directories(soc_esp32s3 PUBLIC . include ../include) diff --git a/components/soc/soc/esp32s3/adc_periph.c b/components/soc/soc/esp32s3/adc_periph.c new file mode 100644 index 000000000..652cc7588 --- /dev/null +++ b/components/soc/soc/esp32s3/adc_periph.c @@ -0,0 +1,29 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/adc_periph.h" + +/* Store IO number corresponding to the ADC channel number. */ +const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = { + /* ADC1 */ + { + ADC1_CHANNEL_0_GPIO_NUM, ADC1_CHANNEL_1_GPIO_NUM, ADC1_CHANNEL_2_GPIO_NUM, ADC1_CHANNEL_3_GPIO_NUM, ADC1_CHANNEL_4_GPIO_NUM, + ADC1_CHANNEL_5_GPIO_NUM, ADC1_CHANNEL_6_GPIO_NUM, ADC1_CHANNEL_7_GPIO_NUM, -1, -1 + }, + /* ADC2 */ + { + ADC2_CHANNEL_0_GPIO_NUM, ADC2_CHANNEL_1_GPIO_NUM, ADC2_CHANNEL_2_GPIO_NUM, ADC2_CHANNEL_3_GPIO_NUM, ADC2_CHANNEL_4_GPIO_NUM, + ADC2_CHANNEL_5_GPIO_NUM, ADC2_CHANNEL_6_GPIO_NUM, ADC2_CHANNEL_7_GPIO_NUM, ADC2_CHANNEL_8_GPIO_NUM, ADC2_CHANNEL_9_GPIO_NUM + } +}; diff --git a/components/soc/soc/esp32s3/dac_periph.c b/components/soc/soc/esp32s3/dac_periph.c new file mode 100644 index 000000000..a55e33b5b --- /dev/null +++ b/components/soc/soc/esp32s3/dac_periph.c @@ -0,0 +1,23 @@ +// Copyright 2019 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/dac_periph.h" + +/* + Bunch of constants for DAC peripheral: GPIO number +*/ +const dac_signal_conn_t dac_periph_signal = { + .dac_channel_io_num[0] = DAC_CHANNEL_1_GPIO_NUM, + .dac_channel_io_num[1] = DAC_CHANNEL_2_GPIO_NUM, +}; \ No newline at end of file diff --git a/components/soc/soc/esp32s3/gpio_periph.c b/components/soc/soc/esp32s3/gpio_periph.c new file mode 100644 index 000000000..03ef9143b --- /dev/null +++ b/components/soc/soc/esp32s3/gpio_periph.c @@ -0,0 +1,117 @@ +// Copyright 2018 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/gpio_periph.h" + +const uint32_t GPIO_PIN_MUX_REG[GPIO_PIN_COUNT] = { + IO_MUX_GPIO0_REG, + IO_MUX_GPIO1_REG, + IO_MUX_GPIO2_REG, + IO_MUX_GPIO3_REG, + IO_MUX_GPIO4_REG, + IO_MUX_GPIO5_REG, + IO_MUX_GPIO6_REG, + IO_MUX_GPIO7_REG, + IO_MUX_GPIO8_REG, + IO_MUX_GPIO9_REG, + IO_MUX_GPIO10_REG, + IO_MUX_GPIO11_REG, + IO_MUX_GPIO12_REG, + IO_MUX_GPIO13_REG, + IO_MUX_GPIO14_REG, + IO_MUX_GPIO15_REG, + IO_MUX_GPIO16_REG, + IO_MUX_GPIO17_REG, + IO_MUX_GPIO18_REG, + IO_MUX_GPIO19_REG, + IO_MUX_GPIO20_REG, + IO_MUX_GPIO21_REG, + 0, + 0, + 0, + 0, + IO_MUX_GPIO26_REG, + IO_MUX_GPIO27_REG, + IO_MUX_GPIO28_REG, + IO_MUX_GPIO29_REG, + IO_MUX_GPIO30_REG, + IO_MUX_GPIO31_REG, + IO_MUX_GPIO32_REG, + IO_MUX_GPIO33_REG, + IO_MUX_GPIO34_REG, + IO_MUX_GPIO35_REG, + IO_MUX_GPIO36_REG, + IO_MUX_GPIO37_REG, + IO_MUX_GPIO38_REG, + IO_MUX_GPIO39_REG, + IO_MUX_GPIO40_REG, + IO_MUX_GPIO41_REG, + IO_MUX_GPIO42_REG, + IO_MUX_GPIO43_REG, + IO_MUX_GPIO44_REG, + IO_MUX_GPIO45_REG, + IO_MUX_GPIO46_REG, + 0, +}; + +const uint32_t GPIO_HOLD_MASK[GPIO_PIN_COUNT] = { + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + BIT(1), + BIT(2), + BIT(3), + BIT(4), + BIT(5), + BIT(6), + BIT(7), + BIT(8), + BIT(9), + BIT(10), + BIT(11), + BIT(12), + BIT(13), + BIT(14), + BIT(15), + BIT(16), + BIT(17), + BIT(18), + BIT(19), + BIT(20), + BIT(21), + BIT(22), + BIT(23), + BIT(24), + BIT(25), + BIT(26), +}; diff --git a/components/soc/soc/esp32s3/i2c_bbpll.h b/components/soc/soc/esp32s3/i2c_bbpll.h new file mode 100644 index 000000000..1f56a5f40 --- /dev/null +++ b/components/soc/soc/esp32s3/i2c_bbpll.h @@ -0,0 +1,184 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_apll.h + * @brief Register definitions for digital PLL (BBPLL) + * + * This file lists register fields of BBPLL, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * rtc_clk_cpu_freq_set function in rtc_clk.c. + */ + +#define I2C_BBPLL 0x66 +#define I2C_BBPLL_HOSTID 1 + +#define I2C_BBPLL_IR_CAL_DELAY 0 +#define I2C_BBPLL_IR_CAL_DELAY_MSB 3 +#define I2C_BBPLL_IR_CAL_DELAY_LSB 0 + +#define I2C_BBPLL_IR_CAL_CK_DIV 0 +#define I2C_BBPLL_IR_CAL_CK_DIV_MSB 7 +#define I2C_BBPLL_IR_CAL_CK_DIV_LSB 4 + +#define I2C_BBPLL_IR_CAL_EXT_CAP 1 +#define I2C_BBPLL_IR_CAL_EXT_CAP_MSB 3 +#define I2C_BBPLL_IR_CAL_EXT_CAP_LSB 0 + +#define I2C_BBPLL_IR_CAL_ENX_CAP 1 +#define I2C_BBPLL_IR_CAL_ENX_CAP_MSB 4 +#define I2C_BBPLL_IR_CAL_ENX_CAP_LSB 4 + +#define I2C_BBPLL_IR_CAL_RSTB 1 +#define I2C_BBPLL_IR_CAL_RSTB_MSB 5 +#define I2C_BBPLL_IR_CAL_RSTB_LSB 5 + +#define I2C_BBPLL_IR_CAL_START 1 +#define I2C_BBPLL_IR_CAL_START_MSB 6 +#define I2C_BBPLL_IR_CAL_START_LSB 6 + +#define I2C_BBPLL_IR_CAL_UNSTOP 1 +#define I2C_BBPLL_IR_CAL_UNSTOP_MSB 7 +#define I2C_BBPLL_IR_CAL_UNSTOP_LSB 7 + +#define I2C_BBPLL_OC_REF_DIV 2 +#define I2C_BBPLL_OC_REF_DIV_MSB 3 +#define I2C_BBPLL_OC_REF_DIV_LSB 0 + +#define I2C_BBPLL_OC_DCHGP 2 +#define I2C_BBPLL_OC_DCHGP_MSB 6 +#define I2C_BBPLL_OC_DCHGP_LSB 4 + +#define I2C_BBPLL_OC_ENB_FCAL 2 +#define I2C_BBPLL_OC_ENB_FCAL_MSB 7 +#define I2C_BBPLL_OC_ENB_FCAL_LSB 7 + +#define I2C_BBPLL_OC_DIV_7_0 3 +#define I2C_BBPLL_OC_DIV_7_0_MSB 7 +#define I2C_BBPLL_OC_DIV_7_0_LSB 0 + +#define I2C_BBPLL_RSTB_DIV_ADC 4 +#define I2C_BBPLL_RSTB_DIV_ADC_MSB 0 +#define I2C_BBPLL_RSTB_DIV_ADC_LSB 0 + +#define I2C_BBPLL_MODE_HF 4 +#define I2C_BBPLL_MODE_HF_MSB 1 +#define I2C_BBPLL_MODE_HF_LSB 1 + +#define I2C_BBPLL_DIV_ADC 4 +#define I2C_BBPLL_DIV_ADC_MSB 3 +#define I2C_BBPLL_DIV_ADC_LSB 2 + +#define I2C_BBPLL_DIV_DAC 4 +#define I2C_BBPLL_DIV_DAC_MSB 4 +#define I2C_BBPLL_DIV_DAC_LSB 4 + +#define I2C_BBPLL_DIV_CPU 4 +#define I2C_BBPLL_DIV_CPU_MSB 5 +#define I2C_BBPLL_DIV_CPU_LSB 5 + +#define I2C_BBPLL_OC_ENB_VCON 4 +#define I2C_BBPLL_OC_ENB_VCON_MSB 6 +#define I2C_BBPLL_OC_ENB_VCON_LSB 6 + +#define I2C_BBPLL_OC_TSCHGP 4 +#define I2C_BBPLL_OC_TSCHGP_MSB 7 +#define I2C_BBPLL_OC_TSCHGP_LSB 7 + +#define I2C_BBPLL_OC_DR1 5 +#define I2C_BBPLL_OC_DR1_MSB 2 +#define I2C_BBPLL_OC_DR1_LSB 0 + +#define I2C_BBPLL_OC_DR3 5 +#define I2C_BBPLL_OC_DR3_MSB 6 +#define I2C_BBPLL_OC_DR3_LSB 4 + +#define I2C_BBPLL_EN_USB 5 +#define I2C_BBPLL_EN_USB_MSB 7 +#define I2C_BBPLL_EN_USB_LSB 7 + +#define I2C_BBPLL_OC_DCUR 6 +#define I2C_BBPLL_OC_DCUR_MSB 2 +#define I2C_BBPLL_OC_DCUR_LSB 0 + +#define I2C_BBPLL_INC_CUR 6 +#define I2C_BBPLL_INC_CUR_MSB 3 +#define I2C_BBPLL_INC_CUR_LSB 3 + +#define I2C_BBPLL_OC_DHREF_SEL 6 +#define I2C_BBPLL_OC_DHREF_SEL_MSB 5 +#define I2C_BBPLL_OC_DHREF_SEL_LSB 4 + +#define I2C_BBPLL_OC_DLREF_SEL 6 +#define I2C_BBPLL_OC_DLREF_SEL_MSB 7 +#define I2C_BBPLL_OC_DLREF_SEL_LSB 6 + +#define I2C_BBPLL_OR_CAL_CAP 8 +#define I2C_BBPLL_OR_CAL_CAP_MSB 3 +#define I2C_BBPLL_OR_CAL_CAP_LSB 0 + +#define I2C_BBPLL_OR_CAL_UDF 8 +#define I2C_BBPLL_OR_CAL_UDF_MSB 4 +#define I2C_BBPLL_OR_CAL_UDF_LSB 4 + +#define I2C_BBPLL_OR_CAL_OVF 8 +#define I2C_BBPLL_OR_CAL_OVF_MSB 5 +#define I2C_BBPLL_OR_CAL_OVF_LSB 5 + +#define I2C_BBPLL_OR_CAL_END 8 +#define I2C_BBPLL_OR_CAL_END_MSB 6 +#define I2C_BBPLL_OR_CAL_END_LSB 6 + +#define I2C_BBPLL_OR_LOCK 8 +#define I2C_BBPLL_OR_LOCK_MSB 7 +#define I2C_BBPLL_OR_LOCK_LSB 7 + +#define I2C_BBPLL_BBADC_DELAY1 9 +#define I2C_BBPLL_BBADC_DELAY1_MSB 1 +#define I2C_BBPLL_BBADC_DELAY1_LSB 0 + +#define I2C_BBPLL_BBADC_DELAY2 9 +#define I2C_BBPLL_BBADC_DELAY2_MSB 3 +#define I2C_BBPLL_BBADC_DELAY2_LSB 2 + +#define I2C_BBPLL_BBADC_DVDD 9 +#define I2C_BBPLL_BBADC_DVDD_MSB 5 +#define I2C_BBPLL_BBADC_DVDD_LSB 4 + +#define I2C_BBPLL_BBADC_DREF 9 +#define I2C_BBPLL_BBADC_DREF_MSB 7 +#define I2C_BBPLL_BBADC_DREF_LSB 6 + +#define I2C_BBPLL_BBADC_DCUR 10 +#define I2C_BBPLL_BBADC_DCUR_MSB 1 +#define I2C_BBPLL_BBADC_DCUR_LSB 0 + +#define I2C_BBPLL_BBADC_INPUT_SHORT 10 +#define I2C_BBPLL_BBADC_INPUT_SHORT_MSB 2 +#define I2C_BBPLL_BBADC_INPUT_SHORT_LSB 2 + +#define I2C_BBPLL_ENT_PLL 10 +#define I2C_BBPLL_ENT_PLL_MSB 3 +#define I2C_BBPLL_ENT_PLL_LSB 3 + +#define I2C_BBPLL_DTEST 10 +#define I2C_BBPLL_DTEST_MSB 5 +#define I2C_BBPLL_DTEST_LSB 4 + +#define I2C_BBPLL_ENT_ADC 10 +#define I2C_BBPLL_ENT_ADC_MSB 7 +#define I2C_BBPLL_ENT_ADC_LSB 6 + diff --git a/components/soc/soc/esp32s3/i2c_periph.c b/components/soc/soc/esp32s3/i2c_periph.c new file mode 100644 index 000000000..3003dc5cb --- /dev/null +++ b/components/soc/soc/esp32s3/i2c_periph.c @@ -0,0 +1,38 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/i2c_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2C peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2c_signal_conn_t i2c_periph_signal[SOC_I2C_NUM] = { + { + .sda_out_sig = I2CEXT0_SDA_OUT_IDX, + .sda_in_sig = I2CEXT0_SDA_IN_IDX, + .scl_out_sig = I2CEXT0_SCL_OUT_IDX, + .scl_in_sig = I2CEXT0_SCL_IN_IDX, + .irq = ETS_I2C_EXT0_INTR_SOURCE, + .module = PERIPH_I2C0_MODULE, + }, + { + .sda_out_sig = I2CEXT1_SDA_OUT_IDX, + .sda_in_sig = I2CEXT1_SDA_IN_IDX, + .scl_out_sig = I2CEXT1_SCL_OUT_IDX, + .scl_in_sig = I2CEXT1_SCL_IN_IDX, + .irq = ETS_I2C_EXT1_INTR_SOURCE, + .module = PERIPH_I2C1_MODULE, + }, +}; \ No newline at end of file diff --git a/components/soc/soc/esp32s3/i2c_ulp.h b/components/soc/soc/esp32s3/i2c_ulp.h new file mode 100644 index 000000000..bf60672c9 --- /dev/null +++ b/components/soc/soc/esp32s3/i2c_ulp.h @@ -0,0 +1,39 @@ +// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/** + * @file i2c_ulp.h + * @brief Register definitions for analog to calibrate o_code for getting a more precise voltage. + * + * This file lists register fields of ULP, located on an internal configuration + * bus. These definitions are used via macros defined in i2c_rtc_clk.h, by + * rtc_init function in rtc_init.c. + */ + +#define I2C_ULP 0x61 +#define I2C_ULP_HOSTID 1 + +#define I2C_ULP_IR_RESETB 0 +#define I2C_ULP_IR_RESETB_MSB 0 +#define I2C_ULP_IR_RESETB_LSB 0 + +#define I2C_ULP_O_DONE_FLAG 3 +#define I2C_ULP_O_DONE_FLAG_MSB 0 +#define I2C_ULP_O_DONE_FLAG_LSB 0 + +#define I2C_ULP_BG_O_DONE_FLAG 3 +#define I2C_ULP_BG_O_DONE_FLAG_MSB 3 +#define I2C_ULP_BG_O_DONE_FLAG_LSB 3 diff --git a/components/soc/soc/esp32s3/i2s_periph.c b/components/soc/soc/esp32s3/i2s_periph.c new file mode 100644 index 000000000..52f714edf --- /dev/null +++ b/components/soc/soc/esp32s3/i2s_periph.c @@ -0,0 +1,36 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/i2s_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every I2S peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const i2s_signal_conn_t i2s_periph_signal[SOC_I2S_NUM] = { + { + .o_bck_in_sig = I2S0O_BCK_IN_IDX, + .o_ws_in_sig = I2S0O_WS_IN_IDX, + .o_bck_out_sig = I2S0O_BCK_OUT_IDX, + .o_ws_out_sig = I2S0O_WS_OUT_IDX, + .o_data_out_sig = I2S0O_SD_OUT_IDX, + .i_bck_in_sig = I2S0I_BCK_OUT_IDX, + .i_ws_in_sig = I2S0I_WS_OUT_IDX, + .i_bck_out_sig = I2S0I_BCK_IN_IDX, + .i_ws_out_sig = I2S0I_WS_IN_IDX, + .i_data_in_sig = I2S0I_SD_IN_IDX, + .irq = ETS_I2S0_INTR_SOURCE, + .module = PERIPH_I2S0_MODULE, + } +}; diff --git a/components/soc/soc/esp32s3/include/soc/adc_caps.h b/components/soc/soc/esp32s3/include/soc/adc_caps.h new file mode 100644 index 000000000..c622fb3c9 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/adc_caps.h @@ -0,0 +1,44 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#define SOC_ADC_PERIPH_NUM (2) +#define SOC_ADC_PATT_LEN_MAX (16) + +#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (10) +#define SOC_ADC_MAX_CHANNEL_NUM (10) + +#define SOC_ADC1_DATA_INVERT_DEFAULT (0) +#define SOC_ADC2_DATA_INVERT_DEFAULT (0) + +#define SOC_ADC_DIGI_DATA_INVERT_DEFAULT(PERIPH_NUM) (0) + +#define SOC_ADC_FSM_RSTB_WAIT_DEFAULT (8) +#define SOC_ADC_FSM_START_WAIT_DEFAULT (5) +#define SOC_ADC_FSM_STANDBY_WAIT_DEFAULT (100) +#define ADC_FSM_SAMPLE_CYCLE_DEFAULT (2) + +/** + * Check if adc support digital controller (DMA) mode. + * @value + * - 1 : support; + * - 0 : not support; + */ +#define SOC_ADC_SUPPORT_DMA_MODE(PERIPH_NUM) ((PERIPH_NUM==0)? 1: 1) + +#define SOC_ADC_PWDET_CCT_DEFAULT (4) + +#define SOC_ADC_SAR_CLK_DIV_DEFAULT(PERIPH_NUM) ((PERIPH_NUM==0)? 2 : 1) + +#define SOC_ADC_DIGI_SAR_CLK_DIV_DEFAULT (1) \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/adc_channel.h b/components/soc/soc/esp32s3/include/soc/adc_channel.h new file mode 100644 index 000000000..f15ac9cb7 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/adc_channel.h @@ -0,0 +1,78 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_ADC_CHANNEL_H +#define _SOC_ADC_CHANNEL_H + +#define ADC1_GPIO1_CHANNEL ADC1_CHANNEL_0 +#define ADC1_CHANNEL_0_GPIO_NUM 1 + +#define ADC1_GPIO2_CHANNEL ADC1_CHANNEL_1 +#define ADC1_CHANNEL_1_GPIO_NUM 2 + +#define ADC1_GPIO3_CHANNEL ADC1_CHANNEL_2 +#define ADC1_CHANNEL_2_GPIO_NUM 3 + +#define ADC1_GPIO4_CHANNEL ADC1_CHANNEL_3 +#define ADC1_CHANNEL_3_GPIO_NUM 4 + +#define ADC1_GPIO5_CHANNEL ADC1_CHANNEL_4 +#define ADC1_CHANNEL_4_GPIO_NUM 5 + +#define ADC1_GPIO6_CHANNEL ADC1_CHANNEL_5 +#define ADC1_CHANNEL_5_GPIO_NUM 6 + +#define ADC1_GPIO7_CHANNEL ADC1_CHANNEL_6 +#define ADC1_CHANNEL_6_GPIO_NUM 7 + +#define ADC1_GPIO8_CHANNEL ADC1_CHANNEL_7 +#define ADC1_CHANNEL_7_GPIO_NUM 8 + +#define ADC1_GPIO9_CHANNEL ADC1_CHANNEL_8 +#define ADC1_CHANNEL_8_GPIO_NUM 9 + +#define ADC1_GPIO10_CHANNEL ADC1_CHANNEL_9 +#define ADC1_CHANNEL_9_GPIO_NUM 10 + +#define ADC2_GPIO11_CHANNEL ADC2_CHANNEL_0 +#define ADC2_CHANNEL_0_GPIO_NUM 11 + +#define ADC2_GPIO12_CHANNEL ADC2_CHANNEL_1 +#define ADC2_CHANNEL_1_GPIO_NUM 12 + +#define ADC2_GPIO13_CHANNEL ADC2_CHANNEL_2 +#define ADC2_CHANNEL_2_GPIO_NUM 13 + +#define ADC2_GPIO14_CHANNEL ADC2_CHANNEL_3 +#define ADC2_CHANNEL_3_GPIO_NUM 14 + +#define ADC2_GPIO15_CHANNEL ADC2_CHANNEL_4 +#define ADC2_CHANNEL_4_GPIO_NUM 15 + +#define ADC2_GPIO16_CHANNEL ADC2_CHANNEL_5 +#define ADC2_CHANNEL_5_GPIO_NUM 16 + +#define ADC2_GPIO17_CHANNEL ADC2_CHANNEL_6 +#define ADC2_CHANNEL_6_GPIO_NUM 17 + +#define ADC2_GPIO18_CHANNEL ADC2_CHANNEL_7 +#define ADC2_CHANNEL_7_GPIO_NUM 18 + +#define ADC2_GPIO19_CHANNEL ADC2_CHANNEL_8 +#define ADC2_CHANNEL_8_GPIO_NUM 19 + +#define ADC2_GPIO20_CHANNEL ADC2_CHANNEL_9 +#define ADC2_CHANNEL_9_GPIO_NUM 20 + +#endif diff --git a/components/soc/soc/esp32s3/include/soc/apb_ctrl_reg.h b/components/soc/soc/esp32s3/include/soc/apb_ctrl_reg.h new file mode 100644 index 000000000..0c3e7e0cd --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/apb_ctrl_reg.h @@ -0,0 +1,546 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define APB_CTRL_SYSCLK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x000) +/* APB_CTRL_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_RST_TICK_CNT (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_M (BIT(12)) +#define APB_CTRL_RST_TICK_CNT_V 0x1 +#define APB_CTRL_RST_TICK_CNT_S 12 +/* APB_CTRL_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_EN (BIT(11)) +#define APB_CTRL_CLK_EN_M (BIT(11)) +#define APB_CTRL_CLK_EN_V 0x1 +#define APB_CTRL_CLK_EN_S 11 +/* APB_CTRL_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_EN (BIT(10)) +#define APB_CTRL_CLK_320M_EN_M (BIT(10)) +#define APB_CTRL_CLK_320M_EN_V 0x1 +#define APB_CTRL_CLK_320M_EN_S 10 +/* APB_CTRL_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define APB_CTRL_PRE_DIV_CNT 0x000003FF +#define APB_CTRL_PRE_DIV_CNT_M ((APB_CTRL_PRE_DIV_CNT_V) << (APB_CTRL_PRE_DIV_CNT_S)) +#define APB_CTRL_PRE_DIV_CNT_V 0x3FF +#define APB_CTRL_PRE_DIV_CNT_S 0 + +#define APB_CTRL_TICK_CONF_REG (DR_REG_APB_CTRL_BASE + 0x004) +/* APB_CTRL_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: */ +#define APB_CTRL_TICK_ENABLE (BIT(16)) +#define APB_CTRL_TICK_ENABLE_M (BIT(16)) +#define APB_CTRL_TICK_ENABLE_V 0x1 +#define APB_CTRL_TICK_ENABLE_S 16 +/* APB_CTRL_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ +/*description: */ +#define APB_CTRL_CK8M_TICK_NUM 0x000000FF +#define APB_CTRL_CK8M_TICK_NUM_M ((APB_CTRL_CK8M_TICK_NUM_V) << (APB_CTRL_CK8M_TICK_NUM_S)) +#define APB_CTRL_CK8M_TICK_NUM_V 0xFF +#define APB_CTRL_CK8M_TICK_NUM_S 8 +/* APB_CTRL_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define APB_CTRL_XTAL_TICK_NUM 0x000000FF +#define APB_CTRL_XTAL_TICK_NUM_M ((APB_CTRL_XTAL_TICK_NUM_V) << (APB_CTRL_XTAL_TICK_NUM_S)) +#define APB_CTRL_XTAL_TICK_NUM_V 0xFF +#define APB_CTRL_XTAL_TICK_NUM_S 0 + +#define APB_CTRL_CLK_OUT_EN_REG (DR_REG_APB_CTRL_BASE + 0x008) +/* APB_CTRL_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_XTAL_OEN (BIT(10)) +#define APB_CTRL_CLK_XTAL_OEN_M (BIT(10)) +#define APB_CTRL_CLK_XTAL_OEN_V 0x1 +#define APB_CTRL_CLK_XTAL_OEN_S 10 +/* APB_CTRL_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK40X_BB_OEN (BIT(9)) +#define APB_CTRL_CLK40X_BB_OEN_M (BIT(9)) +#define APB_CTRL_CLK40X_BB_OEN_V 0x1 +#define APB_CTRL_CLK40X_BB_OEN_S 9 +/* APB_CTRL_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_DAC_CPU_OEN (BIT(8)) +#define APB_CTRL_CLK_DAC_CPU_OEN_M (BIT(8)) +#define APB_CTRL_CLK_DAC_CPU_OEN_V 0x1 +#define APB_CTRL_CLK_DAC_CPU_OEN_S 8 +/* APB_CTRL_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_ADC_INF_OEN (BIT(7)) +#define APB_CTRL_CLK_ADC_INF_OEN_M (BIT(7)) +#define APB_CTRL_CLK_ADC_INF_OEN_V 0x1 +#define APB_CTRL_CLK_ADC_INF_OEN_S 7 +/* APB_CTRL_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_320M_OEN (BIT(6)) +#define APB_CTRL_CLK_320M_OEN_M (BIT(6)) +#define APB_CTRL_CLK_320M_OEN_V 0x1 +#define APB_CTRL_CLK_320M_OEN_S 6 +/* APB_CTRL_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK160_OEN (BIT(5)) +#define APB_CTRL_CLK160_OEN_M (BIT(5)) +#define APB_CTRL_CLK160_OEN_V 0x1 +#define APB_CTRL_CLK160_OEN_S 5 +/* APB_CTRL_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK80_OEN (BIT(4)) +#define APB_CTRL_CLK80_OEN_M (BIT(4)) +#define APB_CTRL_CLK80_OEN_V 0x1 +#define APB_CTRL_CLK80_OEN_S 4 +/* APB_CTRL_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK_BB_OEN (BIT(3)) +#define APB_CTRL_CLK_BB_OEN_M (BIT(3)) +#define APB_CTRL_CLK_BB_OEN_V 0x1 +#define APB_CTRL_CLK_BB_OEN_S 3 +/* APB_CTRL_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK44_OEN (BIT(2)) +#define APB_CTRL_CLK44_OEN_M (BIT(2)) +#define APB_CTRL_CLK44_OEN_V 0x1 +#define APB_CTRL_CLK44_OEN_S 2 +/* APB_CTRL_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK22_OEN (BIT(1)) +#define APB_CTRL_CLK22_OEN_M (BIT(1)) +#define APB_CTRL_CLK22_OEN_V 0x1 +#define APB_CTRL_CLK22_OEN_S 1 +/* APB_CTRL_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_CLK20_OEN (BIT(0)) +#define APB_CTRL_CLK20_OEN_M (BIT(0)) +#define APB_CTRL_CLK20_OEN_V 0x1 +#define APB_CTRL_CLK20_OEN_S 0 + +#define APB_CTRL_WIFI_BB_CFG_REG (DR_REG_APB_CTRL_BASE + 0x00C) +/* APB_CTRL_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_WIFI_BB_CFG 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_M ((APB_CTRL_WIFI_BB_CFG_V) << (APB_CTRL_WIFI_BB_CFG_S)) +#define APB_CTRL_WIFI_BB_CFG_V 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_S 0 + +#define APB_CTRL_WIFI_BB_CFG_2_REG (DR_REG_APB_CTRL_BASE + 0x010) +/* APB_CTRL_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_WIFI_BB_CFG_2 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_2_M ((APB_CTRL_WIFI_BB_CFG_2_V) << (APB_CTRL_WIFI_BB_CFG_2_S)) +#define APB_CTRL_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define APB_CTRL_WIFI_BB_CFG_2_S 0 + +#define APB_CTRL_WIFI_CLK_EN_REG (DR_REG_APB_CTRL_BASE + 0x014) +/* APB_CTRL_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define APB_CTRL_WIFI_CLK_EN 0xFFFFFFFF +#define APB_CTRL_WIFI_CLK_EN_M ((APB_CTRL_WIFI_CLK_EN_V) << (APB_CTRL_WIFI_CLK_EN_S)) +#define APB_CTRL_WIFI_CLK_EN_V 0xFFFFFFFF +#define APB_CTRL_WIFI_CLK_EN_S 0 + +#define APB_CTRL_WIFI_RST_EN_REG (DR_REG_APB_CTRL_BASE + 0x018) +/* APB_CTRL_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_WIFI_RST 0xFFFFFFFF +#define APB_CTRL_WIFI_RST_M ((APB_CTRL_WIFI_RST_V) << (APB_CTRL_WIFI_RST_S)) +#define APB_CTRL_WIFI_RST_V 0xFFFFFFFF +#define APB_CTRL_WIFI_RST_S 0 + +#define APB_CTRL_HOST_INF_SEL_REG (DR_REG_APB_CTRL_BASE + 0x01C) +/* APB_CTRL_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define APB_CTRL_PERI_IO_SWAP 0x000000FF +#define APB_CTRL_PERI_IO_SWAP_M ((APB_CTRL_PERI_IO_SWAP_V) << (APB_CTRL_PERI_IO_SWAP_S)) +#define APB_CTRL_PERI_IO_SWAP_V 0xFF +#define APB_CTRL_PERI_IO_SWAP_S 0 + +#define APB_CTRL_EXT_MEM_PMS_LOCK_REG (DR_REG_APB_CTRL_BASE + 0x020) +/* APB_CTRL_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_EXT_MEM_PMS_LOCK (BIT(0)) +#define APB_CTRL_EXT_MEM_PMS_LOCK_M (BIT(0)) +#define APB_CTRL_EXT_MEM_PMS_LOCK_V 0x1 +#define APB_CTRL_EXT_MEM_PMS_LOCK_S 0 + +#define APB_CTRL_EXT_MEM_WRITEBACK_BYPASS_REG (DR_REG_APB_CTRL_BASE + 0x024) +/* APB_CTRL_WRITEBACK_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set 1 to bypass cache writeback request to external memory so + that spi will not check its attribute.*/ +#define APB_CTRL_WRITEBACK_BYPASS (BIT(0)) +#define APB_CTRL_WRITEBACK_BYPASS_M (BIT(0)) +#define APB_CTRL_WRITEBACK_BYPASS_V 0x1 +#define APB_CTRL_WRITEBACK_BYPASS_S 0 + +#define APB_CTRL_FLASH_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x028) +/* APB_CTRL_FLASH_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE0_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE0_ATTR_M ((APB_CTRL_FLASH_ACE0_ATTR_V) << (APB_CTRL_FLASH_ACE0_ATTR_S)) +#define APB_CTRL_FLASH_ACE0_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE0_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x02C) +/* APB_CTRL_FLASH_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE1_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE1_ATTR_M ((APB_CTRL_FLASH_ACE1_ATTR_V) << (APB_CTRL_FLASH_ACE1_ATTR_S)) +#define APB_CTRL_FLASH_ACE1_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE1_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x030) +/* APB_CTRL_FLASH_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE2_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE2_ATTR_M ((APB_CTRL_FLASH_ACE2_ATTR_V) << (APB_CTRL_FLASH_ACE2_ATTR_S)) +#define APB_CTRL_FLASH_ACE2_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE2_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x034) +/* APB_CTRL_FLASH_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE3_ATTR 0x000001FF +#define APB_CTRL_FLASH_ACE3_ATTR_M ((APB_CTRL_FLASH_ACE3_ATTR_V) << (APB_CTRL_FLASH_ACE3_ATTR_S)) +#define APB_CTRL_FLASH_ACE3_ATTR_V 0x1FF +#define APB_CTRL_FLASH_ACE3_ATTR_S 0 + +#define APB_CTRL_FLASH_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x038) +/* APB_CTRL_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE0_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE0_ADDR_S_M ((APB_CTRL_FLASH_ACE0_ADDR_S_V) << (APB_CTRL_FLASH_ACE0_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE0_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x03C) +/* APB_CTRL_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE1_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE1_ADDR_S_M ((APB_CTRL_FLASH_ACE1_ADDR_S_V) << (APB_CTRL_FLASH_ACE1_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE1_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x040) +/* APB_CTRL_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE2_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE2_ADDR_S_M ((APB_CTRL_FLASH_ACE2_ADDR_S_V) << (APB_CTRL_FLASH_ACE2_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE2_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x044) +/* APB_CTRL_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE3_ADDR_S 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE3_ADDR_S_M ((APB_CTRL_FLASH_ACE3_ADDR_S_V) << (APB_CTRL_FLASH_ACE3_ADDR_S_S)) +#define APB_CTRL_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_FLASH_ACE3_ADDR_S_S 0 + +#define APB_CTRL_FLASH_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x048) +/* APB_CTRL_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE0_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE0_SIZE_M ((APB_CTRL_FLASH_ACE0_SIZE_V) << (APB_CTRL_FLASH_ACE0_SIZE_S)) +#define APB_CTRL_FLASH_ACE0_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE0_SIZE_S 0 + +#define APB_CTRL_FLASH_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x04C) +/* APB_CTRL_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE1_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE1_SIZE_M ((APB_CTRL_FLASH_ACE1_SIZE_V) << (APB_CTRL_FLASH_ACE1_SIZE_S)) +#define APB_CTRL_FLASH_ACE1_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE1_SIZE_S 0 + +#define APB_CTRL_FLASH_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x050) +/* APB_CTRL_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE2_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE2_SIZE_M ((APB_CTRL_FLASH_ACE2_SIZE_V) << (APB_CTRL_FLASH_ACE2_SIZE_S)) +#define APB_CTRL_FLASH_ACE2_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE2_SIZE_S 0 + +#define APB_CTRL_FLASH_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x054) +/* APB_CTRL_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_FLASH_ACE3_SIZE 0x0000FFFF +#define APB_CTRL_FLASH_ACE3_SIZE_M ((APB_CTRL_FLASH_ACE3_SIZE_V) << (APB_CTRL_FLASH_ACE3_SIZE_S)) +#define APB_CTRL_FLASH_ACE3_SIZE_V 0xFFFF +#define APB_CTRL_FLASH_ACE3_SIZE_S 0 + +#define APB_CTRL_SRAM_ACE0_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x058) +/* APB_CTRL_SRAM_ACE0_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE0_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE0_ATTR_M ((APB_CTRL_SRAM_ACE0_ATTR_V) << (APB_CTRL_SRAM_ACE0_ATTR_S)) +#define APB_CTRL_SRAM_ACE0_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE0_ATTR_S 0 + +#define APB_CTRL_SRAM_ACE1_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x05C) +/* APB_CTRL_SRAM_ACE1_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE1_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE1_ATTR_M ((APB_CTRL_SRAM_ACE1_ATTR_V) << (APB_CTRL_SRAM_ACE1_ATTR_S)) +#define APB_CTRL_SRAM_ACE1_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE1_ATTR_S 0 + +#define APB_CTRL_SRAM_ACE2_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x060) +/* APB_CTRL_SRAM_ACE2_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE2_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE2_ATTR_M ((APB_CTRL_SRAM_ACE2_ATTR_V) << (APB_CTRL_SRAM_ACE2_ATTR_S)) +#define APB_CTRL_SRAM_ACE2_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE2_ATTR_S 0 + +#define APB_CTRL_SRAM_ACE3_ATTR_REG (DR_REG_APB_CTRL_BASE + 0x064) +/* APB_CTRL_SRAM_ACE3_ATTR : R/W ;bitpos:[8:0] ;default: 9'hff ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE3_ATTR 0x000001FF +#define APB_CTRL_SRAM_ACE3_ATTR_M ((APB_CTRL_SRAM_ACE3_ATTR_V) << (APB_CTRL_SRAM_ACE3_ATTR_S)) +#define APB_CTRL_SRAM_ACE3_ATTR_V 0x1FF +#define APB_CTRL_SRAM_ACE3_ATTR_S 0 + +#define APB_CTRL_SRAM_ACE0_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x068) +/* APB_CTRL_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE0_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE0_ADDR_S_M ((APB_CTRL_SRAM_ACE0_ADDR_S_V) << (APB_CTRL_SRAM_ACE0_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE0_ADDR_S_S 0 + +#define APB_CTRL_SRAM_ACE1_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x06C) +/* APB_CTRL_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE1_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE1_ADDR_S_M ((APB_CTRL_SRAM_ACE1_ADDR_S_V) << (APB_CTRL_SRAM_ACE1_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE1_ADDR_S_S 0 + +#define APB_CTRL_SRAM_ACE2_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x070) +/* APB_CTRL_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE2_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE2_ADDR_S_M ((APB_CTRL_SRAM_ACE2_ADDR_S_V) << (APB_CTRL_SRAM_ACE2_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE2_ADDR_S_S 0 + +#define APB_CTRL_SRAM_ACE3_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x074) +/* APB_CTRL_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE3_ADDR_S 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE3_ADDR_S_M ((APB_CTRL_SRAM_ACE3_ADDR_S_V) << (APB_CTRL_SRAM_ACE3_ADDR_S_S)) +#define APB_CTRL_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF +#define APB_CTRL_SRAM_ACE3_ADDR_S_S 0 + +#define APB_CTRL_SRAM_ACE0_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x078) +/* APB_CTRL_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE0_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE0_SIZE_M ((APB_CTRL_SRAM_ACE0_SIZE_V) << (APB_CTRL_SRAM_ACE0_SIZE_S)) +#define APB_CTRL_SRAM_ACE0_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE0_SIZE_S 0 + +#define APB_CTRL_SRAM_ACE1_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x07C) +/* APB_CTRL_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE1_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE1_SIZE_M ((APB_CTRL_SRAM_ACE1_SIZE_V) << (APB_CTRL_SRAM_ACE1_SIZE_S)) +#define APB_CTRL_SRAM_ACE1_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE1_SIZE_S 0 + +#define APB_CTRL_SRAM_ACE2_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x080) +/* APB_CTRL_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE2_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE2_SIZE_M ((APB_CTRL_SRAM_ACE2_SIZE_V) << (APB_CTRL_SRAM_ACE2_SIZE_S)) +#define APB_CTRL_SRAM_ACE2_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE2_SIZE_S 0 + +#define APB_CTRL_SRAM_ACE3_SIZE_REG (DR_REG_APB_CTRL_BASE + 0x084) +/* APB_CTRL_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define APB_CTRL_SRAM_ACE3_SIZE 0x0000FFFF +#define APB_CTRL_SRAM_ACE3_SIZE_M ((APB_CTRL_SRAM_ACE3_SIZE_V) << (APB_CTRL_SRAM_ACE3_SIZE_S)) +#define APB_CTRL_SRAM_ACE3_SIZE_V 0xFFFF +#define APB_CTRL_SRAM_ACE3_SIZE_S 0 + +#define APB_CTRL_SPI_MEM_PMS_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x088) +/* APB_CTRL_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_CDE 0x0000001F +#define APB_CTRL_SPI_MEM_REJECT_CDE_M ((APB_CTRL_SPI_MEM_REJECT_CDE_V) << (APB_CTRL_SPI_MEM_REJECT_CDE_S)) +#define APB_CTRL_SPI_MEM_REJECT_CDE_V 0x1F +#define APB_CTRL_SPI_MEM_REJECT_CDE_S 2 +/* APB_CTRL_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_CLR (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define APB_CTRL_SPI_MEM_REJECT_CLR_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_CLR_S 1 +/* APB_CTRL_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_INT (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_M (BIT(0)) +#define APB_CTRL_SPI_MEM_REJECT_INT_V 0x1 +#define APB_CTRL_SPI_MEM_REJECT_INT_S 0 + +#define APB_CTRL_SPI_MEM_REJECT_ADDR_REG (DR_REG_APB_CTRL_BASE + 0x08C) +/* APB_CTRL_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define APB_CTRL_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_M ((APB_CTRL_SPI_MEM_REJECT_ADDR_V) << (APB_CTRL_SPI_MEM_REJECT_ADDR_S)) +#define APB_CTRL_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define APB_CTRL_SPI_MEM_REJECT_ADDR_S 0 + +#define APB_CTRL_SDIO_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x090) +/* APB_CTRL_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define APB_CTRL_SDIO_WIN_ACCESS_EN (BIT(0)) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_M (BIT(0)) +#define APB_CTRL_SDIO_WIN_ACCESS_EN_V 0x1 +#define APB_CTRL_SDIO_WIN_ACCESS_EN_S 0 + +#define APB_CTRL_REDCY_SIG0_REG (DR_REG_APB_CTRL_BASE + 0x094) +/* APB_CTRL_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_ANDOR (BIT(31)) +#define APB_CTRL_REDCY_ANDOR_M (BIT(31)) +#define APB_CTRL_REDCY_ANDOR_V 0x1 +#define APB_CTRL_REDCY_ANDOR_S 31 +/* APB_CTRL_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_SIG0 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG0_M ((APB_CTRL_REDCY_SIG0_V) << (APB_CTRL_REDCY_SIG0_S)) +#define APB_CTRL_REDCY_SIG0_V 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG0_S 0 + +#define APB_CTRL_REDCY_SIG1_REG (DR_REG_APB_CTRL_BASE + 0x098) +/* APB_CTRL_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_NANDOR (BIT(31)) +#define APB_CTRL_REDCY_NANDOR_M (BIT(31)) +#define APB_CTRL_REDCY_NANDOR_V 0x1 +#define APB_CTRL_REDCY_NANDOR_S 31 +/* APB_CTRL_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define APB_CTRL_REDCY_SIG1 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG1_M ((APB_CTRL_REDCY_SIG1_V) << (APB_CTRL_REDCY_SIG1_S)) +#define APB_CTRL_REDCY_SIG1_V 0x7FFFFFFF +#define APB_CTRL_REDCY_SIG1_S 0 + +#define APB_CTRL_FRONT_END_MEM_PD_REG (DR_REG_APB_CTRL_BASE + 0x09C) +/* APB_CTRL_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_DC_MEM_FORCE_PD (BIT(5)) +#define APB_CTRL_DC_MEM_FORCE_PD_M (BIT(5)) +#define APB_CTRL_DC_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_DC_MEM_FORCE_PD_S 5 +/* APB_CTRL_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_DC_MEM_FORCE_PU (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_M (BIT(4)) +#define APB_CTRL_DC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_DC_MEM_FORCE_PU_S 4 +/* APB_CTRL_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_PBUS_MEM_FORCE_PD (BIT(3)) +#define APB_CTRL_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define APB_CTRL_PBUS_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_PBUS_MEM_FORCE_PD_S 3 +/* APB_CTRL_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_PBUS_MEM_FORCE_PU (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define APB_CTRL_PBUS_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_PBUS_MEM_FORCE_PU_S 2 +/* APB_CTRL_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define APB_CTRL_AGC_MEM_FORCE_PD (BIT(1)) +#define APB_CTRL_AGC_MEM_FORCE_PD_M (BIT(1)) +#define APB_CTRL_AGC_MEM_FORCE_PD_V 0x1 +#define APB_CTRL_AGC_MEM_FORCE_PD_S 1 +/* APB_CTRL_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define APB_CTRL_AGC_MEM_FORCE_PU (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_M (BIT(0)) +#define APB_CTRL_AGC_MEM_FORCE_PU_V 0x1 +#define APB_CTRL_AGC_MEM_FORCE_PU_S 0 + +#define APB_CTRL_SPI_MEM_ECC_CTRL_REG (DR_REG_APB_CTRL_BASE + 0x0A0) +/* APB_CTRL_SRAM_PAGE_SIZE : R/W ;bitpos:[21:20] ;default: 2'd2 ; */ +/*description: Set the page size of the used MSPI external RAM. 0: 256 bytes. + 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ +#define APB_CTRL_SRAM_PAGE_SIZE 0x00000003 +#define APB_CTRL_SRAM_PAGE_SIZE_M ((APB_CTRL_SRAM_PAGE_SIZE_V) << (APB_CTRL_SRAM_PAGE_SIZE_S)) +#define APB_CTRL_SRAM_PAGE_SIZE_V 0x3 +#define APB_CTRL_SRAM_PAGE_SIZE_S 20 +/* APB_CTRL_FLASH_PAGE_SIZE : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 + bytes. 2: 1024 bytes. 3: 2048 bytes.*/ +#define APB_CTRL_FLASH_PAGE_SIZE 0x00000003 +#define APB_CTRL_FLASH_PAGE_SIZE_M ((APB_CTRL_FLASH_PAGE_SIZE_V) << (APB_CTRL_FLASH_PAGE_SIZE_S)) +#define APB_CTRL_FLASH_PAGE_SIZE_V 0x3 +#define APB_CTRL_FLASH_PAGE_SIZE_S 18 +/* APB_CTRL_ECC_ERR_INT_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to enable MSPI interrupt when the error times of + MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/ +#define APB_CTRL_ECC_ERR_INT_EN (BIT(17)) +#define APB_CTRL_ECC_ERR_INT_EN_M (BIT(17)) +#define APB_CTRL_ECC_ERR_INT_EN_V 0x1 +#define APB_CTRL_ECC_ERR_INT_EN_S 17 +/* APB_CTRL_ECC_ERR_INT_NUM : R/W ;bitpos:[16:9] ;default: 8'd10 ; */ +/*description: Set the error times of MSPI ECC read to generate MSPI interrupt.*/ +#define APB_CTRL_ECC_ERR_INT_NUM 0x000000FF +#define APB_CTRL_ECC_ERR_INT_NUM_M ((APB_CTRL_ECC_ERR_INT_NUM_V) << (APB_CTRL_ECC_ERR_INT_NUM_S)) +#define APB_CTRL_ECC_ERR_INT_NUM_V 0xFF +#define APB_CTRL_ECC_ERR_INT_NUM_S 9 +/* APB_CTRL_ECC_ERR_CNT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/ +#define APB_CTRL_ECC_ERR_CNT_CLR (BIT(8)) +#define APB_CTRL_ECC_ERR_CNT_CLR_M (BIT(8)) +#define APB_CTRL_ECC_ERR_CNT_CLR_V 0x1 +#define APB_CTRL_ECC_ERR_CNT_CLR_S 8 +/* APB_CTRL_ECC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: This bits show the error times of MSPI ECC read.*/ +#define APB_CTRL_ECC_ERR_CNT 0x000000FF +#define APB_CTRL_ECC_ERR_CNT_M ((APB_CTRL_ECC_ERR_CNT_V) << (APB_CTRL_ECC_ERR_CNT_S)) +#define APB_CTRL_ECC_ERR_CNT_V 0xFF +#define APB_CTRL_ECC_ERR_CNT_S 0 + +#define APB_CTRL_SPI_MEM_ECC_ERR_AADR_REG (DR_REG_APB_CTRL_BASE + 0x0A4) +/* APB_CTRL_ECC_ERR_ADDR : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: This bits show the latest MSPI ECC error address.*/ +#define APB_CTRL_ECC_ERR_ADDR 0xFFFFFFFF +#define APB_CTRL_ECC_ERR_ADDR_M ((APB_CTRL_ECC_ERR_ADDR_V) << (APB_CTRL_ECC_ERR_ADDR_S)) +#define APB_CTRL_ECC_ERR_ADDR_V 0xFFFFFFFF +#define APB_CTRL_ECC_ERR_ADDR_S 0 + +#define APB_CTRL_DATE_REG (DR_REG_APB_CTRL_BASE + 0x3FC) +/* APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h20032301 ; */ +/*description: Version control*/ +#define APB_CTRL_DATE 0xFFFFFFFF +#define APB_CTRL_DATE_M ((APB_CTRL_DATE_V) << (APB_CTRL_DATE_S)) +#define APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_CTRL_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/apb_ctrl_struct.h b/components/soc/soc/esp32s3/include/soc/apb_ctrl_struct.h new file mode 100644 index 000000000..6d2cb0b7e --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/apb_ctrl_struct.h @@ -0,0 +1,480 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t pre_div: 10; + uint32_t clk_320m_en: 1; + uint32_t clk_en: 1; + uint32_t rst_tick: 1; + uint32_t reserved13: 19; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t xtal_tick: 8; + uint32_t ck8m_tick: 8; + uint32_t tick_enable: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } tick_conf; + union { + struct { + uint32_t clk20_oen: 1; + uint32_t clk22_oen: 1; + uint32_t clk44_oen: 1; + uint32_t clk_bb_oen: 1; + uint32_t clk80_oen: 1; + uint32_t clk160_oen: 1; + uint32_t clk_320m_oen: 1; + uint32_t clk_adc_inf_oen: 1; + uint32_t clk_dac_cpu_oen: 1; + uint32_t clk40x_bb_oen: 1; + uint32_t clk_xtal_oen: 1; + uint32_t reserved11: 21; + }; + uint32_t val; + } clk_out_en; + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t wifi_clk_en; /**/ + uint32_t wifi_rst_en; /**/ + union { + struct { + uint32_t peri_io_swap: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } host_inf_sel; + union { + struct { + uint32_t ext_mem_pms_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } ext_mem_pms_lock; + union { + struct { + uint32_t writeback_bypass: 1; /*Set 1 to bypass cache writeback request to external memory so that spi will not check its attribute.*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } ext_mem_writeback_bypass; + union { + struct { + uint32_t flash_ace0_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } flash_ace0_attr; + union { + struct { + uint32_t flash_ace1_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } flash_ace1_attr; + union { + struct { + uint32_t flash_ace2_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } flash_ace2_attr; + union { + struct { + uint32_t flash_ace3_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } flash_ace3_attr; + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ + union { + struct { + uint32_t flash_ace0_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace0_size; + union { + struct { + uint32_t flash_ace1_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace1_size; + union { + struct { + uint32_t flash_ace2_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace2_size; + union { + struct { + uint32_t flash_ace3_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace3_size; + union { + struct { + uint32_t sram_ace0_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } sram_ace0_attr; + union { + struct { + uint32_t sram_ace1_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } sram_ace1_attr; + union { + struct { + uint32_t sram_ace2_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } sram_ace2_attr; + union { + struct { + uint32_t sram_ace3_attr: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } sram_ace3_attr; + uint32_t sram_ace0_addr; /**/ + uint32_t sram_ace1_addr; /**/ + uint32_t sram_ace2_addr; /**/ + uint32_t sram_ace3_addr; /**/ + union { + struct { + uint32_t sram_ace0_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace0_size; + union { + struct { + uint32_t sram_ace1_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace1_size; + union { + struct { + uint32_t sram_ace2_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace2_size; + union { + struct { + uint32_t sram_ace3_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace3_size; + union { + struct { + uint32_t spi_mem_reject_int: 1; + uint32_t spi_mem_reject_clr: 1; + uint32_t spi_mem_reject_cde: 5; + uint32_t reserved7: 25; + }; + uint32_t val; + } spi_mem_pms_ctrl; + uint32_t spi_mem_reject_addr; /**/ + union { + struct { + uint32_t sdio_win_access_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } sdio_ctrl; + union { + struct { + uint32_t redcy_sig0: 31; + uint32_t redcy_andor: 1; + }; + uint32_t val; + } redcy_sig0; + union { + struct { + uint32_t redcy_sig1: 31; + uint32_t redcy_nandor: 1; + }; + uint32_t val; + } redcy_sig1; + union { + struct { + uint32_t agc_mem_force_pu: 1; + uint32_t agc_mem_force_pd: 1; + uint32_t pbus_mem_force_pu: 1; + uint32_t pbus_mem_force_pd: 1; + uint32_t dc_mem_force_pu: 1; + uint32_t dc_mem_force_pd: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } front_end_mem_pd; + union { + struct { + uint32_t ecc_err: 8; /*This bits show the error times of MSPI ECC read.*/ + uint32_t ecc_err_clr: 1; /*Set this bit to clear APB_CTRL_ECC_ERR_ADDR.*/ + uint32_t ecc_err_int_num: 8; /*Set the error times of MSPI ECC read to generate MSPI interrupt.*/ + uint32_t ecc_err_int_en: 1; /*Set this bit to enable MSPI interrupt when the error times of MSPI ECC read is bigger than APB_CTRL_ECC_ERR_INT_NUM.*/ + uint32_t flash_page_size: 2; /*Set the page size of the used MSPI flash. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t sram_page_size: 2; /*Set the page size of the used MSPI external RAM. 0: 256 bytes. 1: 512 bytes. 2: 1024 bytes. 3: 2048 bytes.*/ + uint32_t reserved22: 10; /*reserved*/ + }; + uint32_t val; + } spi_mem_ecc_ctrl; + uint32_t spi_mem_ecc_err_aadr; /*This bits show the latest MSPI ECC error address.*/ + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t date; /*Version control*/ +} apb_ctrl_dev_t; + +extern apb_ctrl_dev_t APB_CTRL; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/apb_saradc_reg.h b/components/soc/soc/esp32s3/include/soc/apb_saradc_reg.h new file mode 100644 index 000000000..4ffc30fe4 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/apb_saradc_reg.h @@ -0,0 +1,698 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define APB_SARADC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x000) +/* APB_SARADC_WAIT_ARB_CYCLE : R/W ;bitpos:[31:30] ;default: 2'd1 ; */ +/*description: wait arbit signal stable after sar_done*/ +#define APB_SARADC_WAIT_ARB_CYCLE 0x00000003 +#define APB_SARADC_WAIT_ARB_CYCLE_M ((APB_SARADC_WAIT_ARB_CYCLE_V) << (APB_SARADC_WAIT_ARB_CYCLE_S)) +#define APB_SARADC_WAIT_ARB_CYCLE_V 0x3 +#define APB_SARADC_WAIT_ARB_CYCLE_S 30 +/* APB_SARADC_XPD_SAR_FORCE : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: force option to xpd sar blocks*/ +#define APB_SARADC_XPD_SAR_FORCE 0x00000003 +#define APB_SARADC_XPD_SAR_FORCE_M ((APB_SARADC_XPD_SAR_FORCE_V) << (APB_SARADC_XPD_SAR_FORCE_S)) +#define APB_SARADC_XPD_SAR_FORCE_V 0x3 +#define APB_SARADC_XPD_SAR_FORCE_S 27 +/* APB_SARADC_DATA_TO_I2S : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: I2S input data is from SAR ADC (for DMA) 0: I2S input data + is from GPIO matrix*/ +#define APB_SARADC_DATA_TO_I2S (BIT(26)) +#define APB_SARADC_DATA_TO_I2S_M (BIT(26)) +#define APB_SARADC_DATA_TO_I2S_V 0x1 +#define APB_SARADC_DATA_TO_I2S_S 26 +/* APB_SARADC_DATA_SAR_SEL : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: sar_sel will be coded by the MSB of the 16-bit output data + in this case the resolution should not be larger than 11 bits.*/ +#define APB_SARADC_DATA_SAR_SEL (BIT(25)) +#define APB_SARADC_DATA_SAR_SEL_M (BIT(25)) +#define APB_SARADC_DATA_SAR_SEL_V 0x1 +#define APB_SARADC_DATA_SAR_SEL_S 25 +/* APB_SARADC_SAR2_PATT_P_CLEAR : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC2 CTRL*/ +#define APB_SARADC_SAR2_PATT_P_CLEAR (BIT(24)) +#define APB_SARADC_SAR2_PATT_P_CLEAR_M (BIT(24)) +#define APB_SARADC_SAR2_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR2_PATT_P_CLEAR_S 24 +/* APB_SARADC_SAR1_PATT_P_CLEAR : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear the pointer of pattern table for DIG ADC1 CTRL*/ +#define APB_SARADC_SAR1_PATT_P_CLEAR (BIT(23)) +#define APB_SARADC_SAR1_PATT_P_CLEAR_M (BIT(23)) +#define APB_SARADC_SAR1_PATT_P_CLEAR_V 0x1 +#define APB_SARADC_SAR1_PATT_P_CLEAR_S 23 +/* APB_SARADC_SAR2_PATT_LEN : R/W ;bitpos:[22:19] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_SARADC_SAR2_PATT_LEN 0x0000000F +#define APB_SARADC_SAR2_PATT_LEN_M ((APB_SARADC_SAR2_PATT_LEN_V) << (APB_SARADC_SAR2_PATT_LEN_S)) +#define APB_SARADC_SAR2_PATT_LEN_V 0xF +#define APB_SARADC_SAR2_PATT_LEN_S 19 +/* APB_SARADC_SAR1_PATT_LEN : R/W ;bitpos:[18:15] ;default: 4'd15 ; */ +/*description: 0 ~ 15 means length 1 ~ 16*/ +#define APB_SARADC_SAR1_PATT_LEN 0x0000000F +#define APB_SARADC_SAR1_PATT_LEN_M ((APB_SARADC_SAR1_PATT_LEN_V) << (APB_SARADC_SAR1_PATT_LEN_S)) +#define APB_SARADC_SAR1_PATT_LEN_V 0xF +#define APB_SARADC_SAR1_PATT_LEN_S 15 +/* APB_SARADC_SAR_CLK_DIV : R/W ;bitpos:[14:7] ;default: 8'd4 ; */ +/*description: SAR clock divider*/ +#define APB_SARADC_SAR_CLK_DIV 0x000000FF +#define APB_SARADC_SAR_CLK_DIV_M ((APB_SARADC_SAR_CLK_DIV_V) << (APB_SARADC_SAR_CLK_DIV_S)) +#define APB_SARADC_SAR_CLK_DIV_V 0xFF +#define APB_SARADC_SAR_CLK_DIV_S 7 +/* APB_SARADC_SAR_CLK_GATED : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define APB_SARADC_SAR_CLK_GATED (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_M (BIT(6)) +#define APB_SARADC_SAR_CLK_GATED_V 0x1 +#define APB_SARADC_SAR_CLK_GATED_S 6 +/* APB_SARADC_SAR_SEL : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: SAR1 1: SAR2 only work for single SAR mode*/ +#define APB_SARADC_SAR_SEL (BIT(5)) +#define APB_SARADC_SAR_SEL_M (BIT(5)) +#define APB_SARADC_SAR_SEL_V 0x1 +#define APB_SARADC_SAR_SEL_S 5 +/* APB_SARADC_WORK_MODE : R/W ;bitpos:[4:3] ;default: 2'd0 ; */ +/*description: 0: single mode 1: double mode 2: alternate mode*/ +#define APB_SARADC_WORK_MODE 0x00000003 +#define APB_SARADC_WORK_MODE_M ((APB_SARADC_WORK_MODE_V) << (APB_SARADC_WORK_MODE_S)) +#define APB_SARADC_WORK_MODE_V 0x3 +#define APB_SARADC_WORK_MODE_S 3 +/* APB_SARADC_START : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_START (BIT(1)) +#define APB_SARADC_START_M (BIT(1)) +#define APB_SARADC_START_V 0x1 +#define APB_SARADC_START_S 1 +/* APB_SARADC_START_FORCE : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_START_FORCE (BIT(0)) +#define APB_SARADC_START_FORCE_M (BIT(0)) +#define APB_SARADC_START_FORCE_V 0x1 +#define APB_SARADC_START_FORCE_S 0 + +#define APB_SARADC_CTRL2_REG (DR_REG_APB_SARADC_BASE + 0x004) +/* APB_SARADC_TIMER_EN : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: to enable saradc timer trigger*/ +#define APB_SARADC_TIMER_EN (BIT(24)) +#define APB_SARADC_TIMER_EN_M (BIT(24)) +#define APB_SARADC_TIMER_EN_V 0x1 +#define APB_SARADC_TIMER_EN_S 24 +/* APB_SARADC_TIMER_TARGET : R/W ;bitpos:[23:12] ;default: 12'd10 ; */ +/*description: to set saradc timer target*/ +#define APB_SARADC_TIMER_TARGET 0x00000FFF +#define APB_SARADC_TIMER_TARGET_M ((APB_SARADC_TIMER_TARGET_V) << (APB_SARADC_TIMER_TARGET_S)) +#define APB_SARADC_TIMER_TARGET_V 0xFFF +#define APB_SARADC_TIMER_TARGET_S 12 +/* APB_SARADC_TIMER_SEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: 1: select saradc timer 0: i2s_ws trigger*/ +#define APB_SARADC_TIMER_SEL (BIT(11)) +#define APB_SARADC_TIMER_SEL_M (BIT(11)) +#define APB_SARADC_TIMER_SEL_V 0x1 +#define APB_SARADC_TIMER_SEL_S 11 +/* APB_SARADC_SAR2_INV : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC2 CTRL is inverted otherwise not*/ +#define APB_SARADC_SAR2_INV (BIT(10)) +#define APB_SARADC_SAR2_INV_M (BIT(10)) +#define APB_SARADC_SAR2_INV_V 0x1 +#define APB_SARADC_SAR2_INV_S 10 +/* APB_SARADC_SAR1_INV : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: 1: data to DIG ADC1 CTRL is inverted otherwise not*/ +#define APB_SARADC_SAR1_INV (BIT(9)) +#define APB_SARADC_SAR1_INV_M (BIT(9)) +#define APB_SARADC_SAR1_INV_V 0x1 +#define APB_SARADC_SAR1_INV_S 9 +/* APB_SARADC_MAX_MEAS_NUM : R/W ;bitpos:[8:1] ;default: 8'd255 ; */ +/*description: max conversion number*/ +#define APB_SARADC_MAX_MEAS_NUM 0x000000FF +#define APB_SARADC_MAX_MEAS_NUM_M ((APB_SARADC_MAX_MEAS_NUM_V) << (APB_SARADC_MAX_MEAS_NUM_S)) +#define APB_SARADC_MAX_MEAS_NUM_V 0xFF +#define APB_SARADC_MAX_MEAS_NUM_S 1 +/* APB_SARADC_MEAS_NUM_LIMIT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_MEAS_NUM_LIMIT (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_M (BIT(0)) +#define APB_SARADC_MEAS_NUM_LIMIT_V 0x1 +#define APB_SARADC_MEAS_NUM_LIMIT_S 0 + +#define APB_SARADC_FILTER_CTRL1_REG (DR_REG_APB_SARADC_BASE + 0x008) +/* APB_SARADC_FILTER_FACTOR0 : R/W ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define APB_SARADC_FILTER_FACTOR0 0x00000007 +#define APB_SARADC_FILTER_FACTOR0_M ((APB_SARADC_FILTER_FACTOR0_V) << (APB_SARADC_FILTER_FACTOR0_S)) +#define APB_SARADC_FILTER_FACTOR0_V 0x7 +#define APB_SARADC_FILTER_FACTOR0_S 29 +/* APB_SARADC_FILTER_FACTOR1 : R/W ;bitpos:[28:26] ;default: 3'd0 ; */ +/*description: */ +#define APB_SARADC_FILTER_FACTOR1 0x00000007 +#define APB_SARADC_FILTER_FACTOR1_M ((APB_SARADC_FILTER_FACTOR1_V) << (APB_SARADC_FILTER_FACTOR1_S)) +#define APB_SARADC_FILTER_FACTOR1_V 0x7 +#define APB_SARADC_FILTER_FACTOR1_S 26 + +#define APB_SARADC_FSM_WAIT_REG (DR_REG_APB_SARADC_BASE + 0x00C) +/* APB_SARADC_STANDBY_WAIT : R/W ;bitpos:[23:16] ;default: 8'd255 ; */ +/*description: */ +#define APB_SARADC_STANDBY_WAIT 0x000000FF +#define APB_SARADC_STANDBY_WAIT_M ((APB_SARADC_STANDBY_WAIT_V) << (APB_SARADC_STANDBY_WAIT_S)) +#define APB_SARADC_STANDBY_WAIT_V 0xFF +#define APB_SARADC_STANDBY_WAIT_S 16 +/* APB_SARADC_RSTB_WAIT : R/W ;bitpos:[15:8] ;default: 8'd8 ; */ +/*description: */ +#define APB_SARADC_RSTB_WAIT 0x000000FF +#define APB_SARADC_RSTB_WAIT_M ((APB_SARADC_RSTB_WAIT_V) << (APB_SARADC_RSTB_WAIT_S)) +#define APB_SARADC_RSTB_WAIT_V 0xFF +#define APB_SARADC_RSTB_WAIT_S 8 +/* APB_SARADC_XPD_WAIT : R/W ;bitpos:[7:0] ;default: 8'd8 ; */ +/*description: */ +#define APB_SARADC_XPD_WAIT 0x000000FF +#define APB_SARADC_XPD_WAIT_M ((APB_SARADC_XPD_WAIT_V) << (APB_SARADC_XPD_WAIT_S)) +#define APB_SARADC_XPD_WAIT_V 0xFF +#define APB_SARADC_XPD_WAIT_S 0 + +#define APB_SARADC_SAR1_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x010) +/* APB_SARADC_SAR1_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_SARADC_SAR1_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_M ((APB_SARADC_SAR1_STATUS_V) << (APB_SARADC_SAR1_STATUS_S)) +#define APB_SARADC_SAR1_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR1_STATUS_S 0 + +#define APB_SARADC_SAR2_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x014) +/* APB_SARADC_SAR2_STATUS : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define APB_SARADC_SAR2_STATUS 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_M ((APB_SARADC_SAR2_STATUS_V) << (APB_SARADC_SAR2_STATUS_S)) +#define APB_SARADC_SAR2_STATUS_V 0xFFFFFFFF +#define APB_SARADC_SAR2_STATUS_S 0 + +#define APB_SARADC_SAR1_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x018) +/* APB_SARADC_SAR1_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: item 0 ~ 3 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB1 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB1_M ((APB_SARADC_SAR1_PATT_TAB1_V) << (APB_SARADC_SAR1_PATT_TAB1_S)) +#define APB_SARADC_SAR1_PATT_TAB1_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB1_S 0 + +#define APB_SARADC_SAR1_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x01C) +/* APB_SARADC_SAR1_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Item 4 ~ 7 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB2 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB2_M ((APB_SARADC_SAR1_PATT_TAB2_V) << (APB_SARADC_SAR1_PATT_TAB2_S)) +#define APB_SARADC_SAR1_PATT_TAB2_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB2_S 0 + +#define APB_SARADC_SAR1_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x020) +/* APB_SARADC_SAR1_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Item 8 ~ 11 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB3 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB3_M ((APB_SARADC_SAR1_PATT_TAB3_V) << (APB_SARADC_SAR1_PATT_TAB3_S)) +#define APB_SARADC_SAR1_PATT_TAB3_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB3_S 0 + +#define APB_SARADC_SAR1_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x024) +/* APB_SARADC_SAR1_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Item 12 ~ 15 for pattern table 1 (each item one byte)*/ +#define APB_SARADC_SAR1_PATT_TAB4 0x00FFFFFF +#define APB_SARADC_SAR1_PATT_TAB4_M ((APB_SARADC_SAR1_PATT_TAB4_V) << (APB_SARADC_SAR1_PATT_TAB4_S)) +#define APB_SARADC_SAR1_PATT_TAB4_V 0xFFFFFF +#define APB_SARADC_SAR1_PATT_TAB4_S 0 + +#define APB_SARADC_SAR2_PATT_TAB1_REG (DR_REG_APB_SARADC_BASE + 0x028) +/* APB_SARADC_SAR2_PATT_TAB1 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: item 0 ~ 3 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB1 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB1_M ((APB_SARADC_SAR2_PATT_TAB1_V) << (APB_SARADC_SAR2_PATT_TAB1_S)) +#define APB_SARADC_SAR2_PATT_TAB1_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB1_S 0 + +#define APB_SARADC_SAR2_PATT_TAB2_REG (DR_REG_APB_SARADC_BASE + 0x02C) +/* APB_SARADC_SAR2_PATT_TAB2 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Item 4 ~ 7 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB2 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB2_M ((APB_SARADC_SAR2_PATT_TAB2_V) << (APB_SARADC_SAR2_PATT_TAB2_S)) +#define APB_SARADC_SAR2_PATT_TAB2_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB2_S 0 + +#define APB_SARADC_SAR2_PATT_TAB3_REG (DR_REG_APB_SARADC_BASE + 0x030) +/* APB_SARADC_SAR2_PATT_TAB3 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Item 8 ~ 11 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB3 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB3_M ((APB_SARADC_SAR2_PATT_TAB3_V) << (APB_SARADC_SAR2_PATT_TAB3_S)) +#define APB_SARADC_SAR2_PATT_TAB3_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB3_S 0 + +#define APB_SARADC_SAR2_PATT_TAB4_REG (DR_REG_APB_SARADC_BASE + 0x034) +/* APB_SARADC_SAR2_PATT_TAB4 : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: Item 12 ~ 15 for pattern table 2 (each item one byte)*/ +#define APB_SARADC_SAR2_PATT_TAB4 0x00FFFFFF +#define APB_SARADC_SAR2_PATT_TAB4_M ((APB_SARADC_SAR2_PATT_TAB4_V) << (APB_SARADC_SAR2_PATT_TAB4_S)) +#define APB_SARADC_SAR2_PATT_TAB4_V 0xFFFFFF +#define APB_SARADC_SAR2_PATT_TAB4_S 0 + +#define APB_SARADC_APB_ADC_ARB_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x038) +/* APB_SARADC_ADC_ARB_FIX_PRIORITY : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: adc2 arbiter uses fixed priority*/ +#define APB_SARADC_ADC_ARB_FIX_PRIORITY (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_M (BIT(12)) +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_V 0x1 +#define APB_SARADC_ADC_ARB_FIX_PRIORITY_S 12 +/* APB_SARADC_ADC_ARB_WIFI_PRIORITY : R/W ;bitpos:[11:10] ;default: 2'd2 ; */ +/*description: Set adc2 arbiter wifi priority*/ +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_M ((APB_SARADC_ADC_ARB_WIFI_PRIORITY_V) << (APB_SARADC_ADC_ARB_WIFI_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_WIFI_PRIORITY_S 10 +/* APB_SARADC_ADC_ARB_RTC_PRIORITY : R/W ;bitpos:[9:8] ;default: 2'd1 ; */ +/*description: Set adc2 arbiter rtc priority*/ +#define APB_SARADC_ADC_ARB_RTC_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_M ((APB_SARADC_ADC_ARB_RTC_PRIORITY_V) << (APB_SARADC_ADC_ARB_RTC_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_RTC_PRIORITY_S 8 +/* APB_SARADC_ADC_ARB_APB_PRIORITY : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: Set adc2 arbiterapb priority*/ +#define APB_SARADC_ADC_ARB_APB_PRIORITY 0x00000003 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_M ((APB_SARADC_ADC_ARB_APB_PRIORITY_V) << (APB_SARADC_ADC_ARB_APB_PRIORITY_S)) +#define APB_SARADC_ADC_ARB_APB_PRIORITY_V 0x3 +#define APB_SARADC_ADC_ARB_APB_PRIORITY_S 6 +/* APB_SARADC_ADC_ARB_GRANT_FORCE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: adc2 arbiter force grant*/ +#define APB_SARADC_ADC_ARB_GRANT_FORCE (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_M (BIT(5)) +#define APB_SARADC_ADC_ARB_GRANT_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_GRANT_FORCE_S 5 +/* APB_SARADC_ADC_ARB_WIFI_FORCE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enable wifi controller*/ +#define APB_SARADC_ADC_ARB_WIFI_FORCE (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_M (BIT(4)) +#define APB_SARADC_ADC_ARB_WIFI_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_WIFI_FORCE_S 4 +/* APB_SARADC_ADC_ARB_RTC_FORCE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enable rtc controller*/ +#define APB_SARADC_ADC_ARB_RTC_FORCE (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_M (BIT(3)) +#define APB_SARADC_ADC_ARB_RTC_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_RTC_FORCE_S 3 +/* APB_SARADC_ADC_ARB_APB_FORCE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: adc2 arbiter force to enableapb controller*/ +#define APB_SARADC_ADC_ARB_APB_FORCE (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_M (BIT(2)) +#define APB_SARADC_ADC_ARB_APB_FORCE_V 0x1 +#define APB_SARADC_ADC_ARB_APB_FORCE_S 2 + +#define APB_SARADC_FILTER_CTRL0_REG (DR_REG_APB_SARADC_BASE + 0x03C) +/* APB_SARADC_FILTER_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable apb_adc1_filter*/ +#define APB_SARADC_FILTER_RESET (BIT(31)) +#define APB_SARADC_FILTER_RESET_M (BIT(31)) +#define APB_SARADC_FILTER_RESET_V 0x1 +#define APB_SARADC_FILTER_RESET_S 31 +/* APB_SARADC_FILTER_CHANNEL0 : R/W ;bitpos:[23:19] ;default: 5'hd ; */ +/*description: apb_adc1_filter_factor*/ +#define APB_SARADC_FILTER_CHANNEL0 0x0000001F +#define APB_SARADC_FILTER_CHANNEL0_M ((APB_SARADC_FILTER_CHANNEL0_V) << (APB_SARADC_FILTER_CHANNEL0_S)) +#define APB_SARADC_FILTER_CHANNEL0_V 0x1F +#define APB_SARADC_FILTER_CHANNEL0_S 19 +/* APB_SARADC_FILTER_CHANNEL1 : R/W ;bitpos:[18:14] ;default: 5'hd ; */ +/*description: */ +#define APB_SARADC_FILTER_CHANNEL1 0x0000001F +#define APB_SARADC_FILTER_CHANNEL1_M ((APB_SARADC_FILTER_CHANNEL1_V) << (APB_SARADC_FILTER_CHANNEL1_S)) +#define APB_SARADC_FILTER_CHANNEL1_V 0x1F +#define APB_SARADC_FILTER_CHANNEL1_S 14 + +#define APB_SARADC_1_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x040) +/* APB_SARADC_ADC1_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DATA 0x0001FFFF +#define APB_SARADC_ADC1_DATA_M ((APB_SARADC_ADC1_DATA_V) << (APB_SARADC_ADC1_DATA_S)) +#define APB_SARADC_ADC1_DATA_V 0x1FFFF +#define APB_SARADC_ADC1_DATA_S 0 + +#define APB_SARADC_THRES0_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x044) +/* APB_SARADC_THRES0_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES0_LOW 0x00001FFF +#define APB_SARADC_THRES0_LOW_M ((APB_SARADC_THRES0_LOW_V) << (APB_SARADC_THRES0_LOW_S)) +#define APB_SARADC_THRES0_LOW_V 0x1FFF +#define APB_SARADC_THRES0_LOW_S 18 +/* APB_SARADC_THRES0_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES0_HIGH 0x00001FFF +#define APB_SARADC_THRES0_HIGH_M ((APB_SARADC_THRES0_HIGH_V) << (APB_SARADC_THRES0_HIGH_S)) +#define APB_SARADC_THRES0_HIGH_V 0x1FFF +#define APB_SARADC_THRES0_HIGH_S 5 +/* APB_SARADC_THRES0_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */ +/*description: */ +#define APB_SARADC_THRES0_CHANNEL 0x0000001F +#define APB_SARADC_THRES0_CHANNEL_M ((APB_SARADC_THRES0_CHANNEL_V) << (APB_SARADC_THRES0_CHANNEL_S)) +#define APB_SARADC_THRES0_CHANNEL_V 0x1F +#define APB_SARADC_THRES0_CHANNEL_S 0 + +#define APB_SARADC_THRES1_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x048) +/* APB_SARADC_THRES1_LOW : R/W ;bitpos:[30:18] ;default: 13'd0 ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES1_LOW 0x00001FFF +#define APB_SARADC_THRES1_LOW_M ((APB_SARADC_THRES1_LOW_V) << (APB_SARADC_THRES1_LOW_S)) +#define APB_SARADC_THRES1_LOW_V 0x1FFF +#define APB_SARADC_THRES1_LOW_S 18 +/* APB_SARADC_THRES1_HIGH : R/W ;bitpos:[17:5] ;default: 13'h1fff ; */ +/*description: saradc1's thres0 monitor thres*/ +#define APB_SARADC_THRES1_HIGH 0x00001FFF +#define APB_SARADC_THRES1_HIGH_M ((APB_SARADC_THRES1_HIGH_V) << (APB_SARADC_THRES1_HIGH_S)) +#define APB_SARADC_THRES1_HIGH_V 0x1FFF +#define APB_SARADC_THRES1_HIGH_S 5 +/* APB_SARADC_THRES1_CHANNEL : R/W ;bitpos:[4:0] ;default: 5'd13 ; */ +/*description: */ +#define APB_SARADC_THRES1_CHANNEL 0x0000001F +#define APB_SARADC_THRES1_CHANNEL_M ((APB_SARADC_THRES1_CHANNEL_V) << (APB_SARADC_THRES1_CHANNEL_S)) +#define APB_SARADC_THRES1_CHANNEL_V 0x1F +#define APB_SARADC_THRES1_CHANNEL_S 0 + +#define APB_SARADC_THRES_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x058) +/* APB_SARADC_THRES0_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_EN (BIT(31)) +#define APB_SARADC_THRES0_EN_M (BIT(31)) +#define APB_SARADC_THRES0_EN_V 0x1 +#define APB_SARADC_THRES0_EN_S 31 +/* APB_SARADC_THRES1_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_EN (BIT(30)) +#define APB_SARADC_THRES1_EN_M (BIT(30)) +#define APB_SARADC_THRES1_EN_V 0x1 +#define APB_SARADC_THRES1_EN_S 30 +/* APB_SARADC_THRES2_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES2_EN (BIT(29)) +#define APB_SARADC_THRES2_EN_M (BIT(29)) +#define APB_SARADC_THRES2_EN_V 0x1 +#define APB_SARADC_THRES2_EN_S 29 +/* APB_SARADC_THRES3_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES3_EN (BIT(28)) +#define APB_SARADC_THRES3_EN_M (BIT(28)) +#define APB_SARADC_THRES3_EN_V 0x1 +#define APB_SARADC_THRES3_EN_S 28 +/* APB_SARADC_THRES_ALL_EN : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_THRES_ALL_EN (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_M (BIT(27)) +#define APB_SARADC_THRES_ALL_EN_V 0x1 +#define APB_SARADC_THRES_ALL_EN_S 27 + +#define APB_SARADC_INT_ENA_REG (DR_REG_APB_SARADC_BASE + 0x05C) +/* APB_SARADC_ADC1_DONE_INT_ENA : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_ENA (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ENA_S 31 +/* APB_SARADC_ADC2_DONE_INT_ENA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_ENA (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ENA_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ENA_S 30 +/* APB_SARADC_THRES0_HIGH_INT_ENA : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_ENA (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ENA_S 29 +/* APB_SARADC_THRES1_HIGH_INT_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_ENA (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ENA_S 28 +/* APB_SARADC_THRES0_LOW_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_ENA (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ENA_S 27 +/* APB_SARADC_THRES1_LOW_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_ENA (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ENA_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ENA_S 26 + +#define APB_SARADC_INT_RAW_REG (DR_REG_APB_SARADC_BASE + 0x060) +/* APB_SARADC_ADC1_DONE_INT_RAW : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_RAW (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_RAW_S 31 +/* APB_SARADC_ADC2_DONE_INT_RAW : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_RAW (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_RAW_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_RAW_S 30 +/* APB_SARADC_THRES0_HIGH_INT_RAW : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_RAW (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_RAW_S 29 +/* APB_SARADC_THRES1_HIGH_INT_RAW : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_RAW (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_RAW_S 28 +/* APB_SARADC_THRES0_LOW_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_RAW (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_RAW_S 27 +/* APB_SARADC_THRES1_LOW_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_RAW (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_RAW_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_RAW_S 26 + +#define APB_SARADC_INT_ST_REG (DR_REG_APB_SARADC_BASE + 0x064) +/* APB_SARADC_ADC1_DONE_INT_ST : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_ST (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_ST_S 31 +/* APB_SARADC_ADC2_DONE_INT_ST : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_ST (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_ST_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_ST_S 30 +/* APB_SARADC_THRES0_HIGH_INT_ST : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_ST (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_ST_S 29 +/* APB_SARADC_THRES1_HIGH_INT_ST : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_ST (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_ST_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_ST_S 28 +/* APB_SARADC_THRES0_LOW_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_ST (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_ST_S 27 +/* APB_SARADC_THRES1_LOW_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_ST (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_ST_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_ST_S 26 + +#define APB_SARADC_INT_CLR_REG (DR_REG_APB_SARADC_BASE + 0x068) +/* APB_SARADC_ADC1_DONE_INT_CLR : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC1_DONE_INT_CLR (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_M (BIT(31)) +#define APB_SARADC_ADC1_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC1_DONE_INT_CLR_S 31 +/* APB_SARADC_ADC2_DONE_INT_CLR : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DONE_INT_CLR (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_M (BIT(30)) +#define APB_SARADC_ADC2_DONE_INT_CLR_V 0x1 +#define APB_SARADC_ADC2_DONE_INT_CLR_S 30 +/* APB_SARADC_THRES0_HIGH_INT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_HIGH_INT_CLR (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_M (BIT(29)) +#define APB_SARADC_THRES0_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_HIGH_INT_CLR_S 29 +/* APB_SARADC_THRES1_HIGH_INT_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_HIGH_INT_CLR (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_M (BIT(28)) +#define APB_SARADC_THRES1_HIGH_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_HIGH_INT_CLR_S 28 +/* APB_SARADC_THRES0_LOW_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES0_LOW_INT_CLR (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_M (BIT(27)) +#define APB_SARADC_THRES0_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES0_LOW_INT_CLR_S 27 +/* APB_SARADC_THRES1_LOW_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_THRES1_LOW_INT_CLR (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_M (BIT(26)) +#define APB_SARADC_THRES1_LOW_INT_CLR_V 0x1 +#define APB_SARADC_THRES1_LOW_INT_CLR_S 26 + +#define APB_SARADC_DMA_CONF_REG (DR_REG_APB_SARADC_BASE + 0x06c) +/* APB_SARADC_APB_ADC_TRANS : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: enable apb_adc use spi_dma*/ +#define APB_SARADC_APB_ADC_TRANS (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_M (BIT(31)) +#define APB_SARADC_APB_ADC_TRANS_V 0x1 +#define APB_SARADC_APB_ADC_TRANS_S 31 +/* APB_SARADC_APB_ADC_RESET_FSM : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: reset_apb_adc_state*/ +#define APB_SARADC_APB_ADC_RESET_FSM (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_M (BIT(30)) +#define APB_SARADC_APB_ADC_RESET_FSM_V 0x1 +#define APB_SARADC_APB_ADC_RESET_FSM_S 30 +/* APB_SARADC_APB_ADC_EOF_NUM : R/W ;bitpos:[15:0] ;default: 16'd255 ; */ +/*description: the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ +#define APB_SARADC_APB_ADC_EOF_NUM 0x0000FFFF +#define APB_SARADC_APB_ADC_EOF_NUM_M ((APB_SARADC_APB_ADC_EOF_NUM_V) << (APB_SARADC_APB_ADC_EOF_NUM_S)) +#define APB_SARADC_APB_ADC_EOF_NUM_V 0xFFFF +#define APB_SARADC_APB_ADC_EOF_NUM_S 0 + +#define APB_SARADC_APB_ADC_CLKM_CONF_REG (DR_REG_APB_SARADC_BASE + 0x070) +/* APB_SARADC_CLK_SEL : R/W ;bitpos:[22:21] ;default: 2'b0 ; */ +/*description: Set this bit to enable clk_apll*/ +#define APB_SARADC_CLK_SEL 0x00000003 +#define APB_SARADC_CLK_SEL_M ((APB_SARADC_CLK_SEL_V) << (APB_SARADC_CLK_SEL_S)) +#define APB_SARADC_CLK_SEL_V 0x3 +#define APB_SARADC_CLK_SEL_S 21 +/* APB_SARADC_CLK_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: */ +#define APB_SARADC_CLK_EN (BIT(20)) +#define APB_SARADC_CLK_EN_M (BIT(20)) +#define APB_SARADC_CLK_EN_V 0x1 +#define APB_SARADC_CLK_EN_S 20 +/* APB_SARADC_CLKM_DIV_A : R/W ;bitpos:[19:14] ;default: 6'h0 ; */ +/*description: Fractional clock divider denominator value*/ +#define APB_SARADC_CLKM_DIV_A 0x0000003F +#define APB_SARADC_CLKM_DIV_A_M ((APB_SARADC_CLKM_DIV_A_V) << (APB_SARADC_CLKM_DIV_A_S)) +#define APB_SARADC_CLKM_DIV_A_V 0x3F +#define APB_SARADC_CLKM_DIV_A_S 14 +/* APB_SARADC_CLKM_DIV_B : R/W ;bitpos:[13:8] ;default: 6'h0 ; */ +/*description: Fractional clock divider numerator value*/ +#define APB_SARADC_CLKM_DIV_B 0x0000003F +#define APB_SARADC_CLKM_DIV_B_M ((APB_SARADC_CLKM_DIV_B_V) << (APB_SARADC_CLKM_DIV_B_S)) +#define APB_SARADC_CLKM_DIV_B_V 0x3F +#define APB_SARADC_CLKM_DIV_B_S 8 +/* APB_SARADC_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd4 ; */ +/*description: Integral I2S clock divider value*/ +#define APB_SARADC_CLKM_DIV_NUM 0x000000FF +#define APB_SARADC_CLKM_DIV_NUM_M ((APB_SARADC_CLKM_DIV_NUM_V) << (APB_SARADC_CLKM_DIV_NUM_S)) +#define APB_SARADC_CLKM_DIV_NUM_V 0xFF +#define APB_SARADC_CLKM_DIV_NUM_S 0 + +#define APB_SARADC_APB_DAC_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x074) +/* APB_SARADC_DAC_CLK_GATE_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_DAC_CLK_GATE_EN (BIT(18)) +#define APB_SARADC_DAC_CLK_GATE_EN_M (BIT(18)) +#define APB_SARADC_DAC_CLK_GATE_EN_V 0x1 +#define APB_SARADC_DAC_CLK_GATE_EN_S 18 +/* APB_SARADC_DAC_CLK_FO : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_DAC_CLK_FO (BIT(17)) +#define APB_SARADC_DAC_CLK_FO_M (BIT(17)) +#define APB_SARADC_DAC_CLK_FO_V 0x1 +#define APB_SARADC_DAC_CLK_FO_S 17 +/* APB_SARADC_APB_DAC_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_APB_DAC_RST (BIT(16)) +#define APB_SARADC_APB_DAC_RST_M (BIT(16)) +#define APB_SARADC_APB_DAC_RST_V 0x1 +#define APB_SARADC_APB_DAC_RST_S 16 +/* APB_SARADC_DAC_RESET_FIFO : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define APB_SARADC_DAC_RESET_FIFO (BIT(15)) +#define APB_SARADC_DAC_RESET_FIFO_M (BIT(15)) +#define APB_SARADC_DAC_RESET_FIFO_V 0x1 +#define APB_SARADC_DAC_RESET_FIFO_S 15 +/* APB_SARADC_APB_DAC_TRANS : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable dma_dac*/ +#define APB_SARADC_APB_DAC_TRANS (BIT(14)) +#define APB_SARADC_APB_DAC_TRANS_M (BIT(14)) +#define APB_SARADC_APB_DAC_TRANS_V 0x1 +#define APB_SARADC_APB_DAC_TRANS_S 14 +/* APB_SARADC_APB_DAC_ALTER_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: enable dac alter mode*/ +#define APB_SARADC_APB_DAC_ALTER_MODE (BIT(13)) +#define APB_SARADC_APB_DAC_ALTER_MODE_M (BIT(13)) +#define APB_SARADC_APB_DAC_ALTER_MODE_V 0x1 +#define APB_SARADC_APB_DAC_ALTER_MODE_S 13 +/* APB_SARADC_DAC_TIMER_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable read dac data*/ +#define APB_SARADC_DAC_TIMER_EN (BIT(12)) +#define APB_SARADC_DAC_TIMER_EN_M (BIT(12)) +#define APB_SARADC_DAC_TIMER_EN_V 0x1 +#define APB_SARADC_DAC_TIMER_EN_S 12 +/* APB_SARADC_DAC_TIMER_TARGET : R/W ;bitpos:[11:0] ;default: 12'd100 ; */ +/*description: dac_timer target*/ +#define APB_SARADC_DAC_TIMER_TARGET 0x00000FFF +#define APB_SARADC_DAC_TIMER_TARGET_M ((APB_SARADC_DAC_TIMER_TARGET_V) << (APB_SARADC_DAC_TIMER_TARGET_S)) +#define APB_SARADC_DAC_TIMER_TARGET_V 0xFFF +#define APB_SARADC_DAC_TIMER_TARGET_S 0 + +#define APB_SARADC_2_DATA_STATUS_REG (DR_REG_APB_SARADC_BASE + 0x078) +/* APB_SARADC_ADC2_DATA : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: */ +#define APB_SARADC_ADC2_DATA 0x0001FFFF +#define APB_SARADC_ADC2_DATA_M ((APB_SARADC_ADC2_DATA_V) << (APB_SARADC_ADC2_DATA_S)) +#define APB_SARADC_ADC2_DATA_V 0x1FFFF +#define APB_SARADC_ADC2_DATA_S 0 + +#define APB_SARADC_APB_DAC_CLK_CTRL_REG (DR_REG_APB_SARADC_BASE + 0x07c) +/* APB_SARADC_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: */ +#define APB_SARADC_DAC_CLK_DIV 0x000000FF +#define APB_SARADC_DAC_CLK_DIV_M ((APB_SARADC_DAC_CLK_DIV_V) << (APB_SARADC_DAC_CLK_DIV_S)) +#define APB_SARADC_DAC_CLK_DIV_V 0xFF +#define APB_SARADC_DAC_CLK_DIV_S 0 + +#define APB_SARADC_APB_CTRL_DATE_REG (DR_REG_APB_SARADC_BASE + 0x3FC) +/* APB_SARADC_APB_CTRL_DATE : R/W ;bitpos:[31:0] ;default: 32'h02003060 ; */ +/*description: */ +#define APB_SARADC_APB_CTRL_DATE 0xFFFFFFFF +#define APB_SARADC_APB_CTRL_DATE_M ((APB_SARADC_APB_CTRL_DATE_V) << (APB_SARADC_APB_CTRL_DATE_S)) +#define APB_SARADC_APB_CTRL_DATE_V 0xFFFFFFFF +#define APB_SARADC_APB_CTRL_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/apb_saradc_struct.h b/components/soc/soc/esp32s3/include/soc/apb_saradc_struct.h new file mode 100644 index 000000000..9814b6300 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/apb_saradc_struct.h @@ -0,0 +1,521 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t start_force: 1; + uint32_t start: 1; + uint32_t reserved2: 1; + uint32_t work_mode: 2; /*0: single mode 1: double mode 2: alternate mode*/ + uint32_t sar_sel: 1; /*0: SAR1 1: SAR2 only work for single SAR mode*/ + uint32_t sar_clk_gated: 1; + uint32_t sar_clk_div: 8; /*SAR clock divider*/ + uint32_t sar1_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + uint32_t sar2_patt_len: 4; /*0 ~ 15 means length 1 ~ 16*/ + uint32_t sar1_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC1 CTRL*/ + uint32_t sar2_patt_p_clear: 1; /*clear the pointer of pattern table for DIG ADC2 CTRL*/ + uint32_t data_sar_sel: 1; /*1: sar_sel will be coded by the MSB of the 16-bit output data in this case the resolution should not be larger than 11 bits.*/ + uint32_t data_to_i2s: 1; /*1: I2S input data is from SAR ADC (for DMA) 0: I2S input data is from GPIO matrix*/ + uint32_t xpd_sar_force: 2; /*force option to xpd sar blocks*/ + uint32_t reserved29: 1; + uint32_t wait_arb_cycle: 2; /*wait arbit signal stable after sar_done*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t meas_num_limit: 1; + uint32_t max_meas_num: 8; /*max conversion number*/ + uint32_t sar1_inv: 1; /*1: data to DIG ADC1 CTRL is inverted otherwise not*/ + uint32_t sar2_inv: 1; /*1: data to DIG ADC2 CTRL is inverted otherwise not*/ + uint32_t timer_sel: 1; /*1: select saradc timer 0: i2s_ws trigger*/ + uint32_t timer_target: 12; /*to set saradc timer target*/ + uint32_t timer_en: 1; /*to enable saradc timer trigger*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t reserved0: 26; + uint32_t filter_factor1: 3; + uint32_t filter_factor0: 3; + }; + uint32_t val; + } filter_ctrl1; + union { + struct { + uint32_t xpd_wait: 8; + uint32_t rstb_wait: 8; + uint32_t standby_wait: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } fsm_wait; + uint32_t sar1_status; /**/ + uint32_t sar2_status; /**/ + union { + struct { + uint32_t sar1_patt_tab1: 24; /*item 0 ~ 3 for pattern table 1 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar1_patt_tab1; + union { + struct { + uint32_t sar1_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 1 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar1_patt_tab2; + union { + struct { + uint32_t sar1_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 1 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar1_patt_tab3; + union { + struct { + uint32_t sar1_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 1 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar1_patt_tab4; + union { + struct { + uint32_t sar2_patt_tab1: 24; /*item 0 ~ 3 for pattern table 2 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar2_patt_tab1; + union { + struct { + uint32_t sar2_patt_tab2: 24; /*Item 4 ~ 7 for pattern table 2 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar2_patt_tab2; + union { + struct { + uint32_t sar2_patt_tab3: 24; /*Item 8 ~ 11 for pattern table 2 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar2_patt_tab3; + union { + struct { + uint32_t sar2_patt_tab4: 24; /*Item 12 ~ 15 for pattern table 2 (each item one byte)*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } sar2_patt_tab4; + union { + struct { + uint32_t reserved0: 2; + uint32_t adc_arb_apb_force: 1; /*adc2 arbiter force to enableapb controller*/ + uint32_t adc_arb_rtc_force: 1; /*adc2 arbiter force to enable rtc controller*/ + uint32_t adc_arb_wifi_force: 1; /*adc2 arbiter force to enable wifi controller*/ + uint32_t adc_arb_grant_force: 1; /*adc2 arbiter force grant*/ + uint32_t adc_arb_apb_priority: 2; /*Set adc2 arbiterapb priority*/ + uint32_t adc_arb_rtc_priority: 2; /*Set adc2 arbiter rtc priority*/ + uint32_t adc_arb_wifi_priority: 2; /*Set adc2 arbiter wifi priority*/ + uint32_t adc_arb_fix_priority: 1; /*adc2 arbiter uses fixed priority*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } apb_adc_arb_ctrl; + union { + struct { + uint32_t reserved0: 14; + uint32_t filter_channel1: 5; + uint32_t filter_channel0: 5; /*apb_adc1_filter_factor*/ + uint32_t reserved24: 7; + uint32_t filter_reset: 1; /*enable apb_adc1_filter*/ + }; + uint32_t val; + } filter_ctrl0; + union { + struct { + uint32_t adc1_data: 17; + uint32_t reserved17: 15; + }; + uint32_t val; + } apb_saradc1_data_status; + union { + struct { + uint32_t thres0_channel: 5; + uint32_t thres0_high: 13; /*saradc1's thres0 monitor thres*/ + uint32_t thres0_low: 13; /*saradc1's thres0 monitor thres*/ + }; + uint32_t val; + } thres0_ctrl; + union { + struct { + uint32_t thres1_channel: 5; + uint32_t thres1_high: 13; /*saradc1's thres0 monitor thres*/ + uint32_t thres1_low: 13; /*saradc1's thres0 monitor thres*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } thres1_ctrl; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + union { + struct { + uint32_t reserved0: 27; + uint32_t thres_all_en: 1; + uint32_t thres3_en: 1; + uint32_t thres2_en: 1; + uint32_t thres1_en: 1; + uint32_t thres0_en: 1; + }; + uint32_t val; + } thres_ctrl; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t reserved0: 26; + uint32_t thres1_low: 1; + uint32_t thres0_low: 1; + uint32_t thres1_high: 1; + uint32_t thres0_high: 1; + uint32_t adc2_done: 1; + uint32_t adc1_done: 1; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t apb_adc_eof_num: 16; /*the dma_in_suc_eof gen when sample cnt = spi_eof_num*/ + uint32_t reserved16: 14; + uint32_t apb_adc_reset_fsm: 1; /*reset_apb_adc_state*/ + uint32_t apb_adc_trans: 1; /*enable apb_adc use spi_dma*/ + }; + uint32_t val; + } dma_conf; + union { + struct { + uint32_t clkm_div_num: 8; /*Integral I2S clock divider value*/ + uint32_t clkm_div_b: 6; /*Fractional clock divider numerator value*/ + uint32_t clkm_div_a: 6; /*Fractional clock divider denominator value*/ + uint32_t clk_en: 1; + uint32_t clk_sel: 2; /*Set this bit to enable clk_apll*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } apb_adc_clkm_conf; + union { + struct { + uint32_t dac_timer_target: 12; /*dac_timer target*/ + uint32_t dac_timer_en: 1; /*enable read dac data*/ + uint32_t apb_dac_alter_mode: 1; /*enable dac alter mode*/ + uint32_t apb_dac_trans: 1; /*enable dma_dac*/ + uint32_t dac_reset_fifo: 1; + uint32_t apb_dac_rst: 1; + uint32_t dac_clk_fo: 1; + uint32_t dac_clk_gate_en: 1; + uint32_t reserved19: 13; + }; + uint32_t val; + } apb_dac_ctrl; + union { + struct { + uint32_t adc2_data: 17; + uint32_t reserved17: 15; + }; + uint32_t val; + } apb_saradc2_data_status; + union { + struct { + uint32_t dac_clk_div: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } apb_dac_clk_ctrl; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t apb_ctrl_date; /**/ +} apb_saradc_dev_t; + +extern apb_saradc_dev_t APB_SARADC; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/assist_debug_reg.h b/components/soc/soc/esp32s3/include/soc/assist_debug_reg.h new file mode 100644 index 000000000..ae867a44b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/assist_debug_reg.h @@ -0,0 +1,1332 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define ASSIST_DEBUG_CORE_0_INTERRUPT_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x000) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_ENA_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_ENA_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_ENA_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_ENA_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_ENA_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_ENA_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_ENA_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_ENA_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_ENA_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_ENA_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_ENA_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_ENA_S 0 + +#define ASSIST_DEBUG_CORE_0_INTERRUPT_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x004) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RAW_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RAW_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RAW_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RAW_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RAW_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RAW_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RAW_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RAW_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RAW_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RAW_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RAW_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RAW_S 0 + +#define ASSIST_DEBUG_CORE_0_INTERRUPT_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x008) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_RLS_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_RLS_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_RLS_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_RLS_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_RLS_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_RLS_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_RLS_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_RLS_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_RLS_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_RLS_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_RLS_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_RLS_S 0 + +#define ASSIST_DEBUG_CORE_0_INTERRUPT_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x00C) +/* ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11)) +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_CLR_S 11 +/* ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10)) +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_CLR_S 10 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_M (BIT(9)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MAX_CLR_S 9 +/* ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_M (BIT(8)) +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_SP_SPILL_MIN_CLR_S 8 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_M (BIT(7)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_WR_CLR_S 7 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_M (BIT(6)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_RD_CLR_S 6 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_M (BIT(5)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_WR_CLR_S 5 +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_M (BIT(4)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_RD_CLR_S 4 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_M (BIT(3)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_WR_CLR_S 3 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_M (BIT(2)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_RD_CLR_S 2 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_M (BIT(1)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_WR_CLR_S 1 +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_RD_CLR_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x010) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x014) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x018) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x01C) +/* ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x020) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x024) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x028) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x02C) +/* ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V) << (ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x030) +/* ASSIST_DEBUG_CORE_0_AREA_SP : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_SP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_SP_M ((ASSIST_DEBUG_CORE_0_AREA_SP_V) << (ASSIST_DEBUG_CORE_0_AREA_SP_S)) +#define ASSIST_DEBUG_CORE_0_AREA_SP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_SP_S 0 + +#define ASSIST_DEBUG_CORE_0_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x034) +/* ASSIST_DEBUG_CORE_0_AREA_PC : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_AREA_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PC_M ((ASSIST_DEBUG_CORE_0_AREA_PC_V) << (ASSIST_DEBUG_CORE_0_AREA_PC_S)) +#define ASSIST_DEBUG_CORE_0_AREA_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_AREA_PC_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x038) +/* ASSIST_DEBUG_CORE_0_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE 0x000000FF +#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_M ((ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V) << (ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S)) +#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_V 0xFF +#define ASSIST_DEBUG_CORE_0_SP_UNSTABLE_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x03C) +/* ASSIST_DEBUG_CORE_0_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MIN_M ((ASSIST_DEBUG_CORE_0_SP_MIN_V) << (ASSIST_DEBUG_CORE_0_SP_MIN_S)) +#define ASSIST_DEBUG_CORE_0_SP_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MIN_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x040) +/* ASSIST_DEBUG_CORE_0_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MAX_M ((ASSIST_DEBUG_CORE_0_SP_MAX_V) << (ASSIST_DEBUG_CORE_0_SP_MAX_S)) +#define ASSIST_DEBUG_CORE_0_SP_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_MAX_S 0 + +#define ASSIST_DEBUG_CORE_0_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x044) +/* ASSIST_DEBUG_CORE_0_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_SP_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_PC_M ((ASSIST_DEBUG_CORE_0_SP_PC_V) << (ASSIST_DEBUG_CORE_0_SP_PC_S)) +#define ASSIST_DEBUG_CORE_0_SP_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_SP_PC_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x048) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_V 0x1 +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGENABLE_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x04C) +/* ASSIST_DEBUG_CORE_0_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_RECORDING (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_M (BIT(0)) +#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_V 0x1 +#define ASSIST_DEBUG_CORE_0_RCD_RECORDING_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_REG (DR_REG_ASSIST_DEBUG_BASE + 0x050) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGINST_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x054) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS 0x000000FF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_V 0xFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGSTATUS_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x058) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGDATA_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x05C) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_REG (DR_REG_ASSIST_DEBUG_BASE + 0x060) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0STAT_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x064) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0ADDR_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x068) +/* ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_M ((ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V) << (ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S)) +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_PDEBUGLS0DATA_S 0 + +#define ASSIST_DEBUG_CORE_0_RCD_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x06C) +/* ASSIST_DEBUG_CORE_0_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_RCD_SP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_SP_M ((ASSIST_DEBUG_CORE_0_RCD_SP_V) << (ASSIST_DEBUG_CORE_0_RCD_SP_S)) +#define ASSIST_DEBUG_CORE_0_RCD_SP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_RCD_SP_S 0 + +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x070) +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_0_S 25 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_0_S 24 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x074) +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_LOADSTORE_1_S 25 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_M (BIT(24)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_WR_1_S 24 +/* ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1 0x00FFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_0_IRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x078) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0 (BIT(22)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_M (BIT(22)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_0_S 22 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0 0x003FFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_V 0x3FFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x07C) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0 0x0000FFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_V 0xFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_0_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x080) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_0_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x084) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1 (BIT(22)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_M (BIT(22)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_WR_1_S 22 +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1 0x003FFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_V 0x3FFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x088) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1 0x0000FFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_V 0xFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_BYTEEN_1_S 0 + +#define ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x08C) +/* ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V) << (ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S)) +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_0_DRAM0_RECORDING_PC_1_S 0 + +#define ASSIST_DEBUG_CORE_1_INTERRUPT_ENA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x090) +/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_M (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_ENA_S 11 +/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_M (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_ENA_S 10 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_M (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_ENA_S 9 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_M (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_ENA_S 8 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_M (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_ENA_S 7 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_M (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_ENA_S 6 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_M (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_ENA_S 5 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_M (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_ENA_S 4 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_M (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_ENA_S 3 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_M (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_ENA_S 2 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_M (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_ENA_S 1 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_M (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_ENA_S 0 + +#define ASSIST_DEBUG_CORE_1_INTERRUPT_RAW_REG (DR_REG_ASSIST_DEBUG_BASE + 0x094) +/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_M (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RAW_S 11 +/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_M (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RAW_S 10 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_M (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RAW_S 9 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_M (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RAW_S 8 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_M (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RAW_S 7 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_M (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RAW_S 6 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_M (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RAW_S 5 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_M (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RAW_S 4 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_M (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RAW_S 3 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_M (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RAW_S 2 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_M (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RAW_S 1 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_M (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RAW_S 0 + +#define ASSIST_DEBUG_CORE_1_INTERRUPT_RLS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x098) +/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_M (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_RLS_S 11 +/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_M (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_RLS_S 10 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_M (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_RLS_S 9 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_M (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_RLS_S 8 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_M (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_RLS_S 7 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_M (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_RLS_S 6 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_M (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_RLS_S 5 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_M (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_RLS_S 4 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_M (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_RLS_S 3 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_M (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_RLS_S 2 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_M (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_RLS_S 1 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_M (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_RLS_S 0 + +#define ASSIST_DEBUG_CORE_1_INTERRUPT_CLR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x09C) +/* ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_M (BIT(11)) +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_CLR_S 11 +/* ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_M (BIT(10)) +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_CLR_S 10 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_M (BIT(9)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MAX_CLR_S 9 +/* ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_M (BIT(8)) +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_SP_SPILL_MIN_CLR_S 8 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_M (BIT(7)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_WR_CLR_S 7 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_M (BIT(6)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_RD_CLR_S 6 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_M (BIT(5)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_WR_CLR_S 5 +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_M (BIT(4)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_RD_CLR_S 4 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_M (BIT(3)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_WR_CLR_S 3 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_M (BIT(2)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_RD_CLR_S 2 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_M (BIT(1)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_WR_CLR_S 1 +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_M (BIT(0)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_V 0x1 +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_RD_CLR_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0A0) +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0A4) +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0A8) +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0AC) +/* ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S)) +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_DRAM0_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0B0) +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MIN_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0B4) +/* ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_0_MAX_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0B8) +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MIN_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0BC) +/* ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_M ((ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V) << (ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S)) +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PIF_1_MAX_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0C0) +/* ASSIST_DEBUG_CORE_1_AREA_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PC_M ((ASSIST_DEBUG_CORE_1_AREA_PC_V) << (ASSIST_DEBUG_CORE_1_AREA_PC_S)) +#define ASSIST_DEBUG_CORE_1_AREA_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_PC_S 0 + +#define ASSIST_DEBUG_CORE_1_AREA_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0C4) +/* ASSIST_DEBUG_CORE_1_AREA_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_AREA_SP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_SP_M ((ASSIST_DEBUG_CORE_1_AREA_SP_V) << (ASSIST_DEBUG_CORE_1_AREA_SP_S)) +#define ASSIST_DEBUG_CORE_1_AREA_SP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_AREA_SP_S 0 + +#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0C8) +/* ASSIST_DEBUG_CORE_1_SP_UNSTABLE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE 0x000000FF +#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_M ((ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V) << (ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S)) +#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_V 0xFF +#define ASSIST_DEBUG_CORE_1_SP_UNSTABLE_S 0 + +#define ASSIST_DEBUG_CORE_1_SP_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0CC) +/* ASSIST_DEBUG_CORE_1_SP_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_SP_MIN_M ((ASSIST_DEBUG_CORE_1_SP_MIN_V) << (ASSIST_DEBUG_CORE_1_SP_MIN_S)) +#define ASSIST_DEBUG_CORE_1_SP_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_SP_MIN_S 0 + +#define ASSIST_DEBUG_CORE_1_SP_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0D0) +/* ASSIST_DEBUG_CORE_1_SP_MAX : R/W ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_SP_MAX_M ((ASSIST_DEBUG_CORE_1_SP_MAX_V) << (ASSIST_DEBUG_CORE_1_SP_MAX_S)) +#define ASSIST_DEBUG_CORE_1_SP_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_SP_MAX_S 0 + +#define ASSIST_DEBUG_CORE_1_SP_PC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0D4) +/* ASSIST_DEBUG_CORE_1_SP_PC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_SP_PC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_SP_PC_M ((ASSIST_DEBUG_CORE_1_SP_PC_V) << (ASSIST_DEBUG_CORE_1_SP_PC_S)) +#define ASSIST_DEBUG_CORE_1_SP_PC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_SP_PC_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0D8) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE (BIT(0)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_M (BIT(0)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_V 0x1 +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGENABLE_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0DC) +/* ASSIST_DEBUG_CORE_1_RCD_RECORDING : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_RECORDING (BIT(0)) +#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_M (BIT(0)) +#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_V 0x1 +#define ASSIST_DEBUG_CORE_1_RCD_RECORDING_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0E0) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGINST_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0E4) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS 0x000000FF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_V 0xFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGSTATUS_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0E8) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGDATA_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0EC) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGPC_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0F0) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0STAT_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0F4) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0ADDR_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0F8) +/* ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_M ((ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V) << (ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S)) +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_PDEBUGLS0DATA_S 0 + +#define ASSIST_DEBUG_CORE_1_RCD_SP_REG (DR_REG_ASSIST_DEBUG_BASE + 0x0FC) +/* ASSIST_DEBUG_CORE_1_RCD_SP : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_RCD_SP 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_SP_M ((ASSIST_DEBUG_CORE_1_RCD_SP_V) << (ASSIST_DEBUG_CORE_1_RCD_SP_S)) +#define ASSIST_DEBUG_CORE_1_RCD_SP_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_RCD_SP_S 0 + +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x100) +/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0 (BIT(25)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_M (BIT(25)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_0_S 25 +/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0 (BIT(24)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_M (BIT(24)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_0_S 24 +/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0 0x00FFFFFF +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_1_IRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x104) +/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1 (BIT(25)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_M (BIT(25)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_LOADSTORE_1_S 25 +/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1 (BIT(24)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_M (BIT(24)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_WR_1_S 24 +/* ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 : RO ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1 0x00FFFFFF +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_V 0xFFFFFF +#define ASSIST_DEBUG_CORE_1_IRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x108) +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0 (BIT(22)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_M (BIT(22)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_V 0x1 +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_0_S 22 +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 : RO ;bitpos:[21:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0 0x003FFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_V 0x3FFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_0_S 0 + +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x10C) +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 : RO ;bitpos:[15:0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0 0x0000FFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_V 0xFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_0_S 0 + +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x110) +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_0_S 0 + +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x114) +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1 (BIT(22)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_M (BIT(22)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_V 0x1 +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_WR_1_S 22 +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 : RO ;bitpos:[21:0] ;default: 24'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1 0x003FFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_V 0x3FFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_ADDR_1_S 0 + +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_4_REG (DR_REG_ASSIST_DEBUG_BASE + 0x118) +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 : RO ;bitpos:[15:0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1 0x0000FFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_V 0xFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_BYTEEN_1_S 0 + +#define ASSIST_DEBUG_CORE_1_DRAM0_EXCEPTION_MONITOR_5_REG (DR_REG_ASSIST_DEBUG_BASE + 0x11C) +/* ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 : RO ;bitpos:[31:0] ;default: ~32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_M ((ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V) << (ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S)) +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_V 0xFFFFFFFF +#define ASSIST_DEBUG_CORE_1_DRAM0_RECORDING_PC_1_S 0 + +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x120) +/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0 0x000FFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V) << (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S)) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_V 0xFFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0_S 0 + +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x124) +/* ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 : R/W ;bitpos:[19:0] ;default: ~20'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1 0x000FFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_M ((ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V) << (ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S)) +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_V 0xFFFFF +#define ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1_S 0 + +#define ASSIST_DEBUG_LOG_SETTING_REG (DR_REG_ASSIST_DEBUG_BASE + 0x128) +/* ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE (BIT(6)) +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_M (BIT(6)) +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_V 0x1 +#define ASSIST_DEBUG_LOG_MEM_LOOP_ENABLE_S 6 +/* ASSIST_DEBUG_LOG_MODE : R/W ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MODE 0x00000007 +#define ASSIST_DEBUG_LOG_MODE_M ((ASSIST_DEBUG_LOG_MODE_V) << (ASSIST_DEBUG_LOG_MODE_S)) +#define ASSIST_DEBUG_LOG_MODE_V 0x7 +#define ASSIST_DEBUG_LOG_MODE_S 3 +/* ASSIST_DEBUG_LOG_ENA : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_ENA 0x00000007 +#define ASSIST_DEBUG_LOG_ENA_M ((ASSIST_DEBUG_LOG_ENA_V) << (ASSIST_DEBUG_LOG_ENA_S)) +#define ASSIST_DEBUG_LOG_ENA_V 0x7 +#define ASSIST_DEBUG_LOG_ENA_S 0 + +#define ASSIST_DEBUG_LOG_DATA_0_REG (DR_REG_ASSIST_DEBUG_BASE + 0x12C) +/* ASSIST_DEBUG_LOG_DATA_0 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_DATA_0 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_0_M ((ASSIST_DEBUG_LOG_DATA_0_V) << (ASSIST_DEBUG_LOG_DATA_0_S)) +#define ASSIST_DEBUG_LOG_DATA_0_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_0_S 0 + +#define ASSIST_DEBUG_LOG_DATA_1_REG (DR_REG_ASSIST_DEBUG_BASE + 0x130) +/* ASSIST_DEBUG_LOG_DATA_1 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_DATA_1 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_1_M ((ASSIST_DEBUG_LOG_DATA_1_V) << (ASSIST_DEBUG_LOG_DATA_1_S)) +#define ASSIST_DEBUG_LOG_DATA_1_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_1_S 0 + +#define ASSIST_DEBUG_LOG_DATA_2_REG (DR_REG_ASSIST_DEBUG_BASE + 0x134) +/* ASSIST_DEBUG_LOG_DATA_2 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_DATA_2 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_2_M ((ASSIST_DEBUG_LOG_DATA_2_V) << (ASSIST_DEBUG_LOG_DATA_2_S)) +#define ASSIST_DEBUG_LOG_DATA_2_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_2_S 0 + +#define ASSIST_DEBUG_LOG_DATA_3_REG (DR_REG_ASSIST_DEBUG_BASE + 0x138) +/* ASSIST_DEBUG_LOG_DATA_3 : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_DATA_3 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_3_M ((ASSIST_DEBUG_LOG_DATA_3_V) << (ASSIST_DEBUG_LOG_DATA_3_S)) +#define ASSIST_DEBUG_LOG_DATA_3_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_DATA_3_S 0 + +#define ASSIST_DEBUG_LOG_DATA_MASK_REG (DR_REG_ASSIST_DEBUG_BASE + 0x13C) +/* ASSIST_DEBUG_LOG_DATA_SIZE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_DATA_SIZE 0x0000FFFF +#define ASSIST_DEBUG_LOG_DATA_SIZE_M ((ASSIST_DEBUG_LOG_DATA_SIZE_V) << (ASSIST_DEBUG_LOG_DATA_SIZE_S)) +#define ASSIST_DEBUG_LOG_DATA_SIZE_V 0xFFFF +#define ASSIST_DEBUG_LOG_DATA_SIZE_S 0 + +#define ASSIST_DEBUG_LOG_MIN_REG (DR_REG_ASSIST_DEBUG_BASE + 0x140) +/* ASSIST_DEBUG_LOG_MIN : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MIN 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MIN_M ((ASSIST_DEBUG_LOG_MIN_V) << (ASSIST_DEBUG_LOG_MIN_S)) +#define ASSIST_DEBUG_LOG_MIN_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MIN_S 0 + +#define ASSIST_DEBUG_LOG_MAX_REG (DR_REG_ASSIST_DEBUG_BASE + 0x144) +/* ASSIST_DEBUG_LOG_MAX : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MAX 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MAX_M ((ASSIST_DEBUG_LOG_MAX_V) << (ASSIST_DEBUG_LOG_MAX_S)) +#define ASSIST_DEBUG_LOG_MAX_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MAX_S 0 + +#define ASSIST_DEBUG_LOG_MEM_START_REG (DR_REG_ASSIST_DEBUG_BASE + 0x148) +/* ASSIST_DEBUG_LOG_MEM_START : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_START 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_START_M ((ASSIST_DEBUG_LOG_MEM_START_V) << (ASSIST_DEBUG_LOG_MEM_START_S)) +#define ASSIST_DEBUG_LOG_MEM_START_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_START_S 0 + +#define ASSIST_DEBUG_LOG_MEM_END_REG (DR_REG_ASSIST_DEBUG_BASE + 0x14C) +/* ASSIST_DEBUG_LOG_MEM_END : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_END 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_END_M ((ASSIST_DEBUG_LOG_MEM_END_V) << (ASSIST_DEBUG_LOG_MEM_END_S)) +#define ASSIST_DEBUG_LOG_MEM_END_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_END_S 0 + +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG (DR_REG_ASSIST_DEBUG_BASE + 0x150) +/* ASSIST_DEBUG_LOG_MEM_WRITING_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_M ((ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V) << (ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S)) +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_V 0xFFFFFFFF +#define ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_S 0 + +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG (DR_REG_ASSIST_DEBUG_BASE + 0x154) +/* ASSIST_DEBUG_LOG_MEM_FULL_FLAG : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG (BIT(0)) +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_M (BIT(0)) +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_V 0x1 +#define ASSIST_DEBUG_LOG_MEM_FULL_FLAG_S 0 + +#define ASSIST_DEBUG_DATE_REG (DR_REG_ASSIST_DEBUG_BASE + 0x1FC) +/* ASSIST_DEBUG_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003040 ; */ +/*description: */ +#define ASSIST_DEBUG_DATE 0x0FFFFFFF +#define ASSIST_DEBUG_DATE_M ((ASSIST_DEBUG_DATE_V) << (ASSIST_DEBUG_DATE_S)) +#define ASSIST_DEBUG_DATE_V 0xFFFFFFF +#define ASSIST_DEBUG_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/assist_debug_struct.h b/components/soc/soc/esp32s3/include/soc/assist_debug_struct.h new file mode 100644 index 000000000..d5adb9f27 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/assist_debug_struct.h @@ -0,0 +1,463 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t core_0_area_dram0_0_rd_ena: 1; + uint32_t core_0_area_dram0_0_wr_ena: 1; + uint32_t core_0_area_dram0_1_rd_ena: 1; + uint32_t core_0_area_dram0_1_wr_ena: 1; + uint32_t core_0_area_pif_0_rd_ena: 1; + uint32_t core_0_area_pif_0_wr_ena: 1; + uint32_t core_0_area_pif_1_rd_ena: 1; + uint32_t core_0_area_pif_1_wr_ena: 1; + uint32_t core_0_sp_spill_min_ena: 1; + uint32_t core_0_sp_spill_max_ena: 1; + uint32_t core_0_iram0_exception_monitor_ena: 1; + uint32_t core_0_dram0_exception_monitor_ena: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_interrupt_ena; + union { + struct { + uint32_t core_0_area_dram0_0_rd_raw: 1; + uint32_t core_0_area_dram0_0_wr_raw: 1; + uint32_t core_0_area_dram0_1_rd_raw: 1; + uint32_t core_0_area_dram0_1_wr_raw: 1; + uint32_t core_0_area_pif_0_rd_raw: 1; + uint32_t core_0_area_pif_0_wr_raw: 1; + uint32_t core_0_area_pif_1_rd_raw: 1; + uint32_t core_0_area_pif_1_wr_raw: 1; + uint32_t core_0_sp_spill_min_raw: 1; + uint32_t core_0_sp_spill_max_raw: 1; + uint32_t core_0_iram0_exception_monitor_raw: 1; + uint32_t core_0_dram0_exception_monitor_raw: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_interrupt_raw; + union { + struct { + uint32_t core_0_area_dram0_0_rd_rls: 1; + uint32_t core_0_area_dram0_0_wr_rls: 1; + uint32_t core_0_area_dram0_1_rd_rls: 1; + uint32_t core_0_area_dram0_1_wr_rls: 1; + uint32_t core_0_area_pif_0_rd_rls: 1; + uint32_t core_0_area_pif_0_wr_rls: 1; + uint32_t core_0_area_pif_1_rd_rls: 1; + uint32_t core_0_area_pif_1_wr_rls: 1; + uint32_t core_0_sp_spill_min_rls: 1; + uint32_t core_0_sp_spill_max_rls: 1; + uint32_t core_0_iram0_exception_monitor_rls: 1; + uint32_t core_0_dram0_exception_monitor_rls: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_interrupt_rls; + union { + struct { + uint32_t core_0_area_dram0_0_rd_clr: 1; + uint32_t core_0_area_dram0_0_wr_clr: 1; + uint32_t core_0_area_dram0_1_rd_clr: 1; + uint32_t core_0_area_dram0_1_wr_clr: 1; + uint32_t core_0_area_pif_0_rd_clr: 1; + uint32_t core_0_area_pif_0_wr_clr: 1; + uint32_t core_0_area_pif_1_rd_clr: 1; + uint32_t core_0_area_pif_1_wr_clr: 1; + uint32_t core_0_sp_spill_min_clr: 1; + uint32_t core_0_sp_spill_max_clr: 1; + uint32_t core_0_iram0_exception_monitor_clr: 1; + uint32_t core_0_dram0_exception_monitor_clr: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_interrupt_clr; + uint32_t core_0_area_dram0_0_min; /**/ + uint32_t core_0_area_dram0_0_max; /**/ + uint32_t core_0_area_dram0_1_min; /**/ + uint32_t core_0_area_dram0_1_max; /**/ + uint32_t core_0_area_pif_0_min; /**/ + uint32_t core_0_area_pif_0_max; /**/ + uint32_t core_0_area_pif_1_min; /**/ + uint32_t core_0_area_pif_1_max; /**/ + uint32_t core_0_area_sp; /**/ + uint32_t core_0_area_pc; /**/ + union { + struct { + uint32_t core_0_sp_unstable: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } core_0_sp_unstable; + uint32_t core_0_sp_min; /**/ + uint32_t core_0_sp_max; /**/ + uint32_t core_0_sp_pc; /**/ + union { + struct { + uint32_t core_0_rcd_pdebugenable: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_rcd_pdebugenable; + union { + struct { + uint32_t core_0_rcd_recording: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_rcd_recording; + uint32_t core_0_rcd_pdebuginst; /**/ + union { + struct { + uint32_t core_0_rcd_pdebugstatus: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } core_0_rcd_pdebugstatus; + uint32_t core_0_rcd_pdebugdata; /**/ + uint32_t core_0_rcd_pdebugpc; /**/ + uint32_t core_0_rcd_pdebugls0stat; /**/ + uint32_t core_0_rcd_pdebugls0addr; /**/ + uint32_t core_0_rcd_pdebugls0data; /**/ + uint32_t core_0_rcd_sp; /**/ + union { + struct { + uint32_t core_0_iram0_recording_addr_0: 24; + uint32_t core_0_iram0_recording_wr_0: 1; + uint32_t core_0_iram0_recording_loadstore_0: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } core_0_iram0_exception_monitor_0; + union { + struct { + uint32_t core_0_iram0_recording_addr_1: 24; + uint32_t core_0_iram0_recording_wr_1: 1; + uint32_t core_0_iram0_recording_loadstore_1: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } core_0_iram0_exception_monitor_1; + union { + struct { + uint32_t core_0_dram0_recording_addr_0: 22; + uint32_t core_0_dram0_recording_wr_0: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } core_0_dram0_exception_monitor_0; + union { + struct { + uint32_t core_0_dram0_recording_byteen_0: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } core_0_dram0_exception_monitor_1; + uint32_t core_0_dram0_exception_monitor_2; /**/ + union { + struct { + uint32_t core_0_dram0_recording_addr_1: 22; + uint32_t core_0_dram0_recording_wr_1: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } core_0_dram0_exception_monitor_3; + union { + struct { + uint32_t core_0_dram0_recording_byteen_1: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } core_0_dram0_exception_monitor_4; + uint32_t core_0_dram0_exception_monitor_5; /**/ + union { + struct { + uint32_t core_1_area_dram0_0_rd_ena: 1; + uint32_t core_1_area_dram0_0_wr_ena: 1; + uint32_t core_1_area_dram0_1_rd_ena: 1; + uint32_t core_1_area_dram0_1_wr_ena: 1; + uint32_t core_1_area_pif_0_rd_ena: 1; + uint32_t core_1_area_pif_0_wr_ena: 1; + uint32_t core_1_area_pif_1_rd_ena: 1; + uint32_t core_1_area_pif_1_wr_ena: 1; + uint32_t core_1_sp_spill_min_ena: 1; + uint32_t core_1_sp_spill_max_ena: 1; + uint32_t core_1_iram0_exception_monitor_ena: 1; + uint32_t core_1_dram0_exception_monitor_ena: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_1_interrupt_ena; + union { + struct { + uint32_t core_1_area_dram0_0_rd_raw: 1; + uint32_t core_1_area_dram0_0_wr_raw: 1; + uint32_t core_1_area_dram0_1_rd_raw: 1; + uint32_t core_1_area_dram0_1_wr_raw: 1; + uint32_t core_1_area_pif_0_rd_raw: 1; + uint32_t core_1_area_pif_0_wr_raw: 1; + uint32_t core_1_area_pif_1_rd_raw: 1; + uint32_t core_1_area_pif_1_wr_raw: 1; + uint32_t core_1_sp_spill_min_raw: 1; + uint32_t core_1_sp_spill_max_raw: 1; + uint32_t core_1_iram0_exception_monitor_raw: 1; + uint32_t core_1_dram0_exception_monitor_raw: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_1_interrupt_raw; + union { + struct { + uint32_t core_1_area_dram0_0_rd_rls: 1; + uint32_t core_1_area_dram0_0_wr_rls: 1; + uint32_t core_1_area_dram0_1_rd_rls: 1; + uint32_t core_1_area_dram0_1_wr_rls: 1; + uint32_t core_1_area_pif_0_rd_rls: 1; + uint32_t core_1_area_pif_0_wr_rls: 1; + uint32_t core_1_area_pif_1_rd_rls: 1; + uint32_t core_1_area_pif_1_wr_rls: 1; + uint32_t core_1_sp_spill_min_rls: 1; + uint32_t core_1_sp_spill_max_rls: 1; + uint32_t core_1_iram0_exception_monitor_rls: 1; + uint32_t core_1_dram0_exception_monitor_rls: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_1_interrupt_rls; + union { + struct { + uint32_t core_1_area_dram0_0_rd_clr: 1; + uint32_t core_1_area_dram0_0_wr_clr: 1; + uint32_t core_1_area_dram0_1_rd_clr: 1; + uint32_t core_1_area_dram0_1_wr_clr: 1; + uint32_t core_1_area_pif_0_rd_clr: 1; + uint32_t core_1_area_pif_0_wr_clr: 1; + uint32_t core_1_area_pif_1_rd_clr: 1; + uint32_t core_1_area_pif_1_wr_clr: 1; + uint32_t core_1_sp_spill_min_clr: 1; + uint32_t core_1_sp_spill_max_clr: 1; + uint32_t core_1_iram0_exception_monitor_clr: 1; + uint32_t core_1_dram0_exception_monitor_clr: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_1_interrupt_clr; + uint32_t core_1_area_dram0_0_min; /**/ + uint32_t core_1_area_dram0_0_max; /**/ + uint32_t core_1_area_dram0_1_min; /**/ + uint32_t core_1_area_dram0_1_max; /**/ + uint32_t core_1_area_pif_0_min; /**/ + uint32_t core_1_area_pif_0_max; /**/ + uint32_t core_1_area_pif_1_min; /**/ + uint32_t core_1_area_pif_1_max; /**/ + uint32_t core_1_area_pc; /**/ + uint32_t core_1_area_sp; /**/ + union { + struct { + uint32_t core_1_sp_unstable: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } core_1_sp_unstable; + uint32_t core_1_sp_min; /**/ + uint32_t core_1_sp_max; /**/ + uint32_t core_1_sp_pc; /**/ + union { + struct { + uint32_t core_1_rcd_pdebugenable: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_rcd_pdebugenable; + union { + struct { + uint32_t core_1_rcd_recording: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_rcd_recording; + uint32_t core_1_rcd_pdebuginst; /**/ + union { + struct { + uint32_t core_1_rcd_pdebugstatus: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } core_1_rcd_pdebugstatus; + uint32_t core_1_rcd_pdebugdata; /**/ + uint32_t core_1_rcd_pdebugpc; /**/ + uint32_t core_1_rcd_pdebugls0stat; /**/ + uint32_t core_1_rcd_pdebugls0addr; /**/ + uint32_t core_1_rcd_pdebugls0data; /**/ + uint32_t core_1_rcd_sp; /**/ + union { + struct { + uint32_t core_1_iram0_recording_addr_0: 24; + uint32_t core_1_iram0_recording_wr_0: 1; + uint32_t core_1_iram0_recording_loadstore_0: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } core_1_iram0_exception_monitor_0; + union { + struct { + uint32_t core_1_iram0_recording_addr_1: 24; + uint32_t core_1_iram0_recording_wr_1: 1; + uint32_t core_1_iram0_recording_loadstore_1: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } core_1_iram0_exception_monitor_1; + union { + struct { + uint32_t core_1_dram0_recording_addr_0: 22; + uint32_t core_1_dram0_recording_wr_0: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } core_1_dram0_exception_monitor_0; + union { + struct { + uint32_t core_1_dram0_recording_byteen_0: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } core_1_dram0_exception_monitor_1; + uint32_t core_1_dram0_exception_monitor_2; /**/ + union { + struct { + uint32_t core_1_dram0_recording_addr_1: 22; + uint32_t core_1_dram0_recording_wr_1: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } core_1_dram0_exception_monitor_3; + union { + struct { + uint32_t core_1_dram0_recording_byteen_1: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } core_1_dram0_exception_monitor_4; + uint32_t core_1_dram0_exception_monitor_5; /**/ + union { + struct { + uint32_t core_x_iram0_dram0_limit_cycle_0: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } core_x_iram0_dram0_exception_monitor_0; + union { + struct { + uint32_t core_x_iram0_dram0_limit_cycle_1: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } core_x_iram0_dram0_exception_monitor_1; + union { + struct { + uint32_t log_ena: 3; + uint32_t log_mode: 3; + uint32_t log_mem_loop_enable: 1; + uint32_t reserved7: 25; + }; + uint32_t val; + } log_setting; + uint32_t log_data_0; /**/ + uint32_t log_data_1; /**/ + uint32_t log_data_2; /**/ + uint32_t log_data_3; /**/ + union { + struct { + uint32_t log_data_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } log_data_mask; + uint32_t log_min; /**/ + uint32_t log_max; /**/ + uint32_t log_mem_start; /**/ + uint32_t log_mem_end; /**/ + uint32_t log_mem_writing_addr; /**/ + union { + struct { + uint32_t log_mem_full_flag: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } log_mem_full_flag; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} assist_debug_dev_t; + +extern assist_debug_dev_t ASSIST_DEBUG; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/bb_reg.h b/components/soc/soc/esp32s3/include/soc/bb_reg.h new file mode 100644 index 000000000..186b6f0d2 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/bb_reg.h @@ -0,0 +1,37 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/* Some of the baseband control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define BBPD_CTRL (DR_REG_BB_BASE + 0x0054) +#define BB_FFT_FORCE_PU (BIT(3)) +#define BB_FFT_FORCE_PU_M (BIT(3)) +#define BB_FFT_FORCE_PU_V 1 +#define BB_FFT_FORCE_PU_S 3 +#define BB_FFT_FORCE_PD (BIT(2)) +#define BB_FFT_FORCE_PD_M (BIT(2)) +#define BB_FFT_FORCE_PD_V 1 +#define BB_FFT_FORCE_PD_S 2 +#define BB_DC_EST_FORCE_PU (BIT(1)) +#define BB_DC_EST_FORCE_PU_M (BIT(1)) +#define BB_DC_EST_FORCE_PU_V 1 +#define BB_DC_EST_FORCE_PU_S 1 +#define BB_DC_EST_FORCE_PD (BIT(0)) +#define BB_DC_EST_FORCE_PD_M (BIT(0)) +#define BB_DC_EST_FORCE_PD_V 1 +#define BB_DC_EST_FORCE_PD_S 0 diff --git a/components/soc/soc/esp32s3/include/soc/boot_mode.h b/components/soc/soc/esp32s3/include/soc/boot_mode.h new file mode 100644 index 000000000..d66451f43 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/boot_mode.h @@ -0,0 +1,98 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc.h" + +/*SPI Boot*/ +#define IS_1XXX(v) (((v)&0x08)==0x08) + +/*Download Boot, USB/SPI(or SDIO_V2)/UART0/UART1*/ +#define IS_00XX(v) (((v)&0x0c)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_FEO V2*/ +#define IS_0000(v) (((v)&0x0f)==0x00) + +/*Download Boot, SDIO/UART0/UART1,FEI_REO V2*/ +#define IS_0001(v) (((v)&0x0f)==0x01) + +/*Download Boot, SDIO/UART0/UART1,REI_FEO V2*/ +#define IS_0010(v) (((v)&0x0f)==0x02) + +/*Download Boot, SDIO/UART0/UART1,REI_REO V2*/ +#define IS_0011(v) (((v)&0x0f)==0x03) + +/*legacy SPI Boot*/ +#define IS_0100(v) (((v)&0x0f)==0x04) + +/*ATE/ANALOG Mode*/ +#define IS_0101(v) (((v)&0x0f)==0x05) + +/*SPI(or SDIO_V1) download Mode*/ +#define IS_0110(v) (((v)&0x0f)==0x06) + +/*Diagnostic Mode+UART0 download Mode*/ +#define IS_0111(v) (((v)&0x0f)==0x07) + + + +#define BOOT_MODE_GET() (GPIO_REG_READ(GPIO_STRAP_REG)) + +/*do not include download mode*/ +#define ETS_IS_UART_BOOT() IS_0111(BOOT_MODE_GET()) + +/*all spi boot including spi/legacy*/ +#define ETS_IS_FLASH_BOOT() (IS_1XXX(BOOT_MODE_GET()) || IS_0100(BOOT_MODE_GET())) + +/*all faster spi boot including spi*/ +#define ETS_IS_FAST_FLASH_BOOT() IS_1XXX(BOOT_MODE_GET()) + +#if SUPPORT_SDIO_DOWNLOAD + +/*all sdio V2 of failing edge input, failing edge output*/ +#define ETS_IS_SDIO_FEI_FEO_V2_BOOT() IS_0000(BOOT_MODE_GET()) + +/*all sdio V2 of failing edge input, raising edge output*/ +#define ETS_IS_SDIO_FEI_REO_V2_BOOT() IS_0001(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V2_BOOT() IS_0010(BOOT_MODE_GET()) + +/*all sdio V2 of raising edge input, raising edge output*/ +#define ETS_IS_SDIO_REI_REO_V2_BOOT() IS_0011(BOOT_MODE_GET()) + +/*all sdio V1 of raising edge input, failing edge output*/ +#define ETS_IS_SDIO_REI_FEO_V1_BOOT() IS_0110(BOOT_MODE_GET()) + +/*do not include joint download mode*/ +#define ETS_IS_SDIO_BOOT() IS_0110(BOOT_MODE_GET()) +#else + +/*do not include joint download mode*/ +#define ETS_IS_SPI_DOWNLOAD_BOOT() IS_0110(BOOT_MODE_GET()) + +#endif + +/*joint download boot*/ +#define ETS_IS_JOINT_DOWNLOAD_BOOT() IS_00XX(BOOT_MODE_GET()) + +/*ATE mode*/ +#define ETS_IS_ATE_BOOT() IS_0101(BOOT_MODE_GET()) + +/*used by ETS_IS_SDIO_UART_BOOT*/ +#define SEL_NO_BOOT 0 +#define SEL_SDIO_BOOT BIT0 +#define SEL_UART_BOOT BIT1 +#define SEL_SPI_SLAVE_BOOT BIT2 diff --git a/components/soc/soc/esp32s3/include/soc/brownout_caps.h b/components/soc/soc/esp32s3/include/soc/brownout_caps.h new file mode 100644 index 000000000..797d33ebb --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/brownout_caps.h @@ -0,0 +1,25 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_BROWNOUT_RESET_SUPPORTED 1 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/cache_memory.h b/components/soc/soc/esp32s3/include/soc/cache_memory.h new file mode 100644 index 000000000..e94b97e91 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/cache_memory.h @@ -0,0 +1,103 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +/*IRAM0 is connected with Cache IBUS0*/ +#define IRAM0_ADDRESS_LOW 0x40000000 +#define IRAM0_ADDRESS_HIGH 0x44000000 +#define IRAM0_CACHE_ADDRESS_LOW 0x42000000 +#define IRAM0_CACHE_ADDRESS_HIGH 0x44000000 + +/*DRAM0 is connected with Cache DBUS0*/ +#define DRAM0_ADDRESS_LOW 0x3C000000 +#define DRAM0_ADDRESS_HIGH 0x40000000 +#define DRAM0_CACHE_ADDRESS_LOW 0x3C000000 +#define DRAM0_CACHE_ADDRESS_HIGH 0x3E000000 +#define DRAM0_CACHE_OPERATION_HIGH DRAM0_CACHE_ADDRESS_HIGH +#define ESP_CACHE_TEMP_ADDR 0x3C800000 + +#define BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW) +#define ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH) + +#define ADDRESS_IN_IRAM0(vaddr) ADDRESS_IN_BUS(IRAM0, vaddr) +#define ADDRESS_IN_IRAM0_CACHE(vaddr) ADDRESS_IN_BUS(IRAM0_CACHE, vaddr) +#define ADDRESS_IN_DRAM0(vaddr) ADDRESS_IN_BUS(DRAM0, vaddr) +#define ADDRESS_IN_DRAM0_CACHE(vaddr) ADDRESS_IN_BUS(DRAM0_CACHE, vaddr) + +#define BUS_IRAM0_CACHE_SIZE BUS_SIZE(IRAM0_CACHE) +#define BUS_DRAM0_CACHE_SIZE BUS_SIZE(DRAM0_CACHE) + +#define CACHE_IBUS 0 +#define CACHE_IBUS_MMU_START 0 +#define CACHE_IBUS_MMU_END 0x800 + +#define CACHE_DBUS 1 +#define CACHE_DBUS_MMU_START 0 +#define CACHE_DBUS_MMU_END 0x800 + +#define CACHE_IROM_MMU_START 0 +#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End() +#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START) + +#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END +#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End() +#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START) + +#define CACHE_DROM_MMU_MAX_END 0x400 + +#define MMU_SIZE 0x800 +#define ICACHE_MMU_SIZE 0x800 +#define DCACHE_MMU_SIZE 0x800 + +#define MMU_BUS_START(i) 0 +#define MMU_BUS_SIZE(i) 0x800 + +#define MMU_INVALID BIT(14) +#define MMU_TYPE BIT(15) +#define MMU_ACCESS_FLASH 0 +#define MMU_ACCESS_SPIRAM BIT(15) + +#define CACHE_MAX_SYNC_NUM 0x400000 +#define CACHE_MAX_LOCK_NUM 0x8000 + +#define FLASH_MMU_TABLE ((volatile uint32_t*) DR_REG_MMU_TABLE) +#define FLASH_MMU_TABLE_SIZE (ICACHE_MMU_SIZE/sizeof(uint32_t)) + +#define MMU_TABLE_INVALID_VAL 0x4000 +#define FLASH_MMU_TABLE_INVALID_VAL DPORT_MMU_TABLE_INVALID_VAL +#define MMU_ADDRESS_MASK 0x3fff +#define MMU_PAGE_SIZE 0x10000 +#define INVALID_PHY_PAGE 0xffff + +#define BUS_ADDR_SIZE 0x2000000 +#define BUS_ADDR_MASK (BUS_ADDR_SIZE - 1) + +#define CACHE_ICACHE_LOW_SHIFT 0 +#define CACHE_ICACHE_HIGH_SHIFT 2 +#define CACHE_DCACHE_LOW_SHIFT 4 +#define CACHE_DCACHE_HIGH_SHIFT 6 + +#define CACHE_MEMORY_IBANK0_ADDR 0x40370000 +#define CACHE_MEMORY_IBANK1_ADDR 0x40374000 + +#define CACHE_MEMORY_DBANK0_ADDR 0x3fcf0000 +#define CACHE_MEMORY_DBANK1_ADDR 0x3fcf8000 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/clkout_channel.h b/components/soc/soc/esp32s3/include/soc/clkout_channel.h new file mode 100644 index 000000000..6ddaeb13e --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/clkout_channel.h @@ -0,0 +1,23 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +//CLKOUT channels +#define CLKOUT_GPIO20_DIRECT_CHANNEL CLKOUT_CHANNEL_1 +#define CLKOUT_CHANNEL_1_DIRECT_GPIO_NUM 20 +#define CLKOUT_GPIO19_DIRECT_CHANNEL CLKOUT_CHANNEL_2 +#define CLKOUT_CHANNEL_2_DIRECT_GPIO_NUM 19 +#define CLKOUT_GPIO18_DIRECT_CHANNEL CLKOUT_CHANNEL_3 +#define CLKOUT_CHANNEL_3_DIRECT_GPIO_NUM 18 diff --git a/components/soc/soc/esp32s3/include/soc/cpu.h b/components/soc/soc/esp32s3/include/soc/cpu.h new file mode 100644 index 000000000..ad7f7c11d --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/cpu.h @@ -0,0 +1,131 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include +#include +#include "xtensa/corebits.h" + +/* C macros for xtensa special register read/write/exchange */ + +#define RSR(reg, curval) asm volatile ("rsr %0, " #reg : "=r" (curval)); +#define WSR(reg, newval) asm volatile ("wsr %0, " #reg : : "r" (newval)); +#define XSR(reg, swapval) asm volatile ("xsr %0, " #reg : "+r" (swapval)); + +/** @brief Read current stack pointer address + * + */ +static inline void *get_sp(void) +{ + void *sp; + asm volatile ("mov %0, sp;" : "=r" (sp)); + return sp; +} + +/* Functions to set page attributes for Region Protection option in the CPU. + * See Xtensa ISA Reference manual for explanation of arguments (section 4.6.3.2). + */ + +static inline void cpu_write_dtlb(uint32_t vpn, unsigned attr) +{ + asm volatile ("wdtlb %1, %0; dsync\n" :: "r" (vpn), "r" (attr)); +} + + +static inline void cpu_write_itlb(unsigned vpn, unsigned attr) +{ + asm volatile ("witlb %1, %0; isync\n" :: "r" (vpn), "r" (attr)); +} + +/** + * @brief Configure memory region protection + * + * Make page 0 access raise an exception. + * Also protect some other unused pages so we can catch weirdness. + * Useful attribute values: + * 0 — cached, RW + * 2 — bypass cache, RWX (default value after CPU reset) + * 15 — no access, raise exception + */ + +static inline void cpu_configure_region_protection(void) +{ + const uint32_t pages_to_protect[] = {0x00000000, 0x80000000, 0xa0000000, 0xc0000000, 0xe0000000}; + for (int i = 0; i < sizeof(pages_to_protect) / sizeof(pages_to_protect[0]); ++i) { + cpu_write_dtlb(pages_to_protect[i], 0xf); + cpu_write_itlb(pages_to_protect[i], 0xf); + } + cpu_write_dtlb(0x20000000, 0); + cpu_write_itlb(0x20000000, 0); +} + +/** + * @brief Stall CPU using RTC controller + * @param cpu_id ID of the CPU to stall (0 = PRO, 1 = APP) + */ +void esp_cpu_stall(int cpu_id); + +/** + * @brief Un-stall CPU using RTC controller + * @param cpu_id ID of the CPU to un-stall (0 = PRO, 1 = APP) + */ +void esp_cpu_unstall(int cpu_id); + +/** + * @brief Reset CPU using RTC controller + * @param cpu_id ID of the CPU to reset (0 = PRO, 1 = APP) + */ +void esp_cpu_reset(int cpu_id); + + +/** + * @brief Returns true if a JTAG debugger is attached to CPU + * OCD (on chip debug) port. + * + * @note If "Make exception and panic handlers JTAG/OCD aware" + * is disabled, this function always returns false. + */ +bool esp_cpu_in_ocd_debug_mode(void); + +/** + * @brief Convert the PC register value to its true address + * + * The address of the current instruction is not stored as an exact uint32_t + * representation in PC register. This function will convert the value stored in + * the PC register to a uint32_t address. + * + * @param pc_raw The PC as stored in register format. + * + * @return Address in uint32_t format + */ +static inline uint32_t esp_cpu_process_stack_pc(uint32_t pc) +{ + if (pc & 0x80000000) { + //Top two bits of a0 (return address) specify window increment. Overwrite to map to address space. + pc = (pc & 0x3fffffff) | 0x40000000; + } + //Minus 3 to get PC of previous instruction (i.e. instruction executed before return address) + return pc - 3; +} + +typedef uint32_t esp_cpu_ccount_t; + +static inline esp_cpu_ccount_t esp_cpu_get_ccount(void) +{ + uint32_t result; + RSR(CCOUNT, result); + return result; +} diff --git a/components/soc/soc/esp32s3/include/soc/cpu_caps.h b/components/soc/soc/esp32s3/include/soc/cpu_caps.h new file mode 100644 index 000000000..fbfd780bd --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/cpu_caps.h @@ -0,0 +1,20 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_CPU_BREAKPOINTS_NUM 2 +#define SOC_CPU_WATCHPOINTS_NUM 2 + +#define SOC_CPU_WATCHPOINT_SIZE 64 // bytes \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/dac_caps.h b/components/soc/soc/esp32s3/include/soc/dac_caps.h new file mode 100644 index 000000000..fcd1daca2 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/dac_caps.h @@ -0,0 +1,22 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_RTC_DAC_CAPS_H_ +#define _SOC_RTC_DAC_CAPS_H_ + +#define SOC_DAC_PERIPH_NUM 2 + +#define SOC_DAC_RESOLUTION 8 // DAC resolution ratio 8 bit + +#endif \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/dac_channel.h b/components/soc/soc/esp32s3/include/soc/dac_channel.h new file mode 100644 index 000000000..a7bc04401 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/dac_channel.h @@ -0,0 +1,24 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#ifndef _SOC_DAC_CHANNEL_H +#define _SOC_DAC_CHANNEL_H + +#define DAC_GPIO17_CHANNEL DAC_CHANNEL_1 +#define DAC_CHANNEL_1_GPIO_NUM 17 + +#define DAC_GPIO18_CHANNEL DAC_CHANNEL_2 +#define DAC_CHANNEL_2_GPIO_NUM 18 + +#endif diff --git a/components/soc/soc/esp32s3/include/soc/dma_reg.h b/components/soc/soc/esp32s3/include/soc/dma_reg.h new file mode 100644 index 000000000..ddfc26e8c --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/dma_reg.h @@ -0,0 +1,5168 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define DMA_CONF0_CH0_REG (DR_REG_DMA_BASE + 0x000) +/* DMA_MEM_TRANS_EN_CH0 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH0 (BIT(10)) +#define DMA_MEM_TRANS_EN_CH0_M (BIT(10)) +#define DMA_MEM_TRANS_EN_CH0_V 0x1 +#define DMA_MEM_TRANS_EN_CH0_S 10 +/* DMA_IN_DATA_BURST_EN_CH0 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 0 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH0 (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH0_M (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH0_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH0_S 9 +/* DMA_OUT_DATA_BURST_EN_CH0 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH0 (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH0_M (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH0_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH0_S 8 +/* DMA_INDSCR_BURST_EN_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 0 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH0 (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH0_M (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH0_V 0x1 +#define DMA_INDSCR_BURST_EN_CH0_S 7 +/* DMA_OUTDSCR_BURST_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 0 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH0 (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH0_M (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH0_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH0_S 6 +/* DMA_OUT_EOF_MODE_CH0 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH0 (BIT(5)) +#define DMA_OUT_EOF_MODE_CH0_M (BIT(5)) +#define DMA_OUT_EOF_MODE_CH0_V 0x1 +#define DMA_OUT_EOF_MODE_CH0_S 5 +/* DMA_OUT_AUTO_WRBACK_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH0 (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH0_M (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH0_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH0_S 4 +/* DMA_OUT_LOOP_TEST_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH0 (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH0_M (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH0_V 0x1 +#define DMA_OUT_LOOP_TEST_CH0_S 3 +/* DMA_IN_LOOP_TEST_CH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH0 (BIT(2)) +#define DMA_IN_LOOP_TEST_CH0_M (BIT(2)) +#define DMA_IN_LOOP_TEST_CH0_V 0x1 +#define DMA_IN_LOOP_TEST_CH0_S 2 +/* DMA_OUT_RST_CH0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH0 (BIT(1)) +#define DMA_OUT_RST_CH0_M (BIT(1)) +#define DMA_OUT_RST_CH0_V 0x1 +#define DMA_OUT_RST_CH0_S 1 +/* DMA_IN_RST_CH0 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH0 (BIT(0)) +#define DMA_IN_RST_CH0_M (BIT(0)) +#define DMA_IN_RST_CH0_V 0x1 +#define DMA_IN_RST_CH0_S 0 + +#define DMA_CONF0_CH1_REG (DR_REG_DMA_BASE + 0x004) +/* DMA_MEM_TRANS_EN_CH1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH1 (BIT(10)) +#define DMA_MEM_TRANS_EN_CH1_M (BIT(10)) +#define DMA_MEM_TRANS_EN_CH1_V 0x1 +#define DMA_MEM_TRANS_EN_CH1_S 10 +/* DMA_IN_DATA_BURST_EN_CH1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 1 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH1 (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH1_M (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH1_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH1_S 9 +/* DMA_OUT_DATA_BURST_EN_CH1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 1 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH1 (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH1_M (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH1_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH1_S 8 +/* DMA_INDSCR_BURST_EN_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 1 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH1 (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH1_M (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH1_V 0x1 +#define DMA_INDSCR_BURST_EN_CH1_S 7 +/* DMA_OUTDSCR_BURST_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 1 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH1 (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH1_M (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH1_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH1_S 6 +/* DMA_OUT_EOF_MODE_CH1 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH1 (BIT(5)) +#define DMA_OUT_EOF_MODE_CH1_M (BIT(5)) +#define DMA_OUT_EOF_MODE_CH1_V 0x1 +#define DMA_OUT_EOF_MODE_CH1_S 5 +/* DMA_OUT_AUTO_WRBACK_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH1 (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH1_M (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH1_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH1_S 4 +/* DMA_OUT_LOOP_TEST_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH1 (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH1_M (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH1_V 0x1 +#define DMA_OUT_LOOP_TEST_CH1_S 3 +/* DMA_IN_LOOP_TEST_CH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH1 (BIT(2)) +#define DMA_IN_LOOP_TEST_CH1_M (BIT(2)) +#define DMA_IN_LOOP_TEST_CH1_V 0x1 +#define DMA_IN_LOOP_TEST_CH1_S 2 +/* DMA_OUT_RST_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH1 (BIT(1)) +#define DMA_OUT_RST_CH1_M (BIT(1)) +#define DMA_OUT_RST_CH1_V 0x1 +#define DMA_OUT_RST_CH1_S 1 +/* DMA_IN_RST_CH1 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH1 (BIT(0)) +#define DMA_IN_RST_CH1_M (BIT(0)) +#define DMA_IN_RST_CH1_V 0x1 +#define DMA_IN_RST_CH1_S 0 + +#define DMA_CONF0_CH2_REG (DR_REG_DMA_BASE + 0x008) +/* DMA_MEM_TRANS_EN_CH2 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH2 (BIT(10)) +#define DMA_MEM_TRANS_EN_CH2_M (BIT(10)) +#define DMA_MEM_TRANS_EN_CH2_V 0x1 +#define DMA_MEM_TRANS_EN_CH2_S 10 +/* DMA_IN_DATA_BURST_EN_CH2 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 2 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH2 (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH2_M (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH2_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH2_S 9 +/* DMA_OUT_DATA_BURST_EN_CH2 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 2 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH2 (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH2_M (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH2_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH2_S 8 +/* DMA_INDSCR_BURST_EN_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 2 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH2 (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH2_M (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH2_V 0x1 +#define DMA_INDSCR_BURST_EN_CH2_S 7 +/* DMA_OUTDSCR_BURST_EN_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 2 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH2 (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH2_M (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH2_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH2_S 6 +/* DMA_OUT_EOF_MODE_CH2 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH2 (BIT(5)) +#define DMA_OUT_EOF_MODE_CH2_M (BIT(5)) +#define DMA_OUT_EOF_MODE_CH2_V 0x1 +#define DMA_OUT_EOF_MODE_CH2_S 5 +/* DMA_OUT_AUTO_WRBACK_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH2 (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH2_M (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH2_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH2_S 4 +/* DMA_OUT_LOOP_TEST_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH2 (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH2_M (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH2_V 0x1 +#define DMA_OUT_LOOP_TEST_CH2_S 3 +/* DMA_IN_LOOP_TEST_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH2 (BIT(2)) +#define DMA_IN_LOOP_TEST_CH2_M (BIT(2)) +#define DMA_IN_LOOP_TEST_CH2_V 0x1 +#define DMA_IN_LOOP_TEST_CH2_S 2 +/* DMA_OUT_RST_CH2 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH2 (BIT(1)) +#define DMA_OUT_RST_CH2_M (BIT(1)) +#define DMA_OUT_RST_CH2_V 0x1 +#define DMA_OUT_RST_CH2_S 1 +/* DMA_IN_RST_CH2 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH2 (BIT(0)) +#define DMA_IN_RST_CH2_M (BIT(0)) +#define DMA_IN_RST_CH2_V 0x1 +#define DMA_IN_RST_CH2_S 0 + +#define DMA_CONF0_CH3_REG (DR_REG_DMA_BASE + 0x00C) +/* DMA_MEM_TRANS_EN_CH3 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH3 (BIT(10)) +#define DMA_MEM_TRANS_EN_CH3_M (BIT(10)) +#define DMA_MEM_TRANS_EN_CH3_V 0x1 +#define DMA_MEM_TRANS_EN_CH3_S 10 +/* DMA_IN_DATA_BURST_EN_CH3 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 3 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH3 (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH3_M (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH3_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH3_S 9 +/* DMA_OUT_DATA_BURST_EN_CH3 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 3 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH3 (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH3_M (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH3_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH3_S 8 +/* DMA_INDSCR_BURST_EN_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 3 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH3 (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH3_M (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH3_V 0x1 +#define DMA_INDSCR_BURST_EN_CH3_S 7 +/* DMA_OUTDSCR_BURST_EN_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 3 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH3 (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH3_M (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH3_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH3_S 6 +/* DMA_OUT_EOF_MODE_CH3 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 3 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH3 (BIT(5)) +#define DMA_OUT_EOF_MODE_CH3_M (BIT(5)) +#define DMA_OUT_EOF_MODE_CH3_V 0x1 +#define DMA_OUT_EOF_MODE_CH3_S 5 +/* DMA_OUT_AUTO_WRBACK_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH3 (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH3_M (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH3_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH3_S 4 +/* DMA_OUT_LOOP_TEST_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH3 (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH3_M (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH3_V 0x1 +#define DMA_OUT_LOOP_TEST_CH3_S 3 +/* DMA_IN_LOOP_TEST_CH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH3 (BIT(2)) +#define DMA_IN_LOOP_TEST_CH3_M (BIT(2)) +#define DMA_IN_LOOP_TEST_CH3_V 0x1 +#define DMA_IN_LOOP_TEST_CH3_S 2 +/* DMA_OUT_RST_CH3 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 3 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH3 (BIT(1)) +#define DMA_OUT_RST_CH3_M (BIT(1)) +#define DMA_OUT_RST_CH3_V 0x1 +#define DMA_OUT_RST_CH3_S 1 +/* DMA_IN_RST_CH3 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 3 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH3 (BIT(0)) +#define DMA_IN_RST_CH3_M (BIT(0)) +#define DMA_IN_RST_CH3_V 0x1 +#define DMA_IN_RST_CH3_S 0 + +#define DMA_CONF0_CH4_REG (DR_REG_DMA_BASE + 0x010) +/* DMA_MEM_TRANS_EN_CH4 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit 1 to enable automatic transmitting data from memory + to memory via DMA.*/ +#define DMA_MEM_TRANS_EN_CH4 (BIT(10)) +#define DMA_MEM_TRANS_EN_CH4_M (BIT(10)) +#define DMA_MEM_TRANS_EN_CH4_V 0x1 +#define DMA_MEM_TRANS_EN_CH4_S 10 +/* DMA_IN_DATA_BURST_EN_CH4 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 4 receiving data when accessing internal SRAM.*/ +#define DMA_IN_DATA_BURST_EN_CH4 (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH4_M (BIT(9)) +#define DMA_IN_DATA_BURST_EN_CH4_V 0x1 +#define DMA_IN_DATA_BURST_EN_CH4_S 9 +/* DMA_OUT_DATA_BURST_EN_CH4 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 4 transmitting data when accessing internal SRAM.*/ +#define DMA_OUT_DATA_BURST_EN_CH4 (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH4_M (BIT(8)) +#define DMA_OUT_DATA_BURST_EN_CH4_V 0x1 +#define DMA_OUT_DATA_BURST_EN_CH4_S 8 +/* DMA_INDSCR_BURST_EN_CH4 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Rx channel + 4 reading link descriptor when accessing internal SRAM.*/ +#define DMA_INDSCR_BURST_EN_CH4 (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH4_M (BIT(7)) +#define DMA_INDSCR_BURST_EN_CH4_V 0x1 +#define DMA_INDSCR_BURST_EN_CH4_S 7 +/* DMA_OUTDSCR_BURST_EN_CH4 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to 1 to enable INCR burst transfer for Tx channel + 4 reading link descriptor when accessing internal SRAM.*/ +#define DMA_OUTDSCR_BURST_EN_CH4 (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH4_M (BIT(6)) +#define DMA_OUTDSCR_BURST_EN_CH4_V 0x1 +#define DMA_OUTDSCR_BURST_EN_CH4_S 6 +/* DMA_OUT_EOF_MODE_CH4 : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: EOF flag generation mode when transmitting data. 1: EOF flag + for Tx channel 4 is generated when data need to transmit has been popped from FIFO in DMA*/ +#define DMA_OUT_EOF_MODE_CH4 (BIT(5)) +#define DMA_OUT_EOF_MODE_CH4_M (BIT(5)) +#define DMA_OUT_EOF_MODE_CH4_V 0x1 +#define DMA_OUT_EOF_MODE_CH4_S 5 +/* DMA_OUT_AUTO_WRBACK_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to enable automatic outlink-writeback when all the + data in tx buffer has been transmitted.*/ +#define DMA_OUT_AUTO_WRBACK_CH4 (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH4_M (BIT(4)) +#define DMA_OUT_AUTO_WRBACK_CH4_V 0x1 +#define DMA_OUT_AUTO_WRBACK_CH4_S 4 +/* DMA_OUT_LOOP_TEST_CH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_LOOP_TEST_CH4 (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH4_M (BIT(3)) +#define DMA_OUT_LOOP_TEST_CH4_V 0x1 +#define DMA_OUT_LOOP_TEST_CH4_S 3 +/* DMA_IN_LOOP_TEST_CH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_LOOP_TEST_CH4 (BIT(2)) +#define DMA_IN_LOOP_TEST_CH4_M (BIT(2)) +#define DMA_IN_LOOP_TEST_CH4_V 0x1 +#define DMA_IN_LOOP_TEST_CH4_S 2 +/* DMA_OUT_RST_CH4 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: This bit is used to reset DMA channel 4 Tx FSM and Tx FIFO pointer.*/ +#define DMA_OUT_RST_CH4 (BIT(1)) +#define DMA_OUT_RST_CH4_M (BIT(1)) +#define DMA_OUT_RST_CH4_V 0x1 +#define DMA_OUT_RST_CH4_S 1 +/* DMA_IN_RST_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: This bit is used to reset DMA channel 4 Rx FSM and Rx FIFO pointer.*/ +#define DMA_IN_RST_CH4 (BIT(0)) +#define DMA_IN_RST_CH4_M (BIT(0)) +#define DMA_IN_RST_CH4_V 0x1 +#define DMA_IN_RST_CH4_S 0 + +#define DMA_CONF1_CH0_REG (DR_REG_DMA_BASE + 0x014) +/* DMA_OUT_EXT_MEM_BK_SIZE_CH0 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 0 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_OUT_EXT_MEM_BK_SIZE_CH0 0x00000003 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH0_M ((DMA_OUT_EXT_MEM_BK_SIZE_CH0_V) << (DMA_OUT_EXT_MEM_BK_SIZE_CH0_S)) +#define DMA_OUT_EXT_MEM_BK_SIZE_CH0_V 0x3 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH0_S 15 +/* DMA_IN_EXT_MEM_BK_SIZE_CH0 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 0 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_IN_EXT_MEM_BK_SIZE_CH0 0x00000003 +#define DMA_IN_EXT_MEM_BK_SIZE_CH0_M ((DMA_IN_EXT_MEM_BK_SIZE_CH0_V) << (DMA_IN_EXT_MEM_BK_SIZE_CH0_S)) +#define DMA_IN_EXT_MEM_BK_SIZE_CH0_V 0x3 +#define DMA_IN_EXT_MEM_BK_SIZE_CH0_S 13 +/* DMA_CHECK_OWNER_CH0 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_CHECK_OWNER_CH0 (BIT(12)) +#define DMA_CHECK_OWNER_CH0_M (BIT(12)) +#define DMA_CHECK_OWNER_CH0_V 0x1 +#define DMA_CHECK_OWNER_CH0_S 12 +/* DMA_INFIFO_FULL_THRS_CH0 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt + when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ +#define DMA_INFIFO_FULL_THRS_CH0 0x00000FFF +#define DMA_INFIFO_FULL_THRS_CH0_M ((DMA_INFIFO_FULL_THRS_CH0_V) << (DMA_INFIFO_FULL_THRS_CH0_S)) +#define DMA_INFIFO_FULL_THRS_CH0_V 0xFFF +#define DMA_INFIFO_FULL_THRS_CH0_S 0 + +#define DMA_CONF1_CH1_REG (DR_REG_DMA_BASE + 0x018) +/* DMA_OUT_EXT_MEM_BK_SIZE_CH1 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 1 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_OUT_EXT_MEM_BK_SIZE_CH1 0x00000003 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH1_M ((DMA_OUT_EXT_MEM_BK_SIZE_CH1_V) << (DMA_OUT_EXT_MEM_BK_SIZE_CH1_S)) +#define DMA_OUT_EXT_MEM_BK_SIZE_CH1_V 0x3 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH1_S 15 +/* DMA_IN_EXT_MEM_BK_SIZE_CH1 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 1 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_IN_EXT_MEM_BK_SIZE_CH1 0x00000003 +#define DMA_IN_EXT_MEM_BK_SIZE_CH1_M ((DMA_IN_EXT_MEM_BK_SIZE_CH1_V) << (DMA_IN_EXT_MEM_BK_SIZE_CH1_S)) +#define DMA_IN_EXT_MEM_BK_SIZE_CH1_V 0x3 +#define DMA_IN_EXT_MEM_BK_SIZE_CH1_S 13 +/* DMA_CHECK_OWNER_CH1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_CHECK_OWNER_CH1 (BIT(12)) +#define DMA_CHECK_OWNER_CH1_M (BIT(12)) +#define DMA_CHECK_OWNER_CH1_V 0x1 +#define DMA_CHECK_OWNER_CH1_S 12 +/* DMA_INFIFO_FULL_THRS_CH1 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt + when Rx channel 1 received byte number in Rx FIFO is up to the value of the register.*/ +#define DMA_INFIFO_FULL_THRS_CH1 0x00000FFF +#define DMA_INFIFO_FULL_THRS_CH1_M ((DMA_INFIFO_FULL_THRS_CH1_V) << (DMA_INFIFO_FULL_THRS_CH1_S)) +#define DMA_INFIFO_FULL_THRS_CH1_V 0xFFF +#define DMA_INFIFO_FULL_THRS_CH1_S 0 + +#define DMA_CONF1_CH2_REG (DR_REG_DMA_BASE + 0x01C) +/* DMA_OUT_EXT_MEM_BK_SIZE_CH2 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 2 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_OUT_EXT_MEM_BK_SIZE_CH2 0x00000003 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH2_M ((DMA_OUT_EXT_MEM_BK_SIZE_CH2_V) << (DMA_OUT_EXT_MEM_BK_SIZE_CH2_S)) +#define DMA_OUT_EXT_MEM_BK_SIZE_CH2_V 0x3 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH2_S 15 +/* DMA_IN_EXT_MEM_BK_SIZE_CH2 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 2 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_IN_EXT_MEM_BK_SIZE_CH2 0x00000003 +#define DMA_IN_EXT_MEM_BK_SIZE_CH2_M ((DMA_IN_EXT_MEM_BK_SIZE_CH2_V) << (DMA_IN_EXT_MEM_BK_SIZE_CH2_S)) +#define DMA_IN_EXT_MEM_BK_SIZE_CH2_V 0x3 +#define DMA_IN_EXT_MEM_BK_SIZE_CH2_S 13 +/* DMA_CHECK_OWNER_CH2 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_CHECK_OWNER_CH2 (BIT(12)) +#define DMA_CHECK_OWNER_CH2_M (BIT(12)) +#define DMA_CHECK_OWNER_CH2_V 0x1 +#define DMA_CHECK_OWNER_CH2_S 12 +/* DMA_INFIFO_FULL_THRS_CH2 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt + when Rx channel 2 received byte number in Rx FIFO is up to the value of the register.*/ +#define DMA_INFIFO_FULL_THRS_CH2 0x00000FFF +#define DMA_INFIFO_FULL_THRS_CH2_M ((DMA_INFIFO_FULL_THRS_CH2_V) << (DMA_INFIFO_FULL_THRS_CH2_S)) +#define DMA_INFIFO_FULL_THRS_CH2_V 0xFFF +#define DMA_INFIFO_FULL_THRS_CH2_S 0 + +#define DMA_CONF1_CH3_REG (DR_REG_DMA_BASE + 0x020) +/* DMA_OUT_EXT_MEM_BK_SIZE_CH3 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 3 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_OUT_EXT_MEM_BK_SIZE_CH3 0x00000003 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH3_M ((DMA_OUT_EXT_MEM_BK_SIZE_CH3_V) << (DMA_OUT_EXT_MEM_BK_SIZE_CH3_S)) +#define DMA_OUT_EXT_MEM_BK_SIZE_CH3_V 0x3 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH3_S 15 +/* DMA_IN_EXT_MEM_BK_SIZE_CH3 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 3 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_IN_EXT_MEM_BK_SIZE_CH3 0x00000003 +#define DMA_IN_EXT_MEM_BK_SIZE_CH3_M ((DMA_IN_EXT_MEM_BK_SIZE_CH3_V) << (DMA_IN_EXT_MEM_BK_SIZE_CH3_S)) +#define DMA_IN_EXT_MEM_BK_SIZE_CH3_V 0x3 +#define DMA_IN_EXT_MEM_BK_SIZE_CH3_S 13 +/* DMA_CHECK_OWNER_CH3 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_CHECK_OWNER_CH3 (BIT(12)) +#define DMA_CHECK_OWNER_CH3_M (BIT(12)) +#define DMA_CHECK_OWNER_CH3_V 0x1 +#define DMA_CHECK_OWNER_CH3_S 12 +/* DMA_INFIFO_FULL_THRS_CH3 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt + when Rx channel 3 received byte number in Rx FIFO is up to the value of the register.*/ +#define DMA_INFIFO_FULL_THRS_CH3 0x00000FFF +#define DMA_INFIFO_FULL_THRS_CH3_M ((DMA_INFIFO_FULL_THRS_CH3_V) << (DMA_INFIFO_FULL_THRS_CH3_S)) +#define DMA_INFIFO_FULL_THRS_CH3_V 0xFFF +#define DMA_INFIFO_FULL_THRS_CH3_S 0 + +#define DMA_CONF1_CH4_REG (DR_REG_DMA_BASE + 0x024) +/* DMA_OUT_EXT_MEM_BK_SIZE_CH4 : R/W ;bitpos:[16:15] ;default: 2'b0 ; */ +/*description: Block size of Tx channel 4 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_OUT_EXT_MEM_BK_SIZE_CH4 0x00000003 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH4_M ((DMA_OUT_EXT_MEM_BK_SIZE_CH4_V) << (DMA_OUT_EXT_MEM_BK_SIZE_CH4_S)) +#define DMA_OUT_EXT_MEM_BK_SIZE_CH4_V 0x3 +#define DMA_OUT_EXT_MEM_BK_SIZE_CH4_S 15 +/* DMA_IN_EXT_MEM_BK_SIZE_CH4 : R/W ;bitpos:[14:13] ;default: 2'b0 ; */ +/*description: Block size of Rx channel 4 when DMA access external SRAM. 0: + 16 bytes 1: 32 bytes 2/3:reserved*/ +#define DMA_IN_EXT_MEM_BK_SIZE_CH4 0x00000003 +#define DMA_IN_EXT_MEM_BK_SIZE_CH4_M ((DMA_IN_EXT_MEM_BK_SIZE_CH4_V) << (DMA_IN_EXT_MEM_BK_SIZE_CH4_S)) +#define DMA_IN_EXT_MEM_BK_SIZE_CH4_V 0x3 +#define DMA_IN_EXT_MEM_BK_SIZE_CH4_S 13 +/* DMA_CHECK_OWNER_CH4 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to enable checking the owner attribute of the link descriptor.*/ +#define DMA_CHECK_OWNER_CH4 (BIT(12)) +#define DMA_CHECK_OWNER_CH4_M (BIT(12)) +#define DMA_CHECK_OWNER_CH4_V 0x1 +#define DMA_CHECK_OWNER_CH4_S 12 +/* DMA_INFIFO_FULL_THRS_CH4 : R/W ;bitpos:[11:0] ;default: 12'hc ; */ +/*description: This register is used to generate the INFIFO_FULL_WM_INT interrupt + when Rx channel 4 received byte number in Rx FIFO is up to the value of the register.*/ +#define DMA_INFIFO_FULL_THRS_CH4 0x00000FFF +#define DMA_INFIFO_FULL_THRS_CH4_M ((DMA_INFIFO_FULL_THRS_CH4_V) << (DMA_INFIFO_FULL_THRS_CH4_S)) +#define DMA_INFIFO_FULL_THRS_CH4_V 0xFFF +#define DMA_INFIFO_FULL_THRS_CH4_S 0 + +#define DMA_INT_RAW_CH0_REG (DR_REG_DMA_BASE + 0x028) +/* DMA_OUTFIFO_UDF_L3_CH0_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 0 is underflow.*/ +#define DMA_OUTFIFO_UDF_L3_CH0_INT_RAW (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_RAW_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH0_INT_RAW_S 17 +/* DMA_OUTFIFO_OVF_L3_CH0_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 0 is overflow.*/ +#define DMA_OUTFIFO_OVF_L3_CH0_INT_RAW (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_RAW_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH0_INT_RAW_S 16 +/* DMA_OUTFIFO_UDF_L1_CH0_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is underflow.*/ +#define DMA_OUTFIFO_UDF_L1_CH0_INT_RAW (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH0_INT_RAW_S 15 +/* DMA_OUTFIFO_OVF_L1_CH0_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 0 is overflow.*/ +#define DMA_OUTFIFO_OVF_L1_CH0_INT_RAW (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH0_INT_RAW_S 14 +/* DMA_INFIFO_UDF_L3_CH0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 0 is underflow.*/ +#define DMA_INFIFO_UDF_L3_CH0_INT_RAW (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_RAW_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L3_CH0_INT_RAW_S 13 +/* DMA_INFIFO_OVF_L3_CH0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 0 is overflow.*/ +#define DMA_INFIFO_OVF_L3_CH0_INT_RAW (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_RAW_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L3_CH0_INT_RAW_S 12 +/* DMA_INFIFO_UDF_L1_CH0_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is underflow.*/ +#define DMA_INFIFO_UDF_L1_CH0_INT_RAW (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_RAW_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L1_CH0_INT_RAW_S 11 +/* DMA_INFIFO_OVF_L1_CH0_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 0 is overflow.*/ +#define DMA_INFIFO_OVF_L1_CH0_INT_RAW (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L1_CH0_INT_RAW_S 10 +/* DMA_INFIFO_FULL_WM_CH0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data + byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ +#define DMA_INFIFO_FULL_WM_CH0_INT_RAW (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_RAW_V 0x1 +#define DMA_INFIFO_FULL_WM_CH0_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_RAW_S 5 +/* DMA_OUT_EOF_CH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ +#define DMA_OUT_EOF_CH0_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH0_INT_RAW_S 4 +/* DMA_OUT_DONE_CH0_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ +#define DMA_OUT_DONE_CH0_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH0_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH0_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ +#define DMA_IN_SUC_EOF_CH0_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_RAW_S 1 +/* DMA_IN_DONE_CH0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 0.*/ +#define DMA_IN_DONE_CH0_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH0_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH0_INT_RAW_S 0 + +#define DMA_INT_RAW_CH1_REG (DR_REG_DMA_BASE + 0x02C) +/* DMA_OUTFIFO_UDF_L3_CH1_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 1 is underflow.*/ +#define DMA_OUTFIFO_UDF_L3_CH1_INT_RAW (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_RAW_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH1_INT_RAW_S 17 +/* DMA_OUTFIFO_OVF_L3_CH1_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 1 is overflow.*/ +#define DMA_OUTFIFO_OVF_L3_CH1_INT_RAW (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_RAW_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH1_INT_RAW_S 16 +/* DMA_OUTFIFO_UDF_L1_CH1_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 1 is underflow.*/ +#define DMA_OUTFIFO_UDF_L1_CH1_INT_RAW (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH1_INT_RAW_S 15 +/* DMA_OUTFIFO_OVF_L1_CH1_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 1 is overflow.*/ +#define DMA_OUTFIFO_OVF_L1_CH1_INT_RAW (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH1_INT_RAW_S 14 +/* DMA_INFIFO_UDF_L3_CH1_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 1 is underflow.*/ +#define DMA_INFIFO_UDF_L3_CH1_INT_RAW (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_RAW_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L3_CH1_INT_RAW_S 13 +/* DMA_INFIFO_OVF_L3_CH1_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 1 is overflow.*/ +#define DMA_INFIFO_OVF_L3_CH1_INT_RAW (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_RAW_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L3_CH1_INT_RAW_S 12 +/* DMA_INFIFO_UDF_L1_CH1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 1 is underflow.*/ +#define DMA_INFIFO_UDF_L1_CH1_INT_RAW (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_RAW_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L1_CH1_INT_RAW_S 11 +/* DMA_INFIFO_OVF_L1_CH1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 1 is overflow.*/ +#define DMA_INFIFO_OVF_L1_CH1_INT_RAW (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L1_CH1_INT_RAW_S 10 +/* DMA_INFIFO_FULL_WM_CH1_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data + byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1.*/ +#define DMA_INFIFO_FULL_WM_CH1_INT_RAW (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_RAW_V 0x1 +#define DMA_INFIFO_FULL_WM_CH1_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 1.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 1.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 1.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_RAW_S 5 +/* DMA_OUT_EOF_CH1_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 1.*/ +#define DMA_OUT_EOF_CH1_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH1_INT_RAW_S 4 +/* DMA_OUT_DONE_CH1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.*/ +#define DMA_OUT_DONE_CH1_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH1_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH1_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.*/ +#define DMA_IN_SUC_EOF_CH1_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_RAW_S 1 +/* DMA_IN_DONE_CH1_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 1.*/ +#define DMA_IN_DONE_CH1_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH1_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH1_INT_RAW_S 0 + +#define DMA_INT_RAW_CH2_REG (DR_REG_DMA_BASE + 0x030) +/* DMA_OUTFIFO_UDF_L3_CH2_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 2 is underflow.*/ +#define DMA_OUTFIFO_UDF_L3_CH2_INT_RAW (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_RAW_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH2_INT_RAW_S 17 +/* DMA_OUTFIFO_OVF_L3_CH2_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 2 is overflow.*/ +#define DMA_OUTFIFO_OVF_L3_CH2_INT_RAW (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_RAW_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH2_INT_RAW_S 16 +/* DMA_OUTFIFO_UDF_L1_CH2_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 2 is underflow.*/ +#define DMA_OUTFIFO_UDF_L1_CH2_INT_RAW (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH2_INT_RAW_S 15 +/* DMA_OUTFIFO_OVF_L1_CH2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 2 is overflow.*/ +#define DMA_OUTFIFO_OVF_L1_CH2_INT_RAW (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH2_INT_RAW_S 14 +/* DMA_INFIFO_UDF_L3_CH2_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 2 is underflow.*/ +#define DMA_INFIFO_UDF_L3_CH2_INT_RAW (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_RAW_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L3_CH2_INT_RAW_S 13 +/* DMA_INFIFO_OVF_L3_CH2_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 2 is overflow.*/ +#define DMA_INFIFO_OVF_L3_CH2_INT_RAW (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_RAW_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L3_CH2_INT_RAW_S 12 +/* DMA_INFIFO_UDF_L1_CH2_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 2 is underflow.*/ +#define DMA_INFIFO_UDF_L1_CH2_INT_RAW (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_RAW_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L1_CH2_INT_RAW_S 11 +/* DMA_INFIFO_OVF_L1_CH2_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 2 is overflow.*/ +#define DMA_INFIFO_OVF_L1_CH2_INT_RAW (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L1_CH2_INT_RAW_S 10 +/* DMA_INFIFO_FULL_WM_CH2_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data + byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2.*/ +#define DMA_INFIFO_FULL_WM_CH2_INT_RAW (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_RAW_V 0x1 +#define DMA_INFIFO_FULL_WM_CH2_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 2.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 2.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 2.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_RAW_S 5 +/* DMA_OUT_EOF_CH2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 2.*/ +#define DMA_OUT_EOF_CH2_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH2_INT_RAW_S 4 +/* DMA_OUT_DONE_CH2_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.*/ +#define DMA_OUT_DONE_CH2_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH2_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH2_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.*/ +#define DMA_IN_SUC_EOF_CH2_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_RAW_S 1 +/* DMA_IN_DONE_CH2_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 2.*/ +#define DMA_IN_DONE_CH2_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH2_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH2_INT_RAW_S 0 + +#define DMA_INT_RAW_CH3_REG (DR_REG_DMA_BASE + 0x034) +/* DMA_OUTFIFO_UDF_L3_CH3_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 3 is underflow.*/ +#define DMA_OUTFIFO_UDF_L3_CH3_INT_RAW (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_RAW_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH3_INT_RAW_S 17 +/* DMA_OUTFIFO_OVF_L3_CH3_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 3 is overflow.*/ +#define DMA_OUTFIFO_OVF_L3_CH3_INT_RAW (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_RAW_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH3_INT_RAW_S 16 +/* DMA_OUTFIFO_UDF_L1_CH3_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 3 is underflow.*/ +#define DMA_OUTFIFO_UDF_L1_CH3_INT_RAW (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH3_INT_RAW_S 15 +/* DMA_OUTFIFO_OVF_L1_CH3_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 3 is overflow.*/ +#define DMA_OUTFIFO_OVF_L1_CH3_INT_RAW (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH3_INT_RAW_S 14 +/* DMA_INFIFO_UDF_L3_CH3_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 3 is underflow.*/ +#define DMA_INFIFO_UDF_L3_CH3_INT_RAW (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_RAW_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L3_CH3_INT_RAW_S 13 +/* DMA_INFIFO_OVF_L3_CH3_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 3 is overflow.*/ +#define DMA_INFIFO_OVF_L3_CH3_INT_RAW (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_RAW_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L3_CH3_INT_RAW_S 12 +/* DMA_INFIFO_UDF_L1_CH3_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 3 is underflow.*/ +#define DMA_INFIFO_UDF_L1_CH3_INT_RAW (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_RAW_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L1_CH3_INT_RAW_S 11 +/* DMA_INFIFO_OVF_L1_CH3_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 3 is overflow.*/ +#define DMA_INFIFO_OVF_L1_CH3_INT_RAW (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L1_CH3_INT_RAW_S 10 +/* DMA_INFIFO_FULL_WM_CH3_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data + byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3.*/ +#define DMA_INFIFO_FULL_WM_CH3_INT_RAW (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_RAW_V 0x1 +#define DMA_INFIFO_FULL_WM_CH3_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH3_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 3.*/ +#define DMA_OUT_TOTAL_EOF_CH3_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH3_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 3.*/ +#define DMA_IN_DSCR_EMPTY_CH3_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH3_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH3_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 3.*/ +#define DMA_OUT_DSCR_ERR_CH3_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH3_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH3_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 3.*/ +#define DMA_IN_DSCR_ERR_CH3_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH3_INT_RAW_S 5 +/* DMA_OUT_EOF_CH3_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 3.*/ +#define DMA_OUT_EOF_CH3_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH3_INT_RAW_S 4 +/* DMA_OUT_DONE_CH3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 3.*/ +#define DMA_OUT_DONE_CH3_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH3_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH3_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 3. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH3_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH3_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH3_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 3. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 3.*/ +#define DMA_IN_SUC_EOF_CH3_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH3_INT_RAW_S 1 +/* DMA_IN_DONE_CH3_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 3.*/ +#define DMA_IN_DONE_CH3_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH3_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH3_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH3_INT_RAW_S 0 + +#define DMA_INT_RAW_CH4_REG (DR_REG_DMA_BASE + 0x038) +/* DMA_OUTFIFO_UDF_L3_CH4_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 4 is underflow.*/ +#define DMA_OUTFIFO_UDF_L3_CH4_INT_RAW (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_RAW_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH4_INT_RAW_S 17 +/* DMA_OUTFIFO_OVF_L3_CH4_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Tx channel 4 is overflow.*/ +#define DMA_OUTFIFO_OVF_L3_CH4_INT_RAW (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_RAW_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH4_INT_RAW_S 16 +/* DMA_OUTFIFO_UDF_L1_CH4_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 4 is underflow.*/ +#define DMA_OUTFIFO_UDF_L1_CH4_INT_RAW (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH4_INT_RAW_S 15 +/* DMA_OUTFIFO_OVF_L1_CH4_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Tx channel 4 is overflow.*/ +#define DMA_OUTFIFO_OVF_L1_CH4_INT_RAW (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH4_INT_RAW_S 14 +/* DMA_INFIFO_UDF_L3_CH4_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 4 is underflow.*/ +#define DMA_INFIFO_UDF_L3_CH4_INT_RAW (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_RAW_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L3_CH4_INT_RAW_S 13 +/* DMA_INFIFO_OVF_L3_CH4_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 3 fifo + of Rx channel 4 is overflow.*/ +#define DMA_INFIFO_OVF_L3_CH4_INT_RAW (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_RAW_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L3_CH4_INT_RAW_S 12 +/* DMA_INFIFO_UDF_L1_CH4_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 4 is underflow.*/ +#define DMA_INFIFO_UDF_L1_CH4_INT_RAW (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_RAW_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_RAW_V 0x1 +#define DMA_INFIFO_UDF_L1_CH4_INT_RAW_S 11 +/* DMA_INFIFO_OVF_L1_CH4_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: This raw interrupt bit turns to high level when level 1 fifo + of Rx channel 4 is overflow.*/ +#define DMA_INFIFO_OVF_L1_CH4_INT_RAW (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_RAW_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_RAW_V 0x1 +#define DMA_INFIFO_OVF_L1_CH4_INT_RAW_S 10 +/* DMA_INFIFO_FULL_WM_CH4_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when received data + byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4.*/ +#define DMA_INFIFO_FULL_WM_CH4_INT_RAW (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_RAW_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_RAW_V 0x1 +#define DMA_INFIFO_FULL_WM_CH4_INT_RAW_S 9 +/* DMA_OUT_TOTAL_EOF_CH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data corresponding + a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 4.*/ +#define DMA_OUT_TOTAL_EOF_CH4_INT_RAW (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_RAW_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_RAW_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH4_INT_RAW_S 8 +/* DMA_IN_DSCR_EMPTY_CH4_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when Rx buffer pointed + by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 4.*/ +#define DMA_IN_DSCR_EMPTY_CH4_INT_RAW (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_RAW_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_RAW_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH4_INT_RAW_S 7 +/* DMA_OUT_DSCR_ERR_CH4_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting outlink + descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 4.*/ +#define DMA_OUT_DSCR_ERR_CH4_INT_RAW (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_RAW_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_RAW_V 0x1 +#define DMA_OUT_DSCR_ERR_CH4_INT_RAW_S 6 +/* DMA_IN_DSCR_ERR_CH4_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when detecting inlink + descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 4.*/ +#define DMA_IN_DSCR_ERR_CH4_INT_RAW (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_RAW_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_RAW_V 0x1 +#define DMA_IN_DSCR_ERR_CH4_INT_RAW_S 5 +/* DMA_OUT_EOF_CH4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been read from memory for Tx channel 4.*/ +#define DMA_OUT_EOF_CH4_INT_RAW (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_RAW_M (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_RAW_V 0x1 +#define DMA_OUT_EOF_CH4_INT_RAW_S 4 +/* DMA_OUT_DONE_CH4_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 4.*/ +#define DMA_OUT_DONE_CH4_INT_RAW (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_RAW_M (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_RAW_V 0x1 +#define DMA_OUT_DONE_CH4_INT_RAW_S 3 +/* DMA_IN_ERR_EOF_CH4_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when data error is + detected only in the case that the peripheral is UHCI0 for Rx channel 4. For other peripherals this raw interrupt is reserved.*/ +#define DMA_IN_ERR_EOF_CH4_INT_RAW (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_RAW_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_RAW_V 0x1 +#define DMA_IN_ERR_EOF_CH4_INT_RAW_S 2 +/* DMA_IN_SUC_EOF_CH4_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 4. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 4.*/ +#define DMA_IN_SUC_EOF_CH4_INT_RAW (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_RAW_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_RAW_V 0x1 +#define DMA_IN_SUC_EOF_CH4_INT_RAW_S 1 +/* DMA_IN_DONE_CH4_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt bit turns to high level when the last data + pointed by one inlink descriptor has been received for Rx channel 4.*/ +#define DMA_IN_DONE_CH4_INT_RAW (BIT(0)) +#define DMA_IN_DONE_CH4_INT_RAW_M (BIT(0)) +#define DMA_IN_DONE_CH4_INT_RAW_V 0x1 +#define DMA_IN_DONE_CH4_INT_RAW_S 0 + +#define DMA_INT_ST_CH0_REG (DR_REG_DMA_BASE + 0x040) +/* DMA_OUTFIFO_UDF_L3_CH0_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ST (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ST_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ST_S 17 +/* DMA_OUTFIFO_OVF_L3_CH0_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ST (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ST_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ST_S 16 +/* DMA_OUTFIFO_UDF_L1_CH0_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ST (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ST_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ST_S 15 +/* DMA_OUTFIFO_OVF_L1_CH0_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ST (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ST_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ST_S 14 +/* DMA_INFIFO_UDF_L3_CH0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH0_INT_ST (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_ST_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L3_CH0_INT_ST_S 13 +/* DMA_INFIFO_OVF_L3_CH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH0_INT_ST (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_ST_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L3_CH0_INT_ST_S 12 +/* DMA_INFIFO_UDF_L1_CH0_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH0_INT_ST (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_ST_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L1_CH0_INT_ST_S 11 +/* DMA_INFIFO_OVF_L1_CH0_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH0_INT_ST (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_ST_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L1_CH0_INT_ST_S 10 +/* DMA_INFIFO_FULL_WM_CH0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH0_INT_ST (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_ST_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_ST_V 0x1 +#define DMA_INFIFO_FULL_WM_CH0_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_ST_S 5 +/* DMA_OUT_EOF_CH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH0_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH0_INT_ST_S 4 +/* DMA_OUT_DONE_CH0_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH0_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH0_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH0_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH0_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_ST_S 1 +/* DMA_IN_DONE_CH0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH0_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ST_V 0x1 +#define DMA_IN_DONE_CH0_INT_ST_S 0 + +#define DMA_INT_ST_CH1_REG (DR_REG_DMA_BASE + 0x044) +/* DMA_OUTFIFO_UDF_L3_CH1_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ST (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ST_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ST_S 17 +/* DMA_OUTFIFO_OVF_L3_CH1_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ST (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ST_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ST_S 16 +/* DMA_OUTFIFO_UDF_L1_CH1_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ST (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ST_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ST_S 15 +/* DMA_OUTFIFO_OVF_L1_CH1_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ST (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ST_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ST_S 14 +/* DMA_INFIFO_UDF_L3_CH1_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH1_INT_ST (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_ST_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L3_CH1_INT_ST_S 13 +/* DMA_INFIFO_OVF_L3_CH1_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH1_INT_ST (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_ST_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L3_CH1_INT_ST_S 12 +/* DMA_INFIFO_UDF_L1_CH1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH1_INT_ST (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_ST_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L1_CH1_INT_ST_S 11 +/* DMA_INFIFO_OVF_L1_CH1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH1_INT_ST (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_ST_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L1_CH1_INT_ST_S 10 +/* DMA_INFIFO_FULL_WM_CH1_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH1_INT_ST (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_ST_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_ST_V 0x1 +#define DMA_INFIFO_FULL_WM_CH1_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_ST_S 5 +/* DMA_OUT_EOF_CH1_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH1_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH1_INT_ST_S 4 +/* DMA_OUT_DONE_CH1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH1_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH1_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH1_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH1_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_ST_S 1 +/* DMA_IN_DONE_CH1_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH1_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ST_V 0x1 +#define DMA_IN_DONE_CH1_INT_ST_S 0 + +#define DMA_INT_ST_CH2_REG (DR_REG_DMA_BASE + 0x048) +/* DMA_OUTFIFO_UDF_L3_CH2_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ST (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ST_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ST_S 17 +/* DMA_OUTFIFO_OVF_L3_CH2_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ST (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ST_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ST_S 16 +/* DMA_OUTFIFO_UDF_L1_CH2_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ST (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ST_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ST_S 15 +/* DMA_OUTFIFO_OVF_L1_CH2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ST (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ST_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ST_S 14 +/* DMA_INFIFO_UDF_L3_CH2_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH2_INT_ST (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_ST_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L3_CH2_INT_ST_S 13 +/* DMA_INFIFO_OVF_L3_CH2_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH2_INT_ST (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_ST_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L3_CH2_INT_ST_S 12 +/* DMA_INFIFO_UDF_L1_CH2_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH2_INT_ST (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_ST_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L1_CH2_INT_ST_S 11 +/* DMA_INFIFO_OVF_L1_CH2_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH2_INT_ST (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_ST_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L1_CH2_INT_ST_S 10 +/* DMA_INFIFO_FULL_WM_CH2_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH2_INT_ST (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_ST_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_ST_V 0x1 +#define DMA_INFIFO_FULL_WM_CH2_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_ST_S 5 +/* DMA_OUT_EOF_CH2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH2_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH2_INT_ST_S 4 +/* DMA_OUT_DONE_CH2_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH2_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH2_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH2_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH2_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_ST_S 1 +/* DMA_IN_DONE_CH2_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH2_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ST_V 0x1 +#define DMA_IN_DONE_CH2_INT_ST_S 0 + +#define DMA_INT_ST_CH3_REG (DR_REG_DMA_BASE + 0x04C) +/* DMA_OUTFIFO_UDF_L3_CH3_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ST (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ST_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ST_S 17 +/* DMA_OUTFIFO_OVF_L3_CH3_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ST (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ST_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ST_S 16 +/* DMA_OUTFIFO_UDF_L1_CH3_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ST (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ST_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ST_S 15 +/* DMA_OUTFIFO_OVF_L1_CH3_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ST (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ST_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ST_S 14 +/* DMA_INFIFO_UDF_L3_CH3_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH3_INT_ST (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_ST_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L3_CH3_INT_ST_S 13 +/* DMA_INFIFO_OVF_L3_CH3_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH3_INT_ST (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_ST_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L3_CH3_INT_ST_S 12 +/* DMA_INFIFO_UDF_L1_CH3_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH3_INT_ST (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_ST_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L1_CH3_INT_ST_S 11 +/* DMA_INFIFO_OVF_L1_CH3_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH3_INT_ST (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_ST_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L1_CH3_INT_ST_S 10 +/* DMA_INFIFO_FULL_WM_CH3_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH3_INT_ST (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_ST_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_ST_V 0x1 +#define DMA_INFIFO_FULL_WM_CH3_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH3_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH3_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH3_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH3_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH3_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH3_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH3_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH3_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH3_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH3_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH3_INT_ST_S 5 +/* DMA_OUT_EOF_CH3_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH3_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH3_INT_ST_S 4 +/* DMA_OUT_DONE_CH3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH3_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH3_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH3_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH3_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH3_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH3_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH3_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH3_INT_ST_S 1 +/* DMA_IN_DONE_CH3_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH3_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH3_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH3_INT_ST_V 0x1 +#define DMA_IN_DONE_CH3_INT_ST_S 0 + +#define DMA_INT_ST_CH4_REG (DR_REG_DMA_BASE + 0x050) +/* DMA_OUTFIFO_UDF_L3_CH4_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ST (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ST_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ST_S 17 +/* DMA_OUTFIFO_OVF_L3_CH4_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ST (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ST_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ST_S 16 +/* DMA_OUTFIFO_UDF_L1_CH4_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ST (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ST_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ST_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ST_S 15 +/* DMA_OUTFIFO_OVF_L1_CH4_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ST (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ST_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ST_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ST_S 14 +/* DMA_INFIFO_UDF_L3_CH4_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH4_INT_ST (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_ST_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L3_CH4_INT_ST_S 13 +/* DMA_INFIFO_OVF_L3_CH4_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH4_INT_ST (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_ST_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L3_CH4_INT_ST_S 12 +/* DMA_INFIFO_UDF_L1_CH4_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH4_INT_ST (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_ST_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_ST_V 0x1 +#define DMA_INFIFO_UDF_L1_CH4_INT_ST_S 11 +/* DMA_INFIFO_OVF_L1_CH4_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH4_INT_ST (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_ST_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_ST_V 0x1 +#define DMA_INFIFO_OVF_L1_CH4_INT_ST_S 10 +/* DMA_INFIFO_FULL_WM_CH4_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH4_INT_ST (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_ST_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_ST_V 0x1 +#define DMA_INFIFO_FULL_WM_CH4_INT_ST_S 9 +/* DMA_OUT_TOTAL_EOF_CH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH4_INT_ST (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_ST_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_ST_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH4_INT_ST_S 8 +/* DMA_IN_DSCR_EMPTY_CH4_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH4_INT_ST (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_ST_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_ST_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH4_INT_ST_S 7 +/* DMA_OUT_DSCR_ERR_CH4_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH4_INT_ST (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_ST_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_ST_V 0x1 +#define DMA_OUT_DSCR_ERR_CH4_INT_ST_S 6 +/* DMA_IN_DSCR_ERR_CH4_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH4_INT_ST (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_ST_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_ST_V 0x1 +#define DMA_IN_DSCR_ERR_CH4_INT_ST_S 5 +/* DMA_OUT_EOF_CH4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH4_INT_ST (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_ST_M (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_ST_V 0x1 +#define DMA_OUT_EOF_CH4_INT_ST_S 4 +/* DMA_OUT_DONE_CH4_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH4_INT_ST (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_ST_M (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_ST_V 0x1 +#define DMA_OUT_DONE_CH4_INT_ST_S 3 +/* DMA_IN_ERR_EOF_CH4_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH4_INT_ST (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_ST_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_ST_V 0x1 +#define DMA_IN_ERR_EOF_CH4_INT_ST_S 2 +/* DMA_IN_SUC_EOF_CH4_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH4_INT_ST (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_ST_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_ST_V 0x1 +#define DMA_IN_SUC_EOF_CH4_INT_ST_S 1 +/* DMA_IN_DONE_CH4_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH4_INT_ST (BIT(0)) +#define DMA_IN_DONE_CH4_INT_ST_M (BIT(0)) +#define DMA_IN_DONE_CH4_INT_ST_V 0x1 +#define DMA_IN_DONE_CH4_INT_ST_S 0 + +#define DMA_INT_ENA_CH0_REG (DR_REG_DMA_BASE + 0x054) +/* DMA_OUTFIFO_UDF_L3_CH0_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ENA (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ENA_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH0_INT_ENA_S 17 +/* DMA_OUTFIFO_OVF_L3_CH0_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ENA (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ENA_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH0_INT_ENA_S 16 +/* DMA_OUTFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ENA (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH0_INT_ENA_S 15 +/* DMA_OUTFIFO_OVF_L1_CH0_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ENA (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH0_INT_ENA_S 14 +/* DMA_INFIFO_UDF_L3_CH0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH0_INT_ENA (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_ENA_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L3_CH0_INT_ENA_S 13 +/* DMA_INFIFO_OVF_L3_CH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH0_INT_ENA (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_ENA_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L3_CH0_INT_ENA_S 12 +/* DMA_INFIFO_UDF_L1_CH0_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH0_INT_ENA (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_ENA_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L1_CH0_INT_ENA_S 11 +/* DMA_INFIFO_OVF_L1_CH0_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH0_INT_ENA (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L1_CH0_INT_ENA_S 10 +/* DMA_INFIFO_FULL_WM_CH0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH0_INT_ENA (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_ENA_V 0x1 +#define DMA_INFIFO_FULL_WM_CH0_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_ENA_S 5 +/* DMA_OUT_EOF_CH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH0_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH0_INT_ENA_S 4 +/* DMA_OUT_DONE_CH0_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH0_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH0_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH0_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH0_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_ENA_S 1 +/* DMA_IN_DONE_CH0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH0_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH0_INT_ENA_S 0 + +#define DMA_INT_ENA_CH1_REG (DR_REG_DMA_BASE + 0x058) +/* DMA_OUTFIFO_UDF_L3_CH1_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ENA (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ENA_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH1_INT_ENA_S 17 +/* DMA_OUTFIFO_OVF_L3_CH1_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ENA (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ENA_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH1_INT_ENA_S 16 +/* DMA_OUTFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ENA (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH1_INT_ENA_S 15 +/* DMA_OUTFIFO_OVF_L1_CH1_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ENA (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH1_INT_ENA_S 14 +/* DMA_INFIFO_UDF_L3_CH1_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH1_INT_ENA (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_ENA_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L3_CH1_INT_ENA_S 13 +/* DMA_INFIFO_OVF_L3_CH1_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH1_INT_ENA (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_ENA_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L3_CH1_INT_ENA_S 12 +/* DMA_INFIFO_UDF_L1_CH1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH1_INT_ENA (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_ENA_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L1_CH1_INT_ENA_S 11 +/* DMA_INFIFO_OVF_L1_CH1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH1_INT_ENA (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L1_CH1_INT_ENA_S 10 +/* DMA_INFIFO_FULL_WM_CH1_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH1_INT_ENA (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_ENA_V 0x1 +#define DMA_INFIFO_FULL_WM_CH1_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_ENA_S 5 +/* DMA_OUT_EOF_CH1_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH1_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH1_INT_ENA_S 4 +/* DMA_OUT_DONE_CH1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH1_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH1_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH1_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH1_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_ENA_S 1 +/* DMA_IN_DONE_CH1_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH1_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH1_INT_ENA_S 0 + +#define DMA_INT_ENA_CH2_REG (DR_REG_DMA_BASE + 0x05C) +/* DMA_OUTFIFO_UDF_L3_CH2_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ENA (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ENA_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH2_INT_ENA_S 17 +/* DMA_OUTFIFO_OVF_L3_CH2_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ENA (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ENA_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH2_INT_ENA_S 16 +/* DMA_OUTFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ENA (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH2_INT_ENA_S 15 +/* DMA_OUTFIFO_OVF_L1_CH2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ENA (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH2_INT_ENA_S 14 +/* DMA_INFIFO_UDF_L3_CH2_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH2_INT_ENA (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_ENA_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L3_CH2_INT_ENA_S 13 +/* DMA_INFIFO_OVF_L3_CH2_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH2_INT_ENA (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_ENA_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L3_CH2_INT_ENA_S 12 +/* DMA_INFIFO_UDF_L1_CH2_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH2_INT_ENA (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_ENA_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L1_CH2_INT_ENA_S 11 +/* DMA_INFIFO_OVF_L1_CH2_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH2_INT_ENA (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L1_CH2_INT_ENA_S 10 +/* DMA_INFIFO_FULL_WM_CH2_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH2_INT_ENA (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_ENA_V 0x1 +#define DMA_INFIFO_FULL_WM_CH2_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_ENA_S 5 +/* DMA_OUT_EOF_CH2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH2_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH2_INT_ENA_S 4 +/* DMA_OUT_DONE_CH2_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH2_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH2_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH2_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH2_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_ENA_S 1 +/* DMA_IN_DONE_CH2_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH2_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH2_INT_ENA_S 0 + +#define DMA_INT_ENA_CH3_REG (DR_REG_DMA_BASE + 0x060) +/* DMA_OUTFIFO_UDF_L3_CH3_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ENA (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ENA_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH3_INT_ENA_S 17 +/* DMA_OUTFIFO_OVF_L3_CH3_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ENA (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ENA_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH3_INT_ENA_S 16 +/* DMA_OUTFIFO_UDF_L1_CH3_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ENA (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH3_INT_ENA_S 15 +/* DMA_OUTFIFO_OVF_L1_CH3_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ENA (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH3_INT_ENA_S 14 +/* DMA_INFIFO_UDF_L3_CH3_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH3_INT_ENA (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_ENA_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L3_CH3_INT_ENA_S 13 +/* DMA_INFIFO_OVF_L3_CH3_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH3_INT_ENA (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_ENA_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L3_CH3_INT_ENA_S 12 +/* DMA_INFIFO_UDF_L1_CH3_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH3_INT_ENA (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_ENA_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L1_CH3_INT_ENA_S 11 +/* DMA_INFIFO_OVF_L1_CH3_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH3_INT_ENA (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L1_CH3_INT_ENA_S 10 +/* DMA_INFIFO_FULL_WM_CH3_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH3_INT_ENA (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_ENA_V 0x1 +#define DMA_INFIFO_FULL_WM_CH3_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH3_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH3_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH3_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH3_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH3_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH3_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH3_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH3_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH3_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH3_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH3_INT_ENA_S 5 +/* DMA_OUT_EOF_CH3_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH3_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH3_INT_ENA_S 4 +/* DMA_OUT_DONE_CH3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH3_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH3_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH3_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH3_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH3_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH3_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH3_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH3_INT_ENA_S 1 +/* DMA_IN_DONE_CH3_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH3_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH3_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH3_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH3_INT_ENA_S 0 + +#define DMA_INT_ENA_CH4_REG (DR_REG_DMA_BASE + 0x064) +/* DMA_OUTFIFO_UDF_L3_CH4_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ENA (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ENA_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH4_INT_ENA_S 17 +/* DMA_OUTFIFO_OVF_L3_CH4_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ENA (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ENA_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH4_INT_ENA_S 16 +/* DMA_OUTFIFO_UDF_L1_CH4_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ENA (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH4_INT_ENA_S 15 +/* DMA_OUTFIFO_OVF_L1_CH4_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ENA (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH4_INT_ENA_S 14 +/* DMA_INFIFO_UDF_L3_CH4_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH4_INT_ENA (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_ENA_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L3_CH4_INT_ENA_S 13 +/* DMA_INFIFO_OVF_L3_CH4_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH4_INT_ENA (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_ENA_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L3_CH4_INT_ENA_S 12 +/* DMA_INFIFO_UDF_L1_CH4_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH4_INT_ENA (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_ENA_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_ENA_V 0x1 +#define DMA_INFIFO_UDF_L1_CH4_INT_ENA_S 11 +/* DMA_INFIFO_OVF_L1_CH4_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH4_INT_ENA (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_ENA_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_ENA_V 0x1 +#define DMA_INFIFO_OVF_L1_CH4_INT_ENA_S 10 +/* DMA_INFIFO_FULL_WM_CH4_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH4_INT_ENA (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_ENA_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_ENA_V 0x1 +#define DMA_INFIFO_FULL_WM_CH4_INT_ENA_S 9 +/* DMA_OUT_TOTAL_EOF_CH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH4_INT_ENA (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_ENA_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_ENA_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH4_INT_ENA_S 8 +/* DMA_IN_DSCR_EMPTY_CH4_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH4_INT_ENA (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_ENA_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_ENA_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH4_INT_ENA_S 7 +/* DMA_OUT_DSCR_ERR_CH4_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH4_INT_ENA (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_ENA_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_ENA_V 0x1 +#define DMA_OUT_DSCR_ERR_CH4_INT_ENA_S 6 +/* DMA_IN_DSCR_ERR_CH4_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH4_INT_ENA (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_ENA_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_ENA_V 0x1 +#define DMA_IN_DSCR_ERR_CH4_INT_ENA_S 5 +/* DMA_OUT_EOF_CH4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH4_INT_ENA (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_ENA_M (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_ENA_V 0x1 +#define DMA_OUT_EOF_CH4_INT_ENA_S 4 +/* DMA_OUT_DONE_CH4_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH4_INT_ENA (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_ENA_M (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_ENA_V 0x1 +#define DMA_OUT_DONE_CH4_INT_ENA_S 3 +/* DMA_IN_ERR_EOF_CH4_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH4_INT_ENA (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_ENA_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_ENA_V 0x1 +#define DMA_IN_ERR_EOF_CH4_INT_ENA_S 2 +/* DMA_IN_SUC_EOF_CH4_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH4_INT_ENA (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_ENA_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_ENA_V 0x1 +#define DMA_IN_SUC_EOF_CH4_INT_ENA_S 1 +/* DMA_IN_DONE_CH4_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH4_INT_ENA (BIT(0)) +#define DMA_IN_DONE_CH4_INT_ENA_M (BIT(0)) +#define DMA_IN_DONE_CH4_INT_ENA_V 0x1 +#define DMA_IN_DONE_CH4_INT_ENA_S 0 + +#define DMA_INT_CLR_CH0_REG (DR_REG_DMA_BASE + 0x068) +/* DMA_OUTFIFO_UDF_L3_CH0_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH0_INT_CLR (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_CLR_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH0_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH0_INT_CLR_S 17 +/* DMA_OUTFIFO_OVF_L3_CH0_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH0_INT_CLR (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_CLR_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH0_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH0_INT_CLR_S 16 +/* DMA_OUTFIFO_UDF_L1_CH0_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH0_INT_CLR (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH0_INT_CLR_S 15 +/* DMA_OUTFIFO_OVF_L1_CH0_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH0_INT_CLR (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH0_INT_CLR_S 14 +/* DMA_INFIFO_UDF_L3_CH0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH0_INT_CLR (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_CLR_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH0_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L3_CH0_INT_CLR_S 13 +/* DMA_INFIFO_OVF_L3_CH0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH0_INT_CLR (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_CLR_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH0_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L3_CH0_INT_CLR_S 12 +/* DMA_INFIFO_UDF_L1_CH0_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH0_INT_CLR (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_CLR_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH0_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L1_CH0_INT_CLR_S 11 +/* DMA_INFIFO_OVF_L1_CH0_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH0_INT_CLR (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH0_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L1_CH0_INT_CLR_S 10 +/* DMA_INFIFO_FULL_WM_CH0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH0_INT_CLR (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH0_INT_CLR_V 0x1 +#define DMA_INFIFO_FULL_WM_CH0_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH0_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH0_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH0_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH0_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH0_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH0_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH0_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH0_INT_CLR_S 5 +/* DMA_OUT_EOF_CH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH0_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH0_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH0_INT_CLR_S 4 +/* DMA_OUT_DONE_CH0_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH0_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH0_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH0_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH0_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH0_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH0_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH0_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH0_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH0_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH0_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH0_INT_CLR_S 1 +/* DMA_IN_DONE_CH0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH0_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH0_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH0_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH0_INT_CLR_S 0 + +#define DMA_INT_CLR_CH1_REG (DR_REG_DMA_BASE + 0x06C) +/* DMA_OUTFIFO_UDF_L3_CH1_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH1_INT_CLR (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_CLR_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH1_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH1_INT_CLR_S 17 +/* DMA_OUTFIFO_OVF_L3_CH1_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH1_INT_CLR (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_CLR_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH1_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH1_INT_CLR_S 16 +/* DMA_OUTFIFO_UDF_L1_CH1_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH1_INT_CLR (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH1_INT_CLR_S 15 +/* DMA_OUTFIFO_OVF_L1_CH1_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH1_INT_CLR (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH1_INT_CLR_S 14 +/* DMA_INFIFO_UDF_L3_CH1_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH1_INT_CLR (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_CLR_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH1_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L3_CH1_INT_CLR_S 13 +/* DMA_INFIFO_OVF_L3_CH1_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH1_INT_CLR (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_CLR_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH1_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L3_CH1_INT_CLR_S 12 +/* DMA_INFIFO_UDF_L1_CH1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH1_INT_CLR (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_CLR_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH1_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L1_CH1_INT_CLR_S 11 +/* DMA_INFIFO_OVF_L1_CH1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH1_INT_CLR (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH1_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L1_CH1_INT_CLR_S 10 +/* DMA_INFIFO_FULL_WM_CH1_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH1_INT_CLR (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH1_INT_CLR_V 0x1 +#define DMA_INFIFO_FULL_WM_CH1_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH1_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH1_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH1_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH1_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH1_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH1_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH1_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH1_INT_CLR_S 5 +/* DMA_OUT_EOF_CH1_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH1_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH1_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH1_INT_CLR_S 4 +/* DMA_OUT_DONE_CH1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH1_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH1_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH1_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH1_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH1_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH1_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH1_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH1_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH1_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH1_INT_CLR_S 1 +/* DMA_IN_DONE_CH1_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH1_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH1_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH1_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH1_INT_CLR_S 0 + +#define DMA_INT_CLR_CH2_REG (DR_REG_DMA_BASE + 0x070) +/* DMA_OUTFIFO_UDF_L3_CH2_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH2_INT_CLR (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_CLR_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH2_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH2_INT_CLR_S 17 +/* DMA_OUTFIFO_OVF_L3_CH2_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH2_INT_CLR (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_CLR_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH2_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH2_INT_CLR_S 16 +/* DMA_OUTFIFO_UDF_L1_CH2_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH2_INT_CLR (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH2_INT_CLR_S 15 +/* DMA_OUTFIFO_OVF_L1_CH2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH2_INT_CLR (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH2_INT_CLR_S 14 +/* DMA_INFIFO_UDF_L3_CH2_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH2_INT_CLR (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_CLR_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH2_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L3_CH2_INT_CLR_S 13 +/* DMA_INFIFO_OVF_L3_CH2_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH2_INT_CLR (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_CLR_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH2_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L3_CH2_INT_CLR_S 12 +/* DMA_INFIFO_UDF_L1_CH2_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH2_INT_CLR (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_CLR_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH2_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L1_CH2_INT_CLR_S 11 +/* DMA_INFIFO_OVF_L1_CH2_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH2_INT_CLR (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH2_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L1_CH2_INT_CLR_S 10 +/* DMA_INFIFO_FULL_WM_CH2_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH2_INT_CLR (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH2_INT_CLR_V 0x1 +#define DMA_INFIFO_FULL_WM_CH2_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH2_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH2_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH2_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH2_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH2_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH2_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH2_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH2_INT_CLR_S 5 +/* DMA_OUT_EOF_CH2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH2_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH2_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH2_INT_CLR_S 4 +/* DMA_OUT_DONE_CH2_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH2_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH2_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH2_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH2_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH2_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH2_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH2_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH2_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH2_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH2_INT_CLR_S 1 +/* DMA_IN_DONE_CH2_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH2_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH2_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH2_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH2_INT_CLR_S 0 + +#define DMA_INT_CLR_CH3_REG (DR_REG_DMA_BASE + 0x074) +/* DMA_OUTFIFO_UDF_L3_CH3_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH3_INT_CLR (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_CLR_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH3_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH3_INT_CLR_S 17 +/* DMA_OUTFIFO_OVF_L3_CH3_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH3_INT_CLR (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_CLR_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH3_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH3_INT_CLR_S 16 +/* DMA_OUTFIFO_UDF_L1_CH3_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH3_INT_CLR (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH3_INT_CLR_S 15 +/* DMA_OUTFIFO_OVF_L1_CH3_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH3_INT_CLR (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH3_INT_CLR_S 14 +/* DMA_INFIFO_UDF_L3_CH3_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH3_INT_CLR (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_CLR_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH3_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L3_CH3_INT_CLR_S 13 +/* DMA_INFIFO_OVF_L3_CH3_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH3_INT_CLR (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_CLR_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH3_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L3_CH3_INT_CLR_S 12 +/* DMA_INFIFO_UDF_L1_CH3_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH3_INT_CLR (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_CLR_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH3_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L1_CH3_INT_CLR_S 11 +/* DMA_INFIFO_OVF_L1_CH3_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH3_INT_CLR (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH3_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L1_CH3_INT_CLR_S 10 +/* DMA_INFIFO_FULL_WM_CH3_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH3_INT_CLR (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH3_INT_CLR_V 0x1 +#define DMA_INFIFO_FULL_WM_CH3_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH3_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH3_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH3_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH3_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH3_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH3_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH3_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH3_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH3_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH3_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH3_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH3_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH3_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH3_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH3_INT_CLR_S 5 +/* DMA_OUT_EOF_CH3_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH3_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH3_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH3_INT_CLR_S 4 +/* DMA_OUT_DONE_CH3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH3_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH3_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH3_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH3_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH3_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH3_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH3_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH3_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH3_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH3_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH3_INT_CLR_S 1 +/* DMA_IN_DONE_CH3_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH3_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH3_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH3_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH3_INT_CLR_S 0 + +#define DMA_INT_CLR_CH4_REG (DR_REG_DMA_BASE + 0x078) +/* DMA_OUTFIFO_UDF_L3_CH4_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L3_CH4_INT_CLR (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_CLR_M (BIT(17)) +#define DMA_OUTFIFO_UDF_L3_CH4_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L3_CH4_INT_CLR_S 17 +/* DMA_OUTFIFO_OVF_L3_CH4_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L3_CH4_INT_CLR (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_CLR_M (BIT(16)) +#define DMA_OUTFIFO_OVF_L3_CH4_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L3_CH4_INT_CLR_S 16 +/* DMA_OUTFIFO_UDF_L1_CH4_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_UDF_L1_CH4_INT_CLR (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_M (BIT(15)) +#define DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_V 0x1 +#define DMA_OUTFIFO_UDF_L1_CH4_INT_CLR_S 15 +/* DMA_OUTFIFO_OVF_L1_CH4_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_OUTFIFO_OVF_L1_CH4_INT_CLR (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_M (BIT(14)) +#define DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_V 0x1 +#define DMA_OUTFIFO_OVF_L1_CH4_INT_CLR_S 14 +/* DMA_INFIFO_UDF_L3_CH4_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L3_CH4_INT_CLR (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_CLR_M (BIT(13)) +#define DMA_INFIFO_UDF_L3_CH4_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L3_CH4_INT_CLR_S 13 +/* DMA_INFIFO_OVF_L3_CH4_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L3_CH4_INT_CLR (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_CLR_M (BIT(12)) +#define DMA_INFIFO_OVF_L3_CH4_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L3_CH4_INT_CLR_S 12 +/* DMA_INFIFO_UDF_L1_CH4_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_UDF_L1_CH4_INT_CLR (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_CLR_M (BIT(11)) +#define DMA_INFIFO_UDF_L1_CH4_INT_CLR_V 0x1 +#define DMA_INFIFO_UDF_L1_CH4_INT_CLR_S 11 +/* DMA_INFIFO_OVF_L1_CH4_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ +#define DMA_INFIFO_OVF_L1_CH4_INT_CLR (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_CLR_M (BIT(10)) +#define DMA_INFIFO_OVF_L1_CH4_INT_CLR_V 0x1 +#define DMA_INFIFO_OVF_L1_CH4_INT_CLR_S 10 +/* DMA_INFIFO_FULL_WM_CH4_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ +#define DMA_INFIFO_FULL_WM_CH4_INT_CLR (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_CLR_M (BIT(9)) +#define DMA_INFIFO_FULL_WM_CH4_INT_CLR_V 0x1 +#define DMA_INFIFO_FULL_WM_CH4_INT_CLR_S 9 +/* DMA_OUT_TOTAL_EOF_CH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ +#define DMA_OUT_TOTAL_EOF_CH4_INT_CLR (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_CLR_M (BIT(8)) +#define DMA_OUT_TOTAL_EOF_CH4_INT_CLR_V 0x1 +#define DMA_OUT_TOTAL_EOF_CH4_INT_CLR_S 8 +/* DMA_IN_DSCR_EMPTY_CH4_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ +#define DMA_IN_DSCR_EMPTY_CH4_INT_CLR (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_CLR_M (BIT(7)) +#define DMA_IN_DSCR_EMPTY_CH4_INT_CLR_V 0x1 +#define DMA_IN_DSCR_EMPTY_CH4_INT_CLR_S 7 +/* DMA_OUT_DSCR_ERR_CH4_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_OUT_DSCR_ERR_CH4_INT_CLR (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_CLR_M (BIT(6)) +#define DMA_OUT_DSCR_ERR_CH4_INT_CLR_V 0x1 +#define DMA_OUT_DSCR_ERR_CH4_INT_CLR_S 6 +/* DMA_IN_DSCR_ERR_CH4_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ +#define DMA_IN_DSCR_ERR_CH4_INT_CLR (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_CLR_M (BIT(5)) +#define DMA_IN_DSCR_ERR_CH4_INT_CLR_V 0x1 +#define DMA_IN_DSCR_ERR_CH4_INT_CLR_S 5 +/* DMA_OUT_EOF_CH4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ +#define DMA_OUT_EOF_CH4_INT_CLR (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_CLR_M (BIT(4)) +#define DMA_OUT_EOF_CH4_INT_CLR_V 0x1 +#define DMA_OUT_EOF_CH4_INT_CLR_S 4 +/* DMA_OUT_DONE_CH4_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ +#define DMA_OUT_DONE_CH4_INT_CLR (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_CLR_M (BIT(3)) +#define DMA_OUT_DONE_CH4_INT_CLR_V 0x1 +#define DMA_OUT_DONE_CH4_INT_CLR_S 3 +/* DMA_IN_ERR_EOF_CH4_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ +#define DMA_IN_ERR_EOF_CH4_INT_CLR (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_CLR_M (BIT(2)) +#define DMA_IN_ERR_EOF_CH4_INT_CLR_V 0x1 +#define DMA_IN_ERR_EOF_CH4_INT_CLR_S 2 +/* DMA_IN_SUC_EOF_CH4_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ +#define DMA_IN_SUC_EOF_CH4_INT_CLR (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_CLR_M (BIT(1)) +#define DMA_IN_SUC_EOF_CH4_INT_CLR_V 0x1 +#define DMA_IN_SUC_EOF_CH4_INT_CLR_S 1 +/* DMA_IN_DONE_CH4_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the IN_DONE_CH_INT interrupt.*/ +#define DMA_IN_DONE_CH4_INT_CLR (BIT(0)) +#define DMA_IN_DONE_CH4_INT_CLR_M (BIT(0)) +#define DMA_IN_DONE_CH4_INT_CLR_V 0x1 +#define DMA_IN_DONE_CH4_INT_CLR_S 0 + +#define DMA_INFIFO_STATUS_CH0_REG (DR_REG_DMA_BASE + 0x07C) +/* DMA_IN_BUF_HUNGRY_CH0 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH0 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH0_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH0_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH0_S 27 +/* DMA_IN_REMAIN_UNDER_4B_L3_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_L3_CH0 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH0_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_L3_CH0_S 26 +/* DMA_IN_REMAIN_UNDER_3B_L3_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_L3_CH0 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH0_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_L3_CH0_S 25 +/* DMA_IN_REMAIN_UNDER_2B_L3_CH0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_L3_CH0 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH0_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_L3_CH0_S 24 +/* DMA_IN_REMAIN_UNDER_1B_L3_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_L3_CH0 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH0_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH0_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_L3_CH0_S 23 +/* DMA_INFIFO_CNT_L3_CH0 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ +#define DMA_INFIFO_CNT_L3_CH0 0x0000001F +#define DMA_INFIFO_CNT_L3_CH0_M ((DMA_INFIFO_CNT_L3_CH0_V) << (DMA_INFIFO_CNT_L3_CH0_S)) +#define DMA_INFIFO_CNT_L3_CH0_V 0x1F +#define DMA_INFIFO_CNT_L3_CH0_S 18 +/* DMA_INFIFO_CNT_L2_CH0 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ +#define DMA_INFIFO_CNT_L2_CH0 0x0000007F +#define DMA_INFIFO_CNT_L2_CH0_M ((DMA_INFIFO_CNT_L2_CH0_V) << (DMA_INFIFO_CNT_L2_CH0_S)) +#define DMA_INFIFO_CNT_L2_CH0_V 0x7F +#define DMA_INFIFO_CNT_L2_CH0_S 11 +/* DMA_INFIFO_CNT_L1_CH0 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ +#define DMA_INFIFO_CNT_L1_CH0 0x0000001F +#define DMA_INFIFO_CNT_L1_CH0_M ((DMA_INFIFO_CNT_L1_CH0_V) << (DMA_INFIFO_CNT_L1_CH0_S)) +#define DMA_INFIFO_CNT_L1_CH0_V 0x1F +#define DMA_INFIFO_CNT_L1_CH0_S 6 +/* DMA_INFIFO_EMPTY_L3_CH0 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 0.*/ +#define DMA_INFIFO_EMPTY_L3_CH0 (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH0_M (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH0_V 0x1 +#define DMA_INFIFO_EMPTY_L3_CH0_S 5 +/* DMA_INFIFO_FULL_L3_CH0 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 0.*/ +#define DMA_INFIFO_FULL_L3_CH0 (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH0_M (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH0_V 0x1 +#define DMA_INFIFO_FULL_L3_CH0_S 4 +/* DMA_INFIFO_EMPTY_L2_CH0 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 0.*/ +#define DMA_INFIFO_EMPTY_L2_CH0 (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH0_M (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH0_V 0x1 +#define DMA_INFIFO_EMPTY_L2_CH0_S 3 +/* DMA_INFIFO_FULL_L2_CH0 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 0.*/ +#define DMA_INFIFO_FULL_L2_CH0 (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH0_M (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH0_V 0x1 +#define DMA_INFIFO_FULL_L2_CH0_S 2 +/* DMA_INFIFO_EMPTY_L1_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 0.*/ +#define DMA_INFIFO_EMPTY_L1_CH0 (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH0_M (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH0_V 0x1 +#define DMA_INFIFO_EMPTY_L1_CH0_S 1 +/* DMA_INFIFO_FULL_L1_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 0.*/ +#define DMA_INFIFO_FULL_L1_CH0 (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH0_M (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH0_V 0x1 +#define DMA_INFIFO_FULL_L1_CH0_S 0 + +#define DMA_INFIFO_STATUS_CH1_REG (DR_REG_DMA_BASE + 0x080) +/* DMA_IN_BUF_HUNGRY_CH1 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH1 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH1_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH1_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH1_S 27 +/* DMA_IN_REMAIN_UNDER_4B_L3_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_L3_CH1 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH1_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_L3_CH1_S 26 +/* DMA_IN_REMAIN_UNDER_3B_L3_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_L3_CH1 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH1_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_L3_CH1_S 25 +/* DMA_IN_REMAIN_UNDER_2B_L3_CH1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_L3_CH1 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH1_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_L3_CH1_S 24 +/* DMA_IN_REMAIN_UNDER_1B_L3_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_L3_CH1 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH1_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH1_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_L3_CH1_S 23 +/* DMA_INFIFO_CNT_L3_CH1 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 1.*/ +#define DMA_INFIFO_CNT_L3_CH1 0x0000001F +#define DMA_INFIFO_CNT_L3_CH1_M ((DMA_INFIFO_CNT_L3_CH1_V) << (DMA_INFIFO_CNT_L3_CH1_S)) +#define DMA_INFIFO_CNT_L3_CH1_V 0x1F +#define DMA_INFIFO_CNT_L3_CH1_S 18 +/* DMA_INFIFO_CNT_L2_CH1 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 1.*/ +#define DMA_INFIFO_CNT_L2_CH1 0x0000007F +#define DMA_INFIFO_CNT_L2_CH1_M ((DMA_INFIFO_CNT_L2_CH1_V) << (DMA_INFIFO_CNT_L2_CH1_S)) +#define DMA_INFIFO_CNT_L2_CH1_V 0x7F +#define DMA_INFIFO_CNT_L2_CH1_S 11 +/* DMA_INFIFO_CNT_L1_CH1 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.*/ +#define DMA_INFIFO_CNT_L1_CH1 0x0000001F +#define DMA_INFIFO_CNT_L1_CH1_M ((DMA_INFIFO_CNT_L1_CH1_V) << (DMA_INFIFO_CNT_L1_CH1_S)) +#define DMA_INFIFO_CNT_L1_CH1_V 0x1F +#define DMA_INFIFO_CNT_L1_CH1_S 6 +/* DMA_INFIFO_EMPTY_L3_CH1 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 1.*/ +#define DMA_INFIFO_EMPTY_L3_CH1 (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH1_M (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH1_V 0x1 +#define DMA_INFIFO_EMPTY_L3_CH1_S 5 +/* DMA_INFIFO_FULL_L3_CH1 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 1.*/ +#define DMA_INFIFO_FULL_L3_CH1 (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH1_M (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH1_V 0x1 +#define DMA_INFIFO_FULL_L3_CH1_S 4 +/* DMA_INFIFO_EMPTY_L2_CH1 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 1.*/ +#define DMA_INFIFO_EMPTY_L2_CH1 (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH1_M (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH1_V 0x1 +#define DMA_INFIFO_EMPTY_L2_CH1_S 3 +/* DMA_INFIFO_FULL_L2_CH1 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 1.*/ +#define DMA_INFIFO_FULL_L2_CH1 (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH1_M (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH1_V 0x1 +#define DMA_INFIFO_FULL_L2_CH1_S 2 +/* DMA_INFIFO_EMPTY_L1_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 1.*/ +#define DMA_INFIFO_EMPTY_L1_CH1 (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH1_M (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH1_V 0x1 +#define DMA_INFIFO_EMPTY_L1_CH1_S 1 +/* DMA_INFIFO_FULL_L1_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 1.*/ +#define DMA_INFIFO_FULL_L1_CH1 (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH1_M (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH1_V 0x1 +#define DMA_INFIFO_FULL_L1_CH1_S 0 + +#define DMA_INFIFO_STATUS_CH2_REG (DR_REG_DMA_BASE + 0x084) +/* DMA_IN_BUF_HUNGRY_CH2 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH2 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH2_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH2_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH2_S 27 +/* DMA_IN_REMAIN_UNDER_4B_L3_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_L3_CH2 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH2_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_L3_CH2_S 26 +/* DMA_IN_REMAIN_UNDER_3B_L3_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_L3_CH2 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH2_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_L3_CH2_S 25 +/* DMA_IN_REMAIN_UNDER_2B_L3_CH2 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_L3_CH2 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH2_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_L3_CH2_S 24 +/* DMA_IN_REMAIN_UNDER_1B_L3_CH2 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_L3_CH2 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH2_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH2_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_L3_CH2_S 23 +/* DMA_INFIFO_CNT_L3_CH2 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 2.*/ +#define DMA_INFIFO_CNT_L3_CH2 0x0000001F +#define DMA_INFIFO_CNT_L3_CH2_M ((DMA_INFIFO_CNT_L3_CH2_V) << (DMA_INFIFO_CNT_L3_CH2_S)) +#define DMA_INFIFO_CNT_L3_CH2_V 0x1F +#define DMA_INFIFO_CNT_L3_CH2_S 18 +/* DMA_INFIFO_CNT_L2_CH2 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 2.*/ +#define DMA_INFIFO_CNT_L2_CH2 0x0000007F +#define DMA_INFIFO_CNT_L2_CH2_M ((DMA_INFIFO_CNT_L2_CH2_V) << (DMA_INFIFO_CNT_L2_CH2_S)) +#define DMA_INFIFO_CNT_L2_CH2_V 0x7F +#define DMA_INFIFO_CNT_L2_CH2_S 11 +/* DMA_INFIFO_CNT_L1_CH2 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.*/ +#define DMA_INFIFO_CNT_L1_CH2 0x0000001F +#define DMA_INFIFO_CNT_L1_CH2_M ((DMA_INFIFO_CNT_L1_CH2_V) << (DMA_INFIFO_CNT_L1_CH2_S)) +#define DMA_INFIFO_CNT_L1_CH2_V 0x1F +#define DMA_INFIFO_CNT_L1_CH2_S 6 +/* DMA_INFIFO_EMPTY_L3_CH2 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 2.*/ +#define DMA_INFIFO_EMPTY_L3_CH2 (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH2_M (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH2_V 0x1 +#define DMA_INFIFO_EMPTY_L3_CH2_S 5 +/* DMA_INFIFO_FULL_L3_CH2 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 2.*/ +#define DMA_INFIFO_FULL_L3_CH2 (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH2_M (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH2_V 0x1 +#define DMA_INFIFO_FULL_L3_CH2_S 4 +/* DMA_INFIFO_EMPTY_L2_CH2 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 2.*/ +#define DMA_INFIFO_EMPTY_L2_CH2 (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH2_M (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH2_V 0x1 +#define DMA_INFIFO_EMPTY_L2_CH2_S 3 +/* DMA_INFIFO_FULL_L2_CH2 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 2.*/ +#define DMA_INFIFO_FULL_L2_CH2 (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH2_M (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH2_V 0x1 +#define DMA_INFIFO_FULL_L2_CH2_S 2 +/* DMA_INFIFO_EMPTY_L1_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 2.*/ +#define DMA_INFIFO_EMPTY_L1_CH2 (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH2_M (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH2_V 0x1 +#define DMA_INFIFO_EMPTY_L1_CH2_S 1 +/* DMA_INFIFO_FULL_L1_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 2.*/ +#define DMA_INFIFO_FULL_L1_CH2 (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH2_M (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH2_V 0x1 +#define DMA_INFIFO_FULL_L1_CH2_S 0 + +#define DMA_INFIFO_STATUS_CH3_REG (DR_REG_DMA_BASE + 0x088) +/* DMA_IN_BUF_HUNGRY_CH3 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH3 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH3_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH3_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH3_S 27 +/* DMA_IN_REMAIN_UNDER_4B_L3_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_L3_CH3 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH3_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH3_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_L3_CH3_S 26 +/* DMA_IN_REMAIN_UNDER_3B_L3_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_L3_CH3 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH3_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH3_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_L3_CH3_S 25 +/* DMA_IN_REMAIN_UNDER_2B_L3_CH3 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_L3_CH3 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH3_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH3_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_L3_CH3_S 24 +/* DMA_IN_REMAIN_UNDER_1B_L3_CH3 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_L3_CH3 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH3_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH3_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_L3_CH3_S 23 +/* DMA_INFIFO_CNT_L3_CH3 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 3.*/ +#define DMA_INFIFO_CNT_L3_CH3 0x0000001F +#define DMA_INFIFO_CNT_L3_CH3_M ((DMA_INFIFO_CNT_L3_CH3_V) << (DMA_INFIFO_CNT_L3_CH3_S)) +#define DMA_INFIFO_CNT_L3_CH3_V 0x1F +#define DMA_INFIFO_CNT_L3_CH3_S 18 +/* DMA_INFIFO_CNT_L2_CH3 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 3.*/ +#define DMA_INFIFO_CNT_L2_CH3 0x0000007F +#define DMA_INFIFO_CNT_L2_CH3_M ((DMA_INFIFO_CNT_L2_CH3_V) << (DMA_INFIFO_CNT_L2_CH3_S)) +#define DMA_INFIFO_CNT_L2_CH3_V 0x7F +#define DMA_INFIFO_CNT_L2_CH3_S 11 +/* DMA_INFIFO_CNT_L1_CH3 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 3.*/ +#define DMA_INFIFO_CNT_L1_CH3 0x0000001F +#define DMA_INFIFO_CNT_L1_CH3_M ((DMA_INFIFO_CNT_L1_CH3_V) << (DMA_INFIFO_CNT_L1_CH3_S)) +#define DMA_INFIFO_CNT_L1_CH3_V 0x1F +#define DMA_INFIFO_CNT_L1_CH3_S 6 +/* DMA_INFIFO_EMPTY_L3_CH3 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 3.*/ +#define DMA_INFIFO_EMPTY_L3_CH3 (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH3_M (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH3_V 0x1 +#define DMA_INFIFO_EMPTY_L3_CH3_S 5 +/* DMA_INFIFO_FULL_L3_CH3 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 3.*/ +#define DMA_INFIFO_FULL_L3_CH3 (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH3_M (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH3_V 0x1 +#define DMA_INFIFO_FULL_L3_CH3_S 4 +/* DMA_INFIFO_EMPTY_L2_CH3 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 3.*/ +#define DMA_INFIFO_EMPTY_L2_CH3 (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH3_M (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH3_V 0x1 +#define DMA_INFIFO_EMPTY_L2_CH3_S 3 +/* DMA_INFIFO_FULL_L2_CH3 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 3.*/ +#define DMA_INFIFO_FULL_L2_CH3 (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH3_M (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH3_V 0x1 +#define DMA_INFIFO_FULL_L2_CH3_S 2 +/* DMA_INFIFO_EMPTY_L1_CH3 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 3.*/ +#define DMA_INFIFO_EMPTY_L1_CH3 (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH3_M (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH3_V 0x1 +#define DMA_INFIFO_EMPTY_L1_CH3_S 1 +/* DMA_INFIFO_FULL_L1_CH3 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 3.*/ +#define DMA_INFIFO_FULL_L1_CH3 (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH3_M (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH3_V 0x1 +#define DMA_INFIFO_FULL_L1_CH3_S 0 + +#define DMA_INFIFO_STATUS_CH4_REG (DR_REG_DMA_BASE + 0x08C) +/* DMA_IN_BUF_HUNGRY_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_BUF_HUNGRY_CH4 (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH4_M (BIT(27)) +#define DMA_IN_BUF_HUNGRY_CH4_V 0x1 +#define DMA_IN_BUF_HUNGRY_CH4_S 27 +/* DMA_IN_REMAIN_UNDER_4B_L3_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_4B_L3_CH4 (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH4_M (BIT(26)) +#define DMA_IN_REMAIN_UNDER_4B_L3_CH4_V 0x1 +#define DMA_IN_REMAIN_UNDER_4B_L3_CH4_S 26 +/* DMA_IN_REMAIN_UNDER_3B_L3_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_3B_L3_CH4 (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH4_M (BIT(25)) +#define DMA_IN_REMAIN_UNDER_3B_L3_CH4_V 0x1 +#define DMA_IN_REMAIN_UNDER_3B_L3_CH4_S 25 +/* DMA_IN_REMAIN_UNDER_2B_L3_CH4 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_2B_L3_CH4 (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH4_M (BIT(24)) +#define DMA_IN_REMAIN_UNDER_2B_L3_CH4_V 0x1 +#define DMA_IN_REMAIN_UNDER_2B_L3_CH4_S 24 +/* DMA_IN_REMAIN_UNDER_1B_L3_CH4 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_IN_REMAIN_UNDER_1B_L3_CH4 (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH4_M (BIT(23)) +#define DMA_IN_REMAIN_UNDER_1B_L3_CH4_V 0x1 +#define DMA_IN_REMAIN_UNDER_1B_L3_CH4_S 23 +/* DMA_INFIFO_CNT_L3_CH4 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Rx FIFO for Rx channel 4.*/ +#define DMA_INFIFO_CNT_L3_CH4 0x0000001F +#define DMA_INFIFO_CNT_L3_CH4_M ((DMA_INFIFO_CNT_L3_CH4_V) << (DMA_INFIFO_CNT_L3_CH4_S)) +#define DMA_INFIFO_CNT_L3_CH4_V 0x1F +#define DMA_INFIFO_CNT_L3_CH4_S 18 +/* DMA_INFIFO_CNT_L2_CH4 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Rx FIFO for Rx channel 4.*/ +#define DMA_INFIFO_CNT_L2_CH4 0x0000007F +#define DMA_INFIFO_CNT_L2_CH4_M ((DMA_INFIFO_CNT_L2_CH4_V) << (DMA_INFIFO_CNT_L2_CH4_S)) +#define DMA_INFIFO_CNT_L2_CH4_V 0x7F +#define DMA_INFIFO_CNT_L2_CH4_S 11 +/* DMA_INFIFO_CNT_L1_CH4 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Rx FIFO for Rx channel 4.*/ +#define DMA_INFIFO_CNT_L1_CH4 0x0000001F +#define DMA_INFIFO_CNT_L1_CH4_M ((DMA_INFIFO_CNT_L1_CH4_V) << (DMA_INFIFO_CNT_L1_CH4_S)) +#define DMA_INFIFO_CNT_L1_CH4_V 0x1F +#define DMA_INFIFO_CNT_L1_CH4_S 6 +/* DMA_INFIFO_EMPTY_L3_CH4 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Rx FIFO empty signal for Rx channel 4.*/ +#define DMA_INFIFO_EMPTY_L3_CH4 (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH4_M (BIT(5)) +#define DMA_INFIFO_EMPTY_L3_CH4_V 0x1 +#define DMA_INFIFO_EMPTY_L3_CH4_S 5 +/* DMA_INFIFO_FULL_L3_CH4 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Rx FIFO full signal for Rx channel 4.*/ +#define DMA_INFIFO_FULL_L3_CH4 (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH4_M (BIT(4)) +#define DMA_INFIFO_FULL_L3_CH4_V 0x1 +#define DMA_INFIFO_FULL_L3_CH4_S 4 +/* DMA_INFIFO_EMPTY_L2_CH4 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Rx FIFO empty signal for Rx channel 4.*/ +#define DMA_INFIFO_EMPTY_L2_CH4 (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH4_M (BIT(3)) +#define DMA_INFIFO_EMPTY_L2_CH4_V 0x1 +#define DMA_INFIFO_EMPTY_L2_CH4_S 3 +/* DMA_INFIFO_FULL_L2_CH4 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Rx FIFO full signal for Rx channel 4.*/ +#define DMA_INFIFO_FULL_L2_CH4 (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH4_M (BIT(2)) +#define DMA_INFIFO_FULL_L2_CH4_V 0x1 +#define DMA_INFIFO_FULL_L2_CH4_S 2 +/* DMA_INFIFO_EMPTY_L1_CH4 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Rx FIFO empty signal for Rx channel 4.*/ +#define DMA_INFIFO_EMPTY_L1_CH4 (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH4_M (BIT(1)) +#define DMA_INFIFO_EMPTY_L1_CH4_V 0x1 +#define DMA_INFIFO_EMPTY_L1_CH4_S 1 +/* DMA_INFIFO_FULL_L1_CH4 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Rx FIFO full signal for Rx channel 4.*/ +#define DMA_INFIFO_FULL_L1_CH4 (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH4_M (BIT(0)) +#define DMA_INFIFO_FULL_L1_CH4_V 0x1 +#define DMA_INFIFO_FULL_L1_CH4_S 0 + +#define DMA_OUTFIFO_STATUS_CH0_REG (DR_REG_DMA_BASE + 0x090) +/* DMA_OUT_REMAIN_UNDER_4B_L3_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH0 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH0_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH0_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_L3_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH0 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH0_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH0_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_L3_CH0 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH0 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH0_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH0_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_L3_CH0 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH0 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH0_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH0_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH0_S 23 +/* DMA_OUTFIFO_CNT_L3_CH0 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ +#define DMA_OUTFIFO_CNT_L3_CH0 0x0000001F +#define DMA_OUTFIFO_CNT_L3_CH0_M ((DMA_OUTFIFO_CNT_L3_CH0_V) << (DMA_OUTFIFO_CNT_L3_CH0_S)) +#define DMA_OUTFIFO_CNT_L3_CH0_V 0x1F +#define DMA_OUTFIFO_CNT_L3_CH0_S 18 +/* DMA_OUTFIFO_CNT_L2_CH0 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ +#define DMA_OUTFIFO_CNT_L2_CH0 0x0000007F +#define DMA_OUTFIFO_CNT_L2_CH0_M ((DMA_OUTFIFO_CNT_L2_CH0_V) << (DMA_OUTFIFO_CNT_L2_CH0_S)) +#define DMA_OUTFIFO_CNT_L2_CH0_V 0x7F +#define DMA_OUTFIFO_CNT_L2_CH0_S 11 +/* DMA_OUTFIFO_CNT_L1_CH0 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ +#define DMA_OUTFIFO_CNT_L1_CH0 0x0000001F +#define DMA_OUTFIFO_CNT_L1_CH0_M ((DMA_OUTFIFO_CNT_L1_CH0_V) << (DMA_OUTFIFO_CNT_L1_CH0_S)) +#define DMA_OUTFIFO_CNT_L1_CH0_V 0x1F +#define DMA_OUTFIFO_CNT_L1_CH0_S 6 +/* DMA_OUTFIFO_EMPTY_L3_CH0 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 0.*/ +#define DMA_OUTFIFO_EMPTY_L3_CH0 (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH0_M (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH0_V 0x1 +#define DMA_OUTFIFO_EMPTY_L3_CH0_S 5 +/* DMA_OUTFIFO_FULL_L3_CH0 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 0.*/ +#define DMA_OUTFIFO_FULL_L3_CH0 (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH0_M (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH0_V 0x1 +#define DMA_OUTFIFO_FULL_L3_CH0_S 4 +/* DMA_OUTFIFO_EMPTY_L2_CH0 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 0.*/ +#define DMA_OUTFIFO_EMPTY_L2_CH0 (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH0_M (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH0_V 0x1 +#define DMA_OUTFIFO_EMPTY_L2_CH0_S 3 +/* DMA_OUTFIFO_FULL_L2_CH0 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 0.*/ +#define DMA_OUTFIFO_FULL_L2_CH0 (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH0_M (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH0_V 0x1 +#define DMA_OUTFIFO_FULL_L2_CH0_S 2 +/* DMA_OUTFIFO_EMPTY_L1_CH0 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 0.*/ +#define DMA_OUTFIFO_EMPTY_L1_CH0 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH0_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH0_V 0x1 +#define DMA_OUTFIFO_EMPTY_L1_CH0_S 1 +/* DMA_OUTFIFO_FULL_L1_CH0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 0.*/ +#define DMA_OUTFIFO_FULL_L1_CH0 (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH0_M (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH0_V 0x1 +#define DMA_OUTFIFO_FULL_L1_CH0_S 0 + +#define DMA_OUTFIFO_STATUS_CH1_REG (DR_REG_DMA_BASE + 0x094) +/* DMA_OUT_REMAIN_UNDER_4B_L3_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH1 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH1_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH1_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_L3_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH1 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH1_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH1_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_L3_CH1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH1 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH1_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH1_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_L3_CH1 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH1 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH1_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH1_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH1_S 23 +/* DMA_OUTFIFO_CNT_L3_CH1 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 1.*/ +#define DMA_OUTFIFO_CNT_L3_CH1 0x0000001F +#define DMA_OUTFIFO_CNT_L3_CH1_M ((DMA_OUTFIFO_CNT_L3_CH1_V) << (DMA_OUTFIFO_CNT_L3_CH1_S)) +#define DMA_OUTFIFO_CNT_L3_CH1_V 0x1F +#define DMA_OUTFIFO_CNT_L3_CH1_S 18 +/* DMA_OUTFIFO_CNT_L2_CH1 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 1.*/ +#define DMA_OUTFIFO_CNT_L2_CH1 0x0000007F +#define DMA_OUTFIFO_CNT_L2_CH1_M ((DMA_OUTFIFO_CNT_L2_CH1_V) << (DMA_OUTFIFO_CNT_L2_CH1_S)) +#define DMA_OUTFIFO_CNT_L2_CH1_V 0x7F +#define DMA_OUTFIFO_CNT_L2_CH1_S 11 +/* DMA_OUTFIFO_CNT_L1_CH1 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.*/ +#define DMA_OUTFIFO_CNT_L1_CH1 0x0000001F +#define DMA_OUTFIFO_CNT_L1_CH1_M ((DMA_OUTFIFO_CNT_L1_CH1_V) << (DMA_OUTFIFO_CNT_L1_CH1_S)) +#define DMA_OUTFIFO_CNT_L1_CH1_V 0x1F +#define DMA_OUTFIFO_CNT_L1_CH1_S 6 +/* DMA_OUTFIFO_EMPTY_L3_CH1 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 1.*/ +#define DMA_OUTFIFO_EMPTY_L3_CH1 (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH1_M (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH1_V 0x1 +#define DMA_OUTFIFO_EMPTY_L3_CH1_S 5 +/* DMA_OUTFIFO_FULL_L3_CH1 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 1.*/ +#define DMA_OUTFIFO_FULL_L3_CH1 (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH1_M (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH1_V 0x1 +#define DMA_OUTFIFO_FULL_L3_CH1_S 4 +/* DMA_OUTFIFO_EMPTY_L2_CH1 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 1.*/ +#define DMA_OUTFIFO_EMPTY_L2_CH1 (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH1_M (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH1_V 0x1 +#define DMA_OUTFIFO_EMPTY_L2_CH1_S 3 +/* DMA_OUTFIFO_FULL_L2_CH1 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 1.*/ +#define DMA_OUTFIFO_FULL_L2_CH1 (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH1_M (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH1_V 0x1 +#define DMA_OUTFIFO_FULL_L2_CH1_S 2 +/* DMA_OUTFIFO_EMPTY_L1_CH1 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 1.*/ +#define DMA_OUTFIFO_EMPTY_L1_CH1 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH1_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH1_V 0x1 +#define DMA_OUTFIFO_EMPTY_L1_CH1_S 1 +/* DMA_OUTFIFO_FULL_L1_CH1 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 1.*/ +#define DMA_OUTFIFO_FULL_L1_CH1 (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH1_M (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH1_V 0x1 +#define DMA_OUTFIFO_FULL_L1_CH1_S 0 + +#define DMA_OUTFIFO_STATUS_CH2_REG (DR_REG_DMA_BASE + 0x098) +/* DMA_OUT_REMAIN_UNDER_4B_L3_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH2 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH2_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH2_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_L3_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH2 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH2_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH2_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_L3_CH2 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH2 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH2_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH2_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_L3_CH2 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH2 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH2_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH2_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH2_S 23 +/* DMA_OUTFIFO_CNT_L3_CH2 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 2.*/ +#define DMA_OUTFIFO_CNT_L3_CH2 0x0000001F +#define DMA_OUTFIFO_CNT_L3_CH2_M ((DMA_OUTFIFO_CNT_L3_CH2_V) << (DMA_OUTFIFO_CNT_L3_CH2_S)) +#define DMA_OUTFIFO_CNT_L3_CH2_V 0x1F +#define DMA_OUTFIFO_CNT_L3_CH2_S 18 +/* DMA_OUTFIFO_CNT_L2_CH2 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 2.*/ +#define DMA_OUTFIFO_CNT_L2_CH2 0x0000007F +#define DMA_OUTFIFO_CNT_L2_CH2_M ((DMA_OUTFIFO_CNT_L2_CH2_V) << (DMA_OUTFIFO_CNT_L2_CH2_S)) +#define DMA_OUTFIFO_CNT_L2_CH2_V 0x7F +#define DMA_OUTFIFO_CNT_L2_CH2_S 11 +/* DMA_OUTFIFO_CNT_L1_CH2 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.*/ +#define DMA_OUTFIFO_CNT_L1_CH2 0x0000001F +#define DMA_OUTFIFO_CNT_L1_CH2_M ((DMA_OUTFIFO_CNT_L1_CH2_V) << (DMA_OUTFIFO_CNT_L1_CH2_S)) +#define DMA_OUTFIFO_CNT_L1_CH2_V 0x1F +#define DMA_OUTFIFO_CNT_L1_CH2_S 6 +/* DMA_OUTFIFO_EMPTY_L3_CH2 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 2.*/ +#define DMA_OUTFIFO_EMPTY_L3_CH2 (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH2_M (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH2_V 0x1 +#define DMA_OUTFIFO_EMPTY_L3_CH2_S 5 +/* DMA_OUTFIFO_FULL_L3_CH2 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 2.*/ +#define DMA_OUTFIFO_FULL_L3_CH2 (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH2_M (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH2_V 0x1 +#define DMA_OUTFIFO_FULL_L3_CH2_S 4 +/* DMA_OUTFIFO_EMPTY_L2_CH2 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 2.*/ +#define DMA_OUTFIFO_EMPTY_L2_CH2 (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH2_M (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH2_V 0x1 +#define DMA_OUTFIFO_EMPTY_L2_CH2_S 3 +/* DMA_OUTFIFO_FULL_L2_CH2 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 2.*/ +#define DMA_OUTFIFO_FULL_L2_CH2 (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH2_M (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH2_V 0x1 +#define DMA_OUTFIFO_FULL_L2_CH2_S 2 +/* DMA_OUTFIFO_EMPTY_L1_CH2 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 2.*/ +#define DMA_OUTFIFO_EMPTY_L1_CH2 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH2_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH2_V 0x1 +#define DMA_OUTFIFO_EMPTY_L1_CH2_S 1 +/* DMA_OUTFIFO_FULL_L1_CH2 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 2.*/ +#define DMA_OUTFIFO_FULL_L1_CH2 (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH2_M (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH2_V 0x1 +#define DMA_OUTFIFO_FULL_L1_CH2_S 0 + +#define DMA_OUTFIFO_STATUS_CH3_REG (DR_REG_DMA_BASE + 0x09C) +/* DMA_OUT_REMAIN_UNDER_4B_L3_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH3 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH3_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH3_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH3_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_L3_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH3 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH3_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH3_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH3_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_L3_CH3 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH3 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH3_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH3_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH3_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_L3_CH3 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH3 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH3_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH3_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH3_S 23 +/* DMA_OUTFIFO_CNT_L3_CH3 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 3.*/ +#define DMA_OUTFIFO_CNT_L3_CH3 0x0000001F +#define DMA_OUTFIFO_CNT_L3_CH3_M ((DMA_OUTFIFO_CNT_L3_CH3_V) << (DMA_OUTFIFO_CNT_L3_CH3_S)) +#define DMA_OUTFIFO_CNT_L3_CH3_V 0x1F +#define DMA_OUTFIFO_CNT_L3_CH3_S 18 +/* DMA_OUTFIFO_CNT_L2_CH3 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 3.*/ +#define DMA_OUTFIFO_CNT_L2_CH3 0x0000007F +#define DMA_OUTFIFO_CNT_L2_CH3_M ((DMA_OUTFIFO_CNT_L2_CH3_V) << (DMA_OUTFIFO_CNT_L2_CH3_S)) +#define DMA_OUTFIFO_CNT_L2_CH3_V 0x7F +#define DMA_OUTFIFO_CNT_L2_CH3_S 11 +/* DMA_OUTFIFO_CNT_L1_CH3 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 3.*/ +#define DMA_OUTFIFO_CNT_L1_CH3 0x0000001F +#define DMA_OUTFIFO_CNT_L1_CH3_M ((DMA_OUTFIFO_CNT_L1_CH3_V) << (DMA_OUTFIFO_CNT_L1_CH3_S)) +#define DMA_OUTFIFO_CNT_L1_CH3_V 0x1F +#define DMA_OUTFIFO_CNT_L1_CH3_S 6 +/* DMA_OUTFIFO_EMPTY_L3_CH3 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 3.*/ +#define DMA_OUTFIFO_EMPTY_L3_CH3 (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH3_M (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH3_V 0x1 +#define DMA_OUTFIFO_EMPTY_L3_CH3_S 5 +/* DMA_OUTFIFO_FULL_L3_CH3 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 3.*/ +#define DMA_OUTFIFO_FULL_L3_CH3 (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH3_M (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH3_V 0x1 +#define DMA_OUTFIFO_FULL_L3_CH3_S 4 +/* DMA_OUTFIFO_EMPTY_L2_CH3 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 3.*/ +#define DMA_OUTFIFO_EMPTY_L2_CH3 (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH3_M (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH3_V 0x1 +#define DMA_OUTFIFO_EMPTY_L2_CH3_S 3 +/* DMA_OUTFIFO_FULL_L2_CH3 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 3.*/ +#define DMA_OUTFIFO_FULL_L2_CH3 (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH3_M (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH3_V 0x1 +#define DMA_OUTFIFO_FULL_L2_CH3_S 2 +/* DMA_OUTFIFO_EMPTY_L1_CH3 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 3.*/ +#define DMA_OUTFIFO_EMPTY_L1_CH3 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH3_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH3_V 0x1 +#define DMA_OUTFIFO_EMPTY_L1_CH3_S 1 +/* DMA_OUTFIFO_FULL_L1_CH3 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 3.*/ +#define DMA_OUTFIFO_FULL_L1_CH3 (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH3_M (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH3_V 0x1 +#define DMA_OUTFIFO_FULL_L1_CH3_S 0 + +#define DMA_OUTFIFO_STATUS_CH4_REG (DR_REG_DMA_BASE + 0x0A0) +/* DMA_OUT_REMAIN_UNDER_4B_L3_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH4 (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH4_M (BIT(26)) +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH4_V 0x1 +#define DMA_OUT_REMAIN_UNDER_4B_L3_CH4_S 26 +/* DMA_OUT_REMAIN_UNDER_3B_L3_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH4 (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH4_M (BIT(25)) +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH4_V 0x1 +#define DMA_OUT_REMAIN_UNDER_3B_L3_CH4_S 25 +/* DMA_OUT_REMAIN_UNDER_2B_L3_CH4 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH4 (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH4_M (BIT(24)) +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH4_V 0x1 +#define DMA_OUT_REMAIN_UNDER_2B_L3_CH4_S 24 +/* DMA_OUT_REMAIN_UNDER_1B_L3_CH4 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH4 (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH4_M (BIT(23)) +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH4_V 0x1 +#define DMA_OUT_REMAIN_UNDER_1B_L3_CH4_S 23 +/* DMA_OUTFIFO_CNT_L3_CH4 : RO ;bitpos:[22:18] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L3 Tx FIFO for Tx channel 4.*/ +#define DMA_OUTFIFO_CNT_L3_CH4 0x0000001F +#define DMA_OUTFIFO_CNT_L3_CH4_M ((DMA_OUTFIFO_CNT_L3_CH4_V) << (DMA_OUTFIFO_CNT_L3_CH4_S)) +#define DMA_OUTFIFO_CNT_L3_CH4_V 0x1F +#define DMA_OUTFIFO_CNT_L3_CH4_S 18 +/* DMA_OUTFIFO_CNT_L2_CH4 : RO ;bitpos:[17:11] ;default: 7'b0 ; */ +/*description: The register stores the byte number of the data in L2 Tx FIFO for Tx channel 4.*/ +#define DMA_OUTFIFO_CNT_L2_CH4 0x0000007F +#define DMA_OUTFIFO_CNT_L2_CH4_M ((DMA_OUTFIFO_CNT_L2_CH4_V) << (DMA_OUTFIFO_CNT_L2_CH4_S)) +#define DMA_OUTFIFO_CNT_L2_CH4_V 0x7F +#define DMA_OUTFIFO_CNT_L2_CH4_S 11 +/* DMA_OUTFIFO_CNT_L1_CH4 : RO ;bitpos:[10:6] ;default: 5'b0 ; */ +/*description: The register stores the byte number of the data in L1 Tx FIFO for Tx channel 4.*/ +#define DMA_OUTFIFO_CNT_L1_CH4 0x0000001F +#define DMA_OUTFIFO_CNT_L1_CH4_M ((DMA_OUTFIFO_CNT_L1_CH4_V) << (DMA_OUTFIFO_CNT_L1_CH4_S)) +#define DMA_OUTFIFO_CNT_L1_CH4_V 0x1F +#define DMA_OUTFIFO_CNT_L1_CH4_S 6 +/* DMA_OUTFIFO_EMPTY_L3_CH4 : RO ;bitpos:[5] ;default: 1'b1 ; */ +/*description: L3 Tx FIFO empty signal for Tx channel 4.*/ +#define DMA_OUTFIFO_EMPTY_L3_CH4 (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH4_M (BIT(5)) +#define DMA_OUTFIFO_EMPTY_L3_CH4_V 0x1 +#define DMA_OUTFIFO_EMPTY_L3_CH4_S 5 +/* DMA_OUTFIFO_FULL_L3_CH4 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: L3 Tx FIFO full signal for Tx channel 4.*/ +#define DMA_OUTFIFO_FULL_L3_CH4 (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH4_M (BIT(4)) +#define DMA_OUTFIFO_FULL_L3_CH4_V 0x1 +#define DMA_OUTFIFO_FULL_L3_CH4_S 4 +/* DMA_OUTFIFO_EMPTY_L2_CH4 : RO ;bitpos:[3] ;default: 1'b1 ; */ +/*description: L2 Tx FIFO empty signal for Tx channel 4.*/ +#define DMA_OUTFIFO_EMPTY_L2_CH4 (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH4_M (BIT(3)) +#define DMA_OUTFIFO_EMPTY_L2_CH4_V 0x1 +#define DMA_OUTFIFO_EMPTY_L2_CH4_S 3 +/* DMA_OUTFIFO_FULL_L2_CH4 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: L2 Tx FIFO full signal for Tx channel 4.*/ +#define DMA_OUTFIFO_FULL_L2_CH4 (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH4_M (BIT(2)) +#define DMA_OUTFIFO_FULL_L2_CH4_V 0x1 +#define DMA_OUTFIFO_FULL_L2_CH4_S 2 +/* DMA_OUTFIFO_EMPTY_L1_CH4 : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: L1 Tx FIFO empty signal for Tx channel 4.*/ +#define DMA_OUTFIFO_EMPTY_L1_CH4 (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH4_M (BIT(1)) +#define DMA_OUTFIFO_EMPTY_L1_CH4_V 0x1 +#define DMA_OUTFIFO_EMPTY_L1_CH4_S 1 +/* DMA_OUTFIFO_FULL_L1_CH4 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: L1 Tx FIFO full signal for Tx channel 4.*/ +#define DMA_OUTFIFO_FULL_L1_CH4 (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH4_M (BIT(0)) +#define DMA_OUTFIFO_FULL_L1_CH4_V 0x1 +#define DMA_OUTFIFO_FULL_L1_CH4_S 0 + +#define DMA_OUT_PUSH_CH0_REG (DR_REG_DMA_BASE + 0x0A4) +/* DMA_OUTFIFO_PUSH_CH0 : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH0 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH0_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH0_V 0x1 +#define DMA_OUTFIFO_PUSH_CH0_S 9 +/* DMA_OUTFIFO_WDATA_CH0 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH0 0x000001FF +#define DMA_OUTFIFO_WDATA_CH0_M ((DMA_OUTFIFO_WDATA_CH0_V) << (DMA_OUTFIFO_WDATA_CH0_S)) +#define DMA_OUTFIFO_WDATA_CH0_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH0_S 0 + +#define DMA_OUT_PUSH_CH1_REG (DR_REG_DMA_BASE + 0x0A8) +/* DMA_OUTFIFO_PUSH_CH1 : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH1 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH1_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH1_V 0x1 +#define DMA_OUTFIFO_PUSH_CH1_S 9 +/* DMA_OUTFIFO_WDATA_CH1 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH1 0x000001FF +#define DMA_OUTFIFO_WDATA_CH1_M ((DMA_OUTFIFO_WDATA_CH1_V) << (DMA_OUTFIFO_WDATA_CH1_S)) +#define DMA_OUTFIFO_WDATA_CH1_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH1_S 0 + +#define DMA_OUT_PUSH_CH2_REG (DR_REG_DMA_BASE + 0x0AC) +/* DMA_OUTFIFO_PUSH_CH2 : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH2 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH2_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH2_V 0x1 +#define DMA_OUTFIFO_PUSH_CH2_S 9 +/* DMA_OUTFIFO_WDATA_CH2 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH2 0x000001FF +#define DMA_OUTFIFO_WDATA_CH2_M ((DMA_OUTFIFO_WDATA_CH2_V) << (DMA_OUTFIFO_WDATA_CH2_S)) +#define DMA_OUTFIFO_WDATA_CH2_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH2_S 0 + +#define DMA_OUT_PUSH_CH3_REG (DR_REG_DMA_BASE + 0x0B0) +/* DMA_OUTFIFO_PUSH_CH3 : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH3 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH3_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH3_V 0x1 +#define DMA_OUTFIFO_PUSH_CH3_S 9 +/* DMA_OUTFIFO_WDATA_CH3 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH3 0x000001FF +#define DMA_OUTFIFO_WDATA_CH3_M ((DMA_OUTFIFO_WDATA_CH3_V) << (DMA_OUTFIFO_WDATA_CH3_S)) +#define DMA_OUTFIFO_WDATA_CH3_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH3_S 0 + +#define DMA_OUT_PUSH_CH4_REG (DR_REG_DMA_BASE + 0x0B4) +/* DMA_OUTFIFO_PUSH_CH4 : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: Set this bit to push data into DMA FIFO.*/ +#define DMA_OUTFIFO_PUSH_CH4 (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH4_M (BIT(9)) +#define DMA_OUTFIFO_PUSH_CH4_V 0x1 +#define DMA_OUTFIFO_PUSH_CH4_S 9 +/* DMA_OUTFIFO_WDATA_CH4 : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: This register stores the data that need to be pushed into DMA FIFO.*/ +#define DMA_OUTFIFO_WDATA_CH4 0x000001FF +#define DMA_OUTFIFO_WDATA_CH4_M ((DMA_OUTFIFO_WDATA_CH4_V) << (DMA_OUTFIFO_WDATA_CH4_S)) +#define DMA_OUTFIFO_WDATA_CH4_V 0x1FF +#define DMA_OUTFIFO_WDATA_CH4_S 0 + +#define DMA_IN_POP_CH0_REG (DR_REG_DMA_BASE + 0x0B8) +/* DMA_INFIFO_POP_CH0 : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH0 (BIT(12)) +#define DMA_INFIFO_POP_CH0_M (BIT(12)) +#define DMA_INFIFO_POP_CH0_V 0x1 +#define DMA_INFIFO_POP_CH0_S 12 +/* DMA_INFIFO_RDATA_CH0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH0 0x00000FFF +#define DMA_INFIFO_RDATA_CH0_M ((DMA_INFIFO_RDATA_CH0_V) << (DMA_INFIFO_RDATA_CH0_S)) +#define DMA_INFIFO_RDATA_CH0_V 0xFFF +#define DMA_INFIFO_RDATA_CH0_S 0 + +#define DMA_IN_POP_CH1_REG (DR_REG_DMA_BASE + 0x0BC) +/* DMA_INFIFO_POP_CH1 : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH1 (BIT(12)) +#define DMA_INFIFO_POP_CH1_M (BIT(12)) +#define DMA_INFIFO_POP_CH1_V 0x1 +#define DMA_INFIFO_POP_CH1_S 12 +/* DMA_INFIFO_RDATA_CH1 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH1 0x00000FFF +#define DMA_INFIFO_RDATA_CH1_M ((DMA_INFIFO_RDATA_CH1_V) << (DMA_INFIFO_RDATA_CH1_S)) +#define DMA_INFIFO_RDATA_CH1_V 0xFFF +#define DMA_INFIFO_RDATA_CH1_S 0 + +#define DMA_IN_POP_CH2_REG (DR_REG_DMA_BASE + 0x0C0) +/* DMA_INFIFO_POP_CH2 : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH2 (BIT(12)) +#define DMA_INFIFO_POP_CH2_M (BIT(12)) +#define DMA_INFIFO_POP_CH2_V 0x1 +#define DMA_INFIFO_POP_CH2_S 12 +/* DMA_INFIFO_RDATA_CH2 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH2 0x00000FFF +#define DMA_INFIFO_RDATA_CH2_M ((DMA_INFIFO_RDATA_CH2_V) << (DMA_INFIFO_RDATA_CH2_S)) +#define DMA_INFIFO_RDATA_CH2_V 0xFFF +#define DMA_INFIFO_RDATA_CH2_S 0 + +#define DMA_IN_POP_CH3_REG (DR_REG_DMA_BASE + 0x0C4) +/* DMA_INFIFO_POP_CH3 : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH3 (BIT(12)) +#define DMA_INFIFO_POP_CH3_M (BIT(12)) +#define DMA_INFIFO_POP_CH3_V 0x1 +#define DMA_INFIFO_POP_CH3_S 12 +/* DMA_INFIFO_RDATA_CH3 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH3 0x00000FFF +#define DMA_INFIFO_RDATA_CH3_M ((DMA_INFIFO_RDATA_CH3_V) << (DMA_INFIFO_RDATA_CH3_S)) +#define DMA_INFIFO_RDATA_CH3_V 0xFFF +#define DMA_INFIFO_RDATA_CH3_S 0 + +#define DMA_IN_POP_CH4_REG (DR_REG_DMA_BASE + 0x0C8) +/* DMA_INFIFO_POP_CH4 : R/W ;bitpos:[12] ;default: 1'h0 ; */ +/*description: Set this bit to pop data from DMA FIFO.*/ +#define DMA_INFIFO_POP_CH4 (BIT(12)) +#define DMA_INFIFO_POP_CH4_M (BIT(12)) +#define DMA_INFIFO_POP_CH4_V 0x1 +#define DMA_INFIFO_POP_CH4_S 12 +/* DMA_INFIFO_RDATA_CH4 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: This register stores the data popping from DMA FIFO.*/ +#define DMA_INFIFO_RDATA_CH4 0x00000FFF +#define DMA_INFIFO_RDATA_CH4_M ((DMA_INFIFO_RDATA_CH4_V) << (DMA_INFIFO_RDATA_CH4_S)) +#define DMA_INFIFO_RDATA_CH4_V 0xFFF +#define DMA_INFIFO_RDATA_CH4_S 0 + +#define DMA_OUT_LINK_CH0_REG (DR_REG_DMA_BASE + 0x0CC) +/* DMA_OUTLINK_PARK_CH0 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH0 (BIT(23)) +#define DMA_OUTLINK_PARK_CH0_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH0_V 0x1 +#define DMA_OUTLINK_PARK_CH0_S 23 +/* DMA_OUTLINK_RESTART_CH0 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH0 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH0_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH0_V 0x1 +#define DMA_OUTLINK_RESTART_CH0_S 22 +/* DMA_OUTLINK_START_CH0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH0 (BIT(21)) +#define DMA_OUTLINK_START_CH0_M (BIT(21)) +#define DMA_OUTLINK_START_CH0_V 0x1 +#define DMA_OUTLINK_START_CH0_S 21 +/* DMA_OUTLINK_STOP_CH0 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH0 (BIT(20)) +#define DMA_OUTLINK_STOP_CH0_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH0_V 0x1 +#define DMA_OUTLINK_STOP_CH0_S 20 +/* DMA_OUTLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH0 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH0_M ((DMA_OUTLINK_ADDR_CH0_V) << (DMA_OUTLINK_ADDR_CH0_S)) +#define DMA_OUTLINK_ADDR_CH0_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH0_S 0 + +#define DMA_OUT_LINK_CH1_REG (DR_REG_DMA_BASE + 0x0D0) +/* DMA_OUTLINK_PARK_CH1 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH1 (BIT(23)) +#define DMA_OUTLINK_PARK_CH1_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH1_V 0x1 +#define DMA_OUTLINK_PARK_CH1_S 23 +/* DMA_OUTLINK_RESTART_CH1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH1 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH1_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH1_V 0x1 +#define DMA_OUTLINK_RESTART_CH1_S 22 +/* DMA_OUTLINK_START_CH1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH1 (BIT(21)) +#define DMA_OUTLINK_START_CH1_M (BIT(21)) +#define DMA_OUTLINK_START_CH1_V 0x1 +#define DMA_OUTLINK_START_CH1_S 21 +/* DMA_OUTLINK_STOP_CH1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH1 (BIT(20)) +#define DMA_OUTLINK_STOP_CH1_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH1_V 0x1 +#define DMA_OUTLINK_STOP_CH1_S 20 +/* DMA_OUTLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH1 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH1_M ((DMA_OUTLINK_ADDR_CH1_V) << (DMA_OUTLINK_ADDR_CH1_S)) +#define DMA_OUTLINK_ADDR_CH1_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH1_S 0 + +#define DMA_OUT_LINK_CH2_REG (DR_REG_DMA_BASE + 0x0D4) +/* DMA_OUTLINK_PARK_CH2 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH2 (BIT(23)) +#define DMA_OUTLINK_PARK_CH2_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH2_V 0x1 +#define DMA_OUTLINK_PARK_CH2_S 23 +/* DMA_OUTLINK_RESTART_CH2 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH2 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH2_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH2_V 0x1 +#define DMA_OUTLINK_RESTART_CH2_S 22 +/* DMA_OUTLINK_START_CH2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH2 (BIT(21)) +#define DMA_OUTLINK_START_CH2_M (BIT(21)) +#define DMA_OUTLINK_START_CH2_V 0x1 +#define DMA_OUTLINK_START_CH2_S 21 +/* DMA_OUTLINK_STOP_CH2 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH2 (BIT(20)) +#define DMA_OUTLINK_STOP_CH2_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH2_V 0x1 +#define DMA_OUTLINK_STOP_CH2_S 20 +/* DMA_OUTLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH2 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH2_M ((DMA_OUTLINK_ADDR_CH2_V) << (DMA_OUTLINK_ADDR_CH2_S)) +#define DMA_OUTLINK_ADDR_CH2_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH2_S 0 + +#define DMA_OUT_LINK_CH3_REG (DR_REG_DMA_BASE + 0x0D8) +/* DMA_OUTLINK_PARK_CH3 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH3 (BIT(23)) +#define DMA_OUTLINK_PARK_CH3_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH3_V 0x1 +#define DMA_OUTLINK_PARK_CH3_S 23 +/* DMA_OUTLINK_RESTART_CH3 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH3 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH3_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH3_V 0x1 +#define DMA_OUTLINK_RESTART_CH3_S 22 +/* DMA_OUTLINK_START_CH3 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH3 (BIT(21)) +#define DMA_OUTLINK_START_CH3_M (BIT(21)) +#define DMA_OUTLINK_START_CH3_V 0x1 +#define DMA_OUTLINK_START_CH3_S 21 +/* DMA_OUTLINK_STOP_CH3 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH3 (BIT(20)) +#define DMA_OUTLINK_STOP_CH3_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH3_V 0x1 +#define DMA_OUTLINK_STOP_CH3_S 20 +/* DMA_OUTLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH3 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH3_M ((DMA_OUTLINK_ADDR_CH3_V) << (DMA_OUTLINK_ADDR_CH3_S)) +#define DMA_OUTLINK_ADDR_CH3_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH3_S 0 + +#define DMA_OUT_LINK_CH4_REG (DR_REG_DMA_BASE + 0x0DC) +/* DMA_OUTLINK_PARK_CH4 : RO ;bitpos:[23] ;default: 1'h1 ; */ +/*description: 1: the outlink descriptor's FSM is in idle state. 0: the outlink + descriptor's FSM is working.*/ +#define DMA_OUTLINK_PARK_CH4 (BIT(23)) +#define DMA_OUTLINK_PARK_CH4_M (BIT(23)) +#define DMA_OUTLINK_PARK_CH4_V 0x1 +#define DMA_OUTLINK_PARK_CH4_S 23 +/* DMA_OUTLINK_RESTART_CH4 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to restart a new outlink from the last address.*/ +#define DMA_OUTLINK_RESTART_CH4 (BIT(22)) +#define DMA_OUTLINK_RESTART_CH4_M (BIT(22)) +#define DMA_OUTLINK_RESTART_CH4_V 0x1 +#define DMA_OUTLINK_RESTART_CH4_S 22 +/* DMA_OUTLINK_START_CH4 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_START_CH4 (BIT(21)) +#define DMA_OUTLINK_START_CH4_M (BIT(21)) +#define DMA_OUTLINK_START_CH4_V 0x1 +#define DMA_OUTLINK_START_CH4_S 21 +/* DMA_OUTLINK_STOP_CH4 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the outlink descriptors.*/ +#define DMA_OUTLINK_STOP_CH4 (BIT(20)) +#define DMA_OUTLINK_STOP_CH4_M (BIT(20)) +#define DMA_OUTLINK_STOP_CH4_V 0x1 +#define DMA_OUTLINK_STOP_CH4_S 20 +/* DMA_OUTLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + outlink descriptor's address.*/ +#define DMA_OUTLINK_ADDR_CH4 0x000FFFFF +#define DMA_OUTLINK_ADDR_CH4_M ((DMA_OUTLINK_ADDR_CH4_V) << (DMA_OUTLINK_ADDR_CH4_S)) +#define DMA_OUTLINK_ADDR_CH4_V 0xFFFFF +#define DMA_OUTLINK_ADDR_CH4_S 0 + +#define DMA_IN_LINK_CH0_REG (DR_REG_DMA_BASE + 0x0E0) +/* DMA_INLINK_PARK_CH0 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH0 (BIT(24)) +#define DMA_INLINK_PARK_CH0_M (BIT(24)) +#define DMA_INLINK_PARK_CH0_V 0x1 +#define DMA_INLINK_PARK_CH0_S 24 +/* DMA_INLINK_RESTART_CH0 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH0 (BIT(23)) +#define DMA_INLINK_RESTART_CH0_M (BIT(23)) +#define DMA_INLINK_RESTART_CH0_V 0x1 +#define DMA_INLINK_RESTART_CH0_S 23 +/* DMA_INLINK_START_CH0 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH0 (BIT(22)) +#define DMA_INLINK_START_CH0_M (BIT(22)) +#define DMA_INLINK_START_CH0_V 0x1 +#define DMA_INLINK_START_CH0_S 22 +/* DMA_INLINK_STOP_CH0 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH0 (BIT(21)) +#define DMA_INLINK_STOP_CH0_M (BIT(21)) +#define DMA_INLINK_STOP_CH0_V 0x1 +#define DMA_INLINK_STOP_CH0_S 21 +/* DMA_INLINK_AUTO_RET_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH0 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH0_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH0_V 0x1 +#define DMA_INLINK_AUTO_RET_CH0_S 20 +/* DMA_INLINK_ADDR_CH0 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH0 0x000FFFFF +#define DMA_INLINK_ADDR_CH0_M ((DMA_INLINK_ADDR_CH0_V) << (DMA_INLINK_ADDR_CH0_S)) +#define DMA_INLINK_ADDR_CH0_V 0xFFFFF +#define DMA_INLINK_ADDR_CH0_S 0 + +#define DMA_IN_LINK_CH1_REG (DR_REG_DMA_BASE + 0x0E4) +/* DMA_INLINK_PARK_CH1 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH1 (BIT(24)) +#define DMA_INLINK_PARK_CH1_M (BIT(24)) +#define DMA_INLINK_PARK_CH1_V 0x1 +#define DMA_INLINK_PARK_CH1_S 24 +/* DMA_INLINK_RESTART_CH1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH1 (BIT(23)) +#define DMA_INLINK_RESTART_CH1_M (BIT(23)) +#define DMA_INLINK_RESTART_CH1_V 0x1 +#define DMA_INLINK_RESTART_CH1_S 23 +/* DMA_INLINK_START_CH1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH1 (BIT(22)) +#define DMA_INLINK_START_CH1_M (BIT(22)) +#define DMA_INLINK_START_CH1_V 0x1 +#define DMA_INLINK_START_CH1_S 22 +/* DMA_INLINK_STOP_CH1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH1 (BIT(21)) +#define DMA_INLINK_STOP_CH1_M (BIT(21)) +#define DMA_INLINK_STOP_CH1_V 0x1 +#define DMA_INLINK_STOP_CH1_S 21 +/* DMA_INLINK_AUTO_RET_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH1 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH1_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH1_V 0x1 +#define DMA_INLINK_AUTO_RET_CH1_S 20 +/* DMA_INLINK_ADDR_CH1 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH1 0x000FFFFF +#define DMA_INLINK_ADDR_CH1_M ((DMA_INLINK_ADDR_CH1_V) << (DMA_INLINK_ADDR_CH1_S)) +#define DMA_INLINK_ADDR_CH1_V 0xFFFFF +#define DMA_INLINK_ADDR_CH1_S 0 + +#define DMA_IN_LINK_CH2_REG (DR_REG_DMA_BASE + 0x0E8) +/* DMA_INLINK_PARK_CH2 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH2 (BIT(24)) +#define DMA_INLINK_PARK_CH2_M (BIT(24)) +#define DMA_INLINK_PARK_CH2_V 0x1 +#define DMA_INLINK_PARK_CH2_S 24 +/* DMA_INLINK_RESTART_CH2 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH2 (BIT(23)) +#define DMA_INLINK_RESTART_CH2_M (BIT(23)) +#define DMA_INLINK_RESTART_CH2_V 0x1 +#define DMA_INLINK_RESTART_CH2_S 23 +/* DMA_INLINK_START_CH2 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH2 (BIT(22)) +#define DMA_INLINK_START_CH2_M (BIT(22)) +#define DMA_INLINK_START_CH2_V 0x1 +#define DMA_INLINK_START_CH2_S 22 +/* DMA_INLINK_STOP_CH2 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH2 (BIT(21)) +#define DMA_INLINK_STOP_CH2_M (BIT(21)) +#define DMA_INLINK_STOP_CH2_V 0x1 +#define DMA_INLINK_STOP_CH2_S 21 +/* DMA_INLINK_AUTO_RET_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH2 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH2_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH2_V 0x1 +#define DMA_INLINK_AUTO_RET_CH2_S 20 +/* DMA_INLINK_ADDR_CH2 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH2 0x000FFFFF +#define DMA_INLINK_ADDR_CH2_M ((DMA_INLINK_ADDR_CH2_V) << (DMA_INLINK_ADDR_CH2_S)) +#define DMA_INLINK_ADDR_CH2_V 0xFFFFF +#define DMA_INLINK_ADDR_CH2_S 0 + +#define DMA_IN_LINK_CH3_REG (DR_REG_DMA_BASE + 0x0EC) +/* DMA_INLINK_PARK_CH3 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH3 (BIT(24)) +#define DMA_INLINK_PARK_CH3_M (BIT(24)) +#define DMA_INLINK_PARK_CH3_V 0x1 +#define DMA_INLINK_PARK_CH3_S 24 +/* DMA_INLINK_RESTART_CH3 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH3 (BIT(23)) +#define DMA_INLINK_RESTART_CH3_M (BIT(23)) +#define DMA_INLINK_RESTART_CH3_V 0x1 +#define DMA_INLINK_RESTART_CH3_S 23 +/* DMA_INLINK_START_CH3 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH3 (BIT(22)) +#define DMA_INLINK_START_CH3_M (BIT(22)) +#define DMA_INLINK_START_CH3_V 0x1 +#define DMA_INLINK_START_CH3_S 22 +/* DMA_INLINK_STOP_CH3 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH3 (BIT(21)) +#define DMA_INLINK_STOP_CH3_M (BIT(21)) +#define DMA_INLINK_STOP_CH3_V 0x1 +#define DMA_INLINK_STOP_CH3_S 21 +/* DMA_INLINK_AUTO_RET_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH3 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH3_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH3_V 0x1 +#define DMA_INLINK_AUTO_RET_CH3_S 20 +/* DMA_INLINK_ADDR_CH3 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH3 0x000FFFFF +#define DMA_INLINK_ADDR_CH3_M ((DMA_INLINK_ADDR_CH3_V) << (DMA_INLINK_ADDR_CH3_S)) +#define DMA_INLINK_ADDR_CH3_V 0xFFFFF +#define DMA_INLINK_ADDR_CH3_S 0 + +#define DMA_IN_LINK_CH4_REG (DR_REG_DMA_BASE + 0x0F0) +/* DMA_INLINK_PARK_CH4 : RO ;bitpos:[24] ;default: 1'h1 ; */ +/*description: 1: the inlink descriptor's FSM is in idle state. 0: the inlink + descriptor's FSM is working.*/ +#define DMA_INLINK_PARK_CH4 (BIT(24)) +#define DMA_INLINK_PARK_CH4_M (BIT(24)) +#define DMA_INLINK_PARK_CH4_V 0x1 +#define DMA_INLINK_PARK_CH4_S 24 +/* DMA_INLINK_RESTART_CH4 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to mount a new inlink descriptor.*/ +#define DMA_INLINK_RESTART_CH4 (BIT(23)) +#define DMA_INLINK_RESTART_CH4_M (BIT(23)) +#define DMA_INLINK_RESTART_CH4_V 0x1 +#define DMA_INLINK_RESTART_CH4_S 23 +/* DMA_INLINK_START_CH4 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: Set this bit to start dealing with the inlink descriptors.*/ +#define DMA_INLINK_START_CH4 (BIT(22)) +#define DMA_INLINK_START_CH4_M (BIT(22)) +#define DMA_INLINK_START_CH4_V 0x1 +#define DMA_INLINK_START_CH4_S 22 +/* DMA_INLINK_STOP_CH4 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: Set this bit to stop dealing with the inlink descriptors.*/ +#define DMA_INLINK_STOP_CH4 (BIT(21)) +#define DMA_INLINK_STOP_CH4_M (BIT(21)) +#define DMA_INLINK_STOP_CH4_V 0x1 +#define DMA_INLINK_STOP_CH4_S 21 +/* DMA_INLINK_AUTO_RET_CH4 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: Set this bit to return to current inlink descriptor's address + when there are some errors in current receiving data.*/ +#define DMA_INLINK_AUTO_RET_CH4 (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH4_M (BIT(20)) +#define DMA_INLINK_AUTO_RET_CH4_V 0x1 +#define DMA_INLINK_AUTO_RET_CH4_S 20 +/* DMA_INLINK_ADDR_CH4 : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: This register stores the 20 least significant bits of the first + inlink descriptor's address.*/ +#define DMA_INLINK_ADDR_CH4 0x000FFFFF +#define DMA_INLINK_ADDR_CH4_M ((DMA_INLINK_ADDR_CH4_V) << (DMA_INLINK_ADDR_CH4_S)) +#define DMA_INLINK_ADDR_CH4_V 0xFFFFF +#define DMA_INLINK_ADDR_CH4_S 0 + +#define DMA_IN_STATE_CH0_REG (DR_REG_DMA_BASE + 0x0F4) +/* DMA_IN_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH0 0x00000007 +#define DMA_IN_STATE_CH0_M ((DMA_IN_STATE_CH0_V) << (DMA_IN_STATE_CH0_S)) +#define DMA_IN_STATE_CH0_V 0x7 +#define DMA_IN_STATE_CH0_S 20 +/* DMA_IN_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH0 0x00000003 +#define DMA_IN_DSCR_STATE_CH0_M ((DMA_IN_DSCR_STATE_CH0_V) << (DMA_IN_DSCR_STATE_CH0_S)) +#define DMA_IN_DSCR_STATE_CH0_V 0x3 +#define DMA_IN_DSCR_STATE_CH0_S 18 +/* DMA_INLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_M ((DMA_INLINK_DSCR_ADDR_CH0_V) << (DMA_INLINK_DSCR_ADDR_CH0_S)) +#define DMA_INLINK_DSCR_ADDR_CH0_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH0_S 0 + +#define DMA_IN_STATE_CH1_REG (DR_REG_DMA_BASE + 0x0F8) +/* DMA_IN_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH1 0x00000007 +#define DMA_IN_STATE_CH1_M ((DMA_IN_STATE_CH1_V) << (DMA_IN_STATE_CH1_S)) +#define DMA_IN_STATE_CH1_V 0x7 +#define DMA_IN_STATE_CH1_S 20 +/* DMA_IN_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH1 0x00000003 +#define DMA_IN_DSCR_STATE_CH1_M ((DMA_IN_DSCR_STATE_CH1_V) << (DMA_IN_DSCR_STATE_CH1_S)) +#define DMA_IN_DSCR_STATE_CH1_V 0x3 +#define DMA_IN_DSCR_STATE_CH1_S 18 +/* DMA_INLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_M ((DMA_INLINK_DSCR_ADDR_CH1_V) << (DMA_INLINK_DSCR_ADDR_CH1_S)) +#define DMA_INLINK_DSCR_ADDR_CH1_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH1_S 0 + +#define DMA_IN_STATE_CH2_REG (DR_REG_DMA_BASE + 0x0FC) +/* DMA_IN_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH2 0x00000007 +#define DMA_IN_STATE_CH2_M ((DMA_IN_STATE_CH2_V) << (DMA_IN_STATE_CH2_S)) +#define DMA_IN_STATE_CH2_V 0x7 +#define DMA_IN_STATE_CH2_S 20 +/* DMA_IN_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH2 0x00000003 +#define DMA_IN_DSCR_STATE_CH2_M ((DMA_IN_DSCR_STATE_CH2_V) << (DMA_IN_DSCR_STATE_CH2_S)) +#define DMA_IN_DSCR_STATE_CH2_V 0x3 +#define DMA_IN_DSCR_STATE_CH2_S 18 +/* DMA_INLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_M ((DMA_INLINK_DSCR_ADDR_CH2_V) << (DMA_INLINK_DSCR_ADDR_CH2_S)) +#define DMA_INLINK_DSCR_ADDR_CH2_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH2_S 0 + +#define DMA_IN_STATE_CH3_REG (DR_REG_DMA_BASE + 0x100) +/* DMA_IN_STATE_CH3 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH3 0x00000007 +#define DMA_IN_STATE_CH3_M ((DMA_IN_STATE_CH3_V) << (DMA_IN_STATE_CH3_S)) +#define DMA_IN_STATE_CH3_V 0x7 +#define DMA_IN_STATE_CH3_S 20 +/* DMA_IN_DSCR_STATE_CH3 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH3 0x00000003 +#define DMA_IN_DSCR_STATE_CH3_M ((DMA_IN_DSCR_STATE_CH3_V) << (DMA_IN_DSCR_STATE_CH3_S)) +#define DMA_IN_DSCR_STATE_CH3_V 0x3 +#define DMA_IN_DSCR_STATE_CH3_S 18 +/* DMA_INLINK_DSCR_ADDR_CH3 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH3 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH3_M ((DMA_INLINK_DSCR_ADDR_CH3_V) << (DMA_INLINK_DSCR_ADDR_CH3_S)) +#define DMA_INLINK_DSCR_ADDR_CH3_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH3_S 0 + +#define DMA_IN_STATE_CH4_REG (DR_REG_DMA_BASE + 0x104) +/* DMA_IN_STATE_CH4 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_IN_STATE_CH4 0x00000007 +#define DMA_IN_STATE_CH4_M ((DMA_IN_STATE_CH4_V) << (DMA_IN_STATE_CH4_S)) +#define DMA_IN_STATE_CH4_V 0x7 +#define DMA_IN_STATE_CH4_S 20 +/* DMA_IN_DSCR_STATE_CH4 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_IN_DSCR_STATE_CH4 0x00000003 +#define DMA_IN_DSCR_STATE_CH4_M ((DMA_IN_DSCR_STATE_CH4_V) << (DMA_IN_DSCR_STATE_CH4_S)) +#define DMA_IN_DSCR_STATE_CH4_V 0x3 +#define DMA_IN_DSCR_STATE_CH4_S 18 +/* DMA_INLINK_DSCR_ADDR_CH4 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current inlink descriptor's address.*/ +#define DMA_INLINK_DSCR_ADDR_CH4 0x0003FFFF +#define DMA_INLINK_DSCR_ADDR_CH4_M ((DMA_INLINK_DSCR_ADDR_CH4_V) << (DMA_INLINK_DSCR_ADDR_CH4_S)) +#define DMA_INLINK_DSCR_ADDR_CH4_V 0x3FFFF +#define DMA_INLINK_DSCR_ADDR_CH4_S 0 + +#define DMA_OUT_STATE_CH0_REG (DR_REG_DMA_BASE + 0x108) +/* DMA_OUT_STATE_CH0 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH0 0x00000007 +#define DMA_OUT_STATE_CH0_M ((DMA_OUT_STATE_CH0_V) << (DMA_OUT_STATE_CH0_S)) +#define DMA_OUT_STATE_CH0_V 0x7 +#define DMA_OUT_STATE_CH0_S 20 +/* DMA_OUT_DSCR_STATE_CH0 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH0 0x00000003 +#define DMA_OUT_DSCR_STATE_CH0_M ((DMA_OUT_DSCR_STATE_CH0_V) << (DMA_OUT_DSCR_STATE_CH0_S)) +#define DMA_OUT_DSCR_STATE_CH0_V 0x3 +#define DMA_OUT_DSCR_STATE_CH0_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH0 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH0 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_M ((DMA_OUTLINK_DSCR_ADDR_CH0_V) << (DMA_OUTLINK_DSCR_ADDR_CH0_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH0_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH0_S 0 + +#define DMA_OUT_STATE_CH1_REG (DR_REG_DMA_BASE + 0x10C) +/* DMA_OUT_STATE_CH1 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH1 0x00000007 +#define DMA_OUT_STATE_CH1_M ((DMA_OUT_STATE_CH1_V) << (DMA_OUT_STATE_CH1_S)) +#define DMA_OUT_STATE_CH1_V 0x7 +#define DMA_OUT_STATE_CH1_S 20 +/* DMA_OUT_DSCR_STATE_CH1 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH1 0x00000003 +#define DMA_OUT_DSCR_STATE_CH1_M ((DMA_OUT_DSCR_STATE_CH1_V) << (DMA_OUT_DSCR_STATE_CH1_S)) +#define DMA_OUT_DSCR_STATE_CH1_V 0x3 +#define DMA_OUT_DSCR_STATE_CH1_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH1 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH1 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_M ((DMA_OUTLINK_DSCR_ADDR_CH1_V) << (DMA_OUTLINK_DSCR_ADDR_CH1_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH1_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH1_S 0 + +#define DMA_OUT_STATE_CH2_REG (DR_REG_DMA_BASE + 0x110) +/* DMA_OUT_STATE_CH2 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH2 0x00000007 +#define DMA_OUT_STATE_CH2_M ((DMA_OUT_STATE_CH2_V) << (DMA_OUT_STATE_CH2_S)) +#define DMA_OUT_STATE_CH2_V 0x7 +#define DMA_OUT_STATE_CH2_S 20 +/* DMA_OUT_DSCR_STATE_CH2 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH2 0x00000003 +#define DMA_OUT_DSCR_STATE_CH2_M ((DMA_OUT_DSCR_STATE_CH2_V) << (DMA_OUT_DSCR_STATE_CH2_S)) +#define DMA_OUT_DSCR_STATE_CH2_V 0x3 +#define DMA_OUT_DSCR_STATE_CH2_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH2 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH2 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_M ((DMA_OUTLINK_DSCR_ADDR_CH2_V) << (DMA_OUTLINK_DSCR_ADDR_CH2_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH2_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH2_S 0 + +#define DMA_OUT_STATE_CH3_REG (DR_REG_DMA_BASE + 0x114) +/* DMA_OUT_STATE_CH3 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH3 0x00000007 +#define DMA_OUT_STATE_CH3_M ((DMA_OUT_STATE_CH3_V) << (DMA_OUT_STATE_CH3_S)) +#define DMA_OUT_STATE_CH3_V 0x7 +#define DMA_OUT_STATE_CH3_S 20 +/* DMA_OUT_DSCR_STATE_CH3 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH3 0x00000003 +#define DMA_OUT_DSCR_STATE_CH3_M ((DMA_OUT_DSCR_STATE_CH3_V) << (DMA_OUT_DSCR_STATE_CH3_S)) +#define DMA_OUT_DSCR_STATE_CH3_V 0x3 +#define DMA_OUT_DSCR_STATE_CH3_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH3 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH3 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH3_M ((DMA_OUTLINK_DSCR_ADDR_CH3_V) << (DMA_OUTLINK_DSCR_ADDR_CH3_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH3_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH3_S 0 + +#define DMA_OUT_STATE_CH4_REG (DR_REG_DMA_BASE + 0x118) +/* DMA_OUT_STATE_CH4 : RO ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_STATE_CH4 0x00000007 +#define DMA_OUT_STATE_CH4_M ((DMA_OUT_STATE_CH4_V) << (DMA_OUT_STATE_CH4_S)) +#define DMA_OUT_STATE_CH4_V 0x7 +#define DMA_OUT_STATE_CH4_S 20 +/* DMA_OUT_DSCR_STATE_CH4 : RO ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_OUT_DSCR_STATE_CH4 0x00000003 +#define DMA_OUT_DSCR_STATE_CH4_M ((DMA_OUT_DSCR_STATE_CH4_V) << (DMA_OUT_DSCR_STATE_CH4_S)) +#define DMA_OUT_DSCR_STATE_CH4_V 0x3 +#define DMA_OUT_DSCR_STATE_CH4_S 18 +/* DMA_OUTLINK_DSCR_ADDR_CH4 : RO ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: This register stores the current outlink descriptor's address.*/ +#define DMA_OUTLINK_DSCR_ADDR_CH4 0x0003FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH4_M ((DMA_OUTLINK_DSCR_ADDR_CH4_V) << (DMA_OUTLINK_DSCR_ADDR_CH4_S)) +#define DMA_OUTLINK_DSCR_ADDR_CH4_V 0x3FFFF +#define DMA_OUTLINK_DSCR_ADDR_CH4_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH0_REG (DR_REG_DMA_BASE + 0x11C) +/* DMA_OUT_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_M ((DMA_OUT_EOF_DES_ADDR_CH0_V) << (DMA_OUT_EOF_DES_ADDR_CH0_S)) +#define DMA_OUT_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH0_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH1_REG (DR_REG_DMA_BASE + 0x120) +/* DMA_OUT_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_M ((DMA_OUT_EOF_DES_ADDR_CH1_V) << (DMA_OUT_EOF_DES_ADDR_CH1_S)) +#define DMA_OUT_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH1_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH2_REG (DR_REG_DMA_BASE + 0x124) +/* DMA_OUT_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_M ((DMA_OUT_EOF_DES_ADDR_CH2_V) << (DMA_OUT_EOF_DES_ADDR_CH2_S)) +#define DMA_OUT_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH2_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH3_REG (DR_REG_DMA_BASE + 0x128) +/* DMA_OUT_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH3 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH3_M ((DMA_OUT_EOF_DES_ADDR_CH3_V) << (DMA_OUT_EOF_DES_ADDR_CH3_S)) +#define DMA_OUT_EOF_DES_ADDR_CH3_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH3_S 0 + +#define DMA_OUT_EOF_DES_ADDR_CH4_REG (DR_REG_DMA_BASE + 0x12C) +/* DMA_OUT_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_OUT_EOF_DES_ADDR_CH4 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH4_M ((DMA_OUT_EOF_DES_ADDR_CH4_V) << (DMA_OUT_EOF_DES_ADDR_CH4_S)) +#define DMA_OUT_EOF_DES_ADDR_CH4_V 0xFFFFFFFF +#define DMA_OUT_EOF_DES_ADDR_CH4_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_REG (DR_REG_DMA_BASE + 0x130) +/* DMA_IN_SUC_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_M ((DMA_IN_SUC_EOF_DES_ADDR_CH0_V) << (DMA_IN_SUC_EOF_DES_ADDR_CH0_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH0_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_REG (DR_REG_DMA_BASE + 0x134) +/* DMA_IN_SUC_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_M ((DMA_IN_SUC_EOF_DES_ADDR_CH1_V) << (DMA_IN_SUC_EOF_DES_ADDR_CH1_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH1_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_REG (DR_REG_DMA_BASE + 0x138) +/* DMA_IN_SUC_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_M ((DMA_IN_SUC_EOF_DES_ADDR_CH2_V) << (DMA_IN_SUC_EOF_DES_ADDR_CH2_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH2_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH3_REG (DR_REG_DMA_BASE + 0x13C) +/* DMA_IN_SUC_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH3 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH3_M ((DMA_IN_SUC_EOF_DES_ADDR_CH3_V) << (DMA_IN_SUC_EOF_DES_ADDR_CH3_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH3_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH3_S 0 + +#define DMA_IN_SUC_EOF_DES_ADDR_CH4_REG (DR_REG_DMA_BASE + 0x140) +/* DMA_IN_SUC_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + the EOF bit in this descriptor is 1.*/ +#define DMA_IN_SUC_EOF_DES_ADDR_CH4 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH4_M ((DMA_IN_SUC_EOF_DES_ADDR_CH4_V) << (DMA_IN_SUC_EOF_DES_ADDR_CH4_S)) +#define DMA_IN_SUC_EOF_DES_ADDR_CH4_V 0xFFFFFFFF +#define DMA_IN_SUC_EOF_DES_ADDR_CH4_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_REG (DR_REG_DMA_BASE + 0x144) +/* DMA_IN_ERR_EOF_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_M ((DMA_IN_ERR_EOF_DES_ADDR_CH0_V) << (DMA_IN_ERR_EOF_DES_ADDR_CH0_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH0_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_REG (DR_REG_DMA_BASE + 0x148) +/* DMA_IN_ERR_EOF_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_M ((DMA_IN_ERR_EOF_DES_ADDR_CH1_V) << (DMA_IN_ERR_EOF_DES_ADDR_CH1_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH1_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_REG (DR_REG_DMA_BASE + 0x14C) +/* DMA_IN_ERR_EOF_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_M ((DMA_IN_ERR_EOF_DES_ADDR_CH2_V) << (DMA_IN_ERR_EOF_DES_ADDR_CH2_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH2_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH3_REG (DR_REG_DMA_BASE + 0x150) +/* DMA_IN_ERR_EOF_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH3 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH3_M ((DMA_IN_ERR_EOF_DES_ADDR_CH3_V) << (DMA_IN_ERR_EOF_DES_ADDR_CH3_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH3_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH3_S 0 + +#define DMA_IN_ERR_EOF_DES_ADDR_CH4_REG (DR_REG_DMA_BASE + 0x154) +/* DMA_IN_ERR_EOF_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the inlink descriptor when + there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ +#define DMA_IN_ERR_EOF_DES_ADDR_CH4 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH4_M ((DMA_IN_ERR_EOF_DES_ADDR_CH4_V) << (DMA_IN_ERR_EOF_DES_ADDR_CH4_S)) +#define DMA_IN_ERR_EOF_DES_ADDR_CH4_V 0xFFFFFFFF +#define DMA_IN_ERR_EOF_DES_ADDR_CH4_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG (DR_REG_DMA_BASE + 0x158) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH0_V) << (DMA_OUT_EOF_BFR_DES_ADDR_CH0_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH0_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG (DR_REG_DMA_BASE + 0x15C) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH1_V) << (DMA_OUT_EOF_BFR_DES_ADDR_CH1_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH1_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG (DR_REG_DMA_BASE + 0x160) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH2_V) << (DMA_OUT_EOF_BFR_DES_ADDR_CH2_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH2_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH3_REG (DR_REG_DMA_BASE + 0x164) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH3 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH3 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH3_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH3_V) << (DMA_OUT_EOF_BFR_DES_ADDR_CH3_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH3_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH3_S 0 + +#define DMA_OUT_EOF_BFR_DES_ADDR_CH4_REG (DR_REG_DMA_BASE + 0x168) +/* DMA_OUT_EOF_BFR_DES_ADDR_CH4 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: This register stores the address of the outlink descriptor before + the last outlink descriptor.*/ +#define DMA_OUT_EOF_BFR_DES_ADDR_CH4 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH4_M ((DMA_OUT_EOF_BFR_DES_ADDR_CH4_V) << (DMA_OUT_EOF_BFR_DES_ADDR_CH4_S)) +#define DMA_OUT_EOF_BFR_DES_ADDR_CH4_V 0xFFFFFFFF +#define DMA_OUT_EOF_BFR_DES_ADDR_CH4_S 0 + +#define DMA_AHB_TEST_REG (DR_REG_DMA_BASE + 0x16C) +/* DMA_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: reserved*/ +#define DMA_AHB_TESTADDR 0x00000003 +#define DMA_AHB_TESTADDR_M ((DMA_AHB_TESTADDR_V) << (DMA_AHB_TESTADDR_S)) +#define DMA_AHB_TESTADDR_V 0x3 +#define DMA_AHB_TESTADDR_S 4 +/* DMA_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: reserved*/ +#define DMA_AHB_TESTMODE 0x00000007 +#define DMA_AHB_TESTMODE_M ((DMA_AHB_TESTMODE_V) << (DMA_AHB_TESTMODE_S)) +#define DMA_AHB_TESTMODE_V 0x7 +#define DMA_AHB_TESTMODE_S 0 + +#define DMA_IN_DSCR_CH0_REG (DR_REG_DMA_BASE + 0x170) +/* DMA_INLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_M ((DMA_INLINK_DSCR_CH0_V) << (DMA_INLINK_DSCR_CH0_S)) +#define DMA_INLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH0_S 0 + +#define DMA_IN_DSCR_CH1_REG (DR_REG_DMA_BASE + 0x174) +/* DMA_INLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_M ((DMA_INLINK_DSCR_CH1_V) << (DMA_INLINK_DSCR_CH1_S)) +#define DMA_INLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH1_S 0 + +#define DMA_IN_DSCR_CH2_REG (DR_REG_DMA_BASE + 0x178) +/* DMA_INLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_M ((DMA_INLINK_DSCR_CH2_V) << (DMA_INLINK_DSCR_CH2_S)) +#define DMA_INLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH2_S 0 + +#define DMA_IN_DSCR_CH3_REG (DR_REG_DMA_BASE + 0x17C) +/* DMA_INLINK_DSCR_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH3 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH3_M ((DMA_INLINK_DSCR_CH3_V) << (DMA_INLINK_DSCR_CH3_S)) +#define DMA_INLINK_DSCR_CH3_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH3_S 0 + +#define DMA_IN_DSCR_CH4_REG (DR_REG_DMA_BASE + 0x180) +/* DMA_INLINK_DSCR_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current inlink descriptor x.*/ +#define DMA_INLINK_DSCR_CH4 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH4_M ((DMA_INLINK_DSCR_CH4_V) << (DMA_INLINK_DSCR_CH4_S)) +#define DMA_INLINK_DSCR_CH4_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_CH4_S 0 + +#define DMA_IN_DSCR_BF0_CH0_REG (DR_REG_DMA_BASE + 0x184) +/* DMA_INLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_M ((DMA_INLINK_DSCR_BF0_CH0_V) << (DMA_INLINK_DSCR_BF0_CH0_S)) +#define DMA_INLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH0_S 0 + +#define DMA_IN_DSCR_BF0_CH1_REG (DR_REG_DMA_BASE + 0x188) +/* DMA_INLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_M ((DMA_INLINK_DSCR_BF0_CH1_V) << (DMA_INLINK_DSCR_BF0_CH1_S)) +#define DMA_INLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH1_S 0 + +#define DMA_IN_DSCR_BF0_CH2_REG (DR_REG_DMA_BASE + 0x18C) +/* DMA_INLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_M ((DMA_INLINK_DSCR_BF0_CH2_V) << (DMA_INLINK_DSCR_BF0_CH2_S)) +#define DMA_INLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH2_S 0 + +#define DMA_IN_DSCR_BF0_CH3_REG (DR_REG_DMA_BASE + 0x190) +/* DMA_INLINK_DSCR_BF0_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH3 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH3_M ((DMA_INLINK_DSCR_BF0_CH3_V) << (DMA_INLINK_DSCR_BF0_CH3_S)) +#define DMA_INLINK_DSCR_BF0_CH3_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH3_S 0 + +#define DMA_IN_DSCR_BF0_CH4_REG (DR_REG_DMA_BASE + 0x194) +/* DMA_INLINK_DSCR_BF0_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last inlink descriptor x-1.*/ +#define DMA_INLINK_DSCR_BF0_CH4 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH4_M ((DMA_INLINK_DSCR_BF0_CH4_V) << (DMA_INLINK_DSCR_BF0_CH4_S)) +#define DMA_INLINK_DSCR_BF0_CH4_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF0_CH4_S 0 + +#define DMA_IN_DSCR_BF1_CH0_REG (DR_REG_DMA_BASE + 0x198) +/* DMA_INLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_M ((DMA_INLINK_DSCR_BF1_CH0_V) << (DMA_INLINK_DSCR_BF1_CH0_S)) +#define DMA_INLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH0_S 0 + +#define DMA_IN_DSCR_BF1_CH1_REG (DR_REG_DMA_BASE + 0x19C) +/* DMA_INLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_M ((DMA_INLINK_DSCR_BF1_CH1_V) << (DMA_INLINK_DSCR_BF1_CH1_S)) +#define DMA_INLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH1_S 0 + +#define DMA_IN_DSCR_BF1_CH2_REG (DR_REG_DMA_BASE + 0x1A0) +/* DMA_INLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_M ((DMA_INLINK_DSCR_BF1_CH2_V) << (DMA_INLINK_DSCR_BF1_CH2_S)) +#define DMA_INLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH2_S 0 + +#define DMA_IN_DSCR_BF1_CH3_REG (DR_REG_DMA_BASE + 0x1A4) +/* DMA_INLINK_DSCR_BF1_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH3 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH3_M ((DMA_INLINK_DSCR_BF1_CH3_V) << (DMA_INLINK_DSCR_BF1_CH3_S)) +#define DMA_INLINK_DSCR_BF1_CH3_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH3_S 0 + +#define DMA_IN_DSCR_BF1_CH4_REG (DR_REG_DMA_BASE + 0x1A8) +/* DMA_INLINK_DSCR_BF1_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_INLINK_DSCR_BF1_CH4 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH4_M ((DMA_INLINK_DSCR_BF1_CH4_V) << (DMA_INLINK_DSCR_BF1_CH4_S)) +#define DMA_INLINK_DSCR_BF1_CH4_V 0xFFFFFFFF +#define DMA_INLINK_DSCR_BF1_CH4_S 0 + +#define DMA_OUT_DSCR_CH0_REG (DR_REG_DMA_BASE + 0x1AC) +/* DMA_OUTLINK_DSCR_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_M ((DMA_OUTLINK_DSCR_CH0_V) << (DMA_OUTLINK_DSCR_CH0_S)) +#define DMA_OUTLINK_DSCR_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH0_S 0 + +#define DMA_OUT_DSCR_CH1_REG (DR_REG_DMA_BASE + 0x1B0) +/* DMA_OUTLINK_DSCR_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_M ((DMA_OUTLINK_DSCR_CH1_V) << (DMA_OUTLINK_DSCR_CH1_S)) +#define DMA_OUTLINK_DSCR_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH1_S 0 + +#define DMA_OUT_DSCR_CH2_REG (DR_REG_DMA_BASE + 0x1B4) +/* DMA_OUTLINK_DSCR_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_M ((DMA_OUTLINK_DSCR_CH2_V) << (DMA_OUTLINK_DSCR_CH2_S)) +#define DMA_OUTLINK_DSCR_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH2_S 0 + +#define DMA_OUT_DSCR_CH3_REG (DR_REG_DMA_BASE + 0x1B8) +/* DMA_OUTLINK_DSCR_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH3 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH3_M ((DMA_OUTLINK_DSCR_CH3_V) << (DMA_OUTLINK_DSCR_CH3_S)) +#define DMA_OUTLINK_DSCR_CH3_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH3_S 0 + +#define DMA_OUT_DSCR_CH4_REG (DR_REG_DMA_BASE + 0x1BC) +/* DMA_OUTLINK_DSCR_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the current outlink descriptor y.*/ +#define DMA_OUTLINK_DSCR_CH4 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH4_M ((DMA_OUTLINK_DSCR_CH4_V) << (DMA_OUTLINK_DSCR_CH4_S)) +#define DMA_OUTLINK_DSCR_CH4_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_CH4_S 0 + +#define DMA_OUT_DSCR_BF0_CH0_REG (DR_REG_DMA_BASE + 0x1C0) +/* DMA_OUTLINK_DSCR_BF0_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_M ((DMA_OUTLINK_DSCR_BF0_CH0_V) << (DMA_OUTLINK_DSCR_BF0_CH0_S)) +#define DMA_OUTLINK_DSCR_BF0_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH0_S 0 + +#define DMA_OUT_DSCR_BF0_CH1_REG (DR_REG_DMA_BASE + 0x1C4) +/* DMA_OUTLINK_DSCR_BF0_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_M ((DMA_OUTLINK_DSCR_BF0_CH1_V) << (DMA_OUTLINK_DSCR_BF0_CH1_S)) +#define DMA_OUTLINK_DSCR_BF0_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH1_S 0 + +#define DMA_OUT_DSCR_BF0_CH2_REG (DR_REG_DMA_BASE + 0x1C8) +/* DMA_OUTLINK_DSCR_BF0_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_M ((DMA_OUTLINK_DSCR_BF0_CH2_V) << (DMA_OUTLINK_DSCR_BF0_CH2_S)) +#define DMA_OUTLINK_DSCR_BF0_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH2_S 0 + +#define DMA_OUT_DSCR_BF0_CH3_REG (DR_REG_DMA_BASE + 0x1CC) +/* DMA_OUTLINK_DSCR_BF0_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH3 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH3_M ((DMA_OUTLINK_DSCR_BF0_CH3_V) << (DMA_OUTLINK_DSCR_BF0_CH3_S)) +#define DMA_OUTLINK_DSCR_BF0_CH3_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH3_S 0 + +#define DMA_OUT_DSCR_BF0_CH4_REG (DR_REG_DMA_BASE + 0x1D0) +/* DMA_OUTLINK_DSCR_BF0_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the last outlink descriptor y-1.*/ +#define DMA_OUTLINK_DSCR_BF0_CH4 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH4_M ((DMA_OUTLINK_DSCR_BF0_CH4_V) << (DMA_OUTLINK_DSCR_BF0_CH4_S)) +#define DMA_OUTLINK_DSCR_BF0_CH4_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF0_CH4_S 0 + +#define DMA_OUT_DSCR_BF1_CH0_REG (DR_REG_DMA_BASE + 0x1D4) +/* DMA_OUTLINK_DSCR_BF1_CH0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH0 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_M ((DMA_OUTLINK_DSCR_BF1_CH0_V) << (DMA_OUTLINK_DSCR_BF1_CH0_S)) +#define DMA_OUTLINK_DSCR_BF1_CH0_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH0_S 0 + +#define DMA_OUT_DSCR_BF1_CH1_REG (DR_REG_DMA_BASE + 0x1D8) +/* DMA_OUTLINK_DSCR_BF1_CH1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH1 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_M ((DMA_OUTLINK_DSCR_BF1_CH1_V) << (DMA_OUTLINK_DSCR_BF1_CH1_S)) +#define DMA_OUTLINK_DSCR_BF1_CH1_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH1_S 0 + +#define DMA_OUT_DSCR_BF1_CH2_REG (DR_REG_DMA_BASE + 0x1DC) +/* DMA_OUTLINK_DSCR_BF1_CH2 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH2 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_M ((DMA_OUTLINK_DSCR_BF1_CH2_V) << (DMA_OUTLINK_DSCR_BF1_CH2_S)) +#define DMA_OUTLINK_DSCR_BF1_CH2_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH2_S 0 + +#define DMA_OUT_DSCR_BF1_CH3_REG (DR_REG_DMA_BASE + 0x1E0) +/* DMA_OUTLINK_DSCR_BF1_CH3 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH3 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH3_M ((DMA_OUTLINK_DSCR_BF1_CH3_V) << (DMA_OUTLINK_DSCR_BF1_CH3_S)) +#define DMA_OUTLINK_DSCR_BF1_CH3_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH3_S 0 + +#define DMA_OUT_DSCR_BF1_CH4_REG (DR_REG_DMA_BASE + 0x1E4) +/* DMA_OUTLINK_DSCR_BF1_CH4 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The address of the second-to-last inlink descriptor x-2.*/ +#define DMA_OUTLINK_DSCR_BF1_CH4 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH4_M ((DMA_OUTLINK_DSCR_BF1_CH4_V) << (DMA_OUTLINK_DSCR_BF1_CH4_S)) +#define DMA_OUTLINK_DSCR_BF1_CH4_V 0xFFFFFFFF +#define DMA_OUTLINK_DSCR_BF1_CH4_S 0 + +#define DMA_PD_CONF_REG (DR_REG_DMA_BASE + 0x1E8) +/* DMA_RAM_CLK_FO : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Force to open the clock and bypass the gate-clock when accessing + the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/ +#define DMA_RAM_CLK_FO (BIT(6)) +#define DMA_RAM_CLK_FO_M (BIT(6)) +#define DMA_RAM_CLK_FO_V 0x1 +#define DMA_RAM_CLK_FO_S 6 +/* DMA_RAM_FORCE_PU : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define DMA_RAM_FORCE_PU (BIT(5)) +#define DMA_RAM_FORCE_PU_M (BIT(5)) +#define DMA_RAM_FORCE_PU_V 0x1 +#define DMA_RAM_FORCE_PU_S 5 +/* DMA_RAM_FORCE_PD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: power down*/ +#define DMA_RAM_FORCE_PD (BIT(4)) +#define DMA_RAM_FORCE_PD_M (BIT(4)) +#define DMA_RAM_FORCE_PD_V 0x1 +#define DMA_RAM_FORCE_PD_S 4 + +#define DMA_WIGHT_CH0_REG (DR_REG_DMA_BASE + 0x1EC) +/* DMA_RX_WEIGHT_CH0 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ +/*description: The weight of Rx channel 0.*/ +#define DMA_RX_WEIGHT_CH0 0x0000000F +#define DMA_RX_WEIGHT_CH0_M ((DMA_RX_WEIGHT_CH0_V) << (DMA_RX_WEIGHT_CH0_S)) +#define DMA_RX_WEIGHT_CH0_V 0xF +#define DMA_RX_WEIGHT_CH0_S 4 +/* DMA_TX_WEIGHT_CH0 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ +/*description: The weight of Tx channel 0.*/ +#define DMA_TX_WEIGHT_CH0 0x0000000F +#define DMA_TX_WEIGHT_CH0_M ((DMA_TX_WEIGHT_CH0_V) << (DMA_TX_WEIGHT_CH0_S)) +#define DMA_TX_WEIGHT_CH0_V 0xF +#define DMA_TX_WEIGHT_CH0_S 0 + +#define DMA_WIGHT_CH1_REG (DR_REG_DMA_BASE + 0x1F0) +/* DMA_RX_WEIGHT_CH1 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ +/*description: The weight of Rx channel 1.*/ +#define DMA_RX_WEIGHT_CH1 0x0000000F +#define DMA_RX_WEIGHT_CH1_M ((DMA_RX_WEIGHT_CH1_V) << (DMA_RX_WEIGHT_CH1_S)) +#define DMA_RX_WEIGHT_CH1_V 0xF +#define DMA_RX_WEIGHT_CH1_S 4 +/* DMA_TX_WEIGHT_CH1 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ +/*description: The weight of Tx channel 1.*/ +#define DMA_TX_WEIGHT_CH1 0x0000000F +#define DMA_TX_WEIGHT_CH1_M ((DMA_TX_WEIGHT_CH1_V) << (DMA_TX_WEIGHT_CH1_S)) +#define DMA_TX_WEIGHT_CH1_V 0xF +#define DMA_TX_WEIGHT_CH1_S 0 + +#define DMA_WIGHT_CH2_REG (DR_REG_DMA_BASE + 0x1F4) +/* DMA_RX_WEIGHT_CH2 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ +/*description: The weight of Rx channel 2.*/ +#define DMA_RX_WEIGHT_CH2 0x0000000F +#define DMA_RX_WEIGHT_CH2_M ((DMA_RX_WEIGHT_CH2_V) << (DMA_RX_WEIGHT_CH2_S)) +#define DMA_RX_WEIGHT_CH2_V 0xF +#define DMA_RX_WEIGHT_CH2_S 4 +/* DMA_TX_WEIGHT_CH2 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ +/*description: The weight of Tx channel 2.*/ +#define DMA_TX_WEIGHT_CH2 0x0000000F +#define DMA_TX_WEIGHT_CH2_M ((DMA_TX_WEIGHT_CH2_V) << (DMA_TX_WEIGHT_CH2_S)) +#define DMA_TX_WEIGHT_CH2_V 0xF +#define DMA_TX_WEIGHT_CH2_S 0 + +#define DMA_WIGHT_CH3_REG (DR_REG_DMA_BASE + 0x1F8) +/* DMA_RX_WEIGHT_CH3 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ +/*description: The weight of Rx channel 3.*/ +#define DMA_RX_WEIGHT_CH3 0x0000000F +#define DMA_RX_WEIGHT_CH3_M ((DMA_RX_WEIGHT_CH3_V) << (DMA_RX_WEIGHT_CH3_S)) +#define DMA_RX_WEIGHT_CH3_V 0xF +#define DMA_RX_WEIGHT_CH3_S 4 +/* DMA_TX_WEIGHT_CH3 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ +/*description: The weight of Tx channel 3.*/ +#define DMA_TX_WEIGHT_CH3 0x0000000F +#define DMA_TX_WEIGHT_CH3_M ((DMA_TX_WEIGHT_CH3_V) << (DMA_TX_WEIGHT_CH3_S)) +#define DMA_TX_WEIGHT_CH3_V 0xF +#define DMA_TX_WEIGHT_CH3_S 0 + +#define DMA_WIGHT_CH4_REG (DR_REG_DMA_BASE + 0x1FC) +/* DMA_RX_WEIGHT_CH4 : R/W ;bitpos:[7:4] ;default: 4'hF ; */ +/*description: The weight of Rx channel 4.*/ +#define DMA_RX_WEIGHT_CH4 0x0000000F +#define DMA_RX_WEIGHT_CH4_M ((DMA_RX_WEIGHT_CH4_V) << (DMA_RX_WEIGHT_CH4_S)) +#define DMA_RX_WEIGHT_CH4_V 0xF +#define DMA_RX_WEIGHT_CH4_S 4 +/* DMA_TX_WEIGHT_CH4 : R/W ;bitpos:[3:0] ;default: 4'hF ; */ +/*description: The weight of Tx channel 4.*/ +#define DMA_TX_WEIGHT_CH4 0x0000000F +#define DMA_TX_WEIGHT_CH4_M ((DMA_TX_WEIGHT_CH4_V) << (DMA_TX_WEIGHT_CH4_S)) +#define DMA_TX_WEIGHT_CH4_V 0xF +#define DMA_TX_WEIGHT_CH4_S 0 + +#define DMA_PRI_CH0_REG (DR_REG_DMA_BASE + 0x200) +/* DMA_RX_PRI_CH0 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 0. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH0 0x0000000F +#define DMA_RX_PRI_CH0_M ((DMA_RX_PRI_CH0_V) << (DMA_RX_PRI_CH0_S)) +#define DMA_RX_PRI_CH0_V 0xF +#define DMA_RX_PRI_CH0_S 4 +/* DMA_TX_PRI_CH0 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 0. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH0 0x0000000F +#define DMA_TX_PRI_CH0_M ((DMA_TX_PRI_CH0_V) << (DMA_TX_PRI_CH0_S)) +#define DMA_TX_PRI_CH0_V 0xF +#define DMA_TX_PRI_CH0_S 0 + +#define DMA_PRI_CH1_REG (DR_REG_DMA_BASE + 0x204) +/* DMA_RX_PRI_CH1 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 1. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH1 0x0000000F +#define DMA_RX_PRI_CH1_M ((DMA_RX_PRI_CH1_V) << (DMA_RX_PRI_CH1_S)) +#define DMA_RX_PRI_CH1_V 0xF +#define DMA_RX_PRI_CH1_S 4 +/* DMA_TX_PRI_CH1 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 1. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH1 0x0000000F +#define DMA_TX_PRI_CH1_M ((DMA_TX_PRI_CH1_V) << (DMA_TX_PRI_CH1_S)) +#define DMA_TX_PRI_CH1_V 0xF +#define DMA_TX_PRI_CH1_S 0 + +#define DMA_PRI_CH2_REG (DR_REG_DMA_BASE + 0x208) +/* DMA_RX_PRI_CH2 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 2. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH2 0x0000000F +#define DMA_RX_PRI_CH2_M ((DMA_RX_PRI_CH2_V) << (DMA_RX_PRI_CH2_S)) +#define DMA_RX_PRI_CH2_V 0xF +#define DMA_RX_PRI_CH2_S 4 +/* DMA_TX_PRI_CH2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 2. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH2 0x0000000F +#define DMA_TX_PRI_CH2_M ((DMA_TX_PRI_CH2_V) << (DMA_TX_PRI_CH2_S)) +#define DMA_TX_PRI_CH2_V 0xF +#define DMA_TX_PRI_CH2_S 0 + +#define DMA_PRI_CH3_REG (DR_REG_DMA_BASE + 0x20C) +/* DMA_RX_PRI_CH3 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 3. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH3 0x0000000F +#define DMA_RX_PRI_CH3_M ((DMA_RX_PRI_CH3_V) << (DMA_RX_PRI_CH3_S)) +#define DMA_RX_PRI_CH3_V 0xF +#define DMA_RX_PRI_CH3_S 4 +/* DMA_TX_PRI_CH3 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 3. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH3 0x0000000F +#define DMA_TX_PRI_CH3_M ((DMA_TX_PRI_CH3_V) << (DMA_TX_PRI_CH3_S)) +#define DMA_TX_PRI_CH3_V 0xF +#define DMA_TX_PRI_CH3_S 0 + +#define DMA_PRI_CH4_REG (DR_REG_DMA_BASE + 0x210) +/* DMA_RX_PRI_CH4 : R/W ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: The priority of Rx channel 4. The larger of the value the higher + of the priority.*/ +#define DMA_RX_PRI_CH4 0x0000000F +#define DMA_RX_PRI_CH4_M ((DMA_RX_PRI_CH4_V) << (DMA_RX_PRI_CH4_S)) +#define DMA_RX_PRI_CH4_V 0xF +#define DMA_RX_PRI_CH4_S 4 +/* DMA_TX_PRI_CH4 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: The priority of Tx channel 4. The larger of the value the higher + of the priority.*/ +#define DMA_TX_PRI_CH4 0x0000000F +#define DMA_TX_PRI_CH4_M ((DMA_TX_PRI_CH4_V) << (DMA_TX_PRI_CH4_S)) +#define DMA_TX_PRI_CH4_V 0xF +#define DMA_TX_PRI_CH4_S 0 + +#define DMA_MISC_CONF_REG (DR_REG_DMA_BASE + 0x214) +/* DMA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define DMA_CLK_EN (BIT(3)) +#define DMA_CLK_EN_M (BIT(3)) +#define DMA_CLK_EN_V 0x1 +#define DMA_CLK_EN_S 3 +/* DMA_ARB_PRI_DIS : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to disable priority arbitration function.*/ +#define DMA_ARB_PRI_DIS (BIT(2)) +#define DMA_ARB_PRI_DIS_M (BIT(2)) +#define DMA_ARB_PRI_DIS_V 0x1 +#define DMA_ARB_PRI_DIS_S 2 +/* DMA_AHBM_RST_EXTER : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit then clear this bit to reset the external ahb FSM.*/ +#define DMA_AHBM_RST_EXTER (BIT(1)) +#define DMA_AHBM_RST_EXTER_M (BIT(1)) +#define DMA_AHBM_RST_EXTER_V 0x1 +#define DMA_AHBM_RST_EXTER_S 1 +/* DMA_AHBM_RST_INTER : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit then clear this bit to reset the internal ahb FSM.*/ +#define DMA_AHBM_RST_INTER (BIT(0)) +#define DMA_AHBM_RST_INTER_M (BIT(0)) +#define DMA_AHBM_RST_INTER_V 0x1 +#define DMA_AHBM_RST_INTER_S 0 + +#define DMA_PERI_SEL_CH0_REG (DR_REG_DMA_BASE + 0x218) +/* DMA_PERI_OUT_SEL_CH0 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 0. 0:SPI2*/ +#define DMA_PERI_OUT_SEL_CH0 0x0000003F +#define DMA_PERI_OUT_SEL_CH0_M ((DMA_PERI_OUT_SEL_CH0_V) << (DMA_PERI_OUT_SEL_CH0_S)) +#define DMA_PERI_OUT_SEL_CH0_V 0x3F +#define DMA_PERI_OUT_SEL_CH0_S 6 +/* DMA_PERI_IN_SEL_CH0 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 0. 0:SPI2*/ +#define DMA_PERI_IN_SEL_CH0 0x0000003F +#define DMA_PERI_IN_SEL_CH0_M ((DMA_PERI_IN_SEL_CH0_V) << (DMA_PERI_IN_SEL_CH0_S)) +#define DMA_PERI_IN_SEL_CH0_V 0x3F +#define DMA_PERI_IN_SEL_CH0_S 0 + +#define DMA_PERI_SEL_CH1_REG (DR_REG_DMA_BASE + 0x21C) +/* DMA_PERI_OUT_SEL_CH1 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 1. 0:SPI2*/ +#define DMA_PERI_OUT_SEL_CH1 0x0000003F +#define DMA_PERI_OUT_SEL_CH1_M ((DMA_PERI_OUT_SEL_CH1_V) << (DMA_PERI_OUT_SEL_CH1_S)) +#define DMA_PERI_OUT_SEL_CH1_V 0x3F +#define DMA_PERI_OUT_SEL_CH1_S 6 +/* DMA_PERI_IN_SEL_CH1 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 1. 0:SPI2*/ +#define DMA_PERI_IN_SEL_CH1 0x0000003F +#define DMA_PERI_IN_SEL_CH1_M ((DMA_PERI_IN_SEL_CH1_V) << (DMA_PERI_IN_SEL_CH1_S)) +#define DMA_PERI_IN_SEL_CH1_V 0x3F +#define DMA_PERI_IN_SEL_CH1_S 0 + +#define DMA_PERI_SEL_CH2_REG (DR_REG_DMA_BASE + 0x220) +/* DMA_PERI_OUT_SEL_CH2 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 2. 0:SPI2*/ +#define DMA_PERI_OUT_SEL_CH2 0x0000003F +#define DMA_PERI_OUT_SEL_CH2_M ((DMA_PERI_OUT_SEL_CH2_V) << (DMA_PERI_OUT_SEL_CH2_S)) +#define DMA_PERI_OUT_SEL_CH2_V 0x3F +#define DMA_PERI_OUT_SEL_CH2_S 6 +/* DMA_PERI_IN_SEL_CH2 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 2. 0:SPI2*/ +#define DMA_PERI_IN_SEL_CH2 0x0000003F +#define DMA_PERI_IN_SEL_CH2_M ((DMA_PERI_IN_SEL_CH2_V) << (DMA_PERI_IN_SEL_CH2_S)) +#define DMA_PERI_IN_SEL_CH2_V 0x3F +#define DMA_PERI_IN_SEL_CH2_S 0 + +#define DMA_PERI_SEL_CH3_REG (DR_REG_DMA_BASE + 0x224) +/* DMA_PERI_OUT_SEL_CH3 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 3. 0:SPI2*/ +#define DMA_PERI_OUT_SEL_CH3 0x0000003F +#define DMA_PERI_OUT_SEL_CH3_M ((DMA_PERI_OUT_SEL_CH3_V) << (DMA_PERI_OUT_SEL_CH3_S)) +#define DMA_PERI_OUT_SEL_CH3_V 0x3F +#define DMA_PERI_OUT_SEL_CH3_S 6 +/* DMA_PERI_IN_SEL_CH3 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 3. 0:SPI2*/ +#define DMA_PERI_IN_SEL_CH3 0x0000003F +#define DMA_PERI_IN_SEL_CH3_M ((DMA_PERI_IN_SEL_CH3_V) << (DMA_PERI_IN_SEL_CH3_S)) +#define DMA_PERI_IN_SEL_CH3_V 0x3F +#define DMA_PERI_IN_SEL_CH3_S 0 + +#define DMA_PERI_SEL_CH4_REG (DR_REG_DMA_BASE + 0x228) +/* DMA_PERI_OUT_SEL_CH4 : R/W ;bitpos:[11:6] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Tx channel 4. 0:SPI2*/ +#define DMA_PERI_OUT_SEL_CH4 0x0000003F +#define DMA_PERI_OUT_SEL_CH4_M ((DMA_PERI_OUT_SEL_CH4_V) << (DMA_PERI_OUT_SEL_CH4_S)) +#define DMA_PERI_OUT_SEL_CH4_V 0x3F +#define DMA_PERI_OUT_SEL_CH4_S 6 +/* DMA_PERI_IN_SEL_CH4 : R/W ;bitpos:[5:0] ;default: 6'h3F ; */ +/*description: This register is used to select peripheral for Rx channel 4. 0:SPI2*/ +#define DMA_PERI_IN_SEL_CH4 0x0000003F +#define DMA_PERI_IN_SEL_CH4_M ((DMA_PERI_IN_SEL_CH4_V) << (DMA_PERI_IN_SEL_CH4_S)) +#define DMA_PERI_IN_SEL_CH4_V 0x3F +#define DMA_PERI_IN_SEL_CH4_S 0 + +#define DMA_SRAM_SIZE_CH0_REG (DR_REG_DMA_BASE + 0x22C) +/* DMA_OUT_SIZE_CH0 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for + Tx channel 0. 0:16 bytes*/ +#define DMA_OUT_SIZE_CH0 0x0000001F +#define DMA_OUT_SIZE_CH0_M ((DMA_OUT_SIZE_CH0_V) << (DMA_OUT_SIZE_CH0_S)) +#define DMA_OUT_SIZE_CH0_V 0x1F +#define DMA_OUT_SIZE_CH0_S 5 +/* DMA_IN_SIZE_CH0 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Rx FIFO for + Rx channel 0. 0:16 bytes*/ +#define DMA_IN_SIZE_CH0 0x0000001F +#define DMA_IN_SIZE_CH0_M ((DMA_IN_SIZE_CH0_V) << (DMA_IN_SIZE_CH0_S)) +#define DMA_IN_SIZE_CH0_V 0x1F +#define DMA_IN_SIZE_CH0_S 0 + +#define DMA_SRAM_SIZE_CH1_REG (DR_REG_DMA_BASE + 0x230) +/* DMA_OUT_SIZE_CH1 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for + Tx channel 1. 0:16 bytes*/ +#define DMA_OUT_SIZE_CH1 0x0000001F +#define DMA_OUT_SIZE_CH1_M ((DMA_OUT_SIZE_CH1_V) << (DMA_OUT_SIZE_CH1_S)) +#define DMA_OUT_SIZE_CH1_V 0x1F +#define DMA_OUT_SIZE_CH1_S 5 +/* DMA_IN_SIZE_CH1 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Rx FIFO for + Rx channel 1. 0:16 bytes*/ +#define DMA_IN_SIZE_CH1 0x0000001F +#define DMA_IN_SIZE_CH1_M ((DMA_IN_SIZE_CH1_V) << (DMA_IN_SIZE_CH1_S)) +#define DMA_IN_SIZE_CH1_V 0x1F +#define DMA_IN_SIZE_CH1_S 0 + +#define DMA_SRAM_SIZE_CH2_REG (DR_REG_DMA_BASE + 0x234) +/* DMA_OUT_SIZE_CH2 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for + Tx channel 2. 0:16 bytes*/ +#define DMA_OUT_SIZE_CH2 0x0000001F +#define DMA_OUT_SIZE_CH2_M ((DMA_OUT_SIZE_CH2_V) << (DMA_OUT_SIZE_CH2_S)) +#define DMA_OUT_SIZE_CH2_V 0x1F +#define DMA_OUT_SIZE_CH2_S 5 +/* DMA_IN_SIZE_CH2 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Rx FIFO for + Rx channel 2. 0:16 bytes*/ +#define DMA_IN_SIZE_CH2 0x0000001F +#define DMA_IN_SIZE_CH2_M ((DMA_IN_SIZE_CH2_V) << (DMA_IN_SIZE_CH2_S)) +#define DMA_IN_SIZE_CH2_V 0x1F +#define DMA_IN_SIZE_CH2_S 0 + +#define DMA_SRAM_SIZE_CH3_REG (DR_REG_DMA_BASE + 0x238) +/* DMA_OUT_SIZE_CH3 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for + Tx channel 3. 0:16 bytes*/ +#define DMA_OUT_SIZE_CH3 0x0000001F +#define DMA_OUT_SIZE_CH3_M ((DMA_OUT_SIZE_CH3_V) << (DMA_OUT_SIZE_CH3_S)) +#define DMA_OUT_SIZE_CH3_V 0x1F +#define DMA_OUT_SIZE_CH3_S 5 +/* DMA_IN_SIZE_CH3 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Rx FIFO for + Rx channel 3. 0:16 bytes*/ +#define DMA_IN_SIZE_CH3 0x0000001F +#define DMA_IN_SIZE_CH3_M ((DMA_IN_SIZE_CH3_V) << (DMA_IN_SIZE_CH3_S)) +#define DMA_IN_SIZE_CH3_V 0x1F +#define DMA_IN_SIZE_CH3_S 0 + +#define DMA_SRAM_SIZE_CH4_REG (DR_REG_DMA_BASE + 0x23C) +/* DMA_OUT_SIZE_CH4 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Tx FIFO for + Tx channel 4. 0:16 bytes*/ +#define DMA_OUT_SIZE_CH4 0x0000001F +#define DMA_OUT_SIZE_CH4_M ((DMA_OUT_SIZE_CH4_V) << (DMA_OUT_SIZE_CH4_S)) +#define DMA_OUT_SIZE_CH4_V 0x1F +#define DMA_OUT_SIZE_CH4_S 5 +/* DMA_IN_SIZE_CH4 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: This register is used to configure the size of L2 Rx FIFO for + Rx channel 4. 0:16 bytes*/ +#define DMA_IN_SIZE_CH4 0x0000001F +#define DMA_IN_SIZE_CH4_M ((DMA_IN_SIZE_CH4_V) << (DMA_IN_SIZE_CH4_S)) +#define DMA_IN_SIZE_CH4_V 0x1F +#define DMA_IN_SIZE_CH4_S 0 + +#define DMA_DATE_REG (DR_REG_DMA_BASE + 0x240) +/* DMA_DATE : R/W ;bitpos:[31:0] ;default: 32'h2002260 ; */ +/*description: register version.*/ +#define DMA_DATE 0xFFFFFFFF +#define DMA_DATE_M ((DMA_DATE_V) << (DMA_DATE_S)) +#define DMA_DATE_V 0xFFFFFFFF +#define DMA_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/dma_struct.h b/components/soc/soc/esp32s3/include/soc/dma_struct.h new file mode 100644 index 000000000..164a1ed43 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/dma_struct.h @@ -0,0 +1,1365 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t in_rst_ch0: 1; /*This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.*/ + uint32_t out_rst_ch0: 1; /*This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.*/ + uint32_t in_loop_test_ch0: 1; /*reserved*/ + uint32_t out_loop_test_ch0: 1; /*reserved*/ + uint32_t out_auto_wrback_ch0: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode_ch0: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en_ch0: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.*/ + uint32_t indscr_burst_en_ch0: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.*/ + uint32_t out_data_burst_en_ch0: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.*/ + uint32_t in_data_burst_en_ch0: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.*/ + uint32_t mem_trans_en_ch0: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved11: 21; /*reserved*/ + }; + uint32_t val; + } conf0_ch0; + union { + struct { + uint32_t in_rst_ch1: 1; /*This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.*/ + uint32_t out_rst_ch1: 1; /*This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.*/ + uint32_t in_loop_test_ch1: 1; /*reserved*/ + uint32_t out_loop_test_ch1: 1; /*reserved*/ + uint32_t out_auto_wrback_ch1: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode_ch1: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en_ch1: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.*/ + uint32_t indscr_burst_en_ch1: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.*/ + uint32_t out_data_burst_en_ch1: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.*/ + uint32_t in_data_burst_en_ch1: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.*/ + uint32_t mem_trans_en_ch1: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved11: 21; /*reserved*/ + }; + uint32_t val; + } conf0_ch1; + union { + struct { + uint32_t in_rst_ch2: 1; /*This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.*/ + uint32_t out_rst_ch2: 1; /*This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.*/ + uint32_t in_loop_test_ch2: 1; /*reserved*/ + uint32_t out_loop_test_ch2: 1; /*reserved*/ + uint32_t out_auto_wrback_ch2: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode_ch2: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en_ch2: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.*/ + uint32_t indscr_burst_en_ch2: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.*/ + uint32_t out_data_burst_en_ch2: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.*/ + uint32_t in_data_burst_en_ch2: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.*/ + uint32_t mem_trans_en_ch2: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved11: 21; /*reserved*/ + }; + uint32_t val; + } conf0_ch2; + union { + struct { + uint32_t in_rst_ch3: 1; /*This bit is used to reset DMA channel 3 Rx FSM and Rx FIFO pointer.*/ + uint32_t out_rst_ch3: 1; /*This bit is used to reset DMA channel 3 Tx FSM and Tx FIFO pointer.*/ + uint32_t in_loop_test_ch3: 1; /*reserved*/ + uint32_t out_loop_test_ch3: 1; /*reserved*/ + uint32_t out_auto_wrback_ch3: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode_ch3: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 3 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en_ch3: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 3 reading link descriptor when accessing internal SRAM.*/ + uint32_t indscr_burst_en_ch3: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 3 reading link descriptor when accessing internal SRAM.*/ + uint32_t out_data_burst_en_ch3: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 3 transmitting data when accessing internal SRAM.*/ + uint32_t in_data_burst_en_ch3: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 3 receiving data when accessing internal SRAM.*/ + uint32_t mem_trans_en_ch3: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved11: 21; /*reserved*/ + }; + uint32_t val; + } conf0_ch3; + union { + struct { + uint32_t in_rst_ch4: 1; /*This bit is used to reset DMA channel 4 Rx FSM and Rx FIFO pointer.*/ + uint32_t out_rst_ch4: 1; /*This bit is used to reset DMA channel 4 Tx FSM and Tx FIFO pointer.*/ + uint32_t in_loop_test_ch4: 1; /*reserved*/ + uint32_t out_loop_test_ch4: 1; /*reserved*/ + uint32_t out_auto_wrback_ch4: 1; /*Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.*/ + uint32_t out_eof_mode_ch4: 1; /*EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 4 is generated when data need to transmit has been popped from FIFO in DMA*/ + uint32_t outdscr_burst_en_ch4: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 4 reading link descriptor when accessing internal SRAM.*/ + uint32_t indscr_burst_en_ch4: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 4 reading link descriptor when accessing internal SRAM.*/ + uint32_t out_data_burst_en_ch4: 1; /*Set this bit to 1 to enable INCR burst transfer for Tx channel 4 transmitting data when accessing internal SRAM.*/ + uint32_t in_data_burst_en_ch4: 1; /*Set this bit to 1 to enable INCR burst transfer for Rx channel 4 receiving data when accessing internal SRAM.*/ + uint32_t mem_trans_en_ch4: 1; /*Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.*/ + uint32_t reserved11: 21; /*reserved*/ + }; + uint32_t val; + } conf0_ch4; + union { + struct { + uint32_t infifo_full_thrs_ch0: 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 0 received byte number in Rx FIFO is up to the value of the register.*/ + uint32_t check_owner_ch0: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t in_ext_mem_bk_size_ch0: 2; /*Block size of Rx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t out_ext_mem_bk_size_ch0: 2; /*Block size of Tx channel 0 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } conf1_ch0; + union { + struct { + uint32_t infifo_full_thrs_ch1: 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 1 received byte number in Rx FIFO is up to the value of the register.*/ + uint32_t check_owner_ch1: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t in_ext_mem_bk_size_ch1: 2; /*Block size of Rx channel 1 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t out_ext_mem_bk_size_ch1: 2; /*Block size of Tx channel 1 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } conf1_ch1; + union { + struct { + uint32_t infifo_full_thrs_ch2: 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 2 received byte number in Rx FIFO is up to the value of the register.*/ + uint32_t check_owner_ch2: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t in_ext_mem_bk_size_ch2: 2; /*Block size of Rx channel 2 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t out_ext_mem_bk_size_ch2: 2; /*Block size of Tx channel 2 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } conf1_ch2; + union { + struct { + uint32_t infifo_full_thrs_ch3: 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 3 received byte number in Rx FIFO is up to the value of the register.*/ + uint32_t check_owner_ch3: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t in_ext_mem_bk_size_ch3: 2; /*Block size of Rx channel 3 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t out_ext_mem_bk_size_ch3: 2; /*Block size of Tx channel 3 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } conf1_ch3; + union { + struct { + uint32_t infifo_full_thrs_ch4: 12; /*This register is used to generate the INFIFO_FULL_WM_INT interrupt when Rx channel 4 received byte number in Rx FIFO is up to the value of the register.*/ + uint32_t check_owner_ch4: 1; /*Set this bit to enable checking the owner attribute of the link descriptor.*/ + uint32_t in_ext_mem_bk_size_ch4: 2; /*Block size of Rx channel 4 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t out_ext_mem_bk_size_ch4: 2; /*Block size of Tx channel 4 when DMA access external SRAM. 0: 16 bytes 1: 32 bytes 2/3:reserved*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } conf1_ch4; + union { + struct { + uint32_t in_done_ch0: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.*/ + uint32_t in_suc_eof_ch0: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.*/ + uint32_t in_err_eof_ch0: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals this raw interrupt is reserved.*/ + uint32_t out_done_ch0: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.*/ + uint32_t out_eof_ch0: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.*/ + uint32_t in_dscr_err_ch0: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 0.*/ + uint32_t out_dscr_err_ch0: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 0.*/ + uint32_t in_dscr_empty_ch0: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 0.*/ + uint32_t out_total_eof_ch0: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.*/ + uint32_t infifo_full_wm_ch0: 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 0.*/ + uint32_t infifo_ovf_l1_ch0: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.*/ + uint32_t infifo_udf_l1_ch0: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.*/ + uint32_t infifo_ovf_l3_ch0: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is overflow.*/ + uint32_t infifo_udf_l3_ch0: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 0 is underflow.*/ + uint32_t outfifo_ovf_l1_ch0: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.*/ + uint32_t outfifo_udf_l1_ch0: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.*/ + uint32_t outfifo_ovf_l3_ch0: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is overflow.*/ + uint32_t outfifo_udf_l3_ch0: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 0 is underflow.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_raw_ch0; + union { + struct { + uint32_t in_done_ch1: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.*/ + uint32_t in_suc_eof_ch1: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.*/ + uint32_t in_err_eof_ch1: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals this raw interrupt is reserved.*/ + uint32_t out_done_ch1: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.*/ + uint32_t out_eof_ch1: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.*/ + uint32_t in_dscr_err_ch1: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 1.*/ + uint32_t out_dscr_err_ch1: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 1.*/ + uint32_t in_dscr_empty_ch1: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 1.*/ + uint32_t out_total_eof_ch1: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.*/ + uint32_t infifo_full_wm_ch1: 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 1.*/ + uint32_t infifo_ovf_l1_ch1: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.*/ + uint32_t infifo_udf_l1_ch1: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.*/ + uint32_t infifo_ovf_l3_ch1: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 1 is overflow.*/ + uint32_t infifo_udf_l3_ch1: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 1 is underflow.*/ + uint32_t outfifo_ovf_l1_ch1: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.*/ + uint32_t outfifo_udf_l1_ch1: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.*/ + uint32_t outfifo_ovf_l3_ch1: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 1 is overflow.*/ + uint32_t outfifo_udf_l3_ch1: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 1 is underflow.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_raw_ch1; + union { + struct { + uint32_t in_done_ch2: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.*/ + uint32_t in_suc_eof_ch2: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.*/ + uint32_t in_err_eof_ch2: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals this raw interrupt is reserved.*/ + uint32_t out_done_ch2: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.*/ + uint32_t out_eof_ch2: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.*/ + uint32_t in_dscr_err_ch2: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 2.*/ + uint32_t out_dscr_err_ch2: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 2.*/ + uint32_t in_dscr_empty_ch2: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 2.*/ + uint32_t out_total_eof_ch2: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.*/ + uint32_t infifo_full_wm_ch2: 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 2.*/ + uint32_t infifo_ovf_l1_ch2: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.*/ + uint32_t infifo_udf_l1_ch2: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.*/ + uint32_t infifo_ovf_l3_ch2: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 2 is overflow.*/ + uint32_t infifo_udf_l3_ch2: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 2 is underflow.*/ + uint32_t outfifo_ovf_l1_ch2: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.*/ + uint32_t outfifo_udf_l1_ch2: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.*/ + uint32_t outfifo_ovf_l3_ch2: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 2 is overflow.*/ + uint32_t outfifo_udf_l3_ch2: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 2 is underflow.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_raw_ch2; + union { + struct { + uint32_t in_done_ch3: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 3.*/ + uint32_t in_suc_eof_ch3: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 3. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 3.*/ + uint32_t in_err_eof_ch3: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 3. For other peripherals this raw interrupt is reserved.*/ + uint32_t out_done_ch3: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 3.*/ + uint32_t out_eof_ch3: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 3.*/ + uint32_t in_dscr_err_ch3: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 3.*/ + uint32_t out_dscr_err_ch3: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 3.*/ + uint32_t in_dscr_empty_ch3: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 3.*/ + uint32_t out_total_eof_ch3: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 3.*/ + uint32_t infifo_full_wm_ch3: 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 3.*/ + uint32_t infifo_ovf_l1_ch3: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 3 is overflow.*/ + uint32_t infifo_udf_l1_ch3: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 3 is underflow.*/ + uint32_t infifo_ovf_l3_ch3: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 3 is overflow.*/ + uint32_t infifo_udf_l3_ch3: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 3 is underflow.*/ + uint32_t outfifo_ovf_l1_ch3: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 3 is overflow.*/ + uint32_t outfifo_udf_l1_ch3: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 3 is underflow.*/ + uint32_t outfifo_ovf_l3_ch3: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 3 is overflow.*/ + uint32_t outfifo_udf_l3_ch3: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 3 is underflow.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_raw_ch3; + union { + struct { + uint32_t in_done_ch4: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 4.*/ + uint32_t in_suc_eof_ch4: 1; /*The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 4. For UHCI0 the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 4.*/ + uint32_t in_err_eof_ch4: 1; /*The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 4. For other peripherals this raw interrupt is reserved.*/ + uint32_t out_done_ch4: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 4.*/ + uint32_t out_eof_ch4: 1; /*The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 4.*/ + uint32_t in_dscr_err_ch4: 1; /*The raw interrupt bit turns to high level when detecting inlink descriptor error including owner error the second and third word error of inlink descriptor for Rx channel 4.*/ + uint32_t out_dscr_err_ch4: 1; /*The raw interrupt bit turns to high level when detecting outlink descriptor error including owner error the second and third word error of outlink descriptor for Tx channel 4.*/ + uint32_t in_dscr_empty_ch4: 1; /*The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed but there is no more inlink for Rx channel 4.*/ + uint32_t out_total_eof_ch4: 1; /*The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 4.*/ + uint32_t infifo_full_wm_ch4: 1; /*The raw interrupt bit turns to high level when received data byte number is up to threshold configured by REG_DMA_INFIFO_FULL_THRS_CH0 in Rx FIFO of channel 4.*/ + uint32_t infifo_ovf_l1_ch4: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 4 is overflow.*/ + uint32_t infifo_udf_l1_ch4: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Rx channel 4 is underflow.*/ + uint32_t infifo_ovf_l3_ch4: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 4 is overflow.*/ + uint32_t infifo_udf_l3_ch4: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Rx channel 4 is underflow.*/ + uint32_t outfifo_ovf_l1_ch4: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 4 is overflow.*/ + uint32_t outfifo_udf_l1_ch4: 1; /*This raw interrupt bit turns to high level when level 1 fifo of Tx channel 4 is underflow.*/ + uint32_t outfifo_ovf_l3_ch4: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 4 is overflow.*/ + uint32_t outfifo_udf_l3_ch4: 1; /*This raw interrupt bit turns to high level when level 3 fifo of Tx channel 4 is underflow.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_raw_ch4; + uint32_t reserved_3c; + union { + struct { + uint32_t in_done_ch0: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch0: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch0: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch0: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch0: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch0: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch0: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch0: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch0: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch0: 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch0: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch0: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch0: 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch0: 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch0: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch0: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch0: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch0: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_st_ch0; + union { + struct { + uint32_t in_done_ch1: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch1: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch1: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch1: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch1: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch1: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch1: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch1: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch1: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch1: 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch1: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch1: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch1: 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch1: 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch1: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch1: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch1: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch1: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_st_ch1; + union { + struct { + uint32_t in_done_ch2: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch2: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch2: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch2: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch2: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch2: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch2: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch2: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch2: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch2: 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch2: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch2: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch2: 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch2: 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch2: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch2: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch2: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch2: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_st_ch2; + union { + struct { + uint32_t in_done_ch3: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch3: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch3: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch3: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch3: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch3: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch3: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch3: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch3: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch3: 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch3: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch3: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch3: 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch3: 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch3: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch3: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch3: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch3: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_st_ch3; + union { + struct { + uint32_t in_done_ch4: 1; /*The raw interrupt status bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch4: 1; /*The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch4: 1; /*The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch4: 1; /*The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch4: 1; /*The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch4: 1; /*The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch4: 1; /*The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch4: 1; /*The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch4: 1; /*The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch4: 1; /*The raw interrupt status bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch4: 1; /*The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch4: 1; /*The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch4: 1; /*The raw interrupt status bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch4: 1; /*The raw interrupt status bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch4: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch4: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch4: 1; /*The raw interrupt status bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch4: 1; /*The raw interrupt status bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_st_ch4; + union { + struct { + uint32_t in_done_ch0: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch0: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch0: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch0: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch0: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch0: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch0: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch0: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch0: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch0: 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch0: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch0: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch0: 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch0: 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch0: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch0: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch0: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch0: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_ena_ch0; + union { + struct { + uint32_t in_done_ch1: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch1: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch1: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch1: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch1: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch1: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch1: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch1: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch1: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch1: 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch1: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch1: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch1: 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch1: 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch1: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch1: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch1: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch1: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_ena_ch1; + union { + struct { + uint32_t in_done_ch2: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch2: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch2: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch2: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch2: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch2: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch2: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch2: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch2: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch2: 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch2: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch2: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch2: 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch2: 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch2: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch2: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch2: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch2: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_ena_ch2; + union { + struct { + uint32_t in_done_ch3: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch3: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch3: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch3: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch3: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch3: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch3: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch3: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch3: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch3: 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch3: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch3: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch3: 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch3: 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch3: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch3: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch3: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch3: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_ena_ch3; + union { + struct { + uint32_t in_done_ch4: 1; /*The interrupt enable bit for the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch4: 1; /*The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch4: 1; /*The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch4: 1; /*The interrupt enable bit for the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch4: 1; /*The interrupt enable bit for the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch4: 1; /*The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch4: 1; /*The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch4: 1; /*The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch4: 1; /*The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch4: 1; /*The interrupt enable bit for the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch4: 1; /*The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch4: 1; /*The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch4: 1; /*The interrupt enable bit for the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch4: 1; /*The interrupt enable bit for the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch4: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch4: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch4: 1; /*The interrupt enable bit for the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch4: 1; /*The interrupt enable bit for the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_ena_ch4; + union { + struct { + uint32_t in_done_ch0: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch0: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch0: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch0: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch0: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch0: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch0: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch0: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch0: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch0: 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch0: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch0: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch0: 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch0: 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch0: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch0: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch0: 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch0: 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_clr_ch0; + union { + struct { + uint32_t in_done_ch1: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch1: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch1: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch1: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch1: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch1: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch1: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch1: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch1: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch1: 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch1: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch1: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch1: 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch1: 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch1: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch1: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch1: 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch1: 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_clr_ch1; + union { + struct { + uint32_t in_done_ch2: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch2: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch2: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch2: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch2: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch2: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch2: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch2: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch2: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch2: 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch2: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch2: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch2: 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch2: 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch2: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch2: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch2: 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch2: 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_clr_ch2; + union { + struct { + uint32_t in_done_ch3: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch3: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch3: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch3: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch3: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch3: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch3: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch3: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch3: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch3: 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch3: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch3: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch3: 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch3: 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch3: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch3: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch3: 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch3: 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_clr_ch3; + union { + struct { + uint32_t in_done_ch4: 1; /*Set this bit to clear the IN_DONE_CH_INT interrupt.*/ + uint32_t in_suc_eof_ch4: 1; /*Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.*/ + uint32_t in_err_eof_ch4: 1; /*Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.*/ + uint32_t out_done_ch4: 1; /*Set this bit to clear the OUT_DONE_CH_INT interrupt.*/ + uint32_t out_eof_ch4: 1; /*Set this bit to clear the OUT_EOF_CH_INT interrupt.*/ + uint32_t in_dscr_err_ch4: 1; /*Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.*/ + uint32_t out_dscr_err_ch4: 1; /*Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.*/ + uint32_t in_dscr_empty_ch4: 1; /*Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.*/ + uint32_t out_total_eof_ch4: 1; /*Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.*/ + uint32_t infifo_full_wm_ch4: 1; /*Set this bit to clear the INFIFO_FULL_WM_CH_INT interrupt.*/ + uint32_t infifo_ovf_l1_ch4: 1; /*Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t infifo_udf_l1_ch4: 1; /*Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t infifo_ovf_l3_ch4: 1; /*Set this bit to clear the INFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t infifo_udf_l3_ch4: 1; /*Set this bit to clear the INFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l1_ch4: 1; /*Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.*/ + uint32_t outfifo_udf_l1_ch4: 1; /*Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.*/ + uint32_t outfifo_ovf_l3_ch4: 1; /*Set this bit to clear the OUTFIFO_OVF_L3_CH_INT interrupt.*/ + uint32_t outfifo_udf_l3_ch4: 1; /*Set this bit to clear the OUTFIFO_UDF_L3_CH_INT interrupt.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } int_clr_ch4; + union { + struct { + uint32_t infifo_full_l1_ch0: 1; /*L1 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l1_ch0: 1; /*L1 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_full_l2_ch0: 1; /*L2 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l2_ch0: 1; /*L2 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_full_l3_ch0: 1; /*L3 Rx FIFO full signal for Rx channel 0.*/ + uint32_t infifo_empty_l3_ch0: 1; /*L3 Rx FIFO empty signal for Rx channel 0.*/ + uint32_t infifo_cnt_l1_ch0: 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.*/ + uint32_t infifo_cnt_l2_ch0: 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 0.*/ + uint32_t infifo_cnt_l3_ch0: 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 0.*/ + uint32_t in_remain_under_1b_l3_ch0: 1; /*reserved*/ + uint32_t in_remain_under_2b_l3_ch0: 1; /*reserved*/ + uint32_t in_remain_under_3b_l3_ch0: 1; /*reserved*/ + uint32_t in_remain_under_4b_l3_ch0: 1; /*reserved*/ + uint32_t in_buf_hungry_ch0: 1; /*reserved*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } infifo_status_ch0; + union { + struct { + uint32_t infifo_full_l1_ch1: 1; /*L1 Rx FIFO full signal for Rx channel 1.*/ + uint32_t infifo_empty_l1_ch1: 1; /*L1 Rx FIFO empty signal for Rx channel 1.*/ + uint32_t infifo_full_l2_ch1: 1; /*L2 Rx FIFO full signal for Rx channel 1.*/ + uint32_t infifo_empty_l2_ch1: 1; /*L2 Rx FIFO empty signal for Rx channel 1.*/ + uint32_t infifo_full_l3_ch1: 1; /*L3 Rx FIFO full signal for Rx channel 1.*/ + uint32_t infifo_empty_l3_ch1: 1; /*L3 Rx FIFO empty signal for Rx channel 1.*/ + uint32_t infifo_cnt_l1_ch1: 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.*/ + uint32_t infifo_cnt_l2_ch1: 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 1.*/ + uint32_t infifo_cnt_l3_ch1: 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 1.*/ + uint32_t in_remain_under_1b_l3_ch1: 1; /*reserved*/ + uint32_t in_remain_under_2b_l3_ch1: 1; /*reserved*/ + uint32_t in_remain_under_3b_l3_ch1: 1; /*reserved*/ + uint32_t in_remain_under_4b_l3_ch1: 1; /*reserved*/ + uint32_t in_buf_hungry_ch1: 1; /*reserved*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } infifo_status_ch1; + union { + struct { + uint32_t infifo_full_l1_ch2: 1; /*L1 Rx FIFO full signal for Rx channel 2.*/ + uint32_t infifo_empty_l1_ch2: 1; /*L1 Rx FIFO empty signal for Rx channel 2.*/ + uint32_t infifo_full_l2_ch2: 1; /*L2 Rx FIFO full signal for Rx channel 2.*/ + uint32_t infifo_empty_l2_ch2: 1; /*L2 Rx FIFO empty signal for Rx channel 2.*/ + uint32_t infifo_full_l3_ch2: 1; /*L3 Rx FIFO full signal for Rx channel 2.*/ + uint32_t infifo_empty_l3_ch2: 1; /*L3 Rx FIFO empty signal for Rx channel 2.*/ + uint32_t infifo_cnt_l1_ch2: 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.*/ + uint32_t infifo_cnt_l2_ch2: 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 2.*/ + uint32_t infifo_cnt_l3_ch2: 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 2.*/ + uint32_t in_remain_under_1b_l3_ch2: 1; /*reserved*/ + uint32_t in_remain_under_2b_l3_ch2: 1; /*reserved*/ + uint32_t in_remain_under_3b_l3_ch2: 1; /*reserved*/ + uint32_t in_remain_under_4b_l3_ch2: 1; /*reserved*/ + uint32_t in_buf_hungry_ch2: 1; /*reserved*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } infifo_status_ch2; + union { + struct { + uint32_t infifo_full_l1_ch3: 1; /*L1 Rx FIFO full signal for Rx channel 3.*/ + uint32_t infifo_empty_l1_ch3: 1; /*L1 Rx FIFO empty signal for Rx channel 3.*/ + uint32_t infifo_full_l2_ch3: 1; /*L2 Rx FIFO full signal for Rx channel 3.*/ + uint32_t infifo_empty_l2_ch3: 1; /*L2 Rx FIFO empty signal for Rx channel 3.*/ + uint32_t infifo_full_l3_ch3: 1; /*L3 Rx FIFO full signal for Rx channel 3.*/ + uint32_t infifo_empty_l3_ch3: 1; /*L3 Rx FIFO empty signal for Rx channel 3.*/ + uint32_t infifo_cnt_l1_ch3: 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 3.*/ + uint32_t infifo_cnt_l2_ch3: 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 3.*/ + uint32_t infifo_cnt_l3_ch3: 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 3.*/ + uint32_t in_remain_under_1b_l3_ch3: 1; /*reserved*/ + uint32_t in_remain_under_2b_l3_ch3: 1; /*reserved*/ + uint32_t in_remain_under_3b_l3_ch3: 1; /*reserved*/ + uint32_t in_remain_under_4b_l3_ch3: 1; /*reserved*/ + uint32_t in_buf_hungry_ch3: 1; /*reserved*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } infifo_status_ch3; + union { + struct { + uint32_t infifo_full_l1_ch4: 1; /*L1 Rx FIFO full signal for Rx channel 4.*/ + uint32_t infifo_empty_l1_ch4: 1; /*L1 Rx FIFO empty signal for Rx channel 4.*/ + uint32_t infifo_full_l2_ch4: 1; /*L2 Rx FIFO full signal for Rx channel 4.*/ + uint32_t infifo_empty_l2_ch4: 1; /*L2 Rx FIFO empty signal for Rx channel 4.*/ + uint32_t infifo_full_l3_ch4: 1; /*L3 Rx FIFO full signal for Rx channel 4.*/ + uint32_t infifo_empty_l3_ch4: 1; /*L3 Rx FIFO empty signal for Rx channel 4.*/ + uint32_t infifo_cnt_l1_ch4: 5; /*The register stores the byte number of the data in L1 Rx FIFO for Rx channel 4.*/ + uint32_t infifo_cnt_l2_ch4: 7; /*The register stores the byte number of the data in L2 Rx FIFO for Rx channel 4.*/ + uint32_t infifo_cnt_l3_ch4: 5; /*The register stores the byte number of the data in L3 Rx FIFO for Rx channel 4.*/ + uint32_t in_remain_under_1b_l3_ch4: 1; /*reserved*/ + uint32_t in_remain_under_2b_l3_ch4: 1; /*reserved*/ + uint32_t in_remain_under_3b_l3_ch4: 1; /*reserved*/ + uint32_t in_remain_under_4b_l3_ch4: 1; /*reserved*/ + uint32_t in_buf_hungry_ch4: 1; /*reserved*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } infifo_status_ch4; + union { + struct { + uint32_t outfifo_full_l1_ch0: 1; /*L1 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l1_ch0: 1; /*L1 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_full_l2_ch0: 1; /*L2 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l2_ch0: 1; /*L2 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_full_l3_ch0: 1; /*L3 Tx FIFO full signal for Tx channel 0.*/ + uint32_t outfifo_empty_l3_ch0: 1; /*L3 Tx FIFO empty signal for Tx channel 0.*/ + uint32_t outfifo_cnt_l1_ch0: 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.*/ + uint32_t outfifo_cnt_l2_ch0: 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 0.*/ + uint32_t outfifo_cnt_l3_ch0: 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 0.*/ + uint32_t out_remain_under_1b_l3_ch0: 1; /*reserved*/ + uint32_t out_remain_under_2b_l3_ch0: 1; /*reserved*/ + uint32_t out_remain_under_3b_l3_ch0: 1; /*reserved*/ + uint32_t out_remain_under_4b_l3_ch0: 1; /*reserved*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status_ch0; + union { + struct { + uint32_t outfifo_full_l1_ch1: 1; /*L1 Tx FIFO full signal for Tx channel 1.*/ + uint32_t outfifo_empty_l1_ch1: 1; /*L1 Tx FIFO empty signal for Tx channel 1.*/ + uint32_t outfifo_full_l2_ch1: 1; /*L2 Tx FIFO full signal for Tx channel 1.*/ + uint32_t outfifo_empty_l2_ch1: 1; /*L2 Tx FIFO empty signal for Tx channel 1.*/ + uint32_t outfifo_full_l3_ch1: 1; /*L3 Tx FIFO full signal for Tx channel 1.*/ + uint32_t outfifo_empty_l3_ch1: 1; /*L3 Tx FIFO empty signal for Tx channel 1.*/ + uint32_t outfifo_cnt_l1_ch1: 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.*/ + uint32_t outfifo_cnt_l2_ch1: 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 1.*/ + uint32_t outfifo_cnt_l3_ch1: 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 1.*/ + uint32_t out_remain_under_1b_l3_ch1: 1; /*reserved*/ + uint32_t out_remain_under_2b_l3_ch1: 1; /*reserved*/ + uint32_t out_remain_under_3b_l3_ch1: 1; /*reserved*/ + uint32_t out_remain_under_4b_l3_ch1: 1; /*reserved*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status_ch1; + union { + struct { + uint32_t outfifo_full_l1_ch2: 1; /*L1 Tx FIFO full signal for Tx channel 2.*/ + uint32_t outfifo_empty_l1_ch2: 1; /*L1 Tx FIFO empty signal for Tx channel 2.*/ + uint32_t outfifo_full_l2_ch2: 1; /*L2 Tx FIFO full signal for Tx channel 2.*/ + uint32_t outfifo_empty_l2_ch2: 1; /*L2 Tx FIFO empty signal for Tx channel 2.*/ + uint32_t outfifo_full_l3_ch2: 1; /*L3 Tx FIFO full signal for Tx channel 2.*/ + uint32_t outfifo_empty_l3_ch2: 1; /*L3 Tx FIFO empty signal for Tx channel 2.*/ + uint32_t outfifo_cnt_l1_ch2: 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.*/ + uint32_t outfifo_cnt_l2_ch2: 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 2.*/ + uint32_t outfifo_cnt_l3_ch2: 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 2.*/ + uint32_t out_remain_under_1b_l3_ch2: 1; /*reserved*/ + uint32_t out_remain_under_2b_l3_ch2: 1; /*reserved*/ + uint32_t out_remain_under_3b_l3_ch2: 1; /*reserved*/ + uint32_t out_remain_under_4b_l3_ch2: 1; /*reserved*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status_ch2; + union { + struct { + uint32_t outfifo_full_l1_ch3: 1; /*L1 Tx FIFO full signal for Tx channel 3.*/ + uint32_t outfifo_empty_l1_ch3: 1; /*L1 Tx FIFO empty signal for Tx channel 3.*/ + uint32_t outfifo_full_l2_ch3: 1; /*L2 Tx FIFO full signal for Tx channel 3.*/ + uint32_t outfifo_empty_l2_ch3: 1; /*L2 Tx FIFO empty signal for Tx channel 3.*/ + uint32_t outfifo_full_l3_ch3: 1; /*L3 Tx FIFO full signal for Tx channel 3.*/ + uint32_t outfifo_empty_l3_ch3: 1; /*L3 Tx FIFO empty signal for Tx channel 3.*/ + uint32_t outfifo_cnt_l1_ch3: 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 3.*/ + uint32_t outfifo_cnt_l2_ch3: 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 3.*/ + uint32_t outfifo_cnt_l3_ch3: 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 3.*/ + uint32_t out_remain_under_1b_l3_ch3: 1; /*reserved*/ + uint32_t out_remain_under_2b_l3_ch3: 1; /*reserved*/ + uint32_t out_remain_under_3b_l3_ch3: 1; /*reserved*/ + uint32_t out_remain_under_4b_l3_ch3: 1; /*reserved*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status_ch3; + union { + struct { + uint32_t outfifo_full_l1_ch4: 1; /*L1 Tx FIFO full signal for Tx channel 4.*/ + uint32_t outfifo_empty_l1_ch4: 1; /*L1 Tx FIFO empty signal for Tx channel 4.*/ + uint32_t outfifo_full_l2_ch4: 1; /*L2 Tx FIFO full signal for Tx channel 4.*/ + uint32_t outfifo_empty_l2_ch4: 1; /*L2 Tx FIFO empty signal for Tx channel 4.*/ + uint32_t outfifo_full_l3_ch4: 1; /*L3 Tx FIFO full signal for Tx channel 4.*/ + uint32_t outfifo_empty_l3_ch4: 1; /*L3 Tx FIFO empty signal for Tx channel 4.*/ + uint32_t outfifo_cnt_l1_ch4: 5; /*The register stores the byte number of the data in L1 Tx FIFO for Tx channel 4.*/ + uint32_t outfifo_cnt_l2_ch4: 7; /*The register stores the byte number of the data in L2 Tx FIFO for Tx channel 4.*/ + uint32_t outfifo_cnt_l3_ch4: 5; /*The register stores the byte number of the data in L3 Tx FIFO for Tx channel 4.*/ + uint32_t out_remain_under_1b_l3_ch4: 1; /*reserved*/ + uint32_t out_remain_under_2b_l3_ch4: 1; /*reserved*/ + uint32_t out_remain_under_3b_l3_ch4: 1; /*reserved*/ + uint32_t out_remain_under_4b_l3_ch4: 1; /*reserved*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } outfifo_status_ch4; + union { + struct { + uint32_t outfifo_wdata_ch0: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push_ch0: 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } out_push_ch0; + union { + struct { + uint32_t outfifo_wdata_ch1: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push_ch1: 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } out_push_ch1; + union { + struct { + uint32_t outfifo_wdata_ch2: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push_ch2: 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } out_push_ch2; + union { + struct { + uint32_t outfifo_wdata_ch3: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push_ch3: 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } out_push_ch3; + union { + struct { + uint32_t outfifo_wdata_ch4: 9; /*This register stores the data that need to be pushed into DMA FIFO.*/ + uint32_t outfifo_push_ch4: 1; /*Set this bit to push data into DMA FIFO.*/ + uint32_t reserved10: 22; /*reserved*/ + }; + uint32_t val; + } out_push_ch4; + union { + struct { + uint32_t infifo_rdata_ch0: 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop_ch0: 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } in_pop_ch0; + union { + struct { + uint32_t infifo_rdata_ch1: 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop_ch1: 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } in_pop_ch1; + union { + struct { + uint32_t infifo_rdata_ch2: 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop_ch2: 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } in_pop_ch2; + union { + struct { + uint32_t infifo_rdata_ch3: 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop_ch3: 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } in_pop_ch3; + union { + struct { + uint32_t infifo_rdata_ch4: 12; /*This register stores the data popping from DMA FIFO.*/ + uint32_t infifo_pop_ch4: 1; /*Set this bit to pop data from DMA FIFO.*/ + uint32_t reserved13: 19; /*reserved*/ + }; + uint32_t val; + } in_pop_ch4; + union { + struct { + uint32_t outlink_addr_ch0: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t outlink_stop_ch0: 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t outlink_start_ch0: 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t outlink_restart_ch0: 1; /*Set this bit to restart a new outlink from the last address.*/ + uint32_t outlink_park_ch0: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } out_link_ch0; + union { + struct { + uint32_t outlink_addr_ch1: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t outlink_stop_ch1: 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t outlink_start_ch1: 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t outlink_restart_ch1: 1; /*Set this bit to restart a new outlink from the last address.*/ + uint32_t outlink_park_ch1: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } out_link_ch1; + union { + struct { + uint32_t outlink_addr_ch2: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t outlink_stop_ch2: 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t outlink_start_ch2: 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t outlink_restart_ch2: 1; /*Set this bit to restart a new outlink from the last address.*/ + uint32_t outlink_park_ch2: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } out_link_ch2; + union { + struct { + uint32_t outlink_addr_ch3: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t outlink_stop_ch3: 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t outlink_start_ch3: 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t outlink_restart_ch3: 1; /*Set this bit to restart a new outlink from the last address.*/ + uint32_t outlink_park_ch3: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } out_link_ch3; + union { + struct { + uint32_t outlink_addr_ch4: 20; /*This register stores the 20 least significant bits of the first outlink descriptor's address.*/ + uint32_t outlink_stop_ch4: 1; /*Set this bit to stop dealing with the outlink descriptors.*/ + uint32_t outlink_start_ch4: 1; /*Set this bit to start dealing with the outlink descriptors.*/ + uint32_t outlink_restart_ch4: 1; /*Set this bit to restart a new outlink from the last address.*/ + uint32_t outlink_park_ch4: 1; /*1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } out_link_ch4; + union { + struct { + uint32_t inlink_addr_ch0: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t inlink_auto_ret_ch0: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ + uint32_t inlink_stop_ch0: 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t inlink_start_ch0: 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t inlink_restart_ch0: 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t inlink_park_ch0: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } in_link_ch0; + union { + struct { + uint32_t inlink_addr_ch1: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t inlink_auto_ret_ch1: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ + uint32_t inlink_stop_ch1: 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t inlink_start_ch1: 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t inlink_restart_ch1: 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t inlink_park_ch1: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } in_link_ch1; + union { + struct { + uint32_t inlink_addr_ch2: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t inlink_auto_ret_ch2: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ + uint32_t inlink_stop_ch2: 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t inlink_start_ch2: 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t inlink_restart_ch2: 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t inlink_park_ch2: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } in_link_ch2; + union { + struct { + uint32_t inlink_addr_ch3: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t inlink_auto_ret_ch3: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ + uint32_t inlink_stop_ch3: 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t inlink_start_ch3: 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t inlink_restart_ch3: 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t inlink_park_ch3: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } in_link_ch3; + union { + struct { + uint32_t inlink_addr_ch4: 20; /*This register stores the 20 least significant bits of the first inlink descriptor's address.*/ + uint32_t inlink_auto_ret_ch4: 1; /*Set this bit to return to current inlink descriptor's address when there are some errors in current receiving data.*/ + uint32_t inlink_stop_ch4: 1; /*Set this bit to stop dealing with the inlink descriptors.*/ + uint32_t inlink_start_ch4: 1; /*Set this bit to start dealing with the inlink descriptors.*/ + uint32_t inlink_restart_ch4: 1; /*Set this bit to mount a new inlink descriptor.*/ + uint32_t inlink_park_ch4: 1; /*1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } in_link_ch4; + union { + struct { + uint32_t inlink_dscr_addr_ch0: 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state_ch0: 2; /*reserved*/ + uint32_t in_state_ch0: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } in_state_ch0; + union { + struct { + uint32_t inlink_dscr_addr_ch1: 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state_ch1: 2; /*reserved*/ + uint32_t in_state_ch1: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } in_state_ch1; + union { + struct { + uint32_t inlink_dscr_addr_ch2: 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state_ch2: 2; /*reserved*/ + uint32_t in_state_ch2: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } in_state_ch2; + union { + struct { + uint32_t inlink_dscr_addr_ch3: 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state_ch3: 2; /*reserved*/ + uint32_t in_state_ch3: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } in_state_ch3; + union { + struct { + uint32_t inlink_dscr_addr_ch4: 18; /*This register stores the current inlink descriptor's address.*/ + uint32_t in_dscr_state_ch4: 2; /*reserved*/ + uint32_t in_state_ch4: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } in_state_ch4; + union { + struct { + uint32_t outlink_dscr_addr_ch0: 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state_ch0: 2; /*reserved*/ + uint32_t out_state_ch0: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } out_state_ch0; + union { + struct { + uint32_t outlink_dscr_addr_ch1: 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state_ch1: 2; /*reserved*/ + uint32_t out_state_ch1: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } out_state_ch1; + union { + struct { + uint32_t outlink_dscr_addr_ch2: 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state_ch2: 2; /*reserved*/ + uint32_t out_state_ch2: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } out_state_ch2; + union { + struct { + uint32_t outlink_dscr_addr_ch3: 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state_ch3: 2; /*reserved*/ + uint32_t out_state_ch3: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } out_state_ch3; + union { + struct { + uint32_t outlink_dscr_addr_ch4: 18; /*This register stores the current outlink descriptor's address.*/ + uint32_t out_dscr_state_ch4: 2; /*reserved*/ + uint32_t out_state_ch4: 3; /*reserved*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } out_state_ch4; + uint32_t out_eof_des_addr_ch0; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t out_eof_des_addr_ch1; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t out_eof_des_addr_ch2; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t out_eof_des_addr_ch3; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t out_eof_des_addr_ch4; /*This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t in_suc_eof_des_addr_ch0; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t in_suc_eof_des_addr_ch1; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t in_suc_eof_des_addr_ch2; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t in_suc_eof_des_addr_ch3; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t in_suc_eof_des_addr_ch4; /*This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.*/ + uint32_t in_err_eof_des_addr_ch0; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ + uint32_t in_err_eof_des_addr_ch1; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ + uint32_t in_err_eof_des_addr_ch2; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ + uint32_t in_err_eof_des_addr_ch3; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ + uint32_t in_err_eof_des_addr_ch4; /*This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.*/ + uint32_t out_eof_bfr_des_addr_ch0; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/ + uint32_t out_eof_bfr_des_addr_ch1; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/ + uint32_t out_eof_bfr_des_addr_ch2; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/ + uint32_t out_eof_bfr_des_addr_ch3; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/ + uint32_t out_eof_bfr_des_addr_ch4; /*This register stores the address of the outlink descriptor before the last outlink descriptor.*/ + union { + struct { + uint32_t ahb_testmode: 3; /*reserved*/ + uint32_t reserved3: 1; /*reserved*/ + uint32_t ahb_testaddr: 2; /*reserved*/ + uint32_t reserved6: 26; /*reserved*/ + }; + uint32_t val; + } ahb_test; + uint32_t in_dscr_ch0; /*The address of the current inlink descriptor x.*/ + uint32_t in_dscr_ch1; /*The address of the current inlink descriptor x.*/ + uint32_t in_dscr_ch2; /*The address of the current inlink descriptor x.*/ + uint32_t in_dscr_ch3; /*The address of the current inlink descriptor x.*/ + uint32_t in_dscr_ch4; /*The address of the current inlink descriptor x.*/ + uint32_t in_dscr_bf0_ch0; /*The address of the last inlink descriptor x-1.*/ + uint32_t in_dscr_bf0_ch1; /*The address of the last inlink descriptor x-1.*/ + uint32_t in_dscr_bf0_ch2; /*The address of the last inlink descriptor x-1.*/ + uint32_t in_dscr_bf0_ch3; /*The address of the last inlink descriptor x-1.*/ + uint32_t in_dscr_bf0_ch4; /*The address of the last inlink descriptor x-1.*/ + uint32_t in_dscr_bf1_ch0; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t in_dscr_bf1_ch1; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t in_dscr_bf1_ch2; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t in_dscr_bf1_ch3; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t in_dscr_bf1_ch4; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t out_dscr_ch0; /*The address of the current outlink descriptor y.*/ + uint32_t out_dscr_ch1; /*The address of the current outlink descriptor y.*/ + uint32_t out_dscr_ch2; /*The address of the current outlink descriptor y.*/ + uint32_t out_dscr_ch3; /*The address of the current outlink descriptor y.*/ + uint32_t out_dscr_ch4; /*The address of the current outlink descriptor y.*/ + uint32_t out_dscr_bf0_ch0; /*The address of the last outlink descriptor y-1.*/ + uint32_t out_dscr_bf0_ch1; /*The address of the last outlink descriptor y-1.*/ + uint32_t out_dscr_bf0_ch2; /*The address of the last outlink descriptor y-1.*/ + uint32_t out_dscr_bf0_ch3; /*The address of the last outlink descriptor y-1.*/ + uint32_t out_dscr_bf0_ch4; /*The address of the last outlink descriptor y-1.*/ + uint32_t out_dscr_bf1_ch0; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t out_dscr_bf1_ch1; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t out_dscr_bf1_ch2; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t out_dscr_bf1_ch3; /*The address of the second-to-last inlink descriptor x-2.*/ + uint32_t out_dscr_bf1_ch4; /*The address of the second-to-last inlink descriptor x-2.*/ + union { + struct { + uint32_t reserved0: 4; /*reserved*/ + uint32_t ram_force_pd: 1; /*power down*/ + uint32_t ram_force_pu: 1; + uint32_t ram_clk_fo: 1; /*1: Force to open the clock and bypass the gate-clock when accessing the RAM in DMA. 0: A gate-clock will be used when accessing the RAM in DMA.*/ + uint32_t reserved7: 25; /*reserved*/ + }; + uint32_t val; + } pd_conf; + union { + struct { + uint32_t tx_weight_ch0: 4; /*The weight of Tx channel 0.*/ + uint32_t rx_weight_ch0: 4; /*The weight of Rx channel 0.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } wight_ch0; + union { + struct { + uint32_t tx_weight_ch1: 4; /*The weight of Tx channel 1.*/ + uint32_t rx_weight_ch1: 4; /*The weight of Rx channel 1.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } wight_ch1; + union { + struct { + uint32_t tx_weight_ch2: 4; /*The weight of Tx channel 2.*/ + uint32_t rx_weight_ch2: 4; /*The weight of Rx channel 2.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } wight_ch2; + union { + struct { + uint32_t tx_weight_ch3: 4; /*The weight of Tx channel 3.*/ + uint32_t rx_weight_ch3: 4; /*The weight of Rx channel 3.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } wight_ch3; + union { + struct { + uint32_t tx_weight_ch4: 4; /*The weight of Tx channel 4.*/ + uint32_t rx_weight_ch4: 4; /*The weight of Rx channel 4.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } wight_ch4; + union { + struct { + uint32_t tx_pri_ch0: 4; /*The priority of Tx channel 0. The larger of the value the higher of the priority.*/ + uint32_t rx_pri_ch0: 4; /*The priority of Rx channel 0. The larger of the value the higher of the priority.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pri_ch0; + union { + struct { + uint32_t tx_pri_ch1: 4; /*The priority of Tx channel 1. The larger of the value the higher of the priority.*/ + uint32_t rx_pri_ch1: 4; /*The priority of Rx channel 1. The larger of the value the higher of the priority.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pri_ch1; + union { + struct { + uint32_t tx_pri_ch2: 4; /*The priority of Tx channel 2. The larger of the value the higher of the priority.*/ + uint32_t rx_pri_ch2: 4; /*The priority of Rx channel 2. The larger of the value the higher of the priority.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pri_ch2; + union { + struct { + uint32_t tx_pri_ch3: 4; /*The priority of Tx channel 3. The larger of the value the higher of the priority.*/ + uint32_t rx_pri_ch3: 4; /*The priority of Rx channel 3. The larger of the value the higher of the priority.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pri_ch3; + union { + struct { + uint32_t tx_pri_ch4: 4; /*The priority of Tx channel 4. The larger of the value the higher of the priority.*/ + uint32_t rx_pri_ch4: 4; /*The priority of Rx channel 4. The larger of the value the higher of the priority.*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } pri_ch4; + union { + struct { + uint32_t ahbm_rst_inter: 1; /*Set this bit then clear this bit to reset the internal ahb FSM.*/ + uint32_t ahbm_rst_exter: 1; /*Set this bit then clear this bit to reset the external ahb FSM.*/ + uint32_t arb_pri_dis: 1; /*Set this bit to disable priority arbitration function.*/ + uint32_t clk_en: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } misc_conf; + union { + struct { + uint32_t peri_in_sel_ch0: 6; /*This register is used to select peripheral for Rx channel 0. 0:SPI2*/ + uint32_t peri_out_sel_ch0: 6; /*This register is used to select peripheral for Tx channel 0. 0:SPI2*/ + uint32_t reserved12: 20; + }; + uint32_t val; + } peri_sel_ch0; + union { + struct { + uint32_t peri_in_sel_ch1: 6; /*This register is used to select peripheral for Rx channel 1. 0:SPI2*/ + uint32_t peri_out_sel_ch1: 6; /*This register is used to select peripheral for Tx channel 1. 0:SPI2*/ + uint32_t reserved12: 20; + }; + uint32_t val; + } peri_sel_ch1; + union { + struct { + uint32_t peri_in_sel_ch2: 6; /*This register is used to select peripheral for Rx channel 2. 0:SPI2*/ + uint32_t peri_out_sel_ch2: 6; /*This register is used to select peripheral for Tx channel 2. 0:SPI2*/ + uint32_t reserved12: 20; + }; + uint32_t val; + } peri_sel_ch2; + union { + struct { + uint32_t peri_in_sel_ch3: 6; /*This register is used to select peripheral for Rx channel 3. 0:SPI2*/ + uint32_t peri_out_sel_ch3: 6; /*This register is used to select peripheral for Tx channel 3. 0:SPI2*/ + uint32_t reserved12: 20; + }; + uint32_t val; + } peri_sel_ch3; + union { + struct { + uint32_t peri_in_sel_ch4: 6; /*This register is used to select peripheral for Rx channel 4. 0:SPI2*/ + uint32_t peri_out_sel_ch4: 6; /*This register is used to select peripheral for Tx channel 4. 0:SPI2*/ + uint32_t reserved12: 20; + }; + uint32_t val; + } peri_sel_ch4; + union { + struct { + uint32_t in_size_ch0: 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 0. 0:16 bytes*/ + uint32_t out_size_ch0: 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 0. 0:16 bytes*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sram_size_ch0; + union { + struct { + uint32_t in_size_ch1: 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 1. 0:16 bytes*/ + uint32_t out_size_ch1: 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 1. 0:16 bytes*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sram_size_ch1; + union { + struct { + uint32_t in_size_ch2: 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 2. 0:16 bytes*/ + uint32_t out_size_ch2: 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 2. 0:16 bytes*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sram_size_ch2; + union { + struct { + uint32_t in_size_ch3: 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 3. 0:16 bytes*/ + uint32_t out_size_ch3: 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 3. 0:16 bytes*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sram_size_ch3; + union { + struct { + uint32_t in_size_ch4: 5; /*This register is used to configure the size of L2 Rx FIFO for Rx channel 4. 0:16 bytes*/ + uint32_t out_size_ch4: 5; /*This register is used to configure the size of L2 Tx FIFO for Tx channel 4. 0:16 bytes*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } sram_size_ch4; + uint32_t date; /*register version.*/ +} dma_dev_t; + +extern dma_dev_t DMA; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/dport_access.h b/components/soc/soc/esp32s3/include/soc/dport_access.h new file mode 100644 index 000000000..2f8b1d48d --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/dport_access.h @@ -0,0 +1,109 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include +#include "esp_attr.h" +#include "esp_attr.h" +#include "esp32s3/dport_access.h" +#include "soc.h" +#include "uart_reg.h" +#include "xtensa/xtruntime.h" + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32S3 does not have DPORT bus, so these macros are all same as the non-DPORT versions + +// _DPORT_REG_WRITE & DPORT_REG_WRITE are equivalent. +#define _DPORT_REG_READ(_r) (*(volatile uint32_t *)(_r)) +#define _DPORT_REG_WRITE(_r, _v) (*(volatile uint32_t *)(_r)) = (_v) + +// Write value to DPORT register (does not require protecting) +#define DPORT_REG_WRITE(_r, _v) _DPORT_REG_WRITE((_r), (_v)) + +#define DPORT_REG_READ(_r) _DPORT_REG_READ(_r) +#define DPORT_SEQUENCE_REG_READ(_r) _DPORT_REG_READ(_r) + +//get bit or get bits from register +#define DPORT_REG_GET_BIT(_r, _b) (DPORT_REG_READ(_r) & (_b)) + +//set bit or set bits to register +#define DPORT_REG_SET_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r)|(_b))) + +//clear bit or clear bits of register +#define DPORT_REG_CLR_BIT(_r, _b) DPORT_REG_WRITE((_r), (DPORT_REG_READ(_r) & (~(_b)))) + +//set bits of register controlled by mask +#define DPORT_REG_SET_BITS(_r, _b, _m) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~(_m))) | ((_b) & (_m)))) + +//get field from register, uses field _S & _V to determine mask +#define DPORT_REG_GET_FIELD(_r, _f) ((DPORT_REG_READ(_r) >> (_f##_S)) & (_f##_V)) + +//set field to register, used when _f is not left shifted by _f##_S +#define DPORT_REG_SET_FIELD(_r, _f, _v) DPORT_REG_WRITE((_r), ((DPORT_REG_READ(_r) & (~((_f##_V) << (_f##_S))))|(((_v) & (_f##_V))<<(_f##_S)))) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define DPORT_VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define DPORT_FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//Register read macros with an underscore prefix access DPORT memory directly. In IDF apps, use the non-underscore versions to be SMP-safe. +#define _DPORT_READ_PERI_REG(addr) (*((volatile uint32_t *)(addr))) +#define _DPORT_WRITE_PERI_REG(addr, val) (*((volatile uint32_t *)(addr))) = (uint32_t)(val) +#define _DPORT_REG_SET_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r)|(_b))) +#define _DPORT_REG_CLR_BIT(_r, _b) _DPORT_REG_WRITE((_r), (_DPORT_REG_READ(_r) & (~(_b)))) + +#define DPORT_READ_PERI_REG(addr) _DPORT_READ_PERI_REG(addr) + +//write value to register +#define DPORT_WRITE_PERI_REG(addr, val) _DPORT_WRITE_PERI_REG((addr), (val)) + +//clear bits of register controlled by mask +#define DPORT_CLEAR_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)&(~(mask)))) + +//set bits of register controlled by mask +#define DPORT_SET_PERI_REG_MASK(reg, mask) DPORT_WRITE_PERI_REG((reg), (DPORT_READ_PERI_REG(reg)|(mask))) + +//get bits of register controlled by mask +#define DPORT_GET_PERI_REG_MASK(reg, mask) (DPORT_READ_PERI_REG(reg) & (mask)) + +//get bits of register controlled by highest bit and lowest bit +#define DPORT_GET_PERI_REG_BITS(reg, hipos,lowpos) ((DPORT_READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)) + +//set bits of register controlled by mask and shift +#define DPORT_SET_PERI_REG_BITS(reg,bit_map,value,shift) DPORT_WRITE_PERI_REG((reg), ((DPORT_READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)))) + +//get field of register +#define DPORT_GET_PERI_REG_BITS2(reg, mask,shift) ((DPORT_READ_PERI_REG(reg)>>(shift))&(mask)) +//}} + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/dport_reg.h b/components/soc/soc/esp32s3/include/soc/dport_reg.h new file mode 100644 index 000000000..1a3f69f46 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/dport_reg.h @@ -0,0 +1,33 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "interrupt_reg.h" +#include "system_reg.h" +#include "sensitive_reg.h" +#include "soc.h" + +#define DPORT_DATE_REG SYSTEM_DATE_REG + +#ifndef __ASSEMBLER__ +#include "dport_access.h" +#endif + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/efuse_reg.h b/components/soc/soc/esp32s3/include/soc/efuse_reg.h new file mode 100644 index 000000000..230193647 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/efuse_reg.h @@ -0,0 +1,421 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define EFUSE_RD_RS_ERR0_REG (DR_REG_EFUSE_BASE + 0x1c0) +/* EFUSE_RD_KEY4_FAIL : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_KEY4_FAIL (BIT(31)) +#define EFUSE_RD_KEY4_FAIL_M (BIT(31)) +#define EFUSE_RD_KEY4_FAIL_V 0x1 +#define EFUSE_RD_KEY4_FAIL_S 31 +/* EFUSE_RD_KEY4_ERR_NUM : RO ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_KEY4_ERR_NUM 0x00000007 +#define EFUSE_RD_KEY4_ERR_NUM_M ((EFUSE_RD_KEY4_ERR_NUM_V) << (EFUSE_RD_KEY4_ERR_NUM_S)) +#define EFUSE_RD_KEY4_ERR_NUM_V 0x7 +#define EFUSE_RD_KEY4_ERR_NUM_S 28 +/* EFUSE_RD_KEY3_FAIL : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_KEY3_FAIL (BIT(27)) +#define EFUSE_RD_KEY3_FAIL_M (BIT(27)) +#define EFUSE_RD_KEY3_FAIL_V 0x1 +#define EFUSE_RD_KEY3_FAIL_S 27 +/* EFUSE_RD_KEY3_ERR_NUM : RO ;bitpos:[26:24] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_KEY3_ERR_NUM 0x00000007 +#define EFUSE_RD_KEY3_ERR_NUM_M ((EFUSE_RD_KEY3_ERR_NUM_V) << (EFUSE_RD_KEY3_ERR_NUM_S)) +#define EFUSE_RD_KEY3_ERR_NUM_V 0x7 +#define EFUSE_RD_KEY3_ERR_NUM_S 24 +/* EFUSE_RD_KEY2_FAIL : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_KEY2_FAIL (BIT(23)) +#define EFUSE_RD_KEY2_FAIL_M (BIT(23)) +#define EFUSE_RD_KEY2_FAIL_V 0x1 +#define EFUSE_RD_KEY2_FAIL_S 23 +/* EFUSE_RD_KEY2_ERR_NUM : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_KEY2_ERR_NUM 0x00000007 +#define EFUSE_RD_KEY2_ERR_NUM_M ((EFUSE_RD_KEY2_ERR_NUM_V) << (EFUSE_RD_KEY2_ERR_NUM_S)) +#define EFUSE_RD_KEY2_ERR_NUM_V 0x7 +#define EFUSE_RD_KEY2_ERR_NUM_S 20 +/* EFUSE_RD_KEY1_FAIL : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_KEY1_FAIL (BIT(19)) +#define EFUSE_RD_KEY1_FAIL_M (BIT(19)) +#define EFUSE_RD_KEY1_FAIL_V 0x1 +#define EFUSE_RD_KEY1_FAIL_S 19 +/* EFUSE_RD_KEY1_ERR_NUM : RO ;bitpos:[18:16] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_KEY1_ERR_NUM 0x00000007 +#define EFUSE_RD_KEY1_ERR_NUM_M ((EFUSE_RD_KEY1_ERR_NUM_V) << (EFUSE_RD_KEY1_ERR_NUM_S)) +#define EFUSE_RD_KEY1_ERR_NUM_V 0x7 +#define EFUSE_RD_KEY1_ERR_NUM_S 16 +/* EFUSE_RD_KEY0_FAIL : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of key$n is reliable 1: + Means that programming key$n failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_KEY0_FAIL (BIT(15)) +#define EFUSE_RD_KEY0_FAIL_M (BIT(15)) +#define EFUSE_RD_KEY0_FAIL_V 0x1 +#define EFUSE_RD_KEY0_FAIL_S 15 +/* EFUSE_RD_KEY0_ERR_NUM : RO ;bitpos:[14:12] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_KEY0_ERR_NUM 0x00000007 +#define EFUSE_RD_KEY0_ERR_NUM_M ((EFUSE_RD_KEY0_ERR_NUM_V) << (EFUSE_RD_KEY0_ERR_NUM_S)) +#define EFUSE_RD_KEY0_ERR_NUM_V 0x7 +#define EFUSE_RD_KEY0_ERR_NUM_S 12 +/* EFUSE_RD_USR_DATA_FAIL : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the user data is reliable 1: Means + that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_USR_DATA_FAIL (BIT(11)) +#define EFUSE_RD_USR_DATA_FAIL_M (BIT(11)) +#define EFUSE_RD_USR_DATA_FAIL_V 0x1 +#define EFUSE_RD_USR_DATA_FAIL_S 11 +/* EFUSE_RD_USR_DATA_ERR_NUM : RO ;bitpos:[10:8] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_USR_DATA_ERR_NUM 0x00000007 +#define EFUSE_RD_USR_DATA_ERR_NUM_M ((EFUSE_RD_USR_DATA_ERR_NUM_V) << (EFUSE_RD_USR_DATA_ERR_NUM_S)) +#define EFUSE_RD_USR_DATA_ERR_NUM_V 0x7 +#define EFUSE_RD_USR_DATA_ERR_NUM_S 8 +/* EFUSE_RD_SYS_PART1_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of system part1 is reliable + 1: Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_SYS_PART1_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART1_FAIL_M (BIT(7)) +#define EFUSE_RD_SYS_PART1_FAIL_V 0x1 +#define EFUSE_RD_SYS_PART1_FAIL_S 7 +/* EFUSE_RD_SYS_PART1_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_SYS_PART1_NUM 0x00000007 +#define EFUSE_RD_SYS_PART1_NUM_M ((EFUSE_RD_SYS_PART1_NUM_V) << (EFUSE_RD_SYS_PART1_NUM_S)) +#define EFUSE_RD_SYS_PART1_NUM_V 0x7 +#define EFUSE_RD_SYS_PART1_NUM_S 4 +/* EFUSE_RD_MAC_SPI_8M_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of MAC_SPI_8M is reliable + 1: Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_MAC_SPI_8M_FAIL (BIT(3)) +#define EFUSE_RD_MAC_SPI_8M_FAIL_M (BIT(3)) +#define EFUSE_RD_MAC_SPI_8M_FAIL_V 0x1 +#define EFUSE_RD_MAC_SPI_8M_FAIL_S 3 +/* EFUSE_RD_MAC_SPI_8M_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_MAC_SPI_8M_ERR_NUM 0x00000007 +#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_M ((EFUSE_RD_MAC_SPI_8M_ERR_NUM_V) << (EFUSE_RD_MAC_SPI_8M_ERR_NUM_S)) +#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_V 0x7 +#define EFUSE_RD_MAC_SPI_8M_ERR_NUM_S 0 + +#define EFUSE_RD_RS_ERR1_REG (DR_REG_EFUSE_BASE + 0x1c4) +/* EFUSE_RD_SYS_PART2_FAIL : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of system part2 is reliable + 1: Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_SYS_PART2_FAIL (BIT(7)) +#define EFUSE_RD_SYS_PART2_FAIL_M (BIT(7)) +#define EFUSE_RD_SYS_PART2_FAIL_V 0x1 +#define EFUSE_RD_SYS_PART2_FAIL_S 7 +/* EFUSE_RD_SYS_PART2_NUM : RO ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_SYS_PART2_NUM 0x00000007 +#define EFUSE_RD_SYS_PART2_NUM_M ((EFUSE_RD_SYS_PART2_NUM_V) << (EFUSE_RD_SYS_PART2_NUM_S)) +#define EFUSE_RD_SYS_PART2_NUM_V 0x7 +#define EFUSE_RD_SYS_PART2_NUM_S 4 +/* EFUSE_RD_KEY5_FAIL : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: 0: Means no failure and that the data of KEY5 is reliable 1: + Means that programming user data failed and the number of error bytes is over 6.*/ +#define EFUSE_RD_KEY5_FAIL (BIT(3)) +#define EFUSE_RD_KEY5_FAIL_M (BIT(3)) +#define EFUSE_RD_KEY5_FAIL_V 0x1 +#define EFUSE_RD_KEY5_FAIL_S 3 +/* EFUSE_RD_KEY5_ERR_NUM : RO ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: The value of this signal means the number of error bytes.*/ +#define EFUSE_RD_KEY5_ERR_NUM 0x00000007 +#define EFUSE_RD_KEY5_ERR_NUM_M ((EFUSE_RD_KEY5_ERR_NUM_V) << (EFUSE_RD_KEY5_ERR_NUM_S)) +#define EFUSE_RD_KEY5_ERR_NUM_V 0x7 +#define EFUSE_RD_KEY5_ERR_NUM_S 0 + +#define EFUSE_CLK_REG (DR_REG_EFUSE_BASE + 0x1c8) +/* EFUSE_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit and force to enable clock signal of eFuse memory.*/ +#define EFUSE_CLK_EN (BIT(16)) +#define EFUSE_CLK_EN_M (BIT(16)) +#define EFUSE_CLK_EN_V 0x1 +#define EFUSE_CLK_EN_S 16 +/* EFUSE_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to force eFuse SRAM into working mode.*/ +#define EFUSE_MEM_FORCE_PU (BIT(2)) +#define EFUSE_MEM_FORCE_PU_M (BIT(2)) +#define EFUSE_MEM_FORCE_PU_V 0x1 +#define EFUSE_MEM_FORCE_PU_S 2 +/* EFUSE_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: Set this bit and force to activate clock signal of eFuse SRAM.*/ +#define EFUSE_MEM_CLK_FORCE_ON (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_M (BIT(1)) +#define EFUSE_MEM_CLK_FORCE_ON_V 0x1 +#define EFUSE_MEM_CLK_FORCE_ON_S 1 +/* EFUSE_MEM_FORCE_PD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to force eFuse SRAM into power-saving mode.*/ +#define EFUSE_MEM_FORCE_PD (BIT(0)) +#define EFUSE_MEM_FORCE_PD_M (BIT(0)) +#define EFUSE_MEM_FORCE_PD_V 0x1 +#define EFUSE_MEM_FORCE_PD_S 0 + +#define EFUSE_CONF_REG (DR_REG_EFUSE_BASE + 0x1cc) +/* EFUSE_OP_CODE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: 0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ +#define EFUSE_OP_CODE 0x0000FFFF +#define EFUSE_OP_CODE_M ((EFUSE_OP_CODE_V) << (EFUSE_OP_CODE_S)) +#define EFUSE_OP_CODE_V 0xFFFF +#define EFUSE_OP_CODE_S 0 + +#define EFUSE_STATUS_REG (DR_REG_EFUSE_BASE + 0x1d0) +/* EFUSE_REPEAT_ERR_CNT : RO ;bitpos:[17:10] ;default: 8'h0 ; */ +/*description: Indicates the number of error bits during programming BLOCK0.*/ +#define EFUSE_REPEAT_ERR_CNT 0x000000FF +#define EFUSE_REPEAT_ERR_CNT_M ((EFUSE_REPEAT_ERR_CNT_V) << (EFUSE_REPEAT_ERR_CNT_S)) +#define EFUSE_REPEAT_ERR_CNT_V 0xFF +#define EFUSE_REPEAT_ERR_CNT_S 10 +/* EFUSE_OTP_VDDQ_IS_SW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The value of OTP_VDDQ_IS_SW.*/ +#define EFUSE_OTP_VDDQ_IS_SW (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_M (BIT(9)) +#define EFUSE_OTP_VDDQ_IS_SW_V 0x1 +#define EFUSE_OTP_VDDQ_IS_SW_S 9 +/* EFUSE_OTP_PGENB_SW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The value of OTP_PGENB_SW.*/ +#define EFUSE_OTP_PGENB_SW (BIT(8)) +#define EFUSE_OTP_PGENB_SW_M (BIT(8)) +#define EFUSE_OTP_PGENB_SW_V 0x1 +#define EFUSE_OTP_PGENB_SW_S 8 +/* EFUSE_OTP_CSB_SW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The value of OTP_CSB_SW.*/ +#define EFUSE_OTP_CSB_SW (BIT(7)) +#define EFUSE_OTP_CSB_SW_M (BIT(7)) +#define EFUSE_OTP_CSB_SW_V 0x1 +#define EFUSE_OTP_CSB_SW_S 7 +/* EFUSE_OTP_STROBE_SW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The value of OTP_STROBE_SW.*/ +#define EFUSE_OTP_STROBE_SW (BIT(6)) +#define EFUSE_OTP_STROBE_SW_M (BIT(6)) +#define EFUSE_OTP_STROBE_SW_V 0x1 +#define EFUSE_OTP_STROBE_SW_S 6 +/* EFUSE_OTP_VDDQ_C_SYNC2 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The value of OTP_VDDQ_C_SYNC2.*/ +#define EFUSE_OTP_VDDQ_C_SYNC2 (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_M (BIT(5)) +#define EFUSE_OTP_VDDQ_C_SYNC2_V 0x1 +#define EFUSE_OTP_VDDQ_C_SYNC2_S 5 +/* EFUSE_OTP_LOAD_SW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The value of OTP_LOAD_SW.*/ +#define EFUSE_OTP_LOAD_SW (BIT(4)) +#define EFUSE_OTP_LOAD_SW_M (BIT(4)) +#define EFUSE_OTP_LOAD_SW_V 0x1 +#define EFUSE_OTP_LOAD_SW_S 4 +/* EFUSE_STATE : RO ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: Indicates the state of the eFuse state machine.*/ +#define EFUSE_STATE 0x0000000F +#define EFUSE_STATE_M ((EFUSE_STATE_V) << (EFUSE_STATE_S)) +#define EFUSE_STATE_V 0xF +#define EFUSE_STATE_S 0 + +#define EFUSE_CMD_REG (DR_REG_EFUSE_BASE + 0x1d4) +/* EFUSE_BLK_NUM : R/W ;bitpos:[5:2] ;default: 4'h0 ; */ +/*description: The serial number of the block to be programmed. Value 0-10 corresponds + to block number 0-10 respectively.*/ +#define EFUSE_BLK_NUM 0x0000000F +#define EFUSE_BLK_NUM_M ((EFUSE_BLK_NUM_V) << (EFUSE_BLK_NUM_S)) +#define EFUSE_BLK_NUM_V 0xF +#define EFUSE_BLK_NUM_S 2 +/* EFUSE_PGM_CMD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to send programming command.*/ +#define EFUSE_PGM_CMD (BIT(1)) +#define EFUSE_PGM_CMD_M (BIT(1)) +#define EFUSE_PGM_CMD_V 0x1 +#define EFUSE_PGM_CMD_S 1 +/* EFUSE_READ_CMD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to send read command.*/ +#define EFUSE_READ_CMD (BIT(0)) +#define EFUSE_READ_CMD_M (BIT(0)) +#define EFUSE_READ_CMD_V 0x1 +#define EFUSE_READ_CMD_S 0 + +#define EFUSE_INT_RAW_REG (DR_REG_EFUSE_BASE + 0x1d8) +/* EFUSE_PGM_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_RAW (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_RAW_V 0x1 +#define EFUSE_PGM_DONE_INT_RAW_S 1 +/* EFUSE_READ_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_RAW (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_M (BIT(0)) +#define EFUSE_READ_DONE_INT_RAW_V 0x1 +#define EFUSE_READ_DONE_INT_RAW_S 0 + +#define EFUSE_INT_ST_REG (DR_REG_EFUSE_BASE + 0x1dc) +/* EFUSE_PGM_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_ST (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ST_V 0x1 +#define EFUSE_PGM_DONE_INT_ST_S 1 +/* EFUSE_READ_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_ST (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ST_V 0x1 +#define EFUSE_READ_DONE_INT_ST_S 0 + +#define EFUSE_INT_ENA_REG (DR_REG_EFUSE_BASE + 0x1e0) +/* EFUSE_PGM_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_ENA (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_ENA_V 0x1 +#define EFUSE_PGM_DONE_INT_ENA_S 1 +/* EFUSE_READ_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_ENA (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_M (BIT(0)) +#define EFUSE_READ_DONE_INT_ENA_V 0x1 +#define EFUSE_READ_DONE_INT_ENA_S 0 + +#define EFUSE_INT_CLR_REG (DR_REG_EFUSE_BASE + 0x1e4) +/* EFUSE_PGM_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear signal for pgm_done interrupt.*/ +#define EFUSE_PGM_DONE_INT_CLR (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_M (BIT(1)) +#define EFUSE_PGM_DONE_INT_CLR_V 0x1 +#define EFUSE_PGM_DONE_INT_CLR_S 1 +/* EFUSE_READ_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear signal for read_done interrupt.*/ +#define EFUSE_READ_DONE_INT_CLR (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_M (BIT(0)) +#define EFUSE_READ_DONE_INT_CLR_V 0x1 +#define EFUSE_READ_DONE_INT_CLR_S 0 + +#define EFUSE_DAC_CONF_REG (DR_REG_EFUSE_BASE + 0x1e8) +/* EFUSE_OE_CLR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Reduces the power supply of the programming voltage.*/ +#define EFUSE_OE_CLR (BIT(17)) +#define EFUSE_OE_CLR_M (BIT(17)) +#define EFUSE_OE_CLR_V 0x1 +#define EFUSE_OE_CLR_S 17 +/* EFUSE_DAC_NUM : R/W ;bitpos:[16:9] ;default: 8'd255 ; */ +/*description: Controls the rising period of the programming voltage.*/ +#define EFUSE_DAC_NUM 0x000000FF +#define EFUSE_DAC_NUM_M ((EFUSE_DAC_NUM_V) << (EFUSE_DAC_NUM_S)) +#define EFUSE_DAC_NUM_V 0xFF +#define EFUSE_DAC_NUM_S 9 +/* EFUSE_DAC_CLK_PAD_SEL : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Don't care.*/ +#define EFUSE_DAC_CLK_PAD_SEL (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_M (BIT(8)) +#define EFUSE_DAC_CLK_PAD_SEL_V 0x1 +#define EFUSE_DAC_CLK_PAD_SEL_S 8 +/* EFUSE_DAC_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'h28 ; */ +/*description: Controls the division factor of the rising clock of the programming voltage.*/ +#define EFUSE_DAC_CLK_DIV 0x000000FF +#define EFUSE_DAC_CLK_DIV_M ((EFUSE_DAC_CLK_DIV_V) << (EFUSE_DAC_CLK_DIV_S)) +#define EFUSE_DAC_CLK_DIV_V 0xFF +#define EFUSE_DAC_CLK_DIV_S 0 + +#define EFUSE_RD_TIM_CONF_REG (DR_REG_EFUSE_BASE + 0x1ec) +/* EFUSE_READ_INIT_NUM : R/W ;bitpos:[31:24] ;default: 8'h12 ; */ +/*description: Configures the initial read time of eFuse.*/ +#define EFUSE_READ_INIT_NUM 0x000000FF +#define EFUSE_READ_INIT_NUM_M ((EFUSE_READ_INIT_NUM_V) << (EFUSE_READ_INIT_NUM_S)) +#define EFUSE_READ_INIT_NUM_V 0xFF +#define EFUSE_READ_INIT_NUM_S 24 +/* EFUSE_TSUR_A : R/W ;bitpos:[23:16] ;default: 8'h1 ; */ +/*description: Configures the setup time of read operation.*/ +#define EFUSE_TSUR_A 0x000000FF +#define EFUSE_TSUR_A_M ((EFUSE_TSUR_A_V) << (EFUSE_TSUR_A_S)) +#define EFUSE_TSUR_A_V 0xFF +#define EFUSE_TSUR_A_S 16 +/* EFUSE_TRD : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: Configures the length of pulse of read operation.*/ +#define EFUSE_TRD 0x000000FF +#define EFUSE_TRD_M ((EFUSE_TRD_V) << (EFUSE_TRD_S)) +#define EFUSE_TRD_V 0xFF +#define EFUSE_TRD_S 8 +/* EFUSE_THR_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ +/*description: Configures the hold time of read operation.*/ +#define EFUSE_THR_A 0x000000FF +#define EFUSE_THR_A_M ((EFUSE_THR_A_V) << (EFUSE_THR_A_S)) +#define EFUSE_THR_A_V 0xFF +#define EFUSE_THR_A_S 0 + +#define EFUSE_WR_TIM_CONF0_REG (DR_REG_EFUSE_BASE + 0x1F0) +/* EFUSE_TPGM : R/W ;bitpos:[31:16] ;default: 16'hc8 ; */ +/*description: Configures the length of pulse during programming 1 to eFuse.*/ +#define EFUSE_TPGM 0x0000FFFF +#define EFUSE_TPGM_M ((EFUSE_TPGM_V) << (EFUSE_TPGM_S)) +#define EFUSE_TPGM_V 0xFFFF +#define EFUSE_TPGM_S 16 +/* EFUSE_TPGM_INACTIVE : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: Configures the length of pulse during programming 0 to eFuse.*/ +#define EFUSE_TPGM_INACTIVE 0x000000FF +#define EFUSE_TPGM_INACTIVE_M ((EFUSE_TPGM_INACTIVE_V) << (EFUSE_TPGM_INACTIVE_S)) +#define EFUSE_TPGM_INACTIVE_V 0xFF +#define EFUSE_TPGM_INACTIVE_S 8 +/* EFUSE_THP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ +/*description: Configures the hold time of programming operation.*/ +#define EFUSE_THP_A 0x000000FF +#define EFUSE_THP_A_M ((EFUSE_THP_A_V) << (EFUSE_THP_A_S)) +#define EFUSE_THP_A_V 0xFF +#define EFUSE_THP_A_S 0 + +#define EFUSE_WR_TIM_CONF1_REG (DR_REG_EFUSE_BASE + 0x1F4) +/* EFUSE_PWR_ON_NUM : R/W ;bitpos:[23:8] ;default: 16'h2880 ; */ +/*description: Configures the power up time for VDDQ.*/ +#define EFUSE_PWR_ON_NUM 0x0000FFFF +#define EFUSE_PWR_ON_NUM_M ((EFUSE_PWR_ON_NUM_V) << (EFUSE_PWR_ON_NUM_S)) +#define EFUSE_PWR_ON_NUM_V 0xFFFF +#define EFUSE_PWR_ON_NUM_S 8 +/* EFUSE_TSUP_A : R/W ;bitpos:[7:0] ;default: 8'h1 ; */ +/*description: Configures the setup time of programming operation.*/ +#define EFUSE_TSUP_A 0x000000FF +#define EFUSE_TSUP_A_M ((EFUSE_TSUP_A_V) << (EFUSE_TSUP_A_S)) +#define EFUSE_TSUP_A_V 0xFF +#define EFUSE_TSUP_A_S 0 + +#define EFUSE_WR_TIM_CONF2_REG (DR_REG_EFUSE_BASE + 0x1F8) +/* EFUSE_PWR_OFF_NUM : R/W ;bitpos:[15:0] ;default: 16'h190 ; */ +/*description: Configures the power outage time for VDDQ.*/ +#define EFUSE_PWR_OFF_NUM 0x0000FFFF +#define EFUSE_PWR_OFF_NUM_M ((EFUSE_PWR_OFF_NUM_V) << (EFUSE_PWR_OFF_NUM_S)) +#define EFUSE_PWR_OFF_NUM_V 0xFFFF +#define EFUSE_PWR_OFF_NUM_S 0 + +#define EFUSE_DATE_REG (DR_REG_EFUSE_BASE + 0x1FC) +/* EFUSE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003310 ; */ +/*description: Stores eFuse version.*/ +#define EFUSE_DATE 0x0FFFFFFF +#define EFUSE_DATE_M ((EFUSE_DATE_V) << (EFUSE_DATE_S)) +#define EFUSE_DATE_V 0xFFFFFFF +#define EFUSE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/efuse_struct.h b/components/soc/soc/esp32s3/include/soc/efuse_struct.h new file mode 100644 index 000000000..e4fd4a65f --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/efuse_struct.h @@ -0,0 +1,294 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; + uint32_t reserved_c; + uint32_t reserved_10; + uint32_t reserved_14; + uint32_t reserved_18; + uint32_t reserved_1c; + uint32_t reserved_20; + uint32_t reserved_24; + uint32_t reserved_28; + uint32_t reserved_2c; + uint32_t reserved_30; + uint32_t reserved_34; + uint32_t reserved_38; + uint32_t reserved_3c; + uint32_t reserved_40; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + union { + struct { + uint32_t rd_mac_spi_8m_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_mac_spi_8m_fail: 1; /*0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t rd_sys_part1_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_sys_part1_fail: 1; /*0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t rd_usr_data_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_usr_data_fail: 1; /*0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t rd_key0_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_key0_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t rd_key1_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_key1_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t rd_key2_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_key2_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t rd_key3_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_key3_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + uint32_t rd_key4_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_key4_fail: 1; /*0: Means no failure and that the data of key$n is reliable 1: Means that programming key$n failed and the number of error bytes is over 6.*/ + }; + uint32_t val; + } rd_rs_err0; + union { + struct { + uint32_t rd_key5_err_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_key5_fail: 1; /*0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t rd_sys_part2_num: 3; /*The value of this signal means the number of error bytes.*/ + uint32_t rd_sys_part2_fail: 1; /*0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.*/ + uint32_t reserved8: 24; /*Reserved.*/ + }; + uint32_t val; + } rd_rs_err1; + union { + struct { + uint32_t mem_force_pd: 1; /*Set this bit to force eFuse SRAM into power-saving mode.*/ + uint32_t mem_clk_force_on: 1; /*Set this bit and force to activate clock signal of eFuse SRAM.*/ + uint32_t mem_force_pu: 1; /*Set this bit to force eFuse SRAM into working mode.*/ + uint32_t reserved3: 13; /*Reserved.*/ + uint32_t clk_en: 1; /*Set this bit and force to enable clock signal of eFuse memory.*/ + uint32_t reserved17: 15; /*Reserved.*/ + }; + uint32_t val; + } clk; + union { + struct { + uint32_t op_code: 16; /*0x5A5A: Operate programming command 0x5AA5: Operate read command.*/ + uint32_t reserved16: 16; /*Reserved.*/ + }; + uint32_t val; + } conf; + union { + struct { + uint32_t state: 4; /*Indicates the state of the eFuse state machine.*/ + uint32_t otp_load_sw: 1; /*The value of OTP_LOAD_SW.*/ + uint32_t otp_vddq_c_sync2: 1; /*The value of OTP_VDDQ_C_SYNC2.*/ + uint32_t otp_strobe_sw: 1; /*The value of OTP_STROBE_SW.*/ + uint32_t otp_csb_sw: 1; /*The value of OTP_CSB_SW.*/ + uint32_t otp_pgenb_sw: 1; /*The value of OTP_PGENB_SW.*/ + uint32_t otp_vddq_is_sw: 1; /*The value of OTP_VDDQ_IS_SW.*/ + uint32_t repeat_err_cnt: 8; /*Indicates the number of error bits during programming BLOCK0.*/ + uint32_t reserved18: 14; /*Reserved.*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t read_cmd: 1; /*Set this bit to send read command.*/ + uint32_t pgm_cmd: 1; /*Set this bit to send programming command.*/ + uint32_t blk_num: 4; /*The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10 respectively.*/ + uint32_t reserved6: 26; /*Reserved.*/ + }; + uint32_t val; + } cmd; + union { + struct { + uint32_t read_done: 1; /*The raw bit signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The raw bit signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t read_done: 1; /*The status signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The status signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t read_done: 1; /*The enable signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The enable signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t read_done: 1; /*The clear signal for read_done interrupt.*/ + uint32_t pgm_done: 1; /*The clear signal for pgm_done interrupt.*/ + uint32_t reserved2: 30; /*Reserved.*/ + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t dac_clk_div: 8; /*Controls the division factor of the rising clock of the programming voltage.*/ + uint32_t dac_clk_pad_sel: 1; /*Don't care.*/ + uint32_t dac_num: 8; /*Controls the rising period of the programming voltage.*/ + uint32_t oe_clr: 1; /*Reduces the power supply of the programming voltage.*/ + uint32_t reserved18: 14; /*Reserved.*/ + }; + uint32_t val; + } dac_conf; + union { + struct { + uint32_t thr_a: 8; /*Configures the hold time of read operation.*/ + uint32_t trd: 8; /*Configures the length of pulse of read operation.*/ + uint32_t tsur_a: 8; /*Configures the setup time of read operation.*/ + uint32_t read_init_num: 8; /*Configures the initial read time of eFuse.*/ + }; + uint32_t val; + } rd_tim_conf; + union { + struct { + uint32_t thp_a: 8; /*Configures the hold time of programming operation.*/ + uint32_t tpgm_inactive: 8; /*Configures the length of pulse during programming 0 to eFuse.*/ + uint32_t tpgm: 16; /*Configures the length of pulse during programming 1 to eFuse.*/ + }; + uint32_t val; + } wr_tim_conf0; + union { + struct { + uint32_t tsup_a: 8; /*Configures the setup time of programming operation.*/ + uint32_t pwr_on_num: 16; /*Configures the power up time for VDDQ.*/ + uint32_t reserved24: 8; /*Reserved.*/ + }; + uint32_t val; + } wr_tim_conf1; + union { + struct { + uint32_t pwr_off_num: 16; /*Configures the power outage time for VDDQ.*/ + uint32_t reserved16: 16; /*Reserved.*/ + }; + uint32_t val; + } wr_tim_conf2; + union { + struct { + uint32_t date: 28; /*Stores eFuse version.*/ + uint32_t reserved28: 4; /*Reserved.*/ + }; + uint32_t val; + } date; +} efuse_dev_t; + +extern efuse_dev_t EFUSE; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/extmem_reg.h b/components/soc/soc/esp32s3/include/soc/extmem_reg.h new file mode 100644 index 000000000..a9d9e2bf5 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/extmem_reg.h @@ -0,0 +1,1609 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define EXTMEM_DCACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x000) +/* EXTMEM_DCACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ +#define EXTMEM_DCACHE_BLOCKSIZE_MODE (BIT(3)) +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_M (BIT(3)) +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_V 0x1 +#define EXTMEM_DCACHE_BLOCKSIZE_MODE_S 3 +/* EXTMEM_DCACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache memory size.0: 32KB 1: 64KB*/ +#define EXTMEM_DCACHE_SIZE_MODE (BIT(2)) +#define EXTMEM_DCACHE_SIZE_MODE_M (BIT(2)) +#define EXTMEM_DCACHE_SIZE_MODE_V 0x1 +#define EXTMEM_DCACHE_SIZE_MODE_S 2 +/* EXTMEM_DCACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ +#define EXTMEM_DCACHE_ENABLE (BIT(0)) +#define EXTMEM_DCACHE_ENABLE_M (BIT(0)) +#define EXTMEM_DCACHE_ENABLE_V 0x1 +#define EXTMEM_DCACHE_ENABLE_S 0 + +#define EXTMEM_DCACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x004) +/* EXTMEM_DCACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable core1 dbus 0: enable 1: disable*/ +#define EXTMEM_DCACHE_SHUT_CORE1_BUS (BIT(1)) +#define EXTMEM_DCACHE_SHUT_CORE1_BUS_M (BIT(1)) +#define EXTMEM_DCACHE_SHUT_CORE1_BUS_V 0x1 +#define EXTMEM_DCACHE_SHUT_CORE1_BUS_S 1 +/* EXTMEM_DCACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable core0 dbus 0: enable 1: disable*/ +#define EXTMEM_DCACHE_SHUT_CORE0_BUS (BIT(0)) +#define EXTMEM_DCACHE_SHUT_CORE0_BUS_M (BIT(0)) +#define EXTMEM_DCACHE_SHUT_CORE0_BUS_V 0x1 +#define EXTMEM_DCACHE_SHUT_CORE0_BUS_S 0 + +#define EXTMEM_DCACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x008) +/* EXTMEM_DCACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd + 1: power up*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PU_S 2 +/* EXTMEM_DCACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd + 1: power down*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_PD_S 1 +/* EXTMEM_DCACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of dcache tag memory. 1: + close gating 0: open clock gating.*/ +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_DCACHE_TAG_MEM_FORCE_ON_S 0 + +#define EXTMEM_DCACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x00C) +/* EXTMEM_DCACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section of prelock function.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN (BIT(1)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_M (BIT(1)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_V 0x1 +#define EXTMEM_DCACHE_PRELOCK_SCT1_EN_S 1 +/* EXTMEM_DCACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section of prelock function.*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN (BIT(0)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_M (BIT(0)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_V 0x1 +#define EXTMEM_DCACHE_PRELOCK_SCT0_EN_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x010) +/* EXTMEM_DCACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to configure the first start virtual address + of data prelock which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x014) +/* EXTMEM_DCACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to configure the second start virtual address + of data prelock which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x018) +/* EXTMEM_DCACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The bits are used to configure the first length of data locking + which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/ +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE 0x0000FFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_V 0xFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT0_SIZE_S 16 +/* EXTMEM_DCACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the second length of data locking + which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/ +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE 0x0000FFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S)) +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_V 0xFFFF +#define EXTMEM_DCACHE_PRELOCK_SCT1_SIZE_S 0 + +#define EXTMEM_DCACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x01C) +/* EXTMEM_DCACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate unlock/lock operation is finished.*/ +#define EXTMEM_DCACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_DCACHE_LOCK_DONE_M (BIT(2)) +#define EXTMEM_DCACHE_LOCK_DONE_V 0x1 +#define EXTMEM_DCACHE_LOCK_DONE_S 2 +/* EXTMEM_DCACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable unlock operation. It will be cleared + by hardware after unlock operation done.*/ +#define EXTMEM_DCACHE_UNLOCK_ENA (BIT(1)) +#define EXTMEM_DCACHE_UNLOCK_ENA_M (BIT(1)) +#define EXTMEM_DCACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_DCACHE_UNLOCK_ENA_S 1 +/* EXTMEM_DCACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable lock operation. It will be cleared + by hardware after lock operation done.*/ +#define EXTMEM_DCACHE_LOCK_ENA (BIT(0)) +#define EXTMEM_DCACHE_LOCK_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_LOCK_ENA_V 0x1 +#define EXTMEM_DCACHE_LOCK_ENA_S 0 + +#define EXTMEM_DCACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x020) +/* EXTMEM_DCACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/ +#define EXTMEM_DCACHE_LOCK_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_LOCK_ADDR_M ((EXTMEM_DCACHE_LOCK_ADDR_V)<<(EXTMEM_DCACHE_LOCK_ADDR_S)) +#define EXTMEM_DCACHE_LOCK_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_LOCK_ADDR_S 0 + +#define EXTMEM_DCACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x024) +/* EXTMEM_DCACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the length for lock operations. + The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/ +#define EXTMEM_DCACHE_LOCK_SIZE 0x0000FFFF +#define EXTMEM_DCACHE_LOCK_SIZE_M ((EXTMEM_DCACHE_LOCK_SIZE_V)<<(EXTMEM_DCACHE_LOCK_SIZE_S)) +#define EXTMEM_DCACHE_LOCK_SIZE_V 0xFFFF +#define EXTMEM_DCACHE_LOCK_SIZE_S 0 + +#define EXTMEM_DCACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x028) +/* EXTMEM_DCACHE_SYNC_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate clean/writeback/invalidate operation is finished.*/ +#define EXTMEM_DCACHE_SYNC_DONE (BIT(3)) +#define EXTMEM_DCACHE_SYNC_DONE_M (BIT(3)) +#define EXTMEM_DCACHE_SYNC_DONE_V 0x1 +#define EXTMEM_DCACHE_SYNC_DONE_S 3 +/* EXTMEM_DCACHE_CLEAN_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable clean operation. It will be cleared + by hardware after clean operation done.*/ +#define EXTMEM_DCACHE_CLEAN_ENA (BIT(2)) +#define EXTMEM_DCACHE_CLEAN_ENA_M (BIT(2)) +#define EXTMEM_DCACHE_CLEAN_ENA_V 0x1 +#define EXTMEM_DCACHE_CLEAN_ENA_S 2 +/* EXTMEM_DCACHE_WRITEBACK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable writeback operation. It will be cleared + by hardware after writeback operation done.*/ +#define EXTMEM_DCACHE_WRITEBACK_ENA (BIT(1)) +#define EXTMEM_DCACHE_WRITEBACK_ENA_M (BIT(1)) +#define EXTMEM_DCACHE_WRITEBACK_ENA_V 0x1 +#define EXTMEM_DCACHE_WRITEBACK_ENA_S 1 +/* EXTMEM_DCACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable invalidate operation. It will be cleared + by hardware after invalidate operation done.*/ +#define EXTMEM_DCACHE_INVALIDATE_ENA (BIT(0)) +#define EXTMEM_DCACHE_INVALIDATE_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_DCACHE_INVALIDATE_ENA_S 0 + +#define EXTMEM_DCACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x02C) +/* EXTMEM_DCACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/ +#define EXTMEM_DCACHE_SYNC_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_SYNC_ADDR_M ((EXTMEM_DCACHE_SYNC_ADDR_V)<<(EXTMEM_DCACHE_SYNC_ADDR_S)) +#define EXTMEM_DCACHE_SYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_SYNC_ADDR_S 0 + +#define EXTMEM_DCACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x030) +/* EXTMEM_DCACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ +/*description: The bits are used to configure the length for sync operations. + The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/ +#define EXTMEM_DCACHE_SYNC_SIZE 0x007FFFFF +#define EXTMEM_DCACHE_SYNC_SIZE_M ((EXTMEM_DCACHE_SYNC_SIZE_V)<<(EXTMEM_DCACHE_SYNC_SIZE_S)) +#define EXTMEM_DCACHE_SYNC_SIZE_V 0x7FFFFF +#define EXTMEM_DCACHE_SYNC_SIZE_S 0 + +#define EXTMEM_DCACHE_OCCUPY_CTRL_REG (DR_REG_EXTMEM_BASE + 0x034) +/* EXTMEM_DCACHE_OCCUPY_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate occupy operation is finished.*/ +#define EXTMEM_DCACHE_OCCUPY_DONE (BIT(1)) +#define EXTMEM_DCACHE_OCCUPY_DONE_M (BIT(1)) +#define EXTMEM_DCACHE_OCCUPY_DONE_V 0x1 +#define EXTMEM_DCACHE_OCCUPY_DONE_S 1 +/* EXTMEM_DCACHE_OCCUPY_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable occupy operation. It will be cleared + by hardware after issuing Auot-Invalidate Operation.*/ +#define EXTMEM_DCACHE_OCCUPY_ENA (BIT(0)) +#define EXTMEM_DCACHE_OCCUPY_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_OCCUPY_ENA_V 0x1 +#define EXTMEM_DCACHE_OCCUPY_ENA_S 0 + +#define EXTMEM_DCACHE_OCCUPY_ADDR_REG (DR_REG_EXTMEM_BASE + 0x038) +/* EXTMEM_DCACHE_OCCUPY_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/ +#define EXTMEM_DCACHE_OCCUPY_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_OCCUPY_ADDR_M ((EXTMEM_DCACHE_OCCUPY_ADDR_V)<<(EXTMEM_DCACHE_OCCUPY_ADDR_S)) +#define EXTMEM_DCACHE_OCCUPY_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_OCCUPY_ADDR_S 0 + +#define EXTMEM_DCACHE_OCCUPY_SIZE_REG (DR_REG_EXTMEM_BASE + 0x03C) +/* EXTMEM_DCACHE_OCCUPY_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the length for occupy operation. + The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/ +#define EXTMEM_DCACHE_OCCUPY_SIZE 0x0000FFFF +#define EXTMEM_DCACHE_OCCUPY_SIZE_M ((EXTMEM_DCACHE_OCCUPY_SIZE_V)<<(EXTMEM_DCACHE_OCCUPY_SIZE_S)) +#define EXTMEM_DCACHE_OCCUPY_SIZE_V 0xFFFF +#define EXTMEM_DCACHE_OCCUPY_SIZE_S 0 + +#define EXTMEM_DCACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x040) +/* EXTMEM_DCACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to configure the direction of preload operation. + 1: descending 0: ascending.*/ +#define EXTMEM_DCACHE_PRELOAD_ORDER (BIT(2)) +#define EXTMEM_DCACHE_PRELOAD_ORDER_M (BIT(2)) +#define EXTMEM_DCACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_ORDER_S 2 +/* EXTMEM_DCACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate preload operation is finished.*/ +#define EXTMEM_DCACHE_PRELOAD_DONE (BIT(1)) +#define EXTMEM_DCACHE_PRELOAD_DONE_M (BIT(1)) +#define EXTMEM_DCACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_DONE_S 1 +/* EXTMEM_DCACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable preload operation. It will be cleared + by hardware after preload operation done.*/ +#define EXTMEM_DCACHE_PRELOAD_ENA (BIT(0)) +#define EXTMEM_DCACHE_PRELOAD_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_ENA_S 0 + +#define EXTMEM_DCACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x044) +/* EXTMEM_DCACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_DCACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOAD_ADDR_M ((EXTMEM_DCACHE_PRELOAD_ADDR_V)<<(EXTMEM_DCACHE_PRELOAD_ADDR_S)) +#define EXTMEM_DCACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_PRELOAD_ADDR_S 0 + +#define EXTMEM_DCACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x048) +/* EXTMEM_DCACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the length for preload operation. + The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/ +#define EXTMEM_DCACHE_PRELOAD_SIZE 0x0000FFFF +#define EXTMEM_DCACHE_PRELOAD_SIZE_M ((EXTMEM_DCACHE_PRELOAD_SIZE_V)<<(EXTMEM_DCACHE_PRELOAD_SIZE_S)) +#define EXTMEM_DCACHE_PRELOAD_SIZE_V 0xFFFF +#define EXTMEM_DCACHE_PRELOAD_SIZE_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x04C) +/* EXTMEM_DCACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ +/*description: The bits are used to configure the numbers of the cache block + for the issuing autoload operation.*/ +#define EXTMEM_DCACHE_AUTOLOAD_SIZE 0x00000003 +#define EXTMEM_DCACHE_AUTOLOAD_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SIZE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SIZE_V 0x3 +#define EXTMEM_DCACHE_AUTOLOAD_SIZE_S 7 +/* EXTMEM_DCACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ +/*description: The bits are used to configure trigger conditions for autoload. + 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ +#define EXTMEM_DCACHE_AUTOLOAD_RQST 0x00000003 +#define EXTMEM_DCACHE_AUTOLOAD_RQST_M ((EXTMEM_DCACHE_AUTOLOAD_RQST_V)<<(EXTMEM_DCACHE_AUTOLOAD_RQST_S)) +#define EXTMEM_DCACHE_AUTOLOAD_RQST_V 0x3 +#define EXTMEM_DCACHE_AUTOLOAD_RQST_S 5 +/* EXTMEM_DCACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bits are used to configure the direction of autoload. 1: + descending 0: ascending.*/ +#define EXTMEM_DCACHE_AUTOLOAD_ORDER (BIT(4)) +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_M (BIT(4)) +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_ORDER_S 4 +/* EXTMEM_DCACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate autoload operation is finished.*/ +#define EXTMEM_DCACHE_AUTOLOAD_DONE (BIT(3)) +#define EXTMEM_DCACHE_AUTOLOAD_DONE_M (BIT(3)) +#define EXTMEM_DCACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_DONE_S 3 +/* EXTMEM_DCACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable and disable autoload operation. It + is combined with dcache_autoload_done. 1: enable 0: disable.*/ +#define EXTMEM_DCACHE_AUTOLOAD_ENA (BIT(2)) +#define EXTMEM_DCACHE_AUTOLOAD_ENA_M (BIT(2)) +#define EXTMEM_DCACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_ENA_S 2 +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bits are used to enable the second section for autoload operation.*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA (BIT(1)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ENA_S 1 +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bits are used to enable the first section for autoload operation.*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA (BIT(0)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ENA_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x050) +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_ADDR_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x054) +/* EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: The bits are used to configure the length of the first section + for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT0_SIZE_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x058) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_ADDR_S 0 + +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x05C) +/* EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: The bits are used to configure the length of the second section + for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF +#define EXTMEM_DCACHE_AUTOLOAD_SCT1_SIZE_S 0 + +#define EXTMEM_ICACHE_CTRL_REG (DR_REG_EXTMEM_BASE + 0x060) +/* EXTMEM_ICACHE_BLOCKSIZE_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ +#define EXTMEM_ICACHE_BLOCKSIZE_MODE (BIT(3)) +#define EXTMEM_ICACHE_BLOCKSIZE_MODE_M (BIT(3)) +#define EXTMEM_ICACHE_BLOCKSIZE_MODE_V 0x1 +#define EXTMEM_ICACHE_BLOCKSIZE_MODE_S 3 +/* EXTMEM_ICACHE_SIZE_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache memory size.0: 16KB 1: 32KB*/ +#define EXTMEM_ICACHE_SIZE_MODE (BIT(2)) +#define EXTMEM_ICACHE_SIZE_MODE_M (BIT(2)) +#define EXTMEM_ICACHE_SIZE_MODE_V 0x1 +#define EXTMEM_ICACHE_SIZE_MODE_S 2 +/* EXTMEM_ICACHE_WAY_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to configure cache way mode.0: 4-way 1: 8-way*/ +#define EXTMEM_ICACHE_WAY_MODE (BIT(1)) +#define EXTMEM_ICACHE_WAY_MODE_M (BIT(1)) +#define EXTMEM_ICACHE_WAY_MODE_V 0x1 +#define EXTMEM_ICACHE_WAY_MODE_S 1 +/* EXTMEM_ICACHE_ENABLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to activate the data cache. 0: disable 1: enable*/ +#define EXTMEM_ICACHE_ENABLE (BIT(0)) +#define EXTMEM_ICACHE_ENABLE_M (BIT(0)) +#define EXTMEM_ICACHE_ENABLE_V 0x1 +#define EXTMEM_ICACHE_ENABLE_S 0 + +#define EXTMEM_ICACHE_CTRL1_REG (DR_REG_EXTMEM_BASE + 0x064) +/* EXTMEM_ICACHE_SHUT_CORE1_BUS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable core1 ibus 0: enable 1: disable*/ +#define EXTMEM_ICACHE_SHUT_CORE1_BUS (BIT(1)) +#define EXTMEM_ICACHE_SHUT_CORE1_BUS_M (BIT(1)) +#define EXTMEM_ICACHE_SHUT_CORE1_BUS_V 0x1 +#define EXTMEM_ICACHE_SHUT_CORE1_BUS_S 1 +/* EXTMEM_ICACHE_SHUT_CORE0_BUS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable core0 ibus 0: enable 1: disable*/ +#define EXTMEM_ICACHE_SHUT_CORE0_BUS (BIT(0)) +#define EXTMEM_ICACHE_SHUT_CORE0_BUS_M (BIT(0)) +#define EXTMEM_ICACHE_SHUT_CORE0_BUS_V 0x1 +#define EXTMEM_ICACHE_SHUT_CORE0_BUS_S 0 + +#define EXTMEM_ICACHE_TAG_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x068) +/* EXTMEM_ICACHE_TAG_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PU_S 2 +/* EXTMEM_ICACHE_TAG_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power icache tag memory down 0: follow rtc_lslp + 1: power down*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_PD_S 1 +/* EXTMEM_ICACHE_TAG_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of icache tag memory. + 1: close gating 0: open clock gating.*/ +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_V 0x1 +#define EXTMEM_ICACHE_TAG_MEM_FORCE_ON_S 0 + +#define EXTMEM_ICACHE_PRELOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x06C) +/* EXTMEM_ICACHE_PRELOCK_SCT1_EN : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: The bit is used to enable the second section of prelock function.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN (BIT(1)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_V 0x1 +#define EXTMEM_ICACHE_PRELOCK_SCT1_EN_S 1 +/* EXTMEM_ICACHE_PRELOCK_SCT0_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: The bit is used to enable the first section of prelock function.*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN (BIT(0)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_M (BIT(0)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_V 0x1 +#define EXTMEM_ICACHE_PRELOCK_SCT0_EN_S 0 + +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x070) +/* EXTMEM_ICACHE_PRELOCK_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to configure the first start virtual address + of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_ADDR_S 0 + +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x074) +/* EXTMEM_ICACHE_PRELOCK_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to configure the second start virtual address + of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_M ((EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_ADDR_S 0 + +#define EXTMEM_ICACHE_PRELOCK_SCT_SIZE_REG (DR_REG_EXTMEM_BASE + 0x078) +/* EXTMEM_ICACHE_PRELOCK_SCT0_SIZE : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: The bits are used to configure the first length of data locking + which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT0_SIZE_S 16 +/* EXTMEM_ICACHE_PRELOCK_SCT1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the second length of data locking + which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_M ((EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V)<<(EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S)) +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_PRELOCK_SCT1_SIZE_S 0 + +#define EXTMEM_ICACHE_LOCK_CTRL_REG (DR_REG_EXTMEM_BASE + 0x07C) +/* EXTMEM_ICACHE_LOCK_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate unlock/lock operation is finished.*/ +#define EXTMEM_ICACHE_LOCK_DONE (BIT(2)) +#define EXTMEM_ICACHE_LOCK_DONE_M (BIT(2)) +#define EXTMEM_ICACHE_LOCK_DONE_V 0x1 +#define EXTMEM_ICACHE_LOCK_DONE_S 2 +/* EXTMEM_ICACHE_UNLOCK_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable unlock operation. It will be cleared + by hardware after unlock operation done.*/ +#define EXTMEM_ICACHE_UNLOCK_ENA (BIT(1)) +#define EXTMEM_ICACHE_UNLOCK_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_UNLOCK_ENA_V 0x1 +#define EXTMEM_ICACHE_UNLOCK_ENA_S 1 +/* EXTMEM_ICACHE_LOCK_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable lock operation. It will be cleared + by hardware after lock operation done.*/ +#define EXTMEM_ICACHE_LOCK_ENA (BIT(0)) +#define EXTMEM_ICACHE_LOCK_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_LOCK_ENA_V 0x1 +#define EXTMEM_ICACHE_LOCK_ENA_S 0 + +#define EXTMEM_ICACHE_LOCK_ADDR_REG (DR_REG_EXTMEM_BASE + 0x080) +/* EXTMEM_ICACHE_LOCK_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ +#define EXTMEM_ICACHE_LOCK_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_LOCK_ADDR_M ((EXTMEM_ICACHE_LOCK_ADDR_V)<<(EXTMEM_ICACHE_LOCK_ADDR_S)) +#define EXTMEM_ICACHE_LOCK_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_LOCK_ADDR_S 0 + +#define EXTMEM_ICACHE_LOCK_SIZE_REG (DR_REG_EXTMEM_BASE + 0x084) +/* EXTMEM_ICACHE_LOCK_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the length for lock operations. + The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ +#define EXTMEM_ICACHE_LOCK_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_LOCK_SIZE_M ((EXTMEM_ICACHE_LOCK_SIZE_V)<<(EXTMEM_ICACHE_LOCK_SIZE_S)) +#define EXTMEM_ICACHE_LOCK_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_LOCK_SIZE_S 0 + +#define EXTMEM_ICACHE_SYNC_CTRL_REG (DR_REG_EXTMEM_BASE + 0x088) +/* EXTMEM_ICACHE_SYNC_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate invalidate operation is finished.*/ +#define EXTMEM_ICACHE_SYNC_DONE (BIT(1)) +#define EXTMEM_ICACHE_SYNC_DONE_M (BIT(1)) +#define EXTMEM_ICACHE_SYNC_DONE_V 0x1 +#define EXTMEM_ICACHE_SYNC_DONE_S 1 +/* EXTMEM_ICACHE_INVALIDATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable invalidate operation. It will be cleared + by hardware after invalidate operation done.*/ +#define EXTMEM_ICACHE_INVALIDATE_ENA (BIT(0)) +#define EXTMEM_ICACHE_INVALIDATE_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_INVALIDATE_ENA_V 0x1 +#define EXTMEM_ICACHE_INVALIDATE_ENA_S 0 + +#define EXTMEM_ICACHE_SYNC_ADDR_REG (DR_REG_EXTMEM_BASE + 0x08C) +/* EXTMEM_ICACHE_SYNC_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ +#define EXTMEM_ICACHE_SYNC_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_SYNC_ADDR_M ((EXTMEM_ICACHE_SYNC_ADDR_V)<<(EXTMEM_ICACHE_SYNC_ADDR_S)) +#define EXTMEM_ICACHE_SYNC_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_SYNC_ADDR_S 0 + +#define EXTMEM_ICACHE_SYNC_SIZE_REG (DR_REG_EXTMEM_BASE + 0x090) +/* EXTMEM_ICACHE_SYNC_SIZE : R/W ;bitpos:[22:0] ;default: 23'h0 ; */ +/*description: The bits are used to configure the length for sync operations. + The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ +#define EXTMEM_ICACHE_SYNC_SIZE 0x007FFFFF +#define EXTMEM_ICACHE_SYNC_SIZE_M ((EXTMEM_ICACHE_SYNC_SIZE_V)<<(EXTMEM_ICACHE_SYNC_SIZE_S)) +#define EXTMEM_ICACHE_SYNC_SIZE_V 0x7FFFFF +#define EXTMEM_ICACHE_SYNC_SIZE_S 0 + +#define EXTMEM_ICACHE_PRELOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x094) +/* EXTMEM_ICACHE_PRELOAD_ORDER : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to configure the direction of preload operation. + 1: descending 0: ascending.*/ +#define EXTMEM_ICACHE_PRELOAD_ORDER (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_ORDER_M (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_ORDER_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_ORDER_S 2 +/* EXTMEM_ICACHE_PRELOAD_DONE : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate preload operation is finished.*/ +#define EXTMEM_ICACHE_PRELOAD_DONE (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_DONE_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_DONE_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_DONE_S 1 +/* EXTMEM_ICACHE_PRELOAD_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable preload operation. It will be cleared + by hardware after preload operation done.*/ +#define EXTMEM_ICACHE_PRELOAD_ENA (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_ENA_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_ENA_S 0 + +#define EXTMEM_ICACHE_PRELOAD_ADDR_REG (DR_REG_EXTMEM_BASE + 0x098) +/* EXTMEM_ICACHE_PRELOAD_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address for + preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ +#define EXTMEM_ICACHE_PRELOAD_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOAD_ADDR_M ((EXTMEM_ICACHE_PRELOAD_ADDR_V)<<(EXTMEM_ICACHE_PRELOAD_ADDR_S)) +#define EXTMEM_ICACHE_PRELOAD_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_PRELOAD_ADDR_S 0 + +#define EXTMEM_ICACHE_PRELOAD_SIZE_REG (DR_REG_EXTMEM_BASE + 0x09C) +/* EXTMEM_ICACHE_PRELOAD_SIZE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: The bits are used to configure the length for preload operation. + The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ +#define EXTMEM_ICACHE_PRELOAD_SIZE 0x0000FFFF +#define EXTMEM_ICACHE_PRELOAD_SIZE_M ((EXTMEM_ICACHE_PRELOAD_SIZE_V)<<(EXTMEM_ICACHE_PRELOAD_SIZE_S)) +#define EXTMEM_ICACHE_PRELOAD_SIZE_V 0xFFFF +#define EXTMEM_ICACHE_PRELOAD_SIZE_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_CTRL_REG (DR_REG_EXTMEM_BASE + 0x0A0) +/* EXTMEM_ICACHE_AUTOLOAD_SIZE : R/W ;bitpos:[8:7] ;default: 2'h0 ; */ +/*description: The bits are used to configure the numbers of the cache block + for the issuing autoload operation.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SIZE 0x00000003 +#define EXTMEM_ICACHE_AUTOLOAD_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SIZE_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SIZE_V 0x3 +#define EXTMEM_ICACHE_AUTOLOAD_SIZE_S 7 +/* EXTMEM_ICACHE_AUTOLOAD_RQST : R/W ;bitpos:[6:5] ;default: 2'b0 ; */ +/*description: The bits are used to configure trigger conditions for autoload. + 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ +#define EXTMEM_ICACHE_AUTOLOAD_RQST 0x00000003 +#define EXTMEM_ICACHE_AUTOLOAD_RQST_M ((EXTMEM_ICACHE_AUTOLOAD_RQST_V)<<(EXTMEM_ICACHE_AUTOLOAD_RQST_S)) +#define EXTMEM_ICACHE_AUTOLOAD_RQST_V 0x3 +#define EXTMEM_ICACHE_AUTOLOAD_RQST_S 5 +/* EXTMEM_ICACHE_AUTOLOAD_ORDER : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bits are used to configure the direction of autoload. 1: + descending 0: ascending.*/ +#define EXTMEM_ICACHE_AUTOLOAD_ORDER (BIT(4)) +#define EXTMEM_ICACHE_AUTOLOAD_ORDER_M (BIT(4)) +#define EXTMEM_ICACHE_AUTOLOAD_ORDER_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_ORDER_S 4 +/* EXTMEM_ICACHE_AUTOLOAD_DONE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate autoload operation is finished.*/ +#define EXTMEM_ICACHE_AUTOLOAD_DONE (BIT(3)) +#define EXTMEM_ICACHE_AUTOLOAD_DONE_M (BIT(3)) +#define EXTMEM_ICACHE_AUTOLOAD_DONE_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_DONE_S 3 +/* EXTMEM_ICACHE_AUTOLOAD_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable and disable autoload operation. It + is combined with dcache_autoload_done. 1: enable 0: disable.*/ +#define EXTMEM_ICACHE_AUTOLOAD_ENA (BIT(2)) +#define EXTMEM_ICACHE_AUTOLOAD_ENA_M (BIT(2)) +#define EXTMEM_ICACHE_AUTOLOAD_ENA_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_ENA_S 2 +/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bits are used to enable the second section for autoload operation.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA (BIT(1)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ENA_S 1 +/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bits are used to enable the first section for autoload operation.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA (BIT(0)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_V 0x1 +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ENA_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_REG (DR_REG_EXTMEM_BASE + 0x0A4) +/* EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_ADDR_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_REG (DR_REG_EXTMEM_BASE + 0x0A8) +/* EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: The bits are used to configure the length of the first section + for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE 0x07FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_V 0x7FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT0_SIZE_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_REG (DR_REG_EXTMEM_BASE + 0x0AC) +/* EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of the + second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_V 0xFFFFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_ADDR_S 0 + +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_REG (DR_REG_EXTMEM_BASE + 0x0B0) +/* EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE : R/W ;bitpos:[26:0] ;default: 27'h0 ; */ +/*description: The bits are used to configure the length of the second section + for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE 0x07FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_M ((EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V)<<(EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S)) +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_V 0x7FFFFFF +#define EXTMEM_ICACHE_AUTOLOAD_SCT1_SIZE_S 0 + +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0B4) +/* EXTMEM_IBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'h44000000 ; */ +/*description: The bits are used to configure the start virtual address of ibus + to access flash. The register is used to give constraints to ibus access counter.*/ +#define EXTMEM_IBUS_TO_FLASH_START_VADDR 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_M ((EXTMEM_IBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_START_VADDR_S)) +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_START_VADDR_S 0 + +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0B8) +/* EXTMEM_IBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'h47ffffff ; */ +/*description: The bits are used to configure the end virtual address of ibus + to access flash. The register is used to give constraints to ibus access counter.*/ +#define EXTMEM_IBUS_TO_FLASH_END_VADDR 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_M ((EXTMEM_IBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_IBUS_TO_FLASH_END_VADDR_S)) +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF +#define EXTMEM_IBUS_TO_FLASH_END_VADDR_S 0 + +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0BC) +/* EXTMEM_DBUS_TO_FLASH_START_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the start virtual address of dbus + to access flash. The register is used to give constraints to dbus access counter.*/ +#define EXTMEM_DBUS_TO_FLASH_START_VADDR 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_M ((EXTMEM_DBUS_TO_FLASH_START_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_START_VADDR_S)) +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_V 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_START_VADDR_S 0 + +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_REG (DR_REG_EXTMEM_BASE + 0x0C0) +/* EXTMEM_DBUS_TO_FLASH_END_VADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The bits are used to configure the end virtual address of dbus + to access flash. The register is used to give constraints to dbus access counter.*/ +#define EXTMEM_DBUS_TO_FLASH_END_VADDR 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_M ((EXTMEM_DBUS_TO_FLASH_END_VADDR_V)<<(EXTMEM_DBUS_TO_FLASH_END_VADDR_S)) +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_V 0xFFFFFFFF +#define EXTMEM_DBUS_TO_FLASH_END_VADDR_S 0 + +#define EXTMEM_CACHE_ACS_CNT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0C4) +/* EXTMEM_ICACHE_ACS_CNT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear icache counter.*/ +#define EXTMEM_ICACHE_ACS_CNT_CLR (BIT(1)) +#define EXTMEM_ICACHE_ACS_CNT_CLR_M (BIT(1)) +#define EXTMEM_ICACHE_ACS_CNT_CLR_V 0x1 +#define EXTMEM_ICACHE_ACS_CNT_CLR_S 1 +/* EXTMEM_DCACHE_ACS_CNT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear dcache counter.*/ +#define EXTMEM_DCACHE_ACS_CNT_CLR (BIT(0)) +#define EXTMEM_DCACHE_ACS_CNT_CLR_M (BIT(0)) +#define EXTMEM_DCACHE_ACS_CNT_CLR_V 0x1 +#define EXTMEM_DCACHE_ACS_CNT_CLR_S 0 + +#define EXTMEM_IBUS_ACS_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0C8) +/* EXTMEM_IBUS_ACS_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused + by ibus access flash/spiram.*/ +#define EXTMEM_IBUS_ACS_MISS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_MISS_CNT_M ((EXTMEM_IBUS_ACS_MISS_CNT_V)<<(EXTMEM_IBUS_ACS_MISS_CNT_S)) +#define EXTMEM_IBUS_ACS_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_MISS_CNT_S 0 + +#define EXTMEM_IBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0CC) +/* EXTMEM_IBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of ibus access flash/spiram + through icache.*/ +#define EXTMEM_IBUS_ACS_CNT 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_CNT_M ((EXTMEM_IBUS_ACS_CNT_V)<<(EXTMEM_IBUS_ACS_CNT_S)) +#define EXTMEM_IBUS_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_IBUS_ACS_CNT_S 0 + +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D0) +/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused + by dbus access flash.*/ +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_M ((EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S)) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_S 0 + +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D4) +/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of the cache miss caused + by dbus access spiram.*/ +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_M ((EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V)<<(EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S)) +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_S 0 + +#define EXTMEM_DBUS_ACS_CNT_REG (DR_REG_EXTMEM_BASE + 0x0D8) +/* EXTMEM_DBUS_ACS_CNT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to count the number of dbus access flash/spiram + through dcache.*/ +#define EXTMEM_DBUS_ACS_CNT 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_CNT_M ((EXTMEM_DBUS_ACS_CNT_V)<<(EXTMEM_DBUS_ACS_CNT_S)) +#define EXTMEM_DBUS_ACS_CNT_V 0xFFFFFFFF +#define EXTMEM_DBUS_ACS_CNT_S 0 + +#define EXTMEM_CACHE_ILG_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0DC) +/* EXTMEM_DBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by dbus counter overflow.*/ +#define EXTMEM_DBUS_CNT_OVF_INT_ENA (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_M (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_V 0x1 +#define EXTMEM_DBUS_CNT_OVF_INT_ENA_S 8 +/* EXTMEM_IBUS_CNT_OVF_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by ibus counter overflow.*/ +#define EXTMEM_IBUS_CNT_OVF_INT_ENA (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_M (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_V 0x1 +#define EXTMEM_IBUS_CNT_OVF_INT_ENA_S 7 +/* EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by dcache trying to replace + a line whose blocks all have been occupied by occupy-mode.*/ +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA (BIT(6)) +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_M (BIT(6)) +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_ENA_S 6 +/* EXTMEM_MMU_ENTRY_FAULT_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_M (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_INT_ENA_S 5 +/* EXTMEM_DCACHE_WRITE_FLASH_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by dcache trying to write flash.*/ +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA (BIT(4)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_M (BIT(4)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_WRITE_FLASH_INT_ENA_S 4 +/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by preload configurations fault.*/ +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA_S 3 +/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by sync configurations fault.*/ +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA (BIT(2)) +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(2)) +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA_S 2 +/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by preload configurations fault.*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA_S 1 +/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by sync configurations fault.*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA_S 0 + +#define EXTMEM_CACHE_ILG_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0E0) +/* EXTMEM_DBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by dbus counter overflow.*/ +#define EXTMEM_DBUS_CNT_OVF_INT_CLR (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_M (BIT(8)) +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_V 0x1 +#define EXTMEM_DBUS_CNT_OVF_INT_CLR_S 8 +/* EXTMEM_IBUS_CNT_OVF_INT_CLR : WOD ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by ibus counter overflow.*/ +#define EXTMEM_IBUS_CNT_OVF_INT_CLR (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_M (BIT(7)) +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_V 0x1 +#define EXTMEM_IBUS_CNT_OVF_INT_CLR_S 7 +/* EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR : WOD ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by dcache trying to replace + a line whose blocks all have been occupied by occupy-mode.*/ +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR (BIT(6)) +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_M (BIT(6)) +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_OCCUPY_EXC_INT_CLR_S 6 +/* EXTMEM_MMU_ENTRY_FAULT_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_M (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_INT_CLR_S 5 +/* EXTMEM_DCACHE_WRITE_FLASH_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by dcache trying to write flash.*/ +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR (BIT(4)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_M (BIT(4)) +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_WRITE_FLASH_INT_CLR_S 4 +/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by preload configurations fault.*/ +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR_S 3 +/* EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by sync configurations fault.*/ +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR (BIT(2)) +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(2)) +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR_S 2 +/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by preload configurations fault.*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR_S 1 +/* EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by sync configurations fault.*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR_S 0 + +#define EXTMEM_CACHE_ILG_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0E4) +/* EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus access spiram miss + counter overflow.*/ +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST (BIT(11)) +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_M (BIT(11)) +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS_ACS_SPIRAM_MISS_CNT_OVF_ST_S 11 +/* EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus access flash miss + counter overflow.*/ +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST (BIT(10)) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_M (BIT(10)) +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS_ACS_FLASH_MISS_CNT_OVF_ST_S 10 +/* EXTMEM_DBUS_ACS_CNT_OVF_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dbus access flash/spiram + counter overflow.*/ +#define EXTMEM_DBUS_ACS_CNT_OVF_ST (BIT(9)) +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_M (BIT(9)) +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_DBUS_ACS_CNT_OVF_ST_S 9 +/* EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus access flash/spiram + miss counter overflow.*/ +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST (BIT(8)) +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_M (BIT(8)) +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS_ACS_MISS_CNT_OVF_ST_S 8 +/* EXTMEM_IBUS_ACS_CNT_OVF_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus access flash/spiram + counter overflow.*/ +#define EXTMEM_IBUS_ACS_CNT_OVF_ST (BIT(7)) +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_M (BIT(7)) +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_V 0x1 +#define EXTMEM_IBUS_ACS_CNT_OVF_ST_S 7 +/* EXTMEM_DCACHE_OCCUPY_EXC_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dcache trying to replace + a line whose blocks all have been occupied by occupy-mode.*/ +#define EXTMEM_DCACHE_OCCUPY_EXC_ST (BIT(6)) +#define EXTMEM_DCACHE_OCCUPY_EXC_ST_M (BIT(6)) +#define EXTMEM_DCACHE_OCCUPY_EXC_ST_V 0x1 +#define EXTMEM_DCACHE_OCCUPY_EXC_ST_S 6 +/* EXTMEM_MMU_ENTRY_FAULT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by mmu entry fault.*/ +#define EXTMEM_MMU_ENTRY_FAULT_ST (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_M (BIT(5)) +#define EXTMEM_MMU_ENTRY_FAULT_ST_V 0x1 +#define EXTMEM_MMU_ENTRY_FAULT_ST_S 5 +/* EXTMEM_DCACHE_WRITE_FLASH_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by dcache trying to write flash.*/ +#define EXTMEM_DCACHE_WRITE_FLASH_ST (BIT(4)) +#define EXTMEM_DCACHE_WRITE_FLASH_ST_M (BIT(4)) +#define EXTMEM_DCACHE_WRITE_FLASH_ST_V 0x1 +#define EXTMEM_DCACHE_WRITE_FLASH_ST_S 4 +/* EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by preload configurations fault.*/ +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_M (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_OP_FAULT_ST_S 3 +/* EXTMEM_DCACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by sync configurations fault.*/ +#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST (BIT(2)) +#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_M (BIT(2)) +#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_V 0x1 +#define EXTMEM_DCACHE_SYNC_OP_FAULT_ST_S 2 +/* EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by preload configurations fault.*/ +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_OP_FAULT_ST_S 1 +/* EXTMEM_ICACHE_SYNC_OP_FAULT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by sync configurations fault.*/ +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_V 0x1 +#define EXTMEM_ICACHE_SYNC_OP_FAULT_ST_S 0 + +#define EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0E8) +/* EXTMEM_CORE0_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_M (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_V 0x1 +#define EXTMEM_CORE0_DBUS_REJECT_INT_ENA_S 4 +/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access dcache while + the corresponding dbus is disabled which include speculative access.*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA_S 3 +/* EXTMEM_CORE0_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_M (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_V 0x1 +#define EXTMEM_CORE0_IBUS_REJECT_INT_ENA_S 2 +/* EXTMEM_CORE0_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_M (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_IBUS_WR_IC_INT_ENA_S 1 +/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access icache while + the corresponding ibus is disabled which include speculative access.*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA_S 0 + +#define EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0EC) +/* EXTMEM_CORE0_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_M (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_V 0x1 +#define EXTMEM_CORE0_DBUS_REJECT_INT_CLR_S 4 +/* EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access dcache while + the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR_S 3 +/* EXTMEM_CORE0_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_M (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_V 0x1 +#define EXTMEM_CORE0_IBUS_REJECT_INT_CLR_S 2 +/* EXTMEM_CORE0_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_M (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_IBUS_WR_IC_INT_CLR_S 1 +/* EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access icache while + the corresponding ibus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR_S 0 + +#define EXTMEM_CORE0_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0F0) +/* EXTMEM_CORE0_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_CORE0_DBUS_REJECT_ST (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_ST_M (BIT(4)) +#define EXTMEM_CORE0_DBUS_REJECT_ST_V 0x1 +#define EXTMEM_CORE0_DBUS_REJECT_ST_S 4 +/* EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access dcache while + the core0_dbus is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) +#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_V 0x1 +#define EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST_S 3 +/* EXTMEM_CORE0_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_CORE0_IBUS_REJECT_ST (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_ST_M (BIT(2)) +#define EXTMEM_CORE0_IBUS_REJECT_ST_V 0x1 +#define EXTMEM_CORE0_IBUS_REJECT_ST_S 2 +/* EXTMEM_CORE0_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_M (BIT(1)) +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_V 0x1 +#define EXTMEM_CORE0_IBUS_WR_ICACHE_ST_S 1 +/* EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access icache while + the core0_ibus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST_S 0 + +#define EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG (DR_REG_EXTMEM_BASE + 0x0F4) +/* EXTMEM_CORE1_DBUS_REJECT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA (BIT(4)) +#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_M (BIT(4)) +#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_V 0x1 +#define EXTMEM_CORE1_DBUS_REJECT_INT_ENA_S 4 +/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access dcache while + the corresponding dbus is disabled which include speculative access.*/ +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA (BIT(3)) +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_M (BIT(3)) +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_V 0x1 +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA_S 3 +/* EXTMEM_CORE1_IBUS_REJECT_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by authentication fail.*/ +#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA (BIT(2)) +#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_M (BIT(2)) +#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_V 0x1 +#define EXTMEM_CORE1_IBUS_REJECT_INT_ENA_S 2 +/* EXTMEM_CORE1_IBUS_WR_IC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA (BIT(1)) +#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_M (BIT(1)) +#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE1_IBUS_WR_IC_INT_ENA_S 1 +/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable interrupt by cpu access icache while + the corresponding ibus is disabled which include speculative access.*/ +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA (BIT(0)) +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_M (BIT(0)) +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_V 0x1 +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA_S 0 + +#define EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG (DR_REG_EXTMEM_BASE + 0x0F8) +/* EXTMEM_CORE1_DBUS_REJECT_INT_CLR : WOD ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR (BIT(4)) +#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_M (BIT(4)) +#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_V 0x1 +#define EXTMEM_CORE1_DBUS_REJECT_INT_CLR_S 4 +/* EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR : WOD ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access dcache while + the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR (BIT(3)) +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_M (BIT(3)) +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_V 0x1 +#define EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR_S 3 +/* EXTMEM_CORE1_IBUS_REJECT_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by authentication fail.*/ +#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR (BIT(2)) +#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_M (BIT(2)) +#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_V 0x1 +#define EXTMEM_CORE1_IBUS_REJECT_INT_CLR_S 2 +/* EXTMEM_CORE1_IBUS_WR_IC_INT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR (BIT(1)) +#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_M (BIT(1)) +#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE1_IBUS_WR_IC_INT_CLR_S 1 +/* EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR : WOD ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to clear interrupt by cpu access icache while + the corresponding ibus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR (BIT(0)) +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_M (BIT(0)) +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_V 0x1 +#define EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR_S 0 + +#define EXTMEM_CORE1_ACS_CACHE_INT_ST_REG (DR_REG_EXTMEM_BASE + 0x0FC) +/* EXTMEM_CORE1_DBUS_REJECT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_CORE1_DBUS_REJECT_ST (BIT(4)) +#define EXTMEM_CORE1_DBUS_REJECT_ST_M (BIT(4)) +#define EXTMEM_CORE1_DBUS_REJECT_ST_V 0x1 +#define EXTMEM_CORE1_DBUS_REJECT_ST_S 4 +/* EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access dcache while + the core1_dbus is disabled or dcache is disabled which include speculative access.*/ +#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST (BIT(3)) +#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_M (BIT(3)) +#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_V 0x1 +#define EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST_S 3 +/* EXTMEM_CORE1_IBUS_REJECT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by authentication fail.*/ +#define EXTMEM_CORE1_IBUS_REJECT_ST (BIT(2)) +#define EXTMEM_CORE1_IBUS_REJECT_ST_M (BIT(2)) +#define EXTMEM_CORE1_IBUS_REJECT_ST_V 0x1 +#define EXTMEM_CORE1_IBUS_REJECT_ST_S 2 +/* EXTMEM_CORE1_IBUS_WR_ICACHE_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by ibus trying to write icache*/ +#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST (BIT(1)) +#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_M (BIT(1)) +#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_V 0x1 +#define EXTMEM_CORE1_IBUS_WR_ICACHE_ST_S 1 +/* EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate interrupt by cpu access icache while + the core1_ibus is disabled or icache is disabled which include speculative access.*/ +#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST (BIT(0)) +#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_M (BIT(0)) +#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_V 0x1 +#define EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST_S 0 + +#define EXTMEM_CORE0_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x100) +/* EXTMEM_CORE0_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the world of CPU access dbus when + authentication fail. 0: WORLD0 1: WORLD1*/ +#define EXTMEM_CORE0_DBUS_WORLD (BIT(6)) +#define EXTMEM_CORE0_DBUS_WORLD_M (BIT(6)) +#define EXTMEM_CORE0_DBUS_WORLD_V 0x1 +#define EXTMEM_CORE0_DBUS_WORLD_S 6 +/* EXTMEM_CORE0_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access dbus + when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_CORE0_DBUS_ATTR 0x00000007 +#define EXTMEM_CORE0_DBUS_ATTR_M ((EXTMEM_CORE0_DBUS_ATTR_V)<<(EXTMEM_CORE0_DBUS_ATTR_S)) +#define EXTMEM_CORE0_DBUS_ATTR_V 0x7 +#define EXTMEM_CORE0_DBUS_ATTR_S 3 +/* EXTMEM_CORE0_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of data from external + memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_CORE0_DBUS_TAG_ATTR 0x00000007 +#define EXTMEM_CORE0_DBUS_TAG_ATTR_M ((EXTMEM_CORE0_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_DBUS_TAG_ATTR_S)) +#define EXTMEM_CORE0_DBUS_TAG_ATTR_V 0x7 +#define EXTMEM_CORE0_DBUS_TAG_ATTR_S 0 + +#define EXTMEM_CORE0_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x104) +/* EXTMEM_CORE0_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address of CPU access + dbus when authentication fail.*/ +#define EXTMEM_CORE0_DBUS_VADDR 0xFFFFFFFF +#define EXTMEM_CORE0_DBUS_VADDR_M ((EXTMEM_CORE0_DBUS_VADDR_V)<<(EXTMEM_CORE0_DBUS_VADDR_S)) +#define EXTMEM_CORE0_DBUS_VADDR_V 0xFFFFFFFF +#define EXTMEM_CORE0_DBUS_VADDR_S 0 + +#define EXTMEM_CORE0_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x108) +/* EXTMEM_CORE0_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the world of CPU access ibus when + authentication fail. 0: WORLD0 1: WORLD1*/ +#define EXTMEM_CORE0_IBUS_WORLD (BIT(6)) +#define EXTMEM_CORE0_IBUS_WORLD_M (BIT(6)) +#define EXTMEM_CORE0_IBUS_WORLD_V 0x1 +#define EXTMEM_CORE0_IBUS_WORLD_S 6 +/* EXTMEM_CORE0_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access ibus + when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ +#define EXTMEM_CORE0_IBUS_ATTR 0x00000007 +#define EXTMEM_CORE0_IBUS_ATTR_M ((EXTMEM_CORE0_IBUS_ATTR_V)<<(EXTMEM_CORE0_IBUS_ATTR_S)) +#define EXTMEM_CORE0_IBUS_ATTR_V 0x7 +#define EXTMEM_CORE0_IBUS_ATTR_S 3 +/* EXTMEM_CORE0_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of data from external + memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_CORE0_IBUS_TAG_ATTR 0x00000007 +#define EXTMEM_CORE0_IBUS_TAG_ATTR_M ((EXTMEM_CORE0_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE0_IBUS_TAG_ATTR_S)) +#define EXTMEM_CORE0_IBUS_TAG_ATTR_V 0x7 +#define EXTMEM_CORE0_IBUS_TAG_ATTR_S 0 + +#define EXTMEM_CORE0_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x10C) +/* EXTMEM_CORE0_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address of CPU access + ibus when authentication fail.*/ +#define EXTMEM_CORE0_IBUS_VADDR 0xFFFFFFFF +#define EXTMEM_CORE0_IBUS_VADDR_M ((EXTMEM_CORE0_IBUS_VADDR_V)<<(EXTMEM_CORE0_IBUS_VADDR_S)) +#define EXTMEM_CORE0_IBUS_VADDR_V 0xFFFFFFFF +#define EXTMEM_CORE0_IBUS_VADDR_S 0 + +#define EXTMEM_CORE1_DBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x110) +/* EXTMEM_CORE1_DBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the world of CPU access dbus when + authentication fail. 0: WORLD0 1: WORLD1*/ +#define EXTMEM_CORE1_DBUS_WORLD (BIT(6)) +#define EXTMEM_CORE1_DBUS_WORLD_M (BIT(6)) +#define EXTMEM_CORE1_DBUS_WORLD_V 0x1 +#define EXTMEM_CORE1_DBUS_WORLD_S 6 +/* EXTMEM_CORE1_DBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access dbus + when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_CORE1_DBUS_ATTR 0x00000007 +#define EXTMEM_CORE1_DBUS_ATTR_M ((EXTMEM_CORE1_DBUS_ATTR_V)<<(EXTMEM_CORE1_DBUS_ATTR_S)) +#define EXTMEM_CORE1_DBUS_ATTR_V 0x7 +#define EXTMEM_CORE1_DBUS_ATTR_S 3 +/* EXTMEM_CORE1_DBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of data from external + memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_CORE1_DBUS_TAG_ATTR 0x00000007 +#define EXTMEM_CORE1_DBUS_TAG_ATTR_M ((EXTMEM_CORE1_DBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_DBUS_TAG_ATTR_S)) +#define EXTMEM_CORE1_DBUS_TAG_ATTR_V 0x7 +#define EXTMEM_CORE1_DBUS_TAG_ATTR_S 0 + +#define EXTMEM_CORE1_DBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x114) +/* EXTMEM_CORE1_DBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address of CPU access + dbus when authentication fail.*/ +#define EXTMEM_CORE1_DBUS_VADDR 0xFFFFFFFF +#define EXTMEM_CORE1_DBUS_VADDR_M ((EXTMEM_CORE1_DBUS_VADDR_V)<<(EXTMEM_CORE1_DBUS_VADDR_S)) +#define EXTMEM_CORE1_DBUS_VADDR_V 0xFFFFFFFF +#define EXTMEM_CORE1_DBUS_VADDR_S 0 + +#define EXTMEM_CORE1_IBUS_REJECT_ST_REG (DR_REG_EXTMEM_BASE + 0x118) +/* EXTMEM_CORE1_IBUS_WORLD : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the world of CPU access ibus when + authentication fail. 0: WORLD0 1: WORLD1*/ +#define EXTMEM_CORE1_IBUS_WORLD (BIT(6)) +#define EXTMEM_CORE1_IBUS_WORLD_M (BIT(6)) +#define EXTMEM_CORE1_IBUS_WORLD_V 0x1 +#define EXTMEM_CORE1_IBUS_WORLD_S 6 +/* EXTMEM_CORE1_IBUS_ATTR : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of CPU access ibus + when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ +#define EXTMEM_CORE1_IBUS_ATTR 0x00000007 +#define EXTMEM_CORE1_IBUS_ATTR_M ((EXTMEM_CORE1_IBUS_ATTR_V)<<(EXTMEM_CORE1_IBUS_ATTR_S)) +#define EXTMEM_CORE1_IBUS_ATTR_V 0x7 +#define EXTMEM_CORE1_IBUS_ATTR_S 3 +/* EXTMEM_CORE1_IBUS_TAG_ATTR : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The bits are used to indicate the attribute of data from external + memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ +#define EXTMEM_CORE1_IBUS_TAG_ATTR 0x00000007 +#define EXTMEM_CORE1_IBUS_TAG_ATTR_M ((EXTMEM_CORE1_IBUS_TAG_ATTR_V)<<(EXTMEM_CORE1_IBUS_TAG_ATTR_S)) +#define EXTMEM_CORE1_IBUS_TAG_ATTR_V 0x7 +#define EXTMEM_CORE1_IBUS_TAG_ATTR_S 0 + +#define EXTMEM_CORE1_IBUS_REJECT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x11C) +/* EXTMEM_CORE1_IBUS_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address of CPU access + ibus when authentication fail.*/ +#define EXTMEM_CORE1_IBUS_VADDR 0xFFFFFFFF +#define EXTMEM_CORE1_IBUS_VADDR_M ((EXTMEM_CORE1_IBUS_VADDR_V)<<(EXTMEM_CORE1_IBUS_VADDR_S)) +#define EXTMEM_CORE1_IBUS_VADDR_V 0xFFFFFFFF +#define EXTMEM_CORE1_IBUS_VADDR_S 0 + +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_REG (DR_REG_EXTMEM_BASE + 0x120) +/* EXTMEM_CACHE_MMU_FAULT_CODE : RO ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: The right-most 3 bits are used to indicate the operations which + cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ +#define EXTMEM_CACHE_MMU_FAULT_CODE 0x0000000F +#define EXTMEM_CACHE_MMU_FAULT_CODE_M ((EXTMEM_CACHE_MMU_FAULT_CODE_V)<<(EXTMEM_CACHE_MMU_FAULT_CODE_S)) +#define EXTMEM_CACHE_MMU_FAULT_CODE_V 0xF +#define EXTMEM_CACHE_MMU_FAULT_CODE_S 16 +/* EXTMEM_CACHE_MMU_FAULT_CONTENT : RO ;bitpos:[15:0] ;default: 17'h0 ; */ +/*description: The bits are used to indicate the content of mmu entry which cause mmu fault..*/ +#define EXTMEM_CACHE_MMU_FAULT_CONTENT 0x0000FFFF +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_M ((EXTMEM_CACHE_MMU_FAULT_CONTENT_V)<<(EXTMEM_CACHE_MMU_FAULT_CONTENT_S)) +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_V 0xFFFF +#define EXTMEM_CACHE_MMU_FAULT_CONTENT_S 0 + +#define EXTMEM_CACHE_MMU_FAULT_VADDR_REG (DR_REG_EXTMEM_BASE + 0x124) +/* EXTMEM_CACHE_MMU_FAULT_VADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The bits are used to indicate the virtual address which cause mmu fault..*/ +#define EXTMEM_CACHE_MMU_FAULT_VADDR 0xFFFFFFFF +#define EXTMEM_CACHE_MMU_FAULT_VADDR_M ((EXTMEM_CACHE_MMU_FAULT_VADDR_V)<<(EXTMEM_CACHE_MMU_FAULT_VADDR_S)) +#define EXTMEM_CACHE_MMU_FAULT_VADDR_V 0xFFFFFFFF +#define EXTMEM_CACHE_MMU_FAULT_VADDR_S 0 + +#define EXTMEM_CACHE_WRAP_AROUND_CTRL_REG (DR_REG_EXTMEM_BASE + 0x128) +/* EXTMEM_CACHE_SRAM_RD_WRAP_AROUND : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable wrap around mode when read data from spiram.*/ +#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND (BIT(1)) +#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_M (BIT(1)) +#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_V 0x1 +#define EXTMEM_CACHE_SRAM_RD_WRAP_AROUND_S 1 +/* EXTMEM_CACHE_FLASH_WRAP_AROUND : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable wrap around mode when read data from flash.*/ +#define EXTMEM_CACHE_FLASH_WRAP_AROUND (BIT(0)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_M (BIT(0)) +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_V 0x1 +#define EXTMEM_CACHE_FLASH_WRAP_AROUND_S 0 + +#define EXTMEM_CACHE_MMU_POWER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x12C) +/* EXTMEM_CACHE_MMU_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU (BIT(2)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_M (BIT(2)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_PU_S 2 +/* EXTMEM_CACHE_MMU_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD (BIT(1)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_M (BIT(1)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_PD_S 1 +/* EXTMEM_CACHE_MMU_MEM_FORCE_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable clock gating to save power when access + mmu memory 0: enable 1: disable*/ +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON (BIT(0)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_M (BIT(0)) +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_V 0x1 +#define EXTMEM_CACHE_MMU_MEM_FORCE_ON_S 0 + +#define EXTMEM_CACHE_STATE_REG (DR_REG_EXTMEM_BASE + 0x130) +/* EXTMEM_DCACHE_STATE : RO ;bitpos:[23:12] ;default: 12'h0 ; */ +/*description: The bit is used to indicate whether dcache main fsm is in idle + state or not. 1: in idle state 0: not in idle state*/ +#define EXTMEM_DCACHE_STATE 0x00000FFF +#define EXTMEM_DCACHE_STATE_M ((EXTMEM_DCACHE_STATE_V)<<(EXTMEM_DCACHE_STATE_S)) +#define EXTMEM_DCACHE_STATE_V 0xFFF +#define EXTMEM_DCACHE_STATE_S 12 +/* EXTMEM_ICACHE_STATE : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: The bit is used to indicate whether icache main fsm is in idle + state or not. 1: in idle state 0: not in idle state*/ +#define EXTMEM_ICACHE_STATE 0x00000FFF +#define EXTMEM_ICACHE_STATE_M ((EXTMEM_ICACHE_STATE_V)<<(EXTMEM_ICACHE_STATE_S)) +#define EXTMEM_ICACHE_STATE_V 0xFFF +#define EXTMEM_ICACHE_STATE_S 0 + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE_REG (DR_REG_EXTMEM_BASE + 0x134) +/* EXTMEM_RECORD_DISABLE_G0CB_DECRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_M (BIT(1)) +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_V 0x1 +#define EXTMEM_RECORD_DISABLE_G0CB_DECRYPT_S 1 +/* EXTMEM_RECORD_DISABLE_DB_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT (BIT(0)) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_M (BIT(0)) +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_V 0x1 +#define EXTMEM_RECORD_DISABLE_DB_ENCRYPT_S 0 + +#define EXTMEM_CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON_REG (DR_REG_EXTMEM_BASE + 0x138) +/* EXTMEM_CLK_FORCE_ON_CRYPT : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of external memory encrypt + and decrypt clock. 1: close gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_CRYPT (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_CRYPT_M (BIT(2)) +#define EXTMEM_CLK_FORCE_ON_CRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_CRYPT_S 2 +/* EXTMEM_CLK_FORCE_ON_AUTO_CRYPT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of automatic crypt clock. + 1: close gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_M (BIT(1)) +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_AUTO_CRYPT_S 1 +/* EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to close clock gating of manual crypt clock. + 1: close gating 0: open clock gating.*/ +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT (BIT(0)) +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_M (BIT(0)) +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_V 0x1 +#define EXTMEM_CLK_FORCE_ON_MANUAL_CRYPT_S 0 + +#define EXTMEM_CACHE_BRIDGE_ARBITER_CTRL_REG (DR_REG_EXTMEM_BASE + 0x13C) +/* EXTMEM_ALLOC_WB_HOLD_ARBITER : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Reserved.*/ +#define EXTMEM_ALLOC_WB_HOLD_ARBITER (BIT(0)) +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_M (BIT(0)) +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_V 0x1 +#define EXTMEM_ALLOC_WB_HOLD_ARBITER_S 0 + +#define EXTMEM_CACHE_PRELOAD_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x140) +/* EXTMEM_DCACHE_PRELOAD_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by dcache pre-load done.*/ +#define EXTMEM_DCACHE_PRELOAD_INT_CLR (BIT(5)) +#define EXTMEM_DCACHE_PRELOAD_INT_CLR_M (BIT(5)) +#define EXTMEM_DCACHE_PRELOAD_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_INT_CLR_S 5 +/* EXTMEM_DCACHE_PRELOAD_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by dcache pre-load done.*/ +#define EXTMEM_DCACHE_PRELOAD_INT_ENA (BIT(4)) +#define EXTMEM_DCACHE_PRELOAD_INT_ENA_M (BIT(4)) +#define EXTMEM_DCACHE_PRELOAD_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_INT_ENA_S 4 +/* EXTMEM_DCACHE_PRELOAD_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by dcache pre-load done.*/ +#define EXTMEM_DCACHE_PRELOAD_INT_ST (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_INT_ST_M (BIT(3)) +#define EXTMEM_DCACHE_PRELOAD_INT_ST_V 0x1 +#define EXTMEM_DCACHE_PRELOAD_INT_ST_S 3 +/* EXTMEM_ICACHE_PRELOAD_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by icache pre-load done.*/ +#define EXTMEM_ICACHE_PRELOAD_INT_CLR (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_M (BIT(2)) +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_INT_CLR_S 2 +/* EXTMEM_ICACHE_PRELOAD_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by icache pre-load done.*/ +#define EXTMEM_ICACHE_PRELOAD_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_INT_ENA_S 1 +/* EXTMEM_ICACHE_PRELOAD_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by icache pre-load done.*/ +#define EXTMEM_ICACHE_PRELOAD_INT_ST (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_INT_ST_M (BIT(0)) +#define EXTMEM_ICACHE_PRELOAD_INT_ST_V 0x1 +#define EXTMEM_ICACHE_PRELOAD_INT_ST_S 0 + +#define EXTMEM_CACHE_SYNC_INT_CTRL_REG (DR_REG_EXTMEM_BASE + 0x144) +/* EXTMEM_DCACHE_SYNC_INT_CLR : WOD ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by dcache sync done.*/ +#define EXTMEM_DCACHE_SYNC_INT_CLR (BIT(5)) +#define EXTMEM_DCACHE_SYNC_INT_CLR_M (BIT(5)) +#define EXTMEM_DCACHE_SYNC_INT_CLR_V 0x1 +#define EXTMEM_DCACHE_SYNC_INT_CLR_S 5 +/* EXTMEM_DCACHE_SYNC_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by dcache sync done.*/ +#define EXTMEM_DCACHE_SYNC_INT_ENA (BIT(4)) +#define EXTMEM_DCACHE_SYNC_INT_ENA_M (BIT(4)) +#define EXTMEM_DCACHE_SYNC_INT_ENA_V 0x1 +#define EXTMEM_DCACHE_SYNC_INT_ENA_S 4 +/* EXTMEM_DCACHE_SYNC_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by dcache sync done.*/ +#define EXTMEM_DCACHE_SYNC_INT_ST (BIT(3)) +#define EXTMEM_DCACHE_SYNC_INT_ST_M (BIT(3)) +#define EXTMEM_DCACHE_SYNC_INT_ST_V 0x1 +#define EXTMEM_DCACHE_SYNC_INT_ST_S 3 +/* EXTMEM_ICACHE_SYNC_INT_CLR : WOD ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to clear the interrupt by icache sync done.*/ +#define EXTMEM_ICACHE_SYNC_INT_CLR (BIT(2)) +#define EXTMEM_ICACHE_SYNC_INT_CLR_M (BIT(2)) +#define EXTMEM_ICACHE_SYNC_INT_CLR_V 0x1 +#define EXTMEM_ICACHE_SYNC_INT_CLR_S 2 +/* EXTMEM_ICACHE_SYNC_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable the interrupt by icache sync done.*/ +#define EXTMEM_ICACHE_SYNC_INT_ENA (BIT(1)) +#define EXTMEM_ICACHE_SYNC_INT_ENA_M (BIT(1)) +#define EXTMEM_ICACHE_SYNC_INT_ENA_V 0x1 +#define EXTMEM_ICACHE_SYNC_INT_ENA_S 1 +/* EXTMEM_ICACHE_SYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the interrupt by icache sync done.*/ +#define EXTMEM_ICACHE_SYNC_INT_ST (BIT(0)) +#define EXTMEM_ICACHE_SYNC_INT_ST_M (BIT(0)) +#define EXTMEM_ICACHE_SYNC_INT_ST_V 0x1 +#define EXTMEM_ICACHE_SYNC_INT_ST_S 0 + +#define EXTMEM_CACHE_MMU_OWNER_REG (DR_REG_EXTMEM_BASE + 0x148) +/* EXTMEM_CACHE_MMU_OWNER : R/W ;bitpos:[23:0] ;default: 24'h0 ; */ +/*description: The bits are used to specify the owner of MMU.bit0: icache bit1: + dcache bit2: dma bit3: reserved.*/ +#define EXTMEM_CACHE_MMU_OWNER 0x00FFFFFF +#define EXTMEM_CACHE_MMU_OWNER_M ((EXTMEM_CACHE_MMU_OWNER_V)<<(EXTMEM_CACHE_MMU_OWNER_S)) +#define EXTMEM_CACHE_MMU_OWNER_V 0xFFFFFF +#define EXTMEM_CACHE_MMU_OWNER_S 0 + +#define EXTMEM_CACHE_CONF_MISC_REG (DR_REG_EXTMEM_BASE + 0x14C) +/* EXTMEM_CACHE_TRACE_ENA : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: The bit is used to enable cache trace function.*/ +#define EXTMEM_CACHE_TRACE_ENA (BIT(2)) +#define EXTMEM_CACHE_TRACE_ENA_M (BIT(2)) +#define EXTMEM_CACHE_TRACE_ENA_V 0x1 +#define EXTMEM_CACHE_TRACE_ENA_S 2 +/* EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: The bit is used to disable checking mmu entry fault by sync operation.*/ +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT (BIT(1)) +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_M (BIT(1)) +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_V 0x1 +#define EXTMEM_CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT_S 1 +/* EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to disable checking mmu entry fault by preload operation.*/ +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT (BIT(0)) +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_M (BIT(0)) +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_V 0x1 +#define EXTMEM_CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT_S 0 + +#define EXTMEM_DCACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x150) +/* EXTMEM_DCACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate dcache freeze success*/ +#define EXTMEM_DCACHE_FREEZE_DONE (BIT(2)) +#define EXTMEM_DCACHE_FREEZE_DONE_M (BIT(2)) +#define EXTMEM_DCACHE_FREEZE_DONE_V 0x1 +#define EXTMEM_DCACHE_FREEZE_DONE_S 2 +/* EXTMEM_DCACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to configure freeze mode 0: assert busy if + CPU miss 1: assert hit if CPU miss*/ +#define EXTMEM_DCACHE_FREEZE_MODE (BIT(1)) +#define EXTMEM_DCACHE_FREEZE_MODE_M (BIT(1)) +#define EXTMEM_DCACHE_FREEZE_MODE_V 0x1 +#define EXTMEM_DCACHE_FREEZE_MODE_S 1 +/* EXTMEM_DCACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable dcache freeze mode*/ +#define EXTMEM_DCACHE_FREEZE_ENA (BIT(0)) +#define EXTMEM_DCACHE_FREEZE_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_FREEZE_ENA_V 0x1 +#define EXTMEM_DCACHE_FREEZE_ENA_S 0 + +#define EXTMEM_ICACHE_FREEZE_REG (DR_REG_EXTMEM_BASE + 0x154) +/* EXTMEM_ICACHE_FREEZE_DONE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The bit is used to indicate icache freeze success*/ +#define EXTMEM_ICACHE_FREEZE_DONE (BIT(2)) +#define EXTMEM_ICACHE_FREEZE_DONE_M (BIT(2)) +#define EXTMEM_ICACHE_FREEZE_DONE_V 0x1 +#define EXTMEM_ICACHE_FREEZE_DONE_S 2 +/* EXTMEM_ICACHE_FREEZE_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to configure freeze mode 0: assert busy if + CPU miss 1: assert hit if CPU miss*/ +#define EXTMEM_ICACHE_FREEZE_MODE (BIT(1)) +#define EXTMEM_ICACHE_FREEZE_MODE_M (BIT(1)) +#define EXTMEM_ICACHE_FREEZE_MODE_V 0x1 +#define EXTMEM_ICACHE_FREEZE_MODE_S 1 +/* EXTMEM_ICACHE_FREEZE_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to enable icache freeze mode*/ +#define EXTMEM_ICACHE_FREEZE_ENA (BIT(0)) +#define EXTMEM_ICACHE_FREEZE_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_FREEZE_ENA_V 0x1 +#define EXTMEM_ICACHE_FREEZE_ENA_S 0 + +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x158) +/* EXTMEM_ICACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to activate icache atomic operation protection. + In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA (BIT(0)) +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_V 0x1 +#define EXTMEM_ICACHE_ATOMIC_OPERATE_ENA_S 0 + +#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_REG (DR_REG_EXTMEM_BASE + 0x15C) +/* EXTMEM_DCACHE_ATOMIC_OPERATE_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to activate dcache atomic operation protection. + In this case sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ +#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA (BIT(0)) +#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_M (BIT(0)) +#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_V 0x1 +#define EXTMEM_DCACHE_ATOMIC_OPERATE_ENA_S 0 + +#define EXTMEM_CACHE_REQUEST_REG (DR_REG_EXTMEM_BASE + 0x160) +/* EXTMEM_CACHE_REQUEST_BYPASS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The bit is used to disable request recording which could cause performance issue*/ +#define EXTMEM_CACHE_REQUEST_BYPASS (BIT(0)) +#define EXTMEM_CACHE_REQUEST_BYPASS_M (BIT(0)) +#define EXTMEM_CACHE_REQUEST_BYPASS_V 0x1 +#define EXTMEM_CACHE_REQUEST_BYPASS_S 0 + +#define EXTMEM_CLOCK_GATE_REG (DR_REG_EXTMEM_BASE + 0x164) +/* EXTMEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Reserved.*/ +#define EXTMEM_CLK_EN (BIT(0)) +#define EXTMEM_CLK_EN_M (BIT(0)) +#define EXTMEM_CLK_EN_V 0x1 +#define EXTMEM_CLK_EN_S 0 + +#define EXTMEM_DATE_REG (DR_REG_EXTMEM_BASE + 0x3FC) +/* EXTMEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003242 ; */ +/*description: Reserved.*/ +#define EXTMEM_DATE 0x0FFFFFFF +#define EXTMEM_DATE_M ((EXTMEM_DATE_V)<<(EXTMEM_DATE_S)) +#define EXTMEM_DATE_V 0xFFFFFFF +#define EXTMEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/extmem_struct.h b/components/soc/soc/esp32s3/include/soc/extmem_struct.h new file mode 100644 index 000000000..362944a09 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/extmem_struct.h @@ -0,0 +1,780 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t dcache_enable: 1; /*The bit is used to activate the data cache. 0: disable 1: enable*/ + uint32_t reserved1: 1; /*Reserved*/ + uint32_t dcache_size_mode: 1; /*The bit is used to configure cache memory size.0: 32KB 1: 64KB*/ + uint32_t dcache_blocksize_mode: 1; /*The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } dcache_ctrl; + union { + struct { + uint32_t dcache_shut_core0_bus: 1; /*The bit is used to disable core0 dbus 0: enable 1: disable*/ + uint32_t dcache_shut_core1_bus: 1; /*The bit is used to disable core1 dbus 0: enable 1: disable*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } dcache_ctrl1; + union { + struct { + uint32_t dcache_tag_mem_force_on: 1; /*The bit is used to close clock gating of dcache tag memory. 1: close gating 0: open clock gating.*/ + uint32_t dcache_tag_mem_force_pd: 1; /*The bit is used to power dcache tag memory down 0: follow rtc_lslp_pd 1: power down*/ + uint32_t dcache_tag_mem_force_pu: 1; /*The bit is used to power dcache tag memory up 0: follow rtc_lslp_pd 1: power up*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } dcache_tag_power_ctrl; + union { + struct { + uint32_t dcache_prelock_sct0_en: 1; /*The bit is used to enable the first section of prelock function.*/ + uint32_t dcache_prelock_sct1_en: 1; /*The bit is used to enable the second section of prelock function.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } dcache_prelock_ctrl; + uint32_t dcache_prelock_sct0_addr; /*The bits are used to configure the first start virtual address of data prelock which is combined with DCACHE_PRELOCK_SCT0_SIZE_REG*/ + uint32_t dcache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with DCACHE_PRELOCK_SCT1_SIZE_REG*/ + union { + struct { + uint32_t dcache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with DCACHE_PRELOCK_SCT1_ADDR_REG*/ + uint32_t dcache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with DCACHE_PRELOCK_SCT0_ADDR_REG*/ + }; + uint32_t val; + } dcache_prelock_sct_size; + union { + struct { + uint32_t dcache_lock_ena: 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/ + uint32_t dcache_unlock_ena: 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/ + uint32_t dcache_lock_done: 1; /*The bit is used to indicate unlock/lock operation is finished.*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } dcache_lock_ctrl; + uint32_t dcache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with DCACHE_LOCK_SIZE_REG.*/ + union { + struct { + uint32_t dcache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with DCACHE_LOCK_ADDR_REG.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } dcache_lock_size; + union { + struct { + uint32_t dcache_invalidate_ena: 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/ + uint32_t dcache_writeback_ena: 1; /*The bit is used to enable writeback operation. It will be cleared by hardware after writeback operation done.*/ + uint32_t dcache_clean_ena: 1; /*The bit is used to enable clean operation. It will be cleared by hardware after clean operation done.*/ + uint32_t dcache_sync_done: 1; /*The bit is used to indicate clean/writeback/invalidate operation is finished.*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } dcache_sync_ctrl; + uint32_t dcache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with DCACHE_SYNC_SIZE_REG.*/ + union { + struct { + uint32_t dcache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with DCACHE_SYNC_ADDR_REG.*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } dcache_sync_size; + union { + struct { + uint32_t dcache_occupy_ena: 1; /*The bit is used to enable occupy operation. It will be cleared by hardware after issuing Auot-Invalidate Operation.*/ + uint32_t dcache_occupy_done: 1; /*The bit is used to indicate occupy operation is finished.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } dcache_occupy_ctrl; + uint32_t dcache_occupy_addr; /*The bits are used to configure the start virtual address for occupy operation. It should be combined with DCACHE_OCCUPY_SIZE_REG.*/ + union { + struct { + uint32_t dcache_occupy_size: 16; /*The bits are used to configure the length for occupy operation. The bits are the counts of cache block. It should be combined with DCACHE_OCCUPY_ADDR_REG.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } dcache_occupy_size; + union { + struct { + uint32_t dcache_preload_ena: 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/ + uint32_t dcache_preload_done: 1; /*The bit is used to indicate preload operation is finished.*/ + uint32_t dcache_preload_order: 1; /*The bit is used to configure the direction of preload operation. 1: descending 0: ascending.*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } dcache_preload_ctrl; + uint32_t dcache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with DCACHE_PRELOAD_SIZE_REG.*/ + union { + struct { + uint32_t dcache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with DCACHE_PRELOAD_ADDR_REG..*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } dcache_preload_size; + union { + struct { + uint32_t dcache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/ + uint32_t dcache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/ + uint32_t dcache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/ + uint32_t dcache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/ + uint32_t dcache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/ + uint32_t dcache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ + uint32_t dcache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } dcache_autoload_ctrl; + uint32_t dcache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ + union { + struct { + uint32_t dcache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ + uint32_t reserved27: 5; + }; + uint32_t val; + } dcache_autoload_sct0_size; + uint32_t dcache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ + union { + struct { + uint32_t dcache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ + uint32_t reserved27: 5; + }; + uint32_t val; + } dcache_autoload_sct1_size; + union { + struct { + uint32_t icache_enable: 1; /*The bit is used to activate the data cache. 0: disable 1: enable*/ + uint32_t icache_way_mode: 1; /*The bit is used to configure cache way mode.0: 4-way 1: 8-way*/ + uint32_t icache_size_mode: 1; /*The bit is used to configure cache memory size.0: 16KB 1: 32KB*/ + uint32_t icache_blocksize_mode: 1; /*The bit is used to configure cache block size.0: 16 bytes 1: 32 bytes*/ + uint32_t reserved4: 28; + }; + uint32_t val; + } icache_ctrl; + union { + struct { + uint32_t icache_shut_core0_bus: 1; /*The bit is used to disable core0 ibus 0: enable 1: disable*/ + uint32_t icache_shut_core1_bus: 1; /*The bit is used to disable core1 ibus 0: enable 1: disable*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } icache_ctrl1; + union { + struct { + uint32_t icache_tag_mem_force_on: 1; /*The bit is used to close clock gating of icache tag memory. 1: close gating 0: open clock gating.*/ + uint32_t icache_tag_mem_force_pd: 1; /*The bit is used to power icache tag memory down 0: follow rtc_lslp 1: power down*/ + uint32_t icache_tag_mem_force_pu: 1; /*The bit is used to power icache tag memory up 0: follow rtc_lslp 1: power up*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } icache_tag_power_ctrl; + union { + struct { + uint32_t icache_prelock_sct0_en: 1; /*The bit is used to enable the first section of prelock function.*/ + uint32_t icache_prelock_sct1_en: 1; /*The bit is used to enable the second section of prelock function.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } icache_prelock_ctrl; + uint32_t icache_prelock_sct0_addr; /*The bits are used to configure the first start virtual address of data prelock which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG*/ + uint32_t icache_prelock_sct1_addr; /*The bits are used to configure the second start virtual address of data prelock which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG*/ + union { + struct { + uint32_t icache_prelock_sct1_size: 16; /*The bits are used to configure the second length of data locking which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG*/ + uint32_t icache_prelock_sct0_size: 16; /*The bits are used to configure the first length of data locking which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG*/ + }; + uint32_t val; + } icache_prelock_sct_size; + union { + struct { + uint32_t icache_lock_ena: 1; /*The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.*/ + uint32_t icache_unlock_ena: 1; /*The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.*/ + uint32_t icache_lock_done: 1; /*The bit is used to indicate unlock/lock operation is finished.*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } icache_lock_ctrl; + uint32_t icache_lock_addr; /*The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.*/ + union { + struct { + uint32_t icache_lock_size: 16; /*The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } icache_lock_size; + union { + struct { + uint32_t icache_invalidate_ena: 1; /*The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.*/ + uint32_t icache_sync_done: 1; /*The bit is used to indicate invalidate operation is finished.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } icache_sync_ctrl; + uint32_t icache_sync_addr; /*The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.*/ + union { + struct { + uint32_t icache_sync_size: 23; /*The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } icache_sync_size; + union { + struct { + uint32_t icache_preload_ena: 1; /*The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.*/ + uint32_t icache_preload_done: 1; /*The bit is used to indicate preload operation is finished.*/ + uint32_t icache_preload_order: 1; /*The bit is used to configure the direction of preload operation. 1: descending 0: ascending.*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } icache_preload_ctrl; + uint32_t icache_preload_addr; /*The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.*/ + union { + struct { + uint32_t icache_preload_size: 16; /*The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } icache_preload_size; + union { + struct { + uint32_t icache_autoload_sct0_ena: 1; /*The bits are used to enable the first section for autoload operation.*/ + uint32_t icache_autoload_sct1_ena: 1; /*The bits are used to enable the second section for autoload operation.*/ + uint32_t icache_autoload_ena: 1; /*The bit is used to enable and disable autoload operation. It is combined with dcache_autoload_done. 1: enable 0: disable.*/ + uint32_t icache_autoload_done: 1; /*The bit is used to indicate autoload operation is finished.*/ + uint32_t icache_autoload_order: 1; /*The bits are used to configure the direction of autoload. 1: descending 0: ascending.*/ + uint32_t icache_autoload_rqst: 2; /*The bits are used to configure trigger conditions for autoload. 0/3: cache miss 1: cache hit 2: both cache miss and hit.*/ + uint32_t icache_autoload_size: 2; /*The bits are used to configure the numbers of the cache block for the issuing autoload operation.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } icache_autoload_ctrl; + uint32_t icache_autoload_sct0_addr; /*The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ + union { + struct { + uint32_t icache_autoload_sct0_size: 27; /*The bits are used to configure the length of the first section for autoload operation. It should be combined with dcache_autoload_sct0_ena.*/ + uint32_t reserved27: 5; + }; + uint32_t val; + } icache_autoload_sct0_size; + uint32_t icache_autoload_sct1_addr; /*The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ + union { + struct { + uint32_t icache_autoload_sct1_size: 27; /*The bits are used to configure the length of the second section for autoload operation. It should be combined with dcache_autoload_sct1_ena.*/ + uint32_t reserved27: 5; + }; + uint32_t val; + } icache_autoload_sct1_size; + uint32_t ibus_to_flash_start_vaddr; /*The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.*/ + uint32_t ibus_to_flash_end_vaddr; /*The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.*/ + uint32_t dbus_to_flash_start_vaddr; /*The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.*/ + uint32_t dbus_to_flash_end_vaddr; /*The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.*/ + union { + struct { + uint32_t dcache_acs_cnt_clr: 1; /*The bit is used to clear dcache counter.*/ + uint32_t icache_acs_cnt_clr: 1; /*The bit is used to clear icache counter.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } cache_acs_cnt_clr; + uint32_t ibus_acs_miss_cnt; /*The bits are used to count the number of the cache miss caused by ibus access flash/spiram.*/ + uint32_t ibus_acs_cnt; /*The bits are used to count the number of ibus access flash/spiram through icache.*/ + uint32_t dbus_acs_flash_miss_cnt; /*The bits are used to count the number of the cache miss caused by dbus access flash.*/ + uint32_t dbus_acs_spiram_miss_cnt; /*The bits are used to count the number of the cache miss caused by dbus access spiram.*/ + uint32_t dbus_acs_cnt; /*The bits are used to count the number of dbus access flash/spiram through dcache.*/ + union { + struct { + uint32_t icache_sync_op_fault: 1; /*The bit is used to enable interrupt by sync configurations fault.*/ + uint32_t icache_preload_op_fault: 1; /*The bit is used to enable interrupt by preload configurations fault.*/ + uint32_t dcache_sync_op_fault: 1; /*The bit is used to enable interrupt by sync configurations fault.*/ + uint32_t dcache_preload_op_fault: 1; /*The bit is used to enable interrupt by preload configurations fault.*/ + uint32_t dcache_write_flash: 1; /*The bit is used to enable interrupt by dcache trying to write flash.*/ + uint32_t mmu_entry_fault: 1; /*The bit is used to enable interrupt by mmu entry fault.*/ + uint32_t dcache_occupy_exc: 1; /*The bit is used to enable interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/ + uint32_t ibus_cnt_ovf: 1; /*The bit is used to enable interrupt by ibus counter overflow.*/ + uint32_t dbus_cnt_ovf: 1; /*The bit is used to enable interrupt by dbus counter overflow.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } cache_ilg_int_ena; + union { + struct { + uint32_t icache_sync_op_fault: 1; /*The bit is used to clear interrupt by sync configurations fault.*/ + uint32_t icache_preload_op_fault: 1; /*The bit is used to clear interrupt by preload configurations fault.*/ + uint32_t dcache_sync_op_fault: 1; /*The bit is used to clear interrupt by sync configurations fault.*/ + uint32_t dcache_preload_op_fault: 1; /*The bit is used to clear interrupt by preload configurations fault.*/ + uint32_t dcache_write_flash: 1; /*The bit is used to clear interrupt by dcache trying to write flash.*/ + uint32_t mmu_entry_fault: 1; /*The bit is used to clear interrupt by mmu entry fault.*/ + uint32_t dcache_occupy_exc: 1; /*The bit is used to clear interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/ + uint32_t ibus_cnt_ovf: 1; /*The bit is used to clear interrupt by ibus counter overflow.*/ + uint32_t dbus_cnt_ovf: 1; /*The bit is used to clear interrupt by dbus counter overflow.*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } cache_ilg_int_clr; + union { + struct { + uint32_t icache_sync_op_fault_st: 1; /*The bit is used to indicate interrupt by sync configurations fault.*/ + uint32_t icache_preload_op_fault_st: 1; /*The bit is used to indicate interrupt by preload configurations fault.*/ + uint32_t dcache_sync_op_fault_st: 1; /*The bit is used to indicate interrupt by sync configurations fault.*/ + uint32_t dcache_preload_op_fault_st: 1; /*The bit is used to indicate interrupt by preload configurations fault.*/ + uint32_t dcache_write_flash_st: 1; /*The bit is used to indicate interrupt by dcache trying to write flash.*/ + uint32_t mmu_entry_fault_st: 1; /*The bit is used to indicate interrupt by mmu entry fault.*/ + uint32_t dcache_occupy_exc_st: 1; /*The bit is used to indicate interrupt by dcache trying to replace a line whose blocks all have been occupied by occupy-mode.*/ + uint32_t ibus_acs_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.*/ + uint32_t ibus_acs_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.*/ + uint32_t dbus_acs_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.*/ + uint32_t dbus_acs_flash_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access flash miss counter overflow.*/ + uint32_t dbus_acs_spiram_miss_cnt_ovf_st: 1; /*The bit is used to indicate interrupt by dbus access spiram miss counter overflow.*/ + uint32_t reserved12: 20; + }; + uint32_t val; + } cache_ilg_int_st; + union { + struct { + uint32_t core0_ibus_acs_msk_ic: 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/ + uint32_t core0_ibus_wr_ic: 1; /*The bit is used to enable interrupt by ibus trying to write icache*/ + uint32_t core0_ibus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/ + uint32_t core0_dbus_acs_msk_dc: 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/ + uint32_t core0_dbus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_acs_cache_int_ena; + union { + struct { + uint32_t core0_ibus_acs_msk_ic: 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/ + uint32_t core0_ibus_wr_ic: 1; /*The bit is used to clear interrupt by ibus trying to write icache*/ + uint32_t core0_ibus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/ + uint32_t core0_dbus_acs_msk_dc: 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ + uint32_t core0_dbus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_acs_cache_int_clr; + union { + struct { + uint32_t core0_ibus_acs_msk_icache_st: 1; /*The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.*/ + uint32_t core0_ibus_wr_icache_st: 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/ + uint32_t core0_ibus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/ + uint32_t core0_dbus_acs_msk_dcache_st: 1; /*The bit is used to indicate interrupt by cpu access dcache while the core0_dbus is disabled or dcache is disabled which include speculative access.*/ + uint32_t core0_dbus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_acs_cache_int_st; + union { + struct { + uint32_t core1_ibus_acs_msk_ic: 1; /*The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.*/ + uint32_t core1_ibus_wr_ic: 1; /*The bit is used to enable interrupt by ibus trying to write icache*/ + uint32_t core1_ibus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/ + uint32_t core1_dbus_acs_msk_dc: 1; /*The bit is used to enable interrupt by cpu access dcache while the corresponding dbus is disabled which include speculative access.*/ + uint32_t core1_dbus_reject: 1; /*The bit is used to enable interrupt by authentication fail.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_acs_cache_int_ena; + union { + struct { + uint32_t core1_ibus_acs_msk_ic: 1; /*The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.*/ + uint32_t core1_ibus_wr_ic: 1; /*The bit is used to clear interrupt by ibus trying to write icache*/ + uint32_t core1_ibus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/ + uint32_t core1_dbus_acs_msk_dc: 1; /*The bit is used to clear interrupt by cpu access dcache while the corresponding dbus is disabled or dcache is disabled which include speculative access.*/ + uint32_t core1_dbus_reject: 1; /*The bit is used to clear interrupt by authentication fail.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_acs_cache_int_clr; + union { + struct { + uint32_t core1_ibus_acs_msk_icache_st: 1; /*The bit is used to indicate interrupt by cpu access icache while the core1_ibus is disabled or icache is disabled which include speculative access.*/ + uint32_t core1_ibus_wr_icache_st: 1; /*The bit is used to indicate interrupt by ibus trying to write icache*/ + uint32_t core1_ibus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/ + uint32_t core1_dbus_acs_msk_dcache_st: 1; /*The bit is used to indicate interrupt by cpu access dcache while the core1_dbus is disabled or dcache is disabled which include speculative access.*/ + uint32_t core1_dbus_reject_st: 1; /*The bit is used to indicate interrupt by authentication fail.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_acs_cache_int_st; + union { + struct { + uint32_t core0_dbus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ + uint32_t core0_dbus_attr: 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ + uint32_t core0_dbus_world: 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0 1: WORLD1*/ + uint32_t reserved7: 25; + }; + uint32_t val; + } core0_dbus_reject_st; + uint32_t core0_dbus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access dbus when authentication fail.*/ + union { + struct { + uint32_t core0_ibus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ + uint32_t core0_ibus_attr: 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ + uint32_t core0_ibus_world: 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0 1: WORLD1*/ + uint32_t reserved7: 25; + }; + uint32_t val; + } core0_ibus_reject_st; + uint32_t core0_ibus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access ibus when authentication fail.*/ + union { + struct { + uint32_t core1_dbus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ + uint32_t core1_dbus_attr: 3; /*The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ + uint32_t core1_dbus_world: 1; /*The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0 1: WORLD1*/ + uint32_t reserved7: 25; + }; + uint32_t val; + } core1_dbus_reject_st; + uint32_t core1_dbus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access dbus when authentication fail.*/ + union { + struct { + uint32_t core1_ibus_tag_attr: 3; /*The bits are used to indicate the attribute of data from external memory when authentication fail. 0: invalidate 1: execute-able 2: read-able 4: write-able.*/ + uint32_t core1_ibus_attr: 3; /*The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate 1: execute-able 2: read-able*/ + uint32_t core1_ibus_world: 1; /*The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0 1: WORLD1*/ + uint32_t reserved7: 25; + }; + uint32_t val; + } core1_ibus_reject_st; + uint32_t core1_ibus_reject_vaddr; /*The bits are used to indicate the virtual address of CPU access ibus when authentication fail.*/ + union { + struct { + uint32_t cache_mmu_fault_content: 16; /*The bits are used to indicate the content of mmu entry which cause mmu fault..*/ + uint32_t cache_mmu_fault_code: 4; /*The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default 1: cpu miss 2: preload miss 3: writeback 4: cpu miss evict recovery address 5: load miss evict recovery address 6: external dma tx 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } cache_mmu_fault_content; + uint32_t cache_mmu_fault_vaddr; /*The bits are used to indicate the virtual address which cause mmu fault..*/ + union { + struct { + uint32_t cache_flash_wrap_around: 1; /*The bit is used to enable wrap around mode when read data from flash.*/ + uint32_t cache_sram_rd_wrap_around: 1; /*The bit is used to enable wrap around mode when read data from spiram.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } cache_wrap_around_ctrl; + union { + struct { + uint32_t cache_mmu_mem_force_on: 1; /*The bit is used to enable clock gating to save power when access mmu memory 0: enable 1: disable*/ + uint32_t cache_mmu_mem_force_pd: 1; /*The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power down*/ + uint32_t cache_mmu_mem_force_pu: 1; /*The bit is used to power mmu memory down 0: follow_rtc_lslp_pd 1: power up*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } cache_mmu_power_ctrl; + union { + struct { + uint32_t icache_state: 12; /*The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/ + uint32_t dcache_state: 12; /*The bit is used to indicate whether dcache main fsm is in idle state or not. 1: in idle state 0: not in idle state*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } cache_state; + union { + struct { + uint32_t record_disable_db_encrypt: 1; /*Reserved.*/ + uint32_t record_disable_g0cb_decrypt: 1; /*Reserved.*/ + uint32_t reserved2: 30; + }; + uint32_t val; + } cache_encrypt_decrypt_record_disable; + union { + struct { + uint32_t clk_force_on_manual_crypt: 1; /*The bit is used to close clock gating of manual crypt clock. 1: close gating 0: open clock gating.*/ + uint32_t clk_force_on_auto_crypt: 1; /*The bit is used to close clock gating of automatic crypt clock. 1: close gating 0: open clock gating.*/ + uint32_t clk_force_on_crypt: 1; /*The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating 0: open clock gating.*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } cache_encrypt_decrypt_clk_force_on; + union { + struct { + uint32_t alloc_wb_hold_arbiter: 1; /*Reserved.*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } cache_bridge_arbiter_ctrl; + union { + struct { + uint32_t icache_preload: 1; /*The bit is used to indicate the interrupt by icache pre-load done.*/ + uint32_t icache_preload: 1; /*The bit is used to enable the interrupt by icache pre-load done.*/ + uint32_t icache_preload: 1; /*The bit is used to clear the interrupt by icache pre-load done.*/ + uint32_t dcache_preload: 1; /*The bit is used to indicate the interrupt by dcache pre-load done.*/ + uint32_t dcache_preload: 1; /*The bit is used to enable the interrupt by dcache pre-load done.*/ + uint32_t dcache_preload: 1; /*The bit is used to clear the interrupt by dcache pre-load done.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } cache_preload_int_ctrl; + union { + struct { + uint32_t icache_sync: 1; /*The bit is used to indicate the interrupt by icache sync done.*/ + uint32_t icache_sync: 1; /*The bit is used to enable the interrupt by icache sync done.*/ + uint32_t icache_sync: 1; /*The bit is used to clear the interrupt by icache sync done.*/ + uint32_t dcache_sync: 1; /*The bit is used to indicate the interrupt by dcache sync done.*/ + uint32_t dcache_sync: 1; /*The bit is used to enable the interrupt by dcache sync done.*/ + uint32_t dcache_sync: 1; /*The bit is used to clear the interrupt by dcache sync done.*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } cache_sync_int_ctrl; + union { + struct { + uint32_t cache_mmu_owner: 24; /*The bits are used to specify the owner of MMU.bit0: icache bit1: dcache bit2: dma bit3: reserved.*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } cache_mmu_owner; + union { + struct { + uint32_t cache_ignore_preload_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by preload operation.*/ + uint32_t cache_ignore_sync_mmu_entry_fault: 1; /*The bit is used to disable checking mmu entry fault by sync operation.*/ + uint32_t cache_trace_ena: 1; /*The bit is used to enable cache trace function.*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } cache_conf_misc; + union { + struct { + uint32_t dcache_freeze_ena: 1; /*The bit is used to enable dcache freeze mode*/ + uint32_t dcache_freeze_mode: 1; /*The bit is used to configure freeze mode 0: assert busy if CPU miss 1: assert hit if CPU miss*/ + uint32_t dcache_freeze_done: 1; /*The bit is used to indicate dcache freeze success*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } dcache_freeze; + union { + struct { + uint32_t icache_freeze_ena: 1; /*The bit is used to enable icache freeze mode*/ + uint32_t icache_freeze_mode: 1; /*The bit is used to configure freeze mode 0: assert busy if CPU miss 1: assert hit if CPU miss*/ + uint32_t icache_freeze_done: 1; /*The bit is used to indicate icache freeze success*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } icache_freeze; + union { + struct { + uint32_t icache_atomic_operate_ena: 1; /*The bit is used to activate icache atomic operation protection. In this case sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } icache_atomic_operate_ena; + union { + struct { + uint32_t dcache_atomic_operate_ena: 1; /*The bit is used to activate dcache atomic operation protection. In this case sync/lock/occupy operation can not interrupt miss-work. This feature does not work during invalidateAll operation.*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } dcache_atomic_operate_ena; + union { + struct { + uint32_t cache_request_bypass: 1; /*The bit is used to disable request recording which could cause performance issue*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } cache_request; + union { + struct { + uint32_t clk_en: 1; /*Reserved.*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } clock_gate; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + union { + struct { + uint32_t date: 28; /*Reserved.*/ + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} extmem_dev_t; + +extern extmem_dev_t EXTMEM; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/fe_reg.h b/components/soc/soc/esp32s3/include/soc/fe_reg.h new file mode 100644 index 000000000..5d76651de --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/fe_reg.h @@ -0,0 +1,41 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the RF frontend control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define FE_GEN_CTRL (DR_REG_FE_BASE + 0x0090) +#define FE_IQ_EST_FORCE_PU (BIT(5)) +#define FE_IQ_EST_FORCE_PU_M (BIT(5)) +#define FE_IQ_EST_FORCE_PU_V 1 +#define FE_IQ_EST_FORCE_PU_S 5 +#define FE_IQ_EST_FORCE_PD (BIT(4)) +#define FE_IQ_EST_FORCE_PD_M (BIT(4)) +#define FE_IQ_EST_FORCE_PD_V 1 +#define FE_IQ_EST_FORCE_PD_S 4 + +#define FE2_TX_INTERP_CTRL (DR_REG_FE2_BASE + 0x00f0) +#define FE2_TX_INF_FORCE_PU (BIT(10)) +#define FE2_TX_INF_FORCE_PU_M (BIT(10)) +#define FE2_TX_INF_FORCE_PU_V 1 +#define FE2_TX_INF_FORCE_PU_S 10 +#define FE2_TX_INF_FORCE_PD (BIT(9)) +#define FE2_TX_INF_FORCE_PD_M (BIT(9)) +#define FE2_TX_INF_FORCE_PD_V 1 +#define FE2_TX_INF_FORCE_PD_S 9 diff --git a/components/soc/soc/esp32s3/include/soc/gpio_caps.h b/components/soc/soc/esp32s3/include/soc/gpio_caps.h new file mode 100644 index 000000000..16375c58c --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/gpio_caps.h @@ -0,0 +1,45 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32-S3 has 1 GPIO peripheral +#define SOC_GPIO_PORT (1) +#define GPIO_PIN_COUNT (48) + +// On ESP32 those PADs which have RTC functions must set pullup/down/capability via RTC register. +// On ESP32-S3, Digital IOs have their own registers to control pullup/down/capability, independent with RTC registers. +#define GPIO_SUPPORTS_RTC_INDEPENDENT (1) +// Force hold is a new function of ESP32-S3 +#define GPIO_SUPPORTS_FORCE_HOLD (1) + +#define GPIO_PRO_CPU_INTR_ENA (BIT(0)) +#define GPIO_PRO_CPU_NMI_INTR_ENA (BIT(1)) + +#define GPIO_MODE_DEF_DISABLE (0) +#define GPIO_MODE_DEF_INPUT (BIT0) +#define GPIO_MODE_DEF_OUTPUT (BIT1) +#define GPIO_MODE_DEF_OD (BIT2) + +#define GPIO_IS_VALID_GPIO(gpio_num) ((gpio_num < GPIO_PIN_COUNT && GPIO_PIN_MUX_REG[gpio_num] != 0)) /*!< Check whether it is a valid GPIO number */ +#define GPIO_IS_VALID_OUTPUT_GPIO(gpio_num) ((GPIO_IS_VALID_GPIO(gpio_num)) && (gpio_num < 46)) /*!< Check whether it can be a valid GPIO number of output mode */ +#define GPIO_MASK_CONTAIN_INPUT_GPIO(gpio_mask) ((gpio_mask & (GPIO_SEL_46))) /*!< Check whether it contains input io */ + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/gpio_reg.h b/components/soc/soc/esp32s3/include/soc/gpio_reg.h new file mode 100644 index 000000000..ac2b0ee3a --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/gpio_reg.h @@ -0,0 +1,9216 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define GPIO_PIN_CONFIG_MSB 12 +#define GPIO_PIN_CONFIG_LSB 11 +#define GPIO_PIN_CONFIG_MASK 0x00001800 +#define GPIO_PIN_CONFIG_GET(x) (((x) & GPIO_PIN_CONFIG_MASK) >> GPIO_PIN_CONFIG_LSB) +#define GPIO_PIN_CONFIG_SET(x) (((x) << GPIO_PIN_CONFIG_LSB) & GPIO_PIN_CONFIG_MASK) + +#define GPIO_WAKEUP_ENABLE 1 +#define GPIO_WAKEUP_DISABLE (~GPIO_WAKEUP_ENABLE) +#define GPIO_PIN_WAKEUP_ENABLE_MSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_LSB 10 +#define GPIO_PIN_WAKEUP_ENABLE_MASK 0x00000400 +#define GPIO_PIN_WAKEUP_ENABLE_GET(x) (((x) & GPIO_PIN_WAKEUP_ENABLE_MASK) >> GPIO_PIN_WAKEUP_ENABLE_LSB) +#define GPIO_PIN_WAKEUP_ENABLE_SET(x) (((x) << GPIO_PIN_WAKEUP_ENABLE_LSB) & GPIO_PIN_WAKEUP_ENABLE_MASK) + +#define GPIO_PIN_INT_TYPE_MASK 0x380 +#define GPIO_PIN_INT_TYPE_MSB 9 +#define GPIO_PIN_INT_TYPE_LSB 7 +#define GPIO_PIN_INT_TYPE_GET(x) (((x) & GPIO_PIN_INT_TYPE_MASK) >> GPIO_PIN_INT_TYPE_LSB) +#define GPIO_PIN_INT_TYPE_SET(x) (((x) << GPIO_PIN_INT_TYPE_LSB) & GPIO_PIN_INT_TYPE_MASK) + +#define GPIO_PAD_DRIVER_ENABLE 1 +#define GPIO_PAD_DRIVER_DISABLE (~GPIO_PAD_DRIVER_ENABLE) +#define GPIO_PIN_PAD_DRIVER_MSB 2 +#define GPIO_PIN_PAD_DRIVER_LSB 2 +#define GPIO_PIN_PAD_DRIVER_MASK 0x00000004 +#define GPIO_PIN_PAD_DRIVER_GET(x) (((x) & GPIO_PIN_PAD_DRIVER_MASK) >> GPIO_PIN_PAD_DRIVER_LSB) +#define GPIO_PIN_PAD_DRIVER_SET(x) (((x) << GPIO_PIN_PAD_DRIVER_LSB) & GPIO_PIN_PAD_DRIVER_MASK) + +#define GPIO_BT_SELECT_REG (DR_REG_GPIO_BASE + 0x0) +/* GPIO_BT_SEL : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_BT_SEL 0xFFFFFFFF +#define GPIO_BT_SEL_M ((GPIO_BT_SEL_V)<<(GPIO_BT_SEL_S)) +#define GPIO_BT_SEL_V 0xFFFFFFFF +#define GPIO_BT_SEL_S 0 + +#define GPIO_OUT_REG (DR_REG_GPIO_BASE + 0x4) +/* GPIO_OUT_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_OUT_DATA 0xFFFFFFFF +#define GPIO_OUT_DATA_M ((GPIO_OUT_DATA_V)<<(GPIO_OUT_DATA_S)) +#define GPIO_OUT_DATA_V 0xFFFFFFFF +#define GPIO_OUT_DATA_S 0 + +#define GPIO_OUT_W1TS_REG (DR_REG_GPIO_BASE + 0x8) +/* GPIO_OUT_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_OUT_W1TS 0xFFFFFFFF +#define GPIO_OUT_W1TS_M ((GPIO_OUT_W1TS_V)<<(GPIO_OUT_W1TS_S)) +#define GPIO_OUT_W1TS_V 0xFFFFFFFF +#define GPIO_OUT_W1TS_S 0 + +#define GPIO_OUT_W1TC_REG (DR_REG_GPIO_BASE + 0xC) +/* GPIO_OUT_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_OUT_W1TC 0xFFFFFFFF +#define GPIO_OUT_W1TC_M ((GPIO_OUT_W1TC_V)<<(GPIO_OUT_W1TC_S)) +#define GPIO_OUT_W1TC_V 0xFFFFFFFF +#define GPIO_OUT_W1TC_S 0 + +#define GPIO_OUT1_REG (DR_REG_GPIO_BASE + 0x10) +/* GPIO_OUT1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_OUT1_DATA 0x003FFFFF +#define GPIO_OUT1_DATA_M ((GPIO_OUT1_DATA_V)<<(GPIO_OUT1_DATA_S)) +#define GPIO_OUT1_DATA_V 0x3FFFFF +#define GPIO_OUT1_DATA_S 0 + +#define GPIO_OUT1_W1TS_REG (DR_REG_GPIO_BASE + 0x14) +/* GPIO_OUT1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_OUT1_W1TS 0x003FFFFF +#define GPIO_OUT1_W1TS_M ((GPIO_OUT1_W1TS_V)<<(GPIO_OUT1_W1TS_S)) +#define GPIO_OUT1_W1TS_V 0x3FFFFF +#define GPIO_OUT1_W1TS_S 0 + +#define GPIO_OUT1_W1TC_REG (DR_REG_GPIO_BASE + 0x18) +/* GPIO_OUT1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_OUT1_W1TC 0x003FFFFF +#define GPIO_OUT1_W1TC_M ((GPIO_OUT1_W1TC_V)<<(GPIO_OUT1_W1TC_S)) +#define GPIO_OUT1_W1TC_V 0x3FFFFF +#define GPIO_OUT1_W1TC_S 0 + +#define GPIO_SDIO_SELECT_REG (DR_REG_GPIO_BASE + 0x1C) +/* GPIO_SDIO_SEL : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SDIO_SEL 0x000000FF +#define GPIO_SDIO_SEL_M ((GPIO_SDIO_SEL_V)<<(GPIO_SDIO_SEL_S)) +#define GPIO_SDIO_SEL_V 0xFF +#define GPIO_SDIO_SEL_S 0 + +#define GPIO_ENABLE_REG (DR_REG_GPIO_BASE + 0x20) +/* GPIO_ENABLE_DATA : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_ENABLE_DATA 0xFFFFFFFF +#define GPIO_ENABLE_DATA_M ((GPIO_ENABLE_DATA_V)<<(GPIO_ENABLE_DATA_S)) +#define GPIO_ENABLE_DATA_V 0xFFFFFFFF +#define GPIO_ENABLE_DATA_S 0 + +#define GPIO_ENABLE_W1TS_REG (DR_REG_GPIO_BASE + 0x24) +/* GPIO_ENABLE_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_ENABLE_W1TS 0xFFFFFFFF +#define GPIO_ENABLE_W1TS_M ((GPIO_ENABLE_W1TS_V)<<(GPIO_ENABLE_W1TS_S)) +#define GPIO_ENABLE_W1TS_V 0xFFFFFFFF +#define GPIO_ENABLE_W1TS_S 0 + +#define GPIO_ENABLE_W1TC_REG (DR_REG_GPIO_BASE + 0x28) +/* GPIO_ENABLE_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_ENABLE_W1TC 0xFFFFFFFF +#define GPIO_ENABLE_W1TC_M ((GPIO_ENABLE_W1TC_V)<<(GPIO_ENABLE_W1TC_S)) +#define GPIO_ENABLE_W1TC_V 0xFFFFFFFF +#define GPIO_ENABLE_W1TC_S 0 + +#define GPIO_ENABLE1_REG (DR_REG_GPIO_BASE + 0x2C) +/* GPIO_ENABLE1_DATA : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_ENABLE1_DATA 0x003FFFFF +#define GPIO_ENABLE1_DATA_M ((GPIO_ENABLE1_DATA_V)<<(GPIO_ENABLE1_DATA_S)) +#define GPIO_ENABLE1_DATA_V 0x3FFFFF +#define GPIO_ENABLE1_DATA_S 0 + +#define GPIO_ENABLE1_W1TS_REG (DR_REG_GPIO_BASE + 0x30) +/* GPIO_ENABLE1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_ENABLE1_W1TS 0x003FFFFF +#define GPIO_ENABLE1_W1TS_M ((GPIO_ENABLE1_W1TS_V)<<(GPIO_ENABLE1_W1TS_S)) +#define GPIO_ENABLE1_W1TS_V 0x3FFFFF +#define GPIO_ENABLE1_W1TS_S 0 + +#define GPIO_ENABLE1_W1TC_REG (DR_REG_GPIO_BASE + 0x34) +/* GPIO_ENABLE1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_ENABLE1_W1TC 0x003FFFFF +#define GPIO_ENABLE1_W1TC_M ((GPIO_ENABLE1_W1TC_V)<<(GPIO_ENABLE1_W1TC_S)) +#define GPIO_ENABLE1_W1TC_V 0x3FFFFF +#define GPIO_ENABLE1_W1TC_S 0 + +#define GPIO_STRAP_REG (DR_REG_GPIO_BASE + 0x38) +/* GPIO_STRAPPING : RO ;bitpos:[15:0] ;default: ; */ +/*description: */ +#define GPIO_STRAPPING 0x0000FFFF +#define GPIO_STRAPPING_M ((GPIO_STRAPPING_V)<<(GPIO_STRAPPING_S)) +#define GPIO_STRAPPING_V 0xFFFF +#define GPIO_STRAPPING_S 0 + +#define GPIO_IN_REG (DR_REG_GPIO_BASE + 0x3C) +/* GPIO_IN_DATA : RO ;bitpos:[31:0] ;default: ; */ +/*description: */ +#define GPIO_IN_DATA 0xFFFFFFFF +#define GPIO_IN_DATA_M ((GPIO_IN_DATA_V)<<(GPIO_IN_DATA_S)) +#define GPIO_IN_DATA_V 0xFFFFFFFF +#define GPIO_IN_DATA_S 0 + +#define GPIO_IN1_REG (DR_REG_GPIO_BASE + 0x40) +/* GPIO_IN1_DATA : RO ;bitpos:[21:0] ;default: ; */ +/*description: */ +#define GPIO_IN1_DATA 0x003FFFFF +#define GPIO_IN1_DATA_M ((GPIO_IN1_DATA_V)<<(GPIO_IN1_DATA_S)) +#define GPIO_IN1_DATA_V 0x3FFFFF +#define GPIO_IN1_DATA_S 0 + +#define GPIO_STATUS_REG (DR_REG_GPIO_BASE + 0x44) +/* GPIO_STATUS_INT : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_STATUS_INT 0xFFFFFFFF +#define GPIO_STATUS_INT_M ((GPIO_STATUS_INT_V)<<(GPIO_STATUS_INT_S)) +#define GPIO_STATUS_INT_V 0xFFFFFFFF +#define GPIO_STATUS_INT_S 0 + +#define GPIO_STATUS_W1TS_REG (DR_REG_GPIO_BASE + 0x48) +/* GPIO_STATUS_W1TS : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_STATUS_W1TS 0xFFFFFFFF +#define GPIO_STATUS_W1TS_M ((GPIO_STATUS_W1TS_V)<<(GPIO_STATUS_W1TS_S)) +#define GPIO_STATUS_W1TS_V 0xFFFFFFFF +#define GPIO_STATUS_W1TS_S 0 + +#define GPIO_STATUS_W1TC_REG (DR_REG_GPIO_BASE + 0x4C) +/* GPIO_STATUS_W1TC : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_STATUS_W1TC 0xFFFFFFFF +#define GPIO_STATUS_W1TC_M ((GPIO_STATUS_W1TC_V)<<(GPIO_STATUS_W1TC_S)) +#define GPIO_STATUS_W1TC_V 0xFFFFFFFF +#define GPIO_STATUS_W1TC_S 0 + +#define GPIO_STATUS1_REG (DR_REG_GPIO_BASE + 0x50) +/* GPIO_STATUS1_INT : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_STATUS1_INT 0x003FFFFF +#define GPIO_STATUS1_INT_M ((GPIO_STATUS1_INT_V)<<(GPIO_STATUS1_INT_S)) +#define GPIO_STATUS1_INT_V 0x3FFFFF +#define GPIO_STATUS1_INT_S 0 + +#define GPIO_STATUS1_W1TS_REG (DR_REG_GPIO_BASE + 0x54) +/* GPIO_STATUS1_W1TS : WO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_STATUS1_W1TS 0x003FFFFF +#define GPIO_STATUS1_W1TS_M ((GPIO_STATUS1_W1TS_V)<<(GPIO_STATUS1_W1TS_S)) +#define GPIO_STATUS1_W1TS_V 0x3FFFFF +#define GPIO_STATUS1_W1TS_S 0 + +#define GPIO_STATUS1_W1TC_REG (DR_REG_GPIO_BASE + 0x58) +/* GPIO_STATUS1_W1TC : WO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_STATUS1_W1TC 0x003FFFFF +#define GPIO_STATUS1_W1TC_M ((GPIO_STATUS1_W1TC_V)<<(GPIO_STATUS1_W1TC_S)) +#define GPIO_STATUS1_W1TC_V 0x3FFFFF +#define GPIO_STATUS1_W1TC_S 0 + +#define GPIO_PCPU_INT_REG (DR_REG_GPIO_BASE + 0x5C) +/* GPIO_PROCPU_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_PROCPU_INT 0xFFFFFFFF +#define GPIO_PROCPU_INT_M ((GPIO_PROCPU_INT_V)<<(GPIO_PROCPU_INT_S)) +#define GPIO_PROCPU_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_INT_S 0 + +#define GPIO_PCPU_NMI_INT_REG (DR_REG_GPIO_BASE + 0x60) +/* GPIO_PROCPU_NMI_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_PROCPU_NMI_INT 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_M ((GPIO_PROCPU_NMI_INT_V)<<(GPIO_PROCPU_NMI_INT_S)) +#define GPIO_PROCPU_NMI_INT_V 0xFFFFFFFF +#define GPIO_PROCPU_NMI_INT_S 0 + +#define GPIO_CPUSDIO_INT_REG (DR_REG_GPIO_BASE + 0x64) +/* GPIO_SDIO_INT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_SDIO_INT 0xFFFFFFFF +#define GPIO_SDIO_INT_M ((GPIO_SDIO_INT_V)<<(GPIO_SDIO_INT_S)) +#define GPIO_SDIO_INT_V 0xFFFFFFFF +#define GPIO_SDIO_INT_S 0 + +#define GPIO_PCPU_INT1_REG (DR_REG_GPIO_BASE + 0x68) +/* GPIO_PROCPU_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_PROCPU_INT_H 0x003FFFFF +#define GPIO_PROCPU_INT_H_M ((GPIO_PROCPU_INT_H_V)<<(GPIO_PROCPU_INT_H_S)) +#define GPIO_PROCPU_INT_H_V 0x3FFFFF +#define GPIO_PROCPU_INT_H_S 0 + +#define GPIO_PCPU_NMI_INT1_REG (DR_REG_GPIO_BASE + 0x6C) +/* GPIO_PROCPU_NMI_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_PROCPU_NMI_INT_H 0x003FFFFF +#define GPIO_PROCPU_NMI_INT_H_M ((GPIO_PROCPU_NMI_INT_H_V)<<(GPIO_PROCPU_NMI_INT_H_S)) +#define GPIO_PROCPU_NMI_INT_H_V 0x3FFFFF +#define GPIO_PROCPU_NMI_INT_H_S 0 + +#define GPIO_CPUSDIO_INT1_REG (DR_REG_GPIO_BASE + 0x70) +/* GPIO_SDIO_INT_H : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_SDIO_INT_H 0x003FFFFF +#define GPIO_SDIO_INT_H_M ((GPIO_SDIO_INT_H_V)<<(GPIO_SDIO_INT_H_S)) +#define GPIO_SDIO_INT_H_V 0x3FFFFF +#define GPIO_SDIO_INT_H_S 0 + +#define GPIO_PIN0_REG (DR_REG_GPIO_BASE + 0x74) +/* GPIO_PIN0_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN0_INT_ENA 0x0000001F +#define GPIO_PIN0_INT_ENA_M ((GPIO_PIN0_INT_ENA_V)<<(GPIO_PIN0_INT_ENA_S)) +#define GPIO_PIN0_INT_ENA_V 0x1F +#define GPIO_PIN0_INT_ENA_S 13 +/* GPIO_PIN0_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN0_CONFIG 0x00000003 +#define GPIO_PIN0_CONFIG_M ((GPIO_PIN0_CONFIG_V)<<(GPIO_PIN0_CONFIG_S)) +#define GPIO_PIN0_CONFIG_V 0x3 +#define GPIO_PIN0_CONFIG_S 11 +/* GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN0_INT_TYPE 0x00000007 +#define GPIO_PIN0_INT_TYPE_M ((GPIO_PIN0_INT_TYPE_V)<<(GPIO_PIN0_INT_TYPE_S)) +#define GPIO_PIN0_INT_TYPE_V 0x7 +#define GPIO_PIN0_INT_TYPE_S 7 +/* GPIO_PIN0_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN0_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC1_BYPASS_M ((GPIO_PIN0_SYNC1_BYPASS_V)<<(GPIO_PIN0_SYNC1_BYPASS_S)) +#define GPIO_PIN0_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC1_BYPASS_S 3 +/* GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN0_PAD_DRIVER_V 0x1 +#define GPIO_PIN0_PAD_DRIVER_S 2 +/* GPIO_PIN0_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN0_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN0_SYNC2_BYPASS_M ((GPIO_PIN0_SYNC2_BYPASS_V)<<(GPIO_PIN0_SYNC2_BYPASS_S)) +#define GPIO_PIN0_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN0_SYNC2_BYPASS_S 0 + +#define GPIO_PIN1_REG (DR_REG_GPIO_BASE + 0x78) +/* GPIO_PIN1_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN1_INT_ENA 0x0000001F +#define GPIO_PIN1_INT_ENA_M ((GPIO_PIN1_INT_ENA_V)<<(GPIO_PIN1_INT_ENA_S)) +#define GPIO_PIN1_INT_ENA_V 0x1F +#define GPIO_PIN1_INT_ENA_S 13 +/* GPIO_PIN1_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN1_CONFIG 0x00000003 +#define GPIO_PIN1_CONFIG_M ((GPIO_PIN1_CONFIG_V)<<(GPIO_PIN1_CONFIG_S)) +#define GPIO_PIN1_CONFIG_V 0x3 +#define GPIO_PIN1_CONFIG_S 11 +/* GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN1_INT_TYPE 0x00000007 +#define GPIO_PIN1_INT_TYPE_M ((GPIO_PIN1_INT_TYPE_V)<<(GPIO_PIN1_INT_TYPE_S)) +#define GPIO_PIN1_INT_TYPE_V 0x7 +#define GPIO_PIN1_INT_TYPE_S 7 +/* GPIO_PIN1_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN1_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC1_BYPASS_M ((GPIO_PIN1_SYNC1_BYPASS_V)<<(GPIO_PIN1_SYNC1_BYPASS_S)) +#define GPIO_PIN1_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC1_BYPASS_S 3 +/* GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN1_PAD_DRIVER_V 0x1 +#define GPIO_PIN1_PAD_DRIVER_S 2 +/* GPIO_PIN1_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN1_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN1_SYNC2_BYPASS_M ((GPIO_PIN1_SYNC2_BYPASS_V)<<(GPIO_PIN1_SYNC2_BYPASS_S)) +#define GPIO_PIN1_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN1_SYNC2_BYPASS_S 0 + +#define GPIO_PIN2_REG (DR_REG_GPIO_BASE + 0x7C) +/* GPIO_PIN2_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN2_INT_ENA 0x0000001F +#define GPIO_PIN2_INT_ENA_M ((GPIO_PIN2_INT_ENA_V)<<(GPIO_PIN2_INT_ENA_S)) +#define GPIO_PIN2_INT_ENA_V 0x1F +#define GPIO_PIN2_INT_ENA_S 13 +/* GPIO_PIN2_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN2_CONFIG 0x00000003 +#define GPIO_PIN2_CONFIG_M ((GPIO_PIN2_CONFIG_V)<<(GPIO_PIN2_CONFIG_S)) +#define GPIO_PIN2_CONFIG_V 0x3 +#define GPIO_PIN2_CONFIG_S 11 +/* GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN2_INT_TYPE 0x00000007 +#define GPIO_PIN2_INT_TYPE_M ((GPIO_PIN2_INT_TYPE_V)<<(GPIO_PIN2_INT_TYPE_S)) +#define GPIO_PIN2_INT_TYPE_V 0x7 +#define GPIO_PIN2_INT_TYPE_S 7 +/* GPIO_PIN2_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN2_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC1_BYPASS_M ((GPIO_PIN2_SYNC1_BYPASS_V)<<(GPIO_PIN2_SYNC1_BYPASS_S)) +#define GPIO_PIN2_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC1_BYPASS_S 3 +/* GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN2_PAD_DRIVER_V 0x1 +#define GPIO_PIN2_PAD_DRIVER_S 2 +/* GPIO_PIN2_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN2_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN2_SYNC2_BYPASS_M ((GPIO_PIN2_SYNC2_BYPASS_V)<<(GPIO_PIN2_SYNC2_BYPASS_S)) +#define GPIO_PIN2_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN2_SYNC2_BYPASS_S 0 + +#define GPIO_PIN3_REG (DR_REG_GPIO_BASE + 0x80) +/* GPIO_PIN3_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN3_INT_ENA 0x0000001F +#define GPIO_PIN3_INT_ENA_M ((GPIO_PIN3_INT_ENA_V)<<(GPIO_PIN3_INT_ENA_S)) +#define GPIO_PIN3_INT_ENA_V 0x1F +#define GPIO_PIN3_INT_ENA_S 13 +/* GPIO_PIN3_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN3_CONFIG 0x00000003 +#define GPIO_PIN3_CONFIG_M ((GPIO_PIN3_CONFIG_V)<<(GPIO_PIN3_CONFIG_S)) +#define GPIO_PIN3_CONFIG_V 0x3 +#define GPIO_PIN3_CONFIG_S 11 +/* GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN3_INT_TYPE 0x00000007 +#define GPIO_PIN3_INT_TYPE_M ((GPIO_PIN3_INT_TYPE_V)<<(GPIO_PIN3_INT_TYPE_S)) +#define GPIO_PIN3_INT_TYPE_V 0x7 +#define GPIO_PIN3_INT_TYPE_S 7 +/* GPIO_PIN3_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN3_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC1_BYPASS_M ((GPIO_PIN3_SYNC1_BYPASS_V)<<(GPIO_PIN3_SYNC1_BYPASS_S)) +#define GPIO_PIN3_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC1_BYPASS_S 3 +/* GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN3_PAD_DRIVER_V 0x1 +#define GPIO_PIN3_PAD_DRIVER_S 2 +/* GPIO_PIN3_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN3_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN3_SYNC2_BYPASS_M ((GPIO_PIN3_SYNC2_BYPASS_V)<<(GPIO_PIN3_SYNC2_BYPASS_S)) +#define GPIO_PIN3_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN3_SYNC2_BYPASS_S 0 + +#define GPIO_PIN4_REG (DR_REG_GPIO_BASE + 0x84) +/* GPIO_PIN4_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN4_INT_ENA 0x0000001F +#define GPIO_PIN4_INT_ENA_M ((GPIO_PIN4_INT_ENA_V)<<(GPIO_PIN4_INT_ENA_S)) +#define GPIO_PIN4_INT_ENA_V 0x1F +#define GPIO_PIN4_INT_ENA_S 13 +/* GPIO_PIN4_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN4_CONFIG 0x00000003 +#define GPIO_PIN4_CONFIG_M ((GPIO_PIN4_CONFIG_V)<<(GPIO_PIN4_CONFIG_S)) +#define GPIO_PIN4_CONFIG_V 0x3 +#define GPIO_PIN4_CONFIG_S 11 +/* GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN4_INT_TYPE 0x00000007 +#define GPIO_PIN4_INT_TYPE_M ((GPIO_PIN4_INT_TYPE_V)<<(GPIO_PIN4_INT_TYPE_S)) +#define GPIO_PIN4_INT_TYPE_V 0x7 +#define GPIO_PIN4_INT_TYPE_S 7 +/* GPIO_PIN4_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN4_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC1_BYPASS_M ((GPIO_PIN4_SYNC1_BYPASS_V)<<(GPIO_PIN4_SYNC1_BYPASS_S)) +#define GPIO_PIN4_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC1_BYPASS_S 3 +/* GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN4_PAD_DRIVER_V 0x1 +#define GPIO_PIN4_PAD_DRIVER_S 2 +/* GPIO_PIN4_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN4_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN4_SYNC2_BYPASS_M ((GPIO_PIN4_SYNC2_BYPASS_V)<<(GPIO_PIN4_SYNC2_BYPASS_S)) +#define GPIO_PIN4_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN4_SYNC2_BYPASS_S 0 + +#define GPIO_PIN5_REG (DR_REG_GPIO_BASE + 0x88) +/* GPIO_PIN5_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN5_INT_ENA 0x0000001F +#define GPIO_PIN5_INT_ENA_M ((GPIO_PIN5_INT_ENA_V)<<(GPIO_PIN5_INT_ENA_S)) +#define GPIO_PIN5_INT_ENA_V 0x1F +#define GPIO_PIN5_INT_ENA_S 13 +/* GPIO_PIN5_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN5_CONFIG 0x00000003 +#define GPIO_PIN5_CONFIG_M ((GPIO_PIN5_CONFIG_V)<<(GPIO_PIN5_CONFIG_S)) +#define GPIO_PIN5_CONFIG_V 0x3 +#define GPIO_PIN5_CONFIG_S 11 +/* GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN5_INT_TYPE 0x00000007 +#define GPIO_PIN5_INT_TYPE_M ((GPIO_PIN5_INT_TYPE_V)<<(GPIO_PIN5_INT_TYPE_S)) +#define GPIO_PIN5_INT_TYPE_V 0x7 +#define GPIO_PIN5_INT_TYPE_S 7 +/* GPIO_PIN5_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN5_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC1_BYPASS_M ((GPIO_PIN5_SYNC1_BYPASS_V)<<(GPIO_PIN5_SYNC1_BYPASS_S)) +#define GPIO_PIN5_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC1_BYPASS_S 3 +/* GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN5_PAD_DRIVER_V 0x1 +#define GPIO_PIN5_PAD_DRIVER_S 2 +/* GPIO_PIN5_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN5_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN5_SYNC2_BYPASS_M ((GPIO_PIN5_SYNC2_BYPASS_V)<<(GPIO_PIN5_SYNC2_BYPASS_S)) +#define GPIO_PIN5_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN5_SYNC2_BYPASS_S 0 + +#define GPIO_PIN6_REG (DR_REG_GPIO_BASE + 0x8C) +/* GPIO_PIN6_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN6_INT_ENA 0x0000001F +#define GPIO_PIN6_INT_ENA_M ((GPIO_PIN6_INT_ENA_V)<<(GPIO_PIN6_INT_ENA_S)) +#define GPIO_PIN6_INT_ENA_V 0x1F +#define GPIO_PIN6_INT_ENA_S 13 +/* GPIO_PIN6_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN6_CONFIG 0x00000003 +#define GPIO_PIN6_CONFIG_M ((GPIO_PIN6_CONFIG_V)<<(GPIO_PIN6_CONFIG_S)) +#define GPIO_PIN6_CONFIG_V 0x3 +#define GPIO_PIN6_CONFIG_S 11 +/* GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN6_INT_TYPE 0x00000007 +#define GPIO_PIN6_INT_TYPE_M ((GPIO_PIN6_INT_TYPE_V)<<(GPIO_PIN6_INT_TYPE_S)) +#define GPIO_PIN6_INT_TYPE_V 0x7 +#define GPIO_PIN6_INT_TYPE_S 7 +/* GPIO_PIN6_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN6_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC1_BYPASS_M ((GPIO_PIN6_SYNC1_BYPASS_V)<<(GPIO_PIN6_SYNC1_BYPASS_S)) +#define GPIO_PIN6_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC1_BYPASS_S 3 +/* GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN6_PAD_DRIVER_V 0x1 +#define GPIO_PIN6_PAD_DRIVER_S 2 +/* GPIO_PIN6_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN6_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN6_SYNC2_BYPASS_M ((GPIO_PIN6_SYNC2_BYPASS_V)<<(GPIO_PIN6_SYNC2_BYPASS_S)) +#define GPIO_PIN6_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN6_SYNC2_BYPASS_S 0 + +#define GPIO_PIN7_REG (DR_REG_GPIO_BASE + 0x90) +/* GPIO_PIN7_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN7_INT_ENA 0x0000001F +#define GPIO_PIN7_INT_ENA_M ((GPIO_PIN7_INT_ENA_V)<<(GPIO_PIN7_INT_ENA_S)) +#define GPIO_PIN7_INT_ENA_V 0x1F +#define GPIO_PIN7_INT_ENA_S 13 +/* GPIO_PIN7_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN7_CONFIG 0x00000003 +#define GPIO_PIN7_CONFIG_M ((GPIO_PIN7_CONFIG_V)<<(GPIO_PIN7_CONFIG_S)) +#define GPIO_PIN7_CONFIG_V 0x3 +#define GPIO_PIN7_CONFIG_S 11 +/* GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN7_INT_TYPE 0x00000007 +#define GPIO_PIN7_INT_TYPE_M ((GPIO_PIN7_INT_TYPE_V)<<(GPIO_PIN7_INT_TYPE_S)) +#define GPIO_PIN7_INT_TYPE_V 0x7 +#define GPIO_PIN7_INT_TYPE_S 7 +/* GPIO_PIN7_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN7_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC1_BYPASS_M ((GPIO_PIN7_SYNC1_BYPASS_V)<<(GPIO_PIN7_SYNC1_BYPASS_S)) +#define GPIO_PIN7_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC1_BYPASS_S 3 +/* GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN7_PAD_DRIVER_V 0x1 +#define GPIO_PIN7_PAD_DRIVER_S 2 +/* GPIO_PIN7_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN7_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN7_SYNC2_BYPASS_M ((GPIO_PIN7_SYNC2_BYPASS_V)<<(GPIO_PIN7_SYNC2_BYPASS_S)) +#define GPIO_PIN7_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN7_SYNC2_BYPASS_S 0 + +#define GPIO_PIN8_REG (DR_REG_GPIO_BASE + 0x94) +/* GPIO_PIN8_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN8_INT_ENA 0x0000001F +#define GPIO_PIN8_INT_ENA_M ((GPIO_PIN8_INT_ENA_V)<<(GPIO_PIN8_INT_ENA_S)) +#define GPIO_PIN8_INT_ENA_V 0x1F +#define GPIO_PIN8_INT_ENA_S 13 +/* GPIO_PIN8_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN8_CONFIG 0x00000003 +#define GPIO_PIN8_CONFIG_M ((GPIO_PIN8_CONFIG_V)<<(GPIO_PIN8_CONFIG_S)) +#define GPIO_PIN8_CONFIG_V 0x3 +#define GPIO_PIN8_CONFIG_S 11 +/* GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN8_INT_TYPE 0x00000007 +#define GPIO_PIN8_INT_TYPE_M ((GPIO_PIN8_INT_TYPE_V)<<(GPIO_PIN8_INT_TYPE_S)) +#define GPIO_PIN8_INT_TYPE_V 0x7 +#define GPIO_PIN8_INT_TYPE_S 7 +/* GPIO_PIN8_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN8_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC1_BYPASS_M ((GPIO_PIN8_SYNC1_BYPASS_V)<<(GPIO_PIN8_SYNC1_BYPASS_S)) +#define GPIO_PIN8_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC1_BYPASS_S 3 +/* GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN8_PAD_DRIVER_V 0x1 +#define GPIO_PIN8_PAD_DRIVER_S 2 +/* GPIO_PIN8_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN8_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN8_SYNC2_BYPASS_M ((GPIO_PIN8_SYNC2_BYPASS_V)<<(GPIO_PIN8_SYNC2_BYPASS_S)) +#define GPIO_PIN8_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN8_SYNC2_BYPASS_S 0 + +#define GPIO_PIN9_REG (DR_REG_GPIO_BASE + 0x98) +/* GPIO_PIN9_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN9_INT_ENA 0x0000001F +#define GPIO_PIN9_INT_ENA_M ((GPIO_PIN9_INT_ENA_V)<<(GPIO_PIN9_INT_ENA_S)) +#define GPIO_PIN9_INT_ENA_V 0x1F +#define GPIO_PIN9_INT_ENA_S 13 +/* GPIO_PIN9_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN9_CONFIG 0x00000003 +#define GPIO_PIN9_CONFIG_M ((GPIO_PIN9_CONFIG_V)<<(GPIO_PIN9_CONFIG_S)) +#define GPIO_PIN9_CONFIG_V 0x3 +#define GPIO_PIN9_CONFIG_S 11 +/* GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN9_INT_TYPE 0x00000007 +#define GPIO_PIN9_INT_TYPE_M ((GPIO_PIN9_INT_TYPE_V)<<(GPIO_PIN9_INT_TYPE_S)) +#define GPIO_PIN9_INT_TYPE_V 0x7 +#define GPIO_PIN9_INT_TYPE_S 7 +/* GPIO_PIN9_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN9_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC1_BYPASS_M ((GPIO_PIN9_SYNC1_BYPASS_V)<<(GPIO_PIN9_SYNC1_BYPASS_S)) +#define GPIO_PIN9_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC1_BYPASS_S 3 +/* GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN9_PAD_DRIVER_V 0x1 +#define GPIO_PIN9_PAD_DRIVER_S 2 +/* GPIO_PIN9_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN9_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN9_SYNC2_BYPASS_M ((GPIO_PIN9_SYNC2_BYPASS_V)<<(GPIO_PIN9_SYNC2_BYPASS_S)) +#define GPIO_PIN9_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN9_SYNC2_BYPASS_S 0 + +#define GPIO_PIN10_REG (DR_REG_GPIO_BASE + 0x9C) +/* GPIO_PIN10_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN10_INT_ENA 0x0000001F +#define GPIO_PIN10_INT_ENA_M ((GPIO_PIN10_INT_ENA_V)<<(GPIO_PIN10_INT_ENA_S)) +#define GPIO_PIN10_INT_ENA_V 0x1F +#define GPIO_PIN10_INT_ENA_S 13 +/* GPIO_PIN10_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN10_CONFIG 0x00000003 +#define GPIO_PIN10_CONFIG_M ((GPIO_PIN10_CONFIG_V)<<(GPIO_PIN10_CONFIG_S)) +#define GPIO_PIN10_CONFIG_V 0x3 +#define GPIO_PIN10_CONFIG_S 11 +/* GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN10_INT_TYPE 0x00000007 +#define GPIO_PIN10_INT_TYPE_M ((GPIO_PIN10_INT_TYPE_V)<<(GPIO_PIN10_INT_TYPE_S)) +#define GPIO_PIN10_INT_TYPE_V 0x7 +#define GPIO_PIN10_INT_TYPE_S 7 +/* GPIO_PIN10_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN10_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC1_BYPASS_M ((GPIO_PIN10_SYNC1_BYPASS_V)<<(GPIO_PIN10_SYNC1_BYPASS_S)) +#define GPIO_PIN10_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC1_BYPASS_S 3 +/* GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN10_PAD_DRIVER_V 0x1 +#define GPIO_PIN10_PAD_DRIVER_S 2 +/* GPIO_PIN10_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN10_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN10_SYNC2_BYPASS_M ((GPIO_PIN10_SYNC2_BYPASS_V)<<(GPIO_PIN10_SYNC2_BYPASS_S)) +#define GPIO_PIN10_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN10_SYNC2_BYPASS_S 0 + +#define GPIO_PIN11_REG (DR_REG_GPIO_BASE + 0xA0) +/* GPIO_PIN11_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN11_INT_ENA 0x0000001F +#define GPIO_PIN11_INT_ENA_M ((GPIO_PIN11_INT_ENA_V)<<(GPIO_PIN11_INT_ENA_S)) +#define GPIO_PIN11_INT_ENA_V 0x1F +#define GPIO_PIN11_INT_ENA_S 13 +/* GPIO_PIN11_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN11_CONFIG 0x00000003 +#define GPIO_PIN11_CONFIG_M ((GPIO_PIN11_CONFIG_V)<<(GPIO_PIN11_CONFIG_S)) +#define GPIO_PIN11_CONFIG_V 0x3 +#define GPIO_PIN11_CONFIG_S 11 +/* GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN11_INT_TYPE 0x00000007 +#define GPIO_PIN11_INT_TYPE_M ((GPIO_PIN11_INT_TYPE_V)<<(GPIO_PIN11_INT_TYPE_S)) +#define GPIO_PIN11_INT_TYPE_V 0x7 +#define GPIO_PIN11_INT_TYPE_S 7 +/* GPIO_PIN11_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN11_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC1_BYPASS_M ((GPIO_PIN11_SYNC1_BYPASS_V)<<(GPIO_PIN11_SYNC1_BYPASS_S)) +#define GPIO_PIN11_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC1_BYPASS_S 3 +/* GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN11_PAD_DRIVER_V 0x1 +#define GPIO_PIN11_PAD_DRIVER_S 2 +/* GPIO_PIN11_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN11_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN11_SYNC2_BYPASS_M ((GPIO_PIN11_SYNC2_BYPASS_V)<<(GPIO_PIN11_SYNC2_BYPASS_S)) +#define GPIO_PIN11_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN11_SYNC2_BYPASS_S 0 + +#define GPIO_PIN12_REG (DR_REG_GPIO_BASE + 0xA4) +/* GPIO_PIN12_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN12_INT_ENA 0x0000001F +#define GPIO_PIN12_INT_ENA_M ((GPIO_PIN12_INT_ENA_V)<<(GPIO_PIN12_INT_ENA_S)) +#define GPIO_PIN12_INT_ENA_V 0x1F +#define GPIO_PIN12_INT_ENA_S 13 +/* GPIO_PIN12_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN12_CONFIG 0x00000003 +#define GPIO_PIN12_CONFIG_M ((GPIO_PIN12_CONFIG_V)<<(GPIO_PIN12_CONFIG_S)) +#define GPIO_PIN12_CONFIG_V 0x3 +#define GPIO_PIN12_CONFIG_S 11 +/* GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN12_INT_TYPE 0x00000007 +#define GPIO_PIN12_INT_TYPE_M ((GPIO_PIN12_INT_TYPE_V)<<(GPIO_PIN12_INT_TYPE_S)) +#define GPIO_PIN12_INT_TYPE_V 0x7 +#define GPIO_PIN12_INT_TYPE_S 7 +/* GPIO_PIN12_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN12_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC1_BYPASS_M ((GPIO_PIN12_SYNC1_BYPASS_V)<<(GPIO_PIN12_SYNC1_BYPASS_S)) +#define GPIO_PIN12_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC1_BYPASS_S 3 +/* GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN12_PAD_DRIVER_V 0x1 +#define GPIO_PIN12_PAD_DRIVER_S 2 +/* GPIO_PIN12_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN12_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN12_SYNC2_BYPASS_M ((GPIO_PIN12_SYNC2_BYPASS_V)<<(GPIO_PIN12_SYNC2_BYPASS_S)) +#define GPIO_PIN12_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN12_SYNC2_BYPASS_S 0 + +#define GPIO_PIN13_REG (DR_REG_GPIO_BASE + 0xA8) +/* GPIO_PIN13_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN13_INT_ENA 0x0000001F +#define GPIO_PIN13_INT_ENA_M ((GPIO_PIN13_INT_ENA_V)<<(GPIO_PIN13_INT_ENA_S)) +#define GPIO_PIN13_INT_ENA_V 0x1F +#define GPIO_PIN13_INT_ENA_S 13 +/* GPIO_PIN13_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN13_CONFIG 0x00000003 +#define GPIO_PIN13_CONFIG_M ((GPIO_PIN13_CONFIG_V)<<(GPIO_PIN13_CONFIG_S)) +#define GPIO_PIN13_CONFIG_V 0x3 +#define GPIO_PIN13_CONFIG_S 11 +/* GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN13_INT_TYPE 0x00000007 +#define GPIO_PIN13_INT_TYPE_M ((GPIO_PIN13_INT_TYPE_V)<<(GPIO_PIN13_INT_TYPE_S)) +#define GPIO_PIN13_INT_TYPE_V 0x7 +#define GPIO_PIN13_INT_TYPE_S 7 +/* GPIO_PIN13_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN13_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC1_BYPASS_M ((GPIO_PIN13_SYNC1_BYPASS_V)<<(GPIO_PIN13_SYNC1_BYPASS_S)) +#define GPIO_PIN13_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC1_BYPASS_S 3 +/* GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN13_PAD_DRIVER_V 0x1 +#define GPIO_PIN13_PAD_DRIVER_S 2 +/* GPIO_PIN13_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN13_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN13_SYNC2_BYPASS_M ((GPIO_PIN13_SYNC2_BYPASS_V)<<(GPIO_PIN13_SYNC2_BYPASS_S)) +#define GPIO_PIN13_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN13_SYNC2_BYPASS_S 0 + +#define GPIO_PIN14_REG (DR_REG_GPIO_BASE + 0xAC) +/* GPIO_PIN14_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN14_INT_ENA 0x0000001F +#define GPIO_PIN14_INT_ENA_M ((GPIO_PIN14_INT_ENA_V)<<(GPIO_PIN14_INT_ENA_S)) +#define GPIO_PIN14_INT_ENA_V 0x1F +#define GPIO_PIN14_INT_ENA_S 13 +/* GPIO_PIN14_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN14_CONFIG 0x00000003 +#define GPIO_PIN14_CONFIG_M ((GPIO_PIN14_CONFIG_V)<<(GPIO_PIN14_CONFIG_S)) +#define GPIO_PIN14_CONFIG_V 0x3 +#define GPIO_PIN14_CONFIG_S 11 +/* GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN14_INT_TYPE 0x00000007 +#define GPIO_PIN14_INT_TYPE_M ((GPIO_PIN14_INT_TYPE_V)<<(GPIO_PIN14_INT_TYPE_S)) +#define GPIO_PIN14_INT_TYPE_V 0x7 +#define GPIO_PIN14_INT_TYPE_S 7 +/* GPIO_PIN14_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN14_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC1_BYPASS_M ((GPIO_PIN14_SYNC1_BYPASS_V)<<(GPIO_PIN14_SYNC1_BYPASS_S)) +#define GPIO_PIN14_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC1_BYPASS_S 3 +/* GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN14_PAD_DRIVER_V 0x1 +#define GPIO_PIN14_PAD_DRIVER_S 2 +/* GPIO_PIN14_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN14_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN14_SYNC2_BYPASS_M ((GPIO_PIN14_SYNC2_BYPASS_V)<<(GPIO_PIN14_SYNC2_BYPASS_S)) +#define GPIO_PIN14_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN14_SYNC2_BYPASS_S 0 + +#define GPIO_PIN15_REG (DR_REG_GPIO_BASE + 0xB0) +/* GPIO_PIN15_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN15_INT_ENA 0x0000001F +#define GPIO_PIN15_INT_ENA_M ((GPIO_PIN15_INT_ENA_V)<<(GPIO_PIN15_INT_ENA_S)) +#define GPIO_PIN15_INT_ENA_V 0x1F +#define GPIO_PIN15_INT_ENA_S 13 +/* GPIO_PIN15_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN15_CONFIG 0x00000003 +#define GPIO_PIN15_CONFIG_M ((GPIO_PIN15_CONFIG_V)<<(GPIO_PIN15_CONFIG_S)) +#define GPIO_PIN15_CONFIG_V 0x3 +#define GPIO_PIN15_CONFIG_S 11 +/* GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN15_INT_TYPE 0x00000007 +#define GPIO_PIN15_INT_TYPE_M ((GPIO_PIN15_INT_TYPE_V)<<(GPIO_PIN15_INT_TYPE_S)) +#define GPIO_PIN15_INT_TYPE_V 0x7 +#define GPIO_PIN15_INT_TYPE_S 7 +/* GPIO_PIN15_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN15_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC1_BYPASS_M ((GPIO_PIN15_SYNC1_BYPASS_V)<<(GPIO_PIN15_SYNC1_BYPASS_S)) +#define GPIO_PIN15_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC1_BYPASS_S 3 +/* GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN15_PAD_DRIVER_V 0x1 +#define GPIO_PIN15_PAD_DRIVER_S 2 +/* GPIO_PIN15_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN15_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN15_SYNC2_BYPASS_M ((GPIO_PIN15_SYNC2_BYPASS_V)<<(GPIO_PIN15_SYNC2_BYPASS_S)) +#define GPIO_PIN15_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN15_SYNC2_BYPASS_S 0 + +#define GPIO_PIN16_REG (DR_REG_GPIO_BASE + 0xB4) +/* GPIO_PIN16_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN16_INT_ENA 0x0000001F +#define GPIO_PIN16_INT_ENA_M ((GPIO_PIN16_INT_ENA_V)<<(GPIO_PIN16_INT_ENA_S)) +#define GPIO_PIN16_INT_ENA_V 0x1F +#define GPIO_PIN16_INT_ENA_S 13 +/* GPIO_PIN16_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN16_CONFIG 0x00000003 +#define GPIO_PIN16_CONFIG_M ((GPIO_PIN16_CONFIG_V)<<(GPIO_PIN16_CONFIG_S)) +#define GPIO_PIN16_CONFIG_V 0x3 +#define GPIO_PIN16_CONFIG_S 11 +/* GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN16_INT_TYPE 0x00000007 +#define GPIO_PIN16_INT_TYPE_M ((GPIO_PIN16_INT_TYPE_V)<<(GPIO_PIN16_INT_TYPE_S)) +#define GPIO_PIN16_INT_TYPE_V 0x7 +#define GPIO_PIN16_INT_TYPE_S 7 +/* GPIO_PIN16_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN16_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC1_BYPASS_M ((GPIO_PIN16_SYNC1_BYPASS_V)<<(GPIO_PIN16_SYNC1_BYPASS_S)) +#define GPIO_PIN16_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC1_BYPASS_S 3 +/* GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN16_PAD_DRIVER_V 0x1 +#define GPIO_PIN16_PAD_DRIVER_S 2 +/* GPIO_PIN16_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN16_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN16_SYNC2_BYPASS_M ((GPIO_PIN16_SYNC2_BYPASS_V)<<(GPIO_PIN16_SYNC2_BYPASS_S)) +#define GPIO_PIN16_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN16_SYNC2_BYPASS_S 0 + +#define GPIO_PIN17_REG (DR_REG_GPIO_BASE + 0xB8) +/* GPIO_PIN17_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN17_INT_ENA 0x0000001F +#define GPIO_PIN17_INT_ENA_M ((GPIO_PIN17_INT_ENA_V)<<(GPIO_PIN17_INT_ENA_S)) +#define GPIO_PIN17_INT_ENA_V 0x1F +#define GPIO_PIN17_INT_ENA_S 13 +/* GPIO_PIN17_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN17_CONFIG 0x00000003 +#define GPIO_PIN17_CONFIG_M ((GPIO_PIN17_CONFIG_V)<<(GPIO_PIN17_CONFIG_S)) +#define GPIO_PIN17_CONFIG_V 0x3 +#define GPIO_PIN17_CONFIG_S 11 +/* GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN17_INT_TYPE 0x00000007 +#define GPIO_PIN17_INT_TYPE_M ((GPIO_PIN17_INT_TYPE_V)<<(GPIO_PIN17_INT_TYPE_S)) +#define GPIO_PIN17_INT_TYPE_V 0x7 +#define GPIO_PIN17_INT_TYPE_S 7 +/* GPIO_PIN17_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN17_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC1_BYPASS_M ((GPIO_PIN17_SYNC1_BYPASS_V)<<(GPIO_PIN17_SYNC1_BYPASS_S)) +#define GPIO_PIN17_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC1_BYPASS_S 3 +/* GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN17_PAD_DRIVER_V 0x1 +#define GPIO_PIN17_PAD_DRIVER_S 2 +/* GPIO_PIN17_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN17_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN17_SYNC2_BYPASS_M ((GPIO_PIN17_SYNC2_BYPASS_V)<<(GPIO_PIN17_SYNC2_BYPASS_S)) +#define GPIO_PIN17_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN17_SYNC2_BYPASS_S 0 + +#define GPIO_PIN18_REG (DR_REG_GPIO_BASE + 0xBC) +/* GPIO_PIN18_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN18_INT_ENA 0x0000001F +#define GPIO_PIN18_INT_ENA_M ((GPIO_PIN18_INT_ENA_V)<<(GPIO_PIN18_INT_ENA_S)) +#define GPIO_PIN18_INT_ENA_V 0x1F +#define GPIO_PIN18_INT_ENA_S 13 +/* GPIO_PIN18_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN18_CONFIG 0x00000003 +#define GPIO_PIN18_CONFIG_M ((GPIO_PIN18_CONFIG_V)<<(GPIO_PIN18_CONFIG_S)) +#define GPIO_PIN18_CONFIG_V 0x3 +#define GPIO_PIN18_CONFIG_S 11 +/* GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN18_WAKEUP_ENABLE_S 10 +/* GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN18_INT_TYPE 0x00000007 +#define GPIO_PIN18_INT_TYPE_M ((GPIO_PIN18_INT_TYPE_V)<<(GPIO_PIN18_INT_TYPE_S)) +#define GPIO_PIN18_INT_TYPE_V 0x7 +#define GPIO_PIN18_INT_TYPE_S 7 +/* GPIO_PIN18_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN18_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC1_BYPASS_M ((GPIO_PIN18_SYNC1_BYPASS_V)<<(GPIO_PIN18_SYNC1_BYPASS_S)) +#define GPIO_PIN18_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC1_BYPASS_S 3 +/* GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN18_PAD_DRIVER_V 0x1 +#define GPIO_PIN18_PAD_DRIVER_S 2 +/* GPIO_PIN18_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN18_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN18_SYNC2_BYPASS_M ((GPIO_PIN18_SYNC2_BYPASS_V)<<(GPIO_PIN18_SYNC2_BYPASS_S)) +#define GPIO_PIN18_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN18_SYNC2_BYPASS_S 0 + +#define GPIO_PIN19_REG (DR_REG_GPIO_BASE + 0xC0) +/* GPIO_PIN19_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN19_INT_ENA 0x0000001F +#define GPIO_PIN19_INT_ENA_M ((GPIO_PIN19_INT_ENA_V)<<(GPIO_PIN19_INT_ENA_S)) +#define GPIO_PIN19_INT_ENA_V 0x1F +#define GPIO_PIN19_INT_ENA_S 13 +/* GPIO_PIN19_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN19_CONFIG 0x00000003 +#define GPIO_PIN19_CONFIG_M ((GPIO_PIN19_CONFIG_V)<<(GPIO_PIN19_CONFIG_S)) +#define GPIO_PIN19_CONFIG_V 0x3 +#define GPIO_PIN19_CONFIG_S 11 +/* GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN19_WAKEUP_ENABLE_S 10 +/* GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN19_INT_TYPE 0x00000007 +#define GPIO_PIN19_INT_TYPE_M ((GPIO_PIN19_INT_TYPE_V)<<(GPIO_PIN19_INT_TYPE_S)) +#define GPIO_PIN19_INT_TYPE_V 0x7 +#define GPIO_PIN19_INT_TYPE_S 7 +/* GPIO_PIN19_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN19_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC1_BYPASS_M ((GPIO_PIN19_SYNC1_BYPASS_V)<<(GPIO_PIN19_SYNC1_BYPASS_S)) +#define GPIO_PIN19_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC1_BYPASS_S 3 +/* GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN19_PAD_DRIVER_V 0x1 +#define GPIO_PIN19_PAD_DRIVER_S 2 +/* GPIO_PIN19_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN19_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN19_SYNC2_BYPASS_M ((GPIO_PIN19_SYNC2_BYPASS_V)<<(GPIO_PIN19_SYNC2_BYPASS_S)) +#define GPIO_PIN19_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN19_SYNC2_BYPASS_S 0 + +#define GPIO_PIN20_REG (DR_REG_GPIO_BASE + 0xC4) +/* GPIO_PIN20_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN20_INT_ENA 0x0000001F +#define GPIO_PIN20_INT_ENA_M ((GPIO_PIN20_INT_ENA_V)<<(GPIO_PIN20_INT_ENA_S)) +#define GPIO_PIN20_INT_ENA_V 0x1F +#define GPIO_PIN20_INT_ENA_S 13 +/* GPIO_PIN20_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN20_CONFIG 0x00000003 +#define GPIO_PIN20_CONFIG_M ((GPIO_PIN20_CONFIG_V)<<(GPIO_PIN20_CONFIG_S)) +#define GPIO_PIN20_CONFIG_V 0x3 +#define GPIO_PIN20_CONFIG_S 11 +/* GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN20_WAKEUP_ENABLE_S 10 +/* GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN20_INT_TYPE 0x00000007 +#define GPIO_PIN20_INT_TYPE_M ((GPIO_PIN20_INT_TYPE_V)<<(GPIO_PIN20_INT_TYPE_S)) +#define GPIO_PIN20_INT_TYPE_V 0x7 +#define GPIO_PIN20_INT_TYPE_S 7 +/* GPIO_PIN20_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN20_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC1_BYPASS_M ((GPIO_PIN20_SYNC1_BYPASS_V)<<(GPIO_PIN20_SYNC1_BYPASS_S)) +#define GPIO_PIN20_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC1_BYPASS_S 3 +/* GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN20_PAD_DRIVER_V 0x1 +#define GPIO_PIN20_PAD_DRIVER_S 2 +/* GPIO_PIN20_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN20_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN20_SYNC2_BYPASS_M ((GPIO_PIN20_SYNC2_BYPASS_V)<<(GPIO_PIN20_SYNC2_BYPASS_S)) +#define GPIO_PIN20_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN20_SYNC2_BYPASS_S 0 + +#define GPIO_PIN21_REG (DR_REG_GPIO_BASE + 0xC8) +/* GPIO_PIN21_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN21_INT_ENA 0x0000001F +#define GPIO_PIN21_INT_ENA_M ((GPIO_PIN21_INT_ENA_V)<<(GPIO_PIN21_INT_ENA_S)) +#define GPIO_PIN21_INT_ENA_V 0x1F +#define GPIO_PIN21_INT_ENA_S 13 +/* GPIO_PIN21_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN21_CONFIG 0x00000003 +#define GPIO_PIN21_CONFIG_M ((GPIO_PIN21_CONFIG_V)<<(GPIO_PIN21_CONFIG_S)) +#define GPIO_PIN21_CONFIG_V 0x3 +#define GPIO_PIN21_CONFIG_S 11 +/* GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN21_WAKEUP_ENABLE_S 10 +/* GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN21_INT_TYPE 0x00000007 +#define GPIO_PIN21_INT_TYPE_M ((GPIO_PIN21_INT_TYPE_V)<<(GPIO_PIN21_INT_TYPE_S)) +#define GPIO_PIN21_INT_TYPE_V 0x7 +#define GPIO_PIN21_INT_TYPE_S 7 +/* GPIO_PIN21_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN21_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC1_BYPASS_M ((GPIO_PIN21_SYNC1_BYPASS_V)<<(GPIO_PIN21_SYNC1_BYPASS_S)) +#define GPIO_PIN21_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC1_BYPASS_S 3 +/* GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN21_PAD_DRIVER_V 0x1 +#define GPIO_PIN21_PAD_DRIVER_S 2 +/* GPIO_PIN21_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN21_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN21_SYNC2_BYPASS_M ((GPIO_PIN21_SYNC2_BYPASS_V)<<(GPIO_PIN21_SYNC2_BYPASS_S)) +#define GPIO_PIN21_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN21_SYNC2_BYPASS_S 0 + +#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0xCC) +/* GPIO_PIN22_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN22_INT_ENA 0x0000001F +#define GPIO_PIN22_INT_ENA_M ((GPIO_PIN22_INT_ENA_V)<<(GPIO_PIN22_INT_ENA_S)) +#define GPIO_PIN22_INT_ENA_V 0x1F +#define GPIO_PIN22_INT_ENA_S 13 +/* GPIO_PIN22_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN22_CONFIG 0x00000003 +#define GPIO_PIN22_CONFIG_M ((GPIO_PIN22_CONFIG_V)<<(GPIO_PIN22_CONFIG_S)) +#define GPIO_PIN22_CONFIG_V 0x3 +#define GPIO_PIN22_CONFIG_S 11 +/* GPIO_PIN22_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN22_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN22_WAKEUP_ENABLE_S 10 +/* GPIO_PIN22_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN22_INT_TYPE 0x00000007 +#define GPIO_PIN22_INT_TYPE_M ((GPIO_PIN22_INT_TYPE_V)<<(GPIO_PIN22_INT_TYPE_S)) +#define GPIO_PIN22_INT_TYPE_V 0x7 +#define GPIO_PIN22_INT_TYPE_S 7 +/* GPIO_PIN22_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN22_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC1_BYPASS_M ((GPIO_PIN22_SYNC1_BYPASS_V)<<(GPIO_PIN22_SYNC1_BYPASS_S)) +#define GPIO_PIN22_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC1_BYPASS_S 3 +/* GPIO_PIN22_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN22_PAD_DRIVER (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN22_PAD_DRIVER_V 0x1 +#define GPIO_PIN22_PAD_DRIVER_S 2 +/* GPIO_PIN22_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN22_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN22_SYNC2_BYPASS_M ((GPIO_PIN22_SYNC2_BYPASS_V)<<(GPIO_PIN22_SYNC2_BYPASS_S)) +#define GPIO_PIN22_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN22_SYNC2_BYPASS_S 0 + +#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0xD0) +/* GPIO_PIN23_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN23_INT_ENA 0x0000001F +#define GPIO_PIN23_INT_ENA_M ((GPIO_PIN23_INT_ENA_V)<<(GPIO_PIN23_INT_ENA_S)) +#define GPIO_PIN23_INT_ENA_V 0x1F +#define GPIO_PIN23_INT_ENA_S 13 +/* GPIO_PIN23_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN23_CONFIG 0x00000003 +#define GPIO_PIN23_CONFIG_M ((GPIO_PIN23_CONFIG_V)<<(GPIO_PIN23_CONFIG_S)) +#define GPIO_PIN23_CONFIG_V 0x3 +#define GPIO_PIN23_CONFIG_S 11 +/* GPIO_PIN23_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN23_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN23_WAKEUP_ENABLE_S 10 +/* GPIO_PIN23_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN23_INT_TYPE 0x00000007 +#define GPIO_PIN23_INT_TYPE_M ((GPIO_PIN23_INT_TYPE_V)<<(GPIO_PIN23_INT_TYPE_S)) +#define GPIO_PIN23_INT_TYPE_V 0x7 +#define GPIO_PIN23_INT_TYPE_S 7 +/* GPIO_PIN23_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN23_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC1_BYPASS_M ((GPIO_PIN23_SYNC1_BYPASS_V)<<(GPIO_PIN23_SYNC1_BYPASS_S)) +#define GPIO_PIN23_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC1_BYPASS_S 3 +/* GPIO_PIN23_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN23_PAD_DRIVER (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN23_PAD_DRIVER_V 0x1 +#define GPIO_PIN23_PAD_DRIVER_S 2 +/* GPIO_PIN23_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN23_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN23_SYNC2_BYPASS_M ((GPIO_PIN23_SYNC2_BYPASS_V)<<(GPIO_PIN23_SYNC2_BYPASS_S)) +#define GPIO_PIN23_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN23_SYNC2_BYPASS_S 0 + +#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0xD4) +/* GPIO_PIN24_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN24_INT_ENA 0x0000001F +#define GPIO_PIN24_INT_ENA_M ((GPIO_PIN24_INT_ENA_V)<<(GPIO_PIN24_INT_ENA_S)) +#define GPIO_PIN24_INT_ENA_V 0x1F +#define GPIO_PIN24_INT_ENA_S 13 +/* GPIO_PIN24_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN24_CONFIG 0x00000003 +#define GPIO_PIN24_CONFIG_M ((GPIO_PIN24_CONFIG_V)<<(GPIO_PIN24_CONFIG_S)) +#define GPIO_PIN24_CONFIG_V 0x3 +#define GPIO_PIN24_CONFIG_S 11 +/* GPIO_PIN24_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN24_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN24_WAKEUP_ENABLE_S 10 +/* GPIO_PIN24_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN24_INT_TYPE 0x00000007 +#define GPIO_PIN24_INT_TYPE_M ((GPIO_PIN24_INT_TYPE_V)<<(GPIO_PIN24_INT_TYPE_S)) +#define GPIO_PIN24_INT_TYPE_V 0x7 +#define GPIO_PIN24_INT_TYPE_S 7 +/* GPIO_PIN24_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN24_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC1_BYPASS_M ((GPIO_PIN24_SYNC1_BYPASS_V)<<(GPIO_PIN24_SYNC1_BYPASS_S)) +#define GPIO_PIN24_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC1_BYPASS_S 3 +/* GPIO_PIN24_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN24_PAD_DRIVER (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN24_PAD_DRIVER_V 0x1 +#define GPIO_PIN24_PAD_DRIVER_S 2 +/* GPIO_PIN24_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN24_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN24_SYNC2_BYPASS_M ((GPIO_PIN24_SYNC2_BYPASS_V)<<(GPIO_PIN24_SYNC2_BYPASS_S)) +#define GPIO_PIN24_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN24_SYNC2_BYPASS_S 0 + +#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0xD8) +/* GPIO_PIN25_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN25_INT_ENA 0x0000001F +#define GPIO_PIN25_INT_ENA_M ((GPIO_PIN25_INT_ENA_V)<<(GPIO_PIN25_INT_ENA_S)) +#define GPIO_PIN25_INT_ENA_V 0x1F +#define GPIO_PIN25_INT_ENA_S 13 +/* GPIO_PIN25_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN25_CONFIG 0x00000003 +#define GPIO_PIN25_CONFIG_M ((GPIO_PIN25_CONFIG_V)<<(GPIO_PIN25_CONFIG_S)) +#define GPIO_PIN25_CONFIG_V 0x3 +#define GPIO_PIN25_CONFIG_S 11 +/* GPIO_PIN25_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN25_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN25_WAKEUP_ENABLE_S 10 +/* GPIO_PIN25_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN25_INT_TYPE 0x00000007 +#define GPIO_PIN25_INT_TYPE_M ((GPIO_PIN25_INT_TYPE_V)<<(GPIO_PIN25_INT_TYPE_S)) +#define GPIO_PIN25_INT_TYPE_V 0x7 +#define GPIO_PIN25_INT_TYPE_S 7 +/* GPIO_PIN25_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN25_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC1_BYPASS_M ((GPIO_PIN25_SYNC1_BYPASS_V)<<(GPIO_PIN25_SYNC1_BYPASS_S)) +#define GPIO_PIN25_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC1_BYPASS_S 3 +/* GPIO_PIN25_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN25_PAD_DRIVER (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN25_PAD_DRIVER_V 0x1 +#define GPIO_PIN25_PAD_DRIVER_S 2 +/* GPIO_PIN25_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN25_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN25_SYNC2_BYPASS_M ((GPIO_PIN25_SYNC2_BYPASS_V)<<(GPIO_PIN25_SYNC2_BYPASS_S)) +#define GPIO_PIN25_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN25_SYNC2_BYPASS_S 0 + +#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0xDC) +/* GPIO_PIN26_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN26_INT_ENA 0x0000001F +#define GPIO_PIN26_INT_ENA_M ((GPIO_PIN26_INT_ENA_V)<<(GPIO_PIN26_INT_ENA_S)) +#define GPIO_PIN26_INT_ENA_V 0x1F +#define GPIO_PIN26_INT_ENA_S 13 +/* GPIO_PIN26_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN26_CONFIG 0x00000003 +#define GPIO_PIN26_CONFIG_M ((GPIO_PIN26_CONFIG_V)<<(GPIO_PIN26_CONFIG_S)) +#define GPIO_PIN26_CONFIG_V 0x3 +#define GPIO_PIN26_CONFIG_S 11 +/* GPIO_PIN26_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN26_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN26_WAKEUP_ENABLE_S 10 +/* GPIO_PIN26_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN26_INT_TYPE 0x00000007 +#define GPIO_PIN26_INT_TYPE_M ((GPIO_PIN26_INT_TYPE_V)<<(GPIO_PIN26_INT_TYPE_S)) +#define GPIO_PIN26_INT_TYPE_V 0x7 +#define GPIO_PIN26_INT_TYPE_S 7 +/* GPIO_PIN26_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN26_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC1_BYPASS_M ((GPIO_PIN26_SYNC1_BYPASS_V)<<(GPIO_PIN26_SYNC1_BYPASS_S)) +#define GPIO_PIN26_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN26_SYNC1_BYPASS_S 3 +/* GPIO_PIN26_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN26_PAD_DRIVER (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN26_PAD_DRIVER_V 0x1 +#define GPIO_PIN26_PAD_DRIVER_S 2 +/* GPIO_PIN26_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN26_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN26_SYNC2_BYPASS_M ((GPIO_PIN26_SYNC2_BYPASS_V)<<(GPIO_PIN26_SYNC2_BYPASS_S)) +#define GPIO_PIN26_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN26_SYNC2_BYPASS_S 0 + +#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0xE0) +/* GPIO_PIN27_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN27_INT_ENA 0x0000001F +#define GPIO_PIN27_INT_ENA_M ((GPIO_PIN27_INT_ENA_V)<<(GPIO_PIN27_INT_ENA_S)) +#define GPIO_PIN27_INT_ENA_V 0x1F +#define GPIO_PIN27_INT_ENA_S 13 +/* GPIO_PIN27_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN27_CONFIG 0x00000003 +#define GPIO_PIN27_CONFIG_M ((GPIO_PIN27_CONFIG_V)<<(GPIO_PIN27_CONFIG_S)) +#define GPIO_PIN27_CONFIG_V 0x3 +#define GPIO_PIN27_CONFIG_S 11 +/* GPIO_PIN27_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN27_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN27_WAKEUP_ENABLE_S 10 +/* GPIO_PIN27_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN27_INT_TYPE 0x00000007 +#define GPIO_PIN27_INT_TYPE_M ((GPIO_PIN27_INT_TYPE_V)<<(GPIO_PIN27_INT_TYPE_S)) +#define GPIO_PIN27_INT_TYPE_V 0x7 +#define GPIO_PIN27_INT_TYPE_S 7 +/* GPIO_PIN27_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN27_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC1_BYPASS_M ((GPIO_PIN27_SYNC1_BYPASS_V)<<(GPIO_PIN27_SYNC1_BYPASS_S)) +#define GPIO_PIN27_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN27_SYNC1_BYPASS_S 3 +/* GPIO_PIN27_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN27_PAD_DRIVER (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN27_PAD_DRIVER_V 0x1 +#define GPIO_PIN27_PAD_DRIVER_S 2 +/* GPIO_PIN27_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN27_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN27_SYNC2_BYPASS_M ((GPIO_PIN27_SYNC2_BYPASS_V)<<(GPIO_PIN27_SYNC2_BYPASS_S)) +#define GPIO_PIN27_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN27_SYNC2_BYPASS_S 0 + +#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0xE4) +/* GPIO_PIN28_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN28_INT_ENA 0x0000001F +#define GPIO_PIN28_INT_ENA_M ((GPIO_PIN28_INT_ENA_V)<<(GPIO_PIN28_INT_ENA_S)) +#define GPIO_PIN28_INT_ENA_V 0x1F +#define GPIO_PIN28_INT_ENA_S 13 +/* GPIO_PIN28_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN28_CONFIG 0x00000003 +#define GPIO_PIN28_CONFIG_M ((GPIO_PIN28_CONFIG_V)<<(GPIO_PIN28_CONFIG_S)) +#define GPIO_PIN28_CONFIG_V 0x3 +#define GPIO_PIN28_CONFIG_S 11 +/* GPIO_PIN28_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN28_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN28_WAKEUP_ENABLE_S 10 +/* GPIO_PIN28_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN28_INT_TYPE 0x00000007 +#define GPIO_PIN28_INT_TYPE_M ((GPIO_PIN28_INT_TYPE_V)<<(GPIO_PIN28_INT_TYPE_S)) +#define GPIO_PIN28_INT_TYPE_V 0x7 +#define GPIO_PIN28_INT_TYPE_S 7 +/* GPIO_PIN28_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN28_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC1_BYPASS_M ((GPIO_PIN28_SYNC1_BYPASS_V)<<(GPIO_PIN28_SYNC1_BYPASS_S)) +#define GPIO_PIN28_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN28_SYNC1_BYPASS_S 3 +/* GPIO_PIN28_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN28_PAD_DRIVER (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN28_PAD_DRIVER_V 0x1 +#define GPIO_PIN28_PAD_DRIVER_S 2 +/* GPIO_PIN28_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN28_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN28_SYNC2_BYPASS_M ((GPIO_PIN28_SYNC2_BYPASS_V)<<(GPIO_PIN28_SYNC2_BYPASS_S)) +#define GPIO_PIN28_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN28_SYNC2_BYPASS_S 0 + +#define GPIO_PIN29_REG (DR_REG_GPIO_BASE + 0xE8) +/* GPIO_PIN29_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN29_INT_ENA 0x0000001F +#define GPIO_PIN29_INT_ENA_M ((GPIO_PIN29_INT_ENA_V)<<(GPIO_PIN29_INT_ENA_S)) +#define GPIO_PIN29_INT_ENA_V 0x1F +#define GPIO_PIN29_INT_ENA_S 13 +/* GPIO_PIN29_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN29_CONFIG 0x00000003 +#define GPIO_PIN29_CONFIG_M ((GPIO_PIN29_CONFIG_V)<<(GPIO_PIN29_CONFIG_S)) +#define GPIO_PIN29_CONFIG_V 0x3 +#define GPIO_PIN29_CONFIG_S 11 +/* GPIO_PIN29_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN29_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN29_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN29_WAKEUP_ENABLE_S 10 +/* GPIO_PIN29_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN29_INT_TYPE 0x00000007 +#define GPIO_PIN29_INT_TYPE_M ((GPIO_PIN29_INT_TYPE_V)<<(GPIO_PIN29_INT_TYPE_S)) +#define GPIO_PIN29_INT_TYPE_V 0x7 +#define GPIO_PIN29_INT_TYPE_S 7 +/* GPIO_PIN29_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN29_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC1_BYPASS_M ((GPIO_PIN29_SYNC1_BYPASS_V)<<(GPIO_PIN29_SYNC1_BYPASS_S)) +#define GPIO_PIN29_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN29_SYNC1_BYPASS_S 3 +/* GPIO_PIN29_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN29_PAD_DRIVER (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN29_PAD_DRIVER_V 0x1 +#define GPIO_PIN29_PAD_DRIVER_S 2 +/* GPIO_PIN29_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN29_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN29_SYNC2_BYPASS_M ((GPIO_PIN29_SYNC2_BYPASS_V)<<(GPIO_PIN29_SYNC2_BYPASS_S)) +#define GPIO_PIN29_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN29_SYNC2_BYPASS_S 0 + +#define GPIO_PIN30_REG (DR_REG_GPIO_BASE + 0xEC) +/* GPIO_PIN30_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN30_INT_ENA 0x0000001F +#define GPIO_PIN30_INT_ENA_M ((GPIO_PIN30_INT_ENA_V)<<(GPIO_PIN30_INT_ENA_S)) +#define GPIO_PIN30_INT_ENA_V 0x1F +#define GPIO_PIN30_INT_ENA_S 13 +/* GPIO_PIN30_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN30_CONFIG 0x00000003 +#define GPIO_PIN30_CONFIG_M ((GPIO_PIN30_CONFIG_V)<<(GPIO_PIN30_CONFIG_S)) +#define GPIO_PIN30_CONFIG_V 0x3 +#define GPIO_PIN30_CONFIG_S 11 +/* GPIO_PIN30_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN30_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN30_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN30_WAKEUP_ENABLE_S 10 +/* GPIO_PIN30_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN30_INT_TYPE 0x00000007 +#define GPIO_PIN30_INT_TYPE_M ((GPIO_PIN30_INT_TYPE_V)<<(GPIO_PIN30_INT_TYPE_S)) +#define GPIO_PIN30_INT_TYPE_V 0x7 +#define GPIO_PIN30_INT_TYPE_S 7 +/* GPIO_PIN30_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN30_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC1_BYPASS_M ((GPIO_PIN30_SYNC1_BYPASS_V)<<(GPIO_PIN30_SYNC1_BYPASS_S)) +#define GPIO_PIN30_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN30_SYNC1_BYPASS_S 3 +/* GPIO_PIN30_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN30_PAD_DRIVER (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN30_PAD_DRIVER_V 0x1 +#define GPIO_PIN30_PAD_DRIVER_S 2 +/* GPIO_PIN30_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN30_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN30_SYNC2_BYPASS_M ((GPIO_PIN30_SYNC2_BYPASS_V)<<(GPIO_PIN30_SYNC2_BYPASS_S)) +#define GPIO_PIN30_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN30_SYNC2_BYPASS_S 0 + +#define GPIO_PIN31_REG (DR_REG_GPIO_BASE + 0xF0) +/* GPIO_PIN31_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN31_INT_ENA 0x0000001F +#define GPIO_PIN31_INT_ENA_M ((GPIO_PIN31_INT_ENA_V)<<(GPIO_PIN31_INT_ENA_S)) +#define GPIO_PIN31_INT_ENA_V 0x1F +#define GPIO_PIN31_INT_ENA_S 13 +/* GPIO_PIN31_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN31_CONFIG 0x00000003 +#define GPIO_PIN31_CONFIG_M ((GPIO_PIN31_CONFIG_V)<<(GPIO_PIN31_CONFIG_S)) +#define GPIO_PIN31_CONFIG_V 0x3 +#define GPIO_PIN31_CONFIG_S 11 +/* GPIO_PIN31_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN31_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN31_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN31_WAKEUP_ENABLE_S 10 +/* GPIO_PIN31_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN31_INT_TYPE 0x00000007 +#define GPIO_PIN31_INT_TYPE_M ((GPIO_PIN31_INT_TYPE_V)<<(GPIO_PIN31_INT_TYPE_S)) +#define GPIO_PIN31_INT_TYPE_V 0x7 +#define GPIO_PIN31_INT_TYPE_S 7 +/* GPIO_PIN31_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN31_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC1_BYPASS_M ((GPIO_PIN31_SYNC1_BYPASS_V)<<(GPIO_PIN31_SYNC1_BYPASS_S)) +#define GPIO_PIN31_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN31_SYNC1_BYPASS_S 3 +/* GPIO_PIN31_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN31_PAD_DRIVER (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN31_PAD_DRIVER_V 0x1 +#define GPIO_PIN31_PAD_DRIVER_S 2 +/* GPIO_PIN31_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN31_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN31_SYNC2_BYPASS_M ((GPIO_PIN31_SYNC2_BYPASS_V)<<(GPIO_PIN31_SYNC2_BYPASS_S)) +#define GPIO_PIN31_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN31_SYNC2_BYPASS_S 0 + +#define GPIO_PIN32_REG (DR_REG_GPIO_BASE + 0xF4) +/* GPIO_PIN32_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN32_INT_ENA 0x0000001F +#define GPIO_PIN32_INT_ENA_M ((GPIO_PIN32_INT_ENA_V)<<(GPIO_PIN32_INT_ENA_S)) +#define GPIO_PIN32_INT_ENA_V 0x1F +#define GPIO_PIN32_INT_ENA_S 13 +/* GPIO_PIN32_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN32_CONFIG 0x00000003 +#define GPIO_PIN32_CONFIG_M ((GPIO_PIN32_CONFIG_V)<<(GPIO_PIN32_CONFIG_S)) +#define GPIO_PIN32_CONFIG_V 0x3 +#define GPIO_PIN32_CONFIG_S 11 +/* GPIO_PIN32_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN32_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN32_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN32_WAKEUP_ENABLE_S 10 +/* GPIO_PIN32_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN32_INT_TYPE 0x00000007 +#define GPIO_PIN32_INT_TYPE_M ((GPIO_PIN32_INT_TYPE_V)<<(GPIO_PIN32_INT_TYPE_S)) +#define GPIO_PIN32_INT_TYPE_V 0x7 +#define GPIO_PIN32_INT_TYPE_S 7 +/* GPIO_PIN32_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN32_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC1_BYPASS_M ((GPIO_PIN32_SYNC1_BYPASS_V)<<(GPIO_PIN32_SYNC1_BYPASS_S)) +#define GPIO_PIN32_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN32_SYNC1_BYPASS_S 3 +/* GPIO_PIN32_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN32_PAD_DRIVER (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN32_PAD_DRIVER_V 0x1 +#define GPIO_PIN32_PAD_DRIVER_S 2 +/* GPIO_PIN32_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN32_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN32_SYNC2_BYPASS_M ((GPIO_PIN32_SYNC2_BYPASS_V)<<(GPIO_PIN32_SYNC2_BYPASS_S)) +#define GPIO_PIN32_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN32_SYNC2_BYPASS_S 0 + +#define GPIO_PIN33_REG (DR_REG_GPIO_BASE + 0xF8) +/* GPIO_PIN33_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN33_INT_ENA 0x0000001F +#define GPIO_PIN33_INT_ENA_M ((GPIO_PIN33_INT_ENA_V)<<(GPIO_PIN33_INT_ENA_S)) +#define GPIO_PIN33_INT_ENA_V 0x1F +#define GPIO_PIN33_INT_ENA_S 13 +/* GPIO_PIN33_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN33_CONFIG 0x00000003 +#define GPIO_PIN33_CONFIG_M ((GPIO_PIN33_CONFIG_V)<<(GPIO_PIN33_CONFIG_S)) +#define GPIO_PIN33_CONFIG_V 0x3 +#define GPIO_PIN33_CONFIG_S 11 +/* GPIO_PIN33_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN33_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN33_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN33_WAKEUP_ENABLE_S 10 +/* GPIO_PIN33_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN33_INT_TYPE 0x00000007 +#define GPIO_PIN33_INT_TYPE_M ((GPIO_PIN33_INT_TYPE_V)<<(GPIO_PIN33_INT_TYPE_S)) +#define GPIO_PIN33_INT_TYPE_V 0x7 +#define GPIO_PIN33_INT_TYPE_S 7 +/* GPIO_PIN33_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN33_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC1_BYPASS_M ((GPIO_PIN33_SYNC1_BYPASS_V)<<(GPIO_PIN33_SYNC1_BYPASS_S)) +#define GPIO_PIN33_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN33_SYNC1_BYPASS_S 3 +/* GPIO_PIN33_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN33_PAD_DRIVER (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN33_PAD_DRIVER_V 0x1 +#define GPIO_PIN33_PAD_DRIVER_S 2 +/* GPIO_PIN33_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN33_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN33_SYNC2_BYPASS_M ((GPIO_PIN33_SYNC2_BYPASS_V)<<(GPIO_PIN33_SYNC2_BYPASS_S)) +#define GPIO_PIN33_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN33_SYNC2_BYPASS_S 0 + +#define GPIO_PIN34_REG (DR_REG_GPIO_BASE + 0xFC) +/* GPIO_PIN34_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN34_INT_ENA 0x0000001F +#define GPIO_PIN34_INT_ENA_M ((GPIO_PIN34_INT_ENA_V)<<(GPIO_PIN34_INT_ENA_S)) +#define GPIO_PIN34_INT_ENA_V 0x1F +#define GPIO_PIN34_INT_ENA_S 13 +/* GPIO_PIN34_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN34_CONFIG 0x00000003 +#define GPIO_PIN34_CONFIG_M ((GPIO_PIN34_CONFIG_V)<<(GPIO_PIN34_CONFIG_S)) +#define GPIO_PIN34_CONFIG_V 0x3 +#define GPIO_PIN34_CONFIG_S 11 +/* GPIO_PIN34_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN34_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN34_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN34_WAKEUP_ENABLE_S 10 +/* GPIO_PIN34_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN34_INT_TYPE 0x00000007 +#define GPIO_PIN34_INT_TYPE_M ((GPIO_PIN34_INT_TYPE_V)<<(GPIO_PIN34_INT_TYPE_S)) +#define GPIO_PIN34_INT_TYPE_V 0x7 +#define GPIO_PIN34_INT_TYPE_S 7 +/* GPIO_PIN34_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN34_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC1_BYPASS_M ((GPIO_PIN34_SYNC1_BYPASS_V)<<(GPIO_PIN34_SYNC1_BYPASS_S)) +#define GPIO_PIN34_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN34_SYNC1_BYPASS_S 3 +/* GPIO_PIN34_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN34_PAD_DRIVER (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN34_PAD_DRIVER_V 0x1 +#define GPIO_PIN34_PAD_DRIVER_S 2 +/* GPIO_PIN34_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN34_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN34_SYNC2_BYPASS_M ((GPIO_PIN34_SYNC2_BYPASS_V)<<(GPIO_PIN34_SYNC2_BYPASS_S)) +#define GPIO_PIN34_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN34_SYNC2_BYPASS_S 0 + +#define GPIO_PIN35_REG (DR_REG_GPIO_BASE + 0x100) +/* GPIO_PIN35_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN35_INT_ENA 0x0000001F +#define GPIO_PIN35_INT_ENA_M ((GPIO_PIN35_INT_ENA_V)<<(GPIO_PIN35_INT_ENA_S)) +#define GPIO_PIN35_INT_ENA_V 0x1F +#define GPIO_PIN35_INT_ENA_S 13 +/* GPIO_PIN35_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN35_CONFIG 0x00000003 +#define GPIO_PIN35_CONFIG_M ((GPIO_PIN35_CONFIG_V)<<(GPIO_PIN35_CONFIG_S)) +#define GPIO_PIN35_CONFIG_V 0x3 +#define GPIO_PIN35_CONFIG_S 11 +/* GPIO_PIN35_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN35_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN35_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN35_WAKEUP_ENABLE_S 10 +/* GPIO_PIN35_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN35_INT_TYPE 0x00000007 +#define GPIO_PIN35_INT_TYPE_M ((GPIO_PIN35_INT_TYPE_V)<<(GPIO_PIN35_INT_TYPE_S)) +#define GPIO_PIN35_INT_TYPE_V 0x7 +#define GPIO_PIN35_INT_TYPE_S 7 +/* GPIO_PIN35_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN35_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC1_BYPASS_M ((GPIO_PIN35_SYNC1_BYPASS_V)<<(GPIO_PIN35_SYNC1_BYPASS_S)) +#define GPIO_PIN35_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN35_SYNC1_BYPASS_S 3 +/* GPIO_PIN35_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN35_PAD_DRIVER (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN35_PAD_DRIVER_V 0x1 +#define GPIO_PIN35_PAD_DRIVER_S 2 +/* GPIO_PIN35_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN35_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN35_SYNC2_BYPASS_M ((GPIO_PIN35_SYNC2_BYPASS_V)<<(GPIO_PIN35_SYNC2_BYPASS_S)) +#define GPIO_PIN35_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN35_SYNC2_BYPASS_S 0 + +#define GPIO_PIN36_REG (DR_REG_GPIO_BASE + 0x104) +/* GPIO_PIN36_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN36_INT_ENA 0x0000001F +#define GPIO_PIN36_INT_ENA_M ((GPIO_PIN36_INT_ENA_V)<<(GPIO_PIN36_INT_ENA_S)) +#define GPIO_PIN36_INT_ENA_V 0x1F +#define GPIO_PIN36_INT_ENA_S 13 +/* GPIO_PIN36_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN36_CONFIG 0x00000003 +#define GPIO_PIN36_CONFIG_M ((GPIO_PIN36_CONFIG_V)<<(GPIO_PIN36_CONFIG_S)) +#define GPIO_PIN36_CONFIG_V 0x3 +#define GPIO_PIN36_CONFIG_S 11 +/* GPIO_PIN36_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN36_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN36_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN36_WAKEUP_ENABLE_S 10 +/* GPIO_PIN36_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN36_INT_TYPE 0x00000007 +#define GPIO_PIN36_INT_TYPE_M ((GPIO_PIN36_INT_TYPE_V)<<(GPIO_PIN36_INT_TYPE_S)) +#define GPIO_PIN36_INT_TYPE_V 0x7 +#define GPIO_PIN36_INT_TYPE_S 7 +/* GPIO_PIN36_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN36_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC1_BYPASS_M ((GPIO_PIN36_SYNC1_BYPASS_V)<<(GPIO_PIN36_SYNC1_BYPASS_S)) +#define GPIO_PIN36_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN36_SYNC1_BYPASS_S 3 +/* GPIO_PIN36_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN36_PAD_DRIVER (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN36_PAD_DRIVER_V 0x1 +#define GPIO_PIN36_PAD_DRIVER_S 2 +/* GPIO_PIN36_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN36_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN36_SYNC2_BYPASS_M ((GPIO_PIN36_SYNC2_BYPASS_V)<<(GPIO_PIN36_SYNC2_BYPASS_S)) +#define GPIO_PIN36_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN36_SYNC2_BYPASS_S 0 + +#define GPIO_PIN37_REG (DR_REG_GPIO_BASE + 0x108) +/* GPIO_PIN37_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN37_INT_ENA 0x0000001F +#define GPIO_PIN37_INT_ENA_M ((GPIO_PIN37_INT_ENA_V)<<(GPIO_PIN37_INT_ENA_S)) +#define GPIO_PIN37_INT_ENA_V 0x1F +#define GPIO_PIN37_INT_ENA_S 13 +/* GPIO_PIN37_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN37_CONFIG 0x00000003 +#define GPIO_PIN37_CONFIG_M ((GPIO_PIN37_CONFIG_V)<<(GPIO_PIN37_CONFIG_S)) +#define GPIO_PIN37_CONFIG_V 0x3 +#define GPIO_PIN37_CONFIG_S 11 +/* GPIO_PIN37_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN37_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN37_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN37_WAKEUP_ENABLE_S 10 +/* GPIO_PIN37_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN37_INT_TYPE 0x00000007 +#define GPIO_PIN37_INT_TYPE_M ((GPIO_PIN37_INT_TYPE_V)<<(GPIO_PIN37_INT_TYPE_S)) +#define GPIO_PIN37_INT_TYPE_V 0x7 +#define GPIO_PIN37_INT_TYPE_S 7 +/* GPIO_PIN37_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN37_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC1_BYPASS_M ((GPIO_PIN37_SYNC1_BYPASS_V)<<(GPIO_PIN37_SYNC1_BYPASS_S)) +#define GPIO_PIN37_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN37_SYNC1_BYPASS_S 3 +/* GPIO_PIN37_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN37_PAD_DRIVER (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN37_PAD_DRIVER_V 0x1 +#define GPIO_PIN37_PAD_DRIVER_S 2 +/* GPIO_PIN37_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN37_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN37_SYNC2_BYPASS_M ((GPIO_PIN37_SYNC2_BYPASS_V)<<(GPIO_PIN37_SYNC2_BYPASS_S)) +#define GPIO_PIN37_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN37_SYNC2_BYPASS_S 0 + +#define GPIO_PIN38_REG (DR_REG_GPIO_BASE + 0x10C) +/* GPIO_PIN38_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN38_INT_ENA 0x0000001F +#define GPIO_PIN38_INT_ENA_M ((GPIO_PIN38_INT_ENA_V)<<(GPIO_PIN38_INT_ENA_S)) +#define GPIO_PIN38_INT_ENA_V 0x1F +#define GPIO_PIN38_INT_ENA_S 13 +/* GPIO_PIN38_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN38_CONFIG 0x00000003 +#define GPIO_PIN38_CONFIG_M ((GPIO_PIN38_CONFIG_V)<<(GPIO_PIN38_CONFIG_S)) +#define GPIO_PIN38_CONFIG_V 0x3 +#define GPIO_PIN38_CONFIG_S 11 +/* GPIO_PIN38_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN38_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN38_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN38_WAKEUP_ENABLE_S 10 +/* GPIO_PIN38_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN38_INT_TYPE 0x00000007 +#define GPIO_PIN38_INT_TYPE_M ((GPIO_PIN38_INT_TYPE_V)<<(GPIO_PIN38_INT_TYPE_S)) +#define GPIO_PIN38_INT_TYPE_V 0x7 +#define GPIO_PIN38_INT_TYPE_S 7 +/* GPIO_PIN38_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN38_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC1_BYPASS_M ((GPIO_PIN38_SYNC1_BYPASS_V)<<(GPIO_PIN38_SYNC1_BYPASS_S)) +#define GPIO_PIN38_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN38_SYNC1_BYPASS_S 3 +/* GPIO_PIN38_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN38_PAD_DRIVER (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN38_PAD_DRIVER_V 0x1 +#define GPIO_PIN38_PAD_DRIVER_S 2 +/* GPIO_PIN38_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN38_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN38_SYNC2_BYPASS_M ((GPIO_PIN38_SYNC2_BYPASS_V)<<(GPIO_PIN38_SYNC2_BYPASS_S)) +#define GPIO_PIN38_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN38_SYNC2_BYPASS_S 0 + +#define GPIO_PIN39_REG (DR_REG_GPIO_BASE + 0x110) +/* GPIO_PIN39_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN39_INT_ENA 0x0000001F +#define GPIO_PIN39_INT_ENA_M ((GPIO_PIN39_INT_ENA_V)<<(GPIO_PIN39_INT_ENA_S)) +#define GPIO_PIN39_INT_ENA_V 0x1F +#define GPIO_PIN39_INT_ENA_S 13 +/* GPIO_PIN39_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN39_CONFIG 0x00000003 +#define GPIO_PIN39_CONFIG_M ((GPIO_PIN39_CONFIG_V)<<(GPIO_PIN39_CONFIG_S)) +#define GPIO_PIN39_CONFIG_V 0x3 +#define GPIO_PIN39_CONFIG_S 11 +/* GPIO_PIN39_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN39_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN39_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN39_WAKEUP_ENABLE_S 10 +/* GPIO_PIN39_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN39_INT_TYPE 0x00000007 +#define GPIO_PIN39_INT_TYPE_M ((GPIO_PIN39_INT_TYPE_V)<<(GPIO_PIN39_INT_TYPE_S)) +#define GPIO_PIN39_INT_TYPE_V 0x7 +#define GPIO_PIN39_INT_TYPE_S 7 +/* GPIO_PIN39_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN39_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC1_BYPASS_M ((GPIO_PIN39_SYNC1_BYPASS_V)<<(GPIO_PIN39_SYNC1_BYPASS_S)) +#define GPIO_PIN39_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN39_SYNC1_BYPASS_S 3 +/* GPIO_PIN39_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN39_PAD_DRIVER (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN39_PAD_DRIVER_V 0x1 +#define GPIO_PIN39_PAD_DRIVER_S 2 +/* GPIO_PIN39_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN39_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN39_SYNC2_BYPASS_M ((GPIO_PIN39_SYNC2_BYPASS_V)<<(GPIO_PIN39_SYNC2_BYPASS_S)) +#define GPIO_PIN39_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN39_SYNC2_BYPASS_S 0 + +#define GPIO_PIN40_REG (DR_REG_GPIO_BASE + 0x114) +/* GPIO_PIN40_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN40_INT_ENA 0x0000001F +#define GPIO_PIN40_INT_ENA_M ((GPIO_PIN40_INT_ENA_V)<<(GPIO_PIN40_INT_ENA_S)) +#define GPIO_PIN40_INT_ENA_V 0x1F +#define GPIO_PIN40_INT_ENA_S 13 +/* GPIO_PIN40_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN40_CONFIG 0x00000003 +#define GPIO_PIN40_CONFIG_M ((GPIO_PIN40_CONFIG_V)<<(GPIO_PIN40_CONFIG_S)) +#define GPIO_PIN40_CONFIG_V 0x3 +#define GPIO_PIN40_CONFIG_S 11 +/* GPIO_PIN40_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN40_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN40_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN40_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN40_WAKEUP_ENABLE_S 10 +/* GPIO_PIN40_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN40_INT_TYPE 0x00000007 +#define GPIO_PIN40_INT_TYPE_M ((GPIO_PIN40_INT_TYPE_V)<<(GPIO_PIN40_INT_TYPE_S)) +#define GPIO_PIN40_INT_TYPE_V 0x7 +#define GPIO_PIN40_INT_TYPE_S 7 +/* GPIO_PIN40_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN40_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC1_BYPASS_M ((GPIO_PIN40_SYNC1_BYPASS_V)<<(GPIO_PIN40_SYNC1_BYPASS_S)) +#define GPIO_PIN40_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN40_SYNC1_BYPASS_S 3 +/* GPIO_PIN40_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN40_PAD_DRIVER (BIT(2)) +#define GPIO_PIN40_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN40_PAD_DRIVER_V 0x1 +#define GPIO_PIN40_PAD_DRIVER_S 2 +/* GPIO_PIN40_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN40_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN40_SYNC2_BYPASS_M ((GPIO_PIN40_SYNC2_BYPASS_V)<<(GPIO_PIN40_SYNC2_BYPASS_S)) +#define GPIO_PIN40_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN40_SYNC2_BYPASS_S 0 + +#define GPIO_PIN41_REG (DR_REG_GPIO_BASE + 0x118) +/* GPIO_PIN41_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN41_INT_ENA 0x0000001F +#define GPIO_PIN41_INT_ENA_M ((GPIO_PIN41_INT_ENA_V)<<(GPIO_PIN41_INT_ENA_S)) +#define GPIO_PIN41_INT_ENA_V 0x1F +#define GPIO_PIN41_INT_ENA_S 13 +/* GPIO_PIN41_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN41_CONFIG 0x00000003 +#define GPIO_PIN41_CONFIG_M ((GPIO_PIN41_CONFIG_V)<<(GPIO_PIN41_CONFIG_S)) +#define GPIO_PIN41_CONFIG_V 0x3 +#define GPIO_PIN41_CONFIG_S 11 +/* GPIO_PIN41_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN41_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN41_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN41_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN41_WAKEUP_ENABLE_S 10 +/* GPIO_PIN41_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN41_INT_TYPE 0x00000007 +#define GPIO_PIN41_INT_TYPE_M ((GPIO_PIN41_INT_TYPE_V)<<(GPIO_PIN41_INT_TYPE_S)) +#define GPIO_PIN41_INT_TYPE_V 0x7 +#define GPIO_PIN41_INT_TYPE_S 7 +/* GPIO_PIN41_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN41_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC1_BYPASS_M ((GPIO_PIN41_SYNC1_BYPASS_V)<<(GPIO_PIN41_SYNC1_BYPASS_S)) +#define GPIO_PIN41_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN41_SYNC1_BYPASS_S 3 +/* GPIO_PIN41_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN41_PAD_DRIVER (BIT(2)) +#define GPIO_PIN41_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN41_PAD_DRIVER_V 0x1 +#define GPIO_PIN41_PAD_DRIVER_S 2 +/* GPIO_PIN41_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN41_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN41_SYNC2_BYPASS_M ((GPIO_PIN41_SYNC2_BYPASS_V)<<(GPIO_PIN41_SYNC2_BYPASS_S)) +#define GPIO_PIN41_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN41_SYNC2_BYPASS_S 0 + +#define GPIO_PIN42_REG (DR_REG_GPIO_BASE + 0x11C) +/* GPIO_PIN42_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN42_INT_ENA 0x0000001F +#define GPIO_PIN42_INT_ENA_M ((GPIO_PIN42_INT_ENA_V)<<(GPIO_PIN42_INT_ENA_S)) +#define GPIO_PIN42_INT_ENA_V 0x1F +#define GPIO_PIN42_INT_ENA_S 13 +/* GPIO_PIN42_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN42_CONFIG 0x00000003 +#define GPIO_PIN42_CONFIG_M ((GPIO_PIN42_CONFIG_V)<<(GPIO_PIN42_CONFIG_S)) +#define GPIO_PIN42_CONFIG_V 0x3 +#define GPIO_PIN42_CONFIG_S 11 +/* GPIO_PIN42_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN42_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN42_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN42_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN42_WAKEUP_ENABLE_S 10 +/* GPIO_PIN42_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN42_INT_TYPE 0x00000007 +#define GPIO_PIN42_INT_TYPE_M ((GPIO_PIN42_INT_TYPE_V)<<(GPIO_PIN42_INT_TYPE_S)) +#define GPIO_PIN42_INT_TYPE_V 0x7 +#define GPIO_PIN42_INT_TYPE_S 7 +/* GPIO_PIN42_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN42_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC1_BYPASS_M ((GPIO_PIN42_SYNC1_BYPASS_V)<<(GPIO_PIN42_SYNC1_BYPASS_S)) +#define GPIO_PIN42_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN42_SYNC1_BYPASS_S 3 +/* GPIO_PIN42_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN42_PAD_DRIVER (BIT(2)) +#define GPIO_PIN42_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN42_PAD_DRIVER_V 0x1 +#define GPIO_PIN42_PAD_DRIVER_S 2 +/* GPIO_PIN42_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN42_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN42_SYNC2_BYPASS_M ((GPIO_PIN42_SYNC2_BYPASS_V)<<(GPIO_PIN42_SYNC2_BYPASS_S)) +#define GPIO_PIN42_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN42_SYNC2_BYPASS_S 0 + +#define GPIO_PIN43_REG (DR_REG_GPIO_BASE + 0x120) +/* GPIO_PIN43_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN43_INT_ENA 0x0000001F +#define GPIO_PIN43_INT_ENA_M ((GPIO_PIN43_INT_ENA_V)<<(GPIO_PIN43_INT_ENA_S)) +#define GPIO_PIN43_INT_ENA_V 0x1F +#define GPIO_PIN43_INT_ENA_S 13 +/* GPIO_PIN43_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN43_CONFIG 0x00000003 +#define GPIO_PIN43_CONFIG_M ((GPIO_PIN43_CONFIG_V)<<(GPIO_PIN43_CONFIG_S)) +#define GPIO_PIN43_CONFIG_V 0x3 +#define GPIO_PIN43_CONFIG_S 11 +/* GPIO_PIN43_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN43_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN43_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN43_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN43_WAKEUP_ENABLE_S 10 +/* GPIO_PIN43_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN43_INT_TYPE 0x00000007 +#define GPIO_PIN43_INT_TYPE_M ((GPIO_PIN43_INT_TYPE_V)<<(GPIO_PIN43_INT_TYPE_S)) +#define GPIO_PIN43_INT_TYPE_V 0x7 +#define GPIO_PIN43_INT_TYPE_S 7 +/* GPIO_PIN43_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN43_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC1_BYPASS_M ((GPIO_PIN43_SYNC1_BYPASS_V)<<(GPIO_PIN43_SYNC1_BYPASS_S)) +#define GPIO_PIN43_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN43_SYNC1_BYPASS_S 3 +/* GPIO_PIN43_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN43_PAD_DRIVER (BIT(2)) +#define GPIO_PIN43_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN43_PAD_DRIVER_V 0x1 +#define GPIO_PIN43_PAD_DRIVER_S 2 +/* GPIO_PIN43_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN43_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN43_SYNC2_BYPASS_M ((GPIO_PIN43_SYNC2_BYPASS_V)<<(GPIO_PIN43_SYNC2_BYPASS_S)) +#define GPIO_PIN43_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN43_SYNC2_BYPASS_S 0 + +#define GPIO_PIN44_REG (DR_REG_GPIO_BASE + 0x124) +/* GPIO_PIN44_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN44_INT_ENA 0x0000001F +#define GPIO_PIN44_INT_ENA_M ((GPIO_PIN44_INT_ENA_V)<<(GPIO_PIN44_INT_ENA_S)) +#define GPIO_PIN44_INT_ENA_V 0x1F +#define GPIO_PIN44_INT_ENA_S 13 +/* GPIO_PIN44_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN44_CONFIG 0x00000003 +#define GPIO_PIN44_CONFIG_M ((GPIO_PIN44_CONFIG_V)<<(GPIO_PIN44_CONFIG_S)) +#define GPIO_PIN44_CONFIG_V 0x3 +#define GPIO_PIN44_CONFIG_S 11 +/* GPIO_PIN44_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN44_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN44_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN44_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN44_WAKEUP_ENABLE_S 10 +/* GPIO_PIN44_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN44_INT_TYPE 0x00000007 +#define GPIO_PIN44_INT_TYPE_M ((GPIO_PIN44_INT_TYPE_V)<<(GPIO_PIN44_INT_TYPE_S)) +#define GPIO_PIN44_INT_TYPE_V 0x7 +#define GPIO_PIN44_INT_TYPE_S 7 +/* GPIO_PIN44_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN44_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC1_BYPASS_M ((GPIO_PIN44_SYNC1_BYPASS_V)<<(GPIO_PIN44_SYNC1_BYPASS_S)) +#define GPIO_PIN44_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN44_SYNC1_BYPASS_S 3 +/* GPIO_PIN44_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN44_PAD_DRIVER (BIT(2)) +#define GPIO_PIN44_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN44_PAD_DRIVER_V 0x1 +#define GPIO_PIN44_PAD_DRIVER_S 2 +/* GPIO_PIN44_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN44_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN44_SYNC2_BYPASS_M ((GPIO_PIN44_SYNC2_BYPASS_V)<<(GPIO_PIN44_SYNC2_BYPASS_S)) +#define GPIO_PIN44_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN44_SYNC2_BYPASS_S 0 + +#define GPIO_PIN45_REG (DR_REG_GPIO_BASE + 0x128) +/* GPIO_PIN45_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN45_INT_ENA 0x0000001F +#define GPIO_PIN45_INT_ENA_M ((GPIO_PIN45_INT_ENA_V)<<(GPIO_PIN45_INT_ENA_S)) +#define GPIO_PIN45_INT_ENA_V 0x1F +#define GPIO_PIN45_INT_ENA_S 13 +/* GPIO_PIN45_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN45_CONFIG 0x00000003 +#define GPIO_PIN45_CONFIG_M ((GPIO_PIN45_CONFIG_V)<<(GPIO_PIN45_CONFIG_S)) +#define GPIO_PIN45_CONFIG_V 0x3 +#define GPIO_PIN45_CONFIG_S 11 +/* GPIO_PIN45_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN45_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN45_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN45_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN45_WAKEUP_ENABLE_S 10 +/* GPIO_PIN45_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN45_INT_TYPE 0x00000007 +#define GPIO_PIN45_INT_TYPE_M ((GPIO_PIN45_INT_TYPE_V)<<(GPIO_PIN45_INT_TYPE_S)) +#define GPIO_PIN45_INT_TYPE_V 0x7 +#define GPIO_PIN45_INT_TYPE_S 7 +/* GPIO_PIN45_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN45_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN45_SYNC1_BYPASS_M ((GPIO_PIN45_SYNC1_BYPASS_V)<<(GPIO_PIN45_SYNC1_BYPASS_S)) +#define GPIO_PIN45_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN45_SYNC1_BYPASS_S 3 +/* GPIO_PIN45_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN45_PAD_DRIVER (BIT(2)) +#define GPIO_PIN45_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN45_PAD_DRIVER_V 0x1 +#define GPIO_PIN45_PAD_DRIVER_S 2 +/* GPIO_PIN45_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN45_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN45_SYNC2_BYPASS_M ((GPIO_PIN45_SYNC2_BYPASS_V)<<(GPIO_PIN45_SYNC2_BYPASS_S)) +#define GPIO_PIN45_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN45_SYNC2_BYPASS_S 0 + +#define GPIO_PIN46_REG (DR_REG_GPIO_BASE + 0x12C) +/* GPIO_PIN46_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN46_INT_ENA 0x0000001F +#define GPIO_PIN46_INT_ENA_M ((GPIO_PIN46_INT_ENA_V)<<(GPIO_PIN46_INT_ENA_S)) +#define GPIO_PIN46_INT_ENA_V 0x1F +#define GPIO_PIN46_INT_ENA_S 13 +/* GPIO_PIN46_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN46_CONFIG 0x00000003 +#define GPIO_PIN46_CONFIG_M ((GPIO_PIN46_CONFIG_V)<<(GPIO_PIN46_CONFIG_S)) +#define GPIO_PIN46_CONFIG_V 0x3 +#define GPIO_PIN46_CONFIG_S 11 +/* GPIO_PIN46_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN46_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN46_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN46_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN46_WAKEUP_ENABLE_S 10 +/* GPIO_PIN46_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN46_INT_TYPE 0x00000007 +#define GPIO_PIN46_INT_TYPE_M ((GPIO_PIN46_INT_TYPE_V)<<(GPIO_PIN46_INT_TYPE_S)) +#define GPIO_PIN46_INT_TYPE_V 0x7 +#define GPIO_PIN46_INT_TYPE_S 7 +/* GPIO_PIN46_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN46_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN46_SYNC1_BYPASS_M ((GPIO_PIN46_SYNC1_BYPASS_V)<<(GPIO_PIN46_SYNC1_BYPASS_S)) +#define GPIO_PIN46_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN46_SYNC1_BYPASS_S 3 +/* GPIO_PIN46_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN46_PAD_DRIVER (BIT(2)) +#define GPIO_PIN46_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN46_PAD_DRIVER_V 0x1 +#define GPIO_PIN46_PAD_DRIVER_S 2 +/* GPIO_PIN46_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN46_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN46_SYNC2_BYPASS_M ((GPIO_PIN46_SYNC2_BYPASS_V)<<(GPIO_PIN46_SYNC2_BYPASS_S)) +#define GPIO_PIN46_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN46_SYNC2_BYPASS_S 0 + +#define GPIO_PIN47_REG (DR_REG_GPIO_BASE + 0x130) +/* GPIO_PIN47_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN47_INT_ENA 0x0000001F +#define GPIO_PIN47_INT_ENA_M ((GPIO_PIN47_INT_ENA_V)<<(GPIO_PIN47_INT_ENA_S)) +#define GPIO_PIN47_INT_ENA_V 0x1F +#define GPIO_PIN47_INT_ENA_S 13 +/* GPIO_PIN47_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN47_CONFIG 0x00000003 +#define GPIO_PIN47_CONFIG_M ((GPIO_PIN47_CONFIG_V)<<(GPIO_PIN47_CONFIG_S)) +#define GPIO_PIN47_CONFIG_V 0x3 +#define GPIO_PIN47_CONFIG_S 11 +/* GPIO_PIN47_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN47_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN47_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN47_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN47_WAKEUP_ENABLE_S 10 +/* GPIO_PIN47_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN47_INT_TYPE 0x00000007 +#define GPIO_PIN47_INT_TYPE_M ((GPIO_PIN47_INT_TYPE_V)<<(GPIO_PIN47_INT_TYPE_S)) +#define GPIO_PIN47_INT_TYPE_V 0x7 +#define GPIO_PIN47_INT_TYPE_S 7 +/* GPIO_PIN47_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN47_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN47_SYNC1_BYPASS_M ((GPIO_PIN47_SYNC1_BYPASS_V)<<(GPIO_PIN47_SYNC1_BYPASS_S)) +#define GPIO_PIN47_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN47_SYNC1_BYPASS_S 3 +/* GPIO_PIN47_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN47_PAD_DRIVER (BIT(2)) +#define GPIO_PIN47_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN47_PAD_DRIVER_V 0x1 +#define GPIO_PIN47_PAD_DRIVER_S 2 +/* GPIO_PIN47_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN47_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN47_SYNC2_BYPASS_M ((GPIO_PIN47_SYNC2_BYPASS_V)<<(GPIO_PIN47_SYNC2_BYPASS_S)) +#define GPIO_PIN47_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN47_SYNC2_BYPASS_S 0 + +#define GPIO_PIN48_REG (DR_REG_GPIO_BASE + 0x134) +/* GPIO_PIN48_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN48_INT_ENA 0x0000001F +#define GPIO_PIN48_INT_ENA_M ((GPIO_PIN48_INT_ENA_V)<<(GPIO_PIN48_INT_ENA_S)) +#define GPIO_PIN48_INT_ENA_V 0x1F +#define GPIO_PIN48_INT_ENA_S 13 +/* GPIO_PIN48_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN48_CONFIG 0x00000003 +#define GPIO_PIN48_CONFIG_M ((GPIO_PIN48_CONFIG_V)<<(GPIO_PIN48_CONFIG_S)) +#define GPIO_PIN48_CONFIG_V 0x3 +#define GPIO_PIN48_CONFIG_S 11 +/* GPIO_PIN48_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN48_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN48_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN48_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN48_WAKEUP_ENABLE_S 10 +/* GPIO_PIN48_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN48_INT_TYPE 0x00000007 +#define GPIO_PIN48_INT_TYPE_M ((GPIO_PIN48_INT_TYPE_V)<<(GPIO_PIN48_INT_TYPE_S)) +#define GPIO_PIN48_INT_TYPE_V 0x7 +#define GPIO_PIN48_INT_TYPE_S 7 +/* GPIO_PIN48_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN48_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN48_SYNC1_BYPASS_M ((GPIO_PIN48_SYNC1_BYPASS_V)<<(GPIO_PIN48_SYNC1_BYPASS_S)) +#define GPIO_PIN48_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN48_SYNC1_BYPASS_S 3 +/* GPIO_PIN48_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN48_PAD_DRIVER (BIT(2)) +#define GPIO_PIN48_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN48_PAD_DRIVER_V 0x1 +#define GPIO_PIN48_PAD_DRIVER_S 2 +/* GPIO_PIN48_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN48_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN48_SYNC2_BYPASS_M ((GPIO_PIN48_SYNC2_BYPASS_V)<<(GPIO_PIN48_SYNC2_BYPASS_S)) +#define GPIO_PIN48_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN48_SYNC2_BYPASS_S 0 + +#define GPIO_PIN49_REG (DR_REG_GPIO_BASE + 0x138) +/* GPIO_PIN49_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN49_INT_ENA 0x0000001F +#define GPIO_PIN49_INT_ENA_M ((GPIO_PIN49_INT_ENA_V)<<(GPIO_PIN49_INT_ENA_S)) +#define GPIO_PIN49_INT_ENA_V 0x1F +#define GPIO_PIN49_INT_ENA_S 13 +/* GPIO_PIN49_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN49_CONFIG 0x00000003 +#define GPIO_PIN49_CONFIG_M ((GPIO_PIN49_CONFIG_V)<<(GPIO_PIN49_CONFIG_S)) +#define GPIO_PIN49_CONFIG_V 0x3 +#define GPIO_PIN49_CONFIG_S 11 +/* GPIO_PIN49_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN49_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN49_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN49_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN49_WAKEUP_ENABLE_S 10 +/* GPIO_PIN49_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN49_INT_TYPE 0x00000007 +#define GPIO_PIN49_INT_TYPE_M ((GPIO_PIN49_INT_TYPE_V)<<(GPIO_PIN49_INT_TYPE_S)) +#define GPIO_PIN49_INT_TYPE_V 0x7 +#define GPIO_PIN49_INT_TYPE_S 7 +/* GPIO_PIN49_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN49_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN49_SYNC1_BYPASS_M ((GPIO_PIN49_SYNC1_BYPASS_V)<<(GPIO_PIN49_SYNC1_BYPASS_S)) +#define GPIO_PIN49_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN49_SYNC1_BYPASS_S 3 +/* GPIO_PIN49_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN49_PAD_DRIVER (BIT(2)) +#define GPIO_PIN49_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN49_PAD_DRIVER_V 0x1 +#define GPIO_PIN49_PAD_DRIVER_S 2 +/* GPIO_PIN49_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN49_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN49_SYNC2_BYPASS_M ((GPIO_PIN49_SYNC2_BYPASS_V)<<(GPIO_PIN49_SYNC2_BYPASS_S)) +#define GPIO_PIN49_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN49_SYNC2_BYPASS_S 0 + +#define GPIO_PIN50_REG (DR_REG_GPIO_BASE + 0x13C) +/* GPIO_PIN50_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN50_INT_ENA 0x0000001F +#define GPIO_PIN50_INT_ENA_M ((GPIO_PIN50_INT_ENA_V)<<(GPIO_PIN50_INT_ENA_S)) +#define GPIO_PIN50_INT_ENA_V 0x1F +#define GPIO_PIN50_INT_ENA_S 13 +/* GPIO_PIN50_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN50_CONFIG 0x00000003 +#define GPIO_PIN50_CONFIG_M ((GPIO_PIN50_CONFIG_V)<<(GPIO_PIN50_CONFIG_S)) +#define GPIO_PIN50_CONFIG_V 0x3 +#define GPIO_PIN50_CONFIG_S 11 +/* GPIO_PIN50_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN50_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN50_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN50_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN50_WAKEUP_ENABLE_S 10 +/* GPIO_PIN50_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN50_INT_TYPE 0x00000007 +#define GPIO_PIN50_INT_TYPE_M ((GPIO_PIN50_INT_TYPE_V)<<(GPIO_PIN50_INT_TYPE_S)) +#define GPIO_PIN50_INT_TYPE_V 0x7 +#define GPIO_PIN50_INT_TYPE_S 7 +/* GPIO_PIN50_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN50_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN50_SYNC1_BYPASS_M ((GPIO_PIN50_SYNC1_BYPASS_V)<<(GPIO_PIN50_SYNC1_BYPASS_S)) +#define GPIO_PIN50_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN50_SYNC1_BYPASS_S 3 +/* GPIO_PIN50_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN50_PAD_DRIVER (BIT(2)) +#define GPIO_PIN50_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN50_PAD_DRIVER_V 0x1 +#define GPIO_PIN50_PAD_DRIVER_S 2 +/* GPIO_PIN50_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN50_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN50_SYNC2_BYPASS_M ((GPIO_PIN50_SYNC2_BYPASS_V)<<(GPIO_PIN50_SYNC2_BYPASS_S)) +#define GPIO_PIN50_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN50_SYNC2_BYPASS_S 0 + +#define GPIO_PIN51_REG (DR_REG_GPIO_BASE + 0x140) +/* GPIO_PIN51_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN51_INT_ENA 0x0000001F +#define GPIO_PIN51_INT_ENA_M ((GPIO_PIN51_INT_ENA_V)<<(GPIO_PIN51_INT_ENA_S)) +#define GPIO_PIN51_INT_ENA_V 0x1F +#define GPIO_PIN51_INT_ENA_S 13 +/* GPIO_PIN51_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN51_CONFIG 0x00000003 +#define GPIO_PIN51_CONFIG_M ((GPIO_PIN51_CONFIG_V)<<(GPIO_PIN51_CONFIG_S)) +#define GPIO_PIN51_CONFIG_V 0x3 +#define GPIO_PIN51_CONFIG_S 11 +/* GPIO_PIN51_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN51_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN51_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN51_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN51_WAKEUP_ENABLE_S 10 +/* GPIO_PIN51_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN51_INT_TYPE 0x00000007 +#define GPIO_PIN51_INT_TYPE_M ((GPIO_PIN51_INT_TYPE_V)<<(GPIO_PIN51_INT_TYPE_S)) +#define GPIO_PIN51_INT_TYPE_V 0x7 +#define GPIO_PIN51_INT_TYPE_S 7 +/* GPIO_PIN51_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN51_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN51_SYNC1_BYPASS_M ((GPIO_PIN51_SYNC1_BYPASS_V)<<(GPIO_PIN51_SYNC1_BYPASS_S)) +#define GPIO_PIN51_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN51_SYNC1_BYPASS_S 3 +/* GPIO_PIN51_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN51_PAD_DRIVER (BIT(2)) +#define GPIO_PIN51_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN51_PAD_DRIVER_V 0x1 +#define GPIO_PIN51_PAD_DRIVER_S 2 +/* GPIO_PIN51_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN51_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN51_SYNC2_BYPASS_M ((GPIO_PIN51_SYNC2_BYPASS_V)<<(GPIO_PIN51_SYNC2_BYPASS_S)) +#define GPIO_PIN51_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN51_SYNC2_BYPASS_S 0 + +#define GPIO_PIN52_REG (DR_REG_GPIO_BASE + 0x144) +/* GPIO_PIN52_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN52_INT_ENA 0x0000001F +#define GPIO_PIN52_INT_ENA_M ((GPIO_PIN52_INT_ENA_V)<<(GPIO_PIN52_INT_ENA_S)) +#define GPIO_PIN52_INT_ENA_V 0x1F +#define GPIO_PIN52_INT_ENA_S 13 +/* GPIO_PIN52_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN52_CONFIG 0x00000003 +#define GPIO_PIN52_CONFIG_M ((GPIO_PIN52_CONFIG_V)<<(GPIO_PIN52_CONFIG_S)) +#define GPIO_PIN52_CONFIG_V 0x3 +#define GPIO_PIN52_CONFIG_S 11 +/* GPIO_PIN52_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN52_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN52_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN52_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN52_WAKEUP_ENABLE_S 10 +/* GPIO_PIN52_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN52_INT_TYPE 0x00000007 +#define GPIO_PIN52_INT_TYPE_M ((GPIO_PIN52_INT_TYPE_V)<<(GPIO_PIN52_INT_TYPE_S)) +#define GPIO_PIN52_INT_TYPE_V 0x7 +#define GPIO_PIN52_INT_TYPE_S 7 +/* GPIO_PIN52_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN52_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN52_SYNC1_BYPASS_M ((GPIO_PIN52_SYNC1_BYPASS_V)<<(GPIO_PIN52_SYNC1_BYPASS_S)) +#define GPIO_PIN52_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN52_SYNC1_BYPASS_S 3 +/* GPIO_PIN52_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN52_PAD_DRIVER (BIT(2)) +#define GPIO_PIN52_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN52_PAD_DRIVER_V 0x1 +#define GPIO_PIN52_PAD_DRIVER_S 2 +/* GPIO_PIN52_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN52_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN52_SYNC2_BYPASS_M ((GPIO_PIN52_SYNC2_BYPASS_V)<<(GPIO_PIN52_SYNC2_BYPASS_S)) +#define GPIO_PIN52_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN52_SYNC2_BYPASS_S 0 + +#define GPIO_PIN53_REG (DR_REG_GPIO_BASE + 0x148) +/* GPIO_PIN53_INT_ENA : R/W ;bitpos:[17:13] ;default: 5'h0 ; */ +/*description: */ +#define GPIO_PIN53_INT_ENA 0x0000001F +#define GPIO_PIN53_INT_ENA_M ((GPIO_PIN53_INT_ENA_V)<<(GPIO_PIN53_INT_ENA_S)) +#define GPIO_PIN53_INT_ENA_V 0x1F +#define GPIO_PIN53_INT_ENA_S 13 +/* GPIO_PIN53_CONFIG : R/W ;bitpos:[12:11] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN53_CONFIG 0x00000003 +#define GPIO_PIN53_CONFIG_M ((GPIO_PIN53_CONFIG_V)<<(GPIO_PIN53_CONFIG_S)) +#define GPIO_PIN53_CONFIG_V 0x3 +#define GPIO_PIN53_CONFIG_S 11 +/* GPIO_PIN53_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN53_WAKEUP_ENABLE (BIT(10)) +#define GPIO_PIN53_WAKEUP_ENABLE_M (BIT(10)) +#define GPIO_PIN53_WAKEUP_ENABLE_V 0x1 +#define GPIO_PIN53_WAKEUP_ENABLE_S 10 +/* GPIO_PIN53_INT_TYPE : R/W ;bitpos:[9:7] ;default: 3'h0 ; */ +/*description: */ +#define GPIO_PIN53_INT_TYPE 0x00000007 +#define GPIO_PIN53_INT_TYPE_M ((GPIO_PIN53_INT_TYPE_V)<<(GPIO_PIN53_INT_TYPE_S)) +#define GPIO_PIN53_INT_TYPE_V 0x7 +#define GPIO_PIN53_INT_TYPE_S 7 +/* GPIO_PIN53_SYNC1_BYPASS : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN53_SYNC1_BYPASS 0x00000003 +#define GPIO_PIN53_SYNC1_BYPASS_M ((GPIO_PIN53_SYNC1_BYPASS_V)<<(GPIO_PIN53_SYNC1_BYPASS_S)) +#define GPIO_PIN53_SYNC1_BYPASS_V 0x3 +#define GPIO_PIN53_SYNC1_BYPASS_S 3 +/* GPIO_PIN53_PAD_DRIVER : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_PIN53_PAD_DRIVER (BIT(2)) +#define GPIO_PIN53_PAD_DRIVER_M (BIT(2)) +#define GPIO_PIN53_PAD_DRIVER_V 0x1 +#define GPIO_PIN53_PAD_DRIVER_S 2 +/* GPIO_PIN53_SYNC2_BYPASS : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: */ +#define GPIO_PIN53_SYNC2_BYPASS 0x00000003 +#define GPIO_PIN53_SYNC2_BYPASS_M ((GPIO_PIN53_SYNC2_BYPASS_V)<<(GPIO_PIN53_SYNC2_BYPASS_S)) +#define GPIO_PIN53_SYNC2_BYPASS_V 0x3 +#define GPIO_PIN53_SYNC2_BYPASS_S 0 + +#define GPIO_STATUS_NEXT_REG (DR_REG_GPIO_BASE + 0x14C) +/* GPIO_STATUS_INTERRUPT_NEXT : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define GPIO_STATUS_INTERRUPT_NEXT 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_M ((GPIO_STATUS_INTERRUPT_NEXT_V)<<(GPIO_STATUS_INTERRUPT_NEXT_S)) +#define GPIO_STATUS_INTERRUPT_NEXT_V 0xFFFFFFFF +#define GPIO_STATUS_INTERRUPT_NEXT_S 0 + +#define GPIO_STATUS_NEXT1_REG (DR_REG_GPIO_BASE + 0x150) +/* GPIO_STATUS_INTERRUPT_NEXT1 : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define GPIO_STATUS_INTERRUPT_NEXT1 0x003FFFFF +#define GPIO_STATUS_INTERRUPT_NEXT1_M ((GPIO_STATUS_INTERRUPT_NEXT1_V)<<(GPIO_STATUS_INTERRUPT_NEXT1_S)) +#define GPIO_STATUS_INTERRUPT_NEXT1_V 0x3FFFFF +#define GPIO_STATUS_INTERRUPT_NEXT1_S 0 + +#define GPIO_FUNC0_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x154) +/* GPIO_SIG0_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG0_IN_SEL (BIT(7)) +#define GPIO_SIG0_IN_SEL_M (BIT(7)) +#define GPIO_SIG0_IN_SEL_V 0x1 +#define GPIO_SIG0_IN_SEL_S 7 +/* GPIO_FUNC0_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC0_IN_INV_SEL_V 0x1 +#define GPIO_FUNC0_IN_INV_SEL_S 6 +/* GPIO_FUNC0_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC0_IN_SEL 0x0000003F +#define GPIO_FUNC0_IN_SEL_M ((GPIO_FUNC0_IN_SEL_V)<<(GPIO_FUNC0_IN_SEL_S)) +#define GPIO_FUNC0_IN_SEL_V 0x3F +#define GPIO_FUNC0_IN_SEL_S 0 + +#define GPIO_FUNC1_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x158) +/* GPIO_SIG1_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG1_IN_SEL (BIT(7)) +#define GPIO_SIG1_IN_SEL_M (BIT(7)) +#define GPIO_SIG1_IN_SEL_V 0x1 +#define GPIO_SIG1_IN_SEL_S 7 +/* GPIO_FUNC1_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC1_IN_INV_SEL_V 0x1 +#define GPIO_FUNC1_IN_INV_SEL_S 6 +/* GPIO_FUNC1_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC1_IN_SEL 0x0000003F +#define GPIO_FUNC1_IN_SEL_M ((GPIO_FUNC1_IN_SEL_V)<<(GPIO_FUNC1_IN_SEL_S)) +#define GPIO_FUNC1_IN_SEL_V 0x3F +#define GPIO_FUNC1_IN_SEL_S 0 + +#define GPIO_FUNC2_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x15C) +/* GPIO_SIG2_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG2_IN_SEL (BIT(7)) +#define GPIO_SIG2_IN_SEL_M (BIT(7)) +#define GPIO_SIG2_IN_SEL_V 0x1 +#define GPIO_SIG2_IN_SEL_S 7 +/* GPIO_FUNC2_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC2_IN_INV_SEL_V 0x1 +#define GPIO_FUNC2_IN_INV_SEL_S 6 +/* GPIO_FUNC2_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC2_IN_SEL 0x0000003F +#define GPIO_FUNC2_IN_SEL_M ((GPIO_FUNC2_IN_SEL_V)<<(GPIO_FUNC2_IN_SEL_S)) +#define GPIO_FUNC2_IN_SEL_V 0x3F +#define GPIO_FUNC2_IN_SEL_S 0 + +#define GPIO_FUNC3_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x160) +/* GPIO_SIG3_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG3_IN_SEL (BIT(7)) +#define GPIO_SIG3_IN_SEL_M (BIT(7)) +#define GPIO_SIG3_IN_SEL_V 0x1 +#define GPIO_SIG3_IN_SEL_S 7 +/* GPIO_FUNC3_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC3_IN_INV_SEL_V 0x1 +#define GPIO_FUNC3_IN_INV_SEL_S 6 +/* GPIO_FUNC3_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC3_IN_SEL 0x0000003F +#define GPIO_FUNC3_IN_SEL_M ((GPIO_FUNC3_IN_SEL_V)<<(GPIO_FUNC3_IN_SEL_S)) +#define GPIO_FUNC3_IN_SEL_V 0x3F +#define GPIO_FUNC3_IN_SEL_S 0 + +#define GPIO_FUNC4_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x164) +/* GPIO_SIG4_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG4_IN_SEL (BIT(7)) +#define GPIO_SIG4_IN_SEL_M (BIT(7)) +#define GPIO_SIG4_IN_SEL_V 0x1 +#define GPIO_SIG4_IN_SEL_S 7 +/* GPIO_FUNC4_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC4_IN_INV_SEL_V 0x1 +#define GPIO_FUNC4_IN_INV_SEL_S 6 +/* GPIO_FUNC4_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC4_IN_SEL 0x0000003F +#define GPIO_FUNC4_IN_SEL_M ((GPIO_FUNC4_IN_SEL_V)<<(GPIO_FUNC4_IN_SEL_S)) +#define GPIO_FUNC4_IN_SEL_V 0x3F +#define GPIO_FUNC4_IN_SEL_S 0 + +#define GPIO_FUNC5_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x168) +/* GPIO_SIG5_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG5_IN_SEL (BIT(7)) +#define GPIO_SIG5_IN_SEL_M (BIT(7)) +#define GPIO_SIG5_IN_SEL_V 0x1 +#define GPIO_SIG5_IN_SEL_S 7 +/* GPIO_FUNC5_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC5_IN_INV_SEL_V 0x1 +#define GPIO_FUNC5_IN_INV_SEL_S 6 +/* GPIO_FUNC5_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC5_IN_SEL 0x0000003F +#define GPIO_FUNC5_IN_SEL_M ((GPIO_FUNC5_IN_SEL_V)<<(GPIO_FUNC5_IN_SEL_S)) +#define GPIO_FUNC5_IN_SEL_V 0x3F +#define GPIO_FUNC5_IN_SEL_S 0 + +#define GPIO_FUNC6_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x16C) +/* GPIO_SIG6_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG6_IN_SEL (BIT(7)) +#define GPIO_SIG6_IN_SEL_M (BIT(7)) +#define GPIO_SIG6_IN_SEL_V 0x1 +#define GPIO_SIG6_IN_SEL_S 7 +/* GPIO_FUNC6_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC6_IN_INV_SEL_V 0x1 +#define GPIO_FUNC6_IN_INV_SEL_S 6 +/* GPIO_FUNC6_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC6_IN_SEL 0x0000003F +#define GPIO_FUNC6_IN_SEL_M ((GPIO_FUNC6_IN_SEL_V)<<(GPIO_FUNC6_IN_SEL_S)) +#define GPIO_FUNC6_IN_SEL_V 0x3F +#define GPIO_FUNC6_IN_SEL_S 0 + +#define GPIO_FUNC7_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x170) +/* GPIO_SIG7_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG7_IN_SEL (BIT(7)) +#define GPIO_SIG7_IN_SEL_M (BIT(7)) +#define GPIO_SIG7_IN_SEL_V 0x1 +#define GPIO_SIG7_IN_SEL_S 7 +/* GPIO_FUNC7_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC7_IN_INV_SEL_V 0x1 +#define GPIO_FUNC7_IN_INV_SEL_S 6 +/* GPIO_FUNC7_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC7_IN_SEL 0x0000003F +#define GPIO_FUNC7_IN_SEL_M ((GPIO_FUNC7_IN_SEL_V)<<(GPIO_FUNC7_IN_SEL_S)) +#define GPIO_FUNC7_IN_SEL_V 0x3F +#define GPIO_FUNC7_IN_SEL_S 0 + +#define GPIO_FUNC8_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x174) +/* GPIO_SIG8_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG8_IN_SEL (BIT(7)) +#define GPIO_SIG8_IN_SEL_M (BIT(7)) +#define GPIO_SIG8_IN_SEL_V 0x1 +#define GPIO_SIG8_IN_SEL_S 7 +/* GPIO_FUNC8_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC8_IN_INV_SEL_V 0x1 +#define GPIO_FUNC8_IN_INV_SEL_S 6 +/* GPIO_FUNC8_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC8_IN_SEL 0x0000003F +#define GPIO_FUNC8_IN_SEL_M ((GPIO_FUNC8_IN_SEL_V)<<(GPIO_FUNC8_IN_SEL_S)) +#define GPIO_FUNC8_IN_SEL_V 0x3F +#define GPIO_FUNC8_IN_SEL_S 0 + +#define GPIO_FUNC9_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x178) +/* GPIO_SIG9_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG9_IN_SEL (BIT(7)) +#define GPIO_SIG9_IN_SEL_M (BIT(7)) +#define GPIO_SIG9_IN_SEL_V 0x1 +#define GPIO_SIG9_IN_SEL_S 7 +/* GPIO_FUNC9_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC9_IN_INV_SEL_V 0x1 +#define GPIO_FUNC9_IN_INV_SEL_S 6 +/* GPIO_FUNC9_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC9_IN_SEL 0x0000003F +#define GPIO_FUNC9_IN_SEL_M ((GPIO_FUNC9_IN_SEL_V)<<(GPIO_FUNC9_IN_SEL_S)) +#define GPIO_FUNC9_IN_SEL_V 0x3F +#define GPIO_FUNC9_IN_SEL_S 0 + +#define GPIO_FUNC10_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x17C) +/* GPIO_SIG10_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG10_IN_SEL (BIT(7)) +#define GPIO_SIG10_IN_SEL_M (BIT(7)) +#define GPIO_SIG10_IN_SEL_V 0x1 +#define GPIO_SIG10_IN_SEL_S 7 +/* GPIO_FUNC10_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC10_IN_INV_SEL_V 0x1 +#define GPIO_FUNC10_IN_INV_SEL_S 6 +/* GPIO_FUNC10_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC10_IN_SEL 0x0000003F +#define GPIO_FUNC10_IN_SEL_M ((GPIO_FUNC10_IN_SEL_V)<<(GPIO_FUNC10_IN_SEL_S)) +#define GPIO_FUNC10_IN_SEL_V 0x3F +#define GPIO_FUNC10_IN_SEL_S 0 + +#define GPIO_FUNC11_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x180) +/* GPIO_SIG11_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG11_IN_SEL (BIT(7)) +#define GPIO_SIG11_IN_SEL_M (BIT(7)) +#define GPIO_SIG11_IN_SEL_V 0x1 +#define GPIO_SIG11_IN_SEL_S 7 +/* GPIO_FUNC11_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC11_IN_INV_SEL_V 0x1 +#define GPIO_FUNC11_IN_INV_SEL_S 6 +/* GPIO_FUNC11_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC11_IN_SEL 0x0000003F +#define GPIO_FUNC11_IN_SEL_M ((GPIO_FUNC11_IN_SEL_V)<<(GPIO_FUNC11_IN_SEL_S)) +#define GPIO_FUNC11_IN_SEL_V 0x3F +#define GPIO_FUNC11_IN_SEL_S 0 + +#define GPIO_FUNC12_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x184) +/* GPIO_SIG12_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG12_IN_SEL (BIT(7)) +#define GPIO_SIG12_IN_SEL_M (BIT(7)) +#define GPIO_SIG12_IN_SEL_V 0x1 +#define GPIO_SIG12_IN_SEL_S 7 +/* GPIO_FUNC12_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC12_IN_INV_SEL_V 0x1 +#define GPIO_FUNC12_IN_INV_SEL_S 6 +/* GPIO_FUNC12_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC12_IN_SEL 0x0000003F +#define GPIO_FUNC12_IN_SEL_M ((GPIO_FUNC12_IN_SEL_V)<<(GPIO_FUNC12_IN_SEL_S)) +#define GPIO_FUNC12_IN_SEL_V 0x3F +#define GPIO_FUNC12_IN_SEL_S 0 + +#define GPIO_FUNC13_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x188) +/* GPIO_SIG13_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG13_IN_SEL (BIT(7)) +#define GPIO_SIG13_IN_SEL_M (BIT(7)) +#define GPIO_SIG13_IN_SEL_V 0x1 +#define GPIO_SIG13_IN_SEL_S 7 +/* GPIO_FUNC13_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC13_IN_INV_SEL_V 0x1 +#define GPIO_FUNC13_IN_INV_SEL_S 6 +/* GPIO_FUNC13_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC13_IN_SEL 0x0000003F +#define GPIO_FUNC13_IN_SEL_M ((GPIO_FUNC13_IN_SEL_V)<<(GPIO_FUNC13_IN_SEL_S)) +#define GPIO_FUNC13_IN_SEL_V 0x3F +#define GPIO_FUNC13_IN_SEL_S 0 + +#define GPIO_FUNC14_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x18C) +/* GPIO_SIG14_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG14_IN_SEL (BIT(7)) +#define GPIO_SIG14_IN_SEL_M (BIT(7)) +#define GPIO_SIG14_IN_SEL_V 0x1 +#define GPIO_SIG14_IN_SEL_S 7 +/* GPIO_FUNC14_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC14_IN_INV_SEL_V 0x1 +#define GPIO_FUNC14_IN_INV_SEL_S 6 +/* GPIO_FUNC14_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC14_IN_SEL 0x0000003F +#define GPIO_FUNC14_IN_SEL_M ((GPIO_FUNC14_IN_SEL_V)<<(GPIO_FUNC14_IN_SEL_S)) +#define GPIO_FUNC14_IN_SEL_V 0x3F +#define GPIO_FUNC14_IN_SEL_S 0 + +#define GPIO_FUNC15_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x190) +/* GPIO_SIG15_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG15_IN_SEL (BIT(7)) +#define GPIO_SIG15_IN_SEL_M (BIT(7)) +#define GPIO_SIG15_IN_SEL_V 0x1 +#define GPIO_SIG15_IN_SEL_S 7 +/* GPIO_FUNC15_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC15_IN_INV_SEL_V 0x1 +#define GPIO_FUNC15_IN_INV_SEL_S 6 +/* GPIO_FUNC15_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC15_IN_SEL 0x0000003F +#define GPIO_FUNC15_IN_SEL_M ((GPIO_FUNC15_IN_SEL_V)<<(GPIO_FUNC15_IN_SEL_S)) +#define GPIO_FUNC15_IN_SEL_V 0x3F +#define GPIO_FUNC15_IN_SEL_S 0 + +#define GPIO_FUNC16_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x194) +/* GPIO_SIG16_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG16_IN_SEL (BIT(7)) +#define GPIO_SIG16_IN_SEL_M (BIT(7)) +#define GPIO_SIG16_IN_SEL_V 0x1 +#define GPIO_SIG16_IN_SEL_S 7 +/* GPIO_FUNC16_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC16_IN_INV_SEL_V 0x1 +#define GPIO_FUNC16_IN_INV_SEL_S 6 +/* GPIO_FUNC16_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC16_IN_SEL 0x0000003F +#define GPIO_FUNC16_IN_SEL_M ((GPIO_FUNC16_IN_SEL_V)<<(GPIO_FUNC16_IN_SEL_S)) +#define GPIO_FUNC16_IN_SEL_V 0x3F +#define GPIO_FUNC16_IN_SEL_S 0 + +#define GPIO_FUNC17_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x198) +/* GPIO_SIG17_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG17_IN_SEL (BIT(7)) +#define GPIO_SIG17_IN_SEL_M (BIT(7)) +#define GPIO_SIG17_IN_SEL_V 0x1 +#define GPIO_SIG17_IN_SEL_S 7 +/* GPIO_FUNC17_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC17_IN_INV_SEL_V 0x1 +#define GPIO_FUNC17_IN_INV_SEL_S 6 +/* GPIO_FUNC17_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC17_IN_SEL 0x0000003F +#define GPIO_FUNC17_IN_SEL_M ((GPIO_FUNC17_IN_SEL_V)<<(GPIO_FUNC17_IN_SEL_S)) +#define GPIO_FUNC17_IN_SEL_V 0x3F +#define GPIO_FUNC17_IN_SEL_S 0 + +#define GPIO_FUNC18_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x19C) +/* GPIO_SIG18_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG18_IN_SEL (BIT(7)) +#define GPIO_SIG18_IN_SEL_M (BIT(7)) +#define GPIO_SIG18_IN_SEL_V 0x1 +#define GPIO_SIG18_IN_SEL_S 7 +/* GPIO_FUNC18_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC18_IN_INV_SEL_V 0x1 +#define GPIO_FUNC18_IN_INV_SEL_S 6 +/* GPIO_FUNC18_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC18_IN_SEL 0x0000003F +#define GPIO_FUNC18_IN_SEL_M ((GPIO_FUNC18_IN_SEL_V)<<(GPIO_FUNC18_IN_SEL_S)) +#define GPIO_FUNC18_IN_SEL_V 0x3F +#define GPIO_FUNC18_IN_SEL_S 0 + +#define GPIO_FUNC19_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A0) +/* GPIO_SIG19_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG19_IN_SEL (BIT(7)) +#define GPIO_SIG19_IN_SEL_M (BIT(7)) +#define GPIO_SIG19_IN_SEL_V 0x1 +#define GPIO_SIG19_IN_SEL_S 7 +/* GPIO_FUNC19_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC19_IN_INV_SEL_V 0x1 +#define GPIO_FUNC19_IN_INV_SEL_S 6 +/* GPIO_FUNC19_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC19_IN_SEL 0x0000003F +#define GPIO_FUNC19_IN_SEL_M ((GPIO_FUNC19_IN_SEL_V)<<(GPIO_FUNC19_IN_SEL_S)) +#define GPIO_FUNC19_IN_SEL_V 0x3F +#define GPIO_FUNC19_IN_SEL_S 0 + +#define GPIO_FUNC20_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A4) +/* GPIO_SIG20_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG20_IN_SEL (BIT(7)) +#define GPIO_SIG20_IN_SEL_M (BIT(7)) +#define GPIO_SIG20_IN_SEL_V 0x1 +#define GPIO_SIG20_IN_SEL_S 7 +/* GPIO_FUNC20_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC20_IN_INV_SEL_V 0x1 +#define GPIO_FUNC20_IN_INV_SEL_S 6 +/* GPIO_FUNC20_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC20_IN_SEL 0x0000003F +#define GPIO_FUNC20_IN_SEL_M ((GPIO_FUNC20_IN_SEL_V)<<(GPIO_FUNC20_IN_SEL_S)) +#define GPIO_FUNC20_IN_SEL_V 0x3F +#define GPIO_FUNC20_IN_SEL_S 0 + +#define GPIO_FUNC21_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1A8) +/* GPIO_SIG21_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG21_IN_SEL (BIT(7)) +#define GPIO_SIG21_IN_SEL_M (BIT(7)) +#define GPIO_SIG21_IN_SEL_V 0x1 +#define GPIO_SIG21_IN_SEL_S 7 +/* GPIO_FUNC21_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC21_IN_INV_SEL_V 0x1 +#define GPIO_FUNC21_IN_INV_SEL_S 6 +/* GPIO_FUNC21_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC21_IN_SEL 0x0000003F +#define GPIO_FUNC21_IN_SEL_M ((GPIO_FUNC21_IN_SEL_V)<<(GPIO_FUNC21_IN_SEL_S)) +#define GPIO_FUNC21_IN_SEL_V 0x3F +#define GPIO_FUNC21_IN_SEL_S 0 + +#define GPIO_FUNC22_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1AC) +/* GPIO_SIG22_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG22_IN_SEL (BIT(7)) +#define GPIO_SIG22_IN_SEL_M (BIT(7)) +#define GPIO_SIG22_IN_SEL_V 0x1 +#define GPIO_SIG22_IN_SEL_S 7 +/* GPIO_FUNC22_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC22_IN_INV_SEL_V 0x1 +#define GPIO_FUNC22_IN_INV_SEL_S 6 +/* GPIO_FUNC22_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC22_IN_SEL 0x0000003F +#define GPIO_FUNC22_IN_SEL_M ((GPIO_FUNC22_IN_SEL_V)<<(GPIO_FUNC22_IN_SEL_S)) +#define GPIO_FUNC22_IN_SEL_V 0x3F +#define GPIO_FUNC22_IN_SEL_S 0 + +#define GPIO_FUNC23_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B0) +/* GPIO_SIG23_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG23_IN_SEL (BIT(7)) +#define GPIO_SIG23_IN_SEL_M (BIT(7)) +#define GPIO_SIG23_IN_SEL_V 0x1 +#define GPIO_SIG23_IN_SEL_S 7 +/* GPIO_FUNC23_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC23_IN_INV_SEL_V 0x1 +#define GPIO_FUNC23_IN_INV_SEL_S 6 +/* GPIO_FUNC23_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC23_IN_SEL 0x0000003F +#define GPIO_FUNC23_IN_SEL_M ((GPIO_FUNC23_IN_SEL_V)<<(GPIO_FUNC23_IN_SEL_S)) +#define GPIO_FUNC23_IN_SEL_V 0x3F +#define GPIO_FUNC23_IN_SEL_S 0 + +#define GPIO_FUNC24_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B4) +/* GPIO_SIG24_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG24_IN_SEL (BIT(7)) +#define GPIO_SIG24_IN_SEL_M (BIT(7)) +#define GPIO_SIG24_IN_SEL_V 0x1 +#define GPIO_SIG24_IN_SEL_S 7 +/* GPIO_FUNC24_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC24_IN_INV_SEL_V 0x1 +#define GPIO_FUNC24_IN_INV_SEL_S 6 +/* GPIO_FUNC24_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC24_IN_SEL 0x0000003F +#define GPIO_FUNC24_IN_SEL_M ((GPIO_FUNC24_IN_SEL_V)<<(GPIO_FUNC24_IN_SEL_S)) +#define GPIO_FUNC24_IN_SEL_V 0x3F +#define GPIO_FUNC24_IN_SEL_S 0 + +#define GPIO_FUNC25_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1B8) +/* GPIO_SIG25_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG25_IN_SEL (BIT(7)) +#define GPIO_SIG25_IN_SEL_M (BIT(7)) +#define GPIO_SIG25_IN_SEL_V 0x1 +#define GPIO_SIG25_IN_SEL_S 7 +/* GPIO_FUNC25_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC25_IN_INV_SEL_V 0x1 +#define GPIO_FUNC25_IN_INV_SEL_S 6 +/* GPIO_FUNC25_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC25_IN_SEL 0x0000003F +#define GPIO_FUNC25_IN_SEL_M ((GPIO_FUNC25_IN_SEL_V)<<(GPIO_FUNC25_IN_SEL_S)) +#define GPIO_FUNC25_IN_SEL_V 0x3F +#define GPIO_FUNC25_IN_SEL_S 0 + +#define GPIO_FUNC26_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1BC) +/* GPIO_SIG26_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG26_IN_SEL (BIT(7)) +#define GPIO_SIG26_IN_SEL_M (BIT(7)) +#define GPIO_SIG26_IN_SEL_V 0x1 +#define GPIO_SIG26_IN_SEL_S 7 +/* GPIO_FUNC26_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC26_IN_INV_SEL_V 0x1 +#define GPIO_FUNC26_IN_INV_SEL_S 6 +/* GPIO_FUNC26_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC26_IN_SEL 0x0000003F +#define GPIO_FUNC26_IN_SEL_M ((GPIO_FUNC26_IN_SEL_V)<<(GPIO_FUNC26_IN_SEL_S)) +#define GPIO_FUNC26_IN_SEL_V 0x3F +#define GPIO_FUNC26_IN_SEL_S 0 + +#define GPIO_FUNC27_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C0) +/* GPIO_SIG27_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG27_IN_SEL (BIT(7)) +#define GPIO_SIG27_IN_SEL_M (BIT(7)) +#define GPIO_SIG27_IN_SEL_V 0x1 +#define GPIO_SIG27_IN_SEL_S 7 +/* GPIO_FUNC27_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC27_IN_INV_SEL_V 0x1 +#define GPIO_FUNC27_IN_INV_SEL_S 6 +/* GPIO_FUNC27_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC27_IN_SEL 0x0000003F +#define GPIO_FUNC27_IN_SEL_M ((GPIO_FUNC27_IN_SEL_V)<<(GPIO_FUNC27_IN_SEL_S)) +#define GPIO_FUNC27_IN_SEL_V 0x3F +#define GPIO_FUNC27_IN_SEL_S 0 + +#define GPIO_FUNC28_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C4) +/* GPIO_SIG28_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG28_IN_SEL (BIT(7)) +#define GPIO_SIG28_IN_SEL_M (BIT(7)) +#define GPIO_SIG28_IN_SEL_V 0x1 +#define GPIO_SIG28_IN_SEL_S 7 +/* GPIO_FUNC28_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC28_IN_INV_SEL_V 0x1 +#define GPIO_FUNC28_IN_INV_SEL_S 6 +/* GPIO_FUNC28_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC28_IN_SEL 0x0000003F +#define GPIO_FUNC28_IN_SEL_M ((GPIO_FUNC28_IN_SEL_V)<<(GPIO_FUNC28_IN_SEL_S)) +#define GPIO_FUNC28_IN_SEL_V 0x3F +#define GPIO_FUNC28_IN_SEL_S 0 + +#define GPIO_FUNC29_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1C8) +/* GPIO_SIG29_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG29_IN_SEL (BIT(7)) +#define GPIO_SIG29_IN_SEL_M (BIT(7)) +#define GPIO_SIG29_IN_SEL_V 0x1 +#define GPIO_SIG29_IN_SEL_S 7 +/* GPIO_FUNC29_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC29_IN_INV_SEL_V 0x1 +#define GPIO_FUNC29_IN_INV_SEL_S 6 +/* GPIO_FUNC29_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC29_IN_SEL 0x0000003F +#define GPIO_FUNC29_IN_SEL_M ((GPIO_FUNC29_IN_SEL_V)<<(GPIO_FUNC29_IN_SEL_S)) +#define GPIO_FUNC29_IN_SEL_V 0x3F +#define GPIO_FUNC29_IN_SEL_S 0 + +#define GPIO_FUNC30_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1CC) +/* GPIO_SIG30_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG30_IN_SEL (BIT(7)) +#define GPIO_SIG30_IN_SEL_M (BIT(7)) +#define GPIO_SIG30_IN_SEL_V 0x1 +#define GPIO_SIG30_IN_SEL_S 7 +/* GPIO_FUNC30_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC30_IN_INV_SEL_V 0x1 +#define GPIO_FUNC30_IN_INV_SEL_S 6 +/* GPIO_FUNC30_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC30_IN_SEL 0x0000003F +#define GPIO_FUNC30_IN_SEL_M ((GPIO_FUNC30_IN_SEL_V)<<(GPIO_FUNC30_IN_SEL_S)) +#define GPIO_FUNC30_IN_SEL_V 0x3F +#define GPIO_FUNC30_IN_SEL_S 0 + +#define GPIO_FUNC31_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D0) +/* GPIO_SIG31_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG31_IN_SEL (BIT(7)) +#define GPIO_SIG31_IN_SEL_M (BIT(7)) +#define GPIO_SIG31_IN_SEL_V 0x1 +#define GPIO_SIG31_IN_SEL_S 7 +/* GPIO_FUNC31_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC31_IN_INV_SEL_V 0x1 +#define GPIO_FUNC31_IN_INV_SEL_S 6 +/* GPIO_FUNC31_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC31_IN_SEL 0x0000003F +#define GPIO_FUNC31_IN_SEL_M ((GPIO_FUNC31_IN_SEL_V)<<(GPIO_FUNC31_IN_SEL_S)) +#define GPIO_FUNC31_IN_SEL_V 0x3F +#define GPIO_FUNC31_IN_SEL_S 0 + +#define GPIO_FUNC32_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D4) +/* GPIO_SIG32_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG32_IN_SEL (BIT(7)) +#define GPIO_SIG32_IN_SEL_M (BIT(7)) +#define GPIO_SIG32_IN_SEL_V 0x1 +#define GPIO_SIG32_IN_SEL_S 7 +/* GPIO_FUNC32_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC32_IN_INV_SEL_V 0x1 +#define GPIO_FUNC32_IN_INV_SEL_S 6 +/* GPIO_FUNC32_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC32_IN_SEL 0x0000003F +#define GPIO_FUNC32_IN_SEL_M ((GPIO_FUNC32_IN_SEL_V)<<(GPIO_FUNC32_IN_SEL_S)) +#define GPIO_FUNC32_IN_SEL_V 0x3F +#define GPIO_FUNC32_IN_SEL_S 0 + +#define GPIO_FUNC33_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1D8) +/* GPIO_SIG33_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG33_IN_SEL (BIT(7)) +#define GPIO_SIG33_IN_SEL_M (BIT(7)) +#define GPIO_SIG33_IN_SEL_V 0x1 +#define GPIO_SIG33_IN_SEL_S 7 +/* GPIO_FUNC33_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC33_IN_INV_SEL_V 0x1 +#define GPIO_FUNC33_IN_INV_SEL_S 6 +/* GPIO_FUNC33_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC33_IN_SEL 0x0000003F +#define GPIO_FUNC33_IN_SEL_M ((GPIO_FUNC33_IN_SEL_V)<<(GPIO_FUNC33_IN_SEL_S)) +#define GPIO_FUNC33_IN_SEL_V 0x3F +#define GPIO_FUNC33_IN_SEL_S 0 + +#define GPIO_FUNC34_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1DC) +/* GPIO_SIG34_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG34_IN_SEL (BIT(7)) +#define GPIO_SIG34_IN_SEL_M (BIT(7)) +#define GPIO_SIG34_IN_SEL_V 0x1 +#define GPIO_SIG34_IN_SEL_S 7 +/* GPIO_FUNC34_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC34_IN_INV_SEL_V 0x1 +#define GPIO_FUNC34_IN_INV_SEL_S 6 +/* GPIO_FUNC34_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC34_IN_SEL 0x0000003F +#define GPIO_FUNC34_IN_SEL_M ((GPIO_FUNC34_IN_SEL_V)<<(GPIO_FUNC34_IN_SEL_S)) +#define GPIO_FUNC34_IN_SEL_V 0x3F +#define GPIO_FUNC34_IN_SEL_S 0 + +#define GPIO_FUNC35_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E0) +/* GPIO_SIG35_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG35_IN_SEL (BIT(7)) +#define GPIO_SIG35_IN_SEL_M (BIT(7)) +#define GPIO_SIG35_IN_SEL_V 0x1 +#define GPIO_SIG35_IN_SEL_S 7 +/* GPIO_FUNC35_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC35_IN_INV_SEL_V 0x1 +#define GPIO_FUNC35_IN_INV_SEL_S 6 +/* GPIO_FUNC35_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC35_IN_SEL 0x0000003F +#define GPIO_FUNC35_IN_SEL_M ((GPIO_FUNC35_IN_SEL_V)<<(GPIO_FUNC35_IN_SEL_S)) +#define GPIO_FUNC35_IN_SEL_V 0x3F +#define GPIO_FUNC35_IN_SEL_S 0 + +#define GPIO_FUNC36_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E4) +/* GPIO_SIG36_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG36_IN_SEL (BIT(7)) +#define GPIO_SIG36_IN_SEL_M (BIT(7)) +#define GPIO_SIG36_IN_SEL_V 0x1 +#define GPIO_SIG36_IN_SEL_S 7 +/* GPIO_FUNC36_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC36_IN_INV_SEL_V 0x1 +#define GPIO_FUNC36_IN_INV_SEL_S 6 +/* GPIO_FUNC36_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC36_IN_SEL 0x0000003F +#define GPIO_FUNC36_IN_SEL_M ((GPIO_FUNC36_IN_SEL_V)<<(GPIO_FUNC36_IN_SEL_S)) +#define GPIO_FUNC36_IN_SEL_V 0x3F +#define GPIO_FUNC36_IN_SEL_S 0 + +#define GPIO_FUNC37_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1E8) +/* GPIO_SIG37_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG37_IN_SEL (BIT(7)) +#define GPIO_SIG37_IN_SEL_M (BIT(7)) +#define GPIO_SIG37_IN_SEL_V 0x1 +#define GPIO_SIG37_IN_SEL_S 7 +/* GPIO_FUNC37_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC37_IN_INV_SEL_V 0x1 +#define GPIO_FUNC37_IN_INV_SEL_S 6 +/* GPIO_FUNC37_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC37_IN_SEL 0x0000003F +#define GPIO_FUNC37_IN_SEL_M ((GPIO_FUNC37_IN_SEL_V)<<(GPIO_FUNC37_IN_SEL_S)) +#define GPIO_FUNC37_IN_SEL_V 0x3F +#define GPIO_FUNC37_IN_SEL_S 0 + +#define GPIO_FUNC38_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1EC) +/* GPIO_SIG38_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG38_IN_SEL (BIT(7)) +#define GPIO_SIG38_IN_SEL_M (BIT(7)) +#define GPIO_SIG38_IN_SEL_V 0x1 +#define GPIO_SIG38_IN_SEL_S 7 +/* GPIO_FUNC38_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC38_IN_INV_SEL_V 0x1 +#define GPIO_FUNC38_IN_INV_SEL_S 6 +/* GPIO_FUNC38_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC38_IN_SEL 0x0000003F +#define GPIO_FUNC38_IN_SEL_M ((GPIO_FUNC38_IN_SEL_V)<<(GPIO_FUNC38_IN_SEL_S)) +#define GPIO_FUNC38_IN_SEL_V 0x3F +#define GPIO_FUNC38_IN_SEL_S 0 + +#define GPIO_FUNC39_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F0) +/* GPIO_SIG39_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG39_IN_SEL (BIT(7)) +#define GPIO_SIG39_IN_SEL_M (BIT(7)) +#define GPIO_SIG39_IN_SEL_V 0x1 +#define GPIO_SIG39_IN_SEL_S 7 +/* GPIO_FUNC39_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC39_IN_INV_SEL_V 0x1 +#define GPIO_FUNC39_IN_INV_SEL_S 6 +/* GPIO_FUNC39_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC39_IN_SEL 0x0000003F +#define GPIO_FUNC39_IN_SEL_M ((GPIO_FUNC39_IN_SEL_V)<<(GPIO_FUNC39_IN_SEL_S)) +#define GPIO_FUNC39_IN_SEL_V 0x3F +#define GPIO_FUNC39_IN_SEL_S 0 + +#define GPIO_FUNC40_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F4) +/* GPIO_SIG40_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG40_IN_SEL (BIT(7)) +#define GPIO_SIG40_IN_SEL_M (BIT(7)) +#define GPIO_SIG40_IN_SEL_V 0x1 +#define GPIO_SIG40_IN_SEL_S 7 +/* GPIO_FUNC40_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC40_IN_INV_SEL_V 0x1 +#define GPIO_FUNC40_IN_INV_SEL_S 6 +/* GPIO_FUNC40_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC40_IN_SEL 0x0000003F +#define GPIO_FUNC40_IN_SEL_M ((GPIO_FUNC40_IN_SEL_V)<<(GPIO_FUNC40_IN_SEL_S)) +#define GPIO_FUNC40_IN_SEL_V 0x3F +#define GPIO_FUNC40_IN_SEL_S 0 + +#define GPIO_FUNC41_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1F8) +/* GPIO_SIG41_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG41_IN_SEL (BIT(7)) +#define GPIO_SIG41_IN_SEL_M (BIT(7)) +#define GPIO_SIG41_IN_SEL_V 0x1 +#define GPIO_SIG41_IN_SEL_S 7 +/* GPIO_FUNC41_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC41_IN_INV_SEL_V 0x1 +#define GPIO_FUNC41_IN_INV_SEL_S 6 +/* GPIO_FUNC41_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC41_IN_SEL 0x0000003F +#define GPIO_FUNC41_IN_SEL_M ((GPIO_FUNC41_IN_SEL_V)<<(GPIO_FUNC41_IN_SEL_S)) +#define GPIO_FUNC41_IN_SEL_V 0x3F +#define GPIO_FUNC41_IN_SEL_S 0 + +#define GPIO_FUNC42_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x1FC) +/* GPIO_SIG42_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG42_IN_SEL (BIT(7)) +#define GPIO_SIG42_IN_SEL_M (BIT(7)) +#define GPIO_SIG42_IN_SEL_V 0x1 +#define GPIO_SIG42_IN_SEL_S 7 +/* GPIO_FUNC42_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC42_IN_INV_SEL_V 0x1 +#define GPIO_FUNC42_IN_INV_SEL_S 6 +/* GPIO_FUNC42_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC42_IN_SEL 0x0000003F +#define GPIO_FUNC42_IN_SEL_M ((GPIO_FUNC42_IN_SEL_V)<<(GPIO_FUNC42_IN_SEL_S)) +#define GPIO_FUNC42_IN_SEL_V 0x3F +#define GPIO_FUNC42_IN_SEL_S 0 + +#define GPIO_FUNC43_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x200) +/* GPIO_SIG43_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG43_IN_SEL (BIT(7)) +#define GPIO_SIG43_IN_SEL_M (BIT(7)) +#define GPIO_SIG43_IN_SEL_V 0x1 +#define GPIO_SIG43_IN_SEL_S 7 +/* GPIO_FUNC43_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC43_IN_INV_SEL_V 0x1 +#define GPIO_FUNC43_IN_INV_SEL_S 6 +/* GPIO_FUNC43_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC43_IN_SEL 0x0000003F +#define GPIO_FUNC43_IN_SEL_M ((GPIO_FUNC43_IN_SEL_V)<<(GPIO_FUNC43_IN_SEL_S)) +#define GPIO_FUNC43_IN_SEL_V 0x3F +#define GPIO_FUNC43_IN_SEL_S 0 + +#define GPIO_FUNC44_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x204) +/* GPIO_SIG44_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG44_IN_SEL (BIT(7)) +#define GPIO_SIG44_IN_SEL_M (BIT(7)) +#define GPIO_SIG44_IN_SEL_V 0x1 +#define GPIO_SIG44_IN_SEL_S 7 +/* GPIO_FUNC44_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC44_IN_INV_SEL_V 0x1 +#define GPIO_FUNC44_IN_INV_SEL_S 6 +/* GPIO_FUNC44_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC44_IN_SEL 0x0000003F +#define GPIO_FUNC44_IN_SEL_M ((GPIO_FUNC44_IN_SEL_V)<<(GPIO_FUNC44_IN_SEL_S)) +#define GPIO_FUNC44_IN_SEL_V 0x3F +#define GPIO_FUNC44_IN_SEL_S 0 + +#define GPIO_FUNC45_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x208) +/* GPIO_SIG45_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG45_IN_SEL (BIT(7)) +#define GPIO_SIG45_IN_SEL_M (BIT(7)) +#define GPIO_SIG45_IN_SEL_V 0x1 +#define GPIO_SIG45_IN_SEL_S 7 +/* GPIO_FUNC45_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC45_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC45_IN_INV_SEL_V 0x1 +#define GPIO_FUNC45_IN_INV_SEL_S 6 +/* GPIO_FUNC45_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC45_IN_SEL 0x0000003F +#define GPIO_FUNC45_IN_SEL_M ((GPIO_FUNC45_IN_SEL_V)<<(GPIO_FUNC45_IN_SEL_S)) +#define GPIO_FUNC45_IN_SEL_V 0x3F +#define GPIO_FUNC45_IN_SEL_S 0 + +#define GPIO_FUNC46_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x20C) +/* GPIO_SIG46_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG46_IN_SEL (BIT(7)) +#define GPIO_SIG46_IN_SEL_M (BIT(7)) +#define GPIO_SIG46_IN_SEL_V 0x1 +#define GPIO_SIG46_IN_SEL_S 7 +/* GPIO_FUNC46_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC46_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC46_IN_INV_SEL_V 0x1 +#define GPIO_FUNC46_IN_INV_SEL_S 6 +/* GPIO_FUNC46_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC46_IN_SEL 0x0000003F +#define GPIO_FUNC46_IN_SEL_M ((GPIO_FUNC46_IN_SEL_V)<<(GPIO_FUNC46_IN_SEL_S)) +#define GPIO_FUNC46_IN_SEL_V 0x3F +#define GPIO_FUNC46_IN_SEL_S 0 + +#define GPIO_FUNC47_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x210) +/* GPIO_SIG47_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG47_IN_SEL (BIT(7)) +#define GPIO_SIG47_IN_SEL_M (BIT(7)) +#define GPIO_SIG47_IN_SEL_V 0x1 +#define GPIO_SIG47_IN_SEL_S 7 +/* GPIO_FUNC47_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC47_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC47_IN_INV_SEL_V 0x1 +#define GPIO_FUNC47_IN_INV_SEL_S 6 +/* GPIO_FUNC47_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC47_IN_SEL 0x0000003F +#define GPIO_FUNC47_IN_SEL_M ((GPIO_FUNC47_IN_SEL_V)<<(GPIO_FUNC47_IN_SEL_S)) +#define GPIO_FUNC47_IN_SEL_V 0x3F +#define GPIO_FUNC47_IN_SEL_S 0 + +#define GPIO_FUNC48_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x214) +/* GPIO_SIG48_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG48_IN_SEL (BIT(7)) +#define GPIO_SIG48_IN_SEL_M (BIT(7)) +#define GPIO_SIG48_IN_SEL_V 0x1 +#define GPIO_SIG48_IN_SEL_S 7 +/* GPIO_FUNC48_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC48_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC48_IN_INV_SEL_V 0x1 +#define GPIO_FUNC48_IN_INV_SEL_S 6 +/* GPIO_FUNC48_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC48_IN_SEL 0x0000003F +#define GPIO_FUNC48_IN_SEL_M ((GPIO_FUNC48_IN_SEL_V)<<(GPIO_FUNC48_IN_SEL_S)) +#define GPIO_FUNC48_IN_SEL_V 0x3F +#define GPIO_FUNC48_IN_SEL_S 0 + +#define GPIO_FUNC49_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x218) +/* GPIO_SIG49_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG49_IN_SEL (BIT(7)) +#define GPIO_SIG49_IN_SEL_M (BIT(7)) +#define GPIO_SIG49_IN_SEL_V 0x1 +#define GPIO_SIG49_IN_SEL_S 7 +/* GPIO_FUNC49_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC49_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC49_IN_INV_SEL_V 0x1 +#define GPIO_FUNC49_IN_INV_SEL_S 6 +/* GPIO_FUNC49_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC49_IN_SEL 0x0000003F +#define GPIO_FUNC49_IN_SEL_M ((GPIO_FUNC49_IN_SEL_V)<<(GPIO_FUNC49_IN_SEL_S)) +#define GPIO_FUNC49_IN_SEL_V 0x3F +#define GPIO_FUNC49_IN_SEL_S 0 + +#define GPIO_FUNC50_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x21C) +/* GPIO_SIG50_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG50_IN_SEL (BIT(7)) +#define GPIO_SIG50_IN_SEL_M (BIT(7)) +#define GPIO_SIG50_IN_SEL_V 0x1 +#define GPIO_SIG50_IN_SEL_S 7 +/* GPIO_FUNC50_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC50_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC50_IN_INV_SEL_V 0x1 +#define GPIO_FUNC50_IN_INV_SEL_S 6 +/* GPIO_FUNC50_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC50_IN_SEL 0x0000003F +#define GPIO_FUNC50_IN_SEL_M ((GPIO_FUNC50_IN_SEL_V)<<(GPIO_FUNC50_IN_SEL_S)) +#define GPIO_FUNC50_IN_SEL_V 0x3F +#define GPIO_FUNC50_IN_SEL_S 0 + +#define GPIO_FUNC51_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x220) +/* GPIO_SIG51_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG51_IN_SEL (BIT(7)) +#define GPIO_SIG51_IN_SEL_M (BIT(7)) +#define GPIO_SIG51_IN_SEL_V 0x1 +#define GPIO_SIG51_IN_SEL_S 7 +/* GPIO_FUNC51_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC51_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC51_IN_INV_SEL_V 0x1 +#define GPIO_FUNC51_IN_INV_SEL_S 6 +/* GPIO_FUNC51_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC51_IN_SEL 0x0000003F +#define GPIO_FUNC51_IN_SEL_M ((GPIO_FUNC51_IN_SEL_V)<<(GPIO_FUNC51_IN_SEL_S)) +#define GPIO_FUNC51_IN_SEL_V 0x3F +#define GPIO_FUNC51_IN_SEL_S 0 + +#define GPIO_FUNC52_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x224) +/* GPIO_SIG52_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG52_IN_SEL (BIT(7)) +#define GPIO_SIG52_IN_SEL_M (BIT(7)) +#define GPIO_SIG52_IN_SEL_V 0x1 +#define GPIO_SIG52_IN_SEL_S 7 +/* GPIO_FUNC52_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC52_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC52_IN_INV_SEL_V 0x1 +#define GPIO_FUNC52_IN_INV_SEL_S 6 +/* GPIO_FUNC52_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC52_IN_SEL 0x0000003F +#define GPIO_FUNC52_IN_SEL_M ((GPIO_FUNC52_IN_SEL_V)<<(GPIO_FUNC52_IN_SEL_S)) +#define GPIO_FUNC52_IN_SEL_V 0x3F +#define GPIO_FUNC52_IN_SEL_S 0 + +#define GPIO_FUNC53_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x228) +/* GPIO_SIG53_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG53_IN_SEL (BIT(7)) +#define GPIO_SIG53_IN_SEL_M (BIT(7)) +#define GPIO_SIG53_IN_SEL_V 0x1 +#define GPIO_SIG53_IN_SEL_S 7 +/* GPIO_FUNC53_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC53_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC53_IN_INV_SEL_V 0x1 +#define GPIO_FUNC53_IN_INV_SEL_S 6 +/* GPIO_FUNC53_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC53_IN_SEL 0x0000003F +#define GPIO_FUNC53_IN_SEL_M ((GPIO_FUNC53_IN_SEL_V)<<(GPIO_FUNC53_IN_SEL_S)) +#define GPIO_FUNC53_IN_SEL_V 0x3F +#define GPIO_FUNC53_IN_SEL_S 0 + +#define GPIO_FUNC54_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x22C) +/* GPIO_SIG54_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG54_IN_SEL (BIT(7)) +#define GPIO_SIG54_IN_SEL_M (BIT(7)) +#define GPIO_SIG54_IN_SEL_V 0x1 +#define GPIO_SIG54_IN_SEL_S 7 +/* GPIO_FUNC54_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC54_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC54_IN_INV_SEL_V 0x1 +#define GPIO_FUNC54_IN_INV_SEL_S 6 +/* GPIO_FUNC54_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC54_IN_SEL 0x0000003F +#define GPIO_FUNC54_IN_SEL_M ((GPIO_FUNC54_IN_SEL_V)<<(GPIO_FUNC54_IN_SEL_S)) +#define GPIO_FUNC54_IN_SEL_V 0x3F +#define GPIO_FUNC54_IN_SEL_S 0 + +#define GPIO_FUNC55_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x230) +/* GPIO_SIG55_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG55_IN_SEL (BIT(7)) +#define GPIO_SIG55_IN_SEL_M (BIT(7)) +#define GPIO_SIG55_IN_SEL_V 0x1 +#define GPIO_SIG55_IN_SEL_S 7 +/* GPIO_FUNC55_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC55_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC55_IN_INV_SEL_V 0x1 +#define GPIO_FUNC55_IN_INV_SEL_S 6 +/* GPIO_FUNC55_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC55_IN_SEL 0x0000003F +#define GPIO_FUNC55_IN_SEL_M ((GPIO_FUNC55_IN_SEL_V)<<(GPIO_FUNC55_IN_SEL_S)) +#define GPIO_FUNC55_IN_SEL_V 0x3F +#define GPIO_FUNC55_IN_SEL_S 0 + +#define GPIO_FUNC56_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x234) +/* GPIO_SIG56_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG56_IN_SEL (BIT(7)) +#define GPIO_SIG56_IN_SEL_M (BIT(7)) +#define GPIO_SIG56_IN_SEL_V 0x1 +#define GPIO_SIG56_IN_SEL_S 7 +/* GPIO_FUNC56_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC56_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC56_IN_INV_SEL_V 0x1 +#define GPIO_FUNC56_IN_INV_SEL_S 6 +/* GPIO_FUNC56_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC56_IN_SEL 0x0000003F +#define GPIO_FUNC56_IN_SEL_M ((GPIO_FUNC56_IN_SEL_V)<<(GPIO_FUNC56_IN_SEL_S)) +#define GPIO_FUNC56_IN_SEL_V 0x3F +#define GPIO_FUNC56_IN_SEL_S 0 + +#define GPIO_FUNC57_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x238) +/* GPIO_SIG57_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG57_IN_SEL (BIT(7)) +#define GPIO_SIG57_IN_SEL_M (BIT(7)) +#define GPIO_SIG57_IN_SEL_V 0x1 +#define GPIO_SIG57_IN_SEL_S 7 +/* GPIO_FUNC57_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC57_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC57_IN_INV_SEL_V 0x1 +#define GPIO_FUNC57_IN_INV_SEL_S 6 +/* GPIO_FUNC57_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC57_IN_SEL 0x0000003F +#define GPIO_FUNC57_IN_SEL_M ((GPIO_FUNC57_IN_SEL_V)<<(GPIO_FUNC57_IN_SEL_S)) +#define GPIO_FUNC57_IN_SEL_V 0x3F +#define GPIO_FUNC57_IN_SEL_S 0 + +#define GPIO_FUNC58_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x23C) +/* GPIO_SIG58_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG58_IN_SEL (BIT(7)) +#define GPIO_SIG58_IN_SEL_M (BIT(7)) +#define GPIO_SIG58_IN_SEL_V 0x1 +#define GPIO_SIG58_IN_SEL_S 7 +/* GPIO_FUNC58_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC58_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC58_IN_INV_SEL_V 0x1 +#define GPIO_FUNC58_IN_INV_SEL_S 6 +/* GPIO_FUNC58_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC58_IN_SEL 0x0000003F +#define GPIO_FUNC58_IN_SEL_M ((GPIO_FUNC58_IN_SEL_V)<<(GPIO_FUNC58_IN_SEL_S)) +#define GPIO_FUNC58_IN_SEL_V 0x3F +#define GPIO_FUNC58_IN_SEL_S 0 + +#define GPIO_FUNC59_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x240) +/* GPIO_SIG59_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG59_IN_SEL (BIT(7)) +#define GPIO_SIG59_IN_SEL_M (BIT(7)) +#define GPIO_SIG59_IN_SEL_V 0x1 +#define GPIO_SIG59_IN_SEL_S 7 +/* GPIO_FUNC59_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC59_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC59_IN_INV_SEL_V 0x1 +#define GPIO_FUNC59_IN_INV_SEL_S 6 +/* GPIO_FUNC59_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC59_IN_SEL 0x0000003F +#define GPIO_FUNC59_IN_SEL_M ((GPIO_FUNC59_IN_SEL_V)<<(GPIO_FUNC59_IN_SEL_S)) +#define GPIO_FUNC59_IN_SEL_V 0x3F +#define GPIO_FUNC59_IN_SEL_S 0 + +#define GPIO_FUNC60_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x244) +/* GPIO_SIG60_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG60_IN_SEL (BIT(7)) +#define GPIO_SIG60_IN_SEL_M (BIT(7)) +#define GPIO_SIG60_IN_SEL_V 0x1 +#define GPIO_SIG60_IN_SEL_S 7 +/* GPIO_FUNC60_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC60_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC60_IN_INV_SEL_V 0x1 +#define GPIO_FUNC60_IN_INV_SEL_S 6 +/* GPIO_FUNC60_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC60_IN_SEL 0x0000003F +#define GPIO_FUNC60_IN_SEL_M ((GPIO_FUNC60_IN_SEL_V)<<(GPIO_FUNC60_IN_SEL_S)) +#define GPIO_FUNC60_IN_SEL_V 0x3F +#define GPIO_FUNC60_IN_SEL_S 0 + +#define GPIO_FUNC61_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x248) +/* GPIO_SIG61_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG61_IN_SEL (BIT(7)) +#define GPIO_SIG61_IN_SEL_M (BIT(7)) +#define GPIO_SIG61_IN_SEL_V 0x1 +#define GPIO_SIG61_IN_SEL_S 7 +/* GPIO_FUNC61_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC61_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC61_IN_INV_SEL_V 0x1 +#define GPIO_FUNC61_IN_INV_SEL_S 6 +/* GPIO_FUNC61_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC61_IN_SEL 0x0000003F +#define GPIO_FUNC61_IN_SEL_M ((GPIO_FUNC61_IN_SEL_V)<<(GPIO_FUNC61_IN_SEL_S)) +#define GPIO_FUNC61_IN_SEL_V 0x3F +#define GPIO_FUNC61_IN_SEL_S 0 + +#define GPIO_FUNC62_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x24C) +/* GPIO_SIG62_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG62_IN_SEL (BIT(7)) +#define GPIO_SIG62_IN_SEL_M (BIT(7)) +#define GPIO_SIG62_IN_SEL_V 0x1 +#define GPIO_SIG62_IN_SEL_S 7 +/* GPIO_FUNC62_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC62_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC62_IN_INV_SEL_V 0x1 +#define GPIO_FUNC62_IN_INV_SEL_S 6 +/* GPIO_FUNC62_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC62_IN_SEL 0x0000003F +#define GPIO_FUNC62_IN_SEL_M ((GPIO_FUNC62_IN_SEL_V)<<(GPIO_FUNC62_IN_SEL_S)) +#define GPIO_FUNC62_IN_SEL_V 0x3F +#define GPIO_FUNC62_IN_SEL_S 0 + +#define GPIO_FUNC63_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x250) +/* GPIO_SIG63_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG63_IN_SEL (BIT(7)) +#define GPIO_SIG63_IN_SEL_M (BIT(7)) +#define GPIO_SIG63_IN_SEL_V 0x1 +#define GPIO_SIG63_IN_SEL_S 7 +/* GPIO_FUNC63_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC63_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC63_IN_INV_SEL_V 0x1 +#define GPIO_FUNC63_IN_INV_SEL_S 6 +/* GPIO_FUNC63_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC63_IN_SEL 0x0000003F +#define GPIO_FUNC63_IN_SEL_M ((GPIO_FUNC63_IN_SEL_V)<<(GPIO_FUNC63_IN_SEL_S)) +#define GPIO_FUNC63_IN_SEL_V 0x3F +#define GPIO_FUNC63_IN_SEL_S 0 + +#define GPIO_FUNC64_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x254) +/* GPIO_SIG64_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG64_IN_SEL (BIT(7)) +#define GPIO_SIG64_IN_SEL_M (BIT(7)) +#define GPIO_SIG64_IN_SEL_V 0x1 +#define GPIO_SIG64_IN_SEL_S 7 +/* GPIO_FUNC64_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC64_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC64_IN_INV_SEL_V 0x1 +#define GPIO_FUNC64_IN_INV_SEL_S 6 +/* GPIO_FUNC64_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC64_IN_SEL 0x0000003F +#define GPIO_FUNC64_IN_SEL_M ((GPIO_FUNC64_IN_SEL_V)<<(GPIO_FUNC64_IN_SEL_S)) +#define GPIO_FUNC64_IN_SEL_V 0x3F +#define GPIO_FUNC64_IN_SEL_S 0 + +#define GPIO_FUNC65_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x258) +/* GPIO_SIG65_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG65_IN_SEL (BIT(7)) +#define GPIO_SIG65_IN_SEL_M (BIT(7)) +#define GPIO_SIG65_IN_SEL_V 0x1 +#define GPIO_SIG65_IN_SEL_S 7 +/* GPIO_FUNC65_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC65_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC65_IN_INV_SEL_V 0x1 +#define GPIO_FUNC65_IN_INV_SEL_S 6 +/* GPIO_FUNC65_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC65_IN_SEL 0x0000003F +#define GPIO_FUNC65_IN_SEL_M ((GPIO_FUNC65_IN_SEL_V)<<(GPIO_FUNC65_IN_SEL_S)) +#define GPIO_FUNC65_IN_SEL_V 0x3F +#define GPIO_FUNC65_IN_SEL_S 0 + +#define GPIO_FUNC66_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x25C) +/* GPIO_SIG66_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG66_IN_SEL (BIT(7)) +#define GPIO_SIG66_IN_SEL_M (BIT(7)) +#define GPIO_SIG66_IN_SEL_V 0x1 +#define GPIO_SIG66_IN_SEL_S 7 +/* GPIO_FUNC66_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC66_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC66_IN_INV_SEL_V 0x1 +#define GPIO_FUNC66_IN_INV_SEL_S 6 +/* GPIO_FUNC66_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC66_IN_SEL 0x0000003F +#define GPIO_FUNC66_IN_SEL_M ((GPIO_FUNC66_IN_SEL_V)<<(GPIO_FUNC66_IN_SEL_S)) +#define GPIO_FUNC66_IN_SEL_V 0x3F +#define GPIO_FUNC66_IN_SEL_S 0 + +#define GPIO_FUNC67_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x260) +/* GPIO_SIG67_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG67_IN_SEL (BIT(7)) +#define GPIO_SIG67_IN_SEL_M (BIT(7)) +#define GPIO_SIG67_IN_SEL_V 0x1 +#define GPIO_SIG67_IN_SEL_S 7 +/* GPIO_FUNC67_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC67_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC67_IN_INV_SEL_V 0x1 +#define GPIO_FUNC67_IN_INV_SEL_S 6 +/* GPIO_FUNC67_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC67_IN_SEL 0x0000003F +#define GPIO_FUNC67_IN_SEL_M ((GPIO_FUNC67_IN_SEL_V)<<(GPIO_FUNC67_IN_SEL_S)) +#define GPIO_FUNC67_IN_SEL_V 0x3F +#define GPIO_FUNC67_IN_SEL_S 0 + +#define GPIO_FUNC68_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x264) +/* GPIO_SIG68_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG68_IN_SEL (BIT(7)) +#define GPIO_SIG68_IN_SEL_M (BIT(7)) +#define GPIO_SIG68_IN_SEL_V 0x1 +#define GPIO_SIG68_IN_SEL_S 7 +/* GPIO_FUNC68_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC68_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC68_IN_INV_SEL_V 0x1 +#define GPIO_FUNC68_IN_INV_SEL_S 6 +/* GPIO_FUNC68_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC68_IN_SEL 0x0000003F +#define GPIO_FUNC68_IN_SEL_M ((GPIO_FUNC68_IN_SEL_V)<<(GPIO_FUNC68_IN_SEL_S)) +#define GPIO_FUNC68_IN_SEL_V 0x3F +#define GPIO_FUNC68_IN_SEL_S 0 + +#define GPIO_FUNC69_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x268) +/* GPIO_SIG69_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG69_IN_SEL (BIT(7)) +#define GPIO_SIG69_IN_SEL_M (BIT(7)) +#define GPIO_SIG69_IN_SEL_V 0x1 +#define GPIO_SIG69_IN_SEL_S 7 +/* GPIO_FUNC69_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC69_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC69_IN_INV_SEL_V 0x1 +#define GPIO_FUNC69_IN_INV_SEL_S 6 +/* GPIO_FUNC69_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC69_IN_SEL 0x0000003F +#define GPIO_FUNC69_IN_SEL_M ((GPIO_FUNC69_IN_SEL_V)<<(GPIO_FUNC69_IN_SEL_S)) +#define GPIO_FUNC69_IN_SEL_V 0x3F +#define GPIO_FUNC69_IN_SEL_S 0 + +#define GPIO_FUNC70_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x26C) +/* GPIO_SIG70_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG70_IN_SEL (BIT(7)) +#define GPIO_SIG70_IN_SEL_M (BIT(7)) +#define GPIO_SIG70_IN_SEL_V 0x1 +#define GPIO_SIG70_IN_SEL_S 7 +/* GPIO_FUNC70_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC70_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC70_IN_INV_SEL_V 0x1 +#define GPIO_FUNC70_IN_INV_SEL_S 6 +/* GPIO_FUNC70_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC70_IN_SEL 0x0000003F +#define GPIO_FUNC70_IN_SEL_M ((GPIO_FUNC70_IN_SEL_V)<<(GPIO_FUNC70_IN_SEL_S)) +#define GPIO_FUNC70_IN_SEL_V 0x3F +#define GPIO_FUNC70_IN_SEL_S 0 + +#define GPIO_FUNC71_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x270) +/* GPIO_SIG71_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG71_IN_SEL (BIT(7)) +#define GPIO_SIG71_IN_SEL_M (BIT(7)) +#define GPIO_SIG71_IN_SEL_V 0x1 +#define GPIO_SIG71_IN_SEL_S 7 +/* GPIO_FUNC71_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC71_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC71_IN_INV_SEL_V 0x1 +#define GPIO_FUNC71_IN_INV_SEL_S 6 +/* GPIO_FUNC71_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC71_IN_SEL 0x0000003F +#define GPIO_FUNC71_IN_SEL_M ((GPIO_FUNC71_IN_SEL_V)<<(GPIO_FUNC71_IN_SEL_S)) +#define GPIO_FUNC71_IN_SEL_V 0x3F +#define GPIO_FUNC71_IN_SEL_S 0 + +#define GPIO_FUNC72_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x274) +/* GPIO_SIG72_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG72_IN_SEL (BIT(7)) +#define GPIO_SIG72_IN_SEL_M (BIT(7)) +#define GPIO_SIG72_IN_SEL_V 0x1 +#define GPIO_SIG72_IN_SEL_S 7 +/* GPIO_FUNC72_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC72_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC72_IN_INV_SEL_V 0x1 +#define GPIO_FUNC72_IN_INV_SEL_S 6 +/* GPIO_FUNC72_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC72_IN_SEL 0x0000003F +#define GPIO_FUNC72_IN_SEL_M ((GPIO_FUNC72_IN_SEL_V)<<(GPIO_FUNC72_IN_SEL_S)) +#define GPIO_FUNC72_IN_SEL_V 0x3F +#define GPIO_FUNC72_IN_SEL_S 0 + +#define GPIO_FUNC73_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x278) +/* GPIO_SIG73_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG73_IN_SEL (BIT(7)) +#define GPIO_SIG73_IN_SEL_M (BIT(7)) +#define GPIO_SIG73_IN_SEL_V 0x1 +#define GPIO_SIG73_IN_SEL_S 7 +/* GPIO_FUNC73_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC73_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC73_IN_INV_SEL_V 0x1 +#define GPIO_FUNC73_IN_INV_SEL_S 6 +/* GPIO_FUNC73_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC73_IN_SEL 0x0000003F +#define GPIO_FUNC73_IN_SEL_M ((GPIO_FUNC73_IN_SEL_V)<<(GPIO_FUNC73_IN_SEL_S)) +#define GPIO_FUNC73_IN_SEL_V 0x3F +#define GPIO_FUNC73_IN_SEL_S 0 + +#define GPIO_FUNC74_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x27C) +/* GPIO_SIG74_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG74_IN_SEL (BIT(7)) +#define GPIO_SIG74_IN_SEL_M (BIT(7)) +#define GPIO_SIG74_IN_SEL_V 0x1 +#define GPIO_SIG74_IN_SEL_S 7 +/* GPIO_FUNC74_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC74_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC74_IN_INV_SEL_V 0x1 +#define GPIO_FUNC74_IN_INV_SEL_S 6 +/* GPIO_FUNC74_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC74_IN_SEL 0x0000003F +#define GPIO_FUNC74_IN_SEL_M ((GPIO_FUNC74_IN_SEL_V)<<(GPIO_FUNC74_IN_SEL_S)) +#define GPIO_FUNC74_IN_SEL_V 0x3F +#define GPIO_FUNC74_IN_SEL_S 0 + +#define GPIO_FUNC75_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x280) +/* GPIO_SIG75_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG75_IN_SEL (BIT(7)) +#define GPIO_SIG75_IN_SEL_M (BIT(7)) +#define GPIO_SIG75_IN_SEL_V 0x1 +#define GPIO_SIG75_IN_SEL_S 7 +/* GPIO_FUNC75_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC75_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC75_IN_INV_SEL_V 0x1 +#define GPIO_FUNC75_IN_INV_SEL_S 6 +/* GPIO_FUNC75_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC75_IN_SEL 0x0000003F +#define GPIO_FUNC75_IN_SEL_M ((GPIO_FUNC75_IN_SEL_V)<<(GPIO_FUNC75_IN_SEL_S)) +#define GPIO_FUNC75_IN_SEL_V 0x3F +#define GPIO_FUNC75_IN_SEL_S 0 + +#define GPIO_FUNC76_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x284) +/* GPIO_SIG76_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG76_IN_SEL (BIT(7)) +#define GPIO_SIG76_IN_SEL_M (BIT(7)) +#define GPIO_SIG76_IN_SEL_V 0x1 +#define GPIO_SIG76_IN_SEL_S 7 +/* GPIO_FUNC76_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC76_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC76_IN_INV_SEL_V 0x1 +#define GPIO_FUNC76_IN_INV_SEL_S 6 +/* GPIO_FUNC76_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC76_IN_SEL 0x0000003F +#define GPIO_FUNC76_IN_SEL_M ((GPIO_FUNC76_IN_SEL_V)<<(GPIO_FUNC76_IN_SEL_S)) +#define GPIO_FUNC76_IN_SEL_V 0x3F +#define GPIO_FUNC76_IN_SEL_S 0 + +#define GPIO_FUNC77_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x288) +/* GPIO_SIG77_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG77_IN_SEL (BIT(7)) +#define GPIO_SIG77_IN_SEL_M (BIT(7)) +#define GPIO_SIG77_IN_SEL_V 0x1 +#define GPIO_SIG77_IN_SEL_S 7 +/* GPIO_FUNC77_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC77_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC77_IN_INV_SEL_V 0x1 +#define GPIO_FUNC77_IN_INV_SEL_S 6 +/* GPIO_FUNC77_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC77_IN_SEL 0x0000003F +#define GPIO_FUNC77_IN_SEL_M ((GPIO_FUNC77_IN_SEL_V)<<(GPIO_FUNC77_IN_SEL_S)) +#define GPIO_FUNC77_IN_SEL_V 0x3F +#define GPIO_FUNC77_IN_SEL_S 0 + +#define GPIO_FUNC78_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x28C) +/* GPIO_SIG78_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG78_IN_SEL (BIT(7)) +#define GPIO_SIG78_IN_SEL_M (BIT(7)) +#define GPIO_SIG78_IN_SEL_V 0x1 +#define GPIO_SIG78_IN_SEL_S 7 +/* GPIO_FUNC78_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC78_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC78_IN_INV_SEL_V 0x1 +#define GPIO_FUNC78_IN_INV_SEL_S 6 +/* GPIO_FUNC78_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC78_IN_SEL 0x0000003F +#define GPIO_FUNC78_IN_SEL_M ((GPIO_FUNC78_IN_SEL_V)<<(GPIO_FUNC78_IN_SEL_S)) +#define GPIO_FUNC78_IN_SEL_V 0x3F +#define GPIO_FUNC78_IN_SEL_S 0 + +#define GPIO_FUNC79_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x290) +/* GPIO_SIG79_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG79_IN_SEL (BIT(7)) +#define GPIO_SIG79_IN_SEL_M (BIT(7)) +#define GPIO_SIG79_IN_SEL_V 0x1 +#define GPIO_SIG79_IN_SEL_S 7 +/* GPIO_FUNC79_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC79_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC79_IN_INV_SEL_V 0x1 +#define GPIO_FUNC79_IN_INV_SEL_S 6 +/* GPIO_FUNC79_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC79_IN_SEL 0x0000003F +#define GPIO_FUNC79_IN_SEL_M ((GPIO_FUNC79_IN_SEL_V)<<(GPIO_FUNC79_IN_SEL_S)) +#define GPIO_FUNC79_IN_SEL_V 0x3F +#define GPIO_FUNC79_IN_SEL_S 0 + +#define GPIO_FUNC80_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x294) +/* GPIO_SIG80_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG80_IN_SEL (BIT(7)) +#define GPIO_SIG80_IN_SEL_M (BIT(7)) +#define GPIO_SIG80_IN_SEL_V 0x1 +#define GPIO_SIG80_IN_SEL_S 7 +/* GPIO_FUNC80_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC80_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC80_IN_INV_SEL_V 0x1 +#define GPIO_FUNC80_IN_INV_SEL_S 6 +/* GPIO_FUNC80_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC80_IN_SEL 0x0000003F +#define GPIO_FUNC80_IN_SEL_M ((GPIO_FUNC80_IN_SEL_V)<<(GPIO_FUNC80_IN_SEL_S)) +#define GPIO_FUNC80_IN_SEL_V 0x3F +#define GPIO_FUNC80_IN_SEL_S 0 + +#define GPIO_FUNC81_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x298) +/* GPIO_SIG81_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG81_IN_SEL (BIT(7)) +#define GPIO_SIG81_IN_SEL_M (BIT(7)) +#define GPIO_SIG81_IN_SEL_V 0x1 +#define GPIO_SIG81_IN_SEL_S 7 +/* GPIO_FUNC81_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC81_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC81_IN_INV_SEL_V 0x1 +#define GPIO_FUNC81_IN_INV_SEL_S 6 +/* GPIO_FUNC81_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC81_IN_SEL 0x0000003F +#define GPIO_FUNC81_IN_SEL_M ((GPIO_FUNC81_IN_SEL_V)<<(GPIO_FUNC81_IN_SEL_S)) +#define GPIO_FUNC81_IN_SEL_V 0x3F +#define GPIO_FUNC81_IN_SEL_S 0 + +#define GPIO_FUNC82_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x29C) +/* GPIO_SIG82_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG82_IN_SEL (BIT(7)) +#define GPIO_SIG82_IN_SEL_M (BIT(7)) +#define GPIO_SIG82_IN_SEL_V 0x1 +#define GPIO_SIG82_IN_SEL_S 7 +/* GPIO_FUNC82_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC82_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC82_IN_INV_SEL_V 0x1 +#define GPIO_FUNC82_IN_INV_SEL_S 6 +/* GPIO_FUNC82_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC82_IN_SEL 0x0000003F +#define GPIO_FUNC82_IN_SEL_M ((GPIO_FUNC82_IN_SEL_V)<<(GPIO_FUNC82_IN_SEL_S)) +#define GPIO_FUNC82_IN_SEL_V 0x3F +#define GPIO_FUNC82_IN_SEL_S 0 + +#define GPIO_FUNC83_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A0) +/* GPIO_SIG83_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG83_IN_SEL (BIT(7)) +#define GPIO_SIG83_IN_SEL_M (BIT(7)) +#define GPIO_SIG83_IN_SEL_V 0x1 +#define GPIO_SIG83_IN_SEL_S 7 +/* GPIO_FUNC83_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC83_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC83_IN_INV_SEL_V 0x1 +#define GPIO_FUNC83_IN_INV_SEL_S 6 +/* GPIO_FUNC83_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC83_IN_SEL 0x0000003F +#define GPIO_FUNC83_IN_SEL_M ((GPIO_FUNC83_IN_SEL_V)<<(GPIO_FUNC83_IN_SEL_S)) +#define GPIO_FUNC83_IN_SEL_V 0x3F +#define GPIO_FUNC83_IN_SEL_S 0 + +#define GPIO_FUNC84_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A4) +/* GPIO_SIG84_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG84_IN_SEL (BIT(7)) +#define GPIO_SIG84_IN_SEL_M (BIT(7)) +#define GPIO_SIG84_IN_SEL_V 0x1 +#define GPIO_SIG84_IN_SEL_S 7 +/* GPIO_FUNC84_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC84_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC84_IN_INV_SEL_V 0x1 +#define GPIO_FUNC84_IN_INV_SEL_S 6 +/* GPIO_FUNC84_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC84_IN_SEL 0x0000003F +#define GPIO_FUNC84_IN_SEL_M ((GPIO_FUNC84_IN_SEL_V)<<(GPIO_FUNC84_IN_SEL_S)) +#define GPIO_FUNC84_IN_SEL_V 0x3F +#define GPIO_FUNC84_IN_SEL_S 0 + +#define GPIO_FUNC85_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2A8) +/* GPIO_SIG85_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG85_IN_SEL (BIT(7)) +#define GPIO_SIG85_IN_SEL_M (BIT(7)) +#define GPIO_SIG85_IN_SEL_V 0x1 +#define GPIO_SIG85_IN_SEL_S 7 +/* GPIO_FUNC85_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC85_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC85_IN_INV_SEL_V 0x1 +#define GPIO_FUNC85_IN_INV_SEL_S 6 +/* GPIO_FUNC85_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC85_IN_SEL 0x0000003F +#define GPIO_FUNC85_IN_SEL_M ((GPIO_FUNC85_IN_SEL_V)<<(GPIO_FUNC85_IN_SEL_S)) +#define GPIO_FUNC85_IN_SEL_V 0x3F +#define GPIO_FUNC85_IN_SEL_S 0 + +#define GPIO_FUNC86_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2AC) +/* GPIO_SIG86_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG86_IN_SEL (BIT(7)) +#define GPIO_SIG86_IN_SEL_M (BIT(7)) +#define GPIO_SIG86_IN_SEL_V 0x1 +#define GPIO_SIG86_IN_SEL_S 7 +/* GPIO_FUNC86_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC86_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC86_IN_INV_SEL_V 0x1 +#define GPIO_FUNC86_IN_INV_SEL_S 6 +/* GPIO_FUNC86_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC86_IN_SEL 0x0000003F +#define GPIO_FUNC86_IN_SEL_M ((GPIO_FUNC86_IN_SEL_V)<<(GPIO_FUNC86_IN_SEL_S)) +#define GPIO_FUNC86_IN_SEL_V 0x3F +#define GPIO_FUNC86_IN_SEL_S 0 + +#define GPIO_FUNC87_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B0) +/* GPIO_SIG87_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG87_IN_SEL (BIT(7)) +#define GPIO_SIG87_IN_SEL_M (BIT(7)) +#define GPIO_SIG87_IN_SEL_V 0x1 +#define GPIO_SIG87_IN_SEL_S 7 +/* GPIO_FUNC87_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC87_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC87_IN_INV_SEL_V 0x1 +#define GPIO_FUNC87_IN_INV_SEL_S 6 +/* GPIO_FUNC87_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC87_IN_SEL 0x0000003F +#define GPIO_FUNC87_IN_SEL_M ((GPIO_FUNC87_IN_SEL_V)<<(GPIO_FUNC87_IN_SEL_S)) +#define GPIO_FUNC87_IN_SEL_V 0x3F +#define GPIO_FUNC87_IN_SEL_S 0 + +#define GPIO_FUNC88_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B4) +/* GPIO_SIG88_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG88_IN_SEL (BIT(7)) +#define GPIO_SIG88_IN_SEL_M (BIT(7)) +#define GPIO_SIG88_IN_SEL_V 0x1 +#define GPIO_SIG88_IN_SEL_S 7 +/* GPIO_FUNC88_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC88_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC88_IN_INV_SEL_V 0x1 +#define GPIO_FUNC88_IN_INV_SEL_S 6 +/* GPIO_FUNC88_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC88_IN_SEL 0x0000003F +#define GPIO_FUNC88_IN_SEL_M ((GPIO_FUNC88_IN_SEL_V)<<(GPIO_FUNC88_IN_SEL_S)) +#define GPIO_FUNC88_IN_SEL_V 0x3F +#define GPIO_FUNC88_IN_SEL_S 0 + +#define GPIO_FUNC89_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2B8) +/* GPIO_SIG89_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG89_IN_SEL (BIT(7)) +#define GPIO_SIG89_IN_SEL_M (BIT(7)) +#define GPIO_SIG89_IN_SEL_V 0x1 +#define GPIO_SIG89_IN_SEL_S 7 +/* GPIO_FUNC89_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC89_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC89_IN_INV_SEL_V 0x1 +#define GPIO_FUNC89_IN_INV_SEL_S 6 +/* GPIO_FUNC89_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC89_IN_SEL 0x0000003F +#define GPIO_FUNC89_IN_SEL_M ((GPIO_FUNC89_IN_SEL_V)<<(GPIO_FUNC89_IN_SEL_S)) +#define GPIO_FUNC89_IN_SEL_V 0x3F +#define GPIO_FUNC89_IN_SEL_S 0 + +#define GPIO_FUNC90_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2BC) +/* GPIO_SIG90_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG90_IN_SEL (BIT(7)) +#define GPIO_SIG90_IN_SEL_M (BIT(7)) +#define GPIO_SIG90_IN_SEL_V 0x1 +#define GPIO_SIG90_IN_SEL_S 7 +/* GPIO_FUNC90_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC90_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC90_IN_INV_SEL_V 0x1 +#define GPIO_FUNC90_IN_INV_SEL_S 6 +/* GPIO_FUNC90_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC90_IN_SEL 0x0000003F +#define GPIO_FUNC90_IN_SEL_M ((GPIO_FUNC90_IN_SEL_V)<<(GPIO_FUNC90_IN_SEL_S)) +#define GPIO_FUNC90_IN_SEL_V 0x3F +#define GPIO_FUNC90_IN_SEL_S 0 + +#define GPIO_FUNC91_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C0) +/* GPIO_SIG91_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG91_IN_SEL (BIT(7)) +#define GPIO_SIG91_IN_SEL_M (BIT(7)) +#define GPIO_SIG91_IN_SEL_V 0x1 +#define GPIO_SIG91_IN_SEL_S 7 +/* GPIO_FUNC91_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC91_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC91_IN_INV_SEL_V 0x1 +#define GPIO_FUNC91_IN_INV_SEL_S 6 +/* GPIO_FUNC91_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC91_IN_SEL 0x0000003F +#define GPIO_FUNC91_IN_SEL_M ((GPIO_FUNC91_IN_SEL_V)<<(GPIO_FUNC91_IN_SEL_S)) +#define GPIO_FUNC91_IN_SEL_V 0x3F +#define GPIO_FUNC91_IN_SEL_S 0 + +#define GPIO_FUNC92_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C4) +/* GPIO_SIG92_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG92_IN_SEL (BIT(7)) +#define GPIO_SIG92_IN_SEL_M (BIT(7)) +#define GPIO_SIG92_IN_SEL_V 0x1 +#define GPIO_SIG92_IN_SEL_S 7 +/* GPIO_FUNC92_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC92_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC92_IN_INV_SEL_V 0x1 +#define GPIO_FUNC92_IN_INV_SEL_S 6 +/* GPIO_FUNC92_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC92_IN_SEL 0x0000003F +#define GPIO_FUNC92_IN_SEL_M ((GPIO_FUNC92_IN_SEL_V)<<(GPIO_FUNC92_IN_SEL_S)) +#define GPIO_FUNC92_IN_SEL_V 0x3F +#define GPIO_FUNC92_IN_SEL_S 0 + +#define GPIO_FUNC93_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2C8) +/* GPIO_SIG93_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG93_IN_SEL (BIT(7)) +#define GPIO_SIG93_IN_SEL_M (BIT(7)) +#define GPIO_SIG93_IN_SEL_V 0x1 +#define GPIO_SIG93_IN_SEL_S 7 +/* GPIO_FUNC93_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC93_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC93_IN_INV_SEL_V 0x1 +#define GPIO_FUNC93_IN_INV_SEL_S 6 +/* GPIO_FUNC93_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC93_IN_SEL 0x0000003F +#define GPIO_FUNC93_IN_SEL_M ((GPIO_FUNC93_IN_SEL_V)<<(GPIO_FUNC93_IN_SEL_S)) +#define GPIO_FUNC93_IN_SEL_V 0x3F +#define GPIO_FUNC93_IN_SEL_S 0 + +#define GPIO_FUNC94_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2CC) +/* GPIO_SIG94_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG94_IN_SEL (BIT(7)) +#define GPIO_SIG94_IN_SEL_M (BIT(7)) +#define GPIO_SIG94_IN_SEL_V 0x1 +#define GPIO_SIG94_IN_SEL_S 7 +/* GPIO_FUNC94_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC94_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC94_IN_INV_SEL_V 0x1 +#define GPIO_FUNC94_IN_INV_SEL_S 6 +/* GPIO_FUNC94_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC94_IN_SEL 0x0000003F +#define GPIO_FUNC94_IN_SEL_M ((GPIO_FUNC94_IN_SEL_V)<<(GPIO_FUNC94_IN_SEL_S)) +#define GPIO_FUNC94_IN_SEL_V 0x3F +#define GPIO_FUNC94_IN_SEL_S 0 + +#define GPIO_FUNC95_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D0) +/* GPIO_SIG95_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG95_IN_SEL (BIT(7)) +#define GPIO_SIG95_IN_SEL_M (BIT(7)) +#define GPIO_SIG95_IN_SEL_V 0x1 +#define GPIO_SIG95_IN_SEL_S 7 +/* GPIO_FUNC95_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC95_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC95_IN_INV_SEL_V 0x1 +#define GPIO_FUNC95_IN_INV_SEL_S 6 +/* GPIO_FUNC95_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC95_IN_SEL 0x0000003F +#define GPIO_FUNC95_IN_SEL_M ((GPIO_FUNC95_IN_SEL_V)<<(GPIO_FUNC95_IN_SEL_S)) +#define GPIO_FUNC95_IN_SEL_V 0x3F +#define GPIO_FUNC95_IN_SEL_S 0 + +#define GPIO_FUNC96_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D4) +/* GPIO_SIG96_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG96_IN_SEL (BIT(7)) +#define GPIO_SIG96_IN_SEL_M (BIT(7)) +#define GPIO_SIG96_IN_SEL_V 0x1 +#define GPIO_SIG96_IN_SEL_S 7 +/* GPIO_FUNC96_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC96_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC96_IN_INV_SEL_V 0x1 +#define GPIO_FUNC96_IN_INV_SEL_S 6 +/* GPIO_FUNC96_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC96_IN_SEL 0x0000003F +#define GPIO_FUNC96_IN_SEL_M ((GPIO_FUNC96_IN_SEL_V)<<(GPIO_FUNC96_IN_SEL_S)) +#define GPIO_FUNC96_IN_SEL_V 0x3F +#define GPIO_FUNC96_IN_SEL_S 0 + +#define GPIO_FUNC97_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2D8) +/* GPIO_SIG97_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG97_IN_SEL (BIT(7)) +#define GPIO_SIG97_IN_SEL_M (BIT(7)) +#define GPIO_SIG97_IN_SEL_V 0x1 +#define GPIO_SIG97_IN_SEL_S 7 +/* GPIO_FUNC97_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC97_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC97_IN_INV_SEL_V 0x1 +#define GPIO_FUNC97_IN_INV_SEL_S 6 +/* GPIO_FUNC97_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC97_IN_SEL 0x0000003F +#define GPIO_FUNC97_IN_SEL_M ((GPIO_FUNC97_IN_SEL_V)<<(GPIO_FUNC97_IN_SEL_S)) +#define GPIO_FUNC97_IN_SEL_V 0x3F +#define GPIO_FUNC97_IN_SEL_S 0 + +#define GPIO_FUNC98_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2DC) +/* GPIO_SIG98_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG98_IN_SEL (BIT(7)) +#define GPIO_SIG98_IN_SEL_M (BIT(7)) +#define GPIO_SIG98_IN_SEL_V 0x1 +#define GPIO_SIG98_IN_SEL_S 7 +/* GPIO_FUNC98_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC98_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC98_IN_INV_SEL_V 0x1 +#define GPIO_FUNC98_IN_INV_SEL_S 6 +/* GPIO_FUNC98_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC98_IN_SEL 0x0000003F +#define GPIO_FUNC98_IN_SEL_M ((GPIO_FUNC98_IN_SEL_V)<<(GPIO_FUNC98_IN_SEL_S)) +#define GPIO_FUNC98_IN_SEL_V 0x3F +#define GPIO_FUNC98_IN_SEL_S 0 + +#define GPIO_FUNC99_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E0) +/* GPIO_SIG99_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG99_IN_SEL (BIT(7)) +#define GPIO_SIG99_IN_SEL_M (BIT(7)) +#define GPIO_SIG99_IN_SEL_V 0x1 +#define GPIO_SIG99_IN_SEL_S 7 +/* GPIO_FUNC99_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC99_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC99_IN_INV_SEL_V 0x1 +#define GPIO_FUNC99_IN_INV_SEL_S 6 +/* GPIO_FUNC99_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC99_IN_SEL 0x0000003F +#define GPIO_FUNC99_IN_SEL_M ((GPIO_FUNC99_IN_SEL_V)<<(GPIO_FUNC99_IN_SEL_S)) +#define GPIO_FUNC99_IN_SEL_V 0x3F +#define GPIO_FUNC99_IN_SEL_S 0 + +#define GPIO_FUNC100_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E4) +/* GPIO_SIG100_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG100_IN_SEL (BIT(7)) +#define GPIO_SIG100_IN_SEL_M (BIT(7)) +#define GPIO_SIG100_IN_SEL_V 0x1 +#define GPIO_SIG100_IN_SEL_S 7 +/* GPIO_FUNC100_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC100_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC100_IN_INV_SEL_V 0x1 +#define GPIO_FUNC100_IN_INV_SEL_S 6 +/* GPIO_FUNC100_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC100_IN_SEL 0x0000003F +#define GPIO_FUNC100_IN_SEL_M ((GPIO_FUNC100_IN_SEL_V)<<(GPIO_FUNC100_IN_SEL_S)) +#define GPIO_FUNC100_IN_SEL_V 0x3F +#define GPIO_FUNC100_IN_SEL_S 0 + +#define GPIO_FUNC101_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2E8) +/* GPIO_SIG101_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG101_IN_SEL (BIT(7)) +#define GPIO_SIG101_IN_SEL_M (BIT(7)) +#define GPIO_SIG101_IN_SEL_V 0x1 +#define GPIO_SIG101_IN_SEL_S 7 +/* GPIO_FUNC101_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC101_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC101_IN_INV_SEL_V 0x1 +#define GPIO_FUNC101_IN_INV_SEL_S 6 +/* GPIO_FUNC101_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC101_IN_SEL 0x0000003F +#define GPIO_FUNC101_IN_SEL_M ((GPIO_FUNC101_IN_SEL_V)<<(GPIO_FUNC101_IN_SEL_S)) +#define GPIO_FUNC101_IN_SEL_V 0x3F +#define GPIO_FUNC101_IN_SEL_S 0 + +#define GPIO_FUNC102_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2EC) +/* GPIO_SIG102_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG102_IN_SEL (BIT(7)) +#define GPIO_SIG102_IN_SEL_M (BIT(7)) +#define GPIO_SIG102_IN_SEL_V 0x1 +#define GPIO_SIG102_IN_SEL_S 7 +/* GPIO_FUNC102_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC102_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC102_IN_INV_SEL_V 0x1 +#define GPIO_FUNC102_IN_INV_SEL_S 6 +/* GPIO_FUNC102_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC102_IN_SEL 0x0000003F +#define GPIO_FUNC102_IN_SEL_M ((GPIO_FUNC102_IN_SEL_V)<<(GPIO_FUNC102_IN_SEL_S)) +#define GPIO_FUNC102_IN_SEL_V 0x3F +#define GPIO_FUNC102_IN_SEL_S 0 + +#define GPIO_FUNC103_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F0) +/* GPIO_SIG103_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG103_IN_SEL (BIT(7)) +#define GPIO_SIG103_IN_SEL_M (BIT(7)) +#define GPIO_SIG103_IN_SEL_V 0x1 +#define GPIO_SIG103_IN_SEL_S 7 +/* GPIO_FUNC103_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC103_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC103_IN_INV_SEL_V 0x1 +#define GPIO_FUNC103_IN_INV_SEL_S 6 +/* GPIO_FUNC103_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC103_IN_SEL 0x0000003F +#define GPIO_FUNC103_IN_SEL_M ((GPIO_FUNC103_IN_SEL_V)<<(GPIO_FUNC103_IN_SEL_S)) +#define GPIO_FUNC103_IN_SEL_V 0x3F +#define GPIO_FUNC103_IN_SEL_S 0 + +#define GPIO_FUNC104_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F4) +/* GPIO_SIG104_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG104_IN_SEL (BIT(7)) +#define GPIO_SIG104_IN_SEL_M (BIT(7)) +#define GPIO_SIG104_IN_SEL_V 0x1 +#define GPIO_SIG104_IN_SEL_S 7 +/* GPIO_FUNC104_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC104_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC104_IN_INV_SEL_V 0x1 +#define GPIO_FUNC104_IN_INV_SEL_S 6 +/* GPIO_FUNC104_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC104_IN_SEL 0x0000003F +#define GPIO_FUNC104_IN_SEL_M ((GPIO_FUNC104_IN_SEL_V)<<(GPIO_FUNC104_IN_SEL_S)) +#define GPIO_FUNC104_IN_SEL_V 0x3F +#define GPIO_FUNC104_IN_SEL_S 0 + +#define GPIO_FUNC105_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2F8) +/* GPIO_SIG105_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG105_IN_SEL (BIT(7)) +#define GPIO_SIG105_IN_SEL_M (BIT(7)) +#define GPIO_SIG105_IN_SEL_V 0x1 +#define GPIO_SIG105_IN_SEL_S 7 +/* GPIO_FUNC105_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC105_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC105_IN_INV_SEL_V 0x1 +#define GPIO_FUNC105_IN_INV_SEL_S 6 +/* GPIO_FUNC105_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC105_IN_SEL 0x0000003F +#define GPIO_FUNC105_IN_SEL_M ((GPIO_FUNC105_IN_SEL_V)<<(GPIO_FUNC105_IN_SEL_S)) +#define GPIO_FUNC105_IN_SEL_V 0x3F +#define GPIO_FUNC105_IN_SEL_S 0 + +#define GPIO_FUNC106_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x2FC) +/* GPIO_SIG106_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG106_IN_SEL (BIT(7)) +#define GPIO_SIG106_IN_SEL_M (BIT(7)) +#define GPIO_SIG106_IN_SEL_V 0x1 +#define GPIO_SIG106_IN_SEL_S 7 +/* GPIO_FUNC106_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC106_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC106_IN_INV_SEL_V 0x1 +#define GPIO_FUNC106_IN_INV_SEL_S 6 +/* GPIO_FUNC106_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC106_IN_SEL 0x0000003F +#define GPIO_FUNC106_IN_SEL_M ((GPIO_FUNC106_IN_SEL_V)<<(GPIO_FUNC106_IN_SEL_S)) +#define GPIO_FUNC106_IN_SEL_V 0x3F +#define GPIO_FUNC106_IN_SEL_S 0 + +#define GPIO_FUNC107_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x300) +/* GPIO_SIG107_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG107_IN_SEL (BIT(7)) +#define GPIO_SIG107_IN_SEL_M (BIT(7)) +#define GPIO_SIG107_IN_SEL_V 0x1 +#define GPIO_SIG107_IN_SEL_S 7 +/* GPIO_FUNC107_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC107_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC107_IN_INV_SEL_V 0x1 +#define GPIO_FUNC107_IN_INV_SEL_S 6 +/* GPIO_FUNC107_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC107_IN_SEL 0x0000003F +#define GPIO_FUNC107_IN_SEL_M ((GPIO_FUNC107_IN_SEL_V)<<(GPIO_FUNC107_IN_SEL_S)) +#define GPIO_FUNC107_IN_SEL_V 0x3F +#define GPIO_FUNC107_IN_SEL_S 0 + +#define GPIO_FUNC108_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x304) +/* GPIO_SIG108_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG108_IN_SEL (BIT(7)) +#define GPIO_SIG108_IN_SEL_M (BIT(7)) +#define GPIO_SIG108_IN_SEL_V 0x1 +#define GPIO_SIG108_IN_SEL_S 7 +/* GPIO_FUNC108_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC108_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC108_IN_INV_SEL_V 0x1 +#define GPIO_FUNC108_IN_INV_SEL_S 6 +/* GPIO_FUNC108_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC108_IN_SEL 0x0000003F +#define GPIO_FUNC108_IN_SEL_M ((GPIO_FUNC108_IN_SEL_V)<<(GPIO_FUNC108_IN_SEL_S)) +#define GPIO_FUNC108_IN_SEL_V 0x3F +#define GPIO_FUNC108_IN_SEL_S 0 + +#define GPIO_FUNC109_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x308) +/* GPIO_SIG109_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG109_IN_SEL (BIT(7)) +#define GPIO_SIG109_IN_SEL_M (BIT(7)) +#define GPIO_SIG109_IN_SEL_V 0x1 +#define GPIO_SIG109_IN_SEL_S 7 +/* GPIO_FUNC109_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC109_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC109_IN_INV_SEL_V 0x1 +#define GPIO_FUNC109_IN_INV_SEL_S 6 +/* GPIO_FUNC109_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC109_IN_SEL 0x0000003F +#define GPIO_FUNC109_IN_SEL_M ((GPIO_FUNC109_IN_SEL_V)<<(GPIO_FUNC109_IN_SEL_S)) +#define GPIO_FUNC109_IN_SEL_V 0x3F +#define GPIO_FUNC109_IN_SEL_S 0 + +#define GPIO_FUNC110_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x30C) +/* GPIO_SIG110_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG110_IN_SEL (BIT(7)) +#define GPIO_SIG110_IN_SEL_M (BIT(7)) +#define GPIO_SIG110_IN_SEL_V 0x1 +#define GPIO_SIG110_IN_SEL_S 7 +/* GPIO_FUNC110_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC110_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC110_IN_INV_SEL_V 0x1 +#define GPIO_FUNC110_IN_INV_SEL_S 6 +/* GPIO_FUNC110_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC110_IN_SEL 0x0000003F +#define GPIO_FUNC110_IN_SEL_M ((GPIO_FUNC110_IN_SEL_V)<<(GPIO_FUNC110_IN_SEL_S)) +#define GPIO_FUNC110_IN_SEL_V 0x3F +#define GPIO_FUNC110_IN_SEL_S 0 + +#define GPIO_FUNC111_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x310) +/* GPIO_SIG111_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG111_IN_SEL (BIT(7)) +#define GPIO_SIG111_IN_SEL_M (BIT(7)) +#define GPIO_SIG111_IN_SEL_V 0x1 +#define GPIO_SIG111_IN_SEL_S 7 +/* GPIO_FUNC111_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC111_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC111_IN_INV_SEL_V 0x1 +#define GPIO_FUNC111_IN_INV_SEL_S 6 +/* GPIO_FUNC111_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC111_IN_SEL 0x0000003F +#define GPIO_FUNC111_IN_SEL_M ((GPIO_FUNC111_IN_SEL_V)<<(GPIO_FUNC111_IN_SEL_S)) +#define GPIO_FUNC111_IN_SEL_V 0x3F +#define GPIO_FUNC111_IN_SEL_S 0 + +#define GPIO_FUNC112_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x314) +/* GPIO_SIG112_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG112_IN_SEL (BIT(7)) +#define GPIO_SIG112_IN_SEL_M (BIT(7)) +#define GPIO_SIG112_IN_SEL_V 0x1 +#define GPIO_SIG112_IN_SEL_S 7 +/* GPIO_FUNC112_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC112_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC112_IN_INV_SEL_V 0x1 +#define GPIO_FUNC112_IN_INV_SEL_S 6 +/* GPIO_FUNC112_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC112_IN_SEL 0x0000003F +#define GPIO_FUNC112_IN_SEL_M ((GPIO_FUNC112_IN_SEL_V)<<(GPIO_FUNC112_IN_SEL_S)) +#define GPIO_FUNC112_IN_SEL_V 0x3F +#define GPIO_FUNC112_IN_SEL_S 0 + +#define GPIO_FUNC113_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x318) +/* GPIO_SIG113_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG113_IN_SEL (BIT(7)) +#define GPIO_SIG113_IN_SEL_M (BIT(7)) +#define GPIO_SIG113_IN_SEL_V 0x1 +#define GPIO_SIG113_IN_SEL_S 7 +/* GPIO_FUNC113_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC113_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC113_IN_INV_SEL_V 0x1 +#define GPIO_FUNC113_IN_INV_SEL_S 6 +/* GPIO_FUNC113_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC113_IN_SEL 0x0000003F +#define GPIO_FUNC113_IN_SEL_M ((GPIO_FUNC113_IN_SEL_V)<<(GPIO_FUNC113_IN_SEL_S)) +#define GPIO_FUNC113_IN_SEL_V 0x3F +#define GPIO_FUNC113_IN_SEL_S 0 + +#define GPIO_FUNC114_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x31C) +/* GPIO_SIG114_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG114_IN_SEL (BIT(7)) +#define GPIO_SIG114_IN_SEL_M (BIT(7)) +#define GPIO_SIG114_IN_SEL_V 0x1 +#define GPIO_SIG114_IN_SEL_S 7 +/* GPIO_FUNC114_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC114_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC114_IN_INV_SEL_V 0x1 +#define GPIO_FUNC114_IN_INV_SEL_S 6 +/* GPIO_FUNC114_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC114_IN_SEL 0x0000003F +#define GPIO_FUNC114_IN_SEL_M ((GPIO_FUNC114_IN_SEL_V)<<(GPIO_FUNC114_IN_SEL_S)) +#define GPIO_FUNC114_IN_SEL_V 0x3F +#define GPIO_FUNC114_IN_SEL_S 0 + +#define GPIO_FUNC115_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x320) +/* GPIO_SIG115_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG115_IN_SEL (BIT(7)) +#define GPIO_SIG115_IN_SEL_M (BIT(7)) +#define GPIO_SIG115_IN_SEL_V 0x1 +#define GPIO_SIG115_IN_SEL_S 7 +/* GPIO_FUNC115_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC115_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC115_IN_INV_SEL_V 0x1 +#define GPIO_FUNC115_IN_INV_SEL_S 6 +/* GPIO_FUNC115_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC115_IN_SEL 0x0000003F +#define GPIO_FUNC115_IN_SEL_M ((GPIO_FUNC115_IN_SEL_V)<<(GPIO_FUNC115_IN_SEL_S)) +#define GPIO_FUNC115_IN_SEL_V 0x3F +#define GPIO_FUNC115_IN_SEL_S 0 + +#define GPIO_FUNC116_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x324) +/* GPIO_SIG116_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG116_IN_SEL (BIT(7)) +#define GPIO_SIG116_IN_SEL_M (BIT(7)) +#define GPIO_SIG116_IN_SEL_V 0x1 +#define GPIO_SIG116_IN_SEL_S 7 +/* GPIO_FUNC116_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC116_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC116_IN_INV_SEL_V 0x1 +#define GPIO_FUNC116_IN_INV_SEL_S 6 +/* GPIO_FUNC116_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC116_IN_SEL 0x0000003F +#define GPIO_FUNC116_IN_SEL_M ((GPIO_FUNC116_IN_SEL_V)<<(GPIO_FUNC116_IN_SEL_S)) +#define GPIO_FUNC116_IN_SEL_V 0x3F +#define GPIO_FUNC116_IN_SEL_S 0 + +#define GPIO_FUNC117_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x328) +/* GPIO_SIG117_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG117_IN_SEL (BIT(7)) +#define GPIO_SIG117_IN_SEL_M (BIT(7)) +#define GPIO_SIG117_IN_SEL_V 0x1 +#define GPIO_SIG117_IN_SEL_S 7 +/* GPIO_FUNC117_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC117_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC117_IN_INV_SEL_V 0x1 +#define GPIO_FUNC117_IN_INV_SEL_S 6 +/* GPIO_FUNC117_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC117_IN_SEL 0x0000003F +#define GPIO_FUNC117_IN_SEL_M ((GPIO_FUNC117_IN_SEL_V)<<(GPIO_FUNC117_IN_SEL_S)) +#define GPIO_FUNC117_IN_SEL_V 0x3F +#define GPIO_FUNC117_IN_SEL_S 0 + +#define GPIO_FUNC118_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x32C) +/* GPIO_SIG118_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG118_IN_SEL (BIT(7)) +#define GPIO_SIG118_IN_SEL_M (BIT(7)) +#define GPIO_SIG118_IN_SEL_V 0x1 +#define GPIO_SIG118_IN_SEL_S 7 +/* GPIO_FUNC118_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC118_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC118_IN_INV_SEL_V 0x1 +#define GPIO_FUNC118_IN_INV_SEL_S 6 +/* GPIO_FUNC118_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC118_IN_SEL 0x0000003F +#define GPIO_FUNC118_IN_SEL_M ((GPIO_FUNC118_IN_SEL_V)<<(GPIO_FUNC118_IN_SEL_S)) +#define GPIO_FUNC118_IN_SEL_V 0x3F +#define GPIO_FUNC118_IN_SEL_S 0 + +#define GPIO_FUNC119_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x330) +/* GPIO_SIG119_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG119_IN_SEL (BIT(7)) +#define GPIO_SIG119_IN_SEL_M (BIT(7)) +#define GPIO_SIG119_IN_SEL_V 0x1 +#define GPIO_SIG119_IN_SEL_S 7 +/* GPIO_FUNC119_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC119_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC119_IN_INV_SEL_V 0x1 +#define GPIO_FUNC119_IN_INV_SEL_S 6 +/* GPIO_FUNC119_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC119_IN_SEL 0x0000003F +#define GPIO_FUNC119_IN_SEL_M ((GPIO_FUNC119_IN_SEL_V)<<(GPIO_FUNC119_IN_SEL_S)) +#define GPIO_FUNC119_IN_SEL_V 0x3F +#define GPIO_FUNC119_IN_SEL_S 0 + +#define GPIO_FUNC120_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x334) +/* GPIO_SIG120_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG120_IN_SEL (BIT(7)) +#define GPIO_SIG120_IN_SEL_M (BIT(7)) +#define GPIO_SIG120_IN_SEL_V 0x1 +#define GPIO_SIG120_IN_SEL_S 7 +/* GPIO_FUNC120_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC120_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC120_IN_INV_SEL_V 0x1 +#define GPIO_FUNC120_IN_INV_SEL_S 6 +/* GPIO_FUNC120_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC120_IN_SEL 0x0000003F +#define GPIO_FUNC120_IN_SEL_M ((GPIO_FUNC120_IN_SEL_V)<<(GPIO_FUNC120_IN_SEL_S)) +#define GPIO_FUNC120_IN_SEL_V 0x3F +#define GPIO_FUNC120_IN_SEL_S 0 + +#define GPIO_FUNC121_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x338) +/* GPIO_SIG121_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG121_IN_SEL (BIT(7)) +#define GPIO_SIG121_IN_SEL_M (BIT(7)) +#define GPIO_SIG121_IN_SEL_V 0x1 +#define GPIO_SIG121_IN_SEL_S 7 +/* GPIO_FUNC121_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC121_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC121_IN_INV_SEL_V 0x1 +#define GPIO_FUNC121_IN_INV_SEL_S 6 +/* GPIO_FUNC121_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC121_IN_SEL 0x0000003F +#define GPIO_FUNC121_IN_SEL_M ((GPIO_FUNC121_IN_SEL_V)<<(GPIO_FUNC121_IN_SEL_S)) +#define GPIO_FUNC121_IN_SEL_V 0x3F +#define GPIO_FUNC121_IN_SEL_S 0 + +#define GPIO_FUNC122_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x33C) +/* GPIO_SIG122_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG122_IN_SEL (BIT(7)) +#define GPIO_SIG122_IN_SEL_M (BIT(7)) +#define GPIO_SIG122_IN_SEL_V 0x1 +#define GPIO_SIG122_IN_SEL_S 7 +/* GPIO_FUNC122_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC122_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC122_IN_INV_SEL_V 0x1 +#define GPIO_FUNC122_IN_INV_SEL_S 6 +/* GPIO_FUNC122_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC122_IN_SEL 0x0000003F +#define GPIO_FUNC122_IN_SEL_M ((GPIO_FUNC122_IN_SEL_V)<<(GPIO_FUNC122_IN_SEL_S)) +#define GPIO_FUNC122_IN_SEL_V 0x3F +#define GPIO_FUNC122_IN_SEL_S 0 + +#define GPIO_FUNC123_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x340) +/* GPIO_SIG123_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG123_IN_SEL (BIT(7)) +#define GPIO_SIG123_IN_SEL_M (BIT(7)) +#define GPIO_SIG123_IN_SEL_V 0x1 +#define GPIO_SIG123_IN_SEL_S 7 +/* GPIO_FUNC123_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC123_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC123_IN_INV_SEL_V 0x1 +#define GPIO_FUNC123_IN_INV_SEL_S 6 +/* GPIO_FUNC123_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC123_IN_SEL 0x0000003F +#define GPIO_FUNC123_IN_SEL_M ((GPIO_FUNC123_IN_SEL_V)<<(GPIO_FUNC123_IN_SEL_S)) +#define GPIO_FUNC123_IN_SEL_V 0x3F +#define GPIO_FUNC123_IN_SEL_S 0 + +#define GPIO_FUNC124_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x344) +/* GPIO_SIG124_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG124_IN_SEL (BIT(7)) +#define GPIO_SIG124_IN_SEL_M (BIT(7)) +#define GPIO_SIG124_IN_SEL_V 0x1 +#define GPIO_SIG124_IN_SEL_S 7 +/* GPIO_FUNC124_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC124_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC124_IN_INV_SEL_V 0x1 +#define GPIO_FUNC124_IN_INV_SEL_S 6 +/* GPIO_FUNC124_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC124_IN_SEL 0x0000003F +#define GPIO_FUNC124_IN_SEL_M ((GPIO_FUNC124_IN_SEL_V)<<(GPIO_FUNC124_IN_SEL_S)) +#define GPIO_FUNC124_IN_SEL_V 0x3F +#define GPIO_FUNC124_IN_SEL_S 0 + +#define GPIO_FUNC125_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x348) +/* GPIO_SIG125_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG125_IN_SEL (BIT(7)) +#define GPIO_SIG125_IN_SEL_M (BIT(7)) +#define GPIO_SIG125_IN_SEL_V 0x1 +#define GPIO_SIG125_IN_SEL_S 7 +/* GPIO_FUNC125_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC125_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC125_IN_INV_SEL_V 0x1 +#define GPIO_FUNC125_IN_INV_SEL_S 6 +/* GPIO_FUNC125_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC125_IN_SEL 0x0000003F +#define GPIO_FUNC125_IN_SEL_M ((GPIO_FUNC125_IN_SEL_V)<<(GPIO_FUNC125_IN_SEL_S)) +#define GPIO_FUNC125_IN_SEL_V 0x3F +#define GPIO_FUNC125_IN_SEL_S 0 + +#define GPIO_FUNC126_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x34C) +/* GPIO_SIG126_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG126_IN_SEL (BIT(7)) +#define GPIO_SIG126_IN_SEL_M (BIT(7)) +#define GPIO_SIG126_IN_SEL_V 0x1 +#define GPIO_SIG126_IN_SEL_S 7 +/* GPIO_FUNC126_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC126_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC126_IN_INV_SEL_V 0x1 +#define GPIO_FUNC126_IN_INV_SEL_S 6 +/* GPIO_FUNC126_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC126_IN_SEL 0x0000003F +#define GPIO_FUNC126_IN_SEL_M ((GPIO_FUNC126_IN_SEL_V)<<(GPIO_FUNC126_IN_SEL_S)) +#define GPIO_FUNC126_IN_SEL_V 0x3F +#define GPIO_FUNC126_IN_SEL_S 0 + +#define GPIO_FUNC127_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x350) +/* GPIO_SIG127_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG127_IN_SEL (BIT(7)) +#define GPIO_SIG127_IN_SEL_M (BIT(7)) +#define GPIO_SIG127_IN_SEL_V 0x1 +#define GPIO_SIG127_IN_SEL_S 7 +/* GPIO_FUNC127_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC127_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC127_IN_INV_SEL_V 0x1 +#define GPIO_FUNC127_IN_INV_SEL_S 6 +/* GPIO_FUNC127_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC127_IN_SEL 0x0000003F +#define GPIO_FUNC127_IN_SEL_M ((GPIO_FUNC127_IN_SEL_V)<<(GPIO_FUNC127_IN_SEL_S)) +#define GPIO_FUNC127_IN_SEL_V 0x3F +#define GPIO_FUNC127_IN_SEL_S 0 + +#define GPIO_FUNC128_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x354) +/* GPIO_SIG128_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG128_IN_SEL (BIT(7)) +#define GPIO_SIG128_IN_SEL_M (BIT(7)) +#define GPIO_SIG128_IN_SEL_V 0x1 +#define GPIO_SIG128_IN_SEL_S 7 +/* GPIO_FUNC128_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC128_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC128_IN_INV_SEL_V 0x1 +#define GPIO_FUNC128_IN_INV_SEL_S 6 +/* GPIO_FUNC128_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC128_IN_SEL 0x0000003F +#define GPIO_FUNC128_IN_SEL_M ((GPIO_FUNC128_IN_SEL_V)<<(GPIO_FUNC128_IN_SEL_S)) +#define GPIO_FUNC128_IN_SEL_V 0x3F +#define GPIO_FUNC128_IN_SEL_S 0 + +#define GPIO_FUNC129_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x358) +/* GPIO_SIG129_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG129_IN_SEL (BIT(7)) +#define GPIO_SIG129_IN_SEL_M (BIT(7)) +#define GPIO_SIG129_IN_SEL_V 0x1 +#define GPIO_SIG129_IN_SEL_S 7 +/* GPIO_FUNC129_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC129_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC129_IN_INV_SEL_V 0x1 +#define GPIO_FUNC129_IN_INV_SEL_S 6 +/* GPIO_FUNC129_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC129_IN_SEL 0x0000003F +#define GPIO_FUNC129_IN_SEL_M ((GPIO_FUNC129_IN_SEL_V)<<(GPIO_FUNC129_IN_SEL_S)) +#define GPIO_FUNC129_IN_SEL_V 0x3F +#define GPIO_FUNC129_IN_SEL_S 0 + +#define GPIO_FUNC130_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x35C) +/* GPIO_SIG130_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG130_IN_SEL (BIT(7)) +#define GPIO_SIG130_IN_SEL_M (BIT(7)) +#define GPIO_SIG130_IN_SEL_V 0x1 +#define GPIO_SIG130_IN_SEL_S 7 +/* GPIO_FUNC130_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC130_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC130_IN_INV_SEL_V 0x1 +#define GPIO_FUNC130_IN_INV_SEL_S 6 +/* GPIO_FUNC130_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC130_IN_SEL 0x0000003F +#define GPIO_FUNC130_IN_SEL_M ((GPIO_FUNC130_IN_SEL_V)<<(GPIO_FUNC130_IN_SEL_S)) +#define GPIO_FUNC130_IN_SEL_V 0x3F +#define GPIO_FUNC130_IN_SEL_S 0 + +#define GPIO_FUNC131_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x360) +/* GPIO_SIG131_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG131_IN_SEL (BIT(7)) +#define GPIO_SIG131_IN_SEL_M (BIT(7)) +#define GPIO_SIG131_IN_SEL_V 0x1 +#define GPIO_SIG131_IN_SEL_S 7 +/* GPIO_FUNC131_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC131_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC131_IN_INV_SEL_V 0x1 +#define GPIO_FUNC131_IN_INV_SEL_S 6 +/* GPIO_FUNC131_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC131_IN_SEL 0x0000003F +#define GPIO_FUNC131_IN_SEL_M ((GPIO_FUNC131_IN_SEL_V)<<(GPIO_FUNC131_IN_SEL_S)) +#define GPIO_FUNC131_IN_SEL_V 0x3F +#define GPIO_FUNC131_IN_SEL_S 0 + +#define GPIO_FUNC132_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x364) +/* GPIO_SIG132_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG132_IN_SEL (BIT(7)) +#define GPIO_SIG132_IN_SEL_M (BIT(7)) +#define GPIO_SIG132_IN_SEL_V 0x1 +#define GPIO_SIG132_IN_SEL_S 7 +/* GPIO_FUNC132_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC132_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC132_IN_INV_SEL_V 0x1 +#define GPIO_FUNC132_IN_INV_SEL_S 6 +/* GPIO_FUNC132_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC132_IN_SEL 0x0000003F +#define GPIO_FUNC132_IN_SEL_M ((GPIO_FUNC132_IN_SEL_V)<<(GPIO_FUNC132_IN_SEL_S)) +#define GPIO_FUNC132_IN_SEL_V 0x3F +#define GPIO_FUNC132_IN_SEL_S 0 + +#define GPIO_FUNC133_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x368) +/* GPIO_SIG133_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG133_IN_SEL (BIT(7)) +#define GPIO_SIG133_IN_SEL_M (BIT(7)) +#define GPIO_SIG133_IN_SEL_V 0x1 +#define GPIO_SIG133_IN_SEL_S 7 +/* GPIO_FUNC133_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC133_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC133_IN_INV_SEL_V 0x1 +#define GPIO_FUNC133_IN_INV_SEL_S 6 +/* GPIO_FUNC133_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC133_IN_SEL 0x0000003F +#define GPIO_FUNC133_IN_SEL_M ((GPIO_FUNC133_IN_SEL_V)<<(GPIO_FUNC133_IN_SEL_S)) +#define GPIO_FUNC133_IN_SEL_V 0x3F +#define GPIO_FUNC133_IN_SEL_S 0 + +#define GPIO_FUNC134_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x36C) +/* GPIO_SIG134_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG134_IN_SEL (BIT(7)) +#define GPIO_SIG134_IN_SEL_M (BIT(7)) +#define GPIO_SIG134_IN_SEL_V 0x1 +#define GPIO_SIG134_IN_SEL_S 7 +/* GPIO_FUNC134_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC134_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC134_IN_INV_SEL_V 0x1 +#define GPIO_FUNC134_IN_INV_SEL_S 6 +/* GPIO_FUNC134_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC134_IN_SEL 0x0000003F +#define GPIO_FUNC134_IN_SEL_M ((GPIO_FUNC134_IN_SEL_V)<<(GPIO_FUNC134_IN_SEL_S)) +#define GPIO_FUNC134_IN_SEL_V 0x3F +#define GPIO_FUNC134_IN_SEL_S 0 + +#define GPIO_FUNC135_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x370) +/* GPIO_SIG135_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG135_IN_SEL (BIT(7)) +#define GPIO_SIG135_IN_SEL_M (BIT(7)) +#define GPIO_SIG135_IN_SEL_V 0x1 +#define GPIO_SIG135_IN_SEL_S 7 +/* GPIO_FUNC135_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC135_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC135_IN_INV_SEL_V 0x1 +#define GPIO_FUNC135_IN_INV_SEL_S 6 +/* GPIO_FUNC135_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC135_IN_SEL 0x0000003F +#define GPIO_FUNC135_IN_SEL_M ((GPIO_FUNC135_IN_SEL_V)<<(GPIO_FUNC135_IN_SEL_S)) +#define GPIO_FUNC135_IN_SEL_V 0x3F +#define GPIO_FUNC135_IN_SEL_S 0 + +#define GPIO_FUNC136_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x374) +/* GPIO_SIG136_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG136_IN_SEL (BIT(7)) +#define GPIO_SIG136_IN_SEL_M (BIT(7)) +#define GPIO_SIG136_IN_SEL_V 0x1 +#define GPIO_SIG136_IN_SEL_S 7 +/* GPIO_FUNC136_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC136_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC136_IN_INV_SEL_V 0x1 +#define GPIO_FUNC136_IN_INV_SEL_S 6 +/* GPIO_FUNC136_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC136_IN_SEL 0x0000003F +#define GPIO_FUNC136_IN_SEL_M ((GPIO_FUNC136_IN_SEL_V)<<(GPIO_FUNC136_IN_SEL_S)) +#define GPIO_FUNC136_IN_SEL_V 0x3F +#define GPIO_FUNC136_IN_SEL_S 0 + +#define GPIO_FUNC137_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x378) +/* GPIO_SIG137_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG137_IN_SEL (BIT(7)) +#define GPIO_SIG137_IN_SEL_M (BIT(7)) +#define GPIO_SIG137_IN_SEL_V 0x1 +#define GPIO_SIG137_IN_SEL_S 7 +/* GPIO_FUNC137_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC137_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC137_IN_INV_SEL_V 0x1 +#define GPIO_FUNC137_IN_INV_SEL_S 6 +/* GPIO_FUNC137_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC137_IN_SEL 0x0000003F +#define GPIO_FUNC137_IN_SEL_M ((GPIO_FUNC137_IN_SEL_V)<<(GPIO_FUNC137_IN_SEL_S)) +#define GPIO_FUNC137_IN_SEL_V 0x3F +#define GPIO_FUNC137_IN_SEL_S 0 + +#define GPIO_FUNC138_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x37C) +/* GPIO_SIG138_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG138_IN_SEL (BIT(7)) +#define GPIO_SIG138_IN_SEL_M (BIT(7)) +#define GPIO_SIG138_IN_SEL_V 0x1 +#define GPIO_SIG138_IN_SEL_S 7 +/* GPIO_FUNC138_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC138_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC138_IN_INV_SEL_V 0x1 +#define GPIO_FUNC138_IN_INV_SEL_S 6 +/* GPIO_FUNC138_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC138_IN_SEL 0x0000003F +#define GPIO_FUNC138_IN_SEL_M ((GPIO_FUNC138_IN_SEL_V)<<(GPIO_FUNC138_IN_SEL_S)) +#define GPIO_FUNC138_IN_SEL_V 0x3F +#define GPIO_FUNC138_IN_SEL_S 0 + +#define GPIO_FUNC139_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x380) +/* GPIO_SIG139_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG139_IN_SEL (BIT(7)) +#define GPIO_SIG139_IN_SEL_M (BIT(7)) +#define GPIO_SIG139_IN_SEL_V 0x1 +#define GPIO_SIG139_IN_SEL_S 7 +/* GPIO_FUNC139_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC139_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC139_IN_INV_SEL_V 0x1 +#define GPIO_FUNC139_IN_INV_SEL_S 6 +/* GPIO_FUNC139_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC139_IN_SEL 0x0000003F +#define GPIO_FUNC139_IN_SEL_M ((GPIO_FUNC139_IN_SEL_V)<<(GPIO_FUNC139_IN_SEL_S)) +#define GPIO_FUNC139_IN_SEL_V 0x3F +#define GPIO_FUNC139_IN_SEL_S 0 + +#define GPIO_FUNC140_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x384) +/* GPIO_SIG140_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG140_IN_SEL (BIT(7)) +#define GPIO_SIG140_IN_SEL_M (BIT(7)) +#define GPIO_SIG140_IN_SEL_V 0x1 +#define GPIO_SIG140_IN_SEL_S 7 +/* GPIO_FUNC140_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC140_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC140_IN_INV_SEL_V 0x1 +#define GPIO_FUNC140_IN_INV_SEL_S 6 +/* GPIO_FUNC140_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC140_IN_SEL 0x0000003F +#define GPIO_FUNC140_IN_SEL_M ((GPIO_FUNC140_IN_SEL_V)<<(GPIO_FUNC140_IN_SEL_S)) +#define GPIO_FUNC140_IN_SEL_V 0x3F +#define GPIO_FUNC140_IN_SEL_S 0 + +#define GPIO_FUNC141_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x388) +/* GPIO_SIG141_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG141_IN_SEL (BIT(7)) +#define GPIO_SIG141_IN_SEL_M (BIT(7)) +#define GPIO_SIG141_IN_SEL_V 0x1 +#define GPIO_SIG141_IN_SEL_S 7 +/* GPIO_FUNC141_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC141_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC141_IN_INV_SEL_V 0x1 +#define GPIO_FUNC141_IN_INV_SEL_S 6 +/* GPIO_FUNC141_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC141_IN_SEL 0x0000003F +#define GPIO_FUNC141_IN_SEL_M ((GPIO_FUNC141_IN_SEL_V)<<(GPIO_FUNC141_IN_SEL_S)) +#define GPIO_FUNC141_IN_SEL_V 0x3F +#define GPIO_FUNC141_IN_SEL_S 0 + +#define GPIO_FUNC142_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x38C) +/* GPIO_SIG142_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG142_IN_SEL (BIT(7)) +#define GPIO_SIG142_IN_SEL_M (BIT(7)) +#define GPIO_SIG142_IN_SEL_V 0x1 +#define GPIO_SIG142_IN_SEL_S 7 +/* GPIO_FUNC142_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC142_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC142_IN_INV_SEL_V 0x1 +#define GPIO_FUNC142_IN_INV_SEL_S 6 +/* GPIO_FUNC142_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC142_IN_SEL 0x0000003F +#define GPIO_FUNC142_IN_SEL_M ((GPIO_FUNC142_IN_SEL_V)<<(GPIO_FUNC142_IN_SEL_S)) +#define GPIO_FUNC142_IN_SEL_V 0x3F +#define GPIO_FUNC142_IN_SEL_S 0 + +#define GPIO_FUNC143_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x390) +/* GPIO_SIG143_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG143_IN_SEL (BIT(7)) +#define GPIO_SIG143_IN_SEL_M (BIT(7)) +#define GPIO_SIG143_IN_SEL_V 0x1 +#define GPIO_SIG143_IN_SEL_S 7 +/* GPIO_FUNC143_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC143_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC143_IN_INV_SEL_V 0x1 +#define GPIO_FUNC143_IN_INV_SEL_S 6 +/* GPIO_FUNC143_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC143_IN_SEL 0x0000003F +#define GPIO_FUNC143_IN_SEL_M ((GPIO_FUNC143_IN_SEL_V)<<(GPIO_FUNC143_IN_SEL_S)) +#define GPIO_FUNC143_IN_SEL_V 0x3F +#define GPIO_FUNC143_IN_SEL_S 0 + +#define GPIO_FUNC144_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x394) +/* GPIO_SIG144_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG144_IN_SEL (BIT(7)) +#define GPIO_SIG144_IN_SEL_M (BIT(7)) +#define GPIO_SIG144_IN_SEL_V 0x1 +#define GPIO_SIG144_IN_SEL_S 7 +/* GPIO_FUNC144_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC144_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC144_IN_INV_SEL_V 0x1 +#define GPIO_FUNC144_IN_INV_SEL_S 6 +/* GPIO_FUNC144_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC144_IN_SEL 0x0000003F +#define GPIO_FUNC144_IN_SEL_M ((GPIO_FUNC144_IN_SEL_V)<<(GPIO_FUNC144_IN_SEL_S)) +#define GPIO_FUNC144_IN_SEL_V 0x3F +#define GPIO_FUNC144_IN_SEL_S 0 + +#define GPIO_FUNC145_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x398) +/* GPIO_SIG145_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG145_IN_SEL (BIT(7)) +#define GPIO_SIG145_IN_SEL_M (BIT(7)) +#define GPIO_SIG145_IN_SEL_V 0x1 +#define GPIO_SIG145_IN_SEL_S 7 +/* GPIO_FUNC145_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC145_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC145_IN_INV_SEL_V 0x1 +#define GPIO_FUNC145_IN_INV_SEL_S 6 +/* GPIO_FUNC145_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC145_IN_SEL 0x0000003F +#define GPIO_FUNC145_IN_SEL_M ((GPIO_FUNC145_IN_SEL_V)<<(GPIO_FUNC145_IN_SEL_S)) +#define GPIO_FUNC145_IN_SEL_V 0x3F +#define GPIO_FUNC145_IN_SEL_S 0 + +#define GPIO_FUNC146_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x39C) +/* GPIO_SIG146_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG146_IN_SEL (BIT(7)) +#define GPIO_SIG146_IN_SEL_M (BIT(7)) +#define GPIO_SIG146_IN_SEL_V 0x1 +#define GPIO_SIG146_IN_SEL_S 7 +/* GPIO_FUNC146_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC146_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC146_IN_INV_SEL_V 0x1 +#define GPIO_FUNC146_IN_INV_SEL_S 6 +/* GPIO_FUNC146_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC146_IN_SEL 0x0000003F +#define GPIO_FUNC146_IN_SEL_M ((GPIO_FUNC146_IN_SEL_V)<<(GPIO_FUNC146_IN_SEL_S)) +#define GPIO_FUNC146_IN_SEL_V 0x3F +#define GPIO_FUNC146_IN_SEL_S 0 + +#define GPIO_FUNC147_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3A0) +/* GPIO_SIG147_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG147_IN_SEL (BIT(7)) +#define GPIO_SIG147_IN_SEL_M (BIT(7)) +#define GPIO_SIG147_IN_SEL_V 0x1 +#define GPIO_SIG147_IN_SEL_S 7 +/* GPIO_FUNC147_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC147_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC147_IN_INV_SEL_V 0x1 +#define GPIO_FUNC147_IN_INV_SEL_S 6 +/* GPIO_FUNC147_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC147_IN_SEL 0x0000003F +#define GPIO_FUNC147_IN_SEL_M ((GPIO_FUNC147_IN_SEL_V)<<(GPIO_FUNC147_IN_SEL_S)) +#define GPIO_FUNC147_IN_SEL_V 0x3F +#define GPIO_FUNC147_IN_SEL_S 0 + +#define GPIO_FUNC148_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3A4) +/* GPIO_SIG148_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG148_IN_SEL (BIT(7)) +#define GPIO_SIG148_IN_SEL_M (BIT(7)) +#define GPIO_SIG148_IN_SEL_V 0x1 +#define GPIO_SIG148_IN_SEL_S 7 +/* GPIO_FUNC148_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC148_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC148_IN_INV_SEL_V 0x1 +#define GPIO_FUNC148_IN_INV_SEL_S 6 +/* GPIO_FUNC148_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC148_IN_SEL 0x0000003F +#define GPIO_FUNC148_IN_SEL_M ((GPIO_FUNC148_IN_SEL_V)<<(GPIO_FUNC148_IN_SEL_S)) +#define GPIO_FUNC148_IN_SEL_V 0x3F +#define GPIO_FUNC148_IN_SEL_S 0 + +#define GPIO_FUNC149_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3A8) +/* GPIO_SIG149_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG149_IN_SEL (BIT(7)) +#define GPIO_SIG149_IN_SEL_M (BIT(7)) +#define GPIO_SIG149_IN_SEL_V 0x1 +#define GPIO_SIG149_IN_SEL_S 7 +/* GPIO_FUNC149_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC149_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC149_IN_INV_SEL_V 0x1 +#define GPIO_FUNC149_IN_INV_SEL_S 6 +/* GPIO_FUNC149_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC149_IN_SEL 0x0000003F +#define GPIO_FUNC149_IN_SEL_M ((GPIO_FUNC149_IN_SEL_V)<<(GPIO_FUNC149_IN_SEL_S)) +#define GPIO_FUNC149_IN_SEL_V 0x3F +#define GPIO_FUNC149_IN_SEL_S 0 + +#define GPIO_FUNC150_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3AC) +/* GPIO_SIG150_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG150_IN_SEL (BIT(7)) +#define GPIO_SIG150_IN_SEL_M (BIT(7)) +#define GPIO_SIG150_IN_SEL_V 0x1 +#define GPIO_SIG150_IN_SEL_S 7 +/* GPIO_FUNC150_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC150_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC150_IN_INV_SEL_V 0x1 +#define GPIO_FUNC150_IN_INV_SEL_S 6 +/* GPIO_FUNC150_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC150_IN_SEL 0x0000003F +#define GPIO_FUNC150_IN_SEL_M ((GPIO_FUNC150_IN_SEL_V)<<(GPIO_FUNC150_IN_SEL_S)) +#define GPIO_FUNC150_IN_SEL_V 0x3F +#define GPIO_FUNC150_IN_SEL_S 0 + +#define GPIO_FUNC151_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3B0) +/* GPIO_SIG151_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG151_IN_SEL (BIT(7)) +#define GPIO_SIG151_IN_SEL_M (BIT(7)) +#define GPIO_SIG151_IN_SEL_V 0x1 +#define GPIO_SIG151_IN_SEL_S 7 +/* GPIO_FUNC151_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC151_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC151_IN_INV_SEL_V 0x1 +#define GPIO_FUNC151_IN_INV_SEL_S 6 +/* GPIO_FUNC151_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC151_IN_SEL 0x0000003F +#define GPIO_FUNC151_IN_SEL_M ((GPIO_FUNC151_IN_SEL_V)<<(GPIO_FUNC151_IN_SEL_S)) +#define GPIO_FUNC151_IN_SEL_V 0x3F +#define GPIO_FUNC151_IN_SEL_S 0 + +#define GPIO_FUNC152_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3B4) +/* GPIO_SIG152_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG152_IN_SEL (BIT(7)) +#define GPIO_SIG152_IN_SEL_M (BIT(7)) +#define GPIO_SIG152_IN_SEL_V 0x1 +#define GPIO_SIG152_IN_SEL_S 7 +/* GPIO_FUNC152_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC152_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC152_IN_INV_SEL_V 0x1 +#define GPIO_FUNC152_IN_INV_SEL_S 6 +/* GPIO_FUNC152_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC152_IN_SEL 0x0000003F +#define GPIO_FUNC152_IN_SEL_M ((GPIO_FUNC152_IN_SEL_V)<<(GPIO_FUNC152_IN_SEL_S)) +#define GPIO_FUNC152_IN_SEL_V 0x3F +#define GPIO_FUNC152_IN_SEL_S 0 + +#define GPIO_FUNC153_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3B8) +/* GPIO_SIG153_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG153_IN_SEL (BIT(7)) +#define GPIO_SIG153_IN_SEL_M (BIT(7)) +#define GPIO_SIG153_IN_SEL_V 0x1 +#define GPIO_SIG153_IN_SEL_S 7 +/* GPIO_FUNC153_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC153_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC153_IN_INV_SEL_V 0x1 +#define GPIO_FUNC153_IN_INV_SEL_S 6 +/* GPIO_FUNC153_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC153_IN_SEL 0x0000003F +#define GPIO_FUNC153_IN_SEL_M ((GPIO_FUNC153_IN_SEL_V)<<(GPIO_FUNC153_IN_SEL_S)) +#define GPIO_FUNC153_IN_SEL_V 0x3F +#define GPIO_FUNC153_IN_SEL_S 0 + +#define GPIO_FUNC154_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3BC) +/* GPIO_SIG154_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG154_IN_SEL (BIT(7)) +#define GPIO_SIG154_IN_SEL_M (BIT(7)) +#define GPIO_SIG154_IN_SEL_V 0x1 +#define GPIO_SIG154_IN_SEL_S 7 +/* GPIO_FUNC154_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC154_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC154_IN_INV_SEL_V 0x1 +#define GPIO_FUNC154_IN_INV_SEL_S 6 +/* GPIO_FUNC154_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC154_IN_SEL 0x0000003F +#define GPIO_FUNC154_IN_SEL_M ((GPIO_FUNC154_IN_SEL_V)<<(GPIO_FUNC154_IN_SEL_S)) +#define GPIO_FUNC154_IN_SEL_V 0x3F +#define GPIO_FUNC154_IN_SEL_S 0 + +#define GPIO_FUNC155_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3C0) +/* GPIO_SIG155_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG155_IN_SEL (BIT(7)) +#define GPIO_SIG155_IN_SEL_M (BIT(7)) +#define GPIO_SIG155_IN_SEL_V 0x1 +#define GPIO_SIG155_IN_SEL_S 7 +/* GPIO_FUNC155_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC155_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC155_IN_INV_SEL_V 0x1 +#define GPIO_FUNC155_IN_INV_SEL_S 6 +/* GPIO_FUNC155_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC155_IN_SEL 0x0000003F +#define GPIO_FUNC155_IN_SEL_M ((GPIO_FUNC155_IN_SEL_V)<<(GPIO_FUNC155_IN_SEL_S)) +#define GPIO_FUNC155_IN_SEL_V 0x3F +#define GPIO_FUNC155_IN_SEL_S 0 + +#define GPIO_FUNC156_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3C4) +/* GPIO_SIG156_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG156_IN_SEL (BIT(7)) +#define GPIO_SIG156_IN_SEL_M (BIT(7)) +#define GPIO_SIG156_IN_SEL_V 0x1 +#define GPIO_SIG156_IN_SEL_S 7 +/* GPIO_FUNC156_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC156_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC156_IN_INV_SEL_V 0x1 +#define GPIO_FUNC156_IN_INV_SEL_S 6 +/* GPIO_FUNC156_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC156_IN_SEL 0x0000003F +#define GPIO_FUNC156_IN_SEL_M ((GPIO_FUNC156_IN_SEL_V)<<(GPIO_FUNC156_IN_SEL_S)) +#define GPIO_FUNC156_IN_SEL_V 0x3F +#define GPIO_FUNC156_IN_SEL_S 0 + +#define GPIO_FUNC157_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3C8) +/* GPIO_SIG157_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG157_IN_SEL (BIT(7)) +#define GPIO_SIG157_IN_SEL_M (BIT(7)) +#define GPIO_SIG157_IN_SEL_V 0x1 +#define GPIO_SIG157_IN_SEL_S 7 +/* GPIO_FUNC157_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC157_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC157_IN_INV_SEL_V 0x1 +#define GPIO_FUNC157_IN_INV_SEL_S 6 +/* GPIO_FUNC157_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC157_IN_SEL 0x0000003F +#define GPIO_FUNC157_IN_SEL_M ((GPIO_FUNC157_IN_SEL_V)<<(GPIO_FUNC157_IN_SEL_S)) +#define GPIO_FUNC157_IN_SEL_V 0x3F +#define GPIO_FUNC157_IN_SEL_S 0 + +#define GPIO_FUNC158_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3CC) +/* GPIO_SIG158_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG158_IN_SEL (BIT(7)) +#define GPIO_SIG158_IN_SEL_M (BIT(7)) +#define GPIO_SIG158_IN_SEL_V 0x1 +#define GPIO_SIG158_IN_SEL_S 7 +/* GPIO_FUNC158_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC158_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC158_IN_INV_SEL_V 0x1 +#define GPIO_FUNC158_IN_INV_SEL_S 6 +/* GPIO_FUNC158_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC158_IN_SEL 0x0000003F +#define GPIO_FUNC158_IN_SEL_M ((GPIO_FUNC158_IN_SEL_V)<<(GPIO_FUNC158_IN_SEL_S)) +#define GPIO_FUNC158_IN_SEL_V 0x3F +#define GPIO_FUNC158_IN_SEL_S 0 + +#define GPIO_FUNC159_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3D0) +/* GPIO_SIG159_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG159_IN_SEL (BIT(7)) +#define GPIO_SIG159_IN_SEL_M (BIT(7)) +#define GPIO_SIG159_IN_SEL_V 0x1 +#define GPIO_SIG159_IN_SEL_S 7 +/* GPIO_FUNC159_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC159_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC159_IN_INV_SEL_V 0x1 +#define GPIO_FUNC159_IN_INV_SEL_S 6 +/* GPIO_FUNC159_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC159_IN_SEL 0x0000003F +#define GPIO_FUNC159_IN_SEL_M ((GPIO_FUNC159_IN_SEL_V)<<(GPIO_FUNC159_IN_SEL_S)) +#define GPIO_FUNC159_IN_SEL_V 0x3F +#define GPIO_FUNC159_IN_SEL_S 0 + +#define GPIO_FUNC160_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3D4) +/* GPIO_SIG160_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG160_IN_SEL (BIT(7)) +#define GPIO_SIG160_IN_SEL_M (BIT(7)) +#define GPIO_SIG160_IN_SEL_V 0x1 +#define GPIO_SIG160_IN_SEL_S 7 +/* GPIO_FUNC160_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC160_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC160_IN_INV_SEL_V 0x1 +#define GPIO_FUNC160_IN_INV_SEL_S 6 +/* GPIO_FUNC160_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC160_IN_SEL 0x0000003F +#define GPIO_FUNC160_IN_SEL_M ((GPIO_FUNC160_IN_SEL_V)<<(GPIO_FUNC160_IN_SEL_S)) +#define GPIO_FUNC160_IN_SEL_V 0x3F +#define GPIO_FUNC160_IN_SEL_S 0 + +#define GPIO_FUNC161_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3D8) +/* GPIO_SIG161_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG161_IN_SEL (BIT(7)) +#define GPIO_SIG161_IN_SEL_M (BIT(7)) +#define GPIO_SIG161_IN_SEL_V 0x1 +#define GPIO_SIG161_IN_SEL_S 7 +/* GPIO_FUNC161_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC161_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC161_IN_INV_SEL_V 0x1 +#define GPIO_FUNC161_IN_INV_SEL_S 6 +/* GPIO_FUNC161_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC161_IN_SEL 0x0000003F +#define GPIO_FUNC161_IN_SEL_M ((GPIO_FUNC161_IN_SEL_V)<<(GPIO_FUNC161_IN_SEL_S)) +#define GPIO_FUNC161_IN_SEL_V 0x3F +#define GPIO_FUNC161_IN_SEL_S 0 + +#define GPIO_FUNC162_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3DC) +/* GPIO_SIG162_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG162_IN_SEL (BIT(7)) +#define GPIO_SIG162_IN_SEL_M (BIT(7)) +#define GPIO_SIG162_IN_SEL_V 0x1 +#define GPIO_SIG162_IN_SEL_S 7 +/* GPIO_FUNC162_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC162_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC162_IN_INV_SEL_V 0x1 +#define GPIO_FUNC162_IN_INV_SEL_S 6 +/* GPIO_FUNC162_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC162_IN_SEL 0x0000003F +#define GPIO_FUNC162_IN_SEL_M ((GPIO_FUNC162_IN_SEL_V)<<(GPIO_FUNC162_IN_SEL_S)) +#define GPIO_FUNC162_IN_SEL_V 0x3F +#define GPIO_FUNC162_IN_SEL_S 0 + +#define GPIO_FUNC163_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3E0) +/* GPIO_SIG163_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG163_IN_SEL (BIT(7)) +#define GPIO_SIG163_IN_SEL_M (BIT(7)) +#define GPIO_SIG163_IN_SEL_V 0x1 +#define GPIO_SIG163_IN_SEL_S 7 +/* GPIO_FUNC163_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC163_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC163_IN_INV_SEL_V 0x1 +#define GPIO_FUNC163_IN_INV_SEL_S 6 +/* GPIO_FUNC163_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC163_IN_SEL 0x0000003F +#define GPIO_FUNC163_IN_SEL_M ((GPIO_FUNC163_IN_SEL_V)<<(GPIO_FUNC163_IN_SEL_S)) +#define GPIO_FUNC163_IN_SEL_V 0x3F +#define GPIO_FUNC163_IN_SEL_S 0 + +#define GPIO_FUNC164_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3E4) +/* GPIO_SIG164_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG164_IN_SEL (BIT(7)) +#define GPIO_SIG164_IN_SEL_M (BIT(7)) +#define GPIO_SIG164_IN_SEL_V 0x1 +#define GPIO_SIG164_IN_SEL_S 7 +/* GPIO_FUNC164_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC164_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC164_IN_INV_SEL_V 0x1 +#define GPIO_FUNC164_IN_INV_SEL_S 6 +/* GPIO_FUNC164_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC164_IN_SEL 0x0000003F +#define GPIO_FUNC164_IN_SEL_M ((GPIO_FUNC164_IN_SEL_V)<<(GPIO_FUNC164_IN_SEL_S)) +#define GPIO_FUNC164_IN_SEL_V 0x3F +#define GPIO_FUNC164_IN_SEL_S 0 + +#define GPIO_FUNC165_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3E8) +/* GPIO_SIG165_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG165_IN_SEL (BIT(7)) +#define GPIO_SIG165_IN_SEL_M (BIT(7)) +#define GPIO_SIG165_IN_SEL_V 0x1 +#define GPIO_SIG165_IN_SEL_S 7 +/* GPIO_FUNC165_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC165_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC165_IN_INV_SEL_V 0x1 +#define GPIO_FUNC165_IN_INV_SEL_S 6 +/* GPIO_FUNC165_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC165_IN_SEL 0x0000003F +#define GPIO_FUNC165_IN_SEL_M ((GPIO_FUNC165_IN_SEL_V)<<(GPIO_FUNC165_IN_SEL_S)) +#define GPIO_FUNC165_IN_SEL_V 0x3F +#define GPIO_FUNC165_IN_SEL_S 0 + +#define GPIO_FUNC166_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3EC) +/* GPIO_SIG166_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG166_IN_SEL (BIT(7)) +#define GPIO_SIG166_IN_SEL_M (BIT(7)) +#define GPIO_SIG166_IN_SEL_V 0x1 +#define GPIO_SIG166_IN_SEL_S 7 +/* GPIO_FUNC166_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC166_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC166_IN_INV_SEL_V 0x1 +#define GPIO_FUNC166_IN_INV_SEL_S 6 +/* GPIO_FUNC166_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC166_IN_SEL 0x0000003F +#define GPIO_FUNC166_IN_SEL_M ((GPIO_FUNC166_IN_SEL_V)<<(GPIO_FUNC166_IN_SEL_S)) +#define GPIO_FUNC166_IN_SEL_V 0x3F +#define GPIO_FUNC166_IN_SEL_S 0 + +#define GPIO_FUNC167_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3F0) +/* GPIO_SIG167_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG167_IN_SEL (BIT(7)) +#define GPIO_SIG167_IN_SEL_M (BIT(7)) +#define GPIO_SIG167_IN_SEL_V 0x1 +#define GPIO_SIG167_IN_SEL_S 7 +/* GPIO_FUNC167_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC167_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC167_IN_INV_SEL_V 0x1 +#define GPIO_FUNC167_IN_INV_SEL_S 6 +/* GPIO_FUNC167_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC167_IN_SEL 0x0000003F +#define GPIO_FUNC167_IN_SEL_M ((GPIO_FUNC167_IN_SEL_V)<<(GPIO_FUNC167_IN_SEL_S)) +#define GPIO_FUNC167_IN_SEL_V 0x3F +#define GPIO_FUNC167_IN_SEL_S 0 + +#define GPIO_FUNC168_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3F4) +/* GPIO_SIG168_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG168_IN_SEL (BIT(7)) +#define GPIO_SIG168_IN_SEL_M (BIT(7)) +#define GPIO_SIG168_IN_SEL_V 0x1 +#define GPIO_SIG168_IN_SEL_S 7 +/* GPIO_FUNC168_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC168_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC168_IN_INV_SEL_V 0x1 +#define GPIO_FUNC168_IN_INV_SEL_S 6 +/* GPIO_FUNC168_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC168_IN_SEL 0x0000003F +#define GPIO_FUNC168_IN_SEL_M ((GPIO_FUNC168_IN_SEL_V)<<(GPIO_FUNC168_IN_SEL_S)) +#define GPIO_FUNC168_IN_SEL_V 0x3F +#define GPIO_FUNC168_IN_SEL_S 0 + +#define GPIO_FUNC169_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3F8) +/* GPIO_SIG169_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG169_IN_SEL (BIT(7)) +#define GPIO_SIG169_IN_SEL_M (BIT(7)) +#define GPIO_SIG169_IN_SEL_V 0x1 +#define GPIO_SIG169_IN_SEL_S 7 +/* GPIO_FUNC169_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC169_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC169_IN_INV_SEL_V 0x1 +#define GPIO_FUNC169_IN_INV_SEL_S 6 +/* GPIO_FUNC169_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC169_IN_SEL 0x0000003F +#define GPIO_FUNC169_IN_SEL_M ((GPIO_FUNC169_IN_SEL_V)<<(GPIO_FUNC169_IN_SEL_S)) +#define GPIO_FUNC169_IN_SEL_V 0x3F +#define GPIO_FUNC169_IN_SEL_S 0 + +#define GPIO_FUNC170_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x3FC) +/* GPIO_SIG170_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG170_IN_SEL (BIT(7)) +#define GPIO_SIG170_IN_SEL_M (BIT(7)) +#define GPIO_SIG170_IN_SEL_V 0x1 +#define GPIO_SIG170_IN_SEL_S 7 +/* GPIO_FUNC170_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC170_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC170_IN_INV_SEL_V 0x1 +#define GPIO_FUNC170_IN_INV_SEL_S 6 +/* GPIO_FUNC170_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC170_IN_SEL 0x0000003F +#define GPIO_FUNC170_IN_SEL_M ((GPIO_FUNC170_IN_SEL_V)<<(GPIO_FUNC170_IN_SEL_S)) +#define GPIO_FUNC170_IN_SEL_V 0x3F +#define GPIO_FUNC170_IN_SEL_S 0 + +#define GPIO_FUNC171_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x400) +/* GPIO_SIG171_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG171_IN_SEL (BIT(7)) +#define GPIO_SIG171_IN_SEL_M (BIT(7)) +#define GPIO_SIG171_IN_SEL_V 0x1 +#define GPIO_SIG171_IN_SEL_S 7 +/* GPIO_FUNC171_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC171_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC171_IN_INV_SEL_V 0x1 +#define GPIO_FUNC171_IN_INV_SEL_S 6 +/* GPIO_FUNC171_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC171_IN_SEL 0x0000003F +#define GPIO_FUNC171_IN_SEL_M ((GPIO_FUNC171_IN_SEL_V)<<(GPIO_FUNC171_IN_SEL_S)) +#define GPIO_FUNC171_IN_SEL_V 0x3F +#define GPIO_FUNC171_IN_SEL_S 0 + +#define GPIO_FUNC172_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x404) +/* GPIO_SIG172_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG172_IN_SEL (BIT(7)) +#define GPIO_SIG172_IN_SEL_M (BIT(7)) +#define GPIO_SIG172_IN_SEL_V 0x1 +#define GPIO_SIG172_IN_SEL_S 7 +/* GPIO_FUNC172_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC172_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC172_IN_INV_SEL_V 0x1 +#define GPIO_FUNC172_IN_INV_SEL_S 6 +/* GPIO_FUNC172_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC172_IN_SEL 0x0000003F +#define GPIO_FUNC172_IN_SEL_M ((GPIO_FUNC172_IN_SEL_V)<<(GPIO_FUNC172_IN_SEL_S)) +#define GPIO_FUNC172_IN_SEL_V 0x3F +#define GPIO_FUNC172_IN_SEL_S 0 + +#define GPIO_FUNC173_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x408) +/* GPIO_SIG173_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG173_IN_SEL (BIT(7)) +#define GPIO_SIG173_IN_SEL_M (BIT(7)) +#define GPIO_SIG173_IN_SEL_V 0x1 +#define GPIO_SIG173_IN_SEL_S 7 +/* GPIO_FUNC173_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC173_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC173_IN_INV_SEL_V 0x1 +#define GPIO_FUNC173_IN_INV_SEL_S 6 +/* GPIO_FUNC173_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC173_IN_SEL 0x0000003F +#define GPIO_FUNC173_IN_SEL_M ((GPIO_FUNC173_IN_SEL_V)<<(GPIO_FUNC173_IN_SEL_S)) +#define GPIO_FUNC173_IN_SEL_V 0x3F +#define GPIO_FUNC173_IN_SEL_S 0 + +#define GPIO_FUNC174_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x40C) +/* GPIO_SIG174_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG174_IN_SEL (BIT(7)) +#define GPIO_SIG174_IN_SEL_M (BIT(7)) +#define GPIO_SIG174_IN_SEL_V 0x1 +#define GPIO_SIG174_IN_SEL_S 7 +/* GPIO_FUNC174_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC174_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC174_IN_INV_SEL_V 0x1 +#define GPIO_FUNC174_IN_INV_SEL_S 6 +/* GPIO_FUNC174_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC174_IN_SEL 0x0000003F +#define GPIO_FUNC174_IN_SEL_M ((GPIO_FUNC174_IN_SEL_V)<<(GPIO_FUNC174_IN_SEL_S)) +#define GPIO_FUNC174_IN_SEL_V 0x3F +#define GPIO_FUNC174_IN_SEL_S 0 + +#define GPIO_FUNC175_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x410) +/* GPIO_SIG175_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG175_IN_SEL (BIT(7)) +#define GPIO_SIG175_IN_SEL_M (BIT(7)) +#define GPIO_SIG175_IN_SEL_V 0x1 +#define GPIO_SIG175_IN_SEL_S 7 +/* GPIO_FUNC175_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC175_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC175_IN_INV_SEL_V 0x1 +#define GPIO_FUNC175_IN_INV_SEL_S 6 +/* GPIO_FUNC175_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC175_IN_SEL 0x0000003F +#define GPIO_FUNC175_IN_SEL_M ((GPIO_FUNC175_IN_SEL_V)<<(GPIO_FUNC175_IN_SEL_S)) +#define GPIO_FUNC175_IN_SEL_V 0x3F +#define GPIO_FUNC175_IN_SEL_S 0 + +#define GPIO_FUNC176_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x414) +/* GPIO_SIG176_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG176_IN_SEL (BIT(7)) +#define GPIO_SIG176_IN_SEL_M (BIT(7)) +#define GPIO_SIG176_IN_SEL_V 0x1 +#define GPIO_SIG176_IN_SEL_S 7 +/* GPIO_FUNC176_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC176_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC176_IN_INV_SEL_V 0x1 +#define GPIO_FUNC176_IN_INV_SEL_S 6 +/* GPIO_FUNC176_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC176_IN_SEL 0x0000003F +#define GPIO_FUNC176_IN_SEL_M ((GPIO_FUNC176_IN_SEL_V)<<(GPIO_FUNC176_IN_SEL_S)) +#define GPIO_FUNC176_IN_SEL_V 0x3F +#define GPIO_FUNC176_IN_SEL_S 0 + +#define GPIO_FUNC177_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x418) +/* GPIO_SIG177_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG177_IN_SEL (BIT(7)) +#define GPIO_SIG177_IN_SEL_M (BIT(7)) +#define GPIO_SIG177_IN_SEL_V 0x1 +#define GPIO_SIG177_IN_SEL_S 7 +/* GPIO_FUNC177_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC177_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC177_IN_INV_SEL_V 0x1 +#define GPIO_FUNC177_IN_INV_SEL_S 6 +/* GPIO_FUNC177_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC177_IN_SEL 0x0000003F +#define GPIO_FUNC177_IN_SEL_M ((GPIO_FUNC177_IN_SEL_V)<<(GPIO_FUNC177_IN_SEL_S)) +#define GPIO_FUNC177_IN_SEL_V 0x3F +#define GPIO_FUNC177_IN_SEL_S 0 + +#define GPIO_FUNC178_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x41C) +/* GPIO_SIG178_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG178_IN_SEL (BIT(7)) +#define GPIO_SIG178_IN_SEL_M (BIT(7)) +#define GPIO_SIG178_IN_SEL_V 0x1 +#define GPIO_SIG178_IN_SEL_S 7 +/* GPIO_FUNC178_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC178_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC178_IN_INV_SEL_V 0x1 +#define GPIO_FUNC178_IN_INV_SEL_S 6 +/* GPIO_FUNC178_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC178_IN_SEL 0x0000003F +#define GPIO_FUNC178_IN_SEL_M ((GPIO_FUNC178_IN_SEL_V)<<(GPIO_FUNC178_IN_SEL_S)) +#define GPIO_FUNC178_IN_SEL_V 0x3F +#define GPIO_FUNC178_IN_SEL_S 0 + +#define GPIO_FUNC179_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x420) +/* GPIO_SIG179_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG179_IN_SEL (BIT(7)) +#define GPIO_SIG179_IN_SEL_M (BIT(7)) +#define GPIO_SIG179_IN_SEL_V 0x1 +#define GPIO_SIG179_IN_SEL_S 7 +/* GPIO_FUNC179_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC179_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC179_IN_INV_SEL_V 0x1 +#define GPIO_FUNC179_IN_INV_SEL_S 6 +/* GPIO_FUNC179_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC179_IN_SEL 0x0000003F +#define GPIO_FUNC179_IN_SEL_M ((GPIO_FUNC179_IN_SEL_V)<<(GPIO_FUNC179_IN_SEL_S)) +#define GPIO_FUNC179_IN_SEL_V 0x3F +#define GPIO_FUNC179_IN_SEL_S 0 + +#define GPIO_FUNC180_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x424) +/* GPIO_SIG180_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG180_IN_SEL (BIT(7)) +#define GPIO_SIG180_IN_SEL_M (BIT(7)) +#define GPIO_SIG180_IN_SEL_V 0x1 +#define GPIO_SIG180_IN_SEL_S 7 +/* GPIO_FUNC180_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC180_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC180_IN_INV_SEL_V 0x1 +#define GPIO_FUNC180_IN_INV_SEL_S 6 +/* GPIO_FUNC180_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC180_IN_SEL 0x0000003F +#define GPIO_FUNC180_IN_SEL_M ((GPIO_FUNC180_IN_SEL_V)<<(GPIO_FUNC180_IN_SEL_S)) +#define GPIO_FUNC180_IN_SEL_V 0x3F +#define GPIO_FUNC180_IN_SEL_S 0 + +#define GPIO_FUNC181_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x428) +/* GPIO_SIG181_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG181_IN_SEL (BIT(7)) +#define GPIO_SIG181_IN_SEL_M (BIT(7)) +#define GPIO_SIG181_IN_SEL_V 0x1 +#define GPIO_SIG181_IN_SEL_S 7 +/* GPIO_FUNC181_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC181_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC181_IN_INV_SEL_V 0x1 +#define GPIO_FUNC181_IN_INV_SEL_S 6 +/* GPIO_FUNC181_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC181_IN_SEL 0x0000003F +#define GPIO_FUNC181_IN_SEL_M ((GPIO_FUNC181_IN_SEL_V)<<(GPIO_FUNC181_IN_SEL_S)) +#define GPIO_FUNC181_IN_SEL_V 0x3F +#define GPIO_FUNC181_IN_SEL_S 0 + +#define GPIO_FUNC182_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x42C) +/* GPIO_SIG182_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG182_IN_SEL (BIT(7)) +#define GPIO_SIG182_IN_SEL_M (BIT(7)) +#define GPIO_SIG182_IN_SEL_V 0x1 +#define GPIO_SIG182_IN_SEL_S 7 +/* GPIO_FUNC182_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC182_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC182_IN_INV_SEL_V 0x1 +#define GPIO_FUNC182_IN_INV_SEL_S 6 +/* GPIO_FUNC182_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC182_IN_SEL 0x0000003F +#define GPIO_FUNC182_IN_SEL_M ((GPIO_FUNC182_IN_SEL_V)<<(GPIO_FUNC182_IN_SEL_S)) +#define GPIO_FUNC182_IN_SEL_V 0x3F +#define GPIO_FUNC182_IN_SEL_S 0 + +#define GPIO_FUNC183_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x430) +/* GPIO_SIG183_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG183_IN_SEL (BIT(7)) +#define GPIO_SIG183_IN_SEL_M (BIT(7)) +#define GPIO_SIG183_IN_SEL_V 0x1 +#define GPIO_SIG183_IN_SEL_S 7 +/* GPIO_FUNC183_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC183_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC183_IN_INV_SEL_V 0x1 +#define GPIO_FUNC183_IN_INV_SEL_S 6 +/* GPIO_FUNC183_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC183_IN_SEL 0x0000003F +#define GPIO_FUNC183_IN_SEL_M ((GPIO_FUNC183_IN_SEL_V)<<(GPIO_FUNC183_IN_SEL_S)) +#define GPIO_FUNC183_IN_SEL_V 0x3F +#define GPIO_FUNC183_IN_SEL_S 0 + +#define GPIO_FUNC184_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x434) +/* GPIO_SIG184_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG184_IN_SEL (BIT(7)) +#define GPIO_SIG184_IN_SEL_M (BIT(7)) +#define GPIO_SIG184_IN_SEL_V 0x1 +#define GPIO_SIG184_IN_SEL_S 7 +/* GPIO_FUNC184_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC184_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC184_IN_INV_SEL_V 0x1 +#define GPIO_FUNC184_IN_INV_SEL_S 6 +/* GPIO_FUNC184_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC184_IN_SEL 0x0000003F +#define GPIO_FUNC184_IN_SEL_M ((GPIO_FUNC184_IN_SEL_V)<<(GPIO_FUNC184_IN_SEL_S)) +#define GPIO_FUNC184_IN_SEL_V 0x3F +#define GPIO_FUNC184_IN_SEL_S 0 + +#define GPIO_FUNC185_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x438) +/* GPIO_SIG185_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG185_IN_SEL (BIT(7)) +#define GPIO_SIG185_IN_SEL_M (BIT(7)) +#define GPIO_SIG185_IN_SEL_V 0x1 +#define GPIO_SIG185_IN_SEL_S 7 +/* GPIO_FUNC185_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC185_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC185_IN_INV_SEL_V 0x1 +#define GPIO_FUNC185_IN_INV_SEL_S 6 +/* GPIO_FUNC185_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC185_IN_SEL 0x0000003F +#define GPIO_FUNC185_IN_SEL_M ((GPIO_FUNC185_IN_SEL_V)<<(GPIO_FUNC185_IN_SEL_S)) +#define GPIO_FUNC185_IN_SEL_V 0x3F +#define GPIO_FUNC185_IN_SEL_S 0 + +#define GPIO_FUNC186_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x43C) +/* GPIO_SIG186_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG186_IN_SEL (BIT(7)) +#define GPIO_SIG186_IN_SEL_M (BIT(7)) +#define GPIO_SIG186_IN_SEL_V 0x1 +#define GPIO_SIG186_IN_SEL_S 7 +/* GPIO_FUNC186_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC186_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC186_IN_INV_SEL_V 0x1 +#define GPIO_FUNC186_IN_INV_SEL_S 6 +/* GPIO_FUNC186_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC186_IN_SEL 0x0000003F +#define GPIO_FUNC186_IN_SEL_M ((GPIO_FUNC186_IN_SEL_V)<<(GPIO_FUNC186_IN_SEL_S)) +#define GPIO_FUNC186_IN_SEL_V 0x3F +#define GPIO_FUNC186_IN_SEL_S 0 + +#define GPIO_FUNC187_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x440) +/* GPIO_SIG187_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG187_IN_SEL (BIT(7)) +#define GPIO_SIG187_IN_SEL_M (BIT(7)) +#define GPIO_SIG187_IN_SEL_V 0x1 +#define GPIO_SIG187_IN_SEL_S 7 +/* GPIO_FUNC187_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC187_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC187_IN_INV_SEL_V 0x1 +#define GPIO_FUNC187_IN_INV_SEL_S 6 +/* GPIO_FUNC187_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC187_IN_SEL 0x0000003F +#define GPIO_FUNC187_IN_SEL_M ((GPIO_FUNC187_IN_SEL_V)<<(GPIO_FUNC187_IN_SEL_S)) +#define GPIO_FUNC187_IN_SEL_V 0x3F +#define GPIO_FUNC187_IN_SEL_S 0 + +#define GPIO_FUNC188_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x444) +/* GPIO_SIG188_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG188_IN_SEL (BIT(7)) +#define GPIO_SIG188_IN_SEL_M (BIT(7)) +#define GPIO_SIG188_IN_SEL_V 0x1 +#define GPIO_SIG188_IN_SEL_S 7 +/* GPIO_FUNC188_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC188_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC188_IN_INV_SEL_V 0x1 +#define GPIO_FUNC188_IN_INV_SEL_S 6 +/* GPIO_FUNC188_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC188_IN_SEL 0x0000003F +#define GPIO_FUNC188_IN_SEL_M ((GPIO_FUNC188_IN_SEL_V)<<(GPIO_FUNC188_IN_SEL_S)) +#define GPIO_FUNC188_IN_SEL_V 0x3F +#define GPIO_FUNC188_IN_SEL_S 0 + +#define GPIO_FUNC189_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x448) +/* GPIO_SIG189_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG189_IN_SEL (BIT(7)) +#define GPIO_SIG189_IN_SEL_M (BIT(7)) +#define GPIO_SIG189_IN_SEL_V 0x1 +#define GPIO_SIG189_IN_SEL_S 7 +/* GPIO_FUNC189_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC189_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC189_IN_INV_SEL_V 0x1 +#define GPIO_FUNC189_IN_INV_SEL_S 6 +/* GPIO_FUNC189_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC189_IN_SEL 0x0000003F +#define GPIO_FUNC189_IN_SEL_M ((GPIO_FUNC189_IN_SEL_V)<<(GPIO_FUNC189_IN_SEL_S)) +#define GPIO_FUNC189_IN_SEL_V 0x3F +#define GPIO_FUNC189_IN_SEL_S 0 + +#define GPIO_FUNC190_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x44C) +/* GPIO_SIG190_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG190_IN_SEL (BIT(7)) +#define GPIO_SIG190_IN_SEL_M (BIT(7)) +#define GPIO_SIG190_IN_SEL_V 0x1 +#define GPIO_SIG190_IN_SEL_S 7 +/* GPIO_FUNC190_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC190_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC190_IN_INV_SEL_V 0x1 +#define GPIO_FUNC190_IN_INV_SEL_S 6 +/* GPIO_FUNC190_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC190_IN_SEL 0x0000003F +#define GPIO_FUNC190_IN_SEL_M ((GPIO_FUNC190_IN_SEL_V)<<(GPIO_FUNC190_IN_SEL_S)) +#define GPIO_FUNC190_IN_SEL_V 0x3F +#define GPIO_FUNC190_IN_SEL_S 0 + +#define GPIO_FUNC191_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x450) +/* GPIO_SIG191_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG191_IN_SEL (BIT(7)) +#define GPIO_SIG191_IN_SEL_M (BIT(7)) +#define GPIO_SIG191_IN_SEL_V 0x1 +#define GPIO_SIG191_IN_SEL_S 7 +/* GPIO_FUNC191_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC191_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC191_IN_INV_SEL_V 0x1 +#define GPIO_FUNC191_IN_INV_SEL_S 6 +/* GPIO_FUNC191_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC191_IN_SEL 0x0000003F +#define GPIO_FUNC191_IN_SEL_M ((GPIO_FUNC191_IN_SEL_V)<<(GPIO_FUNC191_IN_SEL_S)) +#define GPIO_FUNC191_IN_SEL_V 0x3F +#define GPIO_FUNC191_IN_SEL_S 0 + +#define GPIO_FUNC192_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x454) +/* GPIO_SIG192_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG192_IN_SEL (BIT(7)) +#define GPIO_SIG192_IN_SEL_M (BIT(7)) +#define GPIO_SIG192_IN_SEL_V 0x1 +#define GPIO_SIG192_IN_SEL_S 7 +/* GPIO_FUNC192_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC192_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC192_IN_INV_SEL_V 0x1 +#define GPIO_FUNC192_IN_INV_SEL_S 6 +/* GPIO_FUNC192_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC192_IN_SEL 0x0000003F +#define GPIO_FUNC192_IN_SEL_M ((GPIO_FUNC192_IN_SEL_V)<<(GPIO_FUNC192_IN_SEL_S)) +#define GPIO_FUNC192_IN_SEL_V 0x3F +#define GPIO_FUNC192_IN_SEL_S 0 + +#define GPIO_FUNC193_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x458) +/* GPIO_SIG193_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG193_IN_SEL (BIT(7)) +#define GPIO_SIG193_IN_SEL_M (BIT(7)) +#define GPIO_SIG193_IN_SEL_V 0x1 +#define GPIO_SIG193_IN_SEL_S 7 +/* GPIO_FUNC193_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC193_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC193_IN_INV_SEL_V 0x1 +#define GPIO_FUNC193_IN_INV_SEL_S 6 +/* GPIO_FUNC193_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC193_IN_SEL 0x0000003F +#define GPIO_FUNC193_IN_SEL_M ((GPIO_FUNC193_IN_SEL_V)<<(GPIO_FUNC193_IN_SEL_S)) +#define GPIO_FUNC193_IN_SEL_V 0x3F +#define GPIO_FUNC193_IN_SEL_S 0 + +#define GPIO_FUNC194_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x45C) +/* GPIO_SIG194_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG194_IN_SEL (BIT(7)) +#define GPIO_SIG194_IN_SEL_M (BIT(7)) +#define GPIO_SIG194_IN_SEL_V 0x1 +#define GPIO_SIG194_IN_SEL_S 7 +/* GPIO_FUNC194_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC194_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC194_IN_INV_SEL_V 0x1 +#define GPIO_FUNC194_IN_INV_SEL_S 6 +/* GPIO_FUNC194_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC194_IN_SEL 0x0000003F +#define GPIO_FUNC194_IN_SEL_M ((GPIO_FUNC194_IN_SEL_V)<<(GPIO_FUNC194_IN_SEL_S)) +#define GPIO_FUNC194_IN_SEL_V 0x3F +#define GPIO_FUNC194_IN_SEL_S 0 + +#define GPIO_FUNC195_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x460) +/* GPIO_SIG195_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG195_IN_SEL (BIT(7)) +#define GPIO_SIG195_IN_SEL_M (BIT(7)) +#define GPIO_SIG195_IN_SEL_V 0x1 +#define GPIO_SIG195_IN_SEL_S 7 +/* GPIO_FUNC195_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC195_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC195_IN_INV_SEL_V 0x1 +#define GPIO_FUNC195_IN_INV_SEL_S 6 +/* GPIO_FUNC195_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC195_IN_SEL 0x0000003F +#define GPIO_FUNC195_IN_SEL_M ((GPIO_FUNC195_IN_SEL_V)<<(GPIO_FUNC195_IN_SEL_S)) +#define GPIO_FUNC195_IN_SEL_V 0x3F +#define GPIO_FUNC195_IN_SEL_S 0 + +#define GPIO_FUNC196_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x464) +/* GPIO_SIG196_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG196_IN_SEL (BIT(7)) +#define GPIO_SIG196_IN_SEL_M (BIT(7)) +#define GPIO_SIG196_IN_SEL_V 0x1 +#define GPIO_SIG196_IN_SEL_S 7 +/* GPIO_FUNC196_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC196_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC196_IN_INV_SEL_V 0x1 +#define GPIO_FUNC196_IN_INV_SEL_S 6 +/* GPIO_FUNC196_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC196_IN_SEL 0x0000003F +#define GPIO_FUNC196_IN_SEL_M ((GPIO_FUNC196_IN_SEL_V)<<(GPIO_FUNC196_IN_SEL_S)) +#define GPIO_FUNC196_IN_SEL_V 0x3F +#define GPIO_FUNC196_IN_SEL_S 0 + +#define GPIO_FUNC197_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x468) +/* GPIO_SIG197_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG197_IN_SEL (BIT(7)) +#define GPIO_SIG197_IN_SEL_M (BIT(7)) +#define GPIO_SIG197_IN_SEL_V 0x1 +#define GPIO_SIG197_IN_SEL_S 7 +/* GPIO_FUNC197_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC197_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC197_IN_INV_SEL_V 0x1 +#define GPIO_FUNC197_IN_INV_SEL_S 6 +/* GPIO_FUNC197_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC197_IN_SEL 0x0000003F +#define GPIO_FUNC197_IN_SEL_M ((GPIO_FUNC197_IN_SEL_V)<<(GPIO_FUNC197_IN_SEL_S)) +#define GPIO_FUNC197_IN_SEL_V 0x3F +#define GPIO_FUNC197_IN_SEL_S 0 + +#define GPIO_FUNC198_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x46C) +/* GPIO_SIG198_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG198_IN_SEL (BIT(7)) +#define GPIO_SIG198_IN_SEL_M (BIT(7)) +#define GPIO_SIG198_IN_SEL_V 0x1 +#define GPIO_SIG198_IN_SEL_S 7 +/* GPIO_FUNC198_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC198_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC198_IN_INV_SEL_V 0x1 +#define GPIO_FUNC198_IN_INV_SEL_S 6 +/* GPIO_FUNC198_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC198_IN_SEL 0x0000003F +#define GPIO_FUNC198_IN_SEL_M ((GPIO_FUNC198_IN_SEL_V)<<(GPIO_FUNC198_IN_SEL_S)) +#define GPIO_FUNC198_IN_SEL_V 0x3F +#define GPIO_FUNC198_IN_SEL_S 0 + +#define GPIO_FUNC199_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x470) +/* GPIO_SIG199_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG199_IN_SEL (BIT(7)) +#define GPIO_SIG199_IN_SEL_M (BIT(7)) +#define GPIO_SIG199_IN_SEL_V 0x1 +#define GPIO_SIG199_IN_SEL_S 7 +/* GPIO_FUNC199_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC199_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC199_IN_INV_SEL_V 0x1 +#define GPIO_FUNC199_IN_INV_SEL_S 6 +/* GPIO_FUNC199_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC199_IN_SEL 0x0000003F +#define GPIO_FUNC199_IN_SEL_M ((GPIO_FUNC199_IN_SEL_V)<<(GPIO_FUNC199_IN_SEL_S)) +#define GPIO_FUNC199_IN_SEL_V 0x3F +#define GPIO_FUNC199_IN_SEL_S 0 + +#define GPIO_FUNC200_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x474) +/* GPIO_SIG200_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG200_IN_SEL (BIT(7)) +#define GPIO_SIG200_IN_SEL_M (BIT(7)) +#define GPIO_SIG200_IN_SEL_V 0x1 +#define GPIO_SIG200_IN_SEL_S 7 +/* GPIO_FUNC200_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC200_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC200_IN_INV_SEL_V 0x1 +#define GPIO_FUNC200_IN_INV_SEL_S 6 +/* GPIO_FUNC200_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC200_IN_SEL 0x0000003F +#define GPIO_FUNC200_IN_SEL_M ((GPIO_FUNC200_IN_SEL_V)<<(GPIO_FUNC200_IN_SEL_S)) +#define GPIO_FUNC200_IN_SEL_V 0x3F +#define GPIO_FUNC200_IN_SEL_S 0 + +#define GPIO_FUNC201_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x478) +/* GPIO_SIG201_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG201_IN_SEL (BIT(7)) +#define GPIO_SIG201_IN_SEL_M (BIT(7)) +#define GPIO_SIG201_IN_SEL_V 0x1 +#define GPIO_SIG201_IN_SEL_S 7 +/* GPIO_FUNC201_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC201_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC201_IN_INV_SEL_V 0x1 +#define GPIO_FUNC201_IN_INV_SEL_S 6 +/* GPIO_FUNC201_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC201_IN_SEL 0x0000003F +#define GPIO_FUNC201_IN_SEL_M ((GPIO_FUNC201_IN_SEL_V)<<(GPIO_FUNC201_IN_SEL_S)) +#define GPIO_FUNC201_IN_SEL_V 0x3F +#define GPIO_FUNC201_IN_SEL_S 0 + +#define GPIO_FUNC202_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x47C) +/* GPIO_SIG202_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG202_IN_SEL (BIT(7)) +#define GPIO_SIG202_IN_SEL_M (BIT(7)) +#define GPIO_SIG202_IN_SEL_V 0x1 +#define GPIO_SIG202_IN_SEL_S 7 +/* GPIO_FUNC202_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC202_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC202_IN_INV_SEL_V 0x1 +#define GPIO_FUNC202_IN_INV_SEL_S 6 +/* GPIO_FUNC202_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC202_IN_SEL 0x0000003F +#define GPIO_FUNC202_IN_SEL_M ((GPIO_FUNC202_IN_SEL_V)<<(GPIO_FUNC202_IN_SEL_S)) +#define GPIO_FUNC202_IN_SEL_V 0x3F +#define GPIO_FUNC202_IN_SEL_S 0 + +#define GPIO_FUNC203_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x480) +/* GPIO_SIG203_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG203_IN_SEL (BIT(7)) +#define GPIO_SIG203_IN_SEL_M (BIT(7)) +#define GPIO_SIG203_IN_SEL_V 0x1 +#define GPIO_SIG203_IN_SEL_S 7 +/* GPIO_FUNC203_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC203_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC203_IN_INV_SEL_V 0x1 +#define GPIO_FUNC203_IN_INV_SEL_S 6 +/* GPIO_FUNC203_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC203_IN_SEL 0x0000003F +#define GPIO_FUNC203_IN_SEL_M ((GPIO_FUNC203_IN_SEL_V)<<(GPIO_FUNC203_IN_SEL_S)) +#define GPIO_FUNC203_IN_SEL_V 0x3F +#define GPIO_FUNC203_IN_SEL_S 0 + +#define GPIO_FUNC204_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x484) +/* GPIO_SIG204_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG204_IN_SEL (BIT(7)) +#define GPIO_SIG204_IN_SEL_M (BIT(7)) +#define GPIO_SIG204_IN_SEL_V 0x1 +#define GPIO_SIG204_IN_SEL_S 7 +/* GPIO_FUNC204_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC204_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC204_IN_INV_SEL_V 0x1 +#define GPIO_FUNC204_IN_INV_SEL_S 6 +/* GPIO_FUNC204_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC204_IN_SEL 0x0000003F +#define GPIO_FUNC204_IN_SEL_M ((GPIO_FUNC204_IN_SEL_V)<<(GPIO_FUNC204_IN_SEL_S)) +#define GPIO_FUNC204_IN_SEL_V 0x3F +#define GPIO_FUNC204_IN_SEL_S 0 + +#define GPIO_FUNC205_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x488) +/* GPIO_SIG205_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG205_IN_SEL (BIT(7)) +#define GPIO_SIG205_IN_SEL_M (BIT(7)) +#define GPIO_SIG205_IN_SEL_V 0x1 +#define GPIO_SIG205_IN_SEL_S 7 +/* GPIO_FUNC205_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC205_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC205_IN_INV_SEL_V 0x1 +#define GPIO_FUNC205_IN_INV_SEL_S 6 +/* GPIO_FUNC205_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC205_IN_SEL 0x0000003F +#define GPIO_FUNC205_IN_SEL_M ((GPIO_FUNC205_IN_SEL_V)<<(GPIO_FUNC205_IN_SEL_S)) +#define GPIO_FUNC205_IN_SEL_V 0x3F +#define GPIO_FUNC205_IN_SEL_S 0 + +#define GPIO_FUNC206_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x48C) +/* GPIO_SIG206_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG206_IN_SEL (BIT(7)) +#define GPIO_SIG206_IN_SEL_M (BIT(7)) +#define GPIO_SIG206_IN_SEL_V 0x1 +#define GPIO_SIG206_IN_SEL_S 7 +/* GPIO_FUNC206_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC206_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC206_IN_INV_SEL_V 0x1 +#define GPIO_FUNC206_IN_INV_SEL_S 6 +/* GPIO_FUNC206_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC206_IN_SEL 0x0000003F +#define GPIO_FUNC206_IN_SEL_M ((GPIO_FUNC206_IN_SEL_V)<<(GPIO_FUNC206_IN_SEL_S)) +#define GPIO_FUNC206_IN_SEL_V 0x3F +#define GPIO_FUNC206_IN_SEL_S 0 + +#define GPIO_FUNC207_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x490) +/* GPIO_SIG207_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG207_IN_SEL (BIT(7)) +#define GPIO_SIG207_IN_SEL_M (BIT(7)) +#define GPIO_SIG207_IN_SEL_V 0x1 +#define GPIO_SIG207_IN_SEL_S 7 +/* GPIO_FUNC207_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC207_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC207_IN_INV_SEL_V 0x1 +#define GPIO_FUNC207_IN_INV_SEL_S 6 +/* GPIO_FUNC207_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC207_IN_SEL 0x0000003F +#define GPIO_FUNC207_IN_SEL_M ((GPIO_FUNC207_IN_SEL_V)<<(GPIO_FUNC207_IN_SEL_S)) +#define GPIO_FUNC207_IN_SEL_V 0x3F +#define GPIO_FUNC207_IN_SEL_S 0 + +#define GPIO_FUNC208_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x494) +/* GPIO_SIG208_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG208_IN_SEL (BIT(7)) +#define GPIO_SIG208_IN_SEL_M (BIT(7)) +#define GPIO_SIG208_IN_SEL_V 0x1 +#define GPIO_SIG208_IN_SEL_S 7 +/* GPIO_FUNC208_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC208_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC208_IN_INV_SEL_V 0x1 +#define GPIO_FUNC208_IN_INV_SEL_S 6 +/* GPIO_FUNC208_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC208_IN_SEL 0x0000003F +#define GPIO_FUNC208_IN_SEL_M ((GPIO_FUNC208_IN_SEL_V)<<(GPIO_FUNC208_IN_SEL_S)) +#define GPIO_FUNC208_IN_SEL_V 0x3F +#define GPIO_FUNC208_IN_SEL_S 0 + +#define GPIO_FUNC209_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x498) +/* GPIO_SIG209_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG209_IN_SEL (BIT(7)) +#define GPIO_SIG209_IN_SEL_M (BIT(7)) +#define GPIO_SIG209_IN_SEL_V 0x1 +#define GPIO_SIG209_IN_SEL_S 7 +/* GPIO_FUNC209_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC209_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC209_IN_INV_SEL_V 0x1 +#define GPIO_FUNC209_IN_INV_SEL_S 6 +/* GPIO_FUNC209_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC209_IN_SEL 0x0000003F +#define GPIO_FUNC209_IN_SEL_M ((GPIO_FUNC209_IN_SEL_V)<<(GPIO_FUNC209_IN_SEL_S)) +#define GPIO_FUNC209_IN_SEL_V 0x3F +#define GPIO_FUNC209_IN_SEL_S 0 + +#define GPIO_FUNC210_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x49C) +/* GPIO_SIG210_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG210_IN_SEL (BIT(7)) +#define GPIO_SIG210_IN_SEL_M (BIT(7)) +#define GPIO_SIG210_IN_SEL_V 0x1 +#define GPIO_SIG210_IN_SEL_S 7 +/* GPIO_FUNC210_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC210_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC210_IN_INV_SEL_V 0x1 +#define GPIO_FUNC210_IN_INV_SEL_S 6 +/* GPIO_FUNC210_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC210_IN_SEL 0x0000003F +#define GPIO_FUNC210_IN_SEL_M ((GPIO_FUNC210_IN_SEL_V)<<(GPIO_FUNC210_IN_SEL_S)) +#define GPIO_FUNC210_IN_SEL_V 0x3F +#define GPIO_FUNC210_IN_SEL_S 0 + +#define GPIO_FUNC211_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4A0) +/* GPIO_SIG211_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG211_IN_SEL (BIT(7)) +#define GPIO_SIG211_IN_SEL_M (BIT(7)) +#define GPIO_SIG211_IN_SEL_V 0x1 +#define GPIO_SIG211_IN_SEL_S 7 +/* GPIO_FUNC211_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC211_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC211_IN_INV_SEL_V 0x1 +#define GPIO_FUNC211_IN_INV_SEL_S 6 +/* GPIO_FUNC211_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC211_IN_SEL 0x0000003F +#define GPIO_FUNC211_IN_SEL_M ((GPIO_FUNC211_IN_SEL_V)<<(GPIO_FUNC211_IN_SEL_S)) +#define GPIO_FUNC211_IN_SEL_V 0x3F +#define GPIO_FUNC211_IN_SEL_S 0 + +#define GPIO_FUNC212_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4A4) +/* GPIO_SIG212_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG212_IN_SEL (BIT(7)) +#define GPIO_SIG212_IN_SEL_M (BIT(7)) +#define GPIO_SIG212_IN_SEL_V 0x1 +#define GPIO_SIG212_IN_SEL_S 7 +/* GPIO_FUNC212_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC212_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC212_IN_INV_SEL_V 0x1 +#define GPIO_FUNC212_IN_INV_SEL_S 6 +/* GPIO_FUNC212_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC212_IN_SEL 0x0000003F +#define GPIO_FUNC212_IN_SEL_M ((GPIO_FUNC212_IN_SEL_V)<<(GPIO_FUNC212_IN_SEL_S)) +#define GPIO_FUNC212_IN_SEL_V 0x3F +#define GPIO_FUNC212_IN_SEL_S 0 + +#define GPIO_FUNC213_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4A8) +/* GPIO_SIG213_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG213_IN_SEL (BIT(7)) +#define GPIO_SIG213_IN_SEL_M (BIT(7)) +#define GPIO_SIG213_IN_SEL_V 0x1 +#define GPIO_SIG213_IN_SEL_S 7 +/* GPIO_FUNC213_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC213_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC213_IN_INV_SEL_V 0x1 +#define GPIO_FUNC213_IN_INV_SEL_S 6 +/* GPIO_FUNC213_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC213_IN_SEL 0x0000003F +#define GPIO_FUNC213_IN_SEL_M ((GPIO_FUNC213_IN_SEL_V)<<(GPIO_FUNC213_IN_SEL_S)) +#define GPIO_FUNC213_IN_SEL_V 0x3F +#define GPIO_FUNC213_IN_SEL_S 0 + +#define GPIO_FUNC214_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4AC) +/* GPIO_SIG214_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG214_IN_SEL (BIT(7)) +#define GPIO_SIG214_IN_SEL_M (BIT(7)) +#define GPIO_SIG214_IN_SEL_V 0x1 +#define GPIO_SIG214_IN_SEL_S 7 +/* GPIO_FUNC214_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC214_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC214_IN_INV_SEL_V 0x1 +#define GPIO_FUNC214_IN_INV_SEL_S 6 +/* GPIO_FUNC214_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC214_IN_SEL 0x0000003F +#define GPIO_FUNC214_IN_SEL_M ((GPIO_FUNC214_IN_SEL_V)<<(GPIO_FUNC214_IN_SEL_S)) +#define GPIO_FUNC214_IN_SEL_V 0x3F +#define GPIO_FUNC214_IN_SEL_S 0 + +#define GPIO_FUNC215_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4B0) +/* GPIO_SIG215_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG215_IN_SEL (BIT(7)) +#define GPIO_SIG215_IN_SEL_M (BIT(7)) +#define GPIO_SIG215_IN_SEL_V 0x1 +#define GPIO_SIG215_IN_SEL_S 7 +/* GPIO_FUNC215_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC215_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC215_IN_INV_SEL_V 0x1 +#define GPIO_FUNC215_IN_INV_SEL_S 6 +/* GPIO_FUNC215_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC215_IN_SEL 0x0000003F +#define GPIO_FUNC215_IN_SEL_M ((GPIO_FUNC215_IN_SEL_V)<<(GPIO_FUNC215_IN_SEL_S)) +#define GPIO_FUNC215_IN_SEL_V 0x3F +#define GPIO_FUNC215_IN_SEL_S 0 + +#define GPIO_FUNC216_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4B4) +/* GPIO_SIG216_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG216_IN_SEL (BIT(7)) +#define GPIO_SIG216_IN_SEL_M (BIT(7)) +#define GPIO_SIG216_IN_SEL_V 0x1 +#define GPIO_SIG216_IN_SEL_S 7 +/* GPIO_FUNC216_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC216_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC216_IN_INV_SEL_V 0x1 +#define GPIO_FUNC216_IN_INV_SEL_S 6 +/* GPIO_FUNC216_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC216_IN_SEL 0x0000003F +#define GPIO_FUNC216_IN_SEL_M ((GPIO_FUNC216_IN_SEL_V)<<(GPIO_FUNC216_IN_SEL_S)) +#define GPIO_FUNC216_IN_SEL_V 0x3F +#define GPIO_FUNC216_IN_SEL_S 0 + +#define GPIO_FUNC217_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4B8) +/* GPIO_SIG217_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG217_IN_SEL (BIT(7)) +#define GPIO_SIG217_IN_SEL_M (BIT(7)) +#define GPIO_SIG217_IN_SEL_V 0x1 +#define GPIO_SIG217_IN_SEL_S 7 +/* GPIO_FUNC217_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC217_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC217_IN_INV_SEL_V 0x1 +#define GPIO_FUNC217_IN_INV_SEL_S 6 +/* GPIO_FUNC217_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC217_IN_SEL 0x0000003F +#define GPIO_FUNC217_IN_SEL_M ((GPIO_FUNC217_IN_SEL_V)<<(GPIO_FUNC217_IN_SEL_S)) +#define GPIO_FUNC217_IN_SEL_V 0x3F +#define GPIO_FUNC217_IN_SEL_S 0 + +#define GPIO_FUNC218_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4BC) +/* GPIO_SIG218_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG218_IN_SEL (BIT(7)) +#define GPIO_SIG218_IN_SEL_M (BIT(7)) +#define GPIO_SIG218_IN_SEL_V 0x1 +#define GPIO_SIG218_IN_SEL_S 7 +/* GPIO_FUNC218_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC218_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC218_IN_INV_SEL_V 0x1 +#define GPIO_FUNC218_IN_INV_SEL_S 6 +/* GPIO_FUNC218_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC218_IN_SEL 0x0000003F +#define GPIO_FUNC218_IN_SEL_M ((GPIO_FUNC218_IN_SEL_V)<<(GPIO_FUNC218_IN_SEL_S)) +#define GPIO_FUNC218_IN_SEL_V 0x3F +#define GPIO_FUNC218_IN_SEL_S 0 + +#define GPIO_FUNC219_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4C0) +/* GPIO_SIG219_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG219_IN_SEL (BIT(7)) +#define GPIO_SIG219_IN_SEL_M (BIT(7)) +#define GPIO_SIG219_IN_SEL_V 0x1 +#define GPIO_SIG219_IN_SEL_S 7 +/* GPIO_FUNC219_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC219_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC219_IN_INV_SEL_V 0x1 +#define GPIO_FUNC219_IN_INV_SEL_S 6 +/* GPIO_FUNC219_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC219_IN_SEL 0x0000003F +#define GPIO_FUNC219_IN_SEL_M ((GPIO_FUNC219_IN_SEL_V)<<(GPIO_FUNC219_IN_SEL_S)) +#define GPIO_FUNC219_IN_SEL_V 0x3F +#define GPIO_FUNC219_IN_SEL_S 0 + +#define GPIO_FUNC220_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4C4) +/* GPIO_SIG220_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG220_IN_SEL (BIT(7)) +#define GPIO_SIG220_IN_SEL_M (BIT(7)) +#define GPIO_SIG220_IN_SEL_V 0x1 +#define GPIO_SIG220_IN_SEL_S 7 +/* GPIO_FUNC220_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC220_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC220_IN_INV_SEL_V 0x1 +#define GPIO_FUNC220_IN_INV_SEL_S 6 +/* GPIO_FUNC220_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC220_IN_SEL 0x0000003F +#define GPIO_FUNC220_IN_SEL_M ((GPIO_FUNC220_IN_SEL_V)<<(GPIO_FUNC220_IN_SEL_S)) +#define GPIO_FUNC220_IN_SEL_V 0x3F +#define GPIO_FUNC220_IN_SEL_S 0 + +#define GPIO_FUNC221_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4C8) +/* GPIO_SIG221_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG221_IN_SEL (BIT(7)) +#define GPIO_SIG221_IN_SEL_M (BIT(7)) +#define GPIO_SIG221_IN_SEL_V 0x1 +#define GPIO_SIG221_IN_SEL_S 7 +/* GPIO_FUNC221_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC221_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC221_IN_INV_SEL_V 0x1 +#define GPIO_FUNC221_IN_INV_SEL_S 6 +/* GPIO_FUNC221_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC221_IN_SEL 0x0000003F +#define GPIO_FUNC221_IN_SEL_M ((GPIO_FUNC221_IN_SEL_V)<<(GPIO_FUNC221_IN_SEL_S)) +#define GPIO_FUNC221_IN_SEL_V 0x3F +#define GPIO_FUNC221_IN_SEL_S 0 + +#define GPIO_FUNC222_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4CC) +/* GPIO_SIG222_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG222_IN_SEL (BIT(7)) +#define GPIO_SIG222_IN_SEL_M (BIT(7)) +#define GPIO_SIG222_IN_SEL_V 0x1 +#define GPIO_SIG222_IN_SEL_S 7 +/* GPIO_FUNC222_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC222_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC222_IN_INV_SEL_V 0x1 +#define GPIO_FUNC222_IN_INV_SEL_S 6 +/* GPIO_FUNC222_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC222_IN_SEL 0x0000003F +#define GPIO_FUNC222_IN_SEL_M ((GPIO_FUNC222_IN_SEL_V)<<(GPIO_FUNC222_IN_SEL_S)) +#define GPIO_FUNC222_IN_SEL_V 0x3F +#define GPIO_FUNC222_IN_SEL_S 0 + +#define GPIO_FUNC223_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4D0) +/* GPIO_SIG223_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG223_IN_SEL (BIT(7)) +#define GPIO_SIG223_IN_SEL_M (BIT(7)) +#define GPIO_SIG223_IN_SEL_V 0x1 +#define GPIO_SIG223_IN_SEL_S 7 +/* GPIO_FUNC223_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC223_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC223_IN_INV_SEL_V 0x1 +#define GPIO_FUNC223_IN_INV_SEL_S 6 +/* GPIO_FUNC223_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC223_IN_SEL 0x0000003F +#define GPIO_FUNC223_IN_SEL_M ((GPIO_FUNC223_IN_SEL_V)<<(GPIO_FUNC223_IN_SEL_S)) +#define GPIO_FUNC223_IN_SEL_V 0x3F +#define GPIO_FUNC223_IN_SEL_S 0 + +#define GPIO_FUNC224_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4D4) +/* GPIO_SIG224_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG224_IN_SEL (BIT(7)) +#define GPIO_SIG224_IN_SEL_M (BIT(7)) +#define GPIO_SIG224_IN_SEL_V 0x1 +#define GPIO_SIG224_IN_SEL_S 7 +/* GPIO_FUNC224_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC224_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC224_IN_INV_SEL_V 0x1 +#define GPIO_FUNC224_IN_INV_SEL_S 6 +/* GPIO_FUNC224_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC224_IN_SEL 0x0000003F +#define GPIO_FUNC224_IN_SEL_M ((GPIO_FUNC224_IN_SEL_V)<<(GPIO_FUNC224_IN_SEL_S)) +#define GPIO_FUNC224_IN_SEL_V 0x3F +#define GPIO_FUNC224_IN_SEL_S 0 + +#define GPIO_FUNC225_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4D8) +/* GPIO_SIG225_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG225_IN_SEL (BIT(7)) +#define GPIO_SIG225_IN_SEL_M (BIT(7)) +#define GPIO_SIG225_IN_SEL_V 0x1 +#define GPIO_SIG225_IN_SEL_S 7 +/* GPIO_FUNC225_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC225_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC225_IN_INV_SEL_V 0x1 +#define GPIO_FUNC225_IN_INV_SEL_S 6 +/* GPIO_FUNC225_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC225_IN_SEL 0x0000003F +#define GPIO_FUNC225_IN_SEL_M ((GPIO_FUNC225_IN_SEL_V)<<(GPIO_FUNC225_IN_SEL_S)) +#define GPIO_FUNC225_IN_SEL_V 0x3F +#define GPIO_FUNC225_IN_SEL_S 0 + +#define GPIO_FUNC226_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4DC) +/* GPIO_SIG226_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG226_IN_SEL (BIT(7)) +#define GPIO_SIG226_IN_SEL_M (BIT(7)) +#define GPIO_SIG226_IN_SEL_V 0x1 +#define GPIO_SIG226_IN_SEL_S 7 +/* GPIO_FUNC226_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC226_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC226_IN_INV_SEL_V 0x1 +#define GPIO_FUNC226_IN_INV_SEL_S 6 +/* GPIO_FUNC226_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC226_IN_SEL 0x0000003F +#define GPIO_FUNC226_IN_SEL_M ((GPIO_FUNC226_IN_SEL_V)<<(GPIO_FUNC226_IN_SEL_S)) +#define GPIO_FUNC226_IN_SEL_V 0x3F +#define GPIO_FUNC226_IN_SEL_S 0 + +#define GPIO_FUNC227_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4E0) +/* GPIO_SIG227_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG227_IN_SEL (BIT(7)) +#define GPIO_SIG227_IN_SEL_M (BIT(7)) +#define GPIO_SIG227_IN_SEL_V 0x1 +#define GPIO_SIG227_IN_SEL_S 7 +/* GPIO_FUNC227_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC227_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC227_IN_INV_SEL_V 0x1 +#define GPIO_FUNC227_IN_INV_SEL_S 6 +/* GPIO_FUNC227_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC227_IN_SEL 0x0000003F +#define GPIO_FUNC227_IN_SEL_M ((GPIO_FUNC227_IN_SEL_V)<<(GPIO_FUNC227_IN_SEL_S)) +#define GPIO_FUNC227_IN_SEL_V 0x3F +#define GPIO_FUNC227_IN_SEL_S 0 + +#define GPIO_FUNC228_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4E4) +/* GPIO_SIG228_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG228_IN_SEL (BIT(7)) +#define GPIO_SIG228_IN_SEL_M (BIT(7)) +#define GPIO_SIG228_IN_SEL_V 0x1 +#define GPIO_SIG228_IN_SEL_S 7 +/* GPIO_FUNC228_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC228_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC228_IN_INV_SEL_V 0x1 +#define GPIO_FUNC228_IN_INV_SEL_S 6 +/* GPIO_FUNC228_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC228_IN_SEL 0x0000003F +#define GPIO_FUNC228_IN_SEL_M ((GPIO_FUNC228_IN_SEL_V)<<(GPIO_FUNC228_IN_SEL_S)) +#define GPIO_FUNC228_IN_SEL_V 0x3F +#define GPIO_FUNC228_IN_SEL_S 0 + +#define GPIO_FUNC229_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4E8) +/* GPIO_SIG229_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG229_IN_SEL (BIT(7)) +#define GPIO_SIG229_IN_SEL_M (BIT(7)) +#define GPIO_SIG229_IN_SEL_V 0x1 +#define GPIO_SIG229_IN_SEL_S 7 +/* GPIO_FUNC229_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC229_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC229_IN_INV_SEL_V 0x1 +#define GPIO_FUNC229_IN_INV_SEL_S 6 +/* GPIO_FUNC229_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC229_IN_SEL 0x0000003F +#define GPIO_FUNC229_IN_SEL_M ((GPIO_FUNC229_IN_SEL_V)<<(GPIO_FUNC229_IN_SEL_S)) +#define GPIO_FUNC229_IN_SEL_V 0x3F +#define GPIO_FUNC229_IN_SEL_S 0 + +#define GPIO_FUNC230_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4EC) +/* GPIO_SIG230_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG230_IN_SEL (BIT(7)) +#define GPIO_SIG230_IN_SEL_M (BIT(7)) +#define GPIO_SIG230_IN_SEL_V 0x1 +#define GPIO_SIG230_IN_SEL_S 7 +/* GPIO_FUNC230_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC230_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC230_IN_INV_SEL_V 0x1 +#define GPIO_FUNC230_IN_INV_SEL_S 6 +/* GPIO_FUNC230_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC230_IN_SEL 0x0000003F +#define GPIO_FUNC230_IN_SEL_M ((GPIO_FUNC230_IN_SEL_V)<<(GPIO_FUNC230_IN_SEL_S)) +#define GPIO_FUNC230_IN_SEL_V 0x3F +#define GPIO_FUNC230_IN_SEL_S 0 + +#define GPIO_FUNC231_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4F0) +/* GPIO_SIG231_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG231_IN_SEL (BIT(7)) +#define GPIO_SIG231_IN_SEL_M (BIT(7)) +#define GPIO_SIG231_IN_SEL_V 0x1 +#define GPIO_SIG231_IN_SEL_S 7 +/* GPIO_FUNC231_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC231_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC231_IN_INV_SEL_V 0x1 +#define GPIO_FUNC231_IN_INV_SEL_S 6 +/* GPIO_FUNC231_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC231_IN_SEL 0x0000003F +#define GPIO_FUNC231_IN_SEL_M ((GPIO_FUNC231_IN_SEL_V)<<(GPIO_FUNC231_IN_SEL_S)) +#define GPIO_FUNC231_IN_SEL_V 0x3F +#define GPIO_FUNC231_IN_SEL_S 0 + +#define GPIO_FUNC232_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4F4) +/* GPIO_SIG232_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG232_IN_SEL (BIT(7)) +#define GPIO_SIG232_IN_SEL_M (BIT(7)) +#define GPIO_SIG232_IN_SEL_V 0x1 +#define GPIO_SIG232_IN_SEL_S 7 +/* GPIO_FUNC232_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC232_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC232_IN_INV_SEL_V 0x1 +#define GPIO_FUNC232_IN_INV_SEL_S 6 +/* GPIO_FUNC232_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC232_IN_SEL 0x0000003F +#define GPIO_FUNC232_IN_SEL_M ((GPIO_FUNC232_IN_SEL_V)<<(GPIO_FUNC232_IN_SEL_S)) +#define GPIO_FUNC232_IN_SEL_V 0x3F +#define GPIO_FUNC232_IN_SEL_S 0 + +#define GPIO_FUNC233_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4F8) +/* GPIO_SIG233_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG233_IN_SEL (BIT(7)) +#define GPIO_SIG233_IN_SEL_M (BIT(7)) +#define GPIO_SIG233_IN_SEL_V 0x1 +#define GPIO_SIG233_IN_SEL_S 7 +/* GPIO_FUNC233_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC233_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC233_IN_INV_SEL_V 0x1 +#define GPIO_FUNC233_IN_INV_SEL_S 6 +/* GPIO_FUNC233_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC233_IN_SEL 0x0000003F +#define GPIO_FUNC233_IN_SEL_M ((GPIO_FUNC233_IN_SEL_V)<<(GPIO_FUNC233_IN_SEL_S)) +#define GPIO_FUNC233_IN_SEL_V 0x3F +#define GPIO_FUNC233_IN_SEL_S 0 + +#define GPIO_FUNC234_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x4FC) +/* GPIO_SIG234_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG234_IN_SEL (BIT(7)) +#define GPIO_SIG234_IN_SEL_M (BIT(7)) +#define GPIO_SIG234_IN_SEL_V 0x1 +#define GPIO_SIG234_IN_SEL_S 7 +/* GPIO_FUNC234_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC234_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC234_IN_INV_SEL_V 0x1 +#define GPIO_FUNC234_IN_INV_SEL_S 6 +/* GPIO_FUNC234_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC234_IN_SEL 0x0000003F +#define GPIO_FUNC234_IN_SEL_M ((GPIO_FUNC234_IN_SEL_V)<<(GPIO_FUNC234_IN_SEL_S)) +#define GPIO_FUNC234_IN_SEL_V 0x3F +#define GPIO_FUNC234_IN_SEL_S 0 + +#define GPIO_FUNC235_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x500) +/* GPIO_SIG235_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG235_IN_SEL (BIT(7)) +#define GPIO_SIG235_IN_SEL_M (BIT(7)) +#define GPIO_SIG235_IN_SEL_V 0x1 +#define GPIO_SIG235_IN_SEL_S 7 +/* GPIO_FUNC235_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC235_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC235_IN_INV_SEL_V 0x1 +#define GPIO_FUNC235_IN_INV_SEL_S 6 +/* GPIO_FUNC235_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC235_IN_SEL 0x0000003F +#define GPIO_FUNC235_IN_SEL_M ((GPIO_FUNC235_IN_SEL_V)<<(GPIO_FUNC235_IN_SEL_S)) +#define GPIO_FUNC235_IN_SEL_V 0x3F +#define GPIO_FUNC235_IN_SEL_S 0 + +#define GPIO_FUNC236_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x504) +/* GPIO_SIG236_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG236_IN_SEL (BIT(7)) +#define GPIO_SIG236_IN_SEL_M (BIT(7)) +#define GPIO_SIG236_IN_SEL_V 0x1 +#define GPIO_SIG236_IN_SEL_S 7 +/* GPIO_FUNC236_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC236_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC236_IN_INV_SEL_V 0x1 +#define GPIO_FUNC236_IN_INV_SEL_S 6 +/* GPIO_FUNC236_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC236_IN_SEL 0x0000003F +#define GPIO_FUNC236_IN_SEL_M ((GPIO_FUNC236_IN_SEL_V)<<(GPIO_FUNC236_IN_SEL_S)) +#define GPIO_FUNC236_IN_SEL_V 0x3F +#define GPIO_FUNC236_IN_SEL_S 0 + +#define GPIO_FUNC237_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x508) +/* GPIO_SIG237_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG237_IN_SEL (BIT(7)) +#define GPIO_SIG237_IN_SEL_M (BIT(7)) +#define GPIO_SIG237_IN_SEL_V 0x1 +#define GPIO_SIG237_IN_SEL_S 7 +/* GPIO_FUNC237_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC237_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC237_IN_INV_SEL_V 0x1 +#define GPIO_FUNC237_IN_INV_SEL_S 6 +/* GPIO_FUNC237_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC237_IN_SEL 0x0000003F +#define GPIO_FUNC237_IN_SEL_M ((GPIO_FUNC237_IN_SEL_V)<<(GPIO_FUNC237_IN_SEL_S)) +#define GPIO_FUNC237_IN_SEL_V 0x3F +#define GPIO_FUNC237_IN_SEL_S 0 + +#define GPIO_FUNC238_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x50C) +/* GPIO_SIG238_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG238_IN_SEL (BIT(7)) +#define GPIO_SIG238_IN_SEL_M (BIT(7)) +#define GPIO_SIG238_IN_SEL_V 0x1 +#define GPIO_SIG238_IN_SEL_S 7 +/* GPIO_FUNC238_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC238_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC238_IN_INV_SEL_V 0x1 +#define GPIO_FUNC238_IN_INV_SEL_S 6 +/* GPIO_FUNC238_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC238_IN_SEL 0x0000003F +#define GPIO_FUNC238_IN_SEL_M ((GPIO_FUNC238_IN_SEL_V)<<(GPIO_FUNC238_IN_SEL_S)) +#define GPIO_FUNC238_IN_SEL_V 0x3F +#define GPIO_FUNC238_IN_SEL_S 0 + +#define GPIO_FUNC239_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x510) +/* GPIO_SIG239_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG239_IN_SEL (BIT(7)) +#define GPIO_SIG239_IN_SEL_M (BIT(7)) +#define GPIO_SIG239_IN_SEL_V 0x1 +#define GPIO_SIG239_IN_SEL_S 7 +/* GPIO_FUNC239_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC239_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC239_IN_INV_SEL_V 0x1 +#define GPIO_FUNC239_IN_INV_SEL_S 6 +/* GPIO_FUNC239_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC239_IN_SEL 0x0000003F +#define GPIO_FUNC239_IN_SEL_M ((GPIO_FUNC239_IN_SEL_V)<<(GPIO_FUNC239_IN_SEL_S)) +#define GPIO_FUNC239_IN_SEL_V 0x3F +#define GPIO_FUNC239_IN_SEL_S 0 + +#define GPIO_FUNC240_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x514) +/* GPIO_SIG240_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG240_IN_SEL (BIT(7)) +#define GPIO_SIG240_IN_SEL_M (BIT(7)) +#define GPIO_SIG240_IN_SEL_V 0x1 +#define GPIO_SIG240_IN_SEL_S 7 +/* GPIO_FUNC240_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC240_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC240_IN_INV_SEL_V 0x1 +#define GPIO_FUNC240_IN_INV_SEL_S 6 +/* GPIO_FUNC240_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC240_IN_SEL 0x0000003F +#define GPIO_FUNC240_IN_SEL_M ((GPIO_FUNC240_IN_SEL_V)<<(GPIO_FUNC240_IN_SEL_S)) +#define GPIO_FUNC240_IN_SEL_V 0x3F +#define GPIO_FUNC240_IN_SEL_S 0 + +#define GPIO_FUNC241_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x518) +/* GPIO_SIG241_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG241_IN_SEL (BIT(7)) +#define GPIO_SIG241_IN_SEL_M (BIT(7)) +#define GPIO_SIG241_IN_SEL_V 0x1 +#define GPIO_SIG241_IN_SEL_S 7 +/* GPIO_FUNC241_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC241_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC241_IN_INV_SEL_V 0x1 +#define GPIO_FUNC241_IN_INV_SEL_S 6 +/* GPIO_FUNC241_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC241_IN_SEL 0x0000003F +#define GPIO_FUNC241_IN_SEL_M ((GPIO_FUNC241_IN_SEL_V)<<(GPIO_FUNC241_IN_SEL_S)) +#define GPIO_FUNC241_IN_SEL_V 0x3F +#define GPIO_FUNC241_IN_SEL_S 0 + +#define GPIO_FUNC242_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x51C) +/* GPIO_SIG242_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG242_IN_SEL (BIT(7)) +#define GPIO_SIG242_IN_SEL_M (BIT(7)) +#define GPIO_SIG242_IN_SEL_V 0x1 +#define GPIO_SIG242_IN_SEL_S 7 +/* GPIO_FUNC242_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC242_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC242_IN_INV_SEL_V 0x1 +#define GPIO_FUNC242_IN_INV_SEL_S 6 +/* GPIO_FUNC242_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC242_IN_SEL 0x0000003F +#define GPIO_FUNC242_IN_SEL_M ((GPIO_FUNC242_IN_SEL_V)<<(GPIO_FUNC242_IN_SEL_S)) +#define GPIO_FUNC242_IN_SEL_V 0x3F +#define GPIO_FUNC242_IN_SEL_S 0 + +#define GPIO_FUNC243_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x520) +/* GPIO_SIG243_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG243_IN_SEL (BIT(7)) +#define GPIO_SIG243_IN_SEL_M (BIT(7)) +#define GPIO_SIG243_IN_SEL_V 0x1 +#define GPIO_SIG243_IN_SEL_S 7 +/* GPIO_FUNC243_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC243_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC243_IN_INV_SEL_V 0x1 +#define GPIO_FUNC243_IN_INV_SEL_S 6 +/* GPIO_FUNC243_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC243_IN_SEL 0x0000003F +#define GPIO_FUNC243_IN_SEL_M ((GPIO_FUNC243_IN_SEL_V)<<(GPIO_FUNC243_IN_SEL_S)) +#define GPIO_FUNC243_IN_SEL_V 0x3F +#define GPIO_FUNC243_IN_SEL_S 0 + +#define GPIO_FUNC244_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x524) +/* GPIO_SIG244_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG244_IN_SEL (BIT(7)) +#define GPIO_SIG244_IN_SEL_M (BIT(7)) +#define GPIO_SIG244_IN_SEL_V 0x1 +#define GPIO_SIG244_IN_SEL_S 7 +/* GPIO_FUNC244_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC244_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC244_IN_INV_SEL_V 0x1 +#define GPIO_FUNC244_IN_INV_SEL_S 6 +/* GPIO_FUNC244_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC244_IN_SEL 0x0000003F +#define GPIO_FUNC244_IN_SEL_M ((GPIO_FUNC244_IN_SEL_V)<<(GPIO_FUNC244_IN_SEL_S)) +#define GPIO_FUNC244_IN_SEL_V 0x3F +#define GPIO_FUNC244_IN_SEL_S 0 + +#define GPIO_FUNC245_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x528) +/* GPIO_SIG245_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG245_IN_SEL (BIT(7)) +#define GPIO_SIG245_IN_SEL_M (BIT(7)) +#define GPIO_SIG245_IN_SEL_V 0x1 +#define GPIO_SIG245_IN_SEL_S 7 +/* GPIO_FUNC245_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC245_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC245_IN_INV_SEL_V 0x1 +#define GPIO_FUNC245_IN_INV_SEL_S 6 +/* GPIO_FUNC245_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC245_IN_SEL 0x0000003F +#define GPIO_FUNC245_IN_SEL_M ((GPIO_FUNC245_IN_SEL_V)<<(GPIO_FUNC245_IN_SEL_S)) +#define GPIO_FUNC245_IN_SEL_V 0x3F +#define GPIO_FUNC245_IN_SEL_S 0 + +#define GPIO_FUNC246_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x52C) +/* GPIO_SIG246_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG246_IN_SEL (BIT(7)) +#define GPIO_SIG246_IN_SEL_M (BIT(7)) +#define GPIO_SIG246_IN_SEL_V 0x1 +#define GPIO_SIG246_IN_SEL_S 7 +/* GPIO_FUNC246_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC246_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC246_IN_INV_SEL_V 0x1 +#define GPIO_FUNC246_IN_INV_SEL_S 6 +/* GPIO_FUNC246_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC246_IN_SEL 0x0000003F +#define GPIO_FUNC246_IN_SEL_M ((GPIO_FUNC246_IN_SEL_V)<<(GPIO_FUNC246_IN_SEL_S)) +#define GPIO_FUNC246_IN_SEL_V 0x3F +#define GPIO_FUNC246_IN_SEL_S 0 + +#define GPIO_FUNC247_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x530) +/* GPIO_SIG247_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG247_IN_SEL (BIT(7)) +#define GPIO_SIG247_IN_SEL_M (BIT(7)) +#define GPIO_SIG247_IN_SEL_V 0x1 +#define GPIO_SIG247_IN_SEL_S 7 +/* GPIO_FUNC247_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC247_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC247_IN_INV_SEL_V 0x1 +#define GPIO_FUNC247_IN_INV_SEL_S 6 +/* GPIO_FUNC247_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC247_IN_SEL 0x0000003F +#define GPIO_FUNC247_IN_SEL_M ((GPIO_FUNC247_IN_SEL_V)<<(GPIO_FUNC247_IN_SEL_S)) +#define GPIO_FUNC247_IN_SEL_V 0x3F +#define GPIO_FUNC247_IN_SEL_S 0 + +#define GPIO_FUNC248_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x534) +/* GPIO_SIG248_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG248_IN_SEL (BIT(7)) +#define GPIO_SIG248_IN_SEL_M (BIT(7)) +#define GPIO_SIG248_IN_SEL_V 0x1 +#define GPIO_SIG248_IN_SEL_S 7 +/* GPIO_FUNC248_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC248_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC248_IN_INV_SEL_V 0x1 +#define GPIO_FUNC248_IN_INV_SEL_S 6 +/* GPIO_FUNC248_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC248_IN_SEL 0x0000003F +#define GPIO_FUNC248_IN_SEL_M ((GPIO_FUNC248_IN_SEL_V)<<(GPIO_FUNC248_IN_SEL_S)) +#define GPIO_FUNC248_IN_SEL_V 0x3F +#define GPIO_FUNC248_IN_SEL_S 0 + +#define GPIO_FUNC249_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x538) +/* GPIO_SIG249_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG249_IN_SEL (BIT(7)) +#define GPIO_SIG249_IN_SEL_M (BIT(7)) +#define GPIO_SIG249_IN_SEL_V 0x1 +#define GPIO_SIG249_IN_SEL_S 7 +/* GPIO_FUNC249_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC249_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC249_IN_INV_SEL_V 0x1 +#define GPIO_FUNC249_IN_INV_SEL_S 6 +/* GPIO_FUNC249_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC249_IN_SEL 0x0000003F +#define GPIO_FUNC249_IN_SEL_M ((GPIO_FUNC249_IN_SEL_V)<<(GPIO_FUNC249_IN_SEL_S)) +#define GPIO_FUNC249_IN_SEL_V 0x3F +#define GPIO_FUNC249_IN_SEL_S 0 + +#define GPIO_FUNC250_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x53C) +/* GPIO_SIG250_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG250_IN_SEL (BIT(7)) +#define GPIO_SIG250_IN_SEL_M (BIT(7)) +#define GPIO_SIG250_IN_SEL_V 0x1 +#define GPIO_SIG250_IN_SEL_S 7 +/* GPIO_FUNC250_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC250_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC250_IN_INV_SEL_V 0x1 +#define GPIO_FUNC250_IN_INV_SEL_S 6 +/* GPIO_FUNC250_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC250_IN_SEL 0x0000003F +#define GPIO_FUNC250_IN_SEL_M ((GPIO_FUNC250_IN_SEL_V)<<(GPIO_FUNC250_IN_SEL_S)) +#define GPIO_FUNC250_IN_SEL_V 0x3F +#define GPIO_FUNC250_IN_SEL_S 0 + +#define GPIO_FUNC251_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x540) +/* GPIO_SIG251_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG251_IN_SEL (BIT(7)) +#define GPIO_SIG251_IN_SEL_M (BIT(7)) +#define GPIO_SIG251_IN_SEL_V 0x1 +#define GPIO_SIG251_IN_SEL_S 7 +/* GPIO_FUNC251_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC251_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC251_IN_INV_SEL_V 0x1 +#define GPIO_FUNC251_IN_INV_SEL_S 6 +/* GPIO_FUNC251_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC251_IN_SEL 0x0000003F +#define GPIO_FUNC251_IN_SEL_M ((GPIO_FUNC251_IN_SEL_V)<<(GPIO_FUNC251_IN_SEL_S)) +#define GPIO_FUNC251_IN_SEL_V 0x3F +#define GPIO_FUNC251_IN_SEL_S 0 + +#define GPIO_FUNC252_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x544) +/* GPIO_SIG252_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG252_IN_SEL (BIT(7)) +#define GPIO_SIG252_IN_SEL_M (BIT(7)) +#define GPIO_SIG252_IN_SEL_V 0x1 +#define GPIO_SIG252_IN_SEL_S 7 +/* GPIO_FUNC252_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC252_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC252_IN_INV_SEL_V 0x1 +#define GPIO_FUNC252_IN_INV_SEL_S 6 +/* GPIO_FUNC252_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC252_IN_SEL 0x0000003F +#define GPIO_FUNC252_IN_SEL_M ((GPIO_FUNC252_IN_SEL_V)<<(GPIO_FUNC252_IN_SEL_S)) +#define GPIO_FUNC252_IN_SEL_V 0x3F +#define GPIO_FUNC252_IN_SEL_S 0 + +#define GPIO_FUNC253_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x548) +/* GPIO_SIG253_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG253_IN_SEL (BIT(7)) +#define GPIO_SIG253_IN_SEL_M (BIT(7)) +#define GPIO_SIG253_IN_SEL_V 0x1 +#define GPIO_SIG253_IN_SEL_S 7 +/* GPIO_FUNC253_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC253_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC253_IN_INV_SEL_V 0x1 +#define GPIO_FUNC253_IN_INV_SEL_S 6 +/* GPIO_FUNC253_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC253_IN_SEL 0x0000003F +#define GPIO_FUNC253_IN_SEL_M ((GPIO_FUNC253_IN_SEL_V)<<(GPIO_FUNC253_IN_SEL_S)) +#define GPIO_FUNC253_IN_SEL_V 0x3F +#define GPIO_FUNC253_IN_SEL_S 0 + +#define GPIO_FUNC254_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x54C) +/* GPIO_SIG254_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG254_IN_SEL (BIT(7)) +#define GPIO_SIG254_IN_SEL_M (BIT(7)) +#define GPIO_SIG254_IN_SEL_V 0x1 +#define GPIO_SIG254_IN_SEL_S 7 +/* GPIO_FUNC254_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC254_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC254_IN_INV_SEL_V 0x1 +#define GPIO_FUNC254_IN_INV_SEL_S 6 +/* GPIO_FUNC254_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC254_IN_SEL 0x0000003F +#define GPIO_FUNC254_IN_SEL_M ((GPIO_FUNC254_IN_SEL_V)<<(GPIO_FUNC254_IN_SEL_S)) +#define GPIO_FUNC254_IN_SEL_V 0x3F +#define GPIO_FUNC254_IN_SEL_S 0 + +#define GPIO_FUNC255_IN_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x550) +/* GPIO_SIG255_IN_SEL : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SIG255_IN_SEL (BIT(7)) +#define GPIO_SIG255_IN_SEL_M (BIT(7)) +#define GPIO_SIG255_IN_SEL_V 0x1 +#define GPIO_SIG255_IN_SEL_S 7 +/* GPIO_FUNC255_IN_INV_SEL : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC255_IN_INV_SEL (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_M (BIT(6)) +#define GPIO_FUNC255_IN_INV_SEL_V 0x1 +#define GPIO_FUNC255_IN_INV_SEL_S 6 +/* GPIO_FUNC255_IN_SEL : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define GPIO_FUNC255_IN_SEL 0x0000003F +#define GPIO_FUNC255_IN_SEL_M ((GPIO_FUNC255_IN_SEL_V)<<(GPIO_FUNC255_IN_SEL_S)) +#define GPIO_FUNC255_IN_SEL_V 0x3F +#define GPIO_FUNC255_IN_SEL_S 0 + +#define GPIO_FUNC0_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x554) +/* GPIO_FUNC0_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC0_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC0_OEN_INV_SEL_S 11 +/* GPIO_FUNC0_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_OEN_SEL (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC0_OEN_SEL_V 0x1 +#define GPIO_FUNC0_OEN_SEL_S 10 +/* GPIO_FUNC0_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC0_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC0_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC0_OUT_INV_SEL_S 9 +/* GPIO_FUNC0_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC0_OUT_SEL 0x000001FF +#define GPIO_FUNC0_OUT_SEL_M ((GPIO_FUNC0_OUT_SEL_V)<<(GPIO_FUNC0_OUT_SEL_S)) +#define GPIO_FUNC0_OUT_SEL_V 0x1FF +#define GPIO_FUNC0_OUT_SEL_S 0 + +#define GPIO_FUNC1_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x558) +/* GPIO_FUNC1_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC1_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC1_OEN_INV_SEL_S 11 +/* GPIO_FUNC1_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_OEN_SEL (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC1_OEN_SEL_V 0x1 +#define GPIO_FUNC1_OEN_SEL_S 10 +/* GPIO_FUNC1_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC1_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC1_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC1_OUT_INV_SEL_S 9 +/* GPIO_FUNC1_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC1_OUT_SEL 0x000001FF +#define GPIO_FUNC1_OUT_SEL_M ((GPIO_FUNC1_OUT_SEL_V)<<(GPIO_FUNC1_OUT_SEL_S)) +#define GPIO_FUNC1_OUT_SEL_V 0x1FF +#define GPIO_FUNC1_OUT_SEL_S 0 + +#define GPIO_FUNC2_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x55C) +/* GPIO_FUNC2_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC2_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC2_OEN_INV_SEL_S 11 +/* GPIO_FUNC2_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_OEN_SEL (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC2_OEN_SEL_V 0x1 +#define GPIO_FUNC2_OEN_SEL_S 10 +/* GPIO_FUNC2_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC2_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC2_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC2_OUT_INV_SEL_S 9 +/* GPIO_FUNC2_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC2_OUT_SEL 0x000001FF +#define GPIO_FUNC2_OUT_SEL_M ((GPIO_FUNC2_OUT_SEL_V)<<(GPIO_FUNC2_OUT_SEL_S)) +#define GPIO_FUNC2_OUT_SEL_V 0x1FF +#define GPIO_FUNC2_OUT_SEL_S 0 + +#define GPIO_FUNC3_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x560) +/* GPIO_FUNC3_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC3_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC3_OEN_INV_SEL_S 11 +/* GPIO_FUNC3_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_OEN_SEL (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC3_OEN_SEL_V 0x1 +#define GPIO_FUNC3_OEN_SEL_S 10 +/* GPIO_FUNC3_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC3_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC3_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC3_OUT_INV_SEL_S 9 +/* GPIO_FUNC3_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC3_OUT_SEL 0x000001FF +#define GPIO_FUNC3_OUT_SEL_M ((GPIO_FUNC3_OUT_SEL_V)<<(GPIO_FUNC3_OUT_SEL_S)) +#define GPIO_FUNC3_OUT_SEL_V 0x1FF +#define GPIO_FUNC3_OUT_SEL_S 0 + +#define GPIO_FUNC4_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x564) +/* GPIO_FUNC4_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC4_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC4_OEN_INV_SEL_S 11 +/* GPIO_FUNC4_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_OEN_SEL (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC4_OEN_SEL_V 0x1 +#define GPIO_FUNC4_OEN_SEL_S 10 +/* GPIO_FUNC4_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC4_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC4_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC4_OUT_INV_SEL_S 9 +/* GPIO_FUNC4_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC4_OUT_SEL 0x000001FF +#define GPIO_FUNC4_OUT_SEL_M ((GPIO_FUNC4_OUT_SEL_V)<<(GPIO_FUNC4_OUT_SEL_S)) +#define GPIO_FUNC4_OUT_SEL_V 0x1FF +#define GPIO_FUNC4_OUT_SEL_S 0 + +#define GPIO_FUNC5_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x568) +/* GPIO_FUNC5_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC5_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC5_OEN_INV_SEL_S 11 +/* GPIO_FUNC5_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_OEN_SEL (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC5_OEN_SEL_V 0x1 +#define GPIO_FUNC5_OEN_SEL_S 10 +/* GPIO_FUNC5_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC5_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC5_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC5_OUT_INV_SEL_S 9 +/* GPIO_FUNC5_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC5_OUT_SEL 0x000001FF +#define GPIO_FUNC5_OUT_SEL_M ((GPIO_FUNC5_OUT_SEL_V)<<(GPIO_FUNC5_OUT_SEL_S)) +#define GPIO_FUNC5_OUT_SEL_V 0x1FF +#define GPIO_FUNC5_OUT_SEL_S 0 + +#define GPIO_FUNC6_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x56C) +/* GPIO_FUNC6_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC6_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC6_OEN_INV_SEL_S 11 +/* GPIO_FUNC6_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_OEN_SEL (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC6_OEN_SEL_V 0x1 +#define GPIO_FUNC6_OEN_SEL_S 10 +/* GPIO_FUNC6_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC6_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC6_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC6_OUT_INV_SEL_S 9 +/* GPIO_FUNC6_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC6_OUT_SEL 0x000001FF +#define GPIO_FUNC6_OUT_SEL_M ((GPIO_FUNC6_OUT_SEL_V)<<(GPIO_FUNC6_OUT_SEL_S)) +#define GPIO_FUNC6_OUT_SEL_V 0x1FF +#define GPIO_FUNC6_OUT_SEL_S 0 + +#define GPIO_FUNC7_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x570) +/* GPIO_FUNC7_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC7_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC7_OEN_INV_SEL_S 11 +/* GPIO_FUNC7_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_OEN_SEL (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC7_OEN_SEL_V 0x1 +#define GPIO_FUNC7_OEN_SEL_S 10 +/* GPIO_FUNC7_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC7_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC7_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC7_OUT_INV_SEL_S 9 +/* GPIO_FUNC7_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC7_OUT_SEL 0x000001FF +#define GPIO_FUNC7_OUT_SEL_M ((GPIO_FUNC7_OUT_SEL_V)<<(GPIO_FUNC7_OUT_SEL_S)) +#define GPIO_FUNC7_OUT_SEL_V 0x1FF +#define GPIO_FUNC7_OUT_SEL_S 0 + +#define GPIO_FUNC8_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x574) +/* GPIO_FUNC8_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC8_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC8_OEN_INV_SEL_S 11 +/* GPIO_FUNC8_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_OEN_SEL (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC8_OEN_SEL_V 0x1 +#define GPIO_FUNC8_OEN_SEL_S 10 +/* GPIO_FUNC8_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC8_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC8_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC8_OUT_INV_SEL_S 9 +/* GPIO_FUNC8_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC8_OUT_SEL 0x000001FF +#define GPIO_FUNC8_OUT_SEL_M ((GPIO_FUNC8_OUT_SEL_V)<<(GPIO_FUNC8_OUT_SEL_S)) +#define GPIO_FUNC8_OUT_SEL_V 0x1FF +#define GPIO_FUNC8_OUT_SEL_S 0 + +#define GPIO_FUNC9_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x578) +/* GPIO_FUNC9_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC9_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC9_OEN_INV_SEL_S 11 +/* GPIO_FUNC9_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_OEN_SEL (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC9_OEN_SEL_V 0x1 +#define GPIO_FUNC9_OEN_SEL_S 10 +/* GPIO_FUNC9_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC9_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC9_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC9_OUT_INV_SEL_S 9 +/* GPIO_FUNC9_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC9_OUT_SEL 0x000001FF +#define GPIO_FUNC9_OUT_SEL_M ((GPIO_FUNC9_OUT_SEL_V)<<(GPIO_FUNC9_OUT_SEL_S)) +#define GPIO_FUNC9_OUT_SEL_V 0x1FF +#define GPIO_FUNC9_OUT_SEL_S 0 + +#define GPIO_FUNC10_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x57C) +/* GPIO_FUNC10_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC10_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC10_OEN_INV_SEL_S 11 +/* GPIO_FUNC10_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_OEN_SEL (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC10_OEN_SEL_V 0x1 +#define GPIO_FUNC10_OEN_SEL_S 10 +/* GPIO_FUNC10_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC10_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC10_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC10_OUT_INV_SEL_S 9 +/* GPIO_FUNC10_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC10_OUT_SEL 0x000001FF +#define GPIO_FUNC10_OUT_SEL_M ((GPIO_FUNC10_OUT_SEL_V)<<(GPIO_FUNC10_OUT_SEL_S)) +#define GPIO_FUNC10_OUT_SEL_V 0x1FF +#define GPIO_FUNC10_OUT_SEL_S 0 + +#define GPIO_FUNC11_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x580) +/* GPIO_FUNC11_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC11_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC11_OEN_INV_SEL_S 11 +/* GPIO_FUNC11_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_OEN_SEL (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC11_OEN_SEL_V 0x1 +#define GPIO_FUNC11_OEN_SEL_S 10 +/* GPIO_FUNC11_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC11_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC11_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC11_OUT_INV_SEL_S 9 +/* GPIO_FUNC11_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC11_OUT_SEL 0x000001FF +#define GPIO_FUNC11_OUT_SEL_M ((GPIO_FUNC11_OUT_SEL_V)<<(GPIO_FUNC11_OUT_SEL_S)) +#define GPIO_FUNC11_OUT_SEL_V 0x1FF +#define GPIO_FUNC11_OUT_SEL_S 0 + +#define GPIO_FUNC12_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x584) +/* GPIO_FUNC12_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC12_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC12_OEN_INV_SEL_S 11 +/* GPIO_FUNC12_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_OEN_SEL (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC12_OEN_SEL_V 0x1 +#define GPIO_FUNC12_OEN_SEL_S 10 +/* GPIO_FUNC12_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC12_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC12_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC12_OUT_INV_SEL_S 9 +/* GPIO_FUNC12_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC12_OUT_SEL 0x000001FF +#define GPIO_FUNC12_OUT_SEL_M ((GPIO_FUNC12_OUT_SEL_V)<<(GPIO_FUNC12_OUT_SEL_S)) +#define GPIO_FUNC12_OUT_SEL_V 0x1FF +#define GPIO_FUNC12_OUT_SEL_S 0 + +#define GPIO_FUNC13_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x588) +/* GPIO_FUNC13_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC13_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC13_OEN_INV_SEL_S 11 +/* GPIO_FUNC13_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_OEN_SEL (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC13_OEN_SEL_V 0x1 +#define GPIO_FUNC13_OEN_SEL_S 10 +/* GPIO_FUNC13_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC13_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC13_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC13_OUT_INV_SEL_S 9 +/* GPIO_FUNC13_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC13_OUT_SEL 0x000001FF +#define GPIO_FUNC13_OUT_SEL_M ((GPIO_FUNC13_OUT_SEL_V)<<(GPIO_FUNC13_OUT_SEL_S)) +#define GPIO_FUNC13_OUT_SEL_V 0x1FF +#define GPIO_FUNC13_OUT_SEL_S 0 + +#define GPIO_FUNC14_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x58C) +/* GPIO_FUNC14_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC14_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC14_OEN_INV_SEL_S 11 +/* GPIO_FUNC14_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_OEN_SEL (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC14_OEN_SEL_V 0x1 +#define GPIO_FUNC14_OEN_SEL_S 10 +/* GPIO_FUNC14_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC14_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC14_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC14_OUT_INV_SEL_S 9 +/* GPIO_FUNC14_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC14_OUT_SEL 0x000001FF +#define GPIO_FUNC14_OUT_SEL_M ((GPIO_FUNC14_OUT_SEL_V)<<(GPIO_FUNC14_OUT_SEL_S)) +#define GPIO_FUNC14_OUT_SEL_V 0x1FF +#define GPIO_FUNC14_OUT_SEL_S 0 + +#define GPIO_FUNC15_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x590) +/* GPIO_FUNC15_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC15_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC15_OEN_INV_SEL_S 11 +/* GPIO_FUNC15_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_OEN_SEL (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC15_OEN_SEL_V 0x1 +#define GPIO_FUNC15_OEN_SEL_S 10 +/* GPIO_FUNC15_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC15_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC15_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC15_OUT_INV_SEL_S 9 +/* GPIO_FUNC15_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC15_OUT_SEL 0x000001FF +#define GPIO_FUNC15_OUT_SEL_M ((GPIO_FUNC15_OUT_SEL_V)<<(GPIO_FUNC15_OUT_SEL_S)) +#define GPIO_FUNC15_OUT_SEL_V 0x1FF +#define GPIO_FUNC15_OUT_SEL_S 0 + +#define GPIO_FUNC16_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x594) +/* GPIO_FUNC16_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC16_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC16_OEN_INV_SEL_S 11 +/* GPIO_FUNC16_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_OEN_SEL (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC16_OEN_SEL_V 0x1 +#define GPIO_FUNC16_OEN_SEL_S 10 +/* GPIO_FUNC16_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC16_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC16_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC16_OUT_INV_SEL_S 9 +/* GPIO_FUNC16_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC16_OUT_SEL 0x000001FF +#define GPIO_FUNC16_OUT_SEL_M ((GPIO_FUNC16_OUT_SEL_V)<<(GPIO_FUNC16_OUT_SEL_S)) +#define GPIO_FUNC16_OUT_SEL_V 0x1FF +#define GPIO_FUNC16_OUT_SEL_S 0 + +#define GPIO_FUNC17_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x598) +/* GPIO_FUNC17_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC17_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC17_OEN_INV_SEL_S 11 +/* GPIO_FUNC17_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_OEN_SEL (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC17_OEN_SEL_V 0x1 +#define GPIO_FUNC17_OEN_SEL_S 10 +/* GPIO_FUNC17_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC17_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC17_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC17_OUT_INV_SEL_S 9 +/* GPIO_FUNC17_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC17_OUT_SEL 0x000001FF +#define GPIO_FUNC17_OUT_SEL_M ((GPIO_FUNC17_OUT_SEL_V)<<(GPIO_FUNC17_OUT_SEL_S)) +#define GPIO_FUNC17_OUT_SEL_V 0x1FF +#define GPIO_FUNC17_OUT_SEL_S 0 + +#define GPIO_FUNC18_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x59C) +/* GPIO_FUNC18_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC18_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC18_OEN_INV_SEL_S 11 +/* GPIO_FUNC18_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_OEN_SEL (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC18_OEN_SEL_V 0x1 +#define GPIO_FUNC18_OEN_SEL_S 10 +/* GPIO_FUNC18_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC18_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC18_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC18_OUT_INV_SEL_S 9 +/* GPIO_FUNC18_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC18_OUT_SEL 0x000001FF +#define GPIO_FUNC18_OUT_SEL_M ((GPIO_FUNC18_OUT_SEL_V)<<(GPIO_FUNC18_OUT_SEL_S)) +#define GPIO_FUNC18_OUT_SEL_V 0x1FF +#define GPIO_FUNC18_OUT_SEL_S 0 + +#define GPIO_FUNC19_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A0) +/* GPIO_FUNC19_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC19_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC19_OEN_INV_SEL_S 11 +/* GPIO_FUNC19_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_OEN_SEL (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC19_OEN_SEL_V 0x1 +#define GPIO_FUNC19_OEN_SEL_S 10 +/* GPIO_FUNC19_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC19_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC19_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC19_OUT_INV_SEL_S 9 +/* GPIO_FUNC19_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC19_OUT_SEL 0x000001FF +#define GPIO_FUNC19_OUT_SEL_M ((GPIO_FUNC19_OUT_SEL_V)<<(GPIO_FUNC19_OUT_SEL_S)) +#define GPIO_FUNC19_OUT_SEL_V 0x1FF +#define GPIO_FUNC19_OUT_SEL_S 0 + +#define GPIO_FUNC20_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A4) +/* GPIO_FUNC20_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC20_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC20_OEN_INV_SEL_S 11 +/* GPIO_FUNC20_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_OEN_SEL (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC20_OEN_SEL_V 0x1 +#define GPIO_FUNC20_OEN_SEL_S 10 +/* GPIO_FUNC20_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC20_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC20_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC20_OUT_INV_SEL_S 9 +/* GPIO_FUNC20_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC20_OUT_SEL 0x000001FF +#define GPIO_FUNC20_OUT_SEL_M ((GPIO_FUNC20_OUT_SEL_V)<<(GPIO_FUNC20_OUT_SEL_S)) +#define GPIO_FUNC20_OUT_SEL_V 0x1FF +#define GPIO_FUNC20_OUT_SEL_S 0 + +#define GPIO_FUNC21_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5A8) +/* GPIO_FUNC21_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC21_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC21_OEN_INV_SEL_S 11 +/* GPIO_FUNC21_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_OEN_SEL (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC21_OEN_SEL_V 0x1 +#define GPIO_FUNC21_OEN_SEL_S 10 +/* GPIO_FUNC21_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC21_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC21_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC21_OUT_INV_SEL_S 9 +/* GPIO_FUNC21_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC21_OUT_SEL 0x000001FF +#define GPIO_FUNC21_OUT_SEL_M ((GPIO_FUNC21_OUT_SEL_V)<<(GPIO_FUNC21_OUT_SEL_S)) +#define GPIO_FUNC21_OUT_SEL_V 0x1FF +#define GPIO_FUNC21_OUT_SEL_S 0 + +#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5AC) +/* GPIO_FUNC22_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC22_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC22_OEN_INV_SEL_S 11 +/* GPIO_FUNC22_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_OEN_SEL (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC22_OEN_SEL_V 0x1 +#define GPIO_FUNC22_OEN_SEL_S 10 +/* GPIO_FUNC22_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC22_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC22_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC22_OUT_INV_SEL_S 9 +/* GPIO_FUNC22_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC22_OUT_SEL 0x000001FF +#define GPIO_FUNC22_OUT_SEL_M ((GPIO_FUNC22_OUT_SEL_V)<<(GPIO_FUNC22_OUT_SEL_S)) +#define GPIO_FUNC22_OUT_SEL_V 0x1FF +#define GPIO_FUNC22_OUT_SEL_S 0 + +#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B0) +/* GPIO_FUNC23_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC23_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC23_OEN_INV_SEL_S 11 +/* GPIO_FUNC23_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_OEN_SEL (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC23_OEN_SEL_V 0x1 +#define GPIO_FUNC23_OEN_SEL_S 10 +/* GPIO_FUNC23_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC23_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC23_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC23_OUT_INV_SEL_S 9 +/* GPIO_FUNC23_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC23_OUT_SEL 0x000001FF +#define GPIO_FUNC23_OUT_SEL_M ((GPIO_FUNC23_OUT_SEL_V)<<(GPIO_FUNC23_OUT_SEL_S)) +#define GPIO_FUNC23_OUT_SEL_V 0x1FF +#define GPIO_FUNC23_OUT_SEL_S 0 + +#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B4) +/* GPIO_FUNC24_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC24_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC24_OEN_INV_SEL_S 11 +/* GPIO_FUNC24_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_OEN_SEL (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC24_OEN_SEL_V 0x1 +#define GPIO_FUNC24_OEN_SEL_S 10 +/* GPIO_FUNC24_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC24_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC24_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC24_OUT_INV_SEL_S 9 +/* GPIO_FUNC24_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC24_OUT_SEL 0x000001FF +#define GPIO_FUNC24_OUT_SEL_M ((GPIO_FUNC24_OUT_SEL_V)<<(GPIO_FUNC24_OUT_SEL_S)) +#define GPIO_FUNC24_OUT_SEL_V 0x1FF +#define GPIO_FUNC24_OUT_SEL_S 0 + +#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5B8) +/* GPIO_FUNC25_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC25_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC25_OEN_INV_SEL_S 11 +/* GPIO_FUNC25_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_OEN_SEL (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC25_OEN_SEL_V 0x1 +#define GPIO_FUNC25_OEN_SEL_S 10 +/* GPIO_FUNC25_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC25_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC25_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC25_OUT_INV_SEL_S 9 +/* GPIO_FUNC25_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC25_OUT_SEL 0x000001FF +#define GPIO_FUNC25_OUT_SEL_M ((GPIO_FUNC25_OUT_SEL_V)<<(GPIO_FUNC25_OUT_SEL_S)) +#define GPIO_FUNC25_OUT_SEL_V 0x1FF +#define GPIO_FUNC25_OUT_SEL_S 0 + +#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5BC) +/* GPIO_FUNC26_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC26_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC26_OEN_INV_SEL_S 11 +/* GPIO_FUNC26_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_OEN_SEL (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC26_OEN_SEL_V 0x1 +#define GPIO_FUNC26_OEN_SEL_S 10 +/* GPIO_FUNC26_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC26_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC26_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC26_OUT_INV_SEL_S 9 +/* GPIO_FUNC26_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC26_OUT_SEL 0x000001FF +#define GPIO_FUNC26_OUT_SEL_M ((GPIO_FUNC26_OUT_SEL_V)<<(GPIO_FUNC26_OUT_SEL_S)) +#define GPIO_FUNC26_OUT_SEL_V 0x1FF +#define GPIO_FUNC26_OUT_SEL_S 0 + +#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C0) +/* GPIO_FUNC27_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC27_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC27_OEN_INV_SEL_S 11 +/* GPIO_FUNC27_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_OEN_SEL (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC27_OEN_SEL_V 0x1 +#define GPIO_FUNC27_OEN_SEL_S 10 +/* GPIO_FUNC27_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC27_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC27_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC27_OUT_INV_SEL_S 9 +/* GPIO_FUNC27_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC27_OUT_SEL 0x000001FF +#define GPIO_FUNC27_OUT_SEL_M ((GPIO_FUNC27_OUT_SEL_V)<<(GPIO_FUNC27_OUT_SEL_S)) +#define GPIO_FUNC27_OUT_SEL_V 0x1FF +#define GPIO_FUNC27_OUT_SEL_S 0 + +#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C4) +/* GPIO_FUNC28_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC28_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC28_OEN_INV_SEL_S 11 +/* GPIO_FUNC28_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_OEN_SEL (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC28_OEN_SEL_V 0x1 +#define GPIO_FUNC28_OEN_SEL_S 10 +/* GPIO_FUNC28_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC28_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC28_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC28_OUT_INV_SEL_S 9 +/* GPIO_FUNC28_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC28_OUT_SEL 0x000001FF +#define GPIO_FUNC28_OUT_SEL_M ((GPIO_FUNC28_OUT_SEL_V)<<(GPIO_FUNC28_OUT_SEL_S)) +#define GPIO_FUNC28_OUT_SEL_V 0x1FF +#define GPIO_FUNC28_OUT_SEL_S 0 + +#define GPIO_FUNC29_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5C8) +/* GPIO_FUNC29_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC29_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC29_OEN_INV_SEL_S 11 +/* GPIO_FUNC29_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_OEN_SEL (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC29_OEN_SEL_V 0x1 +#define GPIO_FUNC29_OEN_SEL_S 10 +/* GPIO_FUNC29_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC29_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC29_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC29_OUT_INV_SEL_S 9 +/* GPIO_FUNC29_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC29_OUT_SEL 0x000001FF +#define GPIO_FUNC29_OUT_SEL_M ((GPIO_FUNC29_OUT_SEL_V)<<(GPIO_FUNC29_OUT_SEL_S)) +#define GPIO_FUNC29_OUT_SEL_V 0x1FF +#define GPIO_FUNC29_OUT_SEL_S 0 + +#define GPIO_FUNC30_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5CC) +/* GPIO_FUNC30_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC30_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC30_OEN_INV_SEL_S 11 +/* GPIO_FUNC30_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_OEN_SEL (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC30_OEN_SEL_V 0x1 +#define GPIO_FUNC30_OEN_SEL_S 10 +/* GPIO_FUNC30_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC30_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC30_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC30_OUT_INV_SEL_S 9 +/* GPIO_FUNC30_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC30_OUT_SEL 0x000001FF +#define GPIO_FUNC30_OUT_SEL_M ((GPIO_FUNC30_OUT_SEL_V)<<(GPIO_FUNC30_OUT_SEL_S)) +#define GPIO_FUNC30_OUT_SEL_V 0x1FF +#define GPIO_FUNC30_OUT_SEL_S 0 + +#define GPIO_FUNC31_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D0) +/* GPIO_FUNC31_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC31_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC31_OEN_INV_SEL_S 11 +/* GPIO_FUNC31_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_OEN_SEL (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC31_OEN_SEL_V 0x1 +#define GPIO_FUNC31_OEN_SEL_S 10 +/* GPIO_FUNC31_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC31_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC31_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC31_OUT_INV_SEL_S 9 +/* GPIO_FUNC31_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC31_OUT_SEL 0x000001FF +#define GPIO_FUNC31_OUT_SEL_M ((GPIO_FUNC31_OUT_SEL_V)<<(GPIO_FUNC31_OUT_SEL_S)) +#define GPIO_FUNC31_OUT_SEL_V 0x1FF +#define GPIO_FUNC31_OUT_SEL_S 0 + +#define GPIO_FUNC32_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D4) +/* GPIO_FUNC32_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC32_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC32_OEN_INV_SEL_S 11 +/* GPIO_FUNC32_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_OEN_SEL (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC32_OEN_SEL_V 0x1 +#define GPIO_FUNC32_OEN_SEL_S 10 +/* GPIO_FUNC32_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC32_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC32_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC32_OUT_INV_SEL_S 9 +/* GPIO_FUNC32_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC32_OUT_SEL 0x000001FF +#define GPIO_FUNC32_OUT_SEL_M ((GPIO_FUNC32_OUT_SEL_V)<<(GPIO_FUNC32_OUT_SEL_S)) +#define GPIO_FUNC32_OUT_SEL_V 0x1FF +#define GPIO_FUNC32_OUT_SEL_S 0 + +#define GPIO_FUNC33_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5D8) +/* GPIO_FUNC33_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC33_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC33_OEN_INV_SEL_S 11 +/* GPIO_FUNC33_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_OEN_SEL (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC33_OEN_SEL_V 0x1 +#define GPIO_FUNC33_OEN_SEL_S 10 +/* GPIO_FUNC33_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC33_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC33_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC33_OUT_INV_SEL_S 9 +/* GPIO_FUNC33_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC33_OUT_SEL 0x000001FF +#define GPIO_FUNC33_OUT_SEL_M ((GPIO_FUNC33_OUT_SEL_V)<<(GPIO_FUNC33_OUT_SEL_S)) +#define GPIO_FUNC33_OUT_SEL_V 0x1FF +#define GPIO_FUNC33_OUT_SEL_S 0 + +#define GPIO_FUNC34_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5DC) +/* GPIO_FUNC34_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC34_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC34_OEN_INV_SEL_S 11 +/* GPIO_FUNC34_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_OEN_SEL (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC34_OEN_SEL_V 0x1 +#define GPIO_FUNC34_OEN_SEL_S 10 +/* GPIO_FUNC34_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC34_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC34_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC34_OUT_INV_SEL_S 9 +/* GPIO_FUNC34_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC34_OUT_SEL 0x000001FF +#define GPIO_FUNC34_OUT_SEL_M ((GPIO_FUNC34_OUT_SEL_V)<<(GPIO_FUNC34_OUT_SEL_S)) +#define GPIO_FUNC34_OUT_SEL_V 0x1FF +#define GPIO_FUNC34_OUT_SEL_S 0 + +#define GPIO_FUNC35_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E0) +/* GPIO_FUNC35_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC35_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC35_OEN_INV_SEL_S 11 +/* GPIO_FUNC35_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_OEN_SEL (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC35_OEN_SEL_V 0x1 +#define GPIO_FUNC35_OEN_SEL_S 10 +/* GPIO_FUNC35_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC35_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC35_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC35_OUT_INV_SEL_S 9 +/* GPIO_FUNC35_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC35_OUT_SEL 0x000001FF +#define GPIO_FUNC35_OUT_SEL_M ((GPIO_FUNC35_OUT_SEL_V)<<(GPIO_FUNC35_OUT_SEL_S)) +#define GPIO_FUNC35_OUT_SEL_V 0x1FF +#define GPIO_FUNC35_OUT_SEL_S 0 + +#define GPIO_FUNC36_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E4) +/* GPIO_FUNC36_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC36_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC36_OEN_INV_SEL_S 11 +/* GPIO_FUNC36_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_OEN_SEL (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC36_OEN_SEL_V 0x1 +#define GPIO_FUNC36_OEN_SEL_S 10 +/* GPIO_FUNC36_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC36_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC36_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC36_OUT_INV_SEL_S 9 +/* GPIO_FUNC36_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC36_OUT_SEL 0x000001FF +#define GPIO_FUNC36_OUT_SEL_M ((GPIO_FUNC36_OUT_SEL_V)<<(GPIO_FUNC36_OUT_SEL_S)) +#define GPIO_FUNC36_OUT_SEL_V 0x1FF +#define GPIO_FUNC36_OUT_SEL_S 0 + +#define GPIO_FUNC37_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5E8) +/* GPIO_FUNC37_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC37_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC37_OEN_INV_SEL_S 11 +/* GPIO_FUNC37_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_OEN_SEL (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC37_OEN_SEL_V 0x1 +#define GPIO_FUNC37_OEN_SEL_S 10 +/* GPIO_FUNC37_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC37_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC37_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC37_OUT_INV_SEL_S 9 +/* GPIO_FUNC37_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC37_OUT_SEL 0x000001FF +#define GPIO_FUNC37_OUT_SEL_M ((GPIO_FUNC37_OUT_SEL_V)<<(GPIO_FUNC37_OUT_SEL_S)) +#define GPIO_FUNC37_OUT_SEL_V 0x1FF +#define GPIO_FUNC37_OUT_SEL_S 0 + +#define GPIO_FUNC38_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5EC) +/* GPIO_FUNC38_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC38_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC38_OEN_INV_SEL_S 11 +/* GPIO_FUNC38_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_OEN_SEL (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC38_OEN_SEL_V 0x1 +#define GPIO_FUNC38_OEN_SEL_S 10 +/* GPIO_FUNC38_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC38_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC38_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC38_OUT_INV_SEL_S 9 +/* GPIO_FUNC38_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC38_OUT_SEL 0x000001FF +#define GPIO_FUNC38_OUT_SEL_M ((GPIO_FUNC38_OUT_SEL_V)<<(GPIO_FUNC38_OUT_SEL_S)) +#define GPIO_FUNC38_OUT_SEL_V 0x1FF +#define GPIO_FUNC38_OUT_SEL_S 0 + +#define GPIO_FUNC39_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F0) +/* GPIO_FUNC39_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC39_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC39_OEN_INV_SEL_S 11 +/* GPIO_FUNC39_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_OEN_SEL (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC39_OEN_SEL_V 0x1 +#define GPIO_FUNC39_OEN_SEL_S 10 +/* GPIO_FUNC39_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC39_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC39_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC39_OUT_INV_SEL_S 9 +/* GPIO_FUNC39_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC39_OUT_SEL 0x000001FF +#define GPIO_FUNC39_OUT_SEL_M ((GPIO_FUNC39_OUT_SEL_V)<<(GPIO_FUNC39_OUT_SEL_S)) +#define GPIO_FUNC39_OUT_SEL_V 0x1FF +#define GPIO_FUNC39_OUT_SEL_S 0 + +#define GPIO_FUNC40_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F4) +/* GPIO_FUNC40_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC40_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC40_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC40_OEN_INV_SEL_S 11 +/* GPIO_FUNC40_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_OEN_SEL (BIT(10)) +#define GPIO_FUNC40_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC40_OEN_SEL_V 0x1 +#define GPIO_FUNC40_OEN_SEL_S 10 +/* GPIO_FUNC40_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC40_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC40_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC40_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC40_OUT_INV_SEL_S 9 +/* GPIO_FUNC40_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC40_OUT_SEL 0x000001FF +#define GPIO_FUNC40_OUT_SEL_M ((GPIO_FUNC40_OUT_SEL_V)<<(GPIO_FUNC40_OUT_SEL_S)) +#define GPIO_FUNC40_OUT_SEL_V 0x1FF +#define GPIO_FUNC40_OUT_SEL_S 0 + +#define GPIO_FUNC41_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5F8) +/* GPIO_FUNC41_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC41_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC41_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC41_OEN_INV_SEL_S 11 +/* GPIO_FUNC41_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_OEN_SEL (BIT(10)) +#define GPIO_FUNC41_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC41_OEN_SEL_V 0x1 +#define GPIO_FUNC41_OEN_SEL_S 10 +/* GPIO_FUNC41_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC41_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC41_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC41_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC41_OUT_INV_SEL_S 9 +/* GPIO_FUNC41_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC41_OUT_SEL 0x000001FF +#define GPIO_FUNC41_OUT_SEL_M ((GPIO_FUNC41_OUT_SEL_V)<<(GPIO_FUNC41_OUT_SEL_S)) +#define GPIO_FUNC41_OUT_SEL_V 0x1FF +#define GPIO_FUNC41_OUT_SEL_S 0 + +#define GPIO_FUNC42_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x5FC) +/* GPIO_FUNC42_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC42_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC42_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC42_OEN_INV_SEL_S 11 +/* GPIO_FUNC42_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_OEN_SEL (BIT(10)) +#define GPIO_FUNC42_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC42_OEN_SEL_V 0x1 +#define GPIO_FUNC42_OEN_SEL_S 10 +/* GPIO_FUNC42_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC42_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC42_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC42_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC42_OUT_INV_SEL_S 9 +/* GPIO_FUNC42_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC42_OUT_SEL 0x000001FF +#define GPIO_FUNC42_OUT_SEL_M ((GPIO_FUNC42_OUT_SEL_V)<<(GPIO_FUNC42_OUT_SEL_S)) +#define GPIO_FUNC42_OUT_SEL_V 0x1FF +#define GPIO_FUNC42_OUT_SEL_S 0 + +#define GPIO_FUNC43_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x600) +/* GPIO_FUNC43_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC43_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC43_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC43_OEN_INV_SEL_S 11 +/* GPIO_FUNC43_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_OEN_SEL (BIT(10)) +#define GPIO_FUNC43_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC43_OEN_SEL_V 0x1 +#define GPIO_FUNC43_OEN_SEL_S 10 +/* GPIO_FUNC43_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC43_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC43_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC43_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC43_OUT_INV_SEL_S 9 +/* GPIO_FUNC43_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC43_OUT_SEL 0x000001FF +#define GPIO_FUNC43_OUT_SEL_M ((GPIO_FUNC43_OUT_SEL_V)<<(GPIO_FUNC43_OUT_SEL_S)) +#define GPIO_FUNC43_OUT_SEL_V 0x1FF +#define GPIO_FUNC43_OUT_SEL_S 0 + +#define GPIO_FUNC44_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x604) +/* GPIO_FUNC44_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC44_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC44_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC44_OEN_INV_SEL_S 11 +/* GPIO_FUNC44_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_OEN_SEL (BIT(10)) +#define GPIO_FUNC44_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC44_OEN_SEL_V 0x1 +#define GPIO_FUNC44_OEN_SEL_S 10 +/* GPIO_FUNC44_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC44_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC44_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC44_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC44_OUT_INV_SEL_S 9 +/* GPIO_FUNC44_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC44_OUT_SEL 0x000001FF +#define GPIO_FUNC44_OUT_SEL_M ((GPIO_FUNC44_OUT_SEL_V)<<(GPIO_FUNC44_OUT_SEL_S)) +#define GPIO_FUNC44_OUT_SEL_V 0x1FF +#define GPIO_FUNC44_OUT_SEL_S 0 + +#define GPIO_FUNC45_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x608) +/* GPIO_FUNC45_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC45_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC45_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC45_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC45_OEN_INV_SEL_S 11 +/* GPIO_FUNC45_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC45_OEN_SEL (BIT(10)) +#define GPIO_FUNC45_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC45_OEN_SEL_V 0x1 +#define GPIO_FUNC45_OEN_SEL_S 10 +/* GPIO_FUNC45_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC45_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC45_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC45_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC45_OUT_INV_SEL_S 9 +/* GPIO_FUNC45_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC45_OUT_SEL 0x000001FF +#define GPIO_FUNC45_OUT_SEL_M ((GPIO_FUNC45_OUT_SEL_V)<<(GPIO_FUNC45_OUT_SEL_S)) +#define GPIO_FUNC45_OUT_SEL_V 0x1FF +#define GPIO_FUNC45_OUT_SEL_S 0 + +#define GPIO_FUNC46_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x60C) +/* GPIO_FUNC46_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC46_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC46_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC46_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC46_OEN_INV_SEL_S 11 +/* GPIO_FUNC46_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC46_OEN_SEL (BIT(10)) +#define GPIO_FUNC46_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC46_OEN_SEL_V 0x1 +#define GPIO_FUNC46_OEN_SEL_S 10 +/* GPIO_FUNC46_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC46_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC46_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC46_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC46_OUT_INV_SEL_S 9 +/* GPIO_FUNC46_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC46_OUT_SEL 0x000001FF +#define GPIO_FUNC46_OUT_SEL_M ((GPIO_FUNC46_OUT_SEL_V)<<(GPIO_FUNC46_OUT_SEL_S)) +#define GPIO_FUNC46_OUT_SEL_V 0x1FF +#define GPIO_FUNC46_OUT_SEL_S 0 + +#define GPIO_FUNC47_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x610) +/* GPIO_FUNC47_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC47_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC47_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC47_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC47_OEN_INV_SEL_S 11 +/* GPIO_FUNC47_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC47_OEN_SEL (BIT(10)) +#define GPIO_FUNC47_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC47_OEN_SEL_V 0x1 +#define GPIO_FUNC47_OEN_SEL_S 10 +/* GPIO_FUNC47_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC47_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC47_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC47_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC47_OUT_INV_SEL_S 9 +/* GPIO_FUNC47_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC47_OUT_SEL 0x000001FF +#define GPIO_FUNC47_OUT_SEL_M ((GPIO_FUNC47_OUT_SEL_V)<<(GPIO_FUNC47_OUT_SEL_S)) +#define GPIO_FUNC47_OUT_SEL_V 0x1FF +#define GPIO_FUNC47_OUT_SEL_S 0 + +#define GPIO_FUNC48_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x614) +/* GPIO_FUNC48_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC48_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC48_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC48_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC48_OEN_INV_SEL_S 11 +/* GPIO_FUNC48_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC48_OEN_SEL (BIT(10)) +#define GPIO_FUNC48_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC48_OEN_SEL_V 0x1 +#define GPIO_FUNC48_OEN_SEL_S 10 +/* GPIO_FUNC48_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC48_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC48_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC48_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC48_OUT_INV_SEL_S 9 +/* GPIO_FUNC48_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC48_OUT_SEL 0x000001FF +#define GPIO_FUNC48_OUT_SEL_M ((GPIO_FUNC48_OUT_SEL_V)<<(GPIO_FUNC48_OUT_SEL_S)) +#define GPIO_FUNC48_OUT_SEL_V 0x1FF +#define GPIO_FUNC48_OUT_SEL_S 0 + +#define GPIO_FUNC49_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x618) +/* GPIO_FUNC49_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC49_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC49_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC49_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC49_OEN_INV_SEL_S 11 +/* GPIO_FUNC49_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC49_OEN_SEL (BIT(10)) +#define GPIO_FUNC49_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC49_OEN_SEL_V 0x1 +#define GPIO_FUNC49_OEN_SEL_S 10 +/* GPIO_FUNC49_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC49_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC49_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC49_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC49_OUT_INV_SEL_S 9 +/* GPIO_FUNC49_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC49_OUT_SEL 0x000001FF +#define GPIO_FUNC49_OUT_SEL_M ((GPIO_FUNC49_OUT_SEL_V)<<(GPIO_FUNC49_OUT_SEL_S)) +#define GPIO_FUNC49_OUT_SEL_V 0x1FF +#define GPIO_FUNC49_OUT_SEL_S 0 + +#define GPIO_FUNC50_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x61C) +/* GPIO_FUNC50_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC50_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC50_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC50_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC50_OEN_INV_SEL_S 11 +/* GPIO_FUNC50_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC50_OEN_SEL (BIT(10)) +#define GPIO_FUNC50_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC50_OEN_SEL_V 0x1 +#define GPIO_FUNC50_OEN_SEL_S 10 +/* GPIO_FUNC50_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC50_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC50_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC50_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC50_OUT_INV_SEL_S 9 +/* GPIO_FUNC50_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC50_OUT_SEL 0x000001FF +#define GPIO_FUNC50_OUT_SEL_M ((GPIO_FUNC50_OUT_SEL_V)<<(GPIO_FUNC50_OUT_SEL_S)) +#define GPIO_FUNC50_OUT_SEL_V 0x1FF +#define GPIO_FUNC50_OUT_SEL_S 0 + +#define GPIO_FUNC51_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x620) +/* GPIO_FUNC51_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC51_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC51_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC51_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC51_OEN_INV_SEL_S 11 +/* GPIO_FUNC51_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC51_OEN_SEL (BIT(10)) +#define GPIO_FUNC51_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC51_OEN_SEL_V 0x1 +#define GPIO_FUNC51_OEN_SEL_S 10 +/* GPIO_FUNC51_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC51_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC51_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC51_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC51_OUT_INV_SEL_S 9 +/* GPIO_FUNC51_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC51_OUT_SEL 0x000001FF +#define GPIO_FUNC51_OUT_SEL_M ((GPIO_FUNC51_OUT_SEL_V)<<(GPIO_FUNC51_OUT_SEL_S)) +#define GPIO_FUNC51_OUT_SEL_V 0x1FF +#define GPIO_FUNC51_OUT_SEL_S 0 + +#define GPIO_FUNC52_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x624) +/* GPIO_FUNC52_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC52_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC52_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC52_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC52_OEN_INV_SEL_S 11 +/* GPIO_FUNC52_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC52_OEN_SEL (BIT(10)) +#define GPIO_FUNC52_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC52_OEN_SEL_V 0x1 +#define GPIO_FUNC52_OEN_SEL_S 10 +/* GPIO_FUNC52_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC52_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC52_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC52_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC52_OUT_INV_SEL_S 9 +/* GPIO_FUNC52_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC52_OUT_SEL 0x000001FF +#define GPIO_FUNC52_OUT_SEL_M ((GPIO_FUNC52_OUT_SEL_V)<<(GPIO_FUNC52_OUT_SEL_S)) +#define GPIO_FUNC52_OUT_SEL_V 0x1FF +#define GPIO_FUNC52_OUT_SEL_S 0 + +#define GPIO_FUNC53_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0x628) +/* GPIO_FUNC53_OEN_INV_SEL : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC53_OEN_INV_SEL (BIT(11)) +#define GPIO_FUNC53_OEN_INV_SEL_M (BIT(11)) +#define GPIO_FUNC53_OEN_INV_SEL_V 0x1 +#define GPIO_FUNC53_OEN_INV_SEL_S 11 +/* GPIO_FUNC53_OEN_SEL : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC53_OEN_SEL (BIT(10)) +#define GPIO_FUNC53_OEN_SEL_M (BIT(10)) +#define GPIO_FUNC53_OEN_SEL_V 0x1 +#define GPIO_FUNC53_OEN_SEL_S 10 +/* GPIO_FUNC53_OUT_INV_SEL : R/W ;bitpos:[9] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_FUNC53_OUT_INV_SEL (BIT(9)) +#define GPIO_FUNC53_OUT_INV_SEL_M (BIT(9)) +#define GPIO_FUNC53_OUT_INV_SEL_V 0x1 +#define GPIO_FUNC53_OUT_INV_SEL_S 9 +/* GPIO_FUNC53_OUT_SEL : R/W ;bitpos:[8:0] ;default: 9'h100 ; */ +/*description: */ +#define GPIO_FUNC53_OUT_SEL 0x000001FF +#define GPIO_FUNC53_OUT_SEL_M ((GPIO_FUNC53_OUT_SEL_V)<<(GPIO_FUNC53_OUT_SEL_S)) +#define GPIO_FUNC53_OUT_SEL_V 0x1FF +#define GPIO_FUNC53_OUT_SEL_S 0 + +#define GPIO_CLOCK_GATE_REG (DR_REG_GPIO_BASE + 0x62C) +/* GPIO_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define GPIO_CLK_EN (BIT(0)) +#define GPIO_CLK_EN_M (BIT(0)) +#define GPIO_CLK_EN_V 0x1 +#define GPIO_CLK_EN_S 0 + +#define GPIO_DATE_REG (DR_REG_GPIO_BASE + 0x6FC) +/* GPIO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1907040 ; */ +/*description: */ +#define GPIO_DATE 0x0FFFFFFF +#define GPIO_DATE_M ((GPIO_DATE_V)<<(GPIO_DATE_S)) +#define GPIO_DATE_V 0xFFFFFFF +#define GPIO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/gpio_sd_reg.h b/components/soc/soc/esp32s3/include/soc/gpio_sd_reg.h new file mode 100644 index 000000000..625a06c33 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/gpio_sd_reg.h @@ -0,0 +1,166 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define GPIO_SIGMADELTA0_REG (DR_REG_GPIO_SD_BASE + 0x0000) +/* GPIO_SD0_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD0_PRESCALE 0x000000FF +#define GPIO_SD0_PRESCALE_M ((GPIO_SD0_PRESCALE_V) << (GPIO_SD0_PRESCALE_S)) +#define GPIO_SD0_PRESCALE_V 0xFF +#define GPIO_SD0_PRESCALE_S 8 +/* GPIO_SD0_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD0_IN 0x000000FF +#define GPIO_SD0_IN_M ((GPIO_SD0_IN_V) << (GPIO_SD0_IN_S)) +#define GPIO_SD0_IN_V 0xFF +#define GPIO_SD0_IN_S 0 + +#define GPIO_SIGMADELTA1_REG (DR_REG_GPIO_SD_BASE + 0x0004) +/* GPIO_SD1_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD1_PRESCALE 0x000000FF +#define GPIO_SD1_PRESCALE_M ((GPIO_SD1_PRESCALE_V) << (GPIO_SD1_PRESCALE_S)) +#define GPIO_SD1_PRESCALE_V 0xFF +#define GPIO_SD1_PRESCALE_S 8 +/* GPIO_SD1_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD1_IN 0x000000FF +#define GPIO_SD1_IN_M ((GPIO_SD1_IN_V) << (GPIO_SD1_IN_S)) +#define GPIO_SD1_IN_V 0xFF +#define GPIO_SD1_IN_S 0 + +#define GPIO_SIGMADELTA2_REG (DR_REG_GPIO_SD_BASE + 0x0008) +/* GPIO_SD2_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD2_PRESCALE 0x000000FF +#define GPIO_SD2_PRESCALE_M ((GPIO_SD2_PRESCALE_V) << (GPIO_SD2_PRESCALE_S)) +#define GPIO_SD2_PRESCALE_V 0xFF +#define GPIO_SD2_PRESCALE_S 8 +/* GPIO_SD2_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD2_IN 0x000000FF +#define GPIO_SD2_IN_M ((GPIO_SD2_IN_V) << (GPIO_SD2_IN_S)) +#define GPIO_SD2_IN_V 0xFF +#define GPIO_SD2_IN_S 0 + +#define GPIO_SIGMADELTA3_REG (DR_REG_GPIO_SD_BASE + 0x000c) +/* GPIO_SD3_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD3_PRESCALE 0x000000FF +#define GPIO_SD3_PRESCALE_M ((GPIO_SD3_PRESCALE_V) << (GPIO_SD3_PRESCALE_S)) +#define GPIO_SD3_PRESCALE_V 0xFF +#define GPIO_SD3_PRESCALE_S 8 +/* GPIO_SD3_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD3_IN 0x000000FF +#define GPIO_SD3_IN_M ((GPIO_SD3_IN_V) << (GPIO_SD3_IN_S)) +#define GPIO_SD3_IN_V 0xFF +#define GPIO_SD3_IN_S 0 + +#define GPIO_SIGMADELTA4_REG (DR_REG_GPIO_SD_BASE + 0x0010) +/* GPIO_SD4_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD4_PRESCALE 0x000000FF +#define GPIO_SD4_PRESCALE_M ((GPIO_SD4_PRESCALE_V) << (GPIO_SD4_PRESCALE_S)) +#define GPIO_SD4_PRESCALE_V 0xFF +#define GPIO_SD4_PRESCALE_S 8 +/* GPIO_SD4_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD4_IN 0x000000FF +#define GPIO_SD4_IN_M ((GPIO_SD4_IN_V) << (GPIO_SD4_IN_S)) +#define GPIO_SD4_IN_V 0xFF +#define GPIO_SD4_IN_S 0 + +#define GPIO_SIGMADELTA5_REG (DR_REG_GPIO_SD_BASE + 0x0014) +/* GPIO_SD5_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD5_PRESCALE 0x000000FF +#define GPIO_SD5_PRESCALE_M ((GPIO_SD5_PRESCALE_V) << (GPIO_SD5_PRESCALE_S)) +#define GPIO_SD5_PRESCALE_V 0xFF +#define GPIO_SD5_PRESCALE_S 8 +/* GPIO_SD5_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD5_IN 0x000000FF +#define GPIO_SD5_IN_M ((GPIO_SD5_IN_V) << (GPIO_SD5_IN_S)) +#define GPIO_SD5_IN_V 0xFF +#define GPIO_SD5_IN_S 0 + +#define GPIO_SIGMADELTA6_REG (DR_REG_GPIO_SD_BASE + 0x0018) +/* GPIO_SD6_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD6_PRESCALE 0x000000FF +#define GPIO_SD6_PRESCALE_M ((GPIO_SD6_PRESCALE_V) << (GPIO_SD6_PRESCALE_S)) +#define GPIO_SD6_PRESCALE_V 0xFF +#define GPIO_SD6_PRESCALE_S 8 +/* GPIO_SD6_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD6_IN 0x000000FF +#define GPIO_SD6_IN_M ((GPIO_SD6_IN_V) << (GPIO_SD6_IN_S)) +#define GPIO_SD6_IN_V 0xFF +#define GPIO_SD6_IN_S 0 + +#define GPIO_SIGMADELTA7_REG (DR_REG_GPIO_SD_BASE + 0x001c) +/* GPIO_SD7_PRESCALE : R/W ;bitpos:[15:8] ;default: 8'hff ; */ +/*description: */ +#define GPIO_SD7_PRESCALE 0x000000FF +#define GPIO_SD7_PRESCALE_M ((GPIO_SD7_PRESCALE_V) << (GPIO_SD7_PRESCALE_S)) +#define GPIO_SD7_PRESCALE_V 0xFF +#define GPIO_SD7_PRESCALE_S 8 +/* GPIO_SD7_IN : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define GPIO_SD7_IN 0x000000FF +#define GPIO_SD7_IN_M ((GPIO_SD7_IN_V) << (GPIO_SD7_IN_S)) +#define GPIO_SD7_IN_V 0xFF +#define GPIO_SD7_IN_S 0 + +#define GPIO_SIGMADELTA_CG_REG (DR_REG_GPIO_SD_BASE + 0x0020) +/* GPIO_SD_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SD_CLK_EN (BIT(31)) +#define GPIO_SD_CLK_EN_M (BIT(31)) +#define GPIO_SD_CLK_EN_V 0x1 +#define GPIO_SD_CLK_EN_S 31 + +#define GPIO_SIGMADELTA_MISC_REG (DR_REG_GPIO_SD_BASE + 0x0024) +/* GPIO_SPI_SWAP : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define GPIO_SPI_SWAP (BIT(31)) +#define GPIO_SPI_SWAP_M (BIT(31)) +#define GPIO_SPI_SWAP_V 0x1 +#define GPIO_SPI_SWAP_S 31 +/* GPIO_FUNCTION_CLK_EN : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: */ +#define GPIO_FUNCTION_CLK_EN (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_M (BIT(30)) +#define GPIO_FUNCTION_CLK_EN_V 0x1 +#define GPIO_FUNCTION_CLK_EN_S 30 + +#define GPIO_SIGMADELTA_VERSION_REG (DR_REG_GPIO_SD_BASE + 0x0028) +/* GPIO_SD_DATE : R/W ;bitpos:[27:0] ;default: 28'h1802260 ; */ +/*description: */ +#define GPIO_SD_DATE 0x0FFFFFFF +#define GPIO_SD_DATE_M ((GPIO_SD_DATE_V) << (GPIO_SD_DATE_S)) +#define GPIO_SD_DATE_V 0xFFFFFFF +#define GPIO_SD_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/gpio_sd_struct.h b/components/soc/soc/esp32s3/include/soc/gpio_sd_struct.h new file mode 100644 index 000000000..43d9a8030 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/gpio_sd_struct.h @@ -0,0 +1,59 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t duty: 8; + uint32_t prescale: 8; + uint32_t reserved16: 16; + }; + uint32_t val; + } channel[8]; + union { + struct { + uint32_t reserved0: 31; + uint32_t clk_en: 1; + }; + uint32_t val; + } cg; + union { + struct { + uint32_t reserved0: 30; + uint32_t function_clk_en: 1; + uint32_t spi_swap: 1; + }; + uint32_t val; + } misc; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } version; +} gpio_sd_dev_t; + +extern gpio_sd_dev_t SIGMADELTA; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/gpio_sig_map.h b/components/soc/soc/esp32s3/include/soc/gpio_sig_map.h new file mode 100644 index 000000000..5f8162e24 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/gpio_sig_map.h @@ -0,0 +1,433 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#define SPIQ_IN_IDX 0 +#define SPIQ_OUT_IDX 0 +#define SPID_IN_IDX 1 +#define SPID_OUT_IDX 1 +#define SPIHD_IN_IDX 2 +#define SPIHD_OUT_IDX 2 +#define SPIWP_IN_IDX 3 +#define SPIWP_OUT_IDX 3 +#define SPICLK_OUT_IDX 4 +#define SPICS0_OUT_IDX 5 +#define SPICS1_OUT_IDX 6 +#define SPID4_IN_IDX 7 +#define SPID4_OUT_IDX 7 +#define SPID5_IN_IDX 8 +#define SPID5_OUT_IDX 8 +#define SPID6_IN_IDX 9 +#define SPID6_OUT_IDX 9 +#define SPID7_IN_IDX 10 +#define SPID7_OUT_IDX 10 +#define SPIDQS_IN_IDX 11 +#define SPIDQS_OUT_IDX 11 +#define U0RXD_IN_IDX 12 +#define U0TXD_OUT_IDX 12 +#define U0CTS_IN_IDX 13 +#define U0RTS_OUT_IDX 13 +#define U0DSR_IN_IDX 14 +#define U0DTR_OUT_IDX 14 +#define U1RXD_IN_IDX 15 +#define U1TXD_OUT_IDX 15 +#define U1CTS_IN_IDX 16 +#define U1RTS_OUT_IDX 16 +#define U1DSR_IN_IDX 17 +#define U1DTR_OUT_IDX 17 +#define U2RXD_IN_IDX 18 +#define U2TXD_OUT_IDX 18 +#define U2CTS_IN_IDX 19 +#define U2RTS_OUT_IDX 19 +#define U2DSR_IN_IDX 20 +#define U2DTR_OUT_IDX 20 +#define I2S1_MCLK_IN_IDX 21 +#define I2S1_MCLK_OUT_IDX 21 +#define I2S0O_BCK_IN_IDX 22 +#define I2S0O_BCK_OUT_IDX 22 +#define I2S0_MCLK_IN_IDX 23 +#define I2S0_MCLK_OUT_IDX 23 +#define I2S0O_WS_IN_IDX 24 +#define I2S0O_WS_OUT_IDX 24 +#define I2S0I_SD_IN_IDX 25 +#define I2S0O_SD_OUT_IDX 25 +#define I2S0I_BCK_IN_IDX 26 +#define I2S0I_BCK_OUT_IDX 26 +#define I2S0I_WS_IN_IDX 27 +#define I2S0I_WS_OUT_IDX 27 +#define I2S1O_BCK_IN_IDX 28 +#define I2S1O_BCK_OUT_IDX 28 +#define I2S1O_WS_IN_IDX 29 +#define I2S1O_WS_OUT_IDX 29 +#define I2S1I_SD_IN_IDX 30 +#define I2S1O_SD_OUT_IDX 30 +#define I2S1I_BCK_IN_IDX 31 +#define I2S1I_BCK_OUT_IDX 31 +#define I2S1I_WS_IN_IDX 32 +#define I2S1I_WS_OUT_IDX 32 +#define PCNT_SIG_CH0_IN0_IDX 33 +#define GPIO_WLAN_PRIO_IDX 33 +#define PCNT_SIG_CH1_IN0_IDX 34 +#define GPIO_WLAN_ACTIVE_IDX 34 +#define PCNT_CTRL_CH0_IN0_IDX 35 +#define BB_DIAG0_IDX 35 +#define PCNT_CTRL_CH1_IN0_IDX 36 +#define BB_DIAG1_IDX 36 +#define PCNT_SIG_CH0_IN1_IDX 37 +#define BB_DIAG2_IDX 37 +#define PCNT_SIG_CH1_IN1_IDX 38 +#define BB_DIAG3_IDX 38 +#define PCNT_CTRL_CH0_IN1_IDX 39 +#define BB_DIAG4_IDX 39 +#define PCNT_CTRL_CH1_IN1_IDX 40 +#define BB_DIAG5_IDX 40 +#define PCNT_SIG_CH0_IN2_IDX 41 +#define BB_DIAG6_IDX 41 +#define PCNT_SIG_CH1_IN2_IDX 42 +#define BB_DIAG7_IDX 42 +#define PCNT_CTRL_CH0_IN2_IDX 43 +#define BB_DIAG8_IDX 43 +#define PCNT_CTRL_CH1_IN2_IDX 44 +#define BB_DIAG9_IDX 44 +#define PCNT_SIG_CH0_IN3_IDX 45 +#define BB_DIAG10_IDX 45 +#define PCNT_SIG_CH1_IN3_IDX 46 +#define BB_DIAG11_IDX 46 +#define PCNT_CTRL_CH0_IN3_IDX 47 +#define BB_DIAG12_IDX 47 +#define PCNT_CTRL_CH1_IN3_IDX 48 +#define BB_DIAG13_IDX 48 +#define GPIO_BT_ACTIVE_IDX 49 +#define BB_DIAG14_IDX 49 +#define GPIO_BT_PRIORITY_IDX 50 +#define BB_DIAG15_IDX 50 +#define I2S0I_SD1_IN_IDX 51 +#define BB_DIAG16_IDX 51 +#define I2S0I_SD2_IN_IDX 52 +#define BB_DIAG17_IDX 52 +#define I2S0I_SD3_IN_IDX 53 +#define BB_DIAG18_IDX 53 +#define BB_DIAG19_IDX 54 +#define USB_EXTPHY_VP_IDX 55 +#define USB_EXTPHY_OEN_IDX 55 +#define USB_EXTPHY_VM_IDX 56 +#define USB_EXTPHY_SPEED_IDX 56 +#define USB_EXTPHY_RCV_IDX 57 +#define USB_EXTPHY_VPO_IDX 57 +#define USB_OTG_IDDIG_IN_IDX 58 +#define USB_EXTPHY_VMO_IDX 58 +#define USB_OTG_AVALID_IN_IDX 59 +#define USB_EXTPHY_SUSPND_IDX 59 +#define USB_SRP_BVALID_IN_IDX 60 +#define USB_OTG_IDPULLUP_IDX 60 +#define USB_OTG_VBUSVALID_IN_IDX 61 +#define USB_OTG_DPPULLDOWN_IDX 61 +#define USB_SRP_SESSEND_IN_IDX 62 +#define USB_OTG_DMPULLDOWN_IDX 62 +#define USB_OTG_DRVVBUS_IDX 63 +#define USB_SRP_CHRGVBUS_IDX 64 +#define USB_SRP_DISCHRGVBUS_IDX 65 +#define SPI3_CLK_IN_IDX 66 +#define SPI3_CLK_OUT_IDX 66 +#define SPI3_Q_IN_IDX 67 +#define SPI3_Q_OUT_IDX 67 +#define SPI3_D_IN_IDX 68 +#define SPI3_D_OUT_IDX 68 +#define SPI3_HD_IN_IDX 69 +#define SPI3_HD_OUT_IDX 69 +#define SPI3_WP_IN_IDX 70 +#define SPI3_WP_OUT_IDX 70 +#define SPI3_CS0_IN_IDX 71 +#define SPI3_CS0_OUT_IDX 71 +#define SPI3_CS1_OUT_IDX 72 +#define EXT_ADC_START_IDX 73 +#define LEDC_LS_SIG_OUT0_IDX 73 +#define LEDC_LS_SIG_OUT1_IDX 74 +#define LEDC_LS_SIG_OUT2_IDX 75 +#define LEDC_LS_SIG_OUT3_IDX 76 +#define LEDC_LS_SIG_OUT4_IDX 77 +#define LEDC_LS_SIG_OUT5_IDX 78 +#define LEDC_LS_SIG_OUT6_IDX 79 +#define LEDC_LS_SIG_OUT7_IDX 80 +#define RMT_SIG_IN0_IDX 81 +#define RMT_SIG_OUT0_IDX 81 +#define RMT_SIG_IN1_IDX 82 +#define RMT_SIG_OUT1_IDX 82 +#define RMT_SIG_IN2_IDX 83 +#define RMT_SIG_OUT2_IDX 83 +#define RMT_SIG_IN3_IDX 84 +#define RMT_SIG_OUT3_IDX 84 +#define I2CEXT0_SCL_IN_IDX 89 +#define I2CEXT0_SCL_OUT_IDX 89 +#define I2CEXT0_SDA_IN_IDX 90 +#define I2CEXT0_SDA_OUT_IDX 90 +#define I2CEXT1_SCL_IN_IDX 91 +#define I2CEXT1_SCL_OUT_IDX 91 +#define I2CEXT1_SDA_IN_IDX 92 +#define I2CEXT1_SDA_OUT_IDX 92 +#define GPIO_SD0_OUT_IDX 93 +#define GPIO_SD1_OUT_IDX 94 +#define GPIO_SD2_OUT_IDX 95 +#define GPIO_SD3_OUT_IDX 96 +#define GPIO_SD4_OUT_IDX 97 +#define GPIO_SD5_OUT_IDX 98 +#define GPIO_SD6_OUT_IDX 99 +#define GPIO_SD7_OUT_IDX 100 +#define FSPICLK_IN_IDX 101 +#define FSPICLK_OUT_IDX 101 +#define FSPIQ_IN_IDX 102 +#define FSPIQ_OUT_IDX 102 +#define FSPID_IN_IDX 103 +#define FSPID_OUT_IDX 103 +#define FSPIHD_IN_IDX 104 +#define FSPIHD_OUT_IDX 104 +#define FSPIWP_IN_IDX 105 +#define FSPIWP_OUT_IDX 105 +#define FSPIIO4_IN_IDX 106 +#define FSPIIO4_OUT_IDX 106 +#define FSPIIO5_IN_IDX 107 +#define FSPIIO5_OUT_IDX 107 +#define FSPIIO6_IN_IDX 108 +#define FSPIIO6_OUT_IDX 108 +#define FSPIIO7_IN_IDX 109 +#define FSPIIO7_OUT_IDX 109 +#define FSPICS0_IN_IDX 110 +#define FSPICS0_OUT_IDX 110 +#define FSPICS1_OUT_IDX 111 +#define FSPICS2_OUT_IDX 112 +#define FSPICS3_OUT_IDX 113 +#define FSPICS4_OUT_IDX 114 +#define FSPICS5_OUT_IDX 115 +#define TWAI_RX_IDX 116 +#define TWAI_TX_IDX 116 +#define TWAI_BUS_OFF_ON_IDX 117 +#define TWAI_CLKOUT_IDX 118 +#define SUBSPICLK_OUT_IDX 119 +#define SUBSPIQ_IN_IDX 120 +#define SUBSPIQ_OUT_IDX 120 +#define SUBSPID_IN_IDX 121 +#define SUBSPID_OUT_IDX 121 +#define SUBSPIHD_IN_IDX 122 +#define SUBSPIHD_OUT_IDX 122 +#define SUBSPIWP_IN_IDX 123 +#define SUBSPIWP_OUT_IDX 123 +#define SUBSPICS0_OUT_IDX 124 +#define SUBSPICS1_OUT_IDX 125 +#define FSPIDQS_OUT_IDX 126 +#define SPI3_CS2_OUT_IDX 127 +#define LCD_CS_IDX 132 +#define CAM_DATA_IN0_IDX 133 +#define LCD_DATA_OUT0_IDX 133 +#define CAM_DATA_IN1_IDX 134 +#define LCD_DATA_OUT1_IDX 134 +#define CAM_DATA_IN2_IDX 135 +#define LCD_DATA_OUT2_IDX 135 +#define CAM_DATA_IN3_IDX 136 +#define LCD_DATA_OUT3_IDX 136 +#define CAM_DATA_IN4_IDX 137 +#define LCD_DATA_OUT4_IDX 137 +#define CAM_DATA_IN5_IDX 138 +#define LCD_DATA_OUT5_IDX 138 +#define CAM_DATA_IN6_IDX 139 +#define LCD_DATA_OUT6_IDX 139 +#define CAM_DATA_IN7_IDX 140 +#define LCD_DATA_OUT7_IDX 140 +#define CAM_DATA_IN8_IDX 141 +#define LCD_DATA_OUT8_IDX 141 +#define CAM_DATA_IN9_IDX 142 +#define LCD_DATA_OUT9_IDX 142 +#define CAM_DATA_IN10_IDX 143 +#define LCD_DATA_OUT10_IDX 143 +#define CAM_DATA_IN11_IDX 144 +#define LCD_DATA_OUT11_IDX 144 +#define CAM_DATA_IN12_IDX 145 +#define LCD_DATA_OUT12_IDX 145 +#define CAM_DATA_IN13_IDX 146 +#define LCD_DATA_OUT13_IDX 146 +#define CAM_DATA_IN14_IDX 147 +#define LCD_DATA_OUT14_IDX 147 +#define CAM_DATA_IN15_IDX 148 +#define LCD_DATA_OUT15_IDX 148 +#define CAM_PCLK_IDX 149 +#define CAM_CLK_IDX 149 +#define CAM_H_ENABLE_IDX 150 +#define LCD_H_ENABLE_IDX 150 +#define CAM_H_SYNC_IDX 151 +#define LCD_H_SYNC_IDX 151 +#define CAM_V_SYNC_IDX 152 +#define LCD_V_SYNC_IDX 152 +#define LCD_DC_IDX 153 +#define LCD_PCLK_IDX 154 +#define SUBSPID4_IN_IDX 155 +#define SUBSPID4_OUT_IDX 155 +#define SUBSPID5_IN_IDX 156 +#define SUBSPID5_OUT_IDX 156 +#define SUBSPID6_IN_IDX 157 +#define SUBSPID6_OUT_IDX 157 +#define SUBSPID7_IN_IDX 158 +#define SUBSPID7_OUT_IDX 158 +#define SUBSPIDQS_IN_IDX 159 +#define SUBSPIDQS_OUT_IDX 159 +#define PWM0_SYNC0_IN_IDX 160 +#define PWM0_OUT0A_IDX 160 +#define PWM0_SYNC1_IN_IDX 161 +#define PWM0_OUT0B_IDX 161 +#define PWM0_SYNC2_IN_IDX 162 +#define PWM0_OUT1A_IDX 162 +#define PWM0_F0_IN_IDX 163 +#define PWM0_OUT1B_IDX 163 +#define PWM0_F1_IN_IDX 164 +#define PWM0_OUT2A_IDX 164 +#define PWM0_F2_IN_IDX 165 +#define PWM0_OUT2B_IDX 165 +#define PWM0_CAP0_IN_IDX 166 +#define PWM1_OUT0A_IDX 166 +#define PWM0_CAP1_IN_IDX 167 +#define PWM1_OUT0B_IDX 167 +#define PWM0_CAP2_IN_IDX 168 +#define PWM1_OUT1A_IDX 168 +#define PWM1_SYNC0_IN_IDX 169 +#define PWM1_OUT1B_IDX 169 +#define PWM1_SYNC1_IN_IDX 170 +#define PWM1_OUT2A_IDX 170 +#define PWM1_SYNC2_IN_IDX 171 +#define PWM1_OUT2B_IDX 171 +#define PWM1_F0_IN_IDX 172 +#define SDHOST_CCLK_OUT_1_IDX 172 +#define PWM1_F1_IN_IDX 173 +#define SDHOST_CCLK_OUT_2_IDX 173 +#define PWM1_F2_IN_IDX 174 +#define SDHOST_RST_N_1_IDX 174 +#define PWM1_CAP0_IN_IDX 175 +#define SDHOST_RST_N_2_IDX 175 +#define PWM1_CAP1_IN_IDX 176 +#define SDHOST_CCMD_OD_PULLUP_EN_N_IDX176 +#define PWM1_CAP2_IN_IDX 177 +#define SDIO_TOHOST_INT_OUT_IDX 177 +#define SDHOST_CCMD_IN_1_IDX 178 +#define SDHOST_CCMD_OUT_1_IDX 178 +#define SDHOST_CCMD_IN_2_IDX 179 +#define SDHOST_CCMD_OUT_2_IDX 179 +#define SDHOST_CDATA_IN_10_IDX 180 +#define SDHOST_CDATA_OUT_10_IDX 180 +#define SDHOST_CDATA_IN_11_IDX 181 +#define SDHOST_CDATA_OUT_11_IDX 181 +#define SDHOST_CDATA_IN_12_IDX 182 +#define SDHOST_CDATA_OUT_12_IDX 182 +#define SDHOST_CDATA_IN_13_IDX 183 +#define SDHOST_CDATA_OUT_13_IDX 183 +#define SDHOST_CDATA_IN_14_IDX 184 +#define SDHOST_CDATA_OUT_14_IDX 184 +#define SDHOST_CDATA_IN_15_IDX 185 +#define SDHOST_CDATA_OUT_15_IDX 185 +#define SDHOST_CDATA_IN_16_IDX 186 +#define SDHOST_CDATA_OUT_16_IDX 186 +#define SDHOST_CDATA_IN_17_IDX 187 +#define SDHOST_CDATA_OUT_17_IDX 187 +#define PCMFSYNC_IN_IDX 188 +#define BT_AUDIO0_IRQ_IDX 188 +#define PCMCLK_IN_IDX 189 +#define BT_AUDIO1_IRQ_IDX 189 +#define PCMDIN_IDX 190 +#define BT_AUDIO2_IRQ_IDX 190 +#define RW_WAKEUP_REQ_IDX 191 +#define BLE_AUDIO0_IRQ_IDX 191 +#define SDHOST_DATA_STROBE_1_IDX 192 +#define BLE_AUDIO1_IRQ_IDX 192 +#define SDHOST_DATA_STROBE_2_IDX 193 +#define BLE_AUDIO2_IRQ_IDX 193 +#define SDHOST_CARD_DETECT_N_1_IDX 194 +#define PCMFSYNC_OUT_IDX 194 +#define SDHOST_CARD_DETECT_N_2_IDX 195 +#define PCMCLK_OUT_IDX 195 +#define SDHOST_CARD_WRITE_PRT_1_IDX 196 +#define PCMDOUT_IDX 196 +#define SDHOST_CARD_WRITE_PRT_2_IDX 197 +#define BLE_AUDIO_SYNC0_P_IDX 197 +#define SDHOST_CARD_INT_N_1_IDX 198 +#define BLE_AUDIO_SYNC1_P_IDX 198 +#define SDHOST_CARD_INT_N_2_IDX 199 +#define BLE_AUDIO_SYNC2_P_IDX 199 +#define ANT_SEL0_IDX 200 +#define ANT_SEL1_IDX 201 +#define ANT_SEL2_IDX 202 +#define ANT_SEL3_IDX 203 +#define ANT_SEL4_IDX 204 +#define ANT_SEL5_IDX 205 +#define ANT_SEL6_IDX 206 +#define ANT_SEL7_IDX 207 +#define SIG_IN_FUNC_223_IDX 208 +#define SIG_IN_FUNC223_IDX 208 +#define SIG_IN_FUNC_224_IDX 209 +#define SIG_IN_FUNC224_IDX 209 +#define SIG_IN_FUNC_225_IDX 210 +#define SIG_IN_FUNC225_IDX 210 +#define SIG_IN_FUNC_226_IDX 211 +#define SIG_IN_FUNC226_IDX 211 +#define SIG_IN_FUNC_227_IDX 212 +#define SIG_IN_FUNC227_IDX 212 +#define SDHOST_CDATA_IN_20_IDX 213 +#define SDHOST_CDATA_OUT_20_IDX 213 +#define SDHOST_CDATA_IN_21_IDX 214 +#define SDHOST_CDATA_OUT_21_IDX 214 +#define SDHOST_CDATA_IN_22_IDX 215 +#define SDHOST_CDATA_OUT_22_IDX 215 +#define SDHOST_CDATA_IN_23_IDX 216 +#define SDHOST_CDATA_OUT_23_IDX 216 +#define SDHOST_CDATA_IN_24_IDX 217 +#define SDHOST_CDATA_OUT_24_IDX 217 +#define SDHOST_CDATA_IN_25_IDX 218 +#define SDHOST_CDATA_OUT_25_IDX 218 +#define SDHOST_CDATA_IN_26_IDX 219 +#define SDHOST_CDATA_OUT_26_IDX 219 +#define SDHOST_CDATA_IN_27_IDX 220 +#define SDHOST_CDATA_OUT_27_IDX 220 +#define PRO_ALONEGPIO_IN0_IDX 221 +#define PRO_ALONEGPIO_OUT0_IDX 221 +#define PRO_ALONEGPIO_IN1_IDX 222 +#define PRO_ALONEGPIO_OUT1_IDX 222 +#define PRO_ALONEGPIO_IN2_IDX 223 +#define PRO_ALONEGPIO_OUT2_IDX 223 +#define PRO_ALONEGPIO_IN3_IDX 224 +#define PRO_ALONEGPIO_OUT3_IDX 224 +#define PRO_ALONEGPIO_IN4_IDX 225 +#define PRO_ALONEGPIO_OUT4_IDX 225 +#define PRO_ALONEGPIO_IN5_IDX 226 +#define PRO_ALONEGPIO_OUT5_IDX 226 +#define PRO_ALONEGPIO_IN6_IDX 227 +#define PRO_ALONEGPIO_OUT6_IDX 227 +#define PRO_ALONEGPIO_IN7_IDX 228 +#define PRO_ALONEGPIO_OUT7_IDX 228 +#define SYNCERR_IDX 229 +#define SYNCFOUND_FLAG_IDX 230 +#define EVT_CNTL_IMMEDIATE_ABORT_IDX 231 +#define LINKLBL_IDX 232 +#define DATA_EN_IDX 233 +#define DATA_IDX 234 +#define PKT_TX_ON_IDX 235 +#define PKT_RX_ON_IDX 236 +#define RW_TX_ON_IDX 237 +#define RW_RX_ON_IDX 238 +#define EVT_REQ_P_IDX 239 +#define EVT_STOP_P_IDX 240 +#define BT_MODE_ON_IDX 241 +#define GPIO_LC_DIAG0_IDX 242 +#define GPIO_LC_DIAG1_IDX 243 +#define GPIO_LC_DIAG2_IDX 244 +#define CH_IDX_IDX 245 +#define RX_WINDOW_IDX 246 +#define UPDATE_RX_IDX 247 +#define RX_STATUS_IDX 248 +#define CLK_GPIO_IDX 249 +#define NBT_BLE_IDX 250 diff --git a/components/soc/soc/esp32s3/include/soc/gpio_struct.h b/components/soc/soc/esp32s3/include/soc/gpio_struct.h new file mode 100644 index 000000000..ff589aac9 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/gpio_struct.h @@ -0,0 +1,254 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + uint32_t bt_select; /**/ + uint32_t out; /**/ + uint32_t out_w1ts; /**/ + uint32_t out_w1tc; /**/ + union { + struct { + uint32_t data: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } out1; + union { + struct { + uint32_t data: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } out1_w1ts; + union { + struct { + uint32_t data: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } out1_w1tc; + union { + struct { + uint32_t sel: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } sdio_select; + uint32_t enable; /**/ + uint32_t enable_w1ts; /**/ + uint32_t enable_w1tc; /**/ + union { + struct { + uint32_t data: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } enable1; + union { + struct { + uint32_t data: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } enable1_w1ts; + union { + struct { + uint32_t data: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } enable1_w1tc; + union { + struct { + uint32_t strapping: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } strap; + uint32_t in; /**/ + union { + struct { + uint32_t data: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } in1; + uint32_t status; /**/ + uint32_t status_w1ts; /**/ + uint32_t status_w1tc; /**/ + union { + struct { + uint32_t intr_st: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } status1; + union { + struct { + uint32_t intr_st: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } status1_w1ts; + union { + struct { + uint32_t intr_st: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } status1_w1tc; + uint32_t pcpu_int; /**/ + uint32_t pcpu_nmi_int; /**/ + uint32_t cpusdio_int; /**/ + union { + struct { + uint32_t intr: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } pcpu_int1; + union { + struct { + uint32_t intr: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } pcpu_nmi_int1; + union { + struct { + uint32_t intr: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } cpusdio_int1; + union { + struct { + uint32_t sync2_bypass: 2; + uint32_t pad_driver: 1; + uint32_t sync1_bypass: 2; + uint32_t reserved5: 2; + uint32_t int_type: 3; + uint32_t wakeup_enable: 1; + uint32_t config: 2; + uint32_t int_ena: 5; + uint32_t reserved18: 14; + }; + uint32_t val; + } pin[54]; + uint32_t status_next; /**/ + union { + struct { + uint32_t intr_st_next: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } status_next1; + union { + struct { + uint32_t func_sel: 6; + uint32_t sig_in_inv: 1; + uint32_t sig_in_sel: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } func_in_sel_cfg[256]; + union { + struct { + uint32_t func_sel: 9; + uint32_t inv_sel: 1; + uint32_t oen_sel: 1; + uint32_t oen_inv_sel: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } func_out_sel_cfg[54]; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } clock_gate; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} gpio_dev_t; + +extern gpio_dev_t GPIO; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/hinf_reg.h b/components/soc/soc/esp32s3/include/soc/hinf_reg.h new file mode 100644 index 000000000..212fe817c --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/hinf_reg.h @@ -0,0 +1,240 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc.h" + +#define HINF_CFG_DATA0_REG (DR_REG_HINF_BASE + 0x0) +/* HINF_DEVICE_ID_FN1 : R/W ;bitpos:[31:16] ;default: 16'h2222 ; */ +/*description: */ +#define HINF_DEVICE_ID_FN1 0x0000FFFF +#define HINF_DEVICE_ID_FN1_M ((HINF_DEVICE_ID_FN1_V) << (HINF_DEVICE_ID_FN1_S)) +#define HINF_DEVICE_ID_FN1_V 0xFFFF +#define HINF_DEVICE_ID_FN1_S 16 +/* HINF_USER_ID_FN1 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */ +/*description: */ +#define HINF_USER_ID_FN1 0x0000FFFF +#define HINF_USER_ID_FN1_M ((HINF_USER_ID_FN1_V) << (HINF_USER_ID_FN1_S)) +#define HINF_USER_ID_FN1_V 0xFFFF +#define HINF_USER_ID_FN1_S 0 + +#define HINF_CFG_DATA1_REG (DR_REG_HINF_BASE + 0x4) +/* HINF_SDIO20_CONF1 : R/W ;bitpos:[31:29] ;default: 3'h0 ; */ +/*description: */ +#define HINF_SDIO20_CONF1 0x00000007 +#define HINF_SDIO20_CONF1_M ((HINF_SDIO20_CONF1_V) << (HINF_SDIO20_CONF1_S)) +#define HINF_SDIO20_CONF1_V 0x7 +#define HINF_SDIO20_CONF1_S 29 +/* HINF_FUNC2_EPS : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define HINF_FUNC2_EPS (BIT(28)) +#define HINF_FUNC2_EPS_M (BIT(28)) +#define HINF_FUNC2_EPS_V 0x1 +#define HINF_FUNC2_EPS_S 28 +/* HINF_SDIO_VER : R/W ;bitpos:[27:16] ;default: 12'h111 ; */ +/*description: */ +#define HINF_SDIO_VER 0x00000FFF +#define HINF_SDIO_VER_M ((HINF_SDIO_VER_V) << (HINF_SDIO_VER_S)) +#define HINF_SDIO_VER_V 0xFFF +#define HINF_SDIO_VER_S 16 +/* HINF_SDIO20_CONF0 : R/W ;bitpos:[15:12] ;default: 4'b0 ; */ +/*description: */ +#define HINF_SDIO20_CONF0 0x0000000F +#define HINF_SDIO20_CONF0_M ((HINF_SDIO20_CONF0_V) << (HINF_SDIO20_CONF0_S)) +#define HINF_SDIO20_CONF0_V 0xF +#define HINF_SDIO20_CONF0_S 12 +/* HINF_IOENABLE1 : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HINF_IOENABLE1 (BIT(11)) +#define HINF_IOENABLE1_M (BIT(11)) +#define HINF_IOENABLE1_V 0x1 +#define HINF_IOENABLE1_S 11 +/* HINF_EMP : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HINF_EMP (BIT(10)) +#define HINF_EMP_M (BIT(10)) +#define HINF_EMP_V 0x1 +#define HINF_EMP_S 10 +/* HINF_FUNC1_EPS : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HINF_FUNC1_EPS (BIT(9)) +#define HINF_FUNC1_EPS_M (BIT(9)) +#define HINF_FUNC1_EPS_V 0x1 +#define HINF_FUNC1_EPS_S 9 +/* HINF_CD_DISABLE : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HINF_CD_DISABLE (BIT(8)) +#define HINF_CD_DISABLE_M (BIT(8)) +#define HINF_CD_DISABLE_V 0x1 +#define HINF_CD_DISABLE_S 8 +/* HINF_IOENABLE2 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HINF_IOENABLE2 (BIT(7)) +#define HINF_IOENABLE2_M (BIT(7)) +#define HINF_IOENABLE2_V 0x1 +#define HINF_IOENABLE2_S 7 +/* HINF_SDIO_INT_MASK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_INT_MASK (BIT(6)) +#define HINF_SDIO_INT_MASK_M (BIT(6)) +#define HINF_SDIO_INT_MASK_V 0x1 +#define HINF_SDIO_INT_MASK_S 6 +/* HINF_SDIO_IOREADY2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_IOREADY2 (BIT(5)) +#define HINF_SDIO_IOREADY2_M (BIT(5)) +#define HINF_SDIO_IOREADY2_V 0x1 +#define HINF_SDIO_IOREADY2_S 5 +/* HINF_SDIO_CD_ENABLE : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define HINF_SDIO_CD_ENABLE (BIT(4)) +#define HINF_SDIO_CD_ENABLE_M (BIT(4)) +#define HINF_SDIO_CD_ENABLE_V 0x1 +#define HINF_SDIO_CD_ENABLE_S 4 +/* HINF_HIGHSPEED_MODE : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HINF_HIGHSPEED_MODE (BIT(3)) +#define HINF_HIGHSPEED_MODE_M (BIT(3)) +#define HINF_HIGHSPEED_MODE_V 0x1 +#define HINF_HIGHSPEED_MODE_S 3 +/* HINF_HIGHSPEED_ENABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HINF_HIGHSPEED_ENABLE (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_M (BIT(2)) +#define HINF_HIGHSPEED_ENABLE_V 0x1 +#define HINF_HIGHSPEED_ENABLE_S 2 +/* HINF_SDIO_IOREADY1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_IOREADY1 (BIT(1)) +#define HINF_SDIO_IOREADY1_M (BIT(1)) +#define HINF_SDIO_IOREADY1_V 0x1 +#define HINF_SDIO_IOREADY1_S 1 +/* HINF_SDIO_ENABLE : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define HINF_SDIO_ENABLE (BIT(0)) +#define HINF_SDIO_ENABLE_M (BIT(0)) +#define HINF_SDIO_ENABLE_V 0x1 +#define HINF_SDIO_ENABLE_S 0 + +#define HINF_CFG_DATA7_REG (DR_REG_HINF_BASE + 0x1C) +/* HINF_SDIO_IOREADY0 : R/W ;bitpos:[17] ;default: 1'b1 ; */ +/*description: */ +#define HINF_SDIO_IOREADY0 (BIT(17)) +#define HINF_SDIO_IOREADY0_M (BIT(17)) +#define HINF_SDIO_IOREADY0_V 0x1 +#define HINF_SDIO_IOREADY0_S 17 +/* HINF_SDIO_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HINF_SDIO_RST (BIT(16)) +#define HINF_SDIO_RST_M (BIT(16)) +#define HINF_SDIO_RST_V 0x1 +#define HINF_SDIO_RST_S 16 +/* HINF_CHIP_STATE : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: */ +#define HINF_CHIP_STATE 0x000000FF +#define HINF_CHIP_STATE_M ((HINF_CHIP_STATE_V) << (HINF_CHIP_STATE_S)) +#define HINF_CHIP_STATE_V 0xFF +#define HINF_CHIP_STATE_S 8 +/* HINF_PIN_STATE : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define HINF_PIN_STATE 0x000000FF +#define HINF_PIN_STATE_M ((HINF_PIN_STATE_V) << (HINF_PIN_STATE_S)) +#define HINF_PIN_STATE_V 0xFF +#define HINF_PIN_STATE_S 0 + +#define HINF_CIS_CONF0_REG (DR_REG_HINF_BASE + 0x20) +/* HINF_CIS_CONF_W0 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W0 0xFFFFFFFF +#define HINF_CIS_CONF_W0_M ((HINF_CIS_CONF_W0_V) << (HINF_CIS_CONF_W0_S)) +#define HINF_CIS_CONF_W0_V 0xFFFFFFFF +#define HINF_CIS_CONF_W0_S 0 + +#define HINF_CIS_CONF1_REG (DR_REG_HINF_BASE + 0x24) +/* HINF_CIS_CONF_W1 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W1 0xFFFFFFFF +#define HINF_CIS_CONF_W1_M ((HINF_CIS_CONF_W1_V) << (HINF_CIS_CONF_W1_S)) +#define HINF_CIS_CONF_W1_V 0xFFFFFFFF +#define HINF_CIS_CONF_W1_S 0 + +#define HINF_CIS_CONF2_REG (DR_REG_HINF_BASE + 0x28) +/* HINF_CIS_CONF_W2 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W2 0xFFFFFFFF +#define HINF_CIS_CONF_W2_M ((HINF_CIS_CONF_W2_V) << (HINF_CIS_CONF_W2_S)) +#define HINF_CIS_CONF_W2_V 0xFFFFFFFF +#define HINF_CIS_CONF_W2_S 0 + +#define HINF_CIS_CONF3_REG (DR_REG_HINF_BASE + 0x2C) +/* HINF_CIS_CONF_W3 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W3 0xFFFFFFFF +#define HINF_CIS_CONF_W3_M ((HINF_CIS_CONF_W3_V) << (HINF_CIS_CONF_W3_S)) +#define HINF_CIS_CONF_W3_V 0xFFFFFFFF +#define HINF_CIS_CONF_W3_S 0 + +#define HINF_CIS_CONF4_REG (DR_REG_HINF_BASE + 0x30) +/* HINF_CIS_CONF_W4 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W4 0xFFFFFFFF +#define HINF_CIS_CONF_W4_M ((HINF_CIS_CONF_W4_V) << (HINF_CIS_CONF_W4_S)) +#define HINF_CIS_CONF_W4_V 0xFFFFFFFF +#define HINF_CIS_CONF_W4_S 0 + +#define HINF_CIS_CONF5_REG (DR_REG_HINF_BASE + 0x34) +/* HINF_CIS_CONF_W5 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W5 0xFFFFFFFF +#define HINF_CIS_CONF_W5_M ((HINF_CIS_CONF_W5_V) << (HINF_CIS_CONF_W5_S)) +#define HINF_CIS_CONF_W5_V 0xFFFFFFFF +#define HINF_CIS_CONF_W5_S 0 + +#define HINF_CIS_CONF6_REG (DR_REG_HINF_BASE + 0x38) +/* HINF_CIS_CONF_W6 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W6 0xFFFFFFFF +#define HINF_CIS_CONF_W6_M ((HINF_CIS_CONF_W6_V) << (HINF_CIS_CONF_W6_S)) +#define HINF_CIS_CONF_W6_V 0xFFFFFFFF +#define HINF_CIS_CONF_W6_S 0 + +#define HINF_CIS_CONF7_REG (DR_REG_HINF_BASE + 0x3C) +/* HINF_CIS_CONF_W7 : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: */ +#define HINF_CIS_CONF_W7 0xFFFFFFFF +#define HINF_CIS_CONF_W7_M ((HINF_CIS_CONF_W7_V) << (HINF_CIS_CONF_W7_S)) +#define HINF_CIS_CONF_W7_V 0xFFFFFFFF +#define HINF_CIS_CONF_W7_S 0 + +#define HINF_CFG_DATA16_REG (DR_REG_HINF_BASE + 0x40) +/* HINF_DEVICE_ID_FN2 : R/W ;bitpos:[31:16] ;default: 16'h3333 ; */ +/*description: */ +#define HINF_DEVICE_ID_FN2 0x0000FFFF +#define HINF_DEVICE_ID_FN2_M ((HINF_DEVICE_ID_FN2_V) << (HINF_DEVICE_ID_FN2_S)) +#define HINF_DEVICE_ID_FN2_V 0xFFFF +#define HINF_DEVICE_ID_FN2_S 16 +/* HINF_USER_ID_FN2 : R/W ;bitpos:[15:0] ;default: 16'h6666 ; */ +/*description: */ +#define HINF_USER_ID_FN2 0x0000FFFF +#define HINF_USER_ID_FN2_M ((HINF_USER_ID_FN2_V) << (HINF_USER_ID_FN2_S)) +#define HINF_USER_ID_FN2_V 0xFFFF +#define HINF_USER_ID_FN2_S 0 + +#define HINF_DATE_REG (DR_REG_HINF_BASE + 0xFC) +/* HINF_SDIO_DATE : R/W ;bitpos:[31:0] ;default: 32'h15030200 ; */ +/*description: */ +#define HINF_SDIO_DATE 0xFFFFFFFF +#define HINF_SDIO_DATE_M ((HINF_SDIO_DATE_V) << (HINF_SDIO_DATE_S)) +#define HINF_SDIO_DATE_V 0xFFFFFFFF +#define HINF_SDIO_DATE_S 0 diff --git a/components/soc/soc/esp32s3/include/soc/hinf_struct.h b/components/soc/soc/esp32s3/include/soc/hinf_struct.h new file mode 100644 index 000000000..9d927ed9d --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/hinf_struct.h @@ -0,0 +1,134 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t user_id_fn1: 16; + uint32_t device_id_fn1: 16; + }; + uint32_t val; + } cfg_data0; + union { + struct { + uint32_t sdio_enable: 1; + uint32_t sdio_ioready1: 1; + uint32_t highspeed_enable: 1; + uint32_t highspeed_mode: 1; + uint32_t sdio_cd_enable: 1; + uint32_t sdio_ioready2: 1; + uint32_t sdio_int_mask: 1; + uint32_t ioenable2: 1; + uint32_t cd_disable: 1; + uint32_t func1_eps: 1; + uint32_t emp: 1; + uint32_t ioenable1: 1; + uint32_t sdio20_conf0: 4; + uint32_t sdio_ver: 12; + uint32_t func2_eps: 1; + uint32_t sdio20_conf1: 3; + }; + uint32_t val; + } cfg_data1; + uint32_t reserved_8; + uint32_t reserved_c; + uint32_t reserved_10; + uint32_t reserved_14; + uint32_t reserved_18; + union { + struct { + uint32_t pin_state: 8; + uint32_t chip_state: 8; + uint32_t sdio_rst: 1; + uint32_t sdio_ioready0: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } cfg_data7; + uint32_t cis_conf0; /**/ + uint32_t cis_conf1; /**/ + uint32_t cis_conf2; /**/ + uint32_t cis_conf3; /**/ + uint32_t cis_conf4; /**/ + uint32_t cis_conf5; /**/ + uint32_t cis_conf6; /**/ + uint32_t cis_conf7; /**/ + union { + struct { + uint32_t user_id_fn2: 16; + uint32_t device_id_fn2: 16; + }; + uint32_t val; + } cfg_data16; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} hinf_dev_t; + +extern hinf_dev_t HINF; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/host_reg.h b/components/soc/soc/esp32s3/include/soc/host_reg.h new file mode 100644 index 000000000..d54a7b270 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/host_reg.h @@ -0,0 +1,1798 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define HOST_SLCHOST_FUNC2_2_REG (DR_REG_SLCHOST_BASE + 0x20) +/* HOST_SLC_FUNC1_MDSTAT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define HOST_SLC_FUNC1_MDSTAT (BIT(0)) +#define HOST_SLC_FUNC1_MDSTAT_M (BIT(0)) +#define HOST_SLC_FUNC1_MDSTAT_V 0x1 +#define HOST_SLC_FUNC1_MDSTAT_S 0 + +#define HOST_SLCHOST_GPIO_STATUS0_REG (DR_REG_SLCHOST_BASE + 0x34) +/* HOST_GPIO_SDIO_INT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT0 0xFFFFFFFF +#define HOST_GPIO_SDIO_INT0_M ((HOST_GPIO_SDIO_INT0_V) << (HOST_GPIO_SDIO_INT0_S)) +#define HOST_GPIO_SDIO_INT0_V 0xFFFFFFFF +#define HOST_GPIO_SDIO_INT0_S 0 + +#define HOST_SLCHOST_GPIO_STATUS1_REG (DR_REG_SLCHOST_BASE + 0x38) +/* HOST_GPIO_SDIO_INT1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT1 0x003FFFFF +#define HOST_GPIO_SDIO_INT1_M ((HOST_GPIO_SDIO_INT1_V) << (HOST_GPIO_SDIO_INT1_S)) +#define HOST_GPIO_SDIO_INT1_V 0x3FFFFF +#define HOST_GPIO_SDIO_INT1_S 0 + +#define HOST_SLCHOST_GPIO_IN0_REG (DR_REG_SLCHOST_BASE + 0x3C) +/* HOST_GPIO_SDIO_IN0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_IN0 0xFFFFFFFF +#define HOST_GPIO_SDIO_IN0_M ((HOST_GPIO_SDIO_IN0_V) << (HOST_GPIO_SDIO_IN0_S)) +#define HOST_GPIO_SDIO_IN0_V 0xFFFFFFFF +#define HOST_GPIO_SDIO_IN0_S 0 + +#define HOST_SLCHOST_GPIO_IN1_REG (DR_REG_SLCHOST_BASE + 0x40) +/* HOST_GPIO_SDIO_IN1 : RO ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_IN1 0x003FFFFF +#define HOST_GPIO_SDIO_IN1_M ((HOST_GPIO_SDIO_IN1_V) << (HOST_GPIO_SDIO_IN1_S)) +#define HOST_GPIO_SDIO_IN1_V 0x3FFFFF +#define HOST_GPIO_SDIO_IN1_S 0 + +#define HOST_SLC0HOST_TOKEN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x44) +/* HOST_SLC0_RX_PF_EOF : RO ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_EOF 0x0000000F +#define HOST_SLC0_RX_PF_EOF_M ((HOST_SLC0_RX_PF_EOF_V) << (HOST_SLC0_RX_PF_EOF_S)) +#define HOST_SLC0_RX_PF_EOF_V 0xF +#define HOST_SLC0_RX_PF_EOF_S 28 +/* HOST_HOSTSLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_TOKEN1 0x00000FFF +#define HOST_HOSTSLC0_TOKEN1_M ((HOST_HOSTSLC0_TOKEN1_V) << (HOST_HOSTSLC0_TOKEN1_S)) +#define HOST_HOSTSLC0_TOKEN1_V 0xFFF +#define HOST_HOSTSLC0_TOKEN1_S 16 +/* HOST_SLC0_RX_PF_VALID : RO ;bitpos:[12] ;default: 4'h0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID (BIT(12)) +#define HOST_SLC0_RX_PF_VALID_M (BIT(12)) +#define HOST_SLC0_RX_PF_VALID_V 0x1 +#define HOST_SLC0_RX_PF_VALID_S 12 +/* HOST_SLC0_TOKEN0 : RO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0 0x00000FFF +#define HOST_SLC0_TOKEN0_M ((HOST_SLC0_TOKEN0_V) << (HOST_SLC0_TOKEN0_S)) +#define HOST_SLC0_TOKEN0_V 0xFFF +#define HOST_SLC0_TOKEN0_S 0 + +#define HOST_SLC0_HOST_PF_REG (DR_REG_SLCHOST_BASE + 0x48) +/* HOST_SLC0_PF_DATA : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define HOST_SLC0_PF_DATA 0xFFFFFFFF +#define HOST_SLC0_PF_DATA_M ((HOST_SLC0_PF_DATA_V) << (HOST_SLC0_PF_DATA_S)) +#define HOST_SLC0_PF_DATA_V 0xFFFFFFFF +#define HOST_SLC0_PF_DATA_S 0 + +#define HOST_SLC0HOST_INT_RAW_REG (DR_REG_SLCHOST_BASE + 0x50) +/* HOST_GPIO_SDIO_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_RAW (BIT(25)) +#define HOST_GPIO_SDIO_INT_RAW_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_RAW_V 0x1 +#define HOST_GPIO_SDIO_INT_RAW_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_RAW_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_RAW_S 23 +/* HOST_SLC0_EXT_BIT3_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_RAW (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_RAW_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_RAW_S 22 +/* HOST_SLC0_EXT_BIT2_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_RAW (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_RAW_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_RAW_S 21 +/* HOST_SLC0_EXT_BIT1_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_RAW (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_RAW_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_RAW_S 20 +/* HOST_SLC0_EXT_BIT0_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_RAW (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_RAW_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_RAW_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_RAW_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_RAW (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_RAW_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_RAW_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_RAW_S 18 +/* HOST_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_RAW (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_RAW_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_RAW_V 0x1 +#define HOST_SLC0_TX_OVF_INT_RAW_S 17 +/* HOST_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_RAW (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_RAW_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_RAW_V 0x1 +#define HOST_SLC0_RX_UDF_INT_RAW_S 16 +/* HOST_SLC0HOST_TX_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_RAW (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_RAW_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_RAW_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_RAW_S 15 +/* HOST_SLC0HOST_RX_START_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_RAW (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_RAW_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_RAW_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_RAW_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_RAW (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_RAW_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_RAW_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_RAW_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_RAW (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_RAW_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_RAW_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_RAW_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_RAW_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_RAW_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_RAW_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_RAW_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_RAW (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_RAW_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_RAW_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_RAW (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_RAW_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_RAW_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_RAW (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_RAW_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_RAW_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_RAW (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_RAW_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_RAW_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_RAW (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_RAW_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_RAW_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_RAW (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_RAW_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_RAW_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_RAW (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_RAW_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_RAW_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_RAW (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_RAW_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_RAW_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_RAW_S 0 + +#define HOST_SLC0HOST_INT_ST_REG (DR_REG_SLCHOST_BASE + 0x58) +/* HOST_GPIO_SDIO_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_ST (BIT(25)) +#define HOST_GPIO_SDIO_INT_ST_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_ST_V 0x1 +#define HOST_GPIO_SDIO_INT_ST_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_ST (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ST_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ST_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_ST_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_ST (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ST_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ST_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_ST_S 23 +/* HOST_SLC0_EXT_BIT3_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_ST (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ST_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_ST_S 22 +/* HOST_SLC0_EXT_BIT2_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_ST (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ST_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_ST_S 21 +/* HOST_SLC0_EXT_BIT1_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_ST (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ST_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_ST_S 20 +/* HOST_SLC0_EXT_BIT0_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_ST (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ST_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ST_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_ST_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_ST (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ST_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ST_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_ST_S 18 +/* HOST_SLC0_TX_OVF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_ST (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ST_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ST_V 0x1 +#define HOST_SLC0_TX_OVF_INT_ST_S 17 +/* HOST_SLC0_RX_UDF_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_ST (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ST_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ST_V 0x1 +#define HOST_SLC0_RX_UDF_INT_ST_S 16 +/* HOST_SLC0HOST_TX_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_ST (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ST_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ST_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_ST_S 15 +/* HOST_SLC0HOST_RX_START_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_ST (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ST_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ST_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_ST_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_ST (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ST_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ST_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_ST_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_ST (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ST_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ST_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_ST_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_ST (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ST_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_ST_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_ST (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ST_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_ST_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_ST (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_ST_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_ST (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ST_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_ST_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_ST (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ST_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_ST_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_ST (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ST_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_ST_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_ST (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ST_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_ST_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_ST (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ST_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_ST_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_ST (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ST_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_ST_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_ST (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ST_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_ST_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_ST (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ST_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_ST_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_ST (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ST_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ST_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_ST_S 0 + +#define HOST_SLCHOST_PKT_LEN_REG (DR_REG_SLCHOST_BASE + 0x60) +/* HOST_HOSTSLC0_LEN_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN_CHECK 0x00000FFF +#define HOST_HOSTSLC0_LEN_CHECK_M ((HOST_HOSTSLC0_LEN_CHECK_V) << (HOST_HOSTSLC0_LEN_CHECK_S)) +#define HOST_HOSTSLC0_LEN_CHECK_V 0xFFF +#define HOST_HOSTSLC0_LEN_CHECK_S 20 +/* HOST_HOSTSLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN 0x000FFFFF +#define HOST_HOSTSLC0_LEN_M ((HOST_HOSTSLC0_LEN_V) << (HOST_HOSTSLC0_LEN_S)) +#define HOST_HOSTSLC0_LEN_V 0xFFFFF +#define HOST_HOSTSLC0_LEN_S 0 + +#define HOST_SLCHOST_STATE_W0_REG (DR_REG_SLCHOST_BASE + 0x64) +/* HOST_SLCHOST_STATE3 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE3 0x000000FF +#define HOST_SLCHOST_STATE3_M ((HOST_SLCHOST_STATE3_V) << (HOST_SLCHOST_STATE3_S)) +#define HOST_SLCHOST_STATE3_V 0xFF +#define HOST_SLCHOST_STATE3_S 24 +/* HOST_SLCHOST_STATE2 : RO ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE2 0x000000FF +#define HOST_SLCHOST_STATE2_M ((HOST_SLCHOST_STATE2_V) << (HOST_SLCHOST_STATE2_S)) +#define HOST_SLCHOST_STATE2_V 0xFF +#define HOST_SLCHOST_STATE2_S 16 +/* HOST_SLCHOST_STATE1 : RO ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE1 0x000000FF +#define HOST_SLCHOST_STATE1_M ((HOST_SLCHOST_STATE1_V) << (HOST_SLCHOST_STATE1_S)) +#define HOST_SLCHOST_STATE1_V 0xFF +#define HOST_SLCHOST_STATE1_S 8 +/* HOST_SLCHOST_STATE0 : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE0 0x000000FF +#define HOST_SLCHOST_STATE0_M ((HOST_SLCHOST_STATE0_V) << (HOST_SLCHOST_STATE0_S)) +#define HOST_SLCHOST_STATE0_V 0xFF +#define HOST_SLCHOST_STATE0_S 0 + +#define HOST_SLCHOST_STATE_W1_REG (DR_REG_SLCHOST_BASE + 0x68) +/* HOST_SLCHOST_STATE7 : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE7 0x000000FF +#define HOST_SLCHOST_STATE7_M ((HOST_SLCHOST_STATE7_V) << (HOST_SLCHOST_STATE7_S)) +#define HOST_SLCHOST_STATE7_V 0xFF +#define HOST_SLCHOST_STATE7_S 24 +/* HOST_SLCHOST_STATE6 : RO ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE6 0x000000FF +#define HOST_SLCHOST_STATE6_M ((HOST_SLCHOST_STATE6_V) << (HOST_SLCHOST_STATE6_S)) +#define HOST_SLCHOST_STATE6_V 0xFF +#define HOST_SLCHOST_STATE6_S 16 +/* HOST_SLCHOST_STATE5 : RO ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE5 0x000000FF +#define HOST_SLCHOST_STATE5_M ((HOST_SLCHOST_STATE5_V) << (HOST_SLCHOST_STATE5_S)) +#define HOST_SLCHOST_STATE5_V 0xFF +#define HOST_SLCHOST_STATE5_S 8 +/* HOST_SLCHOST_STATE4 : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_STATE4 0x000000FF +#define HOST_SLCHOST_STATE4_M ((HOST_SLCHOST_STATE4_V) << (HOST_SLCHOST_STATE4_S)) +#define HOST_SLCHOST_STATE4_V 0xFF +#define HOST_SLCHOST_STATE4_S 0 + +#define HOST_SLCHOST_CONF_W0_REG (DR_REG_SLCHOST_BASE + 0x6C) +/* HOST_SLCHOST_CONF3 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF3 0x000000FF +#define HOST_SLCHOST_CONF3_M ((HOST_SLCHOST_CONF3_V) << (HOST_SLCHOST_CONF3_S)) +#define HOST_SLCHOST_CONF3_V 0xFF +#define HOST_SLCHOST_CONF3_S 24 +/* HOST_SLCHOST_CONF2 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF2 0x000000FF +#define HOST_SLCHOST_CONF2_M ((HOST_SLCHOST_CONF2_V) << (HOST_SLCHOST_CONF2_S)) +#define HOST_SLCHOST_CONF2_V 0xFF +#define HOST_SLCHOST_CONF2_S 16 +/* HOST_SLCHOST_CONF1 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF1 0x000000FF +#define HOST_SLCHOST_CONF1_M ((HOST_SLCHOST_CONF1_V) << (HOST_SLCHOST_CONF1_S)) +#define HOST_SLCHOST_CONF1_V 0xFF +#define HOST_SLCHOST_CONF1_S 8 +/* HOST_SLCHOST_CONF0 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF0 0x000000FF +#define HOST_SLCHOST_CONF0_M ((HOST_SLCHOST_CONF0_V) << (HOST_SLCHOST_CONF0_S)) +#define HOST_SLCHOST_CONF0_V 0xFF +#define HOST_SLCHOST_CONF0_S 0 + +#define HOST_SLCHOST_CONF_W1_REG (DR_REG_SLCHOST_BASE + 0x70) +/* HOST_SLCHOST_CONF7 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF7 0x000000FF +#define HOST_SLCHOST_CONF7_M ((HOST_SLCHOST_CONF7_V) << (HOST_SLCHOST_CONF7_S)) +#define HOST_SLCHOST_CONF7_V 0xFF +#define HOST_SLCHOST_CONF7_S 24 +/* HOST_SLCHOST_CONF6 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF6 0x000000FF +#define HOST_SLCHOST_CONF6_M ((HOST_SLCHOST_CONF6_V) << (HOST_SLCHOST_CONF6_S)) +#define HOST_SLCHOST_CONF6_V 0xFF +#define HOST_SLCHOST_CONF6_S 16 +/* HOST_SLCHOST_CONF5 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF5 0x000000FF +#define HOST_SLCHOST_CONF5_M ((HOST_SLCHOST_CONF5_V) << (HOST_SLCHOST_CONF5_S)) +#define HOST_SLCHOST_CONF5_V 0xFF +#define HOST_SLCHOST_CONF5_S 8 +/* HOST_SLCHOST_CONF4 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF4 0x000000FF +#define HOST_SLCHOST_CONF4_M ((HOST_SLCHOST_CONF4_V) << (HOST_SLCHOST_CONF4_S)) +#define HOST_SLCHOST_CONF4_V 0xFF +#define HOST_SLCHOST_CONF4_S 0 + +#define HOST_SLCHOST_CONF_W2_REG (DR_REG_SLCHOST_BASE + 0x74) +/* HOST_SLCHOST_CONF11 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF11 0x000000FF +#define HOST_SLCHOST_CONF11_M ((HOST_SLCHOST_CONF11_V) << (HOST_SLCHOST_CONF11_S)) +#define HOST_SLCHOST_CONF11_V 0xFF +#define HOST_SLCHOST_CONF11_S 24 +/* HOST_SLCHOST_CONF10 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF10 0x000000FF +#define HOST_SLCHOST_CONF10_M ((HOST_SLCHOST_CONF10_V) << (HOST_SLCHOST_CONF10_S)) +#define HOST_SLCHOST_CONF10_V 0xFF +#define HOST_SLCHOST_CONF10_S 16 +/* HOST_SLCHOST_CONF9 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF9 0x000000FF +#define HOST_SLCHOST_CONF9_M ((HOST_SLCHOST_CONF9_V) << (HOST_SLCHOST_CONF9_S)) +#define HOST_SLCHOST_CONF9_V 0xFF +#define HOST_SLCHOST_CONF9_S 8 +/* HOST_SLCHOST_CONF8 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF8 0x000000FF +#define HOST_SLCHOST_CONF8_M ((HOST_SLCHOST_CONF8_V) << (HOST_SLCHOST_CONF8_S)) +#define HOST_SLCHOST_CONF8_V 0xFF +#define HOST_SLCHOST_CONF8_S 0 + +#define HOST_SLCHOST_CONF_W3_REG (DR_REG_SLCHOST_BASE + 0x78) +/* HOST_SLCHOST_CONF15 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF15 0x000000FF +#define HOST_SLCHOST_CONF15_M ((HOST_SLCHOST_CONF15_V) << (HOST_SLCHOST_CONF15_S)) +#define HOST_SLCHOST_CONF15_V 0xFF +#define HOST_SLCHOST_CONF15_S 24 +/* HOST_SLCHOST_CONF14 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF14 0x000000FF +#define HOST_SLCHOST_CONF14_M ((HOST_SLCHOST_CONF14_V) << (HOST_SLCHOST_CONF14_S)) +#define HOST_SLCHOST_CONF14_V 0xFF +#define HOST_SLCHOST_CONF14_S 16 +/* HOST_SLCHOST_CONF13 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF13 0x000000FF +#define HOST_SLCHOST_CONF13_M ((HOST_SLCHOST_CONF13_V) << (HOST_SLCHOST_CONF13_S)) +#define HOST_SLCHOST_CONF13_V 0xFF +#define HOST_SLCHOST_CONF13_S 8 +/* HOST_SLCHOST_CONF12 : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF12 0x000000FF +#define HOST_SLCHOST_CONF12_M ((HOST_SLCHOST_CONF12_V) << (HOST_SLCHOST_CONF12_S)) +#define HOST_SLCHOST_CONF12_V 0xFF +#define HOST_SLCHOST_CONF12_S 0 + +#define HOST_SLCHOST_CONF_W4_REG (DR_REG_SLCHOST_BASE + 0x7C) +/* HOST_SLCHOST_CONF19 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: Interrupt to target CPU*/ +#define HOST_SLCHOST_CONF19 0x000000FF +#define HOST_SLCHOST_CONF19_M ((HOST_SLCHOST_CONF19_V) << (HOST_SLCHOST_CONF19_S)) +#define HOST_SLCHOST_CONF19_V 0xFF +#define HOST_SLCHOST_CONF19_S 24 +/* HOST_SLCHOST_CONF18 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF18 0x000000FF +#define HOST_SLCHOST_CONF18_M ((HOST_SLCHOST_CONF18_V) << (HOST_SLCHOST_CONF18_S)) +#define HOST_SLCHOST_CONF18_V 0xFF +#define HOST_SLCHOST_CONF18_S 16 +/* HOST_SLCHOST_CONF17 : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: SLC timeout enable*/ +#define HOST_SLCHOST_CONF17 0x000000FF +#define HOST_SLCHOST_CONF17_M ((HOST_SLCHOST_CONF17_V) << (HOST_SLCHOST_CONF17_S)) +#define HOST_SLCHOST_CONF17_V 0xFF +#define HOST_SLCHOST_CONF17_S 8 +/* HOST_SLCHOST_CONF16 : R/W ;bitpos:[7:0] ;default: 8'hFF ; */ +/*description: SLC timeout value*/ +#define HOST_SLCHOST_CONF16 0x000000FF +#define HOST_SLCHOST_CONF16_M ((HOST_SLCHOST_CONF16_V) << (HOST_SLCHOST_CONF16_S)) +#define HOST_SLCHOST_CONF16_V 0xFF +#define HOST_SLCHOST_CONF16_S 0 + +#define HOST_SLCHOST_CONF_W5_REG (DR_REG_SLCHOST_BASE + 0x80) +/* HOST_SLCHOST_CONF23 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF23 0x000000FF +#define HOST_SLCHOST_CONF23_M ((HOST_SLCHOST_CONF23_V) << (HOST_SLCHOST_CONF23_S)) +#define HOST_SLCHOST_CONF23_V 0xFF +#define HOST_SLCHOST_CONF23_S 24 +/* HOST_SLCHOST_CONF22 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF22 0x000000FF +#define HOST_SLCHOST_CONF22_M ((HOST_SLCHOST_CONF22_V) << (HOST_SLCHOST_CONF22_S)) +#define HOST_SLCHOST_CONF22_V 0xFF +#define HOST_SLCHOST_CONF22_S 16 +/* HOST_SLCHOST_CONF21 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF21 0x000000FF +#define HOST_SLCHOST_CONF21_M ((HOST_SLCHOST_CONF21_V) << (HOST_SLCHOST_CONF21_S)) +#define HOST_SLCHOST_CONF21_V 0xFF +#define HOST_SLCHOST_CONF21_S 8 +/* HOST_SLCHOST_CONF20 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF20 0x000000FF +#define HOST_SLCHOST_CONF20_M ((HOST_SLCHOST_CONF20_V) << (HOST_SLCHOST_CONF20_S)) +#define HOST_SLCHOST_CONF20_V 0xFF +#define HOST_SLCHOST_CONF20_S 0 + +#define HOST_SLCHOST_WIN_CMD_REG (DR_REG_SLCHOST_BASE + 0x84) +/* HOST_SLCHOST_WIN_CMD : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: */ +#define HOST_SLCHOST_WIN_CMD 0x0000FFFF +#define HOST_SLCHOST_WIN_CMD_M ((HOST_SLCHOST_WIN_CMD_V) << (HOST_SLCHOST_WIN_CMD_S)) +#define HOST_SLCHOST_WIN_CMD_V 0xFFFF +#define HOST_SLCHOST_WIN_CMD_S 0 + +#define HOST_SLCHOST_CONF_W6_REG (DR_REG_SLCHOST_BASE + 0x88) +/* HOST_SLCHOST_CONF27 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF27 0x000000FF +#define HOST_SLCHOST_CONF27_M ((HOST_SLCHOST_CONF27_V) << (HOST_SLCHOST_CONF27_S)) +#define HOST_SLCHOST_CONF27_V 0xFF +#define HOST_SLCHOST_CONF27_S 24 +/* HOST_SLCHOST_CONF26 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF26 0x000000FF +#define HOST_SLCHOST_CONF26_M ((HOST_SLCHOST_CONF26_V) << (HOST_SLCHOST_CONF26_S)) +#define HOST_SLCHOST_CONF26_V 0xFF +#define HOST_SLCHOST_CONF26_S 16 +/* HOST_SLCHOST_CONF25 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF25 0x000000FF +#define HOST_SLCHOST_CONF25_M ((HOST_SLCHOST_CONF25_V) << (HOST_SLCHOST_CONF25_S)) +#define HOST_SLCHOST_CONF25_V 0xFF +#define HOST_SLCHOST_CONF25_S 8 +/* HOST_SLCHOST_CONF24 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF24 0x000000FF +#define HOST_SLCHOST_CONF24_M ((HOST_SLCHOST_CONF24_V) << (HOST_SLCHOST_CONF24_S)) +#define HOST_SLCHOST_CONF24_V 0xFF +#define HOST_SLCHOST_CONF24_S 0 + +#define HOST_SLCHOST_CONF_W7_REG (DR_REG_SLCHOST_BASE + 0x8C) +/* HOST_SLCHOST_CONF31 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF31 0x000000FF +#define HOST_SLCHOST_CONF31_M ((HOST_SLCHOST_CONF31_V) << (HOST_SLCHOST_CONF31_S)) +#define HOST_SLCHOST_CONF31_V 0xFF +#define HOST_SLCHOST_CONF31_S 24 +/* HOST_SLCHOST_CONF30 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF30 0x000000FF +#define HOST_SLCHOST_CONF30_M ((HOST_SLCHOST_CONF30_V) << (HOST_SLCHOST_CONF30_S)) +#define HOST_SLCHOST_CONF30_V 0xFF +#define HOST_SLCHOST_CONF30_S 16 +/* HOST_SLCHOST_CONF29 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF29 0x000000FF +#define HOST_SLCHOST_CONF29_M ((HOST_SLCHOST_CONF29_V) << (HOST_SLCHOST_CONF29_S)) +#define HOST_SLCHOST_CONF29_V 0xFF +#define HOST_SLCHOST_CONF29_S 8 +/* HOST_SLCHOST_CONF28 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF28 0x000000FF +#define HOST_SLCHOST_CONF28_M ((HOST_SLCHOST_CONF28_V) << (HOST_SLCHOST_CONF28_S)) +#define HOST_SLCHOST_CONF28_V 0xFF +#define HOST_SLCHOST_CONF28_S 0 + +#define HOST_SLCHOST_PKT_LEN0_REG (DR_REG_SLCHOST_BASE + 0x90) +/* HOST_HOSTSLC0_LEN0_CHECK : RO ;bitpos:[31:20] ;default: 12'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN0_CHECK 0x00000FFF +#define HOST_HOSTSLC0_LEN0_CHECK_M ((HOST_HOSTSLC0_LEN0_CHECK_V) << (HOST_HOSTSLC0_LEN0_CHECK_S)) +#define HOST_HOSTSLC0_LEN0_CHECK_V 0xFFF +#define HOST_HOSTSLC0_LEN0_CHECK_S 20 +/* HOST_HOSTSLC0_LEN0 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN0 0x000FFFFF +#define HOST_HOSTSLC0_LEN0_M ((HOST_HOSTSLC0_LEN0_V) << (HOST_HOSTSLC0_LEN0_S)) +#define HOST_HOSTSLC0_LEN0_V 0xFFFFF +#define HOST_HOSTSLC0_LEN0_S 0 + +#define HOST_SLCHOST_PKT_LEN1_REG (DR_REG_SLCHOST_BASE + 0x94) +/* HOST_HOSTSLC0_LEN1_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN1_CHECK 0x00000FFF +#define HOST_HOSTSLC0_LEN1_CHECK_M ((HOST_HOSTSLC0_LEN1_CHECK_V) << (HOST_HOSTSLC0_LEN1_CHECK_S)) +#define HOST_HOSTSLC0_LEN1_CHECK_V 0xFFF +#define HOST_HOSTSLC0_LEN1_CHECK_S 20 +/* HOST_HOSTSLC0_LEN1 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN1 0x000FFFFF +#define HOST_HOSTSLC0_LEN1_M ((HOST_HOSTSLC0_LEN1_V) << (HOST_HOSTSLC0_LEN1_S)) +#define HOST_HOSTSLC0_LEN1_V 0xFFFFF +#define HOST_HOSTSLC0_LEN1_S 0 + +#define HOST_SLCHOST_PKT_LEN2_REG (DR_REG_SLCHOST_BASE + 0x98) +/* HOST_HOSTSLC0_LEN2_CHECK : RO ;bitpos:[31:20] ;default: 10'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN2_CHECK 0x00000FFF +#define HOST_HOSTSLC0_LEN2_CHECK_M ((HOST_HOSTSLC0_LEN2_CHECK_V) << (HOST_HOSTSLC0_LEN2_CHECK_S)) +#define HOST_HOSTSLC0_LEN2_CHECK_V 0xFFF +#define HOST_HOSTSLC0_LEN2_CHECK_S 20 +/* HOST_HOSTSLC0_LEN2 : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define HOST_HOSTSLC0_LEN2 0x000FFFFF +#define HOST_HOSTSLC0_LEN2_M ((HOST_HOSTSLC0_LEN2_V) << (HOST_HOSTSLC0_LEN2_S)) +#define HOST_HOSTSLC0_LEN2_V 0xFFFFF +#define HOST_HOSTSLC0_LEN2_S 0 + +#define HOST_SLCHOST_CONF_W8_REG (DR_REG_SLCHOST_BASE + 0x9C) +/* HOST_SLCHOST_CONF35 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF35 0x000000FF +#define HOST_SLCHOST_CONF35_M ((HOST_SLCHOST_CONF35_V) << (HOST_SLCHOST_CONF35_S)) +#define HOST_SLCHOST_CONF35_V 0xFF +#define HOST_SLCHOST_CONF35_S 24 +/* HOST_SLCHOST_CONF34 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF34 0x000000FF +#define HOST_SLCHOST_CONF34_M ((HOST_SLCHOST_CONF34_V) << (HOST_SLCHOST_CONF34_S)) +#define HOST_SLCHOST_CONF34_V 0xFF +#define HOST_SLCHOST_CONF34_S 16 +/* HOST_SLCHOST_CONF33 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF33 0x000000FF +#define HOST_SLCHOST_CONF33_M ((HOST_SLCHOST_CONF33_V) << (HOST_SLCHOST_CONF33_S)) +#define HOST_SLCHOST_CONF33_V 0xFF +#define HOST_SLCHOST_CONF33_S 8 +/* HOST_SLCHOST_CONF32 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF32 0x000000FF +#define HOST_SLCHOST_CONF32_M ((HOST_SLCHOST_CONF32_V) << (HOST_SLCHOST_CONF32_S)) +#define HOST_SLCHOST_CONF32_V 0xFF +#define HOST_SLCHOST_CONF32_S 0 + +#define HOST_SLCHOST_CONF_W9_REG (DR_REG_SLCHOST_BASE + 0xA0) +/* HOST_SLCHOST_CONF39 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF39 0x000000FF +#define HOST_SLCHOST_CONF39_M ((HOST_SLCHOST_CONF39_V) << (HOST_SLCHOST_CONF39_S)) +#define HOST_SLCHOST_CONF39_V 0xFF +#define HOST_SLCHOST_CONF39_S 24 +/* HOST_SLCHOST_CONF38 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF38 0x000000FF +#define HOST_SLCHOST_CONF38_M ((HOST_SLCHOST_CONF38_V) << (HOST_SLCHOST_CONF38_S)) +#define HOST_SLCHOST_CONF38_V 0xFF +#define HOST_SLCHOST_CONF38_S 16 +/* HOST_SLCHOST_CONF37 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF37 0x000000FF +#define HOST_SLCHOST_CONF37_M ((HOST_SLCHOST_CONF37_V) << (HOST_SLCHOST_CONF37_S)) +#define HOST_SLCHOST_CONF37_V 0xFF +#define HOST_SLCHOST_CONF37_S 8 +/* HOST_SLCHOST_CONF36 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF36 0x000000FF +#define HOST_SLCHOST_CONF36_M ((HOST_SLCHOST_CONF36_V) << (HOST_SLCHOST_CONF36_S)) +#define HOST_SLCHOST_CONF36_V 0xFF +#define HOST_SLCHOST_CONF36_S 0 + +#define HOST_SLCHOST_CONF_W10_REG (DR_REG_SLCHOST_BASE + 0xA4) +/* HOST_SLCHOST_CONF43 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF43 0x000000FF +#define HOST_SLCHOST_CONF43_M ((HOST_SLCHOST_CONF43_V) << (HOST_SLCHOST_CONF43_S)) +#define HOST_SLCHOST_CONF43_V 0xFF +#define HOST_SLCHOST_CONF43_S 24 +/* HOST_SLCHOST_CONF42 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF42 0x000000FF +#define HOST_SLCHOST_CONF42_M ((HOST_SLCHOST_CONF42_V) << (HOST_SLCHOST_CONF42_S)) +#define HOST_SLCHOST_CONF42_V 0xFF +#define HOST_SLCHOST_CONF42_S 16 +/* HOST_SLCHOST_CONF41 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF41 0x000000FF +#define HOST_SLCHOST_CONF41_M ((HOST_SLCHOST_CONF41_V) << (HOST_SLCHOST_CONF41_S)) +#define HOST_SLCHOST_CONF41_V 0xFF +#define HOST_SLCHOST_CONF41_S 8 +/* HOST_SLCHOST_CONF40 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF40 0x000000FF +#define HOST_SLCHOST_CONF40_M ((HOST_SLCHOST_CONF40_V) << (HOST_SLCHOST_CONF40_S)) +#define HOST_SLCHOST_CONF40_V 0xFF +#define HOST_SLCHOST_CONF40_S 0 + +#define HOST_SLCHOST_CONF_W11_REG (DR_REG_SLCHOST_BASE + 0xA8) +/* HOST_SLCHOST_CONF47 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF47 0x000000FF +#define HOST_SLCHOST_CONF47_M ((HOST_SLCHOST_CONF47_V) << (HOST_SLCHOST_CONF47_S)) +#define HOST_SLCHOST_CONF47_V 0xFF +#define HOST_SLCHOST_CONF47_S 24 +/* HOST_SLCHOST_CONF46 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF46 0x000000FF +#define HOST_SLCHOST_CONF46_M ((HOST_SLCHOST_CONF46_V) << (HOST_SLCHOST_CONF46_S)) +#define HOST_SLCHOST_CONF46_V 0xFF +#define HOST_SLCHOST_CONF46_S 16 +/* HOST_SLCHOST_CONF45 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF45 0x000000FF +#define HOST_SLCHOST_CONF45_M ((HOST_SLCHOST_CONF45_V) << (HOST_SLCHOST_CONF45_S)) +#define HOST_SLCHOST_CONF45_V 0xFF +#define HOST_SLCHOST_CONF45_S 8 +/* HOST_SLCHOST_CONF44 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF44 0x000000FF +#define HOST_SLCHOST_CONF44_M ((HOST_SLCHOST_CONF44_V) << (HOST_SLCHOST_CONF44_S)) +#define HOST_SLCHOST_CONF44_V 0xFF +#define HOST_SLCHOST_CONF44_S 0 + +#define HOST_SLCHOST_CONF_W12_REG (DR_REG_SLCHOST_BASE + 0xAC) +/* HOST_SLCHOST_CONF51 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF51 0x000000FF +#define HOST_SLCHOST_CONF51_M ((HOST_SLCHOST_CONF51_V) << (HOST_SLCHOST_CONF51_S)) +#define HOST_SLCHOST_CONF51_V 0xFF +#define HOST_SLCHOST_CONF51_S 24 +/* HOST_SLCHOST_CONF50 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF50 0x000000FF +#define HOST_SLCHOST_CONF50_M ((HOST_SLCHOST_CONF50_V) << (HOST_SLCHOST_CONF50_S)) +#define HOST_SLCHOST_CONF50_V 0xFF +#define HOST_SLCHOST_CONF50_S 16 +/* HOST_SLCHOST_CONF49 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF49 0x000000FF +#define HOST_SLCHOST_CONF49_M ((HOST_SLCHOST_CONF49_V) << (HOST_SLCHOST_CONF49_S)) +#define HOST_SLCHOST_CONF49_V 0xFF +#define HOST_SLCHOST_CONF49_S 8 +/* HOST_SLCHOST_CONF48 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF48 0x000000FF +#define HOST_SLCHOST_CONF48_M ((HOST_SLCHOST_CONF48_V) << (HOST_SLCHOST_CONF48_S)) +#define HOST_SLCHOST_CONF48_V 0xFF +#define HOST_SLCHOST_CONF48_S 0 + +#define HOST_SLCHOST_CONF_W13_REG (DR_REG_SLCHOST_BASE + 0xB0) +/* HOST_SLCHOST_CONF55 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF55 0x000000FF +#define HOST_SLCHOST_CONF55_M ((HOST_SLCHOST_CONF55_V) << (HOST_SLCHOST_CONF55_S)) +#define HOST_SLCHOST_CONF55_V 0xFF +#define HOST_SLCHOST_CONF55_S 24 +/* HOST_SLCHOST_CONF54 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF54 0x000000FF +#define HOST_SLCHOST_CONF54_M ((HOST_SLCHOST_CONF54_V) << (HOST_SLCHOST_CONF54_S)) +#define HOST_SLCHOST_CONF54_V 0xFF +#define HOST_SLCHOST_CONF54_S 16 +/* HOST_SLCHOST_CONF53 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF53 0x000000FF +#define HOST_SLCHOST_CONF53_M ((HOST_SLCHOST_CONF53_V) << (HOST_SLCHOST_CONF53_S)) +#define HOST_SLCHOST_CONF53_V 0xFF +#define HOST_SLCHOST_CONF53_S 8 +/* HOST_SLCHOST_CONF52 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF52 0x000000FF +#define HOST_SLCHOST_CONF52_M ((HOST_SLCHOST_CONF52_V) << (HOST_SLCHOST_CONF52_S)) +#define HOST_SLCHOST_CONF52_V 0xFF +#define HOST_SLCHOST_CONF52_S 0 + +#define HOST_SLCHOST_CONF_W14_REG (DR_REG_SLCHOST_BASE + 0xB4) +/* HOST_SLCHOST_CONF59 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF59 0x000000FF +#define HOST_SLCHOST_CONF59_M ((HOST_SLCHOST_CONF59_V) << (HOST_SLCHOST_CONF59_S)) +#define HOST_SLCHOST_CONF59_V 0xFF +#define HOST_SLCHOST_CONF59_S 24 +/* HOST_SLCHOST_CONF58 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF58 0x000000FF +#define HOST_SLCHOST_CONF58_M ((HOST_SLCHOST_CONF58_V) << (HOST_SLCHOST_CONF58_S)) +#define HOST_SLCHOST_CONF58_V 0xFF +#define HOST_SLCHOST_CONF58_S 16 +/* HOST_SLCHOST_CONF57 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF57 0x000000FF +#define HOST_SLCHOST_CONF57_M ((HOST_SLCHOST_CONF57_V) << (HOST_SLCHOST_CONF57_S)) +#define HOST_SLCHOST_CONF57_V 0xFF +#define HOST_SLCHOST_CONF57_S 8 +/* HOST_SLCHOST_CONF56 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF56 0x000000FF +#define HOST_SLCHOST_CONF56_M ((HOST_SLCHOST_CONF56_V) << (HOST_SLCHOST_CONF56_S)) +#define HOST_SLCHOST_CONF56_V 0xFF +#define HOST_SLCHOST_CONF56_S 0 + +#define HOST_SLCHOST_CONF_W15_REG (DR_REG_SLCHOST_BASE + 0xB8) +/* HOST_SLCHOST_CONF63 : R/W ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF63 0x000000FF +#define HOST_SLCHOST_CONF63_M ((HOST_SLCHOST_CONF63_V) << (HOST_SLCHOST_CONF63_S)) +#define HOST_SLCHOST_CONF63_V 0xFF +#define HOST_SLCHOST_CONF63_S 24 +/* HOST_SLCHOST_CONF62 : R/W ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF62 0x000000FF +#define HOST_SLCHOST_CONF62_M ((HOST_SLCHOST_CONF62_V) << (HOST_SLCHOST_CONF62_S)) +#define HOST_SLCHOST_CONF62_V 0xFF +#define HOST_SLCHOST_CONF62_S 16 +/* HOST_SLCHOST_CONF61 : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF61 0x000000FF +#define HOST_SLCHOST_CONF61_M ((HOST_SLCHOST_CONF61_V) << (HOST_SLCHOST_CONF61_S)) +#define HOST_SLCHOST_CONF61_V 0xFF +#define HOST_SLCHOST_CONF61_S 8 +/* HOST_SLCHOST_CONF60 : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define HOST_SLCHOST_CONF60 0x000000FF +#define HOST_SLCHOST_CONF60_M ((HOST_SLCHOST_CONF60_V) << (HOST_SLCHOST_CONF60_S)) +#define HOST_SLCHOST_CONF60_V 0xFF +#define HOST_SLCHOST_CONF60_S 0 + +#define HOST_SLCHOST_CHECK_SUM0_REG (DR_REG_SLCHOST_BASE + 0xBC) +/* HOST_SLCHOST_CHECK_SUM0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLCHOST_CHECK_SUM0 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM0_M ((HOST_SLCHOST_CHECK_SUM0_V) << (HOST_SLCHOST_CHECK_SUM0_S)) +#define HOST_SLCHOST_CHECK_SUM0_V 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM0_S 0 + +#define HOST_SLCHOST_CHECK_SUM1_REG (DR_REG_SLCHOST_BASE + 0xC0) +/* HOST_SLCHOST_CHECK_SUM1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLCHOST_CHECK_SUM1 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM1_M ((HOST_SLCHOST_CHECK_SUM1_V) << (HOST_SLCHOST_CHECK_SUM1_S)) +#define HOST_SLCHOST_CHECK_SUM1_V 0xFFFFFFFF +#define HOST_SLCHOST_CHECK_SUM1_S 0 + +#define HOST_SLC0HOST_TOKEN_WDATA_REG (DR_REG_SLCHOST_BASE + 0xC8) +/* HOST_SLC0HOST_TOKEN1_WD : R/W ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN1_WD 0x00000FFF +#define HOST_SLC0HOST_TOKEN1_WD_M ((HOST_SLC0HOST_TOKEN1_WD_V) << (HOST_SLC0HOST_TOKEN1_WD_S)) +#define HOST_SLC0HOST_TOKEN1_WD_V 0xFFF +#define HOST_SLC0HOST_TOKEN1_WD_S 16 +/* HOST_SLC0HOST_TOKEN0_WD : R/W ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN0_WD 0x00000FFF +#define HOST_SLC0HOST_TOKEN0_WD_M ((HOST_SLC0HOST_TOKEN0_WD_V) << (HOST_SLC0HOST_TOKEN0_WD_S)) +#define HOST_SLC0HOST_TOKEN0_WD_V 0xFFF +#define HOST_SLC0HOST_TOKEN0_WD_S 0 + +#define HOST_SLCHOST_TOKEN_CON_REG (DR_REG_SLCHOST_BASE + 0xD0) +/* HOST_SLC0HOST_LEN_WR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_LEN_WR (BIT(8)) +#define HOST_SLC0HOST_LEN_WR_M (BIT(8)) +#define HOST_SLC0HOST_LEN_WR_V 0x1 +#define HOST_SLC0HOST_LEN_WR_S 8 +/* HOST_SLC0HOST_TOKEN1_WR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN1_WR (BIT(3)) +#define HOST_SLC0HOST_TOKEN1_WR_M (BIT(3)) +#define HOST_SLC0HOST_TOKEN1_WR_V 0x1 +#define HOST_SLC0HOST_TOKEN1_WR_S 3 +/* HOST_SLC0HOST_TOKEN0_WR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN0_WR (BIT(2)) +#define HOST_SLC0HOST_TOKEN0_WR_M (BIT(2)) +#define HOST_SLC0HOST_TOKEN0_WR_V 0x1 +#define HOST_SLC0HOST_TOKEN0_WR_S 2 +/* HOST_SLC0HOST_TOKEN1_DEC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN1_DEC (BIT(1)) +#define HOST_SLC0HOST_TOKEN1_DEC_M (BIT(1)) +#define HOST_SLC0HOST_TOKEN1_DEC_V 0x1 +#define HOST_SLC0HOST_TOKEN1_DEC_S 1 +/* HOST_SLC0HOST_TOKEN0_DEC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TOKEN0_DEC (BIT(0)) +#define HOST_SLC0HOST_TOKEN0_DEC_M (BIT(0)) +#define HOST_SLC0HOST_TOKEN0_DEC_V 0x1 +#define HOST_SLC0HOST_TOKEN0_DEC_S 0 + +#define HOST_SLC0HOST_INT_CLR_REG (DR_REG_SLCHOST_BASE + 0xD4) +/* HOST_GPIO_SDIO_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_CLR (BIT(25)) +#define HOST_GPIO_SDIO_INT_CLR_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_CLR_V 0x1 +#define HOST_GPIO_SDIO_INT_CLR_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_CLR_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_CLR_S 23 +/* HOST_SLC0_EXT_BIT3_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_CLR (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_CLR_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_CLR_S 22 +/* HOST_SLC0_EXT_BIT2_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_CLR (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_CLR_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_CLR_S 21 +/* HOST_SLC0_EXT_BIT1_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_CLR (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_CLR_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_CLR_S 20 +/* HOST_SLC0_EXT_BIT0_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_CLR (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_CLR_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_CLR_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_CLR_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_CLR (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_CLR_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_CLR_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_CLR_S 18 +/* HOST_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_CLR (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_CLR_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_CLR_V 0x1 +#define HOST_SLC0_TX_OVF_INT_CLR_S 17 +/* HOST_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_CLR (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_CLR_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_CLR_V 0x1 +#define HOST_SLC0_RX_UDF_INT_CLR_S 16 +/* HOST_SLC0HOST_TX_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_CLR (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_CLR_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_CLR_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_CLR_S 15 +/* HOST_SLC0HOST_RX_START_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_CLR (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_CLR_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_CLR_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_CLR_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_CLR (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_CLR_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_CLR_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_CLR_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_CLR (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_CLR_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_CLR_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_CLR_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_CLR_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_CLR_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_CLR_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_CLR_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_CLR (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_CLR_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_CLR_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_CLR (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_CLR_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_CLR_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_CLR (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_CLR_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_CLR_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_CLR (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_CLR_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_CLR_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_CLR (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_CLR_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_CLR_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_CLR (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_CLR_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_CLR_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_CLR (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_CLR_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_CLR_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_CLR (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_CLR_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_CLR_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_CLR_S 0 + +#define HOST_SLC0HOST_FUNC1_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xDC) +/* HOST_FN1_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_GPIO_SDIO_INT_ENA (BIT(25)) +#define HOST_FN1_GPIO_SDIO_INT_ENA_M (BIT(25)) +#define HOST_FN1_GPIO_SDIO_INT_ENA_V 0x1 +#define HOST_FN1_GPIO_SDIO_INT_ENA_S 25 +/* HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_FN1_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT3_INT_ENA_S 22 +/* HOST_FN1_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT2_INT_ENA_S 21 +/* HOST_FN1_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT1_INT_ENA_S 20 +/* HOST_FN1_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_EXT_BIT0_INT_ENA_S 19 +/* HOST_FN1_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_RX_PF_VALID_INT_ENA_S 18 +/* HOST_FN1_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define HOST_FN1_SLC0_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_FN1_SLC0_TX_OVF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TX_OVF_INT_ENA_S 17 +/* HOST_FN1_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define HOST_FN1_SLC0_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_FN1_SLC0_RX_UDF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_RX_UDF_INT_ENA_S 16 +/* HOST_FN1_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_TX_START_INT_ENA_S 15 +/* HOST_FN1_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_RX_START_INT_ENA_S 14 +/* HOST_FN1_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_RX_EOF_INT_ENA_S 13 +/* HOST_FN1_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_FN1_SLC0HOST_RX_SOF_INT_ENA_S 12 +/* HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_FN1_SLC0_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC0HOST_INT_ENA_REG (DR_REG_SLCHOST_BASE + 0xEC) +/* HOST_GPIO_SDIO_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_ENA (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA_V 0x1 +#define HOST_GPIO_SDIO_INT_ENA_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA_S 23 +/* HOST_SLC0_EXT_BIT3_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_ENA (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_ENA_S 22 +/* HOST_SLC0_EXT_BIT2_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_ENA (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_ENA_S 21 +/* HOST_SLC0_EXT_BIT1_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_ENA (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_ENA_S 20 +/* HOST_SLC0_EXT_BIT0_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_ENA (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_ENA_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_ENA (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_ENA_S 18 +/* HOST_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_ENA (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA_V 0x1 +#define HOST_SLC0_TX_OVF_INT_ENA_S 17 +/* HOST_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_ENA (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA_V 0x1 +#define HOST_SLC0_RX_UDF_INT_ENA_S 16 +/* HOST_SLC0HOST_TX_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_ENA (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_ENA_S 15 +/* HOST_SLC0HOST_RX_START_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_ENA (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_ENA_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_ENA (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_ENA_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_ENA (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_ENA_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_ENA (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_ENA_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_ENA (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_ENA_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_ENA (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_ENA_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_ENA (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_ENA_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_ENA (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_ENA_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_ENA (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_ENA_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_ENA (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_ENA_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_ENA (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_ENA_S 0 + +#define HOST_SLC0HOST_RX_INFOR_REG (DR_REG_SLCHOST_BASE + 0xF4) +/* HOST_SLC0HOST_RX_INFOR : R/W ;bitpos:[19:0] ;default: 20'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_INFOR 0x000FFFFF +#define HOST_SLC0HOST_RX_INFOR_M ((HOST_SLC0HOST_RX_INFOR_V) << (HOST_SLC0HOST_RX_INFOR_S)) +#define HOST_SLC0HOST_RX_INFOR_V 0xFFFFF +#define HOST_SLC0HOST_RX_INFOR_S 0 + +#define HOST_SLC0HOST_LEN_WD_REG (DR_REG_SLCHOST_BASE + 0xFC) +/* HOST_SLC0HOST_LEN_WD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_LEN_WD 0xFFFFFFFF +#define HOST_SLC0HOST_LEN_WD_M ((HOST_SLC0HOST_LEN_WD_V) << (HOST_SLC0HOST_LEN_WD_S)) +#define HOST_SLC0HOST_LEN_WD_V 0xFFFFFFFF +#define HOST_SLC0HOST_LEN_WD_S 0 + +#define HOST_SLC_APBWIN_WDATA_REG (DR_REG_SLCHOST_BASE + 0x100) +/* HOST_SLC_APBWIN_WDATA : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_WDATA 0xFFFFFFFF +#define HOST_SLC_APBWIN_WDATA_M ((HOST_SLC_APBWIN_WDATA_V) << (HOST_SLC_APBWIN_WDATA_S)) +#define HOST_SLC_APBWIN_WDATA_V 0xFFFFFFFF +#define HOST_SLC_APBWIN_WDATA_S 0 + +#define HOST_SLC_APBWIN_CONF_REG (DR_REG_SLCHOST_BASE + 0x104) +/* HOST_SLC_APBWIN_BUS : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_BUS (BIT(30)) +#define HOST_SLC_APBWIN_BUS_M (BIT(30)) +#define HOST_SLC_APBWIN_BUS_V 0x1 +#define HOST_SLC_APBWIN_BUS_S 30 +/* HOST_SLC_APBWIN_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_START (BIT(29)) +#define HOST_SLC_APBWIN_START_M (BIT(29)) +#define HOST_SLC_APBWIN_START_V 0x1 +#define HOST_SLC_APBWIN_START_S 29 +/* HOST_SLC_APBWIN_WR : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_WR (BIT(28)) +#define HOST_SLC_APBWIN_WR_M (BIT(28)) +#define HOST_SLC_APBWIN_WR_V 0x1 +#define HOST_SLC_APBWIN_WR_S 28 +/* HOST_SLC_APBWIN_ADDR : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_ADDR 0x0FFFFFFF +#define HOST_SLC_APBWIN_ADDR_M ((HOST_SLC_APBWIN_ADDR_V) << (HOST_SLC_APBWIN_ADDR_S)) +#define HOST_SLC_APBWIN_ADDR_V 0xFFFFFFF +#define HOST_SLC_APBWIN_ADDR_S 0 + +#define HOST_SLC_APBWIN_RDATA_REG (DR_REG_SLCHOST_BASE + 0x108) +/* HOST_SLC_APBWIN_RDATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define HOST_SLC_APBWIN_RDATA 0xFFFFFFFF +#define HOST_SLC_APBWIN_RDATA_M ((HOST_SLC_APBWIN_RDATA_V) << (HOST_SLC_APBWIN_RDATA_S)) +#define HOST_SLC_APBWIN_RDATA_V 0xFFFFFFFF +#define HOST_SLC_APBWIN_RDATA_S 0 + +#define HOST_SLCHOST_RDCLR0_REG (DR_REG_SLCHOST_BASE + 0x10C) +/* HOST_SLCHOST_SLC0_BIT6_CLRADDR : R/W ;bitpos:[17:9] ;default: 9'h1e0 ; */ +/*description: */ +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR 0x000001FF +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT6_CLRADDR_V) << (HOST_SLCHOST_SLC0_BIT6_CLRADDR_S)) +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_V 0x1FF +#define HOST_SLCHOST_SLC0_BIT6_CLRADDR_S 9 +/* HOST_SLCHOST_SLC0_BIT7_CLRADDR : R/W ;bitpos:[8:0] ;default: 9'h44 ; */ +/*description: */ +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR 0x000001FF +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_M ((HOST_SLCHOST_SLC0_BIT7_CLRADDR_V) << (HOST_SLCHOST_SLC0_BIT7_CLRADDR_S)) +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_V 0x1FF +#define HOST_SLCHOST_SLC0_BIT7_CLRADDR_S 0 + +#define HOST_SLC0HOST_INT_ENA1_REG (DR_REG_SLCHOST_BASE + 0x114) +/* HOST_GPIO_SDIO_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_GPIO_SDIO_INT_ENA1 (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA1_M (BIT(25)) +#define HOST_GPIO_SDIO_INT_ENA1_V 0x1 +#define HOST_GPIO_SDIO_INT_ENA1_S 25 +/* HOST_SLC0_HOST_RD_RETRY_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1 (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_M (BIT(24)) +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_V 0x1 +#define HOST_SLC0_HOST_RD_RETRY_INT_ENA1_S 24 +/* HOST_SLC0_RX_NEW_PACKET_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1 (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_M (BIT(23)) +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_V 0x1 +#define HOST_SLC0_RX_NEW_PACKET_INT_ENA1_S 23 +/* HOST_SLC0_EXT_BIT3_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT3_INT_ENA1 (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA1_M (BIT(22)) +#define HOST_SLC0_EXT_BIT3_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT3_INT_ENA1_S 22 +/* HOST_SLC0_EXT_BIT2_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT2_INT_ENA1 (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA1_M (BIT(21)) +#define HOST_SLC0_EXT_BIT2_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT2_INT_ENA1_S 21 +/* HOST_SLC0_EXT_BIT1_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT1_INT_ENA1 (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA1_M (BIT(20)) +#define HOST_SLC0_EXT_BIT1_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT1_INT_ENA1_S 20 +/* HOST_SLC0_EXT_BIT0_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_EXT_BIT0_INT_ENA1 (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA1_M (BIT(19)) +#define HOST_SLC0_EXT_BIT0_INT_ENA1_V 0x1 +#define HOST_SLC0_EXT_BIT0_INT_ENA1_S 19 +/* HOST_SLC0_RX_PF_VALID_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_PF_VALID_INT_ENA1 (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA1_M (BIT(18)) +#define HOST_SLC0_RX_PF_VALID_INT_ENA1_V 0x1 +#define HOST_SLC0_RX_PF_VALID_INT_ENA1_S 18 +/* HOST_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TX_OVF_INT_ENA1 (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA1_M (BIT(17)) +#define HOST_SLC0_TX_OVF_INT_ENA1_V 0x1 +#define HOST_SLC0_TX_OVF_INT_ENA1_S 17 +/* HOST_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_RX_UDF_INT_ENA1 (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA1_M (BIT(16)) +#define HOST_SLC0_RX_UDF_INT_ENA1_V 0x1 +#define HOST_SLC0_RX_UDF_INT_ENA1_S 16 +/* HOST_SLC0HOST_TX_START_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_TX_START_INT_ENA1 (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA1_M (BIT(15)) +#define HOST_SLC0HOST_TX_START_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_TX_START_INT_ENA1_S 15 +/* HOST_SLC0HOST_RX_START_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_START_INT_ENA1 (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA1_M (BIT(14)) +#define HOST_SLC0HOST_RX_START_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_RX_START_INT_ENA1_S 14 +/* HOST_SLC0HOST_RX_EOF_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_EOF_INT_ENA1 (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA1_M (BIT(13)) +#define HOST_SLC0HOST_RX_EOF_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_RX_EOF_INT_ENA1_S 13 +/* HOST_SLC0HOST_RX_SOF_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0HOST_RX_SOF_INT_ENA1 (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA1_M (BIT(12)) +#define HOST_SLC0HOST_RX_SOF_INT_ENA1_V 0x1 +#define HOST_SLC0HOST_RX_SOF_INT_ENA1_S 12 +/* HOST_SLC0_TOKEN1_0TO1_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1 (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_M (BIT(11)) +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN1_0TO1_INT_ENA1_S 11 +/* HOST_SLC0_TOKEN0_0TO1_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1 (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_M (BIT(10)) +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN0_0TO1_INT_ENA1_S 10 +/* HOST_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(9)) +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN1_1TO0_INT_ENA1_S 9 +/* HOST_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(8)) +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1 +#define HOST_SLC0_TOKEN0_1TO0_INT_ENA1_S 8 +/* HOST_SLC0_TOHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1 (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_M (BIT(7)) +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT7_INT_ENA1_S 7 +/* HOST_SLC0_TOHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1 (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_M (BIT(6)) +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT6_INT_ENA1_S 6 +/* HOST_SLC0_TOHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1 (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_M (BIT(5)) +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT5_INT_ENA1_S 5 +/* HOST_SLC0_TOHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1 (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_M (BIT(4)) +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT4_INT_ENA1_S 4 +/* HOST_SLC0_TOHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1 (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_M (BIT(3)) +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT3_INT_ENA1_S 3 +/* HOST_SLC0_TOHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1 (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_M (BIT(2)) +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT2_INT_ENA1_S 2 +/* HOST_SLC0_TOHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1 (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_M (BIT(1)) +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT1_INT_ENA1_S 1 +/* HOST_SLC0_TOHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1 (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_M (BIT(0)) +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_V 0x1 +#define HOST_SLC0_TOHOST_BIT0_INT_ENA1_S 0 + +#define HOST_SLCHOSTDATE_REG (DR_REG_SLCHOST_BASE + 0x178) +/* HOST_SLCHOST_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */ +/*description: */ +#define HOST_SLCHOST_DATE 0xFFFFFFFF +#define HOST_SLCHOST_DATE_M ((HOST_SLCHOST_DATE_V) << (HOST_SLCHOST_DATE_S)) +#define HOST_SLCHOST_DATE_V 0xFFFFFFFF +#define HOST_SLCHOST_DATE_S 0 + +#define HOST_SLCHOSTID_REG (DR_REG_SLCHOST_BASE + 0x17C) +/* HOST_SLCHOST_ID : R/W ;bitpos:[31:0] ;default: 32'h0600 ; */ +/*description: */ +#define HOST_SLCHOST_ID 0xFFFFFFFF +#define HOST_SLCHOST_ID_M ((HOST_SLCHOST_ID_V) << (HOST_SLCHOST_ID_S)) +#define HOST_SLCHOST_ID_V 0xFFFFFFFF +#define HOST_SLCHOST_ID_S 0 + +#define HOST_SLCHOST_CONF_REG (DR_REG_SLCHOST_BASE + 0x1F0) +/* HOST_HSPEED_CON_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define HOST_HSPEED_CON_EN (BIT(27)) +#define HOST_HSPEED_CON_EN_M (BIT(27)) +#define HOST_HSPEED_CON_EN_V 0x1 +#define HOST_HSPEED_CON_EN_S 27 +/* HOST_SDIO_PAD_PULLUP : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SDIO_PAD_PULLUP (BIT(26)) +#define HOST_SDIO_PAD_PULLUP_M (BIT(26)) +#define HOST_SDIO_PAD_PULLUP_V 0x1 +#define HOST_SDIO_PAD_PULLUP_S 26 +/* HOST_SDIO20_INT_DELAY : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define HOST_SDIO20_INT_DELAY (BIT(25)) +#define HOST_SDIO20_INT_DELAY_M (BIT(25)) +#define HOST_SDIO20_INT_DELAY_V 0x1 +#define HOST_SDIO20_INT_DELAY_S 25 +/* HOST_FRC_QUICK_IN : R/W ;bitpos:[24:20] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_QUICK_IN 0x0000001F +#define HOST_FRC_QUICK_IN_M ((HOST_FRC_QUICK_IN_V) << (HOST_FRC_QUICK_IN_S)) +#define HOST_FRC_QUICK_IN_V 0x1F +#define HOST_FRC_QUICK_IN_S 20 +/* HOST_FRC_POS_SAMP : R/W ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_POS_SAMP 0x0000001F +#define HOST_FRC_POS_SAMP_M ((HOST_FRC_POS_SAMP_V) << (HOST_FRC_POS_SAMP_S)) +#define HOST_FRC_POS_SAMP_V 0x1F +#define HOST_FRC_POS_SAMP_S 15 +/* HOST_FRC_NEG_SAMP : R/W ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_NEG_SAMP 0x0000001F +#define HOST_FRC_NEG_SAMP_M ((HOST_FRC_NEG_SAMP_V) << (HOST_FRC_NEG_SAMP_S)) +#define HOST_FRC_NEG_SAMP_V 0x1F +#define HOST_FRC_NEG_SAMP_S 10 +/* HOST_FRC_SDIO20 : R/W ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_SDIO20 0x0000001F +#define HOST_FRC_SDIO20_M ((HOST_FRC_SDIO20_V) << (HOST_FRC_SDIO20_S)) +#define HOST_FRC_SDIO20_V 0x1F +#define HOST_FRC_SDIO20_S 5 +/* HOST_FRC_SDIO11 : R/W ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: */ +#define HOST_FRC_SDIO11 0x0000001F +#define HOST_FRC_SDIO11_M ((HOST_FRC_SDIO11_V) << (HOST_FRC_SDIO11_S)) +#define HOST_FRC_SDIO11_V 0x1F +#define HOST_FRC_SDIO11_S 0 + +#define HOST_SLCHOST_INF_ST_REG (DR_REG_SLCHOST_BASE + 0x1F4) +/* HOST_SDIO_QUICK_IN : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: */ +#define HOST_SDIO_QUICK_IN 0x0000001F +#define HOST_SDIO_QUICK_IN_M ((HOST_SDIO_QUICK_IN_V) << (HOST_SDIO_QUICK_IN_S)) +#define HOST_SDIO_QUICK_IN_V 0x1F +#define HOST_SDIO_QUICK_IN_S 10 +/* HOST_SDIO_NEG_SAMP : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: */ +#define HOST_SDIO_NEG_SAMP 0x0000001F +#define HOST_SDIO_NEG_SAMP_M ((HOST_SDIO_NEG_SAMP_V) << (HOST_SDIO_NEG_SAMP_S)) +#define HOST_SDIO_NEG_SAMP_V 0x1F +#define HOST_SDIO_NEG_SAMP_S 5 +/* HOST_SDIO20_MODE : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: */ +#define HOST_SDIO20_MODE 0x0000001F +#define HOST_SDIO20_MODE_M ((HOST_SDIO20_MODE_V) << (HOST_SDIO20_MODE_S)) +#define HOST_SDIO20_MODE_V 0x1F +#define HOST_SDIO20_MODE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/host_struct.h b/components/soc/soc/esp32s3/include/soc/host_struct.h new file mode 100644 index 000000000..53afef485 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/host_struct.h @@ -0,0 +1,604 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; + uint32_t reserved_c; + uint32_t reserved_10; + uint32_t reserved_14; + uint32_t reserved_18; + uint32_t reserved_1c; + union { + struct { + uint32_t func1_mdstat: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } func2_2; + uint32_t reserved_24; + uint32_t reserved_28; + uint32_t reserved_2c; + uint32_t reserved_30; + uint32_t gpio_status0; /**/ + union { + struct { + uint32_t sdio_int1: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } gpio_status1; + uint32_t gpio_in0; /**/ + union { + struct { + uint32_t sdio_in1: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } gpio_in1; + union { + struct { + uint32_t token0: 12; + uint32_t rx_pf_valid: 1; + uint32_t reserved13: 3; + uint32_t reg_token1: 12; + uint32_t rx_pf_eof: 4; + }; + uint32_t val; + } slc0_token_rdata; + uint32_t slc0_pf; /**/ + uint32_t reserved_4c; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_raw; + uint32_t reserved_54; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_st; + uint32_t reserved_5c; + union { + struct { + uint32_t reg_slc0_len: 20; + uint32_t reg_slc0_len_check: 12; + }; + uint32_t val; + } pkt_len; + union { + struct { + uint32_t state0: 8; + uint32_t state1: 8; + uint32_t state2: 8; + uint32_t state3: 8; + }; + uint32_t val; + } state_w0; + union { + struct { + uint32_t state4: 8; + uint32_t state5: 8; + uint32_t state6: 8; + uint32_t state7: 8; + }; + uint32_t val; + } state_w1; + union { + struct { + uint32_t conf0: 8; + uint32_t conf1: 8; + uint32_t conf2: 8; + uint32_t conf3: 8; + }; + uint32_t val; + } conf_w0; + union { + struct { + uint32_t conf4: 8; + uint32_t conf5: 8; + uint32_t conf6: 8; + uint32_t conf7: 8; + }; + uint32_t val; + } conf_w1; + union { + struct { + uint32_t conf8: 8; + uint32_t conf9: 8; + uint32_t conf10: 8; + uint32_t conf11: 8; + }; + uint32_t val; + } conf_w2; + union { + struct { + uint32_t conf12: 8; + uint32_t conf13: 8; + uint32_t conf14: 8; + uint32_t conf15: 8; + }; + uint32_t val; + } conf_w3; + union { + struct { + uint32_t conf16: 8; /*SLC timeout value*/ + uint32_t conf17: 8; /*SLC timeout enable*/ + uint32_t conf18: 8; + uint32_t conf19: 8; /*Interrupt to target CPU*/ + }; + uint32_t val; + } conf_w4; + union { + struct { + uint32_t conf20: 8; + uint32_t conf21: 8; + uint32_t conf22: 8; + uint32_t conf23: 8; + }; + uint32_t val; + } conf_w5; + union { + struct { + uint32_t win_cmd: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } win_cmd; + union { + struct { + uint32_t conf24: 8; + uint32_t conf25: 8; + uint32_t conf26: 8; + uint32_t conf27: 8; + }; + uint32_t val; + } conf_w6; + union { + struct { + uint32_t conf28: 8; + uint32_t conf29: 8; + uint32_t conf30: 8; + uint32_t conf31: 8; + }; + uint32_t val; + } conf_w7; + union { + struct { + uint32_t reg_slc0_len0: 20; + uint32_t reg_slc0_len0_check: 12; + }; + uint32_t val; + } pkt_len0; + union { + struct { + uint32_t reg_slc0_len1: 20; + uint32_t reg_slc0_len1_check: 12; + }; + uint32_t val; + } pkt_len1; + union { + struct { + uint32_t reg_slc0_len2: 20; + uint32_t reg_slc0_len2_check: 12; + }; + uint32_t val; + } pkt_len2; + union { + struct { + uint32_t conf32: 8; + uint32_t conf33: 8; + uint32_t conf34: 8; + uint32_t conf35: 8; + }; + uint32_t val; + } conf_w8; + union { + struct { + uint32_t conf36: 8; + uint32_t conf37: 8; + uint32_t conf38: 8; + uint32_t conf39: 8; + }; + uint32_t val; + } conf_w9; + union { + struct { + uint32_t conf40: 8; + uint32_t conf41: 8; + uint32_t conf42: 8; + uint32_t conf43: 8; + }; + uint32_t val; + } conf_w10; + union { + struct { + uint32_t conf44: 8; + uint32_t conf45: 8; + uint32_t conf46: 8; + uint32_t conf47: 8; + }; + uint32_t val; + } conf_w11; + union { + struct { + uint32_t conf48: 8; + uint32_t conf49: 8; + uint32_t conf50: 8; + uint32_t conf51: 8; + }; + uint32_t val; + } conf_w12; + union { + struct { + uint32_t conf52: 8; + uint32_t conf53: 8; + uint32_t conf54: 8; + uint32_t conf55: 8; + }; + uint32_t val; + } conf_w13; + union { + struct { + uint32_t conf56: 8; + uint32_t conf57: 8; + uint32_t conf58: 8; + uint32_t conf59: 8; + }; + uint32_t val; + } conf_w14; + union { + struct { + uint32_t conf60: 8; + uint32_t conf61: 8; + uint32_t conf62: 8; + uint32_t conf63: 8; + }; + uint32_t val; + } conf_w15; + uint32_t check_sum0; /**/ + uint32_t check_sum1; /**/ + uint32_t reserved_c4; + union { + struct { + uint32_t token0_wd: 12; + uint32_t reserved12: 4; + uint32_t token1_wd: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_token_wdata; + uint32_t reserved_cc; + union { + struct { + uint32_t slc0_token0_dec: 1; + uint32_t slc0_token1_dec: 1; + uint32_t slc0_token0_wr: 1; + uint32_t slc0_token1_wr: 1; + uint32_t reserved4: 4; + uint32_t slc0_len_wr: 1; + uint32_t reserved9: 23; + }; + uint32_t val; + } token_con; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_clr; + uint32_t reserved_d8; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_func1_int_ena; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + union { + struct { + uint32_t tohost_bit0: 1; + uint32_t tohost_bit1: 1; + uint32_t tohost_bit2: 1; + uint32_t tohost_bit3: 1; + uint32_t tohost_bit4: 1; + uint32_t tohost_bit5: 1; + uint32_t tohost_bit6: 1; + uint32_t tohost_bit7: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t token0_0to1: 1; + uint32_t token1_0to1: 1; + uint32_t rx_sof: 1; + uint32_t rx_eof: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t rx_pf_valid: 1; + uint32_t ext_bit0: 1; + uint32_t ext_bit1: 1; + uint32_t ext_bit2: 1; + uint32_t ext_bit3: 1; + uint32_t rx_new_packet: 1; + uint32_t rd_retry: 1; + uint32_t gpio_sdio: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_ena; + uint32_t reserved_f0; + union { + struct { + uint32_t infor: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } slc0_rx_infor; + uint32_t reserved_f8; + uint32_t slc0_len_wd; /**/ + uint32_t apbwin_wdata; /**/ + union { + struct { + uint32_t addr: 28; + uint32_t wr: 1; + uint32_t start: 1; + uint32_t bus: 1; + uint32_t reserved31: 1; + }; + uint32_t val; + } apbwin_conf; + uint32_t apbwin_rdata; /**/ + union { + struct { + uint32_t bit7_clraddr: 9; + uint32_t bit6_clraddr: 9; + uint32_t reserved18: 14; + }; + uint32_t val; + } slc0_rdclr; + uint32_t reserved_110; + union { + struct { + uint32_t tohost_bit01: 1; + uint32_t tohost_bit11: 1; + uint32_t tohost_bit21: 1; + uint32_t tohost_bit31: 1; + uint32_t tohost_bit41: 1; + uint32_t tohost_bit51: 1; + uint32_t tohost_bit61: 1; + uint32_t tohost_bit71: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t token0_0to11: 1; + uint32_t token1_0to11: 1; + uint32_t rx_sof1: 1; + uint32_t rx_eof1: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t rx_pf_valid1: 1; + uint32_t ext_bit01: 1; + uint32_t ext_bit11: 1; + uint32_t ext_bit21: 1; + uint32_t ext_bit31: 1; + uint32_t rx_new_packet1: 1; + uint32_t rd_retry1: 1; + uint32_t gpio_sdio1: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } slc0_int_ena1; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t date; /**/ + uint32_t id; /**/ + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + union { + struct { + uint32_t frc_sdio11: 5; + uint32_t frc_sdio20: 5; + uint32_t frc_neg_samp: 5; + uint32_t frc_pos_samp: 5; + uint32_t frc_quick_in: 5; + uint32_t sdio20_int_delay: 1; + uint32_t sdio_pad_pullup: 1; + uint32_t hspeed_con_en: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t sdio20_mode: 5; + uint32_t sdio_neg_samp: 5; + uint32_t sdio_quick_in: 5; + uint32_t reserved15: 17; + }; + uint32_t val; + } inf_st; +} host_dev_t; + +extern host_dev_t HOST; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/hwcrypto_reg.h b/components/soc/soc/esp32s3/include/soc/hwcrypto_reg.h new file mode 100644 index 000000000..97ce6e35b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/hwcrypto_reg.h @@ -0,0 +1,238 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc.h" + +/* registers for RSA acceleration via Multiple Precision Integer ops */ +#define RSA_MEM_M_BLOCK_BASE ((DR_REG_RSA_BASE)+0x000) +/* RB & Z use the same memory block, depending on phase of operation */ +#define RSA_MEM_RB_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) +#define RSA_MEM_Z_BLOCK_BASE ((DR_REG_RSA_BASE)+0x200) +#define RSA_MEM_Y_BLOCK_BASE ((DR_REG_RSA_BASE)+0x400) +#define RSA_MEM_X_BLOCK_BASE ((DR_REG_RSA_BASE)+0x600) + +/* Configuration registers */ +#define RSA_M_DASH_REG (DR_REG_RSA_BASE + 0x800) +#define RSA_LENGTH_REG (DR_REG_RSA_BASE + 0x804) +#define RSA_CONSTANT_TIME_REG (DR_REG_RSA_BASE + 0x820) +#define RSA_SEARCH_OPEN_REG (DR_REG_RSA_BASE + 0x824) +#define RSA_SEARCH_POS_REG (DR_REG_RSA_BASE + 0x828) + +/* Initialization registers */ +#define RSA_QUERY_CLEAN_REG (DR_REG_RSA_BASE + 0x808) + +/* Calculation start registers */ +#define RSA_MODEXP_START_REG (DR_REG_RSA_BASE + 0x80c) +#define RSA_MOD_MULT_START_REG (DR_REG_RSA_BASE + 0x810) +#define RSA_MULT_START_REG (DR_REG_RSA_BASE + 0x814) + +/* Interrupt registers */ +#define RSA_QUERY_INTERRUPT_REG (DR_REG_RSA_BASE + 0x818) +#define RSA_CLEAR_INTERRUPT_REG (DR_REG_RSA_BASE + 0x81C) +#define RSA_INTERRUPT_REG (DR_REG_RSA_BASE + 0x82C) + +#define SHA_MODE_SHA1 0 +#define SHA_MODE_SHA224 1 +#define SHA_MODE_SHA256 2 +#define SHA_MODE_SHA384 3 +#define SHA_MODE_SHA512 4 +#define SHA_MODE_SHA512_224 5 +#define SHA_MODE_SHA512_256 6 +#define SHA_MODE_SHA512_T 7 + +/* SHA acceleration registers */ +#define SHA_MODE_REG ((DR_REG_SHA_BASE) + 0x00) +#define SHA_T_STRING_REG ((DR_REG_SHA_BASE) + 0x04) +#define SHA_T_LENGTH_REG ((DR_REG_SHA_BASE) + 0x08) +#define SHA_BLOCK_NUM_REG ((DR_REG_SHA_BASE) + 0x0C) +#define SHA_START_REG ((DR_REG_SHA_BASE) + 0x10) +#define SHA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x14) +#define SHA_BUSY_REG ((DR_REG_SHA_BASE) + 0x18) +#define SHA_DMA_START_REG ((DR_REG_SHA_BASE) + 0x1C) +#define SHA_DMA_CONTINUE_REG ((DR_REG_SHA_BASE) + 0x20) +#define SHA_CLEAR_IRQ_REG ((DR_REG_SHA_BASE) + 0x24) +#define SHA_INT_ENA_REG ((DR_REG_SHA_BASE) + 0x28) + +#define SHA_H_BASE ((DR_REG_SHA_BASE) + 0x40) +#define SHA_TEXT_BASE ((DR_REG_SHA_BASE) + 0x80) + +/* AES Block operation modes */ +#define AES_BLOCK_MODE_ECB 0 +#define AES_BLOCK_MODE_CBC 1 +#define AES_BLOCK_MODE_OFB 2 +#define AES_BLOCK_MODE_CTR 3 +#define AES_BLOCK_MODE_CFB8 4 +#define AES_BLOCK_MODE_CFB128 5 +#define AES_BLOCK_MODE_GCM 6 + +/* AES Block operation modes (used with DMA) */ +#define AES_BLOCK_MODE_ECB 0 +#define AES_BLOCK_MODE_CBC 1 +#define AES_BLOCK_MODE_OFB 2 +#define AES_BLOCK_MODE_CTR 3 +#define AES_BLOCK_MODE_CFB8 4 +#define AES_BLOCK_MODE_CFB128 5 +#define AES_BLOCK_MODE_GCM 6 + +/* AES acceleration registers */ +#define AES_MODE_REG ((DR_REG_AES_BASE) + 0x40) +#define AES_ENDIAN_REG ((DR_REG_AES_BASE) + 0x44) +#define AES_TRIGGER_REG ((DR_REG_AES_BASE) + 0x48) +#define AES_STATE_REG ((DR_REG_AES_BASE) + 0x4c) +#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) +#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) +#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) +#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) +#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) +#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) +#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) +#define AES_INT_CLEAR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) +#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) +#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) + +#define AES_DMA_ENABLE_REG ((DR_REG_AES_BASE) + 0x90) +#define AES_BLOCK_MODE_REG ((DR_REG_AES_BASE) + 0x94) +#define AES_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0x98) +#define AES_INC_SEL_REG ((DR_REG_AES_BASE) + 0x9C) +#define AES_AAD_BLOCK_NUM_REG ((DR_REG_AES_BASE) + 0xA0) +#define AES_BIT_VALID_NUM_REG ((DR_REG_AES_BASE) + 0xA4) +#define AES_CONTINUE_REG ((DR_REG_AES_BASE) + 0xA8) + +#define AES_KEY_BASE ((DR_REG_AES_BASE) + 0x00) +#define AES_TEXT_IN_BASE ((DR_REG_AES_BASE) + 0x20) +#define AES_TEXT_OUT_BASE ((DR_REG_AES_BASE) + 0x30) +#define AES_IV_BASE ((DR_REG_AES_BASE) + 0x50) +#define AES_H_BASE ((DR_REG_AES_BASE) + 0x60) +#define AES_J_BASE ((DR_REG_AES_BASE) + 0x70) +#define AES_T_BASE ((DR_REG_AES_BASE) + 0x80) + +#define AES_INT_CLR_REG ((DR_REG_AES_BASE) + 0xAC) +#define AES_INT_ENA_REG ((DR_REG_AES_BASE) + 0xB0) +#define AES_DATE_REG ((DR_REG_AES_BASE) + 0xB4) +#define AES_DMA_EXIT_REG ((DR_REG_AES_BASE) + 0xB8) + +/* AES_STATE_REG values */ +#define AES_STATE_IDLE 0 +#define AES_STATE_BUSY 1 +#define AES_STATE_DONE 2 + + +/* Crypto DMA */ +#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00) +#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04) +#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08) +#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C) +#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10) +#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14) +#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18) +#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C) +#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20) +#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24) +#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28) +#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C) +#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30) +#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34) +#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38) +#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C) +#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40) +#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44) +#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48) +#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C) +#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50) +#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54) +#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58) +#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C) +#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60) +#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64) +#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC) + +/* HMAC Module */ +#define HMAC_SET_START_REG ((DR_REG_HMAC_BASE) + 0x40) +#define HMAC_SET_PARA_PURPOSE_REG ((DR_REG_HMAC_BASE) + 0x44) +#define HMAC_SET_PARA_KEY_REG ((DR_REG_HMAC_BASE) + 0x48) +#define HMAC_SET_PARA_FINISH_REG ((DR_REG_HMAC_BASE) + 0x4c) +#define HMAC_SET_MESSAGE_ONE_REG ((DR_REG_HMAC_BASE) + 0x50) +#define HMAC_SET_MESSAGE_ING_REG ((DR_REG_HMAC_BASE) + 0x54) +#define HMAC_SET_MESSAGE_END_REG ((DR_REG_HMAC_BASE) + 0x58) +#define HMAC_SET_RESULT_FINISH_REG ((DR_REG_HMAC_BASE) + 0x5c) +#define HMAC_SET_INVALIDATE_JTAG_REG ((DR_REG_HMAC_BASE) + 0x60) +#define HMAC_SET_INVALIDATE_DS_REG ((DR_REG_HMAC_BASE) + 0x64) +#define HMAC_QUERY_ERROR_REG ((DR_REG_HMAC_BASE) + 0x68) +#define HMAC_QUERY_BUSY_REG ((DR_REG_HMAC_BASE) + 0x6c) + +#define HMAC_WDATA_BASE ((DR_REG_HMAC_BASE) + 0x80) +#define HMAC_RDATA_BASE ((DR_REG_HMAC_BASE) + 0xC0) +#define HMAC_SET_MESSAGE_PAD_REG ((DR_REG_HMAC_BASE) + 0xF0) +#define HMAC_ONE_BLOCK_REG ((DR_REG_HMAC_BASE) + 0xF4) + +/* AES-XTS registers */ +#define AES_XTS_PLAIN_BASE ((DR_REG_AES_BASE) + 0x100) +#define AES_XTS_SIZE_REG ((DR_REG_AES_BASE) + 0x140) +#define AES_XTS_DESTINATION_REG ((DR_REG_AES_BASE) + 0x144) +#define AES_XTS_PHYSICAL_ADDR_REG ((DR_REG_AES_BASE) + 0x148) + +#define AES_XTS_TRIGGER_REG ((DR_REG_AES_BASE) + 0x14C) +#define AES_XTS_RELEASE_REG ((DR_REG_AES_BASE) + 0x150) +#define AES_XTS_DESTROY_REG ((DR_REG_AES_BASE) + 0x154) +#define AES_XTS_STATE_REG ((DR_REG_AES_BASE) + 0x158) + +/* Digital Signature registers*/ +#define DS_C_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x000 ) +#define DS_IV_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x630 ) +#define DS_X_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0x800 ) +#define DS_Z_BASE ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xA00 ) + +#define DS_SET_START_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE00) +#define DS_SET_ME_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE04) +#define DS_SET_FINISH_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE08) + +#define DS_QUERY_BUSY_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE0C) +#define DS_QUERY_KEY_WRONG_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE10) +#define DS_QUERY_CHECK_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE14) + +#define DS_QUERY_CHECK_INVALID_DIGEST (1<<0) +#define DS_QUERY_CHECK_INVALID_PADDING (1<<1) + +#define DS_DATE_REG ((DR_REG_DIGITAL_SIGNATURE_BASE) + 0xE20) + +/* Crypto DMA */ +#define CRYPTO_DMA_CONF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x00) +#define CRYPTO_DMA_INT_RAW_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x04) +#define CRYPTO_DMA_INT_ST_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x08) +#define CRYPTO_DMA_INT_ENA_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x0C) +#define CRYPTO_DMA_INT_CLR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x10) +#define CRYPTO_DMA_OUT_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x14) +#define CRYPTO_DMA_OUT_PUSH_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x18) +#define CRYPTO_DMA_IN_STATUS_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x1C) +#define CRYPTO_DMA_IN_POP_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x20) +#define CRYPTO_DMA_OUT_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x24) +#define CRYPTO_DMA_IN_LINK_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x28) +#define CRYPTO_DMA_CONF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x2C) +#define CRYPTO_DMA_STATE0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x30) +#define CRYPTO_DMA_STATE1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x34) +#define CRYPTO_DMA_OUT_EOF_DES_ADDR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x38) +#define CRYPTO_DMA_IN_SUC_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x3C) +#define CRYPTO_DMA_IN_ERR_EOF_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x40) +#define CRYPTO_DMA_OUT_EOF_BFR_DES_ADDR ((DR_REG_CRYPTO_DMA_BASE) + 0x44) +#define CRYPTO_DMA_AHB_TEST ((DR_REG_CRYPTO_DMA_BASE) + 0x48) +#define CRYPTO_DMA_IN_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x4C) +#define CRYPTO_DMA_IN_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x50) +#define CRYPTO_DMA_IN_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x54) +#define CRYPTO_DMA_OUT_DSCR_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x58) +#define CRYPTO_DMA_OUT_DSCR_BF0_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x5C) +#define CRYPTO_DMA_OUT_DSCR_BF1_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x60) +#define CRYPTO_DMA_AES_SHA_SELECT_REG ((DR_REG_CRYPTO_DMA_BASE) + 0x64) +#define CRYPTO_DMA_DATE_REG ((DR_REG_CRYPTO_DMA_BASE) + 0xFC) diff --git a/components/soc/soc/esp32s3/include/soc/i2c_caps.h b/components/soc/soc/esp32s3/include/soc/i2c_caps.h new file mode 100644 index 000000000..f95be82a5 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/i2c_caps.h @@ -0,0 +1,36 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32-S3 have 2 I2C. +#define SOC_I2C_NUM (2) + +#define SOC_I2C_FIFO_LEN (32) /*!< I2C hardware FIFO depth */ +#define I2C_INTR_MASK (0x3fff) /*!< I2C all interrupt bitmap */ + +//ESP32-S3 support hardware FSM reset +#define I2C_SUPPORT_HW_FSM_RST (1) +//ESP32-S3 support hardware clear bus +#define I2C_SUPPORT_HW_CLR_BUS (1) + +#ifdef __cplusplus +} +#endif + + diff --git a/components/soc/soc/esp32s3/include/soc/i2c_reg.h b/components/soc/soc/esp32s3/include/soc/i2c_reg.h new file mode 100644 index 000000000..7baf774bf --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/i2c_reg.h @@ -0,0 +1,1070 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define I2C_SCL_LOW_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0000) +/* I2C_SCL_LOW_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_SCL_LOW_PERIOD 0x00003FFF +#define I2C_SCL_LOW_PERIOD_M ((I2C_SCL_LOW_PERIOD_V) << (I2C_SCL_LOW_PERIOD_S)) +#define I2C_SCL_LOW_PERIOD_V 0x3FFF +#define I2C_SCL_LOW_PERIOD_S 0 + +#define I2C_CTR_REG(i) (REG_I2C_BASE(i) + 0x0004) +/* I2C_REF_ALWAYS_ON : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define I2C_REF_ALWAYS_ON (BIT(11)) +#define I2C_REF_ALWAYS_ON_M (BIT(11)) +#define I2C_REF_ALWAYS_ON_V 0x1 +#define I2C_REF_ALWAYS_ON_S 11 +/* I2C_FSM_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2C_FSM_RST (BIT(10)) +#define I2C_FSM_RST_M (BIT(10)) +#define I2C_FSM_RST_V 0x1 +#define I2C_FSM_RST_S 10 +/* I2C_ARBITRATION_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define I2C_ARBITRATION_EN (BIT(9)) +#define I2C_ARBITRATION_EN_M (BIT(9)) +#define I2C_ARBITRATION_EN_V 0x1 +#define I2C_ARBITRATION_EN_S 9 +/* I2C_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2C_CLK_EN (BIT(8)) +#define I2C_CLK_EN_M (BIT(8)) +#define I2C_CLK_EN_V 0x1 +#define I2C_CLK_EN_S 8 +/* I2C_RX_LSB_FIRST : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define I2C_RX_LSB_FIRST (BIT(7)) +#define I2C_RX_LSB_FIRST_M (BIT(7)) +#define I2C_RX_LSB_FIRST_V 0x1 +#define I2C_RX_LSB_FIRST_S 7 +/* I2C_TX_LSB_FIRST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TX_LSB_FIRST (BIT(6)) +#define I2C_TX_LSB_FIRST_M (BIT(6)) +#define I2C_TX_LSB_FIRST_V 0x1 +#define I2C_TX_LSB_FIRST_S 6 +/* I2C_TRANS_START : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_START (BIT(5)) +#define I2C_TRANS_START_M (BIT(5)) +#define I2C_TRANS_START_V 0x1 +#define I2C_TRANS_START_S 5 +/* I2C_MS_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2C_MS_MODE (BIT(4)) +#define I2C_MS_MODE_M (BIT(4)) +#define I2C_MS_MODE_V 0x1 +#define I2C_MS_MODE_S 4 +/* I2C_ACK_LEVEL : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define I2C_ACK_LEVEL (BIT(3)) +#define I2C_ACK_LEVEL_M (BIT(3)) +#define I2C_ACK_LEVEL_V 0x1 +#define I2C_ACK_LEVEL_S 3 +/* I2C_SAMPLE_SCL_LEVEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SAMPLE_SCL_LEVEL (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_M (BIT(2)) +#define I2C_SAMPLE_SCL_LEVEL_V 0x1 +#define I2C_SAMPLE_SCL_LEVEL_S 2 +/* I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define I2C_SCL_FORCE_OUT (BIT(1)) +#define I2C_SCL_FORCE_OUT_M (BIT(1)) +#define I2C_SCL_FORCE_OUT_V 0x1 +#define I2C_SCL_FORCE_OUT_S 1 +/* I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define I2C_SDA_FORCE_OUT (BIT(0)) +#define I2C_SDA_FORCE_OUT_M (BIT(0)) +#define I2C_SDA_FORCE_OUT_V 0x1 +#define I2C_SDA_FORCE_OUT_S 0 + +#define I2C_SR_REG(i) (REG_I2C_BASE(i) + 0x0008) +/* I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: */ +#define I2C_SCL_STATE_LAST 0x00000007 +#define I2C_SCL_STATE_LAST_M ((I2C_SCL_STATE_LAST_V) << (I2C_SCL_STATE_LAST_S)) +#define I2C_SCL_STATE_LAST_V 0x7 +#define I2C_SCL_STATE_LAST_S 28 +/* I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: */ +#define I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define I2C_SCL_MAIN_STATE_LAST_M ((I2C_SCL_MAIN_STATE_LAST_V) << (I2C_SCL_MAIN_STATE_LAST_S)) +#define I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define I2C_SCL_MAIN_STATE_LAST_S 24 +/* I2C_TXFIFO_CNT : RO ;bitpos:[23:18] ;default: 6'b0 ; */ +/*description: */ +#define I2C_TXFIFO_CNT 0x0000003F +#define I2C_TXFIFO_CNT_M ((I2C_TXFIFO_CNT_V) << (I2C_TXFIFO_CNT_S)) +#define I2C_TXFIFO_CNT_V 0x3F +#define I2C_TXFIFO_CNT_S 18 +/* I2C_RXFIFO_CNT : RO ;bitpos:[13:8] ;default: 6'b0 ; */ +/*description: */ +#define I2C_RXFIFO_CNT 0x0000003F +#define I2C_RXFIFO_CNT_M ((I2C_RXFIFO_CNT_V) << (I2C_RXFIFO_CNT_S)) +#define I2C_RXFIFO_CNT_V 0x3F +#define I2C_RXFIFO_CNT_S 8 +/* I2C_BYTE_TRANS : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2C_BYTE_TRANS (BIT(6)) +#define I2C_BYTE_TRANS_M (BIT(6)) +#define I2C_BYTE_TRANS_V 0x1 +#define I2C_BYTE_TRANS_S 6 +/* I2C_SLAVE_ADDRESSED : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_ADDRESSED (BIT(5)) +#define I2C_SLAVE_ADDRESSED_M (BIT(5)) +#define I2C_SLAVE_ADDRESSED_V 0x1 +#define I2C_SLAVE_ADDRESSED_S 5 +/* I2C_BUS_BUSY : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2C_BUS_BUSY (BIT(4)) +#define I2C_BUS_BUSY_M (BIT(4)) +#define I2C_BUS_BUSY_V 0x1 +#define I2C_BUS_BUSY_S 4 +/* I2C_ARB_LOST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ARB_LOST (BIT(3)) +#define I2C_ARB_LOST_M (BIT(3)) +#define I2C_ARB_LOST_V 0x1 +#define I2C_ARB_LOST_S 3 +/* I2C_TIME_OUT : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TIME_OUT (BIT(2)) +#define I2C_TIME_OUT_M (BIT(2)) +#define I2C_TIME_OUT_V 0x1 +#define I2C_TIME_OUT_S 2 +/* I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_RW (BIT(1)) +#define I2C_SLAVE_RW_M (BIT(1)) +#define I2C_SLAVE_RW_V 0x1 +#define I2C_SLAVE_RW_S 1 +/* I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ACK_REC (BIT(0)) +#define I2C_ACK_REC_M (BIT(0)) +#define I2C_ACK_REC_V 0x1 +#define I2C_ACK_REC_S 0 + +#define I2C_TO_REG(i) (REG_I2C_BASE(i) + 0x000c) +/* I2C_TIME_OUT_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TIME_OUT_EN (BIT(24)) +#define I2C_TIME_OUT_EN_M (BIT(24)) +#define I2C_TIME_OUT_EN_V 0x1 +#define I2C_TIME_OUT_EN_S 24 +/* I2C_TIME_OUT_REG : R/W ;bitpos:[23:0] ;default: 24'b0 ; */ +/*description: */ +#define I2C_TIME_OUT_REG 0x00FFFFFF +#define I2C_TIME_OUT_REG_M ((I2C_TIME_OUT_REG_V) << (I2C_TIME_OUT_REG_S)) +#define I2C_TIME_OUT_REG_V 0xFFFFFF +#define I2C_TIME_OUT_REG_S 0 + +#define I2C_SLAVE_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0010) +/* I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ADDR_10BIT_EN (BIT(31)) +#define I2C_ADDR_10BIT_EN_M (BIT(31)) +#define I2C_ADDR_10BIT_EN_V 0x1 +#define I2C_ADDR_10BIT_EN_S 31 +/* I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: */ +#define I2C_SLAVE_ADDR 0x00007FFF +#define I2C_SLAVE_ADDR_M ((I2C_SLAVE_ADDR_V) << (I2C_SLAVE_ADDR_S)) +#define I2C_SLAVE_ADDR_V 0x7FFF +#define I2C_SLAVE_ADDR_S 0 + +#define I2C_RXFIFO_ST_REG(i) (REG_I2C_BASE(i) + 0x0014) +/* I2C_RXFIFO_INIT_WADDR : RO ;bitpos:[31:27] ;default: 5'b0 ; */ +/*description: */ +#define I2C_RXFIFO_INIT_WADDR 0x0000001F +#define I2C_RXFIFO_INIT_WADDR_M ((I2C_RXFIFO_INIT_WADDR_V) << (I2C_RXFIFO_INIT_WADDR_S)) +#define I2C_RXFIFO_INIT_WADDR_V 0x1F +#define I2C_RXFIFO_INIT_WADDR_S 27 +/* I2C_TXFIFO_INIT_RADDR : RO ;bitpos:[26:22] ;default: 5'b0 ; */ +/*description: */ +#define I2C_TXFIFO_INIT_RADDR 0x0000001F +#define I2C_TXFIFO_INIT_RADDR_M ((I2C_TXFIFO_INIT_RADDR_V) << (I2C_TXFIFO_INIT_RADDR_S)) +#define I2C_TXFIFO_INIT_RADDR_V 0x1F +#define I2C_TXFIFO_INIT_RADDR_S 22 +/* I2C_TX_UPDATE : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TX_UPDATE (BIT(21)) +#define I2C_TX_UPDATE_M (BIT(21)) +#define I2C_TX_UPDATE_V 0x1 +#define I2C_TX_UPDATE_S 21 +/* I2C_RX_UPDATE : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RX_UPDATE (BIT(20)) +#define I2C_RX_UPDATE_M (BIT(20)) +#define I2C_RX_UPDATE_V 0x1 +#define I2C_RX_UPDATE_S 20 +/* I2C_TXFIFO_END_ADDR : RO ;bitpos:[19:15] ;default: 5'b0 ; */ +/*description: */ +#define I2C_TXFIFO_END_ADDR 0x0000001F +#define I2C_TXFIFO_END_ADDR_M ((I2C_TXFIFO_END_ADDR_V) << (I2C_TXFIFO_END_ADDR_S)) +#define I2C_TXFIFO_END_ADDR_V 0x1F +#define I2C_TXFIFO_END_ADDR_S 15 +/* I2C_TXFIFO_START_ADDR : RO ;bitpos:[14:10] ;default: 5'b0 ; */ +/*description: */ +#define I2C_TXFIFO_START_ADDR 0x0000001F +#define I2C_TXFIFO_START_ADDR_M ((I2C_TXFIFO_START_ADDR_V) << (I2C_TXFIFO_START_ADDR_S)) +#define I2C_TXFIFO_START_ADDR_V 0x1F +#define I2C_TXFIFO_START_ADDR_S 10 +/* I2C_RXFIFO_END_ADDR : RO ;bitpos:[9:5] ;default: 5'b0 ; */ +/*description: */ +#define I2C_RXFIFO_END_ADDR 0x0000001F +#define I2C_RXFIFO_END_ADDR_M ((I2C_RXFIFO_END_ADDR_V) << (I2C_RXFIFO_END_ADDR_S)) +#define I2C_RXFIFO_END_ADDR_V 0x1F +#define I2C_RXFIFO_END_ADDR_S 5 +/* I2C_RXFIFO_START_ADDR : RO ;bitpos:[4:0] ;default: 5'b0 ; */ +/*description: */ +#define I2C_RXFIFO_START_ADDR 0x0000001F +#define I2C_RXFIFO_START_ADDR_M ((I2C_RXFIFO_START_ADDR_V) << (I2C_RXFIFO_START_ADDR_S)) +#define I2C_RXFIFO_START_ADDR_V 0x1F +#define I2C_RXFIFO_START_ADDR_S 0 + +#define I2C_FIFO_CONF_REG(i) (REG_I2C_BASE(i) + 0x0018) +/* I2C_NONFIFO_TX_THRES : R/W ;bitpos:[25:20] ;default: 6'h15 ; */ +/*description: */ +#define I2C_NONFIFO_TX_THRES 0x0000003F +#define I2C_NONFIFO_TX_THRES_M ((I2C_NONFIFO_TX_THRES_V) << (I2C_NONFIFO_TX_THRES_S)) +#define I2C_NONFIFO_TX_THRES_V 0x3F +#define I2C_NONFIFO_TX_THRES_S 20 +/* I2C_NONFIFO_RX_THRES : R/W ;bitpos:[19:14] ;default: 6'h15 ; */ +/*description: */ +#define I2C_NONFIFO_RX_THRES 0x0000003F +#define I2C_NONFIFO_RX_THRES_M ((I2C_NONFIFO_RX_THRES_V) << (I2C_NONFIFO_RX_THRES_S)) +#define I2C_NONFIFO_RX_THRES_V 0x3F +#define I2C_NONFIFO_RX_THRES_S 14 +/* I2C_TX_FIFO_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TX_FIFO_RST (BIT(13)) +#define I2C_TX_FIFO_RST_M (BIT(13)) +#define I2C_TX_FIFO_RST_V 0x1 +#define I2C_TX_FIFO_RST_S 13 +/* I2C_RX_FIFO_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RX_FIFO_RST (BIT(12)) +#define I2C_RX_FIFO_RST_M (BIT(12)) +#define I2C_RX_FIFO_RST_V 0x1 +#define I2C_RX_FIFO_RST_S 12 +/* I2C_FIFO_ADDR_CFG_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2C_FIFO_ADDR_CFG_EN (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_M (BIT(11)) +#define I2C_FIFO_ADDR_CFG_EN_V 0x1 +#define I2C_FIFO_ADDR_CFG_EN_S 11 +/* I2C_NONFIFO_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2C_NONFIFO_EN (BIT(10)) +#define I2C_NONFIFO_EN_M (BIT(10)) +#define I2C_NONFIFO_EN_V 0x1 +#define I2C_NONFIFO_EN_S 10 +/* I2C_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[9:5] ;default: 5'h4 ; */ +/*description: */ +#define I2C_TXFIFO_EMPTY_THRHD 0x0000001F +#define I2C_TXFIFO_EMPTY_THRHD_M ((I2C_TXFIFO_EMPTY_THRHD_V) << (I2C_TXFIFO_EMPTY_THRHD_S)) +#define I2C_TXFIFO_EMPTY_THRHD_V 0x1F +#define I2C_TXFIFO_EMPTY_THRHD_S 5 +/* I2C_RXFIFO_FULL_THRHD : R/W ;bitpos:[4:0] ;default: 5'hb ; */ +/*description: */ +#define I2C_RXFIFO_FULL_THRHD 0x0000001F +#define I2C_RXFIFO_FULL_THRHD_M ((I2C_RXFIFO_FULL_THRHD_V) << (I2C_RXFIFO_FULL_THRHD_S)) +#define I2C_RXFIFO_FULL_THRHD_V 0x1F +#define I2C_RXFIFO_FULL_THRHD_S 0 + +#define I2C_DATA_APB_REG(i) (0x60013000 + (i)*0x14000 + 0x001c) + +#define I2C_DATA_REG(i) (REG_I2C_BASE(i) + 0x001c) +/* I2C_FIFO_RDATA : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define I2C_FIFO_RDATA 0x000000FF +#define I2C_FIFO_RDATA_M ((I2C_FIFO_RDATA_V) << (I2C_FIFO_RDATA_S)) +#define I2C_FIFO_RDATA_V 0xFF +#define I2C_FIFO_RDATA_S 0 + +#define I2C_INT_RAW_REG(i) (REG_I2C_BASE(i) + 0x0020) +/* I2C_DET_START_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2C_DET_START_INT_RAW (BIT(15)) +#define I2C_DET_START_INT_RAW_M (BIT(15)) +#define I2C_DET_START_INT_RAW_V 0x1 +#define I2C_DET_START_INT_RAW_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_MAIN_ST_TO_INT_RAW (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_RAW_S 14 +/* I2C_SCL_ST_TO_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_ST_TO_INT_RAW (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_RAW_V 0x1 +#define I2C_SCL_ST_TO_INT_RAW_S 13 +/* I2C_TX_SEND_EMPTY_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TX_SEND_EMPTY_INT_RAW (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_RAW_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_RAW_S 12 +/* I2C_RX_REC_FULL_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RX_REC_FULL_INT_RAW (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_RAW_V 0x1 +#define I2C_RX_REC_FULL_INT_RAW_S 11 +/* I2C_ACK_ERR_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ACK_ERR_INT_RAW (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_M (BIT(10)) +#define I2C_ACK_ERR_INT_RAW_V 0x1 +#define I2C_ACK_ERR_INT_RAW_S 10 +/* I2C_TRANS_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_START_INT_RAW (BIT(9)) +#define I2C_TRANS_START_INT_RAW_M (BIT(9)) +#define I2C_TRANS_START_INT_RAW_V 0x1 +#define I2C_TRANS_START_INT_RAW_S 9 +/* I2C_TIME_OUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TIME_OUT_INT_RAW (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_M (BIT(8)) +#define I2C_TIME_OUT_INT_RAW_V 0x1 +#define I2C_TIME_OUT_INT_RAW_S 8 +/* I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_COMPLETE_INT_RAW (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define I2C_TRANS_COMPLETE_INT_RAW_S 7 +/* I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2C_MASTER_TRAN_COMP_INT_RAW (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_RAW_S 6 +/* I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ARBITRATION_LOST_INT_RAW (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define I2C_ARBITRATION_LOST_INT_RAW_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_RAW_S 4 +/* I2C_END_DETECT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2C_END_DETECT_INT_RAW (BIT(3)) +#define I2C_END_DETECT_INT_RAW_M (BIT(3)) +#define I2C_END_DETECT_INT_RAW_V 0x1 +#define I2C_END_DETECT_INT_RAW_S 3 +/* I2C_RXFIFO_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_OVF_INT_RAW (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_RAW_V 0x1 +#define I2C_RXFIFO_OVF_INT_RAW_S 2 +/* I2C_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_RAW_S 1 +/* I2C_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_FULL_INT_RAW (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_RAW_V 0x1 +#define I2C_RXFIFO_FULL_INT_RAW_S 0 + +#define I2C_INT_CLR_REG(i) (REG_I2C_BASE(i) + 0x0024) +/* I2C_DET_START_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2C_DET_START_INT_CLR (BIT(15)) +#define I2C_DET_START_INT_CLR_M (BIT(15)) +#define I2C_DET_START_INT_CLR_V 0x1 +#define I2C_DET_START_INT_CLR_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_MAIN_ST_TO_INT_CLR (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_CLR_S 14 +/* I2C_SCL_ST_TO_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_ST_TO_INT_CLR (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_CLR_V 0x1 +#define I2C_SCL_ST_TO_INT_CLR_S 13 +/* I2C_TX_SEND_EMPTY_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TX_SEND_EMPTY_INT_CLR (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_CLR_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_CLR_S 12 +/* I2C_RX_REC_FULL_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RX_REC_FULL_INT_CLR (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_CLR_V 0x1 +#define I2C_RX_REC_FULL_INT_CLR_S 11 +/* I2C_ACK_ERR_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ACK_ERR_INT_CLR (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_M (BIT(10)) +#define I2C_ACK_ERR_INT_CLR_V 0x1 +#define I2C_ACK_ERR_INT_CLR_S 10 +/* I2C_TRANS_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_START_INT_CLR (BIT(9)) +#define I2C_TRANS_START_INT_CLR_M (BIT(9)) +#define I2C_TRANS_START_INT_CLR_V 0x1 +#define I2C_TRANS_START_INT_CLR_S 9 +/* I2C_TIME_OUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TIME_OUT_INT_CLR (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_M (BIT(8)) +#define I2C_TIME_OUT_INT_CLR_V 0x1 +#define I2C_TIME_OUT_INT_CLR_S 8 +/* I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_COMPLETE_INT_CLR (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define I2C_TRANS_COMPLETE_INT_CLR_S 7 +/* I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2C_MASTER_TRAN_COMP_INT_CLR (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_CLR_S 6 +/* I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ARBITRATION_LOST_INT_CLR (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define I2C_ARBITRATION_LOST_INT_CLR_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_CLR_S 4 +/* I2C_END_DETECT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2C_END_DETECT_INT_CLR (BIT(3)) +#define I2C_END_DETECT_INT_CLR_M (BIT(3)) +#define I2C_END_DETECT_INT_CLR_V 0x1 +#define I2C_END_DETECT_INT_CLR_S 3 +/* I2C_RXFIFO_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_OVF_INT_CLR (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_CLR_V 0x1 +#define I2C_RXFIFO_OVF_INT_CLR_S 2 +/* I2C_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_CLR_S 1 +/* I2C_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_FULL_INT_CLR (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_CLR_V 0x1 +#define I2C_RXFIFO_FULL_INT_CLR_S 0 + +#define I2C_INT_ENA_REG(i) (REG_I2C_BASE(i) + 0x0028) +/* I2C_DET_START_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2C_DET_START_INT_ENA (BIT(15)) +#define I2C_DET_START_INT_ENA_M (BIT(15)) +#define I2C_DET_START_INT_ENA_V 0x1 +#define I2C_DET_START_INT_ENA_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_MAIN_ST_TO_INT_ENA (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ENA_S 14 +/* I2C_SCL_ST_TO_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_ST_TO_INT_ENA (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ENA_V 0x1 +#define I2C_SCL_ST_TO_INT_ENA_S 13 +/* I2C_TX_SEND_EMPTY_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TX_SEND_EMPTY_INT_ENA (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ENA_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ENA_S 12 +/* I2C_RX_REC_FULL_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RX_REC_FULL_INT_ENA (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ENA_V 0x1 +#define I2C_RX_REC_FULL_INT_ENA_S 11 +/* I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ACK_ERR_INT_ENA (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_M (BIT(10)) +#define I2C_ACK_ERR_INT_ENA_V 0x1 +#define I2C_ACK_ERR_INT_ENA_S 10 +/* I2C_TRANS_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_START_INT_ENA (BIT(9)) +#define I2C_TRANS_START_INT_ENA_M (BIT(9)) +#define I2C_TRANS_START_INT_ENA_V 0x1 +#define I2C_TRANS_START_INT_ENA_S 9 +/* I2C_TIME_OUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TIME_OUT_INT_ENA (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_M (BIT(8)) +#define I2C_TIME_OUT_INT_ENA_V 0x1 +#define I2C_TIME_OUT_INT_ENA_S 8 +/* I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_COMPLETE_INT_ENA (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ENA_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2C_MASTER_TRAN_COMP_INT_ENA (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ENA_S 6 +/* I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ARBITRATION_LOST_INT_ENA (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ENA_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ENA_S 4 +/* I2C_END_DETECT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2C_END_DETECT_INT_ENA (BIT(3)) +#define I2C_END_DETECT_INT_ENA_M (BIT(3)) +#define I2C_END_DETECT_INT_ENA_V 0x1 +#define I2C_END_DETECT_INT_ENA_S 3 +/* I2C_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_OVF_INT_ENA (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ENA_V 0x1 +#define I2C_RXFIFO_OVF_INT_ENA_S 2 +/* I2C_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ENA_S 1 +/* I2C_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_FULL_INT_ENA (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ENA_V 0x1 +#define I2C_RXFIFO_FULL_INT_ENA_S 0 + +#define I2C_INT_STATUS_REG(i) (REG_I2C_BASE(i) + 0x002c) +/* I2C_DET_START_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define I2C_DET_START_INT_ST (BIT(15)) +#define I2C_DET_START_INT_ST_M (BIT(15)) +#define I2C_DET_START_INT_ST_V 0x1 +#define I2C_DET_START_INT_ST_S 15 +/* I2C_SCL_MAIN_ST_TO_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_MAIN_ST_TO_INT_ST (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_M (BIT(14)) +#define I2C_SCL_MAIN_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_MAIN_ST_TO_INT_ST_S 14 +/* I2C_SCL_ST_TO_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_ST_TO_INT_ST (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_M (BIT(13)) +#define I2C_SCL_ST_TO_INT_ST_V 0x1 +#define I2C_SCL_ST_TO_INT_ST_S 13 +/* I2C_TX_SEND_EMPTY_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TX_SEND_EMPTY_INT_ST (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_M (BIT(12)) +#define I2C_TX_SEND_EMPTY_INT_ST_V 0x1 +#define I2C_TX_SEND_EMPTY_INT_ST_S 12 +/* I2C_RX_REC_FULL_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RX_REC_FULL_INT_ST (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_M (BIT(11)) +#define I2C_RX_REC_FULL_INT_ST_V 0x1 +#define I2C_RX_REC_FULL_INT_ST_S 11 +/* I2C_ACK_ERR_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ACK_ERR_INT_ST (BIT(10)) +#define I2C_ACK_ERR_INT_ST_M (BIT(10)) +#define I2C_ACK_ERR_INT_ST_V 0x1 +#define I2C_ACK_ERR_INT_ST_S 10 +/* I2C_TRANS_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_START_INT_ST (BIT(9)) +#define I2C_TRANS_START_INT_ST_M (BIT(9)) +#define I2C_TRANS_START_INT_ST_V 0x1 +#define I2C_TRANS_START_INT_ST_S 9 +/* I2C_TIME_OUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TIME_OUT_INT_ST (BIT(8)) +#define I2C_TIME_OUT_INT_ST_M (BIT(8)) +#define I2C_TIME_OUT_INT_ST_V 0x1 +#define I2C_TIME_OUT_INT_ST_S 8 +/* I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TRANS_COMPLETE_INT_ST (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_M (BIT(7)) +#define I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define I2C_TRANS_COMPLETE_INT_ST_S 7 +/* I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2C_MASTER_TRAN_COMP_INT_ST (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(6)) +#define I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define I2C_MASTER_TRAN_COMP_INT_ST_S 6 +/* I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define I2C_ARBITRATION_LOST_INT_ST (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_M (BIT(5)) +#define I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define I2C_ARBITRATION_LOST_INT_ST_S 5 +/* I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SLAVE_TRAN_COMP_INT_ST (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(4)) +#define I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define I2C_SLAVE_TRAN_COMP_INT_ST_S 4 +/* I2C_END_DETECT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define I2C_END_DETECT_INT_ST (BIT(3)) +#define I2C_END_DETECT_INT_ST_M (BIT(3)) +#define I2C_END_DETECT_INT_ST_V 0x1 +#define I2C_END_DETECT_INT_ST_S 3 +/* I2C_RXFIFO_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_OVF_INT_ST (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_M (BIT(2)) +#define I2C_RXFIFO_OVF_INT_ST_V 0x1 +#define I2C_RXFIFO_OVF_INT_ST_S 2 +/* I2C_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define I2C_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define I2C_TXFIFO_EMPTY_INT_ST_V 0x1 +#define I2C_TXFIFO_EMPTY_INT_ST_S 1 +/* I2C_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2C_RXFIFO_FULL_INT_ST (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define I2C_RXFIFO_FULL_INT_ST_V 0x1 +#define I2C_RXFIFO_FULL_INT_ST_S 0 + +#define I2C_SDA_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0030) +/* I2C_SDA_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define I2C_SDA_HOLD_TIME 0x000003FF +#define I2C_SDA_HOLD_TIME_M ((I2C_SDA_HOLD_TIME_V) << (I2C_SDA_HOLD_TIME_S)) +#define I2C_SDA_HOLD_TIME_V 0x3FF +#define I2C_SDA_HOLD_TIME_S 0 + +#define I2C_SDA_SAMPLE_REG(i) (REG_I2C_BASE(i) + 0x0034) +/* I2C_SDA_SAMPLE_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define I2C_SDA_SAMPLE_TIME 0x000003FF +#define I2C_SDA_SAMPLE_TIME_M ((I2C_SDA_SAMPLE_TIME_V) << (I2C_SDA_SAMPLE_TIME_S)) +#define I2C_SDA_SAMPLE_TIME_V 0x3FF +#define I2C_SDA_SAMPLE_TIME_S 0 + +#define I2C_SCL_HIGH_PERIOD_REG(i) (REG_I2C_BASE(i) + 0x0038) +/* I2C_SCL_WAIT_HIGH_PERIOD : R/W ;bitpos:[27:14] ;default: 14'b0 ; */ +/*description: */ +#define I2C_SCL_WAIT_HIGH_PERIOD 0x00003FFF +#define I2C_SCL_WAIT_HIGH_PERIOD_M ((I2C_SCL_WAIT_HIGH_PERIOD_V) << (I2C_SCL_WAIT_HIGH_PERIOD_S)) +#define I2C_SCL_WAIT_HIGH_PERIOD_V 0x3FFF +#define I2C_SCL_WAIT_HIGH_PERIOD_S 14 +/* I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_SCL_HIGH_PERIOD 0x00003FFF +#define I2C_SCL_HIGH_PERIOD_M ((I2C_SCL_HIGH_PERIOD_V) << (I2C_SCL_HIGH_PERIOD_S)) +#define I2C_SCL_HIGH_PERIOD_V 0x3FFF +#define I2C_SCL_HIGH_PERIOD_S 0 + +#define I2C_SCL_START_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0040) +/* I2C_SCL_START_HOLD_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: */ +#define I2C_SCL_START_HOLD_TIME 0x000003FF +#define I2C_SCL_START_HOLD_TIME_M ((I2C_SCL_START_HOLD_TIME_V) << (I2C_SCL_START_HOLD_TIME_S)) +#define I2C_SCL_START_HOLD_TIME_V 0x3FF +#define I2C_SCL_START_HOLD_TIME_S 0 + +#define I2C_SCL_RSTART_SETUP_REG(i) (REG_I2C_BASE(i) + 0x0044) +/* I2C_SCL_RSTART_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b1000 ; */ +/*description: */ +#define I2C_SCL_RSTART_SETUP_TIME 0x000003FF +#define I2C_SCL_RSTART_SETUP_TIME_M ((I2C_SCL_RSTART_SETUP_TIME_V) << (I2C_SCL_RSTART_SETUP_TIME_S)) +#define I2C_SCL_RSTART_SETUP_TIME_V 0x3FF +#define I2C_SCL_RSTART_SETUP_TIME_S 0 + +#define I2C_SCL_STOP_HOLD_REG(i) (REG_I2C_BASE(i) + 0x0048) +/* I2C_SCL_STOP_HOLD_TIME : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_SCL_STOP_HOLD_TIME 0x00003FFF +#define I2C_SCL_STOP_HOLD_TIME_M ((I2C_SCL_STOP_HOLD_TIME_V) << (I2C_SCL_STOP_HOLD_TIME_S)) +#define I2C_SCL_STOP_HOLD_TIME_V 0x3FFF +#define I2C_SCL_STOP_HOLD_TIME_S 0 + +#define I2C_SCL_STOP_SETUP_REG(i) (REG_I2C_BASE(i) + 0x004C) +/* I2C_SCL_STOP_SETUP_TIME : R/W ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define I2C_SCL_STOP_SETUP_TIME 0x000003FF +#define I2C_SCL_STOP_SETUP_TIME_M ((I2C_SCL_STOP_SETUP_TIME_V) << (I2C_SCL_STOP_SETUP_TIME_S)) +#define I2C_SCL_STOP_SETUP_TIME_V 0x3FF +#define I2C_SCL_STOP_SETUP_TIME_S 0 + +#define I2C_SCL_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0050) +/* I2C_SCL_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define I2C_SCL_FILTER_EN (BIT(3)) +#define I2C_SCL_FILTER_EN_M (BIT(3)) +#define I2C_SCL_FILTER_EN_V 0x1 +#define I2C_SCL_FILTER_EN_S 3 +/* I2C_SCL_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define I2C_SCL_FILTER_THRES 0x00000007 +#define I2C_SCL_FILTER_THRES_M ((I2C_SCL_FILTER_THRES_V) << (I2C_SCL_FILTER_THRES_S)) +#define I2C_SCL_FILTER_THRES_V 0x7 +#define I2C_SCL_FILTER_THRES_S 0 + +#define I2C_SDA_FILTER_CFG_REG(i) (REG_I2C_BASE(i) + 0x0054) +/* I2C_SDA_FILTER_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define I2C_SDA_FILTER_EN (BIT(3)) +#define I2C_SDA_FILTER_EN_M (BIT(3)) +#define I2C_SDA_FILTER_EN_V 0x1 +#define I2C_SDA_FILTER_EN_S 3 +/* I2C_SDA_FILTER_THRES : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define I2C_SDA_FILTER_THRES 0x00000007 +#define I2C_SDA_FILTER_THRES_M ((I2C_SDA_FILTER_THRES_V) << (I2C_SDA_FILTER_THRES_S)) +#define I2C_SDA_FILTER_THRES_V 0x7 +#define I2C_SDA_FILTER_THRES_S 0 + +#define I2C_COMD0_REG(i) (REG_I2C_BASE(i) + 0x0058) +/* I2C_COMMAND0_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND0_DONE (BIT(31)) +#define I2C_COMMAND0_DONE_M (BIT(31)) +#define I2C_COMMAND0_DONE_V 0x1 +#define I2C_COMMAND0_DONE_S 31 +/* I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND0 0x00003FFF +#define I2C_COMMAND0_M ((I2C_COMMAND0_V) << (I2C_COMMAND0_S)) +#define I2C_COMMAND0_V 0x3FFF +#define I2C_COMMAND0_S 0 + +#define I2C_COMD1_REG(i) (REG_I2C_BASE(i) + 0x005C) +/* I2C_COMMAND1_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND1_DONE (BIT(31)) +#define I2C_COMMAND1_DONE_M (BIT(31)) +#define I2C_COMMAND1_DONE_V 0x1 +#define I2C_COMMAND1_DONE_S 31 +/* I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND1 0x00003FFF +#define I2C_COMMAND1_M ((I2C_COMMAND1_V) << (I2C_COMMAND1_S)) +#define I2C_COMMAND1_V 0x3FFF +#define I2C_COMMAND1_S 0 + +#define I2C_COMD2_REG(i) (REG_I2C_BASE(i) + 0x0060) +/* I2C_COMMAND2_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND2_DONE (BIT(31)) +#define I2C_COMMAND2_DONE_M (BIT(31)) +#define I2C_COMMAND2_DONE_V 0x1 +#define I2C_COMMAND2_DONE_S 31 +/* I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND2 0x00003FFF +#define I2C_COMMAND2_M ((I2C_COMMAND2_V) << (I2C_COMMAND2_S)) +#define I2C_COMMAND2_V 0x3FFF +#define I2C_COMMAND2_S 0 + +#define I2C_COMD3_REG(i) (REG_I2C_BASE(i) + 0x0064) +/* I2C_COMMAND3_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND3_DONE (BIT(31)) +#define I2C_COMMAND3_DONE_M (BIT(31)) +#define I2C_COMMAND3_DONE_V 0x1 +#define I2C_COMMAND3_DONE_S 31 +/* I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND3 0x00003FFF +#define I2C_COMMAND3_M ((I2C_COMMAND3_V) << (I2C_COMMAND3_S)) +#define I2C_COMMAND3_V 0x3FFF +#define I2C_COMMAND3_S 0 + +#define I2C_COMD4_REG(i) (REG_I2C_BASE(i) + 0x0068) +/* I2C_COMMAND4_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND4_DONE (BIT(31)) +#define I2C_COMMAND4_DONE_M (BIT(31)) +#define I2C_COMMAND4_DONE_V 0x1 +#define I2C_COMMAND4_DONE_S 31 +/* I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND4 0x00003FFF +#define I2C_COMMAND4_M ((I2C_COMMAND4_V) << (I2C_COMMAND4_S)) +#define I2C_COMMAND4_V 0x3FFF +#define I2C_COMMAND4_S 0 + +#define I2C_COMD5_REG(i) (REG_I2C_BASE(i) + 0x006C) +/* I2C_COMMAND5_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND5_DONE (BIT(31)) +#define I2C_COMMAND5_DONE_M (BIT(31)) +#define I2C_COMMAND5_DONE_V 0x1 +#define I2C_COMMAND5_DONE_S 31 +/* I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND5 0x00003FFF +#define I2C_COMMAND5_M ((I2C_COMMAND5_V) << (I2C_COMMAND5_S)) +#define I2C_COMMAND5_V 0x3FFF +#define I2C_COMMAND5_S 0 + +#define I2C_COMD6_REG(i) (REG_I2C_BASE(i) + 0x0070) +/* I2C_COMMAND6_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND6_DONE (BIT(31)) +#define I2C_COMMAND6_DONE_M (BIT(31)) +#define I2C_COMMAND6_DONE_V 0x1 +#define I2C_COMMAND6_DONE_S 31 +/* I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND6 0x00003FFF +#define I2C_COMMAND6_M ((I2C_COMMAND6_V) << (I2C_COMMAND6_S)) +#define I2C_COMMAND6_V 0x3FFF +#define I2C_COMMAND6_S 0 + +#define I2C_COMD7_REG(i) (REG_I2C_BASE(i) + 0x0074) +/* I2C_COMMAND7_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND7_DONE (BIT(31)) +#define I2C_COMMAND7_DONE_M (BIT(31)) +#define I2C_COMMAND7_DONE_V 0x1 +#define I2C_COMMAND7_DONE_S 31 +/* I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND7 0x00003FFF +#define I2C_COMMAND7_M ((I2C_COMMAND7_V) << (I2C_COMMAND7_S)) +#define I2C_COMMAND7_V 0x3FFF +#define I2C_COMMAND7_S 0 + +#define I2C_COMD8_REG(i) (REG_I2C_BASE(i) + 0x0078) +/* I2C_COMMAND8_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND8_DONE (BIT(31)) +#define I2C_COMMAND8_DONE_M (BIT(31)) +#define I2C_COMMAND8_DONE_V 0x1 +#define I2C_COMMAND8_DONE_S 31 +/* I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND8 0x00003FFF +#define I2C_COMMAND8_M ((I2C_COMMAND8_V) << (I2C_COMMAND8_S)) +#define I2C_COMMAND8_V 0x3FFF +#define I2C_COMMAND8_S 0 + +#define I2C_COMD9_REG(i) (REG_I2C_BASE(i) + 0x007C) +/* I2C_COMMAND9_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND9_DONE (BIT(31)) +#define I2C_COMMAND9_DONE_M (BIT(31)) +#define I2C_COMMAND9_DONE_V 0x1 +#define I2C_COMMAND9_DONE_S 31 +/* I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND9 0x00003FFF +#define I2C_COMMAND9_M ((I2C_COMMAND9_V) << (I2C_COMMAND9_S)) +#define I2C_COMMAND9_V 0x3FFF +#define I2C_COMMAND9_S 0 + +#define I2C_COMD10_REG(i) (REG_I2C_BASE(i) + 0x0080) +/* I2C_COMMAND10_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND10_DONE (BIT(31)) +#define I2C_COMMAND10_DONE_M (BIT(31)) +#define I2C_COMMAND10_DONE_V 0x1 +#define I2C_COMMAND10_DONE_S 31 +/* I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND10 0x00003FFF +#define I2C_COMMAND10_M ((I2C_COMMAND10_V) << (I2C_COMMAND10_S)) +#define I2C_COMMAND10_V 0x3FFF +#define I2C_COMMAND10_S 0 + +#define I2C_COMD11_REG(i) (REG_I2C_BASE(i) + 0x0084) +/* I2C_COMMAND11_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND11_DONE (BIT(31)) +#define I2C_COMMAND11_DONE_M (BIT(31)) +#define I2C_COMMAND11_DONE_V 0x1 +#define I2C_COMMAND11_DONE_S 31 +/* I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND11 0x00003FFF +#define I2C_COMMAND11_M ((I2C_COMMAND11_V) << (I2C_COMMAND11_S)) +#define I2C_COMMAND11_V 0x3FFF +#define I2C_COMMAND11_S 0 + +#define I2C_COMD12_REG(i) (REG_I2C_BASE(i) + 0x0088) +/* I2C_COMMAND12_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND12_DONE (BIT(31)) +#define I2C_COMMAND12_DONE_M (BIT(31)) +#define I2C_COMMAND12_DONE_V 0x1 +#define I2C_COMMAND12_DONE_S 31 +/* I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND12 0x00003FFF +#define I2C_COMMAND12_M ((I2C_COMMAND12_V) << (I2C_COMMAND12_S)) +#define I2C_COMMAND12_V 0x3FFF +#define I2C_COMMAND12_S 0 + +#define I2C_COMD13_REG(i) (REG_I2C_BASE(i) + 0x008C) +/* I2C_COMMAND13_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND13_DONE (BIT(31)) +#define I2C_COMMAND13_DONE_M (BIT(31)) +#define I2C_COMMAND13_DONE_V 0x1 +#define I2C_COMMAND13_DONE_S 31 +/* I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND13 0x00003FFF +#define I2C_COMMAND13_M ((I2C_COMMAND13_V) << (I2C_COMMAND13_S)) +#define I2C_COMMAND13_V 0x3FFF +#define I2C_COMMAND13_S 0 + +#define I2C_COMD14_REG(i) (REG_I2C_BASE(i) + 0x0090) +/* I2C_COMMAND14_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND14_DONE (BIT(31)) +#define I2C_COMMAND14_DONE_M (BIT(31)) +#define I2C_COMMAND14_DONE_V 0x1 +#define I2C_COMMAND14_DONE_S 31 +/* I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND14 0x00003FFF +#define I2C_COMMAND14_M ((I2C_COMMAND14_V) << (I2C_COMMAND14_S)) +#define I2C_COMMAND14_V 0x3FFF +#define I2C_COMMAND14_S 0 + +#define I2C_COMD15_REG(i) (REG_I2C_BASE(i) + 0x0094) +/* I2C_COMMAND15_DONE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define I2C_COMMAND15_DONE (BIT(31)) +#define I2C_COMMAND15_DONE_M (BIT(31)) +#define I2C_COMMAND15_DONE_V 0x1 +#define I2C_COMMAND15_DONE_S 31 +/* I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define I2C_COMMAND15 0x00003FFF +#define I2C_COMMAND15_M ((I2C_COMMAND15_V) << (I2C_COMMAND15_S)) +#define I2C_COMMAND15_V 0x3FFF +#define I2C_COMMAND15_S 0 + +#define I2C_SCL_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x0098) +/* I2C_SCL_ST_TO_REG : R/W ;bitpos:[23:0] ;default: 24'h100 ; */ +/*description: */ +#define I2C_SCL_ST_TO_REG 0x00FFFFFF +#define I2C_SCL_ST_TO_REG_M ((I2C_SCL_ST_TO_REG_V) << (I2C_SCL_ST_TO_REG_S)) +#define I2C_SCL_ST_TO_REG_V 0xFFFFFF +#define I2C_SCL_ST_TO_REG_S 0 + +#define I2C_SCL_MAIN_ST_TIME_OUT_REG(i) (REG_I2C_BASE(i) + 0x009c) +/* I2C_SCL_MAIN_ST_TO_REG : R/W ;bitpos:[23:0] ;default: 24'h100 ; */ +/*description: */ +#define I2C_SCL_MAIN_ST_TO_REG 0x00FFFFFF +#define I2C_SCL_MAIN_ST_TO_REG_M ((I2C_SCL_MAIN_ST_TO_REG_V) << (I2C_SCL_MAIN_ST_TO_REG_S)) +#define I2C_SCL_MAIN_ST_TO_REG_V 0xFFFFFF +#define I2C_SCL_MAIN_ST_TO_REG_S 0 + +#define I2C_SCL_SP_CONF_REG(i) (REG_I2C_BASE(i) + 0x00a0) +/* I2C_SDA_PD_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SDA_PD_EN (BIT(7)) +#define I2C_SDA_PD_EN_M (BIT(7)) +#define I2C_SDA_PD_EN_V 0x1 +#define I2C_SDA_PD_EN_S 7 +/* I2C_SCL_PD_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_PD_EN (BIT(6)) +#define I2C_SCL_PD_EN_M (BIT(6)) +#define I2C_SCL_PD_EN_V 0x1 +#define I2C_SCL_PD_EN_S 6 +/* I2C_SCL_RST_SLV_NUM : R/W ;bitpos:[5:1] ;default: 5'b0 ; */ +/*description: */ +#define I2C_SCL_RST_SLV_NUM 0x0000001F +#define I2C_SCL_RST_SLV_NUM_M ((I2C_SCL_RST_SLV_NUM_V) << (I2C_SCL_RST_SLV_NUM_S)) +#define I2C_SCL_RST_SLV_NUM_V 0x1F +#define I2C_SCL_RST_SLV_NUM_S 1 +/* I2C_SCL_RST_SLV_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define I2C_SCL_RST_SLV_EN (BIT(0)) +#define I2C_SCL_RST_SLV_EN_M (BIT(0)) +#define I2C_SCL_RST_SLV_EN_V 0x1 +#define I2C_SCL_RST_SLV_EN_S 0 + +#define I2C_DATE_REG(i) (REG_I2C_BASE(i) + 0x00F8) +/* I2C_DATE : R/W ;bitpos:[31:0] ;default: 32'h18073100 ; */ +/*description: */ +#define I2C_DATE 0xFFFFFFFF +#define I2C_DATE_M ((I2C_DATE_V) << (I2C_DATE_S)) +#define I2C_DATE_V 0xFFFFFFFF +#define I2C_DATE_S 0 + +#define I2C_FIFO_START_ADDR_REG(i) (REG_I2C_BASE(i) + 0x0100) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/i2c_struct.h b/components/soc/soc/esp32s3/include/soc/i2c_struct.h new file mode 100644 index 000000000..1fb5bcd6d --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/i2c_struct.h @@ -0,0 +1,340 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t period: 14; + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_low_period; + union { + struct { + uint32_t sda_force_out: 1; + uint32_t scl_force_out: 1; + uint32_t sample_scl_level: 1; + uint32_t ack_level: 1; + uint32_t ms_mode: 1; + uint32_t trans_start: 1; + uint32_t tx_lsb_first: 1; + uint32_t rx_lsb_first: 1; + uint32_t clk_en: 1; + uint32_t arbitration_en: 1; + uint32_t fsm_rst: 1; + uint32_t ref_always_on: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } ctr; + union { + struct { + uint32_t ack_rec: 1; + uint32_t slave_rw: 1; + uint32_t time_out: 1; + uint32_t arb_lost: 1; + uint32_t bus_busy: 1; + uint32_t slave_addressed: 1; + uint32_t byte_trans: 1; + uint32_t reserved7: 1; + uint32_t rx_fifo_cnt: 6; + uint32_t reserved14: 4; + uint32_t tx_fifo_cnt: 6; + uint32_t scl_main_state_last: 3; + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; + uint32_t reserved31: 1; + }; + uint32_t val; + } status_reg; + union { + struct { + uint32_t tout: 24; + uint32_t time_out_en: 1; + uint32_t reserved25: 7; + }; + uint32_t val; + } timeout; + union { + struct { + uint32_t addr: 15; + uint32_t reserved15: 16; + uint32_t en_10bit: 1; + }; + uint32_t val; + } slave_addr; + union { + struct { + uint32_t rx_fifo_start_addr: 5; + uint32_t rx_fifo_end_addr: 5; + uint32_t tx_fifo_start_addr: 5; + uint32_t tx_fifo_end_addr: 5; + uint32_t rx_update: 1; + uint32_t tx_update: 1; + uint32_t tx_fifo_init_raddr: 5; + uint32_t rx_fifo_init_waddr: 5; + }; + uint32_t val; + } fifo_st; + union { + struct { + uint32_t rx_fifo_full_thrhd: 5; + uint32_t tx_fifo_empty_thrhd: 5; + uint32_t nonfifo_en: 1; + uint32_t fifo_addr_cfg_en: 1; + uint32_t rx_fifo_rst: 1; + uint32_t tx_fifo_rst: 1; + uint32_t nonfifo_rx_thres: 6; + uint32_t nonfifo_tx_thres: 6; + uint32_t reserved26: 6; + }; + uint32_t val; + } fifo_conf; + union { + struct { + uint8_t data; + uint8_t reserved[3]; + }; + uint32_t val; + } fifo_data; + union { + struct { + uint32_t rx_fifo_full: 1; + uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_ovf: 1; + uint32_t end_detect: 1; + uint32_t slave_tran_comp: 1; + uint32_t arbitration_lost: 1; + uint32_t master_tran_comp: 1; + uint32_t trans_complete: 1; + uint32_t time_out: 1; + uint32_t trans_start: 1; + uint32_t ack_err: 1; + uint32_t rx_rec_full: 1; + uint32_t tx_send_empty: 1; + uint32_t scl_st_to: 1; + uint32_t scl_main_st_to: 1; + uint32_t det_start: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_fifo_full: 1; + uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_ovf: 1; + uint32_t end_detect: 1; + uint32_t slave_tran_comp: 1; + uint32_t arbitration_lost: 1; + uint32_t master_tran_comp: 1; + uint32_t trans_complete: 1; + uint32_t time_out: 1; + uint32_t trans_start: 1; + uint32_t ack_err: 1; + uint32_t rx_rec_full: 1; + uint32_t tx_send_empty: 1; + uint32_t scl_st_to: 1; + uint32_t scl_main_st_to: 1; + uint32_t det_start: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t rx_fifo_full: 1; + uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_ovf: 1; + uint32_t end_detect: 1; + uint32_t slave_tran_comp: 1; + uint32_t arbitration_lost: 1; + uint32_t master_tran_comp: 1; + uint32_t trans_complete: 1; + uint32_t time_out: 1; + uint32_t trans_start: 1; + uint32_t ack_err: 1; + uint32_t rx_rec_full: 1; + uint32_t tx_send_empty: 1; + uint32_t scl_st_to: 1; + uint32_t scl_main_st_to: 1; + uint32_t det_start: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_fifo_full: 1; + uint32_t tx_fifo_empty: 1; + uint32_t rx_fifo_ovf: 1; + uint32_t end_detect: 1; + uint32_t slave_tran_comp: 1; + uint32_t arbitration_lost: 1; + uint32_t master_tran_comp: 1; + uint32_t trans_complete: 1; + uint32_t time_out: 1; + uint32_t trans_start: 1; + uint32_t ack_err: 1; + uint32_t rx_rec_full: 1; + uint32_t tx_send_empty: 1; + uint32_t scl_st_to: 1; + uint32_t scl_main_st_to: 1; + uint32_t det_start: 1; + uint32_t reserved16: 16; + }; + uint32_t val; + } int_status; + union { + struct { + uint32_t time: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } sda_hold; + union { + struct { + uint32_t time: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } sda_sample; + union { + struct { + uint32_t period: 14; + uint32_t scl_wait_high_period: 14; + uint32_t reserved28: 4; + }; + uint32_t val; + } scl_high_period; + uint32_t reserved_3c; + union { + struct { + uint32_t time: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_start_hold; + union { + struct { + uint32_t time: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_rstart_setup; + union { + struct { + uint32_t time: 14; + uint32_t reserved14: 18; + }; + uint32_t val; + } scl_stop_hold; + union { + struct { + uint32_t time: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } scl_stop_setup; + union { + struct { + uint32_t thres: 3; + uint32_t en: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } scl_filter_cfg; + union { + struct { + uint32_t thres: 3; + uint32_t en: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } sda_filter_cfg; + union { + struct { + uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/ + uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/ + uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/ + uint32_t reserved14: 17; + uint32_t done: 1; + }; + uint32_t val; + } command[16]; + union { + struct { + uint32_t scl_st_to: 24; + uint32_t reserved24: 8; + }; + uint32_t val; + } scl_st_time_out; + union { + struct { + uint32_t scl_main_st_to: 24; + uint32_t reserved24: 8; + }; + uint32_t val; + } scl_main_st_time_out; + union { + struct { + uint32_t scl_rst_slv_en: 1; + uint32_t scl_rst_slv_num: 5; + uint32_t scl_pd_en: 1; + uint32_t sda_pd_en: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } scl_sp_conf; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t date; /**/ + uint32_t reserved_fc; + uint32_t ram_data[32]; /**/ +} i2c_dev_t; + +extern i2c_dev_t I2C0; +extern i2c_dev_t I2C1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/i2s_caps.h b/components/soc/soc/esp32s3/include/soc/i2s_caps.h new file mode 100644 index 000000000..bce5c0253 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/i2s_caps.h @@ -0,0 +1,28 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define APLL_MIN_FREQ (250000000) +#define APLL_MAX_FREQ (500000000) +#define APLL_I2S_MIN_RATE (10675) //in Hz, I2S Clock rate limited by hardware +#define I2S_AD_BCK_FACTOR (2) +#define I2S_PDM_BCK_FACTOR (64) +#define I2S_MAX_BUFFER_SIZE (4 * 1024 * 1024) //the maximum RAM can be allocated +#define I2S_BASE_CLK (2*APB_CLK_FREQ) + +// ESP32-S3 have 1 I2S +#define SOC_I2S_NUM (1) + +#define SOC_I2S_SUPPORT_PDM (0) // ESP32-S3 do not support PDM diff --git a/components/soc/soc/esp32s3/include/soc/i2s_reg.h b/components/soc/soc/esp32s3/include/soc/i2s_reg.h new file mode 100644 index 000000000..8b1240f10 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/i2s_reg.h @@ -0,0 +1,971 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define I2S_INT_RAW_REG(i) (REG_I2S_BASE(i) + 0x000c) +/* I2S_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_RAW (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_M (BIT(3)) +#define I2S_TX_HUNG_INT_RAW_V 0x1 +#define I2S_TX_HUNG_INT_RAW_S 3 +/* I2S_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_RAW (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_M (BIT(2)) +#define I2S_RX_HUNG_INT_RAW_V 0x1 +#define I2S_RX_HUNG_INT_RAW_S 2 +/* I2S_TX_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_RAW (BIT(1)) +#define I2S_TX_DONE_INT_RAW_M (BIT(1)) +#define I2S_TX_DONE_INT_RAW_V 0x1 +#define I2S_TX_DONE_INT_RAW_S 1 +/* I2S_RX_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw interrupt status bit for the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_RAW (BIT(0)) +#define I2S_RX_DONE_INT_RAW_M (BIT(0)) +#define I2S_RX_DONE_INT_RAW_V 0x1 +#define I2S_RX_DONE_INT_RAW_S 0 + +#define I2S_INT_ST_REG(i) (REG_I2S_BASE(i) + 0x0010) +/* I2S_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_ST (BIT(3)) +#define I2S_TX_HUNG_INT_ST_M (BIT(3)) +#define I2S_TX_HUNG_INT_ST_V 0x1 +#define I2S_TX_HUNG_INT_ST_S 3 +/* I2S_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_ST (BIT(2)) +#define I2S_RX_HUNG_INT_ST_M (BIT(2)) +#define I2S_RX_HUNG_INT_ST_V 0x1 +#define I2S_RX_HUNG_INT_ST_S 2 +/* I2S_TX_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_ST (BIT(1)) +#define I2S_TX_DONE_INT_ST_M (BIT(1)) +#define I2S_TX_DONE_INT_ST_V 0x1 +#define I2S_TX_DONE_INT_ST_S 1 +/* I2S_RX_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The masked interrupt status bit for the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_ST (BIT(0)) +#define I2S_RX_DONE_INT_ST_M (BIT(0)) +#define I2S_RX_DONE_INT_ST_V 0x1 +#define I2S_RX_DONE_INT_ST_S 0 + +#define I2S_INT_ENA_REG(i) (REG_I2S_BASE(i) + 0x0014) +/* I2S_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_ENA (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_M (BIT(3)) +#define I2S_TX_HUNG_INT_ENA_V 0x1 +#define I2S_TX_HUNG_INT_ENA_S 3 +/* I2S_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_ENA (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_M (BIT(2)) +#define I2S_RX_HUNG_INT_ENA_V 0x1 +#define I2S_RX_HUNG_INT_ENA_S 2 +/* I2S_TX_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_ENA (BIT(1)) +#define I2S_TX_DONE_INT_ENA_M (BIT(1)) +#define I2S_TX_DONE_INT_ENA_V 0x1 +#define I2S_TX_DONE_INT_ENA_S 1 +/* I2S_RX_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The interrupt enable bit for the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_ENA (BIT(0)) +#define I2S_RX_DONE_INT_ENA_M (BIT(0)) +#define I2S_RX_DONE_INT_ENA_V 0x1 +#define I2S_RX_DONE_INT_ENA_S 0 + +#define I2S_INT_CLR_REG(i) (REG_I2S_BASE(i) + 0x0018) +/* I2S_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_tx_hung_int interrupt*/ +#define I2S_TX_HUNG_INT_CLR (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_M (BIT(3)) +#define I2S_TX_HUNG_INT_CLR_V 0x1 +#define I2S_TX_HUNG_INT_CLR_S 3 +/* I2S_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_rx_hung_int interrupt*/ +#define I2S_RX_HUNG_INT_CLR (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_M (BIT(2)) +#define I2S_RX_HUNG_INT_CLR_V 0x1 +#define I2S_RX_HUNG_INT_CLR_S 2 +/* I2S_TX_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_tx_done_int interrupt*/ +#define I2S_TX_DONE_INT_CLR (BIT(1)) +#define I2S_TX_DONE_INT_CLR_M (BIT(1)) +#define I2S_TX_DONE_INT_CLR_V 0x1 +#define I2S_TX_DONE_INT_CLR_S 1 +/* I2S_RX_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to clear the i2s_rx_done_int interrupt*/ +#define I2S_RX_DONE_INT_CLR (BIT(0)) +#define I2S_RX_DONE_INT_CLR_M (BIT(0)) +#define I2S_RX_DONE_INT_CLR_V 0x1 +#define I2S_RX_DONE_INT_CLR_S 0 + +#define I2S_RX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0020) +/* I2S_RX_PDM_SINC_DSR_16_EN : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: */ +#define I2S_RX_PDM_SINC_DSR_16_EN (BIT(22)) +#define I2S_RX_PDM_SINC_DSR_16_EN_M (BIT(22)) +#define I2S_RX_PDM_SINC_DSR_16_EN_V 0x1 +#define I2S_RX_PDM_SINC_DSR_16_EN_S 22 +/* I2S_RX_PDM2PCM_EN : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: 1: Enable PDM2PCM RX mode. 0: DIsable.*/ +#define I2S_RX_PDM2PCM_EN (BIT(21)) +#define I2S_RX_PDM2PCM_EN_M (BIT(21)) +#define I2S_RX_PDM2PCM_EN_V 0x1 +#define I2S_RX_PDM2PCM_EN_S 21 +/* I2S_RX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: 1: Enable I2S PDM Rx mode . 0: Disable.*/ +#define I2S_RX_PDM_EN (BIT(20)) +#define I2S_RX_PDM_EN_M (BIT(20)) +#define I2S_RX_PDM_EN_V 0x1 +#define I2S_RX_PDM_EN_S 20 +/* I2S_RX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: 1: Enable I2S TDM Rx mode . 0: Disable.*/ +#define I2S_RX_TDM_EN (BIT(19)) +#define I2S_RX_TDM_EN_M (BIT(19)) +#define I2S_RX_TDM_EN_V 0x1 +#define I2S_RX_TDM_EN_S 19 +/* I2S_RX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: I2S Rx bit endian. 1:small endian the LSB is received first. + 0:big endian the MSB is received first.*/ +#define I2S_RX_BIT_ORDER (BIT(18)) +#define I2S_RX_BIT_ORDER_M (BIT(18)) +#define I2S_RX_BIT_ORDER_V 0x1 +#define I2S_RX_BIT_ORDER_S 18 +/* I2S_RX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: 0: WS should be 0 when receiving left channel data and WS is + 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ +#define I2S_RX_WS_IDLE_POL (BIT(17)) +#define I2S_RX_WS_IDLE_POL_M (BIT(17)) +#define I2S_RX_WS_IDLE_POL_V 0x1 +#define I2S_RX_WS_IDLE_POL_S 17 +/* I2S_RX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ +#define I2S_RX_24_FILL_EN (BIT(16)) +#define I2S_RX_24_FILL_EN_M (BIT(16)) +#define I2S_RX_24_FILL_EN_V 0x1 +#define I2S_RX_24_FILL_EN_S 16 +/* I2S_RX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ +#define I2S_RX_LEFT_ALIGN (BIT(15)) +#define I2S_RX_LEFT_ALIGN_M (BIT(15)) +#define I2S_RX_LEFT_ALIGN_V 0x1 +#define I2S_RX_LEFT_ALIGN_S 15 +/* I2S_RX_STOP_MODE : R/W ;bitpos:[14:13] ;default: 2'd0 ; */ +/*description: 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop + when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ +#define I2S_RX_STOP_MODE 0x00000003 +#define I2S_RX_STOP_MODE_M ((I2S_RX_STOP_MODE_V) << (I2S_RX_STOP_MODE_S)) +#define I2S_RX_STOP_MODE_V 0x3 +#define I2S_RX_STOP_MODE_S 13 +/* I2S_RX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to bypass Compress/Decompress module for received data.*/ +#define I2S_RX_PCM_BYPASS (BIT(12)) +#define I2S_RX_PCM_BYPASS_M (BIT(12)) +#define I2S_RX_PCM_BYPASS_V 0x1 +#define I2S_RX_PCM_BYPASS_S 12 +/* I2S_RX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h1 ; */ +/*description: I2S RX compress/decompress configuration bit. & 0 (atol): A-Law + decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ +#define I2S_RX_PCM_CONF 0x00000003 +#define I2S_RX_PCM_CONF_M ((I2S_RX_PCM_CONF_V) << (I2S_RX_PCM_CONF_S)) +#define I2S_RX_PCM_CONF_V 0x3 +#define I2S_RX_PCM_CONF_S 10 +/* I2S_RX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: 1: The first channel data value is valid in I2S RX mono mode. + 0: The second channel data value is valid in I2S RX mono mode.*/ +#define I2S_RX_MONO_FST_VLD (BIT(9)) +#define I2S_RX_MONO_FST_VLD_M (BIT(9)) +#define I2S_RX_MONO_FST_VLD_V 0x1 +#define I2S_RX_MONO_FST_VLD_S 9 +/* I2S_RX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set 1 to update I2S RX registers from APB clock domain to I2S + RX clock domain. This bit will be cleared by hardware after update register done.*/ +#define I2S_RX_UPDATE (BIT(8)) +#define I2S_RX_UPDATE_M (BIT(8)) +#define I2S_RX_UPDATE_V 0x1 +#define I2S_RX_UPDATE_S 8 +/* I2S_RX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: I2S Rx byte endian 1: low addr value to high addr. 0: low addr + with low addr value.*/ +#define I2S_RX_BIG_ENDIAN (BIT(7)) +#define I2S_RX_BIG_ENDIAN_M (BIT(7)) +#define I2S_RX_BIG_ENDIAN_V 0x1 +#define I2S_RX_BIG_ENDIAN_S 7 +/* I2S_RX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable receiver in mono mode*/ +#define I2S_RX_MONO (BIT(5)) +#define I2S_RX_MONO_M (BIT(5)) +#define I2S_RX_MONO_V 0x1 +#define I2S_RX_MONO_S 5 +/* I2S_RX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable slave receiver mode*/ +#define I2S_RX_SLAVE_MOD (BIT(3)) +#define I2S_RX_SLAVE_MOD_M (BIT(3)) +#define I2S_RX_SLAVE_MOD_V 0x1 +#define I2S_RX_SLAVE_MOD_S 3 +/* I2S_RX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to start receiving data*/ +#define I2S_RX_START (BIT(2)) +#define I2S_RX_START_M (BIT(2)) +#define I2S_RX_START_V 0x1 +#define I2S_RX_START_S 2 +/* I2S_RX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset Rx AFIFO*/ +#define I2S_RX_FIFO_RESET (BIT(1)) +#define I2S_RX_FIFO_RESET_M (BIT(1)) +#define I2S_RX_FIFO_RESET_V 0x1 +#define I2S_RX_FIFO_RESET_S 1 +/* I2S_RX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to reset receiver*/ +#define I2S_RX_RESET (BIT(0)) +#define I2S_RX_RESET_M (BIT(0)) +#define I2S_RX_RESET_V 0x1 +#define I2S_RX_RESET_S 0 + +#define I2S_TX_CONF_REG(i) (REG_I2S_BASE(i) + 0x0024) +/* I2S_SIG_LOOPBACK : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable signal loop back mode with transmitter module and receiver + module sharing the same WS and BCK signals.*/ +#define I2S_SIG_LOOPBACK (BIT(27)) +#define I2S_SIG_LOOPBACK_M (BIT(27)) +#define I2S_SIG_LOOPBACK_V 0x1 +#define I2S_SIG_LOOPBACK_S 27 +/* I2S_TX_CHAN_MOD : R/W ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: I2S transmitter channel mode configuration bits.*/ +#define I2S_TX_CHAN_MOD 0x00000007 +#define I2S_TX_CHAN_MOD_M ((I2S_TX_CHAN_MOD_V) << (I2S_TX_CHAN_MOD_S)) +#define I2S_TX_CHAN_MOD_V 0x7 +#define I2S_TX_CHAN_MOD_S 24 +/* I2S_TX_PDM_EN : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: 1: Enable I2S PDM Tx mode . 0: Disable.*/ +#define I2S_TX_PDM_EN (BIT(20)) +#define I2S_TX_PDM_EN_M (BIT(20)) +#define I2S_TX_PDM_EN_V 0x1 +#define I2S_TX_PDM_EN_S 20 +/* I2S_TX_TDM_EN : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: 1: Enable I2S TDM Tx mode . 0: Disable.*/ +#define I2S_TX_TDM_EN (BIT(19)) +#define I2S_TX_TDM_EN_M (BIT(19)) +#define I2S_TX_TDM_EN_V 0x1 +#define I2S_TX_TDM_EN_S 19 +/* I2S_TX_BIT_ORDER : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big + endian the MSB is sent first.*/ +#define I2S_TX_BIT_ORDER (BIT(18)) +#define I2S_TX_BIT_ORDER_M (BIT(18)) +#define I2S_TX_BIT_ORDER_V 0x1 +#define I2S_TX_BIT_ORDER_S 18 +/* I2S_TX_WS_IDLE_POL : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: 0: WS should be 0 when sending left channel data and WS is 1in + right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ +#define I2S_TX_WS_IDLE_POL (BIT(17)) +#define I2S_TX_WS_IDLE_POL_M (BIT(17)) +#define I2S_TX_WS_IDLE_POL_V 0x1 +#define I2S_TX_WS_IDLE_POL_S 17 +/* I2S_TX_24_FILL_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ +#define I2S_TX_24_FILL_EN (BIT(16)) +#define I2S_TX_24_FILL_EN_M (BIT(16)) +#define I2S_TX_24_FILL_EN_V 0x1 +#define I2S_TX_24_FILL_EN_S 16 +/* I2S_TX_LEFT_ALIGN : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ +#define I2S_TX_LEFT_ALIGN (BIT(15)) +#define I2S_TX_LEFT_ALIGN_M (BIT(15)) +#define I2S_TX_LEFT_ALIGN_V 0x1 +#define I2S_TX_LEFT_ALIGN_S 15 +/* I2S_TX_STOP_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to stop disable output BCK signal and WS signal + when tx FIFO is emtpy*/ +#define I2S_TX_STOP_EN (BIT(13)) +#define I2S_TX_STOP_EN_M (BIT(13)) +#define I2S_TX_STOP_EN_V 0x1 +#define I2S_TX_STOP_EN_S 13 +/* I2S_TX_PCM_BYPASS : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to bypass Compress/Decompress module for transmitted data.*/ +#define I2S_TX_PCM_BYPASS (BIT(12)) +#define I2S_TX_PCM_BYPASS_M (BIT(12)) +#define I2S_TX_PCM_BYPASS_V 0x1 +#define I2S_TX_PCM_BYPASS_S 12 +/* I2S_TX_PCM_CONF : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: I2S TX compress/decompress configuration bit. & 0 (atol): A-Law + decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ +#define I2S_TX_PCM_CONF 0x00000003 +#define I2S_TX_PCM_CONF_M ((I2S_TX_PCM_CONF_V) << (I2S_TX_PCM_CONF_S)) +#define I2S_TX_PCM_CONF_V 0x3 +#define I2S_TX_PCM_CONF_S 10 +/* I2S_TX_MONO_FST_VLD : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: 1: The first channel data value is valid in I2S TX mono mode. + 0: The second channel data value is valid in I2S TX mono mode.*/ +#define I2S_TX_MONO_FST_VLD (BIT(9)) +#define I2S_TX_MONO_FST_VLD_M (BIT(9)) +#define I2S_TX_MONO_FST_VLD_V 0x1 +#define I2S_TX_MONO_FST_VLD_S 9 +/* I2S_TX_UPDATE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Set 1 to update I2S TX registers from APB clock domain to I2S + TX clock domain. This bit will be cleared by hardware after update register done.*/ +#define I2S_TX_UPDATE (BIT(8)) +#define I2S_TX_UPDATE_M (BIT(8)) +#define I2S_TX_UPDATE_V 0x1 +#define I2S_TX_UPDATE_S 8 +/* I2S_TX_BIG_ENDIAN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: I2S Tx byte endian 1: low addr value to high addr. 0: low addr + with low addr value.*/ +#define I2S_TX_BIG_ENDIAN (BIT(7)) +#define I2S_TX_BIG_ENDIAN_M (BIT(7)) +#define I2S_TX_BIG_ENDIAN_V 0x1 +#define I2S_TX_BIG_ENDIAN_S 7 +/* I2S_TX_CHAN_EQUAL : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: The value of Left channel data is equal to the value of right + channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ +#define I2S_TX_CHAN_EQUAL (BIT(6)) +#define I2S_TX_CHAN_EQUAL_M (BIT(6)) +#define I2S_TX_CHAN_EQUAL_V 0x1 +#define I2S_TX_CHAN_EQUAL_S 6 +/* I2S_TX_MONO : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Set this bit to enable transmitter in mono mode*/ +#define I2S_TX_MONO (BIT(5)) +#define I2S_TX_MONO_M (BIT(5)) +#define I2S_TX_MONO_V 0x1 +#define I2S_TX_MONO_S 5 +/* I2S_TX_SLAVE_MOD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set this bit to enable slave transmitter mode*/ +#define I2S_TX_SLAVE_MOD (BIT(3)) +#define I2S_TX_SLAVE_MOD_M (BIT(3)) +#define I2S_TX_SLAVE_MOD_V 0x1 +#define I2S_TX_SLAVE_MOD_S 3 +/* I2S_TX_START : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set this bit to start transmitting data*/ +#define I2S_TX_START (BIT(2)) +#define I2S_TX_START_M (BIT(2)) +#define I2S_TX_START_V 0x1 +#define I2S_TX_START_S 2 +/* I2S_TX_FIFO_RESET : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to reset Tx AFIFO*/ +#define I2S_TX_FIFO_RESET (BIT(1)) +#define I2S_TX_FIFO_RESET_M (BIT(1)) +#define I2S_TX_FIFO_RESET_V 0x1 +#define I2S_TX_FIFO_RESET_S 1 +/* I2S_TX_RESET : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to reset transmitter*/ +#define I2S_TX_RESET (BIT(0)) +#define I2S_TX_RESET_M (BIT(0)) +#define I2S_TX_RESET_V 0x1 +#define I2S_TX_RESET_S 0 + +#define I2S_RX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x0028) +/* I2S_RX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to enable receiver in Phillips standard mode*/ +#define I2S_RX_MSB_SHIFT (BIT(29)) +#define I2S_RX_MSB_SHIFT_M (BIT(29)) +#define I2S_RX_MSB_SHIFT_V 0x1 +#define I2S_RX_MSB_SHIFT_S 29 +/* I2S_RX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ +/*description: The Rx bit number for each channel minus 1in TDM mode.*/ +#define I2S_RX_TDM_CHAN_BITS 0x0000001F +#define I2S_RX_TDM_CHAN_BITS_M ((I2S_RX_TDM_CHAN_BITS_V) << (I2S_RX_TDM_CHAN_BITS_S)) +#define I2S_RX_TDM_CHAN_BITS_V 0x1F +#define I2S_RX_TDM_CHAN_BITS_S 24 +/* I2S_RX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ +/*description: I2S Rx half sample bits -1.*/ +#define I2S_RX_HALF_SAMPLE_BITS 0x0000003F +#define I2S_RX_HALF_SAMPLE_BITS_M ((I2S_RX_HALF_SAMPLE_BITS_V) << (I2S_RX_HALF_SAMPLE_BITS_S)) +#define I2S_RX_HALF_SAMPLE_BITS_V 0x3F +#define I2S_RX_HALF_SAMPLE_BITS_S 18 +/* I2S_RX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ +/*description: Set the bits to configure bit length of I2S receiver channel.*/ +#define I2S_RX_BITS_MOD 0x0000001F +#define I2S_RX_BITS_MOD_M ((I2S_RX_BITS_MOD_V) << (I2S_RX_BITS_MOD_S)) +#define I2S_RX_BITS_MOD_V 0x1F +#define I2S_RX_BITS_MOD_S 13 +/* I2S_RX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ +/*description: Bit clock configuration bits in receiver mode.*/ +#define I2S_RX_BCK_DIV_NUM 0x0000003F +#define I2S_RX_BCK_DIV_NUM_M ((I2S_RX_BCK_DIV_NUM_V) << (I2S_RX_BCK_DIV_NUM_S)) +#define I2S_RX_BCK_DIV_NUM_V 0x3F +#define I2S_RX_BCK_DIV_NUM_S 7 +/* I2S_RX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ +#define I2S_RX_TDM_WS_WIDTH 0x0000007F +#define I2S_RX_TDM_WS_WIDTH_M ((I2S_RX_TDM_WS_WIDTH_V) << (I2S_RX_TDM_WS_WIDTH_S)) +#define I2S_RX_TDM_WS_WIDTH_V 0x7F +#define I2S_RX_TDM_WS_WIDTH_S 0 + +#define I2S_TX_CONF1_REG(i) (REG_I2S_BASE(i) + 0x002C) +/* I2S_TX_MSB_SHIFT : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: Set this bit to enable transmitter in Phillips standard mode*/ +#define I2S_TX_MSB_SHIFT (BIT(29)) +#define I2S_TX_MSB_SHIFT_M (BIT(29)) +#define I2S_TX_MSB_SHIFT_V 0x1 +#define I2S_TX_MSB_SHIFT_S 29 +/* I2S_TX_TDM_CHAN_BITS : R/W ;bitpos:[28:24] ;default: 5'hF ; */ +/*description: The Tx bit number for each channel minus 1in TDM mode.*/ +#define I2S_TX_TDM_CHAN_BITS 0x0000001F +#define I2S_TX_TDM_CHAN_BITS_M ((I2S_TX_TDM_CHAN_BITS_V) << (I2S_TX_TDM_CHAN_BITS_S)) +#define I2S_TX_TDM_CHAN_BITS_V 0x1F +#define I2S_TX_TDM_CHAN_BITS_S 24 +/* I2S_TX_HALF_SAMPLE_BITS : R/W ;bitpos:[23:18] ;default: 6'hF ; */ +/*description: I2S Tx half sample bits -1.*/ +#define I2S_TX_HALF_SAMPLE_BITS 0x0000003F +#define I2S_TX_HALF_SAMPLE_BITS_M ((I2S_TX_HALF_SAMPLE_BITS_V) << (I2S_TX_HALF_SAMPLE_BITS_S)) +#define I2S_TX_HALF_SAMPLE_BITS_V 0x3F +#define I2S_TX_HALF_SAMPLE_BITS_S 18 +/* I2S_TX_BITS_MOD : R/W ;bitpos:[17:13] ;default: 5'hF ; */ +/*description: Set the bits to configure bit length of I2S transmitter channel.*/ +#define I2S_TX_BITS_MOD 0x0000001F +#define I2S_TX_BITS_MOD_M ((I2S_TX_BITS_MOD_V) << (I2S_TX_BITS_MOD_S)) +#define I2S_TX_BITS_MOD_V 0x1F +#define I2S_TX_BITS_MOD_S 13 +/* I2S_TX_BCK_DIV_NUM : R/W ;bitpos:[12:7] ;default: 6'd6 ; */ +/*description: Bit clock configuration bits in transmitter mode.*/ +#define I2S_TX_BCK_DIV_NUM 0x0000003F +#define I2S_TX_BCK_DIV_NUM_M ((I2S_TX_BCK_DIV_NUM_V) << (I2S_TX_BCK_DIV_NUM_S)) +#define I2S_TX_BCK_DIV_NUM_V 0x3F +#define I2S_TX_BCK_DIV_NUM_S 7 +/* I2S_TX_TDM_WS_WIDTH : R/W ;bitpos:[6:0] ;default: 7'h0 ; */ +/*description: The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ +#define I2S_TX_TDM_WS_WIDTH 0x0000007F +#define I2S_TX_TDM_WS_WIDTH_M ((I2S_TX_TDM_WS_WIDTH_V) << (I2S_TX_TDM_WS_WIDTH_S)) +#define I2S_TX_TDM_WS_WIDTH_V 0x7F +#define I2S_TX_TDM_WS_WIDTH_S 0 + +#define I2S_RX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0030) +/* I2S_MCLK_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module + clock as I2S_MCLK_OUT.*/ +#define I2S_MCLK_SEL (BIT(29)) +#define I2S_MCLK_SEL_M (BIT(29)) +#define I2S_MCLK_SEL_V 0x1 +#define I2S_MCLK_SEL_S 29 +/* I2S_RX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. + 3: I2S_MCLK_in.*/ +#define I2S_RX_CLK_SEL 0x00000003 +#define I2S_RX_CLK_SEL_M ((I2S_RX_CLK_SEL_V) << (I2S_RX_CLK_SEL_S)) +#define I2S_RX_CLK_SEL_V 0x3 +#define I2S_RX_CLK_SEL_S 27 +/* I2S_RX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: I2S Rx module clock enable signal.*/ +#define I2S_RX_CLK_ACTIVE (BIT(26)) +#define I2S_RX_CLK_ACTIVE_M (BIT(26)) +#define I2S_RX_CLK_ACTIVE_V 0x1 +#define I2S_RX_CLK_ACTIVE_S 26 +/* I2S_RX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: Integral I2S clock divider value*/ +#define I2S_RX_CLKM_DIV_NUM 0x000000FF +#define I2S_RX_CLKM_DIV_NUM_M ((I2S_RX_CLKM_DIV_NUM_V) << (I2S_RX_CLKM_DIV_NUM_S)) +#define I2S_RX_CLKM_DIV_NUM_V 0xFF +#define I2S_RX_CLKM_DIV_NUM_S 0 + +#define I2S_TX_CLKM_CONF_REG(i) (REG_I2S_BASE(i) + 0x0034) +/* I2S_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable clk gate*/ +#define I2S_CLK_EN (BIT(29)) +#define I2S_CLK_EN_M (BIT(29)) +#define I2S_CLK_EN_V 0x1 +#define I2S_CLK_EN_S 29 +/* I2S_TX_CLK_SEL : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: + CLK160. 3: I2S_MCLK_in.*/ +#define I2S_TX_CLK_SEL 0x00000003 +#define I2S_TX_CLK_SEL_M ((I2S_TX_CLK_SEL_V) << (I2S_TX_CLK_SEL_S)) +#define I2S_TX_CLK_SEL_V 0x3 +#define I2S_TX_CLK_SEL_S 27 +/* I2S_TX_CLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: I2S Tx module clock enable signal.*/ +#define I2S_TX_CLK_ACTIVE (BIT(26)) +#define I2S_TX_CLK_ACTIVE_M (BIT(26)) +#define I2S_TX_CLK_ACTIVE_V 0x1 +#define I2S_TX_CLK_ACTIVE_S 26 +/* I2S_TX_CLKM_DIV_NUM : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). + There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ +#define I2S_TX_CLKM_DIV_NUM 0x000000FF +#define I2S_TX_CLKM_DIV_NUM_M ((I2S_TX_CLKM_DIV_NUM_V) << (I2S_TX_CLKM_DIV_NUM_S)) +#define I2S_TX_CLKM_DIV_NUM_V 0xFF +#define I2S_TX_CLKM_DIV_NUM_S 0 + +#define I2S_RX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x0038) +/* I2S_RX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > + a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ +#define I2S_RX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_M (BIT(27)) +#define I2S_RX_CLKM_DIV_YN1_V 0x1 +#define I2S_RX_CLKM_DIV_YN1_S 27 +/* I2S_RX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For + b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ +#define I2S_RX_CLKM_DIV_X 0x000001FF +#define I2S_RX_CLKM_DIV_X_M ((I2S_RX_CLKM_DIV_X_V) << (I2S_RX_CLKM_DIV_X_S)) +#define I2S_RX_CLKM_DIV_X_V 0x1FF +#define I2S_RX_CLKM_DIV_X_S 18 +/* I2S_RX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b + > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ +#define I2S_RX_CLKM_DIV_Y 0x000001FF +#define I2S_RX_CLKM_DIV_Y_M ((I2S_RX_CLKM_DIV_Y_V) << (I2S_RX_CLKM_DIV_Y_S)) +#define I2S_RX_CLKM_DIV_Y_V 0x1FF +#define I2S_RX_CLKM_DIV_Y_S 9 +/* I2S_RX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 + the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ +#define I2S_RX_CLKM_DIV_Z 0x000001FF +#define I2S_RX_CLKM_DIV_Z_M ((I2S_RX_CLKM_DIV_Z_V) << (I2S_RX_CLKM_DIV_Z_S)) +#define I2S_RX_CLKM_DIV_Z_V 0x1FF +#define I2S_RX_CLKM_DIV_Z_S 0 + +#define I2S_TX_CLKM_DIV_CONF_REG(i) (REG_I2S_BASE(i) + 0x003C) +/* I2S_TX_CLKM_DIV_YN1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > + a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ +#define I2S_TX_CLKM_DIV_YN1 (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_M (BIT(27)) +#define I2S_TX_CLKM_DIV_YN1_V 0x1 +#define I2S_TX_CLKM_DIV_YN1_S 27 +/* I2S_TX_CLKM_DIV_X : R/W ;bitpos:[26:18] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For + b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ +#define I2S_TX_CLKM_DIV_X 0x000001FF +#define I2S_TX_CLKM_DIV_X_M ((I2S_TX_CLKM_DIV_X_V) << (I2S_TX_CLKM_DIV_X_S)) +#define I2S_TX_CLKM_DIV_X_V 0x1FF +#define I2S_TX_CLKM_DIV_X_S 18 +/* I2S_TX_CLKM_DIV_Y : R/W ;bitpos:[17:9] ;default: 9'h1 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b + > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ +#define I2S_TX_CLKM_DIV_Y 0x000001FF +#define I2S_TX_CLKM_DIV_Y_M ((I2S_TX_CLKM_DIV_Y_V) << (I2S_TX_CLKM_DIV_Y_S)) +#define I2S_TX_CLKM_DIV_Y_V 0x1FF +#define I2S_TX_CLKM_DIV_Y_S 9 +/* I2S_TX_CLKM_DIV_Z : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 + the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ +#define I2S_TX_CLKM_DIV_Z 0x000001FF +#define I2S_TX_CLKM_DIV_Z_M ((I2S_TX_CLKM_DIV_Z_V) << (I2S_TX_CLKM_DIV_Z_S)) +#define I2S_TX_CLKM_DIV_Z_V 0x1FF +#define I2S_TX_CLKM_DIV_Z_S 0 + +#define I2S_RX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0050) +/* I2S_RX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: The total channel number of I2S TX TDM mode.*/ +#define I2S_RX_TDM_TOT_CHAN_NUM 0x0000000F +#define I2S_RX_TDM_TOT_CHAN_NUM_M ((I2S_RX_TDM_TOT_CHAN_NUM_V) << (I2S_RX_TDM_TOT_CHAN_NUM_S)) +#define I2S_RX_TDM_TOT_CHAN_NUM_V 0xF +#define I2S_RX_TDM_TOT_CHAN_NUM_S 16 +/* I2S_RX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN15_EN (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_M (BIT(15)) +#define I2S_RX_TDM_CHAN15_EN_V 0x1 +#define I2S_RX_TDM_CHAN15_EN_S 15 +/* I2S_RX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN14_EN (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_M (BIT(14)) +#define I2S_RX_TDM_CHAN14_EN_V 0x1 +#define I2S_RX_TDM_CHAN14_EN_S 14 +/* I2S_RX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN13_EN (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_M (BIT(13)) +#define I2S_RX_TDM_CHAN13_EN_V 0x1 +#define I2S_RX_TDM_CHAN13_EN_S 13 +/* I2S_RX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN12_EN (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_M (BIT(12)) +#define I2S_RX_TDM_CHAN12_EN_V 0x1 +#define I2S_RX_TDM_CHAN12_EN_S 12 +/* I2S_RX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN11_EN (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_M (BIT(11)) +#define I2S_RX_TDM_CHAN11_EN_V 0x1 +#define I2S_RX_TDM_CHAN11_EN_S 11 +/* I2S_RX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN10_EN (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_M (BIT(10)) +#define I2S_RX_TDM_CHAN10_EN_V 0x1 +#define I2S_RX_TDM_CHAN10_EN_S 10 +/* I2S_RX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN9_EN (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_M (BIT(9)) +#define I2S_RX_TDM_CHAN9_EN_V 0x1 +#define I2S_RX_TDM_CHAN9_EN_S 9 +/* I2S_RX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM channel $n. 0: + Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_CHAN8_EN (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_M (BIT(8)) +#define I2S_RX_TDM_CHAN8_EN_V 0x1 +#define I2S_RX_TDM_CHAN8_EN_S 8 +/* I2S_RX_TDM_PDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN7_EN (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_M (BIT(7)) +#define I2S_RX_TDM_PDM_CHAN7_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN7_EN_S 7 +/* I2S_RX_TDM_PDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN6_EN (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_M (BIT(6)) +#define I2S_RX_TDM_PDM_CHAN6_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN6_EN_S 6 +/* I2S_RX_TDM_PDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN5_EN (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_M (BIT(5)) +#define I2S_RX_TDM_PDM_CHAN5_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN5_EN_S 5 +/* I2S_RX_TDM_PDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN4_EN (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_M (BIT(4)) +#define I2S_RX_TDM_PDM_CHAN4_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN4_EN_S 4 +/* I2S_RX_TDM_PDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN3_EN (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_M (BIT(3)) +#define I2S_RX_TDM_PDM_CHAN3_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN3_EN_S 3 +/* I2S_RX_TDM_PDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN2_EN (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_M (BIT(2)) +#define I2S_RX_TDM_PDM_CHAN2_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN2_EN_S 2 +/* I2S_RX_TDM_PDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN1_EN (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_M (BIT(1)) +#define I2S_RX_TDM_PDM_CHAN1_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN1_EN_S 1 +/* I2S_RX_TDM_PDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data input of I2S RX TDM or PDM channel $n. + 0: Disable just input 0 in this channel.*/ +#define I2S_RX_TDM_PDM_CHAN0_EN (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_M (BIT(0)) +#define I2S_RX_TDM_PDM_CHAN0_EN_V 0x1 +#define I2S_RX_TDM_PDM_CHAN0_EN_S 0 + +#define I2S_TX_TDM_CTRL_REG(i) (REG_I2S_BASE(i) + 0x0054) +/* I2S_TX_TDM_SKIP_MSK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ +#define I2S_TX_TDM_SKIP_MSK_EN (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_M (BIT(20)) +#define I2S_TX_TDM_SKIP_MSK_EN_V 0x1 +#define I2S_TX_TDM_SKIP_MSK_EN_S 20 +/* I2S_TX_TDM_TOT_CHAN_NUM : R/W ;bitpos:[19:16] ;default: 4'h0 ; */ +/*description: The total channel number minus 1 of I2S TX TDM mode.*/ +#define I2S_TX_TDM_TOT_CHAN_NUM 0x0000000F +#define I2S_TX_TDM_TOT_CHAN_NUM_M ((I2S_TX_TDM_TOT_CHAN_NUM_V) << (I2S_TX_TDM_TOT_CHAN_NUM_S)) +#define I2S_TX_TDM_TOT_CHAN_NUM_V 0xF +#define I2S_TX_TDM_TOT_CHAN_NUM_S 16 +/* I2S_TX_TDM_CHAN15_EN : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN15_EN (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_M (BIT(15)) +#define I2S_TX_TDM_CHAN15_EN_V 0x1 +#define I2S_TX_TDM_CHAN15_EN_S 15 +/* I2S_TX_TDM_CHAN14_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN14_EN (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_M (BIT(14)) +#define I2S_TX_TDM_CHAN14_EN_V 0x1 +#define I2S_TX_TDM_CHAN14_EN_S 14 +/* I2S_TX_TDM_CHAN13_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN13_EN (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_M (BIT(13)) +#define I2S_TX_TDM_CHAN13_EN_V 0x1 +#define I2S_TX_TDM_CHAN13_EN_S 13 +/* I2S_TX_TDM_CHAN12_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN12_EN (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_M (BIT(12)) +#define I2S_TX_TDM_CHAN12_EN_V 0x1 +#define I2S_TX_TDM_CHAN12_EN_S 12 +/* I2S_TX_TDM_CHAN11_EN : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN11_EN (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_M (BIT(11)) +#define I2S_TX_TDM_CHAN11_EN_V 0x1 +#define I2S_TX_TDM_CHAN11_EN_S 11 +/* I2S_TX_TDM_CHAN10_EN : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN10_EN (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_M (BIT(10)) +#define I2S_TX_TDM_CHAN10_EN_V 0x1 +#define I2S_TX_TDM_CHAN10_EN_S 10 +/* I2S_TX_TDM_CHAN9_EN : R/W ;bitpos:[9] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN9_EN (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_M (BIT(9)) +#define I2S_TX_TDM_CHAN9_EN_V 0x1 +#define I2S_TX_TDM_CHAN9_EN_S 9 +/* I2S_TX_TDM_CHAN8_EN : R/W ;bitpos:[8] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN8_EN (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_M (BIT(8)) +#define I2S_TX_TDM_CHAN8_EN_V 0x1 +#define I2S_TX_TDM_CHAN8_EN_S 8 +/* I2S_TX_TDM_CHAN7_EN : R/W ;bitpos:[7] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN7_EN (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_M (BIT(7)) +#define I2S_TX_TDM_CHAN7_EN_V 0x1 +#define I2S_TX_TDM_CHAN7_EN_S 7 +/* I2S_TX_TDM_CHAN6_EN : R/W ;bitpos:[6] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN6_EN (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_M (BIT(6)) +#define I2S_TX_TDM_CHAN6_EN_V 0x1 +#define I2S_TX_TDM_CHAN6_EN_S 6 +/* I2S_TX_TDM_CHAN5_EN : R/W ;bitpos:[5] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN5_EN (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_M (BIT(5)) +#define I2S_TX_TDM_CHAN5_EN_V 0x1 +#define I2S_TX_TDM_CHAN5_EN_S 5 +/* I2S_TX_TDM_CHAN4_EN : R/W ;bitpos:[4] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN4_EN (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_M (BIT(4)) +#define I2S_TX_TDM_CHAN4_EN_V 0x1 +#define I2S_TX_TDM_CHAN4_EN_S 4 +/* I2S_TX_TDM_CHAN3_EN : R/W ;bitpos:[3] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN3_EN (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_M (BIT(3)) +#define I2S_TX_TDM_CHAN3_EN_V 0x1 +#define I2S_TX_TDM_CHAN3_EN_S 3 +/* I2S_TX_TDM_CHAN2_EN : R/W ;bitpos:[2] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN2_EN (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_M (BIT(2)) +#define I2S_TX_TDM_CHAN2_EN_V 0x1 +#define I2S_TX_TDM_CHAN2_EN_S 2 +/* I2S_TX_TDM_CHAN1_EN : R/W ;bitpos:[1] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN1_EN (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_M (BIT(1)) +#define I2S_TX_TDM_CHAN1_EN_V 0x1 +#define I2S_TX_TDM_CHAN1_EN_S 1 +/* I2S_TX_TDM_CHAN0_EN : R/W ;bitpos:[0] ;default: 1'h1 ; */ +/*description: 1: Enable the valid data output of I2S TX TDM channel $n. 0: + Disable just output 0 in this channel.*/ +#define I2S_TX_TDM_CHAN0_EN (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_M (BIT(0)) +#define I2S_TX_TDM_CHAN0_EN_V 0x1 +#define I2S_TX_TDM_CHAN0_EN_S 0 + +#define I2S_RX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x0058) +/* I2S_RX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_BCK_IN_DM 0x00000003 +#define I2S_RX_BCK_IN_DM_M ((I2S_RX_BCK_IN_DM_V) << (I2S_RX_BCK_IN_DM_S)) +#define I2S_RX_BCK_IN_DM_V 0x3 +#define I2S_RX_BCK_IN_DM_S 28 +/* I2S_RX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_WS_IN_DM 0x00000003 +#define I2S_RX_WS_IN_DM_M ((I2S_RX_WS_IN_DM_V) << (I2S_RX_WS_IN_DM_S)) +#define I2S_RX_WS_IN_DM_V 0x3 +#define I2S_RX_WS_IN_DM_S 24 +/* I2S_RX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_BCK_OUT_DM 0x00000003 +#define I2S_RX_BCK_OUT_DM_M ((I2S_RX_BCK_OUT_DM_V) << (I2S_RX_BCK_OUT_DM_S)) +#define I2S_RX_BCK_OUT_DM_V 0x3 +#define I2S_RX_BCK_OUT_DM_S 20 +/* I2S_RX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_WS_OUT_DM 0x00000003 +#define I2S_RX_WS_OUT_DM_M ((I2S_RX_WS_OUT_DM_V) << (I2S_RX_WS_OUT_DM_S)) +#define I2S_RX_WS_OUT_DM_V 0x3 +#define I2S_RX_WS_OUT_DM_S 16 +/* I2S_RX_SD3_IN_DM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD3_IN_DM 0x00000003 +#define I2S_RX_SD3_IN_DM_M ((I2S_RX_SD3_IN_DM_V) << (I2S_RX_SD3_IN_DM_S)) +#define I2S_RX_SD3_IN_DM_V 0x3 +#define I2S_RX_SD3_IN_DM_S 12 +/* I2S_RX_SD2_IN_DM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD2_IN_DM 0x00000003 +#define I2S_RX_SD2_IN_DM_M ((I2S_RX_SD2_IN_DM_V) << (I2S_RX_SD2_IN_DM_S)) +#define I2S_RX_SD2_IN_DM_V 0x3 +#define I2S_RX_SD2_IN_DM_S 8 +/* I2S_RX_SD1_IN_DM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD1_IN_DM 0x00000003 +#define I2S_RX_SD1_IN_DM_M ((I2S_RX_SD1_IN_DM_V) << (I2S_RX_SD1_IN_DM_S)) +#define I2S_RX_SD1_IN_DM_V 0x3 +#define I2S_RX_SD1_IN_DM_S 4 +/* I2S_RX_SD_IN_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_RX_SD_IN_DM 0x00000003 +#define I2S_RX_SD_IN_DM_M ((I2S_RX_SD_IN_DM_V) << (I2S_RX_SD_IN_DM_S)) +#define I2S_RX_SD_IN_DM_V 0x3 +#define I2S_RX_SD_IN_DM_S 0 + +#define I2S_TX_TIMING_REG(i) (REG_I2S_BASE(i) + 0x005C) +/* I2S_TX_BCK_IN_DM : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_BCK_IN_DM 0x00000003 +#define I2S_TX_BCK_IN_DM_M ((I2S_TX_BCK_IN_DM_V) << (I2S_TX_BCK_IN_DM_S)) +#define I2S_TX_BCK_IN_DM_V 0x3 +#define I2S_TX_BCK_IN_DM_S 28 +/* I2S_TX_WS_IN_DM : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_WS_IN_DM 0x00000003 +#define I2S_TX_WS_IN_DM_M ((I2S_TX_WS_IN_DM_V) << (I2S_TX_WS_IN_DM_S)) +#define I2S_TX_WS_IN_DM_V 0x3 +#define I2S_TX_WS_IN_DM_S 24 +/* I2S_TX_BCK_OUT_DM : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_BCK_OUT_DM 0x00000003 +#define I2S_TX_BCK_OUT_DM_M ((I2S_TX_BCK_OUT_DM_V) << (I2S_TX_BCK_OUT_DM_S)) +#define I2S_TX_BCK_OUT_DM_V 0x3 +#define I2S_TX_BCK_OUT_DM_S 20 +/* I2S_TX_WS_OUT_DM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_WS_OUT_DM 0x00000003 +#define I2S_TX_WS_OUT_DM_M ((I2S_TX_WS_OUT_DM_V) << (I2S_TX_WS_OUT_DM_S)) +#define I2S_TX_WS_OUT_DM_V 0x3 +#define I2S_TX_WS_OUT_DM_S 16 +/* I2S_TX_SD_OUT_DM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay + by pos edge. 2: delay by neg edge. 3: not used.*/ +#define I2S_TX_SD_OUT_DM 0x00000003 +#define I2S_TX_SD_OUT_DM_M ((I2S_TX_SD_OUT_DM_V) << (I2S_TX_SD_OUT_DM_S)) +#define I2S_TX_SD_OUT_DM_V 0x3 +#define I2S_TX_SD_OUT_DM_S 0 + +#define I2S_LC_HUNG_CONF_REG(i) (REG_I2S_BASE(i) + 0x0060) +/* I2S_LC_FIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: The enable bit for FIFO timeout*/ +#define I2S_LC_FIFO_TIMEOUT_ENA (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_M (BIT(11)) +#define I2S_LC_FIFO_TIMEOUT_ENA_V 0x1 +#define I2S_LC_FIFO_TIMEOUT_ENA_S 11 +/* I2S_LC_FIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: The bits are used to scale tick counter threshold. The tick counter + is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ +#define I2S_LC_FIFO_TIMEOUT_SHIFT 0x00000007 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_M ((I2S_LC_FIFO_TIMEOUT_SHIFT_V) << (I2S_LC_FIFO_TIMEOUT_SHIFT_S)) +#define I2S_LC_FIFO_TIMEOUT_SHIFT_V 0x7 +#define I2S_LC_FIFO_TIMEOUT_SHIFT_S 8 +/* I2S_LC_FIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt + will be triggered when fifo hung counter is equal to this value*/ +#define I2S_LC_FIFO_TIMEOUT 0x000000FF +#define I2S_LC_FIFO_TIMEOUT_M ((I2S_LC_FIFO_TIMEOUT_V) << (I2S_LC_FIFO_TIMEOUT_S)) +#define I2S_LC_FIFO_TIMEOUT_V 0xFF +#define I2S_LC_FIFO_TIMEOUT_S 0 + +#define I2S_RXEOF_NUM_REG(i) (REG_I2S_BASE(i) + 0x0064) +/* I2S_RX_EOF_NUM : R/W ;bitpos:[11:0] ;default: 12'h40 ; */ +/*description: the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ +#define I2S_RX_EOF_NUM 0x00000FFF +#define I2S_RX_EOF_NUM_M ((I2S_RX_EOF_NUM_V) << (I2S_RX_EOF_NUM_S)) +#define I2S_RX_EOF_NUM_V 0xFFF +#define I2S_RX_EOF_NUM_S 0 + +#define I2S_CONF_SIGLE_DATA_REG(i) (REG_I2S_BASE(i) + 0x0068) +/* I2S_SINGLE_DATA : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: the right channel or left channel put out constant value stored + in this register according to tx_chan_mod and reg_tx_msb_right*/ +#define I2S_SINGLE_DATA 0xFFFFFFFF +#define I2S_SINGLE_DATA_M ((I2S_SINGLE_DATA_V) << (I2S_SINGLE_DATA_S)) +#define I2S_SINGLE_DATA_V 0xFFFFFFFF +#define I2S_SINGLE_DATA_S 0 + +#define I2S_STATE_REG(i) (REG_I2S_BASE(i) + 0x006C) +/* I2S_TX_IDLE : RO ;bitpos:[0] ;default: 1'b1 ; */ +/*description: 1: i2s_tx is idle state. 0: i2s_tx is working.*/ +#define I2S_TX_IDLE (BIT(0)) +#define I2S_TX_IDLE_M (BIT(0)) +#define I2S_TX_IDLE_V 0x1 +#define I2S_TX_IDLE_S 0 + +#define I2S_DATE_REG(i) (REG_I2S_BASE(i) + 0x0080) +/* I2S_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003230 ; */ +/*description: Version control register*/ +#define I2S_DATE 0x0FFFFFFF +#define I2S_DATE_M ((I2S_DATE_V) << (I2S_DATE_S)) +#define I2S_DATE_V 0xFFFFFFF +#define I2S_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/i2s_struct.h b/components/soc/soc/esp32s3/include/soc/i2s_struct.h new file mode 100644 index 000000000..dc3fe097a --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/i2s_struct.h @@ -0,0 +1,318 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; + union { + struct { + uint32_t rx_done: 1; /*The raw interrupt status bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*The raw interrupt status bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*The raw interrupt status bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*The raw interrupt status bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_done: 1; /*The masked interrupt status bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*The masked interrupt status bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*The masked interrupt status bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*The masked interrupt status bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_done: 1; /*The interrupt enable bit for the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*The interrupt enable bit for the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*The interrupt enable bit for the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*The interrupt enable bit for the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_done: 1; /*Set this bit to clear the i2s_rx_done_int interrupt*/ + uint32_t tx_done: 1; /*Set this bit to clear the i2s_tx_done_int interrupt*/ + uint32_t rx_hung: 1; /*Set this bit to clear the i2s_rx_hung_int interrupt*/ + uint32_t tx_hung: 1; /*Set this bit to clear the i2s_tx_hung_int interrupt*/ + uint32_t reserved4: 28; /*Reserve*/ + }; + uint32_t val; + } int_clr; + uint32_t reserved_1c; + union { + struct { + uint32_t rx_reset: 1; /*Set this bit to reset receiver*/ + uint32_t rx_fifo_reset: 1; /*Set this bit to reset Rx AFIFO*/ + uint32_t rx_start: 1; /*Set this bit to start receiving data*/ + uint32_t rx_slave_mod: 1; /*Set this bit to enable slave receiver mode*/ + uint32_t reserved4: 1; /*Reserved*/ + uint32_t rx_mono: 1; /*Set this bit to enable receiver in mono mode*/ + uint32_t reserved6: 1; + uint32_t rx_big_endian: 1; /*I2S Rx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ + uint32_t rx_update: 1; /*Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.*/ + uint32_t rx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.*/ + uint32_t rx_pcm_conf: 2; /*I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ + uint32_t rx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for received data.*/ + uint32_t rx_stop_mode: 2; /*0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.*/ + uint32_t rx_left_align: 1; /*1: I2S RX left alignment mode. 0: I2S RX right alignment mode.*/ + uint32_t rx_24_fill_en: 1; /*1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.*/ + uint32_t rx_ws_idle_pol: 1; /*0: WS should be 0 when receiving left channel data and WS is 1in right channel. 1: WS should be 1 when receiving left channel data and WS is 0in right channel.*/ + uint32_t rx_bit_order: 1; /*I2S Rx bit endian. 1:small endian the LSB is received first. 0:big endian the MSB is received first.*/ + uint32_t rx_tdm_en: 1; /*1: Enable I2S TDM Rx mode . 0: Disable.*/ + uint32_t rx_pdm_en: 1; /*1: Enable I2S PDM Rx mode . 0: Disable.*/ + uint32_t rx_pdm2pcm_en: 1; /*1: Enable PDM2PCM RX mode. 0: DIsable.*/ + uint32_t rx_sinc_dsr_16_en: 1; + uint32_t reserved23: 9; /*Reserve*/ + }; + uint32_t val; + } rx_conf; + union { + struct { + uint32_t tx_reset: 1; /*Set this bit to reset transmitter*/ + uint32_t tx_fifo_reset: 1; /*Set this bit to reset Tx AFIFO*/ + uint32_t tx_start: 1; /*Set this bit to start transmitting data*/ + uint32_t tx_slave_mod: 1; /*Set this bit to enable slave transmitter mode*/ + uint32_t reserved4: 1; /*Reserved*/ + uint32_t tx_mono: 1; /*Set this bit to enable transmitter in mono mode*/ + uint32_t tx_chan_equal: 1; /*1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.*/ + uint32_t tx_big_endian: 1; /*I2S Tx byte endian 1: low addr value to high addr. 0: low addr with low addr value.*/ + uint32_t tx_update: 1; /*Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.*/ + uint32_t tx_mono_fst_vld: 1; /*1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.*/ + uint32_t tx_pcm_conf: 2; /*I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress 1 (ltoa) : A-Law compress 2 (utol) : u-Law decompress 3 (ltou) : u-Law compress. &*/ + uint32_t tx_pcm_bypass: 1; /*Set this bit to bypass Compress/Decompress module for transmitted data.*/ + uint32_t tx_stop_en: 1; /*Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy*/ + uint32_t reserved14: 1; + uint32_t tx_left_align: 1; /*1: I2S TX left alignment mode. 0: I2S TX right alignment mode.*/ + uint32_t tx_24_fill_en: 1; /*1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode*/ + uint32_t tx_ws_idle_pol: 1; /*0: WS should be 0 when sending left channel data and WS is 1in right channel. 1: WS should be 1 when sending left channel data and WS is 0in right channel.*/ + uint32_t tx_bit_order: 1; /*I2S Tx bit endian. 1:small endian the LSB is sent first. 0:big endian the MSB is sent first.*/ + uint32_t tx_tdm_en: 1; /*1: Enable I2S TDM Tx mode . 0: Disable.*/ + uint32_t tx_pdm_en: 1; /*1: Enable I2S PDM Tx mode . 0: Disable.*/ + uint32_t reserved21: 3; /*Reserved*/ + uint32_t tx_chan_mod: 3; /*I2S transmitter channel mode configuration bits.*/ + uint32_t sig_loopback: 1; /*Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } tx_conf; + union { + struct { + uint32_t rx_tdm_ws_width: 7; /*The width of rx_ws_out in TDM mode is (reg_rx_tdm_ws_width[6:0] +1) * T_bck*/ + uint32_t rx_bck_div_num: 6; /*Bit clock configuration bits in receiver mode.*/ + uint32_t rx_bits_mod: 5; /*Set the bits to configure bit length of I2S receiver channel.*/ + uint32_t rx_half_sample_bits: 6; /*I2S Rx half sample bits -1.*/ + uint32_t rx_tdm_chan_bits: 5; /*The Rx bit number for each channel minus 1in TDM mode.*/ + uint32_t rx_msb_shift: 1; /*Set this bit to enable receiver in Phillips standard mode*/ + uint32_t reserved30: 2; /*Reserved*/ + }; + uint32_t val; + } rx_conf1; + union { + struct { + uint32_t tx_tdm_ws_width: 7; /*The width of tx_ws_out in TDM mode is (reg_tx_tdm_ws_width[6:0] +1) * T_bck*/ + uint32_t tx_bck_div_num: 6; /*Bit clock configuration bits in transmitter mode.*/ + uint32_t tx_bits_mod: 5; /*Set the bits to configure bit length of I2S transmitter channel.*/ + uint32_t tx_half_sample_bits: 6; /*I2S Tx half sample bits -1.*/ + uint32_t tx_tdm_chan_bits: 5; /*The Tx bit number for each channel minus 1in TDM mode.*/ + uint32_t tx_msb_shift: 1; /*Set this bit to enable transmitter in Phillips standard mode*/ + uint32_t reserved30: 2; /*Reserved*/ + }; + uint32_t val; + } tx_conf1; + union { + struct { + uint32_t rx_clkm_div_num: 8; /*Integral I2S clock divider value*/ + uint32_t reserved8: 18; /*Reserved*/ + uint32_t rx_clk_active: 1; /*I2S Rx module clock enable signal.*/ + uint32_t rx_clk_sel: 2; /*Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t mclk_sel: 1; /*0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.*/ + uint32_t reserved30: 2; /*Reserved*/ + }; + uint32_t val; + } rx_clkm_conf; + union { + struct { + uint32_t tx_clkm_div_num: 8; /*Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2 z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2 z * [n-div + x * (n+1)-div] + y * (n+1)-div.*/ + uint32_t reserved8: 18; /*Reserved*/ + uint32_t tx_clk_active: 1; /*I2S Tx module clock enable signal.*/ + uint32_t tx_clk_sel: 2; /*Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.*/ + uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ + uint32_t reserved30: 2; /*Reserved*/ + }; + uint32_t val; + } tx_clkm_conf; + union { + struct { + uint32_t rx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_RX_CLKM_DIV_Z is (a-b).*/ + uint32_t rx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).*/ + uint32_t rx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.*/ + uint32_t rx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_RX_CLKM_DIV_YN1 is 1.*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } rx_clkm_div_conf; + union { + struct { + uint32_t tx_clkm_div_z: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2 the value of I2S_TX_CLKM_DIV_Z is (a-b).*/ + uint32_t tx_clkm_div_y: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2 the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).*/ + uint32_t tx_clkm_div_x: 9; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2 the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.*/ + uint32_t tx_clkm_div_yn1: 1; /*For b <= a/2 the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2 the value of I2S_TX_CLKM_DIV_YN1 is 1.*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } tx_clkm_div_conf; + uint32_t reserved_40; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + union { + struct { + uint32_t rx_tdm_chan0_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan1_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan2_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan3_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan4_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan5_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan6_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan7_en: 1; /*1: Enable the valid data input of I2S RX TDM or PDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan8_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan9_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan10_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan11_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan12_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan13_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan14_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_chan15_en: 1; /*1: Enable the valid data input of I2S RX TDM channel $n. 0: Disable just input 0 in this channel.*/ + uint32_t rx_tdm_tot_chan_num: 4; /*The total channel number of I2S TX TDM mode.*/ + uint32_t reserved20: 12; /*Reserved*/ + }; + uint32_t val; + } rx_tdm_ctrl; + union { + struct { + uint32_t tx_tdm_chan0_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan1_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan2_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan3_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan4_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan5_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan6_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan7_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan8_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan9_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan10_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan11_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan12_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan13_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan14_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_chan15_en: 1; /*1: Enable the valid data output of I2S TX TDM channel $n. 0: Disable just output 0 in this channel.*/ + uint32_t tx_tdm_tot_chan_num: 4; /*The total channel number minus 1 of I2S TX TDM mode.*/ + uint32_t tx_tdm_skip_msk_en: 1; /*When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels and only the data of the enabled channels is sent then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.*/ + uint32_t reserved21: 11; /*Reserved*/ + }; + uint32_t val; + } tx_tdm_ctrl; + union { + struct { + uint32_t rx_sd_in_dm: 2; /*The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved2: 2; + uint32_t rx_sd1_in_dm: 2; /*The delay mode of I2S Rx SD1 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved6: 2; + uint32_t rx_sd2_in_dm: 2; /*The delay mode of I2S Rx SD2 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved10: 2; + uint32_t rx_sd3_in_dm: 2; /*The delay mode of I2S Rx SD3 input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved14: 2; + uint32_t rx_ws_out_dm: 2; /*The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved18: 2; + uint32_t rx_bck_out_dm: 2; /*The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved22: 2; + uint32_t rx_ws_in_dm: 2; /*The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved26: 2; + uint32_t rx_bck_in_dm: 2; /*The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved30: 2; + }; + uint32_t val; + } rx_timing; + union { + struct { + uint32_t tx_sd_out_dm: 2; /*The delay mode of I2S Tx SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved2: 14; /*Reserved*/ + uint32_t tx_ws_out_dm: 2; /*The delay mode of I2S Tx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved18: 2; + uint32_t tx_bck_out_dm: 2; /*The delay mode of I2S Tx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved22: 2; + uint32_t tx_ws_in_dm: 2; /*The delay mode of I2S Tx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved26: 2; + uint32_t tx_bck_in_dm: 2; /*The delay mode of I2S Tx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.*/ + uint32_t reserved30: 2; + }; + uint32_t val; + } tx_timing; + union { + struct { + uint32_t fifo_timeout: 8; /*the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value*/ + uint32_t fifo_timeout_shift: 3; /*The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift*/ + uint32_t fifo_timeout_ena: 1; /*The enable bit for FIFO timeout*/ + uint32_t reserved12: 20; /*Reserved*/ + }; + uint32_t val; + } lc_hung_conf; + union { + struct { + uint32_t rx_eof_num: 12; /*the length of data to be received. It will trigger i2s_in_suc_eof_int.*/ + uint32_t reserved12: 20; /*Reserved*/ + }; + uint32_t val; + } rx_eof_num; + uint32_t conf_single_data; /*the right channel or left channel put out constant value stored in this register according to tx_chan_mod and reg_tx_msb_right*/ + union { + struct { + uint32_t tx_idle: 1; /*1: i2s_tx is idle state. 0: i2s_tx is working.*/ + uint32_t reserved1: 31; /*Reserved*/ + }; + uint32_t val; + } state; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + union { + struct { + uint32_t date: 28; /*Version control register*/ + uint32_t reserved28: 4; /*Reserved*/ + }; + uint32_t val; + } date; +} i2s_dev_t; + +extern i2s_dev_t I2S0; +extern i2s_dev_t I2S1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/interrupt_core0_reg.h b/components/soc/soc/esp32s3/include/soc/interrupt_core0_reg.h new file mode 100644 index 000000000..ab335cf3c --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/interrupt_core0_reg.h @@ -0,0 +1,784 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define INTERRUPT_CORE0_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x000) +/* INTERRUPT_CORE0_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_INTR_MAP_M ((INTERRUPT_CORE0_MAC_INTR_MAP_V) << (INTERRUPT_CORE0_MAC_INTR_MAP_S)) +#define INTERRUPT_CORE0_MAC_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x004) +/* INTERRUPT_CORE0_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_MAC_NMI_MAP_M ((INTERRUPT_CORE0_MAC_NMI_MAP_V) << (INTERRUPT_CORE0_MAC_NMI_MAP_S)) +#define INTERRUPT_CORE0_MAC_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_MAC_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x008) +/* INTERRUPT_CORE0_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWR_INTR_MAP_M ((INTERRUPT_CORE0_PWR_INTR_MAP_V) << (INTERRUPT_CORE0_PWR_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWR_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWR_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x00C) +/* INTERRUPT_CORE0_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BB_INT_MAP_M ((INTERRUPT_CORE0_BB_INT_MAP_V) << (INTERRUPT_CORE0_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x010) +/* INTERRUPT_CORE0_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_M ((INTERRUPT_CORE0_BT_MAC_INT_MAP_V) << (INTERRUPT_CORE0_BT_MAC_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_MAC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x014) +/* INTERRUPT_CORE0_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_M ((INTERRUPT_CORE0_BT_BB_INT_MAP_V) << (INTERRUPT_CORE0_BT_BB_INT_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x018) +/* INTERRUPT_CORE0_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_M ((INTERRUPT_CORE0_BT_BB_NMI_MAP_V) << (INTERRUPT_CORE0_BT_BB_NMI_MAP_S)) +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_BT_BB_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x01C) +/* INTERRUPT_CORE0_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_M ((INTERRUPT_CORE0_RWBT_IRQ_MAP_V) << (INTERRUPT_CORE0_RWBT_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_IRQ_MAP_S 0 + +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x020) +/* INTERRUPT_CORE0_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE0_RWBLE_IRQ_MAP_V) << (INTERRUPT_CORE0_RWBLE_IRQ_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_IRQ_MAP_S 0 + +#define INTERRUPT_CORE0_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x024) +/* INTERRUPT_CORE0_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_M ((INTERRUPT_CORE0_RWBT_NMI_MAP_V) << (INTERRUPT_CORE0_RWBT_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBT_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBT_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x028) +/* INTERRUPT_CORE0_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_M ((INTERRUPT_CORE0_RWBLE_NMI_MAP_V) << (INTERRUPT_CORE0_RWBLE_NMI_MAP_S)) +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_RWBLE_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x02C) +/* INTERRUPT_CORE0_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2C_MST_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_M ((INTERRUPT_CORE0_I2C_MST_INT_MAP_V) << (INTERRUPT_CORE0_I2C_MST_INT_MAP_S)) +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_MST_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x030) +/* INTERRUPT_CORE0_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_M ((INTERRUPT_CORE0_SLC0_INTR_MAP_V) << (INTERRUPT_CORE0_SLC0_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x034) +/* INTERRUPT_CORE0_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_M ((INTERRUPT_CORE0_SLC1_INTR_MAP_V) << (INTERRUPT_CORE0_SLC1_INTR_MAP_S)) +#define INTERRUPT_CORE0_SLC1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SLC1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x038) +/* INTERRUPT_CORE0_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_M ((INTERRUPT_CORE0_UHCI0_INTR_MAP_V) << (INTERRUPT_CORE0_UHCI0_INTR_MAP_S)) +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UHCI0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x03C) +/* INTERRUPT_CORE0_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_UHCI1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_M ((INTERRUPT_CORE0_UHCI1_INTR_MAP_V) << (INTERRUPT_CORE0_UHCI1_INTR_MAP_S)) +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UHCI1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x040) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x044) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x048) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_MAP_S 0 + +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x04C) +/* INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V) << (INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define INTERRUPT_CORE0_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x050) +/* INTERRUPT_CORE0_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_M ((INTERRUPT_CORE0_SPI_INTR_1_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_1_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_1_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x054) +/* INTERRUPT_CORE0_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_M ((INTERRUPT_CORE0_SPI_INTR_2_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_2_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_2_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x058) +/* INTERRUPT_CORE0_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_INTR_3_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_M ((INTERRUPT_CORE0_SPI_INTR_3_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_3_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_3_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x05C) +/* INTERRUPT_CORE0_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_INTR_4_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_M ((INTERRUPT_CORE0_SPI_INTR_4_MAP_V) << (INTERRUPT_CORE0_SPI_INTR_4_MAP_S)) +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_INTR_4_MAP_S 0 + +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x060) +/* INTERRUPT_CORE0_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE0_LCD_CAM_INT_MAP_V) << (INTERRUPT_CORE0_LCD_CAM_INT_MAP_S)) +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_LCD_CAM_INT_MAP_S 0 + +#define INTERRUPT_CORE0_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x064) +/* INTERRUPT_CORE0_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2S0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2S0_INT_MAP_M ((INTERRUPT_CORE0_I2S0_INT_MAP_V) << (INTERRUPT_CORE0_I2S0_INT_MAP_S)) +#define INTERRUPT_CORE0_I2S0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2S0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x068) +/* INTERRUPT_CORE0_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_I2S1_INT_MAP_M ((INTERRUPT_CORE0_I2S1_INT_MAP_V) << (INTERRUPT_CORE0_I2S1_INT_MAP_S)) +#define INTERRUPT_CORE0_I2S1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_I2S1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x06C) +/* INTERRUPT_CORE0_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_UART_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART_INTR_MAP_M ((INTERRUPT_CORE0_UART_INTR_MAP_V) << (INTERRUPT_CORE0_UART_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x070) +/* INTERRUPT_CORE0_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART1_INTR_MAP_M ((INTERRUPT_CORE0_UART1_INTR_MAP_V) << (INTERRUPT_CORE0_UART1_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x074) +/* INTERRUPT_CORE0_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_UART2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_UART2_INTR_MAP_M ((INTERRUPT_CORE0_UART2_INTR_MAP_V) << (INTERRUPT_CORE0_UART2_INTR_MAP_S)) +#define INTERRUPT_CORE0_UART2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_UART2_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x078) +/* INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V) << (INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S)) +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define INTERRUPT_CORE0_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define INTERRUPT_CORE0_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x07C) +/* INTERRUPT_CORE0_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_PWM0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM0_INTR_MAP_M ((INTERRUPT_CORE0_PWM0_INTR_MAP_V) << (INTERRUPT_CORE0_PWM0_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x080) +/* INTERRUPT_CORE0_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_PWM1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM1_INTR_MAP_M ((INTERRUPT_CORE0_PWM1_INTR_MAP_V) << (INTERRUPT_CORE0_PWM1_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x084) +/* INTERRUPT_CORE0_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_PWM2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM2_INTR_MAP_M ((INTERRUPT_CORE0_PWM2_INTR_MAP_V) << (INTERRUPT_CORE0_PWM2_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM2_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x088) +/* INTERRUPT_CORE0_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_PWM3_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PWM3_INTR_MAP_M ((INTERRUPT_CORE0_PWM3_INTR_MAP_V) << (INTERRUPT_CORE0_PWM3_INTR_MAP_S)) +#define INTERRUPT_CORE0_PWM3_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PWM3_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x08C) +/* INTERRUPT_CORE0_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_LEDC_INT_MAP_M ((INTERRUPT_CORE0_LEDC_INT_MAP_V) << (INTERRUPT_CORE0_LEDC_INT_MAP_S)) +#define INTERRUPT_CORE0_LEDC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_LEDC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x090) +/* INTERRUPT_CORE0_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_M ((INTERRUPT_CORE0_EFUSE_INT_MAP_V) << (INTERRUPT_CORE0_EFUSE_INT_MAP_S)) +#define INTERRUPT_CORE0_EFUSE_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_EFUSE_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x094) +/* INTERRUPT_CORE0_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TWAI_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TWAI_INT_MAP_M ((INTERRUPT_CORE0_TWAI_INT_MAP_V) << (INTERRUPT_CORE0_TWAI_INT_MAP_S)) +#define INTERRUPT_CORE0_TWAI_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TWAI_INT_MAP_S 0 + +#define INTERRUPT_CORE0_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x098) +/* INTERRUPT_CORE0_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_USB_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_USB_INTR_MAP_M ((INTERRUPT_CORE0_USB_INTR_MAP_V) << (INTERRUPT_CORE0_USB_INTR_MAP_S)) +#define INTERRUPT_CORE0_USB_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_USB_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x09C) +/* INTERRUPT_CORE0_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V) << (INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S)) +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RTC_CORE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A0) +/* INTERRUPT_CORE0_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_RMT_INTR_MAP_M ((INTERRUPT_CORE0_RMT_INTR_MAP_V) << (INTERRUPT_CORE0_RMT_INTR_MAP_S)) +#define INTERRUPT_CORE0_RMT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_RMT_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A4) +/* INTERRUPT_CORE0_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_PCNT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_PCNT_INTR_MAP_M ((INTERRUPT_CORE0_PCNT_INTR_MAP_V) << (INTERRUPT_CORE0_PCNT_INTR_MAP_S)) +#define INTERRUPT_CORE0_PCNT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_PCNT_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0A8) +/* INTERRUPT_CORE0_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V) << (INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S)) +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_EXT0_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0AC) +/* INTERRUPT_CORE0_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V) << (INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S)) +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_I2C_EXT1_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B0) +/* INTERRUPT_CORE0_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S)) +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI2_DMA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B4) +/* INTERRUPT_CORE0_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S)) +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI3_DMA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0B8) +/* INTERRUPT_CORE0_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V) << (INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S)) +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI4_DMA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0BC) +/* INTERRUPT_CORE0_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_WDG_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_WDG_INT_MAP_M ((INTERRUPT_CORE0_WDG_INT_MAP_V) << (INTERRUPT_CORE0_WDG_INT_MAP_S)) +#define INTERRUPT_CORE0_WDG_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_WDG_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C0) +/* INTERRUPT_CORE0_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_M ((INTERRUPT_CORE0_TIMER_INT1_MAP_V) << (INTERRUPT_CORE0_TIMER_INT1_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT1_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT1_MAP_S 0 + +#define INTERRUPT_CORE0_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C4) +/* INTERRUPT_CORE0_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_M ((INTERRUPT_CORE0_TIMER_INT2_MAP_V) << (INTERRUPT_CORE0_TIMER_INT2_MAP_S)) +#define INTERRUPT_CORE0_TIMER_INT2_MAP_V 0x1F +#define INTERRUPT_CORE0_TIMER_INT2_MAP_S 0 + +#define INTERRUPT_CORE0_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0C8) +/* INTERRUPT_CORE0_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_M ((INTERRUPT_CORE0_TG_T0_INT_MAP_V) << (INTERRUPT_CORE0_TG_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0CC) +/* INTERRUPT_CORE0_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_T1_INT_MAP_M ((INTERRUPT_CORE0_TG_T1_INT_MAP_V) << (INTERRUPT_CORE0_TG_T1_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_T1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D0) +/* INTERRUPT_CORE0_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG_WDT_INT_MAP_V) << (INTERRUPT_CORE0_TG_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D4) +/* INTERRUPT_CORE0_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG1_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_M ((INTERRUPT_CORE0_TG1_T0_INT_MAP_V) << (INTERRUPT_CORE0_TG1_T0_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0D8) +/* INTERRUPT_CORE0_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG1_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_M ((INTERRUPT_CORE0_TG1_T1_INT_MAP_V) << (INTERRUPT_CORE0_TG1_T1_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_T1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0DC) +/* INTERRUPT_CORE0_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE0_TG1_WDT_INT_MAP_V) << (INTERRUPT_CORE0_TG1_WDT_INT_MAP_S)) +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_TG1_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E0) +/* INTERRUPT_CORE0_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE0_CACHE_IA_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_IA_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_IA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E4) +/* INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0E8) +/* INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0EC) +/* INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V) << (INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S)) +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SYSTIMER_TARGET2_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F0) +/* INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V) << (INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S)) +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_SPI_MEM_REJECT_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F4) +/* INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DCACHE_PRELOAD_INT_MAP_S 0 + +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0F8) +/* INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_PRELOAD_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x0FC) +/* INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DCACHE_SYNC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x100) +/* INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_ICACHE_SYNC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x104) +/* INTERRUPT_CORE0_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_M ((INTERRUPT_CORE0_APB_ADC_INT_MAP_V) << (INTERRUPT_CORE0_APB_ADC_INT_MAP_S)) +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_APB_ADC_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x108) +/* INTERRUPT_CORE0_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH0_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH0_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x10C) +/* INTERRUPT_CORE0_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH1_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH1_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x110) +/* INTERRUPT_CORE0_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH2_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH2_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x114) +/* INTERRUPT_CORE0_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH3_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH3_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH3_INT_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x118) +/* INTERRUPT_CORE0_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_CH4_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE0_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE0_DMA_CH4_INT_MAP_S)) +#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_CH4_INT_MAP_S 0 + +#define INTERRUPT_CORE0_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x11C) +/* INTERRUPT_CORE0_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_RSA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_RSA_INT_MAP_M ((INTERRUPT_CORE0_RSA_INT_MAP_V) << (INTERRUPT_CORE0_RSA_INT_MAP_S)) +#define INTERRUPT_CORE0_RSA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_RSA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x120) +/* INTERRUPT_CORE0_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_AES_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_AES_INT_MAP_M ((INTERRUPT_CORE0_AES_INT_MAP_V) << (INTERRUPT_CORE0_AES_INT_MAP_S)) +#define INTERRUPT_CORE0_AES_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_AES_INT_MAP_S 0 + +#define INTERRUPT_CORE0_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x124) +/* INTERRUPT_CORE0_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_SHA_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_SHA_INT_MAP_M ((INTERRUPT_CORE0_SHA_INT_MAP_V) << (INTERRUPT_CORE0_SHA_INT_MAP_S)) +#define INTERRUPT_CORE0_SHA_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_SHA_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x128) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x12C) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x130) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x134) +/* INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V) << (INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S)) +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define INTERRUPT_CORE0_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x138) +/* INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V) << (INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S)) +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_ASSIST_DEBUG_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x13C) +/* INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x140) +/* INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x144) +/* INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x148) +/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x14C) +/* INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x150) +/* INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x154) +/* INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x158) +/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x15C) +/* INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE0_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x160) +/* INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_CORE0_ACS_INT_MAP_S 0 + +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x164) +/* INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V) << (INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S)) +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE0_CACHE_CORE1_ACS_INT_MAP_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x168) +/* INTERRUPT_CORE0_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_M ((INTERRUPT_CORE0_INTR_STATUS_0_V) << (INTERRUPT_CORE0_INTR_STATUS_0_S)) +#define INTERRUPT_CORE0_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_0_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x16C) +/* INTERRUPT_CORE0_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_M ((INTERRUPT_CORE0_INTR_STATUS_1_V) << (INTERRUPT_CORE0_INTR_STATUS_1_S)) +#define INTERRUPT_CORE0_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_1_S 0 + +#define INTERRUPT_CORE0_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x170) +/* INTERRUPT_CORE0_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_M ((INTERRUPT_CORE0_INTR_STATUS_2_V) << (INTERRUPT_CORE0_INTR_STATUS_2_S)) +#define INTERRUPT_CORE0_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_CORE0_INTR_STATUS_2_S 0 + +#define INTERRUPT_CORE0_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x174) +/* INTERRUPT_CORE0_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define INTERRUPT_CORE0_CLK_EN (BIT(0)) +#define INTERRUPT_CORE0_CLK_EN_M (BIT(0)) +#define INTERRUPT_CORE0_CLK_EN_V 0x1 +#define INTERRUPT_CORE0_CLK_EN_S 0 + +#define INTERRUPT_CORE0_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE0_BASE + 0x7FC) +/* INTERRUPT_CORE0_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ +/*description: */ +#define INTERRUPT_CORE0_INTERRUPT_DATE 0x0FFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_M ((INTERRUPT_CORE0_INTERRUPT_DATE_V) << (INTERRUPT_CORE0_INTERRUPT_DATE_S)) +#define INTERRUPT_CORE0_INTERRUPT_DATE_V 0xFFFFFFF +#define INTERRUPT_CORE0_INTERRUPT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/interrupt_core0_struct.h b/components/soc/soc/esp32s3/include/soc/interrupt_core0_struct.h new file mode 100644 index 000000000..94d7661f0 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/interrupt_core0_struct.h @@ -0,0 +1,1093 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t core0_mac_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_mac_intr_map; + union { + struct { + uint32_t core0_mac_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_mac_nmi_map; + union { + struct { + uint32_t core0_pwr_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_pwr_intr_map; + union { + struct { + uint32_t core0_bb_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_bb_int_map; + union { + struct { + uint32_t core0_bt_mac_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_bt_mac_int_map; + union { + struct { + uint32_t core0_bt_bb_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_bt_bb_int_map; + union { + struct { + uint32_t core0_bt_bb_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_bt_bb_nmi_map; + union { + struct { + uint32_t core0_rwbt_irq_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_rwbt_irq_map; + union { + struct { + uint32_t core0_rwble_irq_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_rwble_irq_map; + union { + struct { + uint32_t core0_rwbt_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_rwbt_nmi_map; + union { + struct { + uint32_t core0_rwble_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_rwble_nmi_map; + union { + struct { + uint32_t core0_i2c_mst_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_i2c_mst_int_map; + union { + struct { + uint32_t core0_slc0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_slc0_intr_map; + union { + struct { + uint32_t core0_slc1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_slc1_intr_map; + union { + struct { + uint32_t core0_uhci0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_uhci0_intr_map; + union { + struct { + uint32_t core0_uhci1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_uhci1_intr_map; + union { + struct { + uint32_t core0_gpio_interrupt_pro_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_gpio_interrupt_pro_map; + union { + struct { + uint32_t core0_gpio_interrupt_pro_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_gpio_interrupt_pro_nmi_map; + union { + struct { + uint32_t core0_gpio_interrupt_app_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_gpio_interrupt_app_map; + union { + struct { + uint32_t core0_gpio_interrupt_app_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_gpio_interrupt_app_nmi_map; + union { + struct { + uint32_t core0_spi_intr_1_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi_intr_1_map; + union { + struct { + uint32_t core0_spi_intr_2_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi_intr_2_map; + union { + struct { + uint32_t core0_spi_intr_3_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi_intr_3_map; + union { + struct { + uint32_t core0_spi_intr_4_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi_intr_4_map; + union { + struct { + uint32_t core0_lcd_cam_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_lcd_cam_int_map; + union { + struct { + uint32_t core0_i2s0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_i2s0_int_map; + union { + struct { + uint32_t core0_i2s1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_i2s1_int_map; + union { + struct { + uint32_t core0_uart_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_uart_intr_map; + union { + struct { + uint32_t core0_uart1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_uart1_intr_map; + union { + struct { + uint32_t core0_uart2_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_uart2_intr_map; + union { + struct { + uint32_t core0_sdio_host_interrupt_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_sdio_host_interrupt_map; + union { + struct { + uint32_t core0_pwm0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_pwm0_intr_map; + union { + struct { + uint32_t core0_pwm1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_pwm1_intr_map; + union { + struct { + uint32_t core0_pwm2_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_pwm2_intr_map; + union { + struct { + uint32_t core0_pwm3_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_pwm3_intr_map; + union { + struct { + uint32_t core0_ledc_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_ledc_int_map; + union { + struct { + uint32_t core0_efuse_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_efuse_int_map; + union { + struct { + uint32_t core0_can_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_can_int_map; + union { + struct { + uint32_t core0_usb_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_usb_intr_map; + union { + struct { + uint32_t core0_rtc_core_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_rtc_core_intr_map; + union { + struct { + uint32_t core0_rmt_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_rmt_intr_map; + union { + struct { + uint32_t core0_pcnt_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_pcnt_intr_map; + union { + struct { + uint32_t core0_i2c_ext0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_i2c_ext0_intr_map; + union { + struct { + uint32_t core0_i2c_ext1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_i2c_ext1_intr_map; + union { + struct { + uint32_t core0_spi2_dma_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi2_dma_int_map; + union { + struct { + uint32_t core0_spi3_dma_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi3_dma_int_map; + union { + struct { + uint32_t core0_spi4_dma_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi4_dma_int_map; + union { + struct { + uint32_t core0_wdg_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_wdg_int_map; + union { + struct { + uint32_t core0_timer_int1_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_timer_int1_map; + union { + struct { + uint32_t core0_timer_int2_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_timer_int2_map; + union { + struct { + uint32_t core0_tg_t0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_tg_t0_int_map; + union { + struct { + uint32_t core0_tg_t1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_tg_t1_int_map; + union { + struct { + uint32_t core0_tg_wdt_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_tg_wdt_int_map; + union { + struct { + uint32_t core0_tg1_t0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_tg1_t0_int_map; + union { + struct { + uint32_t core0_tg1_t1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_tg1_t1_int_map; + union { + struct { + uint32_t core0_tg1_wdt_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_tg1_wdt_int_map; + union { + struct { + uint32_t core0_cache_ia_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_cache_ia_int_map; + union { + struct { + uint32_t core0_systimer_target0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_systimer_target0_int_map; + union { + struct { + uint32_t core0_systimer_target1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_systimer_target1_int_map; + union { + struct { + uint32_t core0_systimer_target2_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_systimer_target2_int_map; + union { + struct { + uint32_t core0_spi_mem_reject_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_spi_mem_reject_intr_map; + union { + struct { + uint32_t core0_dcache_preload_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dcache_preload_int_map; + union { + struct { + uint32_t core0_icache_preload_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_icache_preload_int_map; + union { + struct { + uint32_t core0_dcache_sync_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dcache_sync_int_map; + union { + struct { + uint32_t core0_icache_sync_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_icache_sync_int_map; + union { + struct { + uint32_t core0_apb_adc_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_apb_adc_int_map; + union { + struct { + uint32_t core0_dma_ch0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_ch0_int_map; + union { + struct { + uint32_t core0_dma_ch1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_ch1_int_map; + union { + struct { + uint32_t core0_dma_ch2_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_ch2_int_map; + union { + struct { + uint32_t core0_dma_ch3_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_ch3_int_map; + union { + struct { + uint32_t core0_dma_ch4_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_ch4_int_map; + union { + struct { + uint32_t core0_rsa_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_rsa_int_map; + union { + struct { + uint32_t core0_aes_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_aes_int_map; + union { + struct { + uint32_t core0_sha_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_sha_int_map; + union { + struct { + uint32_t core0_cpu_intr_from_cpu_0_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_cpu_intr_from_cpu_0_map; + union { + struct { + uint32_t core0_cpu_intr_from_cpu_1_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_cpu_intr_from_cpu_1_map; + union { + struct { + uint32_t core0_cpu_intr_from_cpu_2_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_cpu_intr_from_cpu_2_map; + union { + struct { + uint32_t core0_cpu_intr_from_cpu_3_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_cpu_intr_from_cpu_3_map; + union { + struct { + uint32_t core0_assist_debug_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_assist_debug_intr_map; + union { + struct { + uint32_t core0_dma_apbperi_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_dma_apbperi_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core0_core_0_iram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_0_iram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core0_core_0_dram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_0_dram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core0_core_0_pif_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_0_pif_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core0_core_0_pif_pms_monitor_violate_size_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_0_pif_pms_monitor_violate_size_intr_map; + union { + struct { + uint32_t core0_core_1_iram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_1_iram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core0_core_1_dram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_1_dram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core0_core_1_pif_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_1_pif_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core0_core_1_pif_pms_monitor_violate_size_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_core_1_pif_pms_monitor_violate_size_intr_map; + union { + struct { + uint32_t core0_cache_core0_acs_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_cache_core0_acs_int_map; + union { + struct { + uint32_t core0_cache_core1_acs_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core0_cache_core1_acs_int_map; + uint32_t core0_intr_status_0; /**/ + uint32_t core0_intr_status_1; /**/ + uint32_t core0_intr_status_2; /**/ + union { + struct { + uint32_t core0_clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core0_clock_gate; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t reserved_3fc; + uint32_t reserved_400; + uint32_t reserved_404; + uint32_t reserved_408; + uint32_t reserved_40c; + uint32_t reserved_410; + uint32_t reserved_414; + uint32_t reserved_418; + uint32_t reserved_41c; + uint32_t reserved_420; + uint32_t reserved_424; + uint32_t reserved_428; + uint32_t reserved_42c; + uint32_t reserved_430; + uint32_t reserved_434; + uint32_t reserved_438; + uint32_t reserved_43c; + uint32_t reserved_440; + uint32_t reserved_444; + uint32_t reserved_448; + uint32_t reserved_44c; + uint32_t reserved_450; + uint32_t reserved_454; + uint32_t reserved_458; + uint32_t reserved_45c; + uint32_t reserved_460; + uint32_t reserved_464; + uint32_t reserved_468; + uint32_t reserved_46c; + uint32_t reserved_470; + uint32_t reserved_474; + uint32_t reserved_478; + uint32_t reserved_47c; + uint32_t reserved_480; + uint32_t reserved_484; + uint32_t reserved_488; + uint32_t reserved_48c; + uint32_t reserved_490; + uint32_t reserved_494; + uint32_t reserved_498; + uint32_t reserved_49c; + uint32_t reserved_4a0; + uint32_t reserved_4a4; + uint32_t reserved_4a8; + uint32_t reserved_4ac; + uint32_t reserved_4b0; + uint32_t reserved_4b4; + uint32_t reserved_4b8; + uint32_t reserved_4bc; + uint32_t reserved_4c0; + uint32_t reserved_4c4; + uint32_t reserved_4c8; + uint32_t reserved_4cc; + uint32_t reserved_4d0; + uint32_t reserved_4d4; + uint32_t reserved_4d8; + uint32_t reserved_4dc; + uint32_t reserved_4e0; + uint32_t reserved_4e4; + uint32_t reserved_4e8; + uint32_t reserved_4ec; + uint32_t reserved_4f0; + uint32_t reserved_4f4; + uint32_t reserved_4f8; + uint32_t reserved_4fc; + uint32_t reserved_500; + uint32_t reserved_504; + uint32_t reserved_508; + uint32_t reserved_50c; + uint32_t reserved_510; + uint32_t reserved_514; + uint32_t reserved_518; + uint32_t reserved_51c; + uint32_t reserved_520; + uint32_t reserved_524; + uint32_t reserved_528; + uint32_t reserved_52c; + uint32_t reserved_530; + uint32_t reserved_534; + uint32_t reserved_538; + uint32_t reserved_53c; + uint32_t reserved_540; + uint32_t reserved_544; + uint32_t reserved_548; + uint32_t reserved_54c; + uint32_t reserved_550; + uint32_t reserved_554; + uint32_t reserved_558; + uint32_t reserved_55c; + uint32_t reserved_560; + uint32_t reserved_564; + uint32_t reserved_568; + uint32_t reserved_56c; + uint32_t reserved_570; + uint32_t reserved_574; + uint32_t reserved_578; + uint32_t reserved_57c; + uint32_t reserved_580; + uint32_t reserved_584; + uint32_t reserved_588; + uint32_t reserved_58c; + uint32_t reserved_590; + uint32_t reserved_594; + uint32_t reserved_598; + uint32_t reserved_59c; + uint32_t reserved_5a0; + uint32_t reserved_5a4; + uint32_t reserved_5a8; + uint32_t reserved_5ac; + uint32_t reserved_5b0; + uint32_t reserved_5b4; + uint32_t reserved_5b8; + uint32_t reserved_5bc; + uint32_t reserved_5c0; + uint32_t reserved_5c4; + uint32_t reserved_5c8; + uint32_t reserved_5cc; + uint32_t reserved_5d0; + uint32_t reserved_5d4; + uint32_t reserved_5d8; + uint32_t reserved_5dc; + uint32_t reserved_5e0; + uint32_t reserved_5e4; + uint32_t reserved_5e8; + uint32_t reserved_5ec; + uint32_t reserved_5f0; + uint32_t reserved_5f4; + uint32_t reserved_5f8; + uint32_t reserved_5fc; + uint32_t reserved_600; + uint32_t reserved_604; + uint32_t reserved_608; + uint32_t reserved_60c; + uint32_t reserved_610; + uint32_t reserved_614; + uint32_t reserved_618; + uint32_t reserved_61c; + uint32_t reserved_620; + uint32_t reserved_624; + uint32_t reserved_628; + uint32_t reserved_62c; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + uint32_t reserved_6fc; + uint32_t reserved_700; + uint32_t reserved_704; + uint32_t reserved_708; + uint32_t reserved_70c; + uint32_t reserved_710; + uint32_t reserved_714; + uint32_t reserved_718; + uint32_t reserved_71c; + uint32_t reserved_720; + uint32_t reserved_724; + uint32_t reserved_728; + uint32_t reserved_72c; + uint32_t reserved_730; + uint32_t reserved_734; + uint32_t reserved_738; + uint32_t reserved_73c; + uint32_t reserved_740; + uint32_t reserved_744; + uint32_t reserved_748; + uint32_t reserved_74c; + uint32_t reserved_750; + uint32_t reserved_754; + uint32_t reserved_758; + uint32_t reserved_75c; + uint32_t reserved_760; + uint32_t reserved_764; + uint32_t reserved_768; + uint32_t reserved_76c; + uint32_t reserved_770; + uint32_t reserved_774; + uint32_t reserved_778; + uint32_t reserved_77c; + uint32_t reserved_780; + uint32_t reserved_784; + uint32_t reserved_788; + uint32_t reserved_78c; + uint32_t reserved_790; + uint32_t reserved_794; + uint32_t reserved_798; + uint32_t reserved_79c; + uint32_t reserved_7a0; + uint32_t reserved_7a4; + uint32_t reserved_7a8; + uint32_t reserved_7ac; + uint32_t reserved_7b0; + uint32_t reserved_7b4; + uint32_t reserved_7b8; + uint32_t reserved_7bc; + uint32_t reserved_7c0; + uint32_t reserved_7c4; + uint32_t reserved_7c8; + uint32_t reserved_7cc; + uint32_t reserved_7d0; + uint32_t reserved_7d4; + uint32_t reserved_7d8; + uint32_t reserved_7dc; + uint32_t reserved_7e0; + uint32_t reserved_7e4; + uint32_t reserved_7e8; + uint32_t reserved_7ec; + uint32_t reserved_7f0; + uint32_t reserved_7f4; + uint32_t reserved_7f8; + union { + struct { + uint32_t core0_interrupt_date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } core0_interrupt_date; +} interrupt_core0_dev_t; + +extern interrupt_core0_dev_t INTERRUPT_CORE0; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/interrupt_core1_reg.h b/components/soc/soc/esp32s3/include/soc/interrupt_core1_reg.h new file mode 100644 index 000000000..9c223d3f3 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/interrupt_core1_reg.h @@ -0,0 +1,784 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define INTERRUPT_CORE1_MAC_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x800) +/* INTERRUPT_CORE1_MAC_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_MAC_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_MAC_INTR_MAP_M ((INTERRUPT_CORE1_MAC_INTR_MAP_V) << (INTERRUPT_CORE1_MAC_INTR_MAP_S)) +#define INTERRUPT_CORE1_MAC_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_MAC_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_MAC_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x804) +/* INTERRUPT_CORE1_MAC_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_MAC_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_MAC_NMI_MAP_M ((INTERRUPT_CORE1_MAC_NMI_MAP_V) << (INTERRUPT_CORE1_MAC_NMI_MAP_S)) +#define INTERRUPT_CORE1_MAC_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_MAC_NMI_MAP_S 0 + +#define INTERRUPT_CORE1_PWR_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x808) +/* INTERRUPT_CORE1_PWR_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_PWR_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWR_INTR_MAP_M ((INTERRUPT_CORE1_PWR_INTR_MAP_V) << (INTERRUPT_CORE1_PWR_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWR_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWR_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x80C) +/* INTERRUPT_CORE1_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_BB_INT_MAP_M ((INTERRUPT_CORE1_BB_INT_MAP_V) << (INTERRUPT_CORE1_BB_INT_MAP_S)) +#define INTERRUPT_CORE1_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x810) +/* INTERRUPT_CORE1_BT_MAC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_BT_MAC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_M ((INTERRUPT_CORE1_BT_MAC_INT_MAP_V) << (INTERRUPT_CORE1_BT_MAC_INT_MAP_S)) +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_BT_MAC_INT_MAP_S 0 + +#define INTERRUPT_CORE1_BT_BB_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x814) +/* INTERRUPT_CORE1_BT_BB_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_BT_BB_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_BT_BB_INT_MAP_M ((INTERRUPT_CORE1_BT_BB_INT_MAP_V) << (INTERRUPT_CORE1_BT_BB_INT_MAP_S)) +#define INTERRUPT_CORE1_BT_BB_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_BT_BB_INT_MAP_S 0 + +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x818) +/* INTERRUPT_CORE1_BT_BB_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_BT_BB_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_M ((INTERRUPT_CORE1_BT_BB_NMI_MAP_V) << (INTERRUPT_CORE1_BT_BB_NMI_MAP_S)) +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_BT_BB_NMI_MAP_S 0 + +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x81C) +/* INTERRUPT_CORE1_RWBT_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_RWBT_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_M ((INTERRUPT_CORE1_RWBT_IRQ_MAP_V) << (INTERRUPT_CORE1_RWBT_IRQ_MAP_S)) +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBT_IRQ_MAP_S 0 + +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x820) +/* INTERRUPT_CORE1_RWBLE_IRQ_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_M ((INTERRUPT_CORE1_RWBLE_IRQ_MAP_V) << (INTERRUPT_CORE1_RWBLE_IRQ_MAP_S)) +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBLE_IRQ_MAP_S 0 + +#define INTERRUPT_CORE1_RWBT_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x824) +/* INTERRUPT_CORE1_RWBT_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_RWBT_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBT_NMI_MAP_M ((INTERRUPT_CORE1_RWBT_NMI_MAP_V) << (INTERRUPT_CORE1_RWBT_NMI_MAP_S)) +#define INTERRUPT_CORE1_RWBT_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBT_NMI_MAP_S 0 + +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x828) +/* INTERRUPT_CORE1_RWBLE_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_RWBLE_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_M ((INTERRUPT_CORE1_RWBLE_NMI_MAP_V) << (INTERRUPT_CORE1_RWBLE_NMI_MAP_S)) +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_RWBLE_NMI_MAP_S 0 + +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x82C) +/* INTERRUPT_CORE1_I2C_MST_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_I2C_MST_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_M ((INTERRUPT_CORE1_I2C_MST_INT_MAP_V) << (INTERRUPT_CORE1_I2C_MST_INT_MAP_S)) +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_I2C_MST_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SLC0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x830) +/* INTERRUPT_CORE1_SLC0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SLC0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_SLC0_INTR_MAP_M ((INTERRUPT_CORE1_SLC0_INTR_MAP_V) << (INTERRUPT_CORE1_SLC0_INTR_MAP_S)) +#define INTERRUPT_CORE1_SLC0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_SLC0_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_SLC1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x834) +/* INTERRUPT_CORE1_SLC1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SLC1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_SLC1_INTR_MAP_M ((INTERRUPT_CORE1_SLC1_INTR_MAP_V) << (INTERRUPT_CORE1_SLC1_INTR_MAP_S)) +#define INTERRUPT_CORE1_SLC1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_SLC1_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x838) +/* INTERRUPT_CORE1_UHCI0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_UHCI0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_M ((INTERRUPT_CORE1_UHCI0_INTR_MAP_V) << (INTERRUPT_CORE1_UHCI0_INTR_MAP_S)) +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UHCI0_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x83C) +/* INTERRUPT_CORE1_UHCI1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_UHCI1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_M ((INTERRUPT_CORE1_UHCI1_INTR_MAP_V) << (INTERRUPT_CORE1_UHCI1_INTR_MAP_S)) +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UHCI1_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x840) +/* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_MAP_S 0 + +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x844) +/* INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_PRO_NMI_MAP_S 0 + +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x848) +/* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_MAP_S 0 + +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x84C) +/* INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP 0x0000001F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_M ((INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V) << (INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S)) +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_V 0x1F +#define INTERRUPT_CORE1_GPIO_INTERRUPT_APP_NMI_MAP_S 0 + +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x850) +/* INTERRUPT_CORE1_SPI_INTR_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI_INTR_1_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_M ((INTERRUPT_CORE1_SPI_INTR_1_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_1_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_1_MAP_S 0 + +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x854) +/* INTERRUPT_CORE1_SPI_INTR_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI_INTR_2_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_M ((INTERRUPT_CORE1_SPI_INTR_2_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_2_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_2_MAP_S 0 + +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x858) +/* INTERRUPT_CORE1_SPI_INTR_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI_INTR_3_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_M ((INTERRUPT_CORE1_SPI_INTR_3_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_3_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_3_MAP_S 0 + +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x85C) +/* INTERRUPT_CORE1_SPI_INTR_4_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI_INTR_4_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_M ((INTERRUPT_CORE1_SPI_INTR_4_MAP_V) << (INTERRUPT_CORE1_SPI_INTR_4_MAP_S)) +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_INTR_4_MAP_S 0 + +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x860) +/* INTERRUPT_CORE1_LCD_CAM_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_M ((INTERRUPT_CORE1_LCD_CAM_INT_MAP_V) << (INTERRUPT_CORE1_LCD_CAM_INT_MAP_S)) +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_LCD_CAM_INT_MAP_S 0 + +#define INTERRUPT_CORE1_I2S0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x864) +/* INTERRUPT_CORE1_I2S0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_I2S0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_I2S0_INT_MAP_M ((INTERRUPT_CORE1_I2S0_INT_MAP_V) << (INTERRUPT_CORE1_I2S0_INT_MAP_S)) +#define INTERRUPT_CORE1_I2S0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_I2S0_INT_MAP_S 0 + +#define INTERRUPT_CORE1_I2S1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x868) +/* INTERRUPT_CORE1_I2S1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_I2S1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_I2S1_INT_MAP_M ((INTERRUPT_CORE1_I2S1_INT_MAP_V) << (INTERRUPT_CORE1_I2S1_INT_MAP_S)) +#define INTERRUPT_CORE1_I2S1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_I2S1_INT_MAP_S 0 + +#define INTERRUPT_CORE1_UART_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x86C) +/* INTERRUPT_CORE1_UART_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_UART_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UART_INTR_MAP_M ((INTERRUPT_CORE1_UART_INTR_MAP_V) << (INTERRUPT_CORE1_UART_INTR_MAP_S)) +#define INTERRUPT_CORE1_UART_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UART_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_UART1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x870) +/* INTERRUPT_CORE1_UART1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_UART1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UART1_INTR_MAP_M ((INTERRUPT_CORE1_UART1_INTR_MAP_V) << (INTERRUPT_CORE1_UART1_INTR_MAP_S)) +#define INTERRUPT_CORE1_UART1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UART1_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_UART2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x874) +/* INTERRUPT_CORE1_UART2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_UART2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_UART2_INTR_MAP_M ((INTERRUPT_CORE1_UART2_INTR_MAP_V) << (INTERRUPT_CORE1_UART2_INTR_MAP_S)) +#define INTERRUPT_CORE1_UART2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_UART2_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x878) +/* INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP 0x0000001F +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_M ((INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V) << (INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S)) +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_V 0x1F +#define INTERRUPT_CORE1_SDIO_HOST_INTERRUPT_MAP_S 0 + +#define INTERRUPT_CORE1_PWM0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x87C) +/* INTERRUPT_CORE1_PWM0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_PWM0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM0_INTR_MAP_M ((INTERRUPT_CORE1_PWM0_INTR_MAP_V) << (INTERRUPT_CORE1_PWM0_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM0_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_PWM1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x880) +/* INTERRUPT_CORE1_PWM1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_PWM1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM1_INTR_MAP_M ((INTERRUPT_CORE1_PWM1_INTR_MAP_V) << (INTERRUPT_CORE1_PWM1_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM1_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_PWM2_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x884) +/* INTERRUPT_CORE1_PWM2_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_PWM2_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM2_INTR_MAP_M ((INTERRUPT_CORE1_PWM2_INTR_MAP_V) << (INTERRUPT_CORE1_PWM2_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM2_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM2_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_PWM3_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x888) +/* INTERRUPT_CORE1_PWM3_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_PWM3_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PWM3_INTR_MAP_M ((INTERRUPT_CORE1_PWM3_INTR_MAP_V) << (INTERRUPT_CORE1_PWM3_INTR_MAP_S)) +#define INTERRUPT_CORE1_PWM3_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PWM3_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_LEDC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x88C) +/* INTERRUPT_CORE1_LEDC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_LEDC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_LEDC_INT_MAP_M ((INTERRUPT_CORE1_LEDC_INT_MAP_V) << (INTERRUPT_CORE1_LEDC_INT_MAP_S)) +#define INTERRUPT_CORE1_LEDC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_LEDC_INT_MAP_S 0 + +#define INTERRUPT_CORE1_EFUSE_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x890) +/* INTERRUPT_CORE1_EFUSE_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_EFUSE_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_EFUSE_INT_MAP_M ((INTERRUPT_CORE1_EFUSE_INT_MAP_V) << (INTERRUPT_CORE1_EFUSE_INT_MAP_S)) +#define INTERRUPT_CORE1_EFUSE_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_EFUSE_INT_MAP_S 0 + +#define INTERRUPT_CORE1_TWAI_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x894) +/* INTERRUPT_CORE1_TWAI_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TWAI_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TWAI_INT_MAP_M ((INTERRUPT_CORE1_TWAI_INT_MAP_V) << (INTERRUPT_CORE1_TWAI_INT_MAP_S)) +#define INTERRUPT_CORE1_TWAI_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TWAI_INT_MAP_S 0 + +#define INTERRUPT_CORE1_USB_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x898) +/* INTERRUPT_CORE1_USB_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_USB_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_USB_INTR_MAP_M ((INTERRUPT_CORE1_USB_INTR_MAP_V) << (INTERRUPT_CORE1_USB_INTR_MAP_S)) +#define INTERRUPT_CORE1_USB_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_USB_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x89C) +/* INTERRUPT_CORE1_RTC_CORE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_M ((INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V) << (INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S)) +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_RTC_CORE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_RMT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A0) +/* INTERRUPT_CORE1_RMT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_RMT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_RMT_INTR_MAP_M ((INTERRUPT_CORE1_RMT_INTR_MAP_V) << (INTERRUPT_CORE1_RMT_INTR_MAP_S)) +#define INTERRUPT_CORE1_RMT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_RMT_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_PCNT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A4) +/* INTERRUPT_CORE1_PCNT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_PCNT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_PCNT_INTR_MAP_M ((INTERRUPT_CORE1_PCNT_INTR_MAP_V) << (INTERRUPT_CORE1_PCNT_INTR_MAP_S)) +#define INTERRUPT_CORE1_PCNT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_PCNT_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8A8) +/* INTERRUPT_CORE1_I2C_EXT0_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V) << (INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S)) +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_I2C_EXT0_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8AC) +/* INTERRUPT_CORE1_I2C_EXT1_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_M ((INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V) << (INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S)) +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_I2C_EXT1_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B0) +/* INTERRUPT_CORE1_SPI2_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S)) +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI2_DMA_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B4) +/* INTERRUPT_CORE1_SPI3_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S)) +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI3_DMA_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8B8) +/* INTERRUPT_CORE1_SPI4_DMA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_M ((INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V) << (INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S)) +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI4_DMA_INT_MAP_S 0 + +#define INTERRUPT_CORE1_WDG_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8BC) +/* INTERRUPT_CORE1_WDG_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_WDG_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_WDG_INT_MAP_M ((INTERRUPT_CORE1_WDG_INT_MAP_V) << (INTERRUPT_CORE1_WDG_INT_MAP_S)) +#define INTERRUPT_CORE1_WDG_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_WDG_INT_MAP_S 0 + +#define INTERRUPT_CORE1_TIMER_INT1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C0) +/* INTERRUPT_CORE1_TIMER_INT1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TIMER_INT1_MAP 0x0000001F +#define INTERRUPT_CORE1_TIMER_INT1_MAP_M ((INTERRUPT_CORE1_TIMER_INT1_MAP_V) << (INTERRUPT_CORE1_TIMER_INT1_MAP_S)) +#define INTERRUPT_CORE1_TIMER_INT1_MAP_V 0x1F +#define INTERRUPT_CORE1_TIMER_INT1_MAP_S 0 + +#define INTERRUPT_CORE1_TIMER_INT2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C4) +/* INTERRUPT_CORE1_TIMER_INT2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TIMER_INT2_MAP 0x0000001F +#define INTERRUPT_CORE1_TIMER_INT2_MAP_M ((INTERRUPT_CORE1_TIMER_INT2_MAP_V) << (INTERRUPT_CORE1_TIMER_INT2_MAP_S)) +#define INTERRUPT_CORE1_TIMER_INT2_MAP_V 0x1F +#define INTERRUPT_CORE1_TIMER_INT2_MAP_S 0 + +#define INTERRUPT_CORE1_TG_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8C8) +/* INTERRUPT_CORE1_TG_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TG_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG_T0_INT_MAP_M ((INTERRUPT_CORE1_TG_T0_INT_MAP_V) << (INTERRUPT_CORE1_TG_T0_INT_MAP_S)) +#define INTERRUPT_CORE1_TG_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE1_TG_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8CC) +/* INTERRUPT_CORE1_TG_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TG_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG_T1_INT_MAP_M ((INTERRUPT_CORE1_TG_T1_INT_MAP_V) << (INTERRUPT_CORE1_TG_T1_INT_MAP_S)) +#define INTERRUPT_CORE1_TG_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG_T1_INT_MAP_S 0 + +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D0) +/* INTERRUPT_CORE1_TG_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TG_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG_WDT_INT_MAP_V) << (INTERRUPT_CORE1_TG_WDT_INT_MAP_S)) +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D4) +/* INTERRUPT_CORE1_TG1_T0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TG1_T0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_M ((INTERRUPT_CORE1_TG1_T0_INT_MAP_V) << (INTERRUPT_CORE1_TG1_T0_INT_MAP_S)) +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG1_T0_INT_MAP_S 0 + +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8D8) +/* INTERRUPT_CORE1_TG1_T1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TG1_T1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_M ((INTERRUPT_CORE1_TG1_T1_INT_MAP_V) << (INTERRUPT_CORE1_TG1_T1_INT_MAP_S)) +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG1_T1_INT_MAP_S 0 + +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8DC) +/* INTERRUPT_CORE1_TG1_WDT_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_M ((INTERRUPT_CORE1_TG1_WDT_INT_MAP_V) << (INTERRUPT_CORE1_TG1_WDT_INT_MAP_S)) +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_TG1_WDT_INT_MAP_S 0 + +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E0) +/* INTERRUPT_CORE1_CACHE_IA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_M ((INTERRUPT_CORE1_CACHE_IA_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_IA_INT_MAP_S)) +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_CACHE_IA_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E4) +/* INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S)) +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SYSTIMER_TARGET0_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8E8) +/* INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S)) +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SYSTIMER_TARGET1_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8EC) +/* INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_M ((INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V) << (INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S)) +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SYSTIMER_TARGET2_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F0) +/* INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_M ((INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V) << (INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S)) +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_SPI_MEM_REJECT_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F4) +/* INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DCACHE_PRELOAD_INT_MAP_S 0 + +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8F8) +/* INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V) << (INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S)) +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_ICACHE_PRELOAD_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x8FC) +/* INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DCACHE_SYNC_INT_MAP_S 0 + +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x900) +/* INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_M ((INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V) << (INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S)) +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_ICACHE_SYNC_INT_MAP_S 0 + +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x904) +/* INTERRUPT_CORE1_APB_ADC_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_APB_ADC_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_M ((INTERRUPT_CORE1_APB_ADC_INT_MAP_V) << (INTERRUPT_CORE1_APB_ADC_INT_MAP_S)) +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_APB_ADC_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x908) +/* INTERRUPT_CORE1_DMA_CH0_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_CH0_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH0_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH0_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_CH0_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x90C) +/* INTERRUPT_CORE1_DMA_CH1_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_CH1_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH1_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH1_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_CH1_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x910) +/* INTERRUPT_CORE1_DMA_CH2_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_CH2_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH2_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH2_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_CH2_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x914) +/* INTERRUPT_CORE1_DMA_CH3_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_CH3_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH3_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH3_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_CH3_INT_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x918) +/* INTERRUPT_CORE1_DMA_CH4_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_CH4_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_M ((INTERRUPT_CORE1_DMA_CH4_INT_MAP_V) << (INTERRUPT_CORE1_DMA_CH4_INT_MAP_S)) +#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_CH4_INT_MAP_S 0 + +#define INTERRUPT_CORE1_RSA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x91C) +/* INTERRUPT_CORE1_RSA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_RSA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_RSA_INT_MAP_M ((INTERRUPT_CORE1_RSA_INT_MAP_V) << (INTERRUPT_CORE1_RSA_INT_MAP_S)) +#define INTERRUPT_CORE1_RSA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_RSA_INT_MAP_S 0 + +#define INTERRUPT_CORE1_AES_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x920) +/* INTERRUPT_CORE1_AES_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_AES_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_AES_INT_MAP_M ((INTERRUPT_CORE1_AES_INT_MAP_V) << (INTERRUPT_CORE1_AES_INT_MAP_S)) +#define INTERRUPT_CORE1_AES_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_AES_INT_MAP_S 0 + +#define INTERRUPT_CORE1_SHA_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x924) +/* INTERRUPT_CORE1_SHA_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_SHA_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_SHA_INT_MAP_M ((INTERRUPT_CORE1_SHA_INT_MAP_V) << (INTERRUPT_CORE1_SHA_INT_MAP_S)) +#define INTERRUPT_CORE1_SHA_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_SHA_INT_MAP_S 0 + +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x928) +/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_0_MAP_S 0 + +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x92C) +/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_1_MAP_S 0 + +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x930) +/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_2_MAP_S 0 + +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x934) +/* INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP 0x0000001F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_M ((INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V) << (INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S)) +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_V 0x1F +#define INTERRUPT_CORE1_CPU_INTR_FROM_CPU_3_MAP_S 0 + +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x938) +/* INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_M ((INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V) << (INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S)) +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_ASSIST_DEBUG_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x93C) +/* INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x940) +/* INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x944) +/* INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x948) +/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x94C) +/* INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x950) +/* INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x954) +/* INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x958) +/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x95C) +/* INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP 0x0000001F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_M ((INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V) << (INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S)) +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_V 0x1F +#define INTERRUPT_CORE1_CORE_1_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP_S 0 + +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x960) +/* INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S)) +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_CACHE_CORE0_ACS_INT_MAP_S 0 + +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x964) +/* INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP : R/W ;bitpos:[4:0] ;default: 5'd16 ; */ +/*description: */ +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP 0x0000001F +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_M ((INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V) << (INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S)) +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_V 0x1F +#define INTERRUPT_CORE1_CACHE_CORE1_ACS_INT_MAP_S 0 + +#define INTERRUPT_CORE1_INTR_STATUS_0_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x968) +/* INTERRUPT_CORE1_INTR_STATUS_0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE1_INTR_STATUS_0 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_0_M ((INTERRUPT_CORE1_INTR_STATUS_0_V) << (INTERRUPT_CORE1_INTR_STATUS_0_S)) +#define INTERRUPT_CORE1_INTR_STATUS_0_V 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_0_S 0 + +#define INTERRUPT_CORE1_INTR_STATUS_1_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x96C) +/* INTERRUPT_CORE1_INTR_STATUS_1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE1_INTR_STATUS_1 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_1_M ((INTERRUPT_CORE1_INTR_STATUS_1_V) << (INTERRUPT_CORE1_INTR_STATUS_1_S)) +#define INTERRUPT_CORE1_INTR_STATUS_1_V 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_1_S 0 + +#define INTERRUPT_CORE1_INTR_STATUS_2_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x970) +/* INTERRUPT_CORE1_INTR_STATUS_2 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define INTERRUPT_CORE1_INTR_STATUS_2 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_2_M ((INTERRUPT_CORE1_INTR_STATUS_2_V) << (INTERRUPT_CORE1_INTR_STATUS_2_S)) +#define INTERRUPT_CORE1_INTR_STATUS_2_V 0xFFFFFFFF +#define INTERRUPT_CORE1_INTR_STATUS_2_S 0 + +#define INTERRUPT_CORE1_CLOCK_GATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0x974) +/* INTERRUPT_CORE1_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define INTERRUPT_CORE1_CLK_EN (BIT(0)) +#define INTERRUPT_CORE1_CLK_EN_M (BIT(0)) +#define INTERRUPT_CORE1_CLK_EN_V 0x1 +#define INTERRUPT_CORE1_CLK_EN_S 0 + +#define INTERRUPT_CORE1_INTERRUPT_DATE_REG (DR_REG_INTERRUPT_CORE1_BASE + 0xFFC) +/* INTERRUPT_CORE1_INTERRUPT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ +/*description: */ +#define INTERRUPT_CORE1_INTERRUPT_DATE 0x0FFFFFFF +#define INTERRUPT_CORE1_INTERRUPT_DATE_M ((INTERRUPT_CORE1_INTERRUPT_DATE_V) << (INTERRUPT_CORE1_INTERRUPT_DATE_S)) +#define INTERRUPT_CORE1_INTERRUPT_DATE_V 0xFFFFFFF +#define INTERRUPT_CORE1_INTERRUPT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/interrupt_core1_struct.h b/components/soc/soc/esp32s3/include/soc/interrupt_core1_struct.h new file mode 100644 index 000000000..cddcb1030 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/interrupt_core1_struct.h @@ -0,0 +1,1605 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + uint32_t reserved_0; + uint32_t reserved_4; + uint32_t reserved_8; + uint32_t reserved_c; + uint32_t reserved_10; + uint32_t reserved_14; + uint32_t reserved_18; + uint32_t reserved_1c; + uint32_t reserved_20; + uint32_t reserved_24; + uint32_t reserved_28; + uint32_t reserved_2c; + uint32_t reserved_30; + uint32_t reserved_34; + uint32_t reserved_38; + uint32_t reserved_3c; + uint32_t reserved_40; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t reserved_3fc; + uint32_t reserved_400; + uint32_t reserved_404; + uint32_t reserved_408; + uint32_t reserved_40c; + uint32_t reserved_410; + uint32_t reserved_414; + uint32_t reserved_418; + uint32_t reserved_41c; + uint32_t reserved_420; + uint32_t reserved_424; + uint32_t reserved_428; + uint32_t reserved_42c; + uint32_t reserved_430; + uint32_t reserved_434; + uint32_t reserved_438; + uint32_t reserved_43c; + uint32_t reserved_440; + uint32_t reserved_444; + uint32_t reserved_448; + uint32_t reserved_44c; + uint32_t reserved_450; + uint32_t reserved_454; + uint32_t reserved_458; + uint32_t reserved_45c; + uint32_t reserved_460; + uint32_t reserved_464; + uint32_t reserved_468; + uint32_t reserved_46c; + uint32_t reserved_470; + uint32_t reserved_474; + uint32_t reserved_478; + uint32_t reserved_47c; + uint32_t reserved_480; + uint32_t reserved_484; + uint32_t reserved_488; + uint32_t reserved_48c; + uint32_t reserved_490; + uint32_t reserved_494; + uint32_t reserved_498; + uint32_t reserved_49c; + uint32_t reserved_4a0; + uint32_t reserved_4a4; + uint32_t reserved_4a8; + uint32_t reserved_4ac; + uint32_t reserved_4b0; + uint32_t reserved_4b4; + uint32_t reserved_4b8; + uint32_t reserved_4bc; + uint32_t reserved_4c0; + uint32_t reserved_4c4; + uint32_t reserved_4c8; + uint32_t reserved_4cc; + uint32_t reserved_4d0; + uint32_t reserved_4d4; + uint32_t reserved_4d8; + uint32_t reserved_4dc; + uint32_t reserved_4e0; + uint32_t reserved_4e4; + uint32_t reserved_4e8; + uint32_t reserved_4ec; + uint32_t reserved_4f0; + uint32_t reserved_4f4; + uint32_t reserved_4f8; + uint32_t reserved_4fc; + uint32_t reserved_500; + uint32_t reserved_504; + uint32_t reserved_508; + uint32_t reserved_50c; + uint32_t reserved_510; + uint32_t reserved_514; + uint32_t reserved_518; + uint32_t reserved_51c; + uint32_t reserved_520; + uint32_t reserved_524; + uint32_t reserved_528; + uint32_t reserved_52c; + uint32_t reserved_530; + uint32_t reserved_534; + uint32_t reserved_538; + uint32_t reserved_53c; + uint32_t reserved_540; + uint32_t reserved_544; + uint32_t reserved_548; + uint32_t reserved_54c; + uint32_t reserved_550; + uint32_t reserved_554; + uint32_t reserved_558; + uint32_t reserved_55c; + uint32_t reserved_560; + uint32_t reserved_564; + uint32_t reserved_568; + uint32_t reserved_56c; + uint32_t reserved_570; + uint32_t reserved_574; + uint32_t reserved_578; + uint32_t reserved_57c; + uint32_t reserved_580; + uint32_t reserved_584; + uint32_t reserved_588; + uint32_t reserved_58c; + uint32_t reserved_590; + uint32_t reserved_594; + uint32_t reserved_598; + uint32_t reserved_59c; + uint32_t reserved_5a0; + uint32_t reserved_5a4; + uint32_t reserved_5a8; + uint32_t reserved_5ac; + uint32_t reserved_5b0; + uint32_t reserved_5b4; + uint32_t reserved_5b8; + uint32_t reserved_5bc; + uint32_t reserved_5c0; + uint32_t reserved_5c4; + uint32_t reserved_5c8; + uint32_t reserved_5cc; + uint32_t reserved_5d0; + uint32_t reserved_5d4; + uint32_t reserved_5d8; + uint32_t reserved_5dc; + uint32_t reserved_5e0; + uint32_t reserved_5e4; + uint32_t reserved_5e8; + uint32_t reserved_5ec; + uint32_t reserved_5f0; + uint32_t reserved_5f4; + uint32_t reserved_5f8; + uint32_t reserved_5fc; + uint32_t reserved_600; + uint32_t reserved_604; + uint32_t reserved_608; + uint32_t reserved_60c; + uint32_t reserved_610; + uint32_t reserved_614; + uint32_t reserved_618; + uint32_t reserved_61c; + uint32_t reserved_620; + uint32_t reserved_624; + uint32_t reserved_628; + uint32_t reserved_62c; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + uint32_t reserved_6fc; + uint32_t reserved_700; + uint32_t reserved_704; + uint32_t reserved_708; + uint32_t reserved_70c; + uint32_t reserved_710; + uint32_t reserved_714; + uint32_t reserved_718; + uint32_t reserved_71c; + uint32_t reserved_720; + uint32_t reserved_724; + uint32_t reserved_728; + uint32_t reserved_72c; + uint32_t reserved_730; + uint32_t reserved_734; + uint32_t reserved_738; + uint32_t reserved_73c; + uint32_t reserved_740; + uint32_t reserved_744; + uint32_t reserved_748; + uint32_t reserved_74c; + uint32_t reserved_750; + uint32_t reserved_754; + uint32_t reserved_758; + uint32_t reserved_75c; + uint32_t reserved_760; + uint32_t reserved_764; + uint32_t reserved_768; + uint32_t reserved_76c; + uint32_t reserved_770; + uint32_t reserved_774; + uint32_t reserved_778; + uint32_t reserved_77c; + uint32_t reserved_780; + uint32_t reserved_784; + uint32_t reserved_788; + uint32_t reserved_78c; + uint32_t reserved_790; + uint32_t reserved_794; + uint32_t reserved_798; + uint32_t reserved_79c; + uint32_t reserved_7a0; + uint32_t reserved_7a4; + uint32_t reserved_7a8; + uint32_t reserved_7ac; + uint32_t reserved_7b0; + uint32_t reserved_7b4; + uint32_t reserved_7b8; + uint32_t reserved_7bc; + uint32_t reserved_7c0; + uint32_t reserved_7c4; + uint32_t reserved_7c8; + uint32_t reserved_7cc; + uint32_t reserved_7d0; + uint32_t reserved_7d4; + uint32_t reserved_7d8; + uint32_t reserved_7dc; + uint32_t reserved_7e0; + uint32_t reserved_7e4; + uint32_t reserved_7e8; + uint32_t reserved_7ec; + uint32_t reserved_7f0; + uint32_t reserved_7f4; + uint32_t reserved_7f8; + uint32_t reserved_7fc; + union { + struct { + uint32_t core1_mac_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_mac_intr_map; + union { + struct { + uint32_t core1_mac_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_mac_nmi_map; + union { + struct { + uint32_t core1_pwr_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_pwr_intr_map; + union { + struct { + uint32_t core1_bb_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_bb_int_map; + union { + struct { + uint32_t core1_bt_mac_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_bt_mac_int_map; + union { + struct { + uint32_t core1_bt_bb_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_bt_bb_int_map; + union { + struct { + uint32_t core1_bt_bb_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_bt_bb_nmi_map; + union { + struct { + uint32_t core1_rwbt_irq_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_rwbt_irq_map; + union { + struct { + uint32_t core1_rwble_irq_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_rwble_irq_map; + union { + struct { + uint32_t core1_rwbt_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_rwbt_nmi_map; + union { + struct { + uint32_t core1_rwble_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_rwble_nmi_map; + union { + struct { + uint32_t core1_i2c_mst_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_i2c_mst_int_map; + union { + struct { + uint32_t core1_slc0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_slc0_intr_map; + union { + struct { + uint32_t core1_slc1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_slc1_intr_map; + union { + struct { + uint32_t core1_uhci0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_uhci0_intr_map; + union { + struct { + uint32_t core1_uhci1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_uhci1_intr_map; + union { + struct { + uint32_t core1_gpio_interrupt_pro_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_gpio_interrupt_pro_map; + union { + struct { + uint32_t core1_gpio_interrupt_pro_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_gpio_interrupt_pro_nmi_map; + union { + struct { + uint32_t core1_gpio_interrupt_app_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_gpio_interrupt_app_map; + union { + struct { + uint32_t core1_gpio_interrupt_app_nmi_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_gpio_interrupt_app_nmi_map; + union { + struct { + uint32_t core1_spi_intr_1_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi_intr_1_map; + union { + struct { + uint32_t core1_spi_intr_2_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi_intr_2_map; + union { + struct { + uint32_t core1_spi_intr_3_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi_intr_3_map; + union { + struct { + uint32_t core1_spi_intr_4_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi_intr_4_map; + union { + struct { + uint32_t core1_lcd_cam_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_lcd_cam_int_map; + union { + struct { + uint32_t core1_i2s0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_i2s0_int_map; + union { + struct { + uint32_t core1_i2s1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_i2s1_int_map; + union { + struct { + uint32_t core1_uart_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_uart_intr_map; + union { + struct { + uint32_t core1_uart1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_uart1_intr_map; + union { + struct { + uint32_t core1_uart2_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_uart2_intr_map; + union { + struct { + uint32_t core1_sdio_host_interrupt_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_sdio_host_interrupt_map; + union { + struct { + uint32_t core1_pwm0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_pwm0_intr_map; + union { + struct { + uint32_t core1_pwm1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_pwm1_intr_map; + union { + struct { + uint32_t core1_pwm2_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_pwm2_intr_map; + union { + struct { + uint32_t core1_pwm3_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_pwm3_intr_map; + union { + struct { + uint32_t core1_ledc_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_ledc_int_map; + union { + struct { + uint32_t core1_efuse_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_efuse_int_map; + union { + struct { + uint32_t core1_can_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_can_int_map; + union { + struct { + uint32_t core1_usb_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_usb_intr_map; + union { + struct { + uint32_t core1_rtc_core_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_rtc_core_intr_map; + union { + struct { + uint32_t core1_rmt_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_rmt_intr_map; + union { + struct { + uint32_t core1_pcnt_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_pcnt_intr_map; + union { + struct { + uint32_t core1_i2c_ext0_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_i2c_ext0_intr_map; + union { + struct { + uint32_t core1_i2c_ext1_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_i2c_ext1_intr_map; + union { + struct { + uint32_t core1_spi2_dma_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi2_dma_int_map; + union { + struct { + uint32_t core1_spi3_dma_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi3_dma_int_map; + union { + struct { + uint32_t core1_spi4_dma_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi4_dma_int_map; + union { + struct { + uint32_t core1_wdg_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_wdg_int_map; + union { + struct { + uint32_t core1_timer_int1_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_timer_int1_map; + union { + struct { + uint32_t core1_timer_int2_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_timer_int2_map; + union { + struct { + uint32_t core1_tg_t0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_tg_t0_int_map; + union { + struct { + uint32_t core1_tg_t1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_tg_t1_int_map; + union { + struct { + uint32_t core1_tg_wdt_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_tg_wdt_int_map; + union { + struct { + uint32_t core1_tg1_t0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_tg1_t0_int_map; + union { + struct { + uint32_t core1_tg1_t1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_tg1_t1_int_map; + union { + struct { + uint32_t core1_tg1_wdt_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_tg1_wdt_int_map; + union { + struct { + uint32_t core1_cache_ia_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_cache_ia_int_map; + union { + struct { + uint32_t core1_systimer_target0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_systimer_target0_int_map; + union { + struct { + uint32_t core1_systimer_target1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_systimer_target1_int_map; + union { + struct { + uint32_t core1_systimer_target2_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_systimer_target2_int_map; + union { + struct { + uint32_t core1_spi_mem_reject_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_spi_mem_reject_intr_map; + union { + struct { + uint32_t core1_dcache_preload_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dcache_preload_int_map; + union { + struct { + uint32_t core1_icache_preload_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_icache_preload_int_map; + union { + struct { + uint32_t core1_dcache_sync_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dcache_sync_int_map; + union { + struct { + uint32_t core1_icache_sync_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_icache_sync_int_map; + union { + struct { + uint32_t core1_apb_adc_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_apb_adc_int_map; + union { + struct { + uint32_t core1_dma_ch0_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_ch0_int_map; + union { + struct { + uint32_t core1_dma_ch1_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_ch1_int_map; + union { + struct { + uint32_t core1_dma_ch2_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_ch2_int_map; + union { + struct { + uint32_t core1_dma_ch3_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_ch3_int_map; + union { + struct { + uint32_t core1_dma_ch4_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_ch4_int_map; + union { + struct { + uint32_t core1_rsa_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_rsa_int_map; + union { + struct { + uint32_t core1_aes_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_aes_int_map; + union { + struct { + uint32_t core1_sha_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_sha_int_map; + union { + struct { + uint32_t core1_cpu_intr_from_cpu_0_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_cpu_intr_from_cpu_0_map; + union { + struct { + uint32_t core1_cpu_intr_from_cpu_1_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_cpu_intr_from_cpu_1_map; + union { + struct { + uint32_t core1_cpu_intr_from_cpu_2_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_cpu_intr_from_cpu_2_map; + union { + struct { + uint32_t core1_cpu_intr_from_cpu_3_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_cpu_intr_from_cpu_3_map; + union { + struct { + uint32_t core1_assist_debug_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_assist_debug_intr_map; + union { + struct { + uint32_t core1_dma_apbperi_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_dma_apbperi_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core1_core_0_iram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_0_iram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core1_core_0_dram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_0_dram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core1_core_0_pif_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_0_pif_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core1_core_0_pif_pms_monitor_violate_size_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_0_pif_pms_monitor_violate_size_intr_map; + union { + struct { + uint32_t core1_core_1_iram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_1_iram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core1_core_1_dram0_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_1_dram0_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core1_core_1_pif_pms_monitor_violate_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_1_pif_pms_monitor_violate_intr_map; + union { + struct { + uint32_t core1_core_1_pif_pms_monitor_violate_size_intr_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_core_1_pif_pms_monitor_violate_size_intr_map; + union { + struct { + uint32_t core1_cache_core0_acs_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_cache_core0_acs_int_map; + union { + struct { + uint32_t core1_cache_core1_acs_int_map: 5; + uint32_t reserved5: 27; + }; + uint32_t val; + } core1_cache_core1_acs_int_map; + uint32_t core1_intr_status_0; /**/ + uint32_t core1_intr_status_1; /**/ + uint32_t core1_intr_status_2; /**/ + union { + struct { + uint32_t core1_clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core1_clock_gate; + uint32_t reserved_978; + uint32_t reserved_97c; + uint32_t reserved_980; + uint32_t reserved_984; + uint32_t reserved_988; + uint32_t reserved_98c; + uint32_t reserved_990; + uint32_t reserved_994; + uint32_t reserved_998; + uint32_t reserved_99c; + uint32_t reserved_9a0; + uint32_t reserved_9a4; + uint32_t reserved_9a8; + uint32_t reserved_9ac; + uint32_t reserved_9b0; + uint32_t reserved_9b4; + uint32_t reserved_9b8; + uint32_t reserved_9bc; + uint32_t reserved_9c0; + uint32_t reserved_9c4; + uint32_t reserved_9c8; + uint32_t reserved_9cc; + uint32_t reserved_9d0; + uint32_t reserved_9d4; + uint32_t reserved_9d8; + uint32_t reserved_9dc; + uint32_t reserved_9e0; + uint32_t reserved_9e4; + uint32_t reserved_9e8; + uint32_t reserved_9ec; + uint32_t reserved_9f0; + uint32_t reserved_9f4; + uint32_t reserved_9f8; + uint32_t reserved_9fc; + uint32_t reserved_a00; + uint32_t reserved_a04; + uint32_t reserved_a08; + uint32_t reserved_a0c; + uint32_t reserved_a10; + uint32_t reserved_a14; + uint32_t reserved_a18; + uint32_t reserved_a1c; + uint32_t reserved_a20; + uint32_t reserved_a24; + uint32_t reserved_a28; + uint32_t reserved_a2c; + uint32_t reserved_a30; + uint32_t reserved_a34; + uint32_t reserved_a38; + uint32_t reserved_a3c; + uint32_t reserved_a40; + uint32_t reserved_a44; + uint32_t reserved_a48; + uint32_t reserved_a4c; + uint32_t reserved_a50; + uint32_t reserved_a54; + uint32_t reserved_a58; + uint32_t reserved_a5c; + uint32_t reserved_a60; + uint32_t reserved_a64; + uint32_t reserved_a68; + uint32_t reserved_a6c; + uint32_t reserved_a70; + uint32_t reserved_a74; + uint32_t reserved_a78; + uint32_t reserved_a7c; + uint32_t reserved_a80; + uint32_t reserved_a84; + uint32_t reserved_a88; + uint32_t reserved_a8c; + uint32_t reserved_a90; + uint32_t reserved_a94; + uint32_t reserved_a98; + uint32_t reserved_a9c; + uint32_t reserved_aa0; + uint32_t reserved_aa4; + uint32_t reserved_aa8; + uint32_t reserved_aac; + uint32_t reserved_ab0; + uint32_t reserved_ab4; + uint32_t reserved_ab8; + uint32_t reserved_abc; + uint32_t reserved_ac0; + uint32_t reserved_ac4; + uint32_t reserved_ac8; + uint32_t reserved_acc; + uint32_t reserved_ad0; + uint32_t reserved_ad4; + uint32_t reserved_ad8; + uint32_t reserved_adc; + uint32_t reserved_ae0; + uint32_t reserved_ae4; + uint32_t reserved_ae8; + uint32_t reserved_aec; + uint32_t reserved_af0; + uint32_t reserved_af4; + uint32_t reserved_af8; + uint32_t reserved_afc; + uint32_t reserved_b00; + uint32_t reserved_b04; + uint32_t reserved_b08; + uint32_t reserved_b0c; + uint32_t reserved_b10; + uint32_t reserved_b14; + uint32_t reserved_b18; + uint32_t reserved_b1c; + uint32_t reserved_b20; + uint32_t reserved_b24; + uint32_t reserved_b28; + uint32_t reserved_b2c; + uint32_t reserved_b30; + uint32_t reserved_b34; + uint32_t reserved_b38; + uint32_t reserved_b3c; + uint32_t reserved_b40; + uint32_t reserved_b44; + uint32_t reserved_b48; + uint32_t reserved_b4c; + uint32_t reserved_b50; + uint32_t reserved_b54; + uint32_t reserved_b58; + uint32_t reserved_b5c; + uint32_t reserved_b60; + uint32_t reserved_b64; + uint32_t reserved_b68; + uint32_t reserved_b6c; + uint32_t reserved_b70; + uint32_t reserved_b74; + uint32_t reserved_b78; + uint32_t reserved_b7c; + uint32_t reserved_b80; + uint32_t reserved_b84; + uint32_t reserved_b88; + uint32_t reserved_b8c; + uint32_t reserved_b90; + uint32_t reserved_b94; + uint32_t reserved_b98; + uint32_t reserved_b9c; + uint32_t reserved_ba0; + uint32_t reserved_ba4; + uint32_t reserved_ba8; + uint32_t reserved_bac; + uint32_t reserved_bb0; + uint32_t reserved_bb4; + uint32_t reserved_bb8; + uint32_t reserved_bbc; + uint32_t reserved_bc0; + uint32_t reserved_bc4; + uint32_t reserved_bc8; + uint32_t reserved_bcc; + uint32_t reserved_bd0; + uint32_t reserved_bd4; + uint32_t reserved_bd8; + uint32_t reserved_bdc; + uint32_t reserved_be0; + uint32_t reserved_be4; + uint32_t reserved_be8; + uint32_t reserved_bec; + uint32_t reserved_bf0; + uint32_t reserved_bf4; + uint32_t reserved_bf8; + uint32_t reserved_bfc; + uint32_t reserved_c00; + uint32_t reserved_c04; + uint32_t reserved_c08; + uint32_t reserved_c0c; + uint32_t reserved_c10; + uint32_t reserved_c14; + uint32_t reserved_c18; + uint32_t reserved_c1c; + uint32_t reserved_c20; + uint32_t reserved_c24; + uint32_t reserved_c28; + uint32_t reserved_c2c; + uint32_t reserved_c30; + uint32_t reserved_c34; + uint32_t reserved_c38; + uint32_t reserved_c3c; + uint32_t reserved_c40; + uint32_t reserved_c44; + uint32_t reserved_c48; + uint32_t reserved_c4c; + uint32_t reserved_c50; + uint32_t reserved_c54; + uint32_t reserved_c58; + uint32_t reserved_c5c; + uint32_t reserved_c60; + uint32_t reserved_c64; + uint32_t reserved_c68; + uint32_t reserved_c6c; + uint32_t reserved_c70; + uint32_t reserved_c74; + uint32_t reserved_c78; + uint32_t reserved_c7c; + uint32_t reserved_c80; + uint32_t reserved_c84; + uint32_t reserved_c88; + uint32_t reserved_c8c; + uint32_t reserved_c90; + uint32_t reserved_c94; + uint32_t reserved_c98; + uint32_t reserved_c9c; + uint32_t reserved_ca0; + uint32_t reserved_ca4; + uint32_t reserved_ca8; + uint32_t reserved_cac; + uint32_t reserved_cb0; + uint32_t reserved_cb4; + uint32_t reserved_cb8; + uint32_t reserved_cbc; + uint32_t reserved_cc0; + uint32_t reserved_cc4; + uint32_t reserved_cc8; + uint32_t reserved_ccc; + uint32_t reserved_cd0; + uint32_t reserved_cd4; + uint32_t reserved_cd8; + uint32_t reserved_cdc; + uint32_t reserved_ce0; + uint32_t reserved_ce4; + uint32_t reserved_ce8; + uint32_t reserved_cec; + uint32_t reserved_cf0; + uint32_t reserved_cf4; + uint32_t reserved_cf8; + uint32_t reserved_cfc; + uint32_t reserved_d00; + uint32_t reserved_d04; + uint32_t reserved_d08; + uint32_t reserved_d0c; + uint32_t reserved_d10; + uint32_t reserved_d14; + uint32_t reserved_d18; + uint32_t reserved_d1c; + uint32_t reserved_d20; + uint32_t reserved_d24; + uint32_t reserved_d28; + uint32_t reserved_d2c; + uint32_t reserved_d30; + uint32_t reserved_d34; + uint32_t reserved_d38; + uint32_t reserved_d3c; + uint32_t reserved_d40; + uint32_t reserved_d44; + uint32_t reserved_d48; + uint32_t reserved_d4c; + uint32_t reserved_d50; + uint32_t reserved_d54; + uint32_t reserved_d58; + uint32_t reserved_d5c; + uint32_t reserved_d60; + uint32_t reserved_d64; + uint32_t reserved_d68; + uint32_t reserved_d6c; + uint32_t reserved_d70; + uint32_t reserved_d74; + uint32_t reserved_d78; + uint32_t reserved_d7c; + uint32_t reserved_d80; + uint32_t reserved_d84; + uint32_t reserved_d88; + uint32_t reserved_d8c; + uint32_t reserved_d90; + uint32_t reserved_d94; + uint32_t reserved_d98; + uint32_t reserved_d9c; + uint32_t reserved_da0; + uint32_t reserved_da4; + uint32_t reserved_da8; + uint32_t reserved_dac; + uint32_t reserved_db0; + uint32_t reserved_db4; + uint32_t reserved_db8; + uint32_t reserved_dbc; + uint32_t reserved_dc0; + uint32_t reserved_dc4; + uint32_t reserved_dc8; + uint32_t reserved_dcc; + uint32_t reserved_dd0; + uint32_t reserved_dd4; + uint32_t reserved_dd8; + uint32_t reserved_ddc; + uint32_t reserved_de0; + uint32_t reserved_de4; + uint32_t reserved_de8; + uint32_t reserved_dec; + uint32_t reserved_df0; + uint32_t reserved_df4; + uint32_t reserved_df8; + uint32_t reserved_dfc; + uint32_t reserved_e00; + uint32_t reserved_e04; + uint32_t reserved_e08; + uint32_t reserved_e0c; + uint32_t reserved_e10; + uint32_t reserved_e14; + uint32_t reserved_e18; + uint32_t reserved_e1c; + uint32_t reserved_e20; + uint32_t reserved_e24; + uint32_t reserved_e28; + uint32_t reserved_e2c; + uint32_t reserved_e30; + uint32_t reserved_e34; + uint32_t reserved_e38; + uint32_t reserved_e3c; + uint32_t reserved_e40; + uint32_t reserved_e44; + uint32_t reserved_e48; + uint32_t reserved_e4c; + uint32_t reserved_e50; + uint32_t reserved_e54; + uint32_t reserved_e58; + uint32_t reserved_e5c; + uint32_t reserved_e60; + uint32_t reserved_e64; + uint32_t reserved_e68; + uint32_t reserved_e6c; + uint32_t reserved_e70; + uint32_t reserved_e74; + uint32_t reserved_e78; + uint32_t reserved_e7c; + uint32_t reserved_e80; + uint32_t reserved_e84; + uint32_t reserved_e88; + uint32_t reserved_e8c; + uint32_t reserved_e90; + uint32_t reserved_e94; + uint32_t reserved_e98; + uint32_t reserved_e9c; + uint32_t reserved_ea0; + uint32_t reserved_ea4; + uint32_t reserved_ea8; + uint32_t reserved_eac; + uint32_t reserved_eb0; + uint32_t reserved_eb4; + uint32_t reserved_eb8; + uint32_t reserved_ebc; + uint32_t reserved_ec0; + uint32_t reserved_ec4; + uint32_t reserved_ec8; + uint32_t reserved_ecc; + uint32_t reserved_ed0; + uint32_t reserved_ed4; + uint32_t reserved_ed8; + uint32_t reserved_edc; + uint32_t reserved_ee0; + uint32_t reserved_ee4; + uint32_t reserved_ee8; + uint32_t reserved_eec; + uint32_t reserved_ef0; + uint32_t reserved_ef4; + uint32_t reserved_ef8; + uint32_t reserved_efc; + uint32_t reserved_f00; + uint32_t reserved_f04; + uint32_t reserved_f08; + uint32_t reserved_f0c; + uint32_t reserved_f10; + uint32_t reserved_f14; + uint32_t reserved_f18; + uint32_t reserved_f1c; + uint32_t reserved_f20; + uint32_t reserved_f24; + uint32_t reserved_f28; + uint32_t reserved_f2c; + uint32_t reserved_f30; + uint32_t reserved_f34; + uint32_t reserved_f38; + uint32_t reserved_f3c; + uint32_t reserved_f40; + uint32_t reserved_f44; + uint32_t reserved_f48; + uint32_t reserved_f4c; + uint32_t reserved_f50; + uint32_t reserved_f54; + uint32_t reserved_f58; + uint32_t reserved_f5c; + uint32_t reserved_f60; + uint32_t reserved_f64; + uint32_t reserved_f68; + uint32_t reserved_f6c; + uint32_t reserved_f70; + uint32_t reserved_f74; + uint32_t reserved_f78; + uint32_t reserved_f7c; + uint32_t reserved_f80; + uint32_t reserved_f84; + uint32_t reserved_f88; + uint32_t reserved_f8c; + uint32_t reserved_f90; + uint32_t reserved_f94; + uint32_t reserved_f98; + uint32_t reserved_f9c; + uint32_t reserved_fa0; + uint32_t reserved_fa4; + uint32_t reserved_fa8; + uint32_t reserved_fac; + uint32_t reserved_fb0; + uint32_t reserved_fb4; + uint32_t reserved_fb8; + uint32_t reserved_fbc; + uint32_t reserved_fc0; + uint32_t reserved_fc4; + uint32_t reserved_fc8; + uint32_t reserved_fcc; + uint32_t reserved_fd0; + uint32_t reserved_fd4; + uint32_t reserved_fd8; + uint32_t reserved_fdc; + uint32_t reserved_fe0; + uint32_t reserved_fe4; + uint32_t reserved_fe8; + uint32_t reserved_fec; + uint32_t reserved_ff0; + uint32_t reserved_ff4; + uint32_t reserved_ff8; + union { + struct { + uint32_t core1_interrupt_date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } core1_interrupt_date; +} interrupt_core1_dev_t; + +extern interrupt_core1_dev_t INTERRUPT_CORE1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/interrupt_reg.h b/components/soc/soc/esp32s3/include/soc/interrupt_reg.h new file mode 100644 index 000000000..266e577a4 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/interrupt_reg.h @@ -0,0 +1,17 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "interrupt_core0_reg.h" +#include "interrupt_core1_reg.h" \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/io_mux_reg.h b/components/soc/soc/esp32s3/include/soc/io_mux_reg.h new file mode 100644 index 000000000..37a1efa27 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/io_mux_reg.h @@ -0,0 +1,427 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc.h" + +/* The following are the bit fields for PERIPHS_IO_MUX_x_U registers */ +/* Output enable in sleep mode */ +#define SLP_OE (BIT(0)) +#define SLP_OE_M (BIT(0)) +#define SLP_OE_V 1 +#define SLP_OE_S 0 +/* Pin used for wakeup from sleep */ +#define SLP_SEL (BIT(1)) +#define SLP_SEL_M (BIT(1)) +#define SLP_SEL_V 1 +#define SLP_SEL_S 1 +/* Pulldown enable in sleep mode */ +#define SLP_PD (BIT(2)) +#define SLP_PD_M (BIT(2)) +#define SLP_PD_V 1 +#define SLP_PD_S 2 +/* Pullup enable in sleep mode */ +#define SLP_PU (BIT(3)) +#define SLP_PU_M (BIT(3)) +#define SLP_PU_V 1 +#define SLP_PU_S 3 +/* Input enable in sleep mode */ +#define SLP_IE (BIT(4)) +#define SLP_IE_M (BIT(4)) +#define SLP_IE_V 1 +#define SLP_IE_S 4 +/* Drive strength in sleep mode */ +#define SLP_DRV 0x3 +#define SLP_DRV_M (SLP_DRV_V << SLP_DRV_S) +#define SLP_DRV_V 0x3 +#define SLP_DRV_S 5 +/* Pulldown enable */ +#define FUN_PD (BIT(7)) +#define FUN_PD_M (BIT(7)) +#define FUN_PD_V 1 +#define FUN_PD_S 7 +/* Pullup enable */ +#define FUN_PU (BIT(8)) +#define FUN_PU_M (BIT(8)) +#define FUN_PU_V 1 +#define FUN_PU_S 8 +/* Input enable */ +#define FUN_IE (BIT(9)) +#define FUN_IE_M (FUN_IE_V << FUN_IE_S) +#define FUN_IE_V 1 +#define FUN_IE_S 9 +/* Drive strength */ +#define FUN_DRV 0x3 +#define FUN_DRV_M (FUN_DRV_V << FUN_DRV_S) +#define FUN_DRV_V 0x3 +#define FUN_DRV_S 10 +/* Function select (possible values are defined for each pin as FUNC_pinname_function below) */ +#define MCU_SEL 0x7 +#define MCU_SEL_M (MCU_SEL_V << MCU_SEL_S) +#define MCU_SEL_V 0x7 +#define MCU_SEL_S 12 + +#define PIN_INPUT_ENABLE(PIN_NAME) SET_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_INPUT_DISABLE(PIN_NAME) CLEAR_PERI_REG_MASK(PIN_NAME,FUN_IE) +#define PIN_SET_DRV(PIN_NAME, drv) REG_SET_FIELD(PIN_NAME, FUN_DRV, (drv)); +#define PIN_PULLUP_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLUP_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PU) +#define PIN_PULLDWN_DIS(PIN_NAME) REG_CLR_BIT(PIN_NAME, FUN_PD) +#define PIN_PULLDWN_EN(PIN_NAME) REG_SET_BIT(PIN_NAME, FUN_PD) +#define PIN_FUNC_SELECT(PIN_NAME, FUNC) REG_SET_FIELD(PIN_NAME, MCU_SEL, FUNC) + +#define IO_MUX_GPIO0_REG PERIPHS_IO_MUX_GPIO0_U +#define IO_MUX_GPIO1_REG PERIPHS_IO_MUX_GPIO1_U +#define IO_MUX_GPIO2_REG PERIPHS_IO_MUX_GPIO2_U +#define IO_MUX_GPIO3_REG PERIPHS_IO_MUX_GPIO3_U +#define IO_MUX_GPIO4_REG PERIPHS_IO_MUX_GPIO4_U +#define IO_MUX_GPIO5_REG PERIPHS_IO_MUX_GPIO5_U +#define IO_MUX_GPIO6_REG PERIPHS_IO_MUX_GPIO6_U +#define IO_MUX_GPIO7_REG PERIPHS_IO_MUX_GPIO7_U +#define IO_MUX_GPIO8_REG PERIPHS_IO_MUX_GPIO8_U +#define IO_MUX_GPIO9_REG PERIPHS_IO_MUX_GPIO9_U +#define IO_MUX_GPIO10_REG PERIPHS_IO_MUX_GPIO10_U +#define IO_MUX_GPIO11_REG PERIPHS_IO_MUX_GPIO11_U +#define IO_MUX_GPIO12_REG PERIPHS_IO_MUX_GPIO12_U +#define IO_MUX_GPIO13_REG PERIPHS_IO_MUX_GPIO13_U +#define IO_MUX_GPIO14_REG PERIPHS_IO_MUX_GPIO14_U +#define IO_MUX_GPIO15_REG PERIPHS_IO_MUX_XTAL_32K_P_U +#define IO_MUX_GPIO16_REG PERIPHS_IO_MUX_XTAL_32K_N_U +#define IO_MUX_GPIO17_REG PERIPHS_IO_MUX_DAC_1_U +#define IO_MUX_GPIO18_REG PERIPHS_IO_MUX_DAC_2_U +#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_GPIO19_U +#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_GPIO20_U +#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_GPIO21_U +#define IO_MUX_GPIO26_REG PERIPHS_IO_MUX_SPICS1_U +#define IO_MUX_GPIO27_REG PERIPHS_IO_MUX_SPIHD_U +#define IO_MUX_GPIO28_REG PERIPHS_IO_MUX_SPIWP_U +#define IO_MUX_GPIO29_REG PERIPHS_IO_MUX_SPICS0_U +#define IO_MUX_GPIO30_REG PERIPHS_IO_MUX_SPICLK_U +#define IO_MUX_GPIO31_REG PERIPHS_IO_MUX_SPIQ_U +#define IO_MUX_GPIO32_REG PERIPHS_IO_MUX_SPID_U +#define IO_MUX_GPIO33_REG PERIPHS_IO_MUX_GPIO33_U +#define IO_MUX_GPIO34_REG PERIPHS_IO_MUX_GPIO34_U +#define IO_MUX_GPIO35_REG PERIPHS_IO_MUX_GPIO35_U +#define IO_MUX_GPIO36_REG PERIPHS_IO_MUX_GPIO36_U +#define IO_MUX_GPIO37_REG PERIPHS_IO_MUX_GPIO37_U +#define IO_MUX_GPIO38_REG PERIPHS_IO_MUX_GPIO38_U +#define IO_MUX_GPIO39_REG PERIPHS_IO_MUX_MTCK_U +#define IO_MUX_GPIO40_REG PERIPHS_IO_MUX_MTDO_U +#define IO_MUX_GPIO41_REG PERIPHS_IO_MUX_MTDI_U +#define IO_MUX_GPIO42_REG PERIPHS_IO_MUX_MTMS_U +#define IO_MUX_GPIO43_REG PERIPHS_IO_MUX_U0TXD_U +#define IO_MUX_GPIO44_REG PERIPHS_IO_MUX_U0RXD_U +#define IO_MUX_GPIO45_REG PERIPHS_IO_MUX_GPIO45_U +#define IO_MUX_GPIO46_REG PERIPHS_IO_MUX_GPIO46_U +#define IO_MUX_GPIO47_REG PERIPHS_IO_MUX_SPICLK_P_U +#define IO_MUX_GPIO48_REG PERIPHS_IO_MUX_SPICLK_N_U + +#define FUNC_GPIO_GPIO 1 +#define PIN_FUNC_GPIO 1 + +#define GPIO_PAD_PULLDOWN(num) do{PIN_PULLDWN_DIS(IOMUX_REG_GPIO##num);PIN_PULLUP_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_PULLUP(num) do{PIN_PULLUP_DIS(IOMUX_REG_GPIO##num);PIN_PULLDWN_EN(IOMUX_REG_GPIO##num);}while(0) +#define GPIO_PAD_SET_DRV(num, drv) PIN_SET_DRV(IOMUX_REG_GPIO##num, drv) + +#define U1RXD_GPIO_NUM 18 +#define U1TXD_GPIO_NUM 17 +#define U0RXD_GPIO_NUM 44 +#define U0TXD_GPIO_NUM 43 + +#define SPI_HD_GPIO_NUM 27 +#define SPI_WP_GPIO_NUM 28 +#define SPI_CS0_GPIO_NUM 29 +#define SPI_CLK_GPIO_NUM 30 +#define SPI_Q_GPIO_NUM 31 +#define SPI_D_GPIO_NUM 32 +#define SPI_D4_GPIO_NUM 33 +#define SPI_D5_GPIO_NUM 34 +#define SPI_D6_GPIO_NUM 35 +#define SPI_D7_GPIO_NUM 36 +#define SPI_DQS_GPIO_NUM 37 +#define SD_CLK_GPIO_NUM 12 +#define SD_CMD_GPIO_NUM 11 +#define SD_DATA0_GPIO_NUM 13 +#define SD_DATA1_GPIO_NUM 14 +#define SD_DATA2_GPIO_NUM 9 +#define SD_DATA3_GPIO_NUM 10 + +#define MAX_RTC_GPIO_NUM 21 +#define MAX_PAD_GPIO_NUM 48 +#define MAX_GPIO_NUM 53 + +#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE +#define PIN_CTRL (REG_IO_MUX_BASE +0x00) +#define PAD_POWER_SEL BIT(15) +#define PAD_POWER_SEL_V 0x1 +#define PAD_POWER_SEL_M BIT(15) +#define PAD_POWER_SEL_S 15 + + +#define PAD_POWER_SWITCH_DELAY 0x7 +#define PAD_POWER_SWITCH_DELAY_V 0x7 +#define PAD_POWER_SWITCH_DELAY_M (PAD_POWER_SWITCH_DELAY_V << PAD_POWER_SWITCH_DELAY_S) +#define PAD_POWER_SWITCH_DELAY_S 12 + + +#define CLK_OUT3 0xf +#define CLK_OUT3_V CLK_OUT3 +#define CLK_OUT3_S 8 +#define CLK_OUT3_M (CLK_OUT3_V << CLK_OUT3_S) +#define CLK_OUT2 0xf +#define CLK_OUT2_V CLK_OUT2 +#define CLK_OUT2_S 4 +#define CLK_OUT2_M (CLK_OUT2_V << CLK_OUT2_S) +#define CLK_OUT1 0xf +#define CLK_OUT1_V CLK_OUT1 +#define CLK_OUT1_S 0 +#define CLK_OUT1_M (CLK_OUT1_V << CLK_OUT1_S) + +#define PERIPHS_IO_MUX_GPIO0_U (REG_IO_MUX_BASE +0x04) +#define FUNC_GPIO0_GPIO0 1 +#define FUNC_GPIO0_GPIO0_0 0 + +#define PERIPHS_IO_MUX_GPIO1_U (REG_IO_MUX_BASE +0x08) +#define FUNC_GPIO1_GPIO1 1 +#define FUNC_GPIO1_GPIO1_0 0 + +#define PERIPHS_IO_MUX_GPIO2_U (REG_IO_MUX_BASE +0x0c) +#define FUNC_GPIO2_GPIO2 1 +#define FUNC_GPIO2_GPIO2_0 0 + +#define PERIPHS_IO_MUX_GPIO3_U (REG_IO_MUX_BASE +0x10) +#define FUNC_GPIO3_GPIO3 1 +#define FUNC_GPIO3_GPIO3_0 0 + +#define PERIPHS_IO_MUX_GPIO4_U (REG_IO_MUX_BASE +0x14) +#define FUNC_GPIO4_GPIO4 1 +#define FUNC_GPIO4_GPIO4_0 0 + +#define PERIPHS_IO_MUX_GPIO5_U (REG_IO_MUX_BASE +0x18) +#define FUNC_GPIO5_GPIO5 1 +#define FUNC_GPIO5_GPIO5_0 0 + +#define PERIPHS_IO_MUX_GPIO6_U (REG_IO_MUX_BASE +0x1c) +#define FUNC_GPIO6_GPIO6 1 +#define FUNC_GPIO6_GPIO6_0 0 + +#define PERIPHS_IO_MUX_GPIO7_U (REG_IO_MUX_BASE +0x20) +#define FUNC_GPIO7_GPIO7 1 +#define FUNC_GPIO7_GPIO7_0 0 + +#define PERIPHS_IO_MUX_GPIO8_U (REG_IO_MUX_BASE +0x24) +#define FUNC_GPIO8_SUBSPICS1 3 +#define FUNC_GPIO8_GPIO8 1 +#define FUNC_GPIO8_GPIO8_0 0 + +#define PERIPHS_IO_MUX_GPIO9_U (REG_IO_MUX_BASE +0x28) +#define FUNC_GPIO9_FSPIHD 4 +#define FUNC_GPIO9_SUBSPIHD 3 +#define FUNC_GPIO9_GPIO9 1 +#define FUNC_GPIO9_GPIO9_0 0 + +#define PERIPHS_IO_MUX_GPIO10_U (REG_IO_MUX_BASE +0x2c) +#define FUNC_GPIO10_FSPICS0 4 +#define FUNC_GPIO10_SUBSPICS0 3 +#define FUNC_GPIO10_FSPIIO4 2 +#define FUNC_GPIO10_GPIO10 1 +#define FUNC_GPIO10_GPIO10_0 0 + +#define PERIPHS_IO_MUX_GPIO11_U (REG_IO_MUX_BASE +0x30) +#define FUNC_GPIO11_FSPID 4 +#define FUNC_GPIO11_SUBSPID 3 +#define FUNC_GPIO11_FSPIIO5 2 +#define FUNC_GPIO11_GPIO11 1 +#define FUNC_GPIO11_GPIO11_0 0 + +#define PERIPHS_IO_MUX_GPIO12_U (REG_IO_MUX_BASE +0x34) +#define FUNC_GPIO12_FSPICLK 4 +#define FUNC_GPIO12_SUBSPICLK 3 +#define FUNC_GPIO12_FSPIIO6 2 +#define FUNC_GPIO12_GPIO12 1 +#define FUNC_GPIO12_GPIO12_0 0 + +#define PERIPHS_IO_MUX_GPIO13_U (REG_IO_MUX_BASE +0x38) +#define FUNC_GPIO13_FSPIQ 4 +#define FUNC_GPIO13_SUBSPIQ 3 +#define FUNC_GPIO13_FSPIIO7 2 +#define FUNC_GPIO13_GPIO13 1 +#define FUNC_GPIO13_GPIO13_0 0 + +#define PERIPHS_IO_MUX_GPIO14_U (REG_IO_MUX_BASE +0x3c) +#define FUNC_GPIO14_FSPIWP 4 +#define FUNC_GPIO14_SUBSPIWP 3 +#define FUNC_GPIO14_FSPIDQS 2 +#define FUNC_GPIO14_GPIO14 1 +#define FUNC_GPIO14_GPIO14_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_P_U (REG_IO_MUX_BASE +0x40) +#define FUNC_XTAL_32K_P_U0RTS 2 +#define FUNC_XTAL_32K_P_GPIO15 1 +#define FUNC_XTAL_32K_P_GPIO15_0 0 + +#define PERIPHS_IO_MUX_XTAL_32K_N_U (REG_IO_MUX_BASE +0x44) +#define FUNC_XTAL_32K_N_U0CTS 2 +#define FUNC_XTAL_32K_N_GPIO16 1 +#define FUNC_XTAL_32K_N_GPIO16_0 0 + +#define PERIPHS_IO_MUX_DAC_1_U (REG_IO_MUX_BASE +0x48) +#define FUNC_DAC_1_U1TXD 2 +#define FUNC_DAC_1_GPIO17 1 +#define FUNC_DAC_1_GPIO17_0 0 + +#define PERIPHS_IO_MUX_DAC_2_U (REG_IO_MUX_BASE +0x4c) +#define FUNC_DAC_2_CLK_OUT3 3 +#define FUNC_DAC_2_U1RXD 2 +#define FUNC_DAC_2_GPIO18 1 +#define FUNC_DAC_2_GPIO18_0 0 + +#define PERIPHS_IO_MUX_GPIO19_U (REG_IO_MUX_BASE +0x50) +#define FUNC_GPIO19_CLK_OUT2 3 +#define FUNC_GPIO19_U1RTS 2 +#define FUNC_GPIO19_GPIO19 1 +#define FUNC_GPIO19_GPIO19_0 0 + +#define PERIPHS_IO_MUX_GPIO20_U (REG_IO_MUX_BASE +0x54) +#define FUNC_GPIO20_CLK_OUT1 3 +#define FUNC_GPIO20_U1CTS 2 +#define FUNC_GPIO20_GPIO20 1 +#define FUNC_GPIO20_GPIO20_0 0 + +#define PERIPHS_IO_MUX_GPIO21_U (REG_IO_MUX_BASE +0x58) +#define FUNC_GPIO21_GPIO21 1 +#define FUNC_GPIO21_GPIO21_0 0 + +#define PERIPHS_IO_MUX_SPICS1_U (REG_IO_MUX_BASE +0x6c) +#define FUNC_SPICS1_GPIO26 1 +#define FUNC_SPICS1_SPICS1 0 + +#define PERIPHS_IO_MUX_SPIHD_U (REG_IO_MUX_BASE +0x70) +#define FUNC_SPIHD_GPIO27 1 +#define FUNC_SPIHD_SPIHD 0 + +#define PERIPHS_IO_MUX_SPIWP_U (REG_IO_MUX_BASE +0x74) +#define FUNC_SPIWP_GPIO28 1 +#define FUNC_SPIWP_SPIWP 0 + +#define PERIPHS_IO_MUX_SPICS0_U (REG_IO_MUX_BASE +0x78) +#define FUNC_SPICS0_GPIO29 1 +#define FUNC_SPICS0_SPICS0 0 + +#define PERIPHS_IO_MUX_SPICLK_U (REG_IO_MUX_BASE +0x7c) +#define FUNC_SPICLK_GPIO30 1 +#define FUNC_SPICLK_SPICLK 0 + +#define PERIPHS_IO_MUX_SPIQ_U (REG_IO_MUX_BASE +0x80) +#define FUNC_SPIQ_GPIO31 1 +#define FUNC_SPIQ_SPIQ 0 + +#define PERIPHS_IO_MUX_SPID_U (REG_IO_MUX_BASE +0x84) +#define FUNC_SPID_GPIO32 1 +#define FUNC_SPID_SPID 0 + +#define PERIPHS_IO_MUX_GPIO33_U (REG_IO_MUX_BASE +0x88) +#define FUNC_GPIO33_SPIIO4 4 +#define FUNC_GPIO33_SUBSPIHD 3 +#define FUNC_GPIO33_FSPIHD 2 +#define FUNC_GPIO33_GPIO33 1 +#define FUNC_GPIO33_GPIO33_0 0 + +#define PERIPHS_IO_MUX_GPIO34_U (REG_IO_MUX_BASE +0x8c) +#define FUNC_GPIO34_SPIIO5 4 +#define FUNC_GPIO34_SUBSPICS0 3 +#define FUNC_GPIO34_FSPICS0 2 +#define FUNC_GPIO34_GPIO34 1 +#define FUNC_GPIO34_GPIO34_0 0 + +#define PERIPHS_IO_MUX_GPIO35_U (REG_IO_MUX_BASE +0x90) +#define FUNC_GPIO35_SPIIO6 4 +#define FUNC_GPIO35_SUBSPID 3 +#define FUNC_GPIO35_FSPID 2 +#define FUNC_GPIO35_GPIO35 1 +#define FUNC_GPIO35_GPIO35_0 0 + +#define PERIPHS_IO_MUX_GPIO36_U (REG_IO_MUX_BASE +0x94) +#define FUNC_GPIO36_SPIIO7 4 +#define FUNC_GPIO36_SUBSPICLK 3 +#define FUNC_GPIO36_FSPICLK 2 +#define FUNC_GPIO36_GPIO36 1 +#define FUNC_GPIO36_GPIO36_0 0 + +#define PERIPHS_IO_MUX_GPIO37_U (REG_IO_MUX_BASE +0x98) +#define FUNC_GPIO37_SPIDQS 4 +#define FUNC_GPIO37_SUBSPIQ 3 +#define FUNC_GPIO37_FSPIQ 2 +#define FUNC_GPIO37_GPIO37 1 +#define FUNC_GPIO37_GPIO37_0 0 + +#define PERIPHS_IO_MUX_GPIO38_U (REG_IO_MUX_BASE +0x9c) +#define FUNC_GPIO38_SUBSPIWP 3 +#define FUNC_GPIO38_FSPIWP 2 +#define FUNC_GPIO38_GPIO38 1 +#define FUNC_GPIO38_GPIO38_0 0 + +#define PERIPHS_IO_MUX_MTCK_U (REG_IO_MUX_BASE +0xa0) +#define FUNC_MTCK_SUBSPICS1 3 +#define FUNC_MTCK_CLK_OUT3 2 +#define FUNC_MTCK_GPIO39 1 +#define FUNC_MTCK_MTCK 0 + +#define PERIPHS_IO_MUX_MTDO_U (REG_IO_MUX_BASE +0xa4) +#define FUNC_MTDO_CLK_OUT2 2 +#define FUNC_MTDO_GPIO40 1 +#define FUNC_MTDO_MTDO 0 + +#define PERIPHS_IO_MUX_MTDI_U (REG_IO_MUX_BASE +0xa8) +#define FUNC_MTDI_CLK_OUT1 2 +#define FUNC_MTDI_GPIO41 1 +#define FUNC_MTDI_MTDI 0 + +#define PERIPHS_IO_MUX_MTMS_U (REG_IO_MUX_BASE +0xac) +#define FUNC_MTMS_GPIO42 1 +#define FUNC_MTMS_MTMS 0 + +#define PERIPHS_IO_MUX_U0TXD_U (REG_IO_MUX_BASE +0xb0) +#define FUNC_U0TXD_CLK_OUT1 2 +#define FUNC_U0TXD_GPIO43 1 +#define FUNC_U0TXD_U0TXD 0 + +#define PERIPHS_IO_MUX_U0RXD_U (REG_IO_MUX_BASE +0xb4) +#define FUNC_U0RXD_CLK_OUT2 2 +#define FUNC_U0RXD_GPIO44 1 +#define FUNC_U0RXD_U0RXD 0 + +#define PERIPHS_IO_MUX_GPIO45_U (REG_IO_MUX_BASE +0xb8) +#define FUNC_GPIO45_GPIO45 1 +#define FUNC_GPIO45_GPIO45_0 0 + +#define PERIPHS_IO_MUX_GPIO46_U (REG_IO_MUX_BASE +0xbc) +#define FUNC_GPIO46_GPIO46 1 +#define FUNC_GPIO46_GPIO46_0 0 + +#define PERIPHS_IO_MUX_SPICLK_P_U (REG_IO_MUX_BASE +0xc0) +#define FUNC_SPICLK_P_SUBSPICLK_DIFF 2 +#define FUNC_SPICLK_P_GPIO47 1 +#define FUNC_SPICLK_P_SPICLK_DIFF 0 + +#define PERIPHS_IO_MUX_SPICLK_N_U (REG_IO_MUX_BASE +0xc4) +#define FUNC_SPICLK_N_SUBSPICLK_DIFF 2 +#define FUNC_SPICLK_N_GPIO48 1 +#define FUNC_SPICLK_N_SPICLK_DIFF 0 + + +#define IO_MUX_DATE_REG (REG_IO_MUX_BASE + 0xfc) +#define IO_MUX_DATE 0xFFFFFFFF +#define IO_MUX_DATE_S 0 +#define IO_MUX_DATE_VERSION 0x1907160 diff --git a/components/soc/soc/esp32s3/include/soc/lcd_cam_reg.h b/components/soc/soc/esp32s3/include/soc/lcd_cam_reg.h new file mode 100644 index 000000000..f43dfd6e6 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/lcd_cam_reg.h @@ -0,0 +1,840 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define LCD_CAM_LCD_CLOCK_REG (DR_REG_LCD_CAM_BASE + 0x000) +/* LCD_CAM_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to enable clk gate*/ +#define LCD_CAM_CLK_EN (BIT(31)) +#define LCD_CAM_CLK_EN_M (BIT(31)) +#define LCD_CAM_CLK_EN_V 0x1 +#define LCD_CAM_CLK_EN_S 31 +/* LCD_CAM_LCD_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ +/*description: Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ +#define LCD_CAM_LCD_CLK_SEL 0x00000003 +#define LCD_CAM_LCD_CLK_SEL_M ((LCD_CAM_LCD_CLK_SEL_V) << (LCD_CAM_LCD_CLK_SEL_S)) +#define LCD_CAM_LCD_CLK_SEL_V 0x3 +#define LCD_CAM_LCD_CLK_SEL_S 29 +/* LCD_CAM_LCD_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */ +/*description: Fractional clock divider denominator value*/ +#define LCD_CAM_LCD_CLKM_DIV_A 0x0000003F +#define LCD_CAM_LCD_CLKM_DIV_A_M ((LCD_CAM_LCD_CLKM_DIV_A_V) << (LCD_CAM_LCD_CLKM_DIV_A_S)) +#define LCD_CAM_LCD_CLKM_DIV_A_V 0x3F +#define LCD_CAM_LCD_CLKM_DIV_A_S 23 +/* LCD_CAM_LCD_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */ +/*description: Fractional clock divider numerator value*/ +#define LCD_CAM_LCD_CLKM_DIV_B 0x0000003F +#define LCD_CAM_LCD_CLKM_DIV_B_M ((LCD_CAM_LCD_CLKM_DIV_B_V) << (LCD_CAM_LCD_CLKM_DIV_B_S)) +#define LCD_CAM_LCD_CLKM_DIV_B_V 0x3F +#define LCD_CAM_LCD_CLKM_DIV_B_S 17 +/* LCD_CAM_LCD_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */ +/*description: Integral LCD clock divider value*/ +#define LCD_CAM_LCD_CLKM_DIV_NUM 0x000000FF +#define LCD_CAM_LCD_CLKM_DIV_NUM_M ((LCD_CAM_LCD_CLKM_DIV_NUM_V) << (LCD_CAM_LCD_CLKM_DIV_NUM_S)) +#define LCD_CAM_LCD_CLKM_DIV_NUM_V 0xFF +#define LCD_CAM_LCD_CLKM_DIV_NUM_S 9 +/* LCD_CAM_LCD_CK_OUT_EDGE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define LCD_CAM_LCD_CK_OUT_EDGE (BIT(8)) +#define LCD_CAM_LCD_CK_OUT_EDGE_M (BIT(8)) +#define LCD_CAM_LCD_CK_OUT_EDGE_V 0x1 +#define LCD_CAM_LCD_CK_OUT_EDGE_S 8 +/* LCD_CAM_LCD_CK_IDLE_EDGE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: 1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.*/ +#define LCD_CAM_LCD_CK_IDLE_EDGE (BIT(7)) +#define LCD_CAM_LCD_CK_IDLE_EDGE_M (BIT(7)) +#define LCD_CAM_LCD_CK_IDLE_EDGE_V 0x1 +#define LCD_CAM_LCD_CK_IDLE_EDGE_S 7 +/* LCD_CAM_LCD_CLK_EQU_SYSCLK : R/W ;bitpos:[6] ;default: 1'h1 ; */ +/*description: 1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/ +#define LCD_CAM_LCD_CLK_EQU_SYSCLK (BIT(6)) +#define LCD_CAM_LCD_CLK_EQU_SYSCLK_M (BIT(6)) +#define LCD_CAM_LCD_CLK_EQU_SYSCLK_V 0x1 +#define LCD_CAM_LCD_CLK_EQU_SYSCLK_S 6 +/* LCD_CAM_LCD_CLKCNT_N : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ +/*description: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/ +#define LCD_CAM_LCD_CLKCNT_N 0x0000003F +#define LCD_CAM_LCD_CLKCNT_N_M ((LCD_CAM_LCD_CLKCNT_N_V) << (LCD_CAM_LCD_CLKCNT_N_S)) +#define LCD_CAM_LCD_CLKCNT_N_V 0x3F +#define LCD_CAM_LCD_CLKCNT_N_S 0 + +#define LCD_CAM_CAM_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x004) +/* LCD_CAM_CAM_CLK_SEL : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ +/*description: Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ +#define LCD_CAM_CAM_CLK_SEL 0x00000003 +#define LCD_CAM_CAM_CLK_SEL_M ((LCD_CAM_CAM_CLK_SEL_V) << (LCD_CAM_CAM_CLK_SEL_S)) +#define LCD_CAM_CAM_CLK_SEL_V 0x3 +#define LCD_CAM_CAM_CLK_SEL_S 29 +/* LCD_CAM_CAM_CLKM_DIV_A : R/W ;bitpos:[28:23] ;default: 6'h0 ; */ +/*description: Fractional clock divider denominator value*/ +#define LCD_CAM_CAM_CLKM_DIV_A 0x0000003F +#define LCD_CAM_CAM_CLKM_DIV_A_M ((LCD_CAM_CAM_CLKM_DIV_A_V) << (LCD_CAM_CAM_CLKM_DIV_A_S)) +#define LCD_CAM_CAM_CLKM_DIV_A_V 0x3F +#define LCD_CAM_CAM_CLKM_DIV_A_S 23 +/* LCD_CAM_CAM_CLKM_DIV_B : R/W ;bitpos:[22:17] ;default: 6'h0 ; */ +/*description: Fractional clock divider numerator value*/ +#define LCD_CAM_CAM_CLKM_DIV_B 0x0000003F +#define LCD_CAM_CAM_CLKM_DIV_B_M ((LCD_CAM_CAM_CLKM_DIV_B_V) << (LCD_CAM_CAM_CLKM_DIV_B_S)) +#define LCD_CAM_CAM_CLKM_DIV_B_V 0x3F +#define LCD_CAM_CAM_CLKM_DIV_B_S 17 +/* LCD_CAM_CAM_CLKM_DIV_NUM : R/W ;bitpos:[16:9] ;default: 8'd4 ; */ +/*description: Integral Camera clock divider value*/ +#define LCD_CAM_CAM_CLKM_DIV_NUM 0x000000FF +#define LCD_CAM_CAM_CLKM_DIV_NUM_M ((LCD_CAM_CAM_CLKM_DIV_NUM_V) << (LCD_CAM_CAM_CLKM_DIV_NUM_S)) +#define LCD_CAM_CAM_CLKM_DIV_NUM_V 0xFF +#define LCD_CAM_CAM_CLKM_DIV_NUM_S 9 +/* LCD_CAM_CAM_VS_EOF_EN : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: 1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled + by reg_cam_rec_data_cyclelen.*/ +#define LCD_CAM_CAM_VS_EOF_EN (BIT(8)) +#define LCD_CAM_CAM_VS_EOF_EN_M (BIT(8)) +#define LCD_CAM_CAM_VS_EOF_EN_V 0x1 +#define LCD_CAM_CAM_VS_EOF_EN_S 8 +/* LCD_CAM_CAM_LINE_INT_EN : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: 1: Enable to generate CAM_HS_INT. 0: Disable.*/ +#define LCD_CAM_CAM_LINE_INT_EN (BIT(7)) +#define LCD_CAM_CAM_LINE_INT_EN_M (BIT(7)) +#define LCD_CAM_CAM_LINE_INT_EN_V 0x1 +#define LCD_CAM_CAM_LINE_INT_EN_S 7 +/* LCD_CAM_CAM_BIT_ORDER : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: 1: invert data byte order only valid in 2 byte mode. 0: Not change.*/ +#define LCD_CAM_CAM_BIT_ORDER (BIT(6)) +#define LCD_CAM_CAM_BIT_ORDER_M (BIT(6)) +#define LCD_CAM_CAM_BIT_ORDER_V 0x1 +#define LCD_CAM_CAM_BIT_ORDER_S 6 +/* LCD_CAM_CAM_BYTE_ORDER : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: 1: Change data bit order change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] + in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ +#define LCD_CAM_CAM_BYTE_ORDER (BIT(5)) +#define LCD_CAM_CAM_BYTE_ORDER_M (BIT(5)) +#define LCD_CAM_CAM_BYTE_ORDER_V 0x1 +#define LCD_CAM_CAM_BYTE_ORDER_S 5 +/* LCD_CAM_CAM_UPDATE_REG : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: 1: Update Camera registers will be cleared by hardware. 0 : Not care.*/ +#define LCD_CAM_CAM_UPDATE_REG (BIT(4)) +#define LCD_CAM_CAM_UPDATE_REG_M (BIT(4)) +#define LCD_CAM_CAM_UPDATE_REG_V 0x1 +#define LCD_CAM_CAM_UPDATE_REG_S 4 +/* LCD_CAM_CAM_VSYNC_FILTER_THRES : R/W ;bitpos:[3:1] ;default: 3'h0 ; */ +/*description: Filter threshold value for CAM_VSYNC signal.*/ +#define LCD_CAM_CAM_VSYNC_FILTER_THRES 0x00000007 +#define LCD_CAM_CAM_VSYNC_FILTER_THRES_M ((LCD_CAM_CAM_VSYNC_FILTER_THRES_V) << (LCD_CAM_CAM_VSYNC_FILTER_THRES_S)) +#define LCD_CAM_CAM_VSYNC_FILTER_THRES_V 0x7 +#define LCD_CAM_CAM_VSYNC_FILTER_THRES_S 1 +/* LCD_CAM_CAM_STOP_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: Camera stop enable signal 1: camera stops when DMA Rx FIFO is + full. 0: Not stop.*/ +#define LCD_CAM_CAM_STOP_EN (BIT(0)) +#define LCD_CAM_CAM_STOP_EN_M (BIT(0)) +#define LCD_CAM_CAM_STOP_EN_V 0x1 +#define LCD_CAM_CAM_STOP_EN_S 0 + +#define LCD_CAM_CAM_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x008) +/* LCD_CAM_CAM_AFIFO_RESET : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Camera AFIFO reset signal.*/ +#define LCD_CAM_CAM_AFIFO_RESET (BIT(31)) +#define LCD_CAM_CAM_AFIFO_RESET_M (BIT(31)) +#define LCD_CAM_CAM_AFIFO_RESET_V 0x1 +#define LCD_CAM_CAM_AFIFO_RESET_S 31 +/* LCD_CAM_CAM_RESET : WO ;bitpos:[30] ;default: 1'h0 ; */ +/*description: Camera module reset signal.*/ +#define LCD_CAM_CAM_RESET (BIT(30)) +#define LCD_CAM_CAM_RESET_M (BIT(30)) +#define LCD_CAM_CAM_RESET_V 0x1 +#define LCD_CAM_CAM_RESET_S 30 +/* LCD_CAM_CAM_START : R/W ;bitpos:[29] ;default: 1'h0 ; */ +/*description: Camera module start signal.*/ +#define LCD_CAM_CAM_START (BIT(29)) +#define LCD_CAM_CAM_START_M (BIT(29)) +#define LCD_CAM_CAM_START_V 0x1 +#define LCD_CAM_CAM_START_S 29 +/* LCD_CAM_CAM_VH_DE_MODE_EN : R/W ;bitpos:[28] ;default: 1'h0 ; */ +/*description: 1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is + 1. 0: Input control signals are CAM_DE and CAM_VSYNC*/ +#define LCD_CAM_CAM_VH_DE_MODE_EN (BIT(28)) +#define LCD_CAM_CAM_VH_DE_MODE_EN_M (BIT(28)) +#define LCD_CAM_CAM_VH_DE_MODE_EN_V 0x1 +#define LCD_CAM_CAM_VH_DE_MODE_EN_S 28 +/* LCD_CAM_CAM_VSYNC_INV : R/W ;bitpos:[27] ;default: 1'h0 ; */ +/*description: CAM_VSYNC invert enable signal valid in high level.*/ +#define LCD_CAM_CAM_VSYNC_INV (BIT(27)) +#define LCD_CAM_CAM_VSYNC_INV_M (BIT(27)) +#define LCD_CAM_CAM_VSYNC_INV_V 0x1 +#define LCD_CAM_CAM_VSYNC_INV_S 27 +/* LCD_CAM_CAM_HSYNC_INV : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: CAM_HSYNC invert enable signal valid in high level.*/ +#define LCD_CAM_CAM_HSYNC_INV (BIT(26)) +#define LCD_CAM_CAM_HSYNC_INV_M (BIT(26)) +#define LCD_CAM_CAM_HSYNC_INV_V 0x1 +#define LCD_CAM_CAM_HSYNC_INV_S 26 +/* LCD_CAM_CAM_DE_INV : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: CAM_DE invert enable signal valid in high level.*/ +#define LCD_CAM_CAM_DE_INV (BIT(25)) +#define LCD_CAM_CAM_DE_INV_M (BIT(25)) +#define LCD_CAM_CAM_DE_INV_V 0x1 +#define LCD_CAM_CAM_DE_INV_S 25 +/* LCD_CAM_CAM_2BYTE_EN : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: 1: The bit number of input data is 9~16. 0: The bit number of + input data is 0~8.*/ +#define LCD_CAM_CAM_2BYTE_EN (BIT(24)) +#define LCD_CAM_CAM_2BYTE_EN_M (BIT(24)) +#define LCD_CAM_CAM_2BYTE_EN_V 0x1 +#define LCD_CAM_CAM_2BYTE_EN_S 24 +/* LCD_CAM_CAM_VSYNC_FILTER_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: 1: Enable CAM_VSYNC filter function. 0: bypass.*/ +#define LCD_CAM_CAM_VSYNC_FILTER_EN (BIT(23)) +#define LCD_CAM_CAM_VSYNC_FILTER_EN_M (BIT(23)) +#define LCD_CAM_CAM_VSYNC_FILTER_EN_V 0x1 +#define LCD_CAM_CAM_VSYNC_FILTER_EN_S 23 +/* LCD_CAM_CAM_CLK_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: Invert the input signal CAM_PCLK. 0: Not invert.*/ +#define LCD_CAM_CAM_CLK_INV (BIT(21)) +#define LCD_CAM_CAM_CLK_INV_M (BIT(21)) +#define LCD_CAM_CAM_CLK_INV_V 0x1 +#define LCD_CAM_CAM_CLK_INV_S 21 +/* LCD_CAM_CAM_LINE_INT_NUM : R/W ;bitpos:[20:14] ;default: 7'h0 ; */ +/*description: The line number minus 1 to generate cam_hs_int.*/ +#define LCD_CAM_CAM_LINE_INT_NUM 0x0000007F +#define LCD_CAM_CAM_LINE_INT_NUM_M ((LCD_CAM_CAM_LINE_INT_NUM_V) << (LCD_CAM_CAM_LINE_INT_NUM_S)) +#define LCD_CAM_CAM_LINE_INT_NUM_V 0x7F +#define LCD_CAM_CAM_LINE_INT_NUM_S 14 +/* LCD_CAM_CAM_REC_DATA_BYTELEN : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/ +#define LCD_CAM_CAM_REC_DATA_BYTELEN 0x00003FFF +#define LCD_CAM_CAM_REC_DATA_BYTELEN_M ((LCD_CAM_CAM_REC_DATA_BYTELEN_V) << (LCD_CAM_CAM_REC_DATA_BYTELEN_S)) +#define LCD_CAM_CAM_REC_DATA_BYTELEN_V 0x3FFF +#define LCD_CAM_CAM_REC_DATA_BYTELEN_S 0 + +#define LCD_CAM_CAM_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x00C) +/* LCD_CAM_CAM_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: Bypass converter. 1: Enable converter.*/ +#define LCD_CAM_CAM_CONV_BYPASS (BIT(31)) +#define LCD_CAM_CAM_CONV_BYPASS_M (BIT(31)) +#define LCD_CAM_CAM_CONV_BYPASS_V 0x1 +#define LCD_CAM_CAM_CONV_BYPASS_S 31 +/* LCD_CAM_CAM_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: YUV to RGB. 1: RGB to YUV.*/ +#define LCD_CAM_CAM_CONV_TRANS_MODE (BIT(30)) +#define LCD_CAM_CAM_CONV_TRANS_MODE_M (BIT(30)) +#define LCD_CAM_CAM_CONV_TRANS_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_TRANS_MODE_S 30 +/* LCD_CAM_CAM_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 0: 16bits mode. 1: 8bits mode.*/ +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON (BIT(29)) +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_M (BIT(29)) +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_V 0x1 +#define LCD_CAM_CAM_CONV_MODE_8BITS_ON_S 29 +/* LCD_CAM_CAM_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full*/ +#define LCD_CAM_CAM_CONV_DATA_IN_MODE (BIT(28)) +#define LCD_CAM_CAM_CONV_DATA_IN_MODE_M (BIT(28)) +#define LCD_CAM_CAM_CONV_DATA_IN_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_DATA_IN_MODE_S 28 +/* LCD_CAM_CAM_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full*/ +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE (BIT(27)) +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_M (BIT(27)) +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_DATA_OUT_MODE_S 27 +/* LCD_CAM_CAM_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 0:BT601. 1:BT709.*/ +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE (BIT(26)) +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_M (BIT(26)) +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_V 0x1 +#define LCD_CAM_CAM_CONV_PROTOCOL_MODE_S 26 +/* LCD_CAM_CAM_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ +/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode + decides the yuv mode of Data_in*/ +#define LCD_CAM_CAM_CONV_YUV_MODE 0x00000003 +#define LCD_CAM_CAM_CONV_YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV_MODE_V) << (LCD_CAM_CAM_CONV_YUV_MODE_S)) +#define LCD_CAM_CAM_CONV_YUV_MODE_V 0x3 +#define LCD_CAM_CAM_CONV_YUV_MODE_S 24 +/* LCD_CAM_CAM_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */ +/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable + yuv2yuv mode trans_mode must be set to 1.*/ +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE 0x00000003 +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_M ((LCD_CAM_CAM_CONV_YUV2YUV_MODE_V) << (LCD_CAM_CAM_CONV_YUV2YUV_MODE_S)) +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_V 0x3 +#define LCD_CAM_CAM_CONV_YUV2YUV_MODE_S 22 +/* LCD_CAM_CAM_CONV_8BITS_DATA_INV : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1:invert every two 8bits input data. 2. disabled.*/ +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV (BIT(21)) +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_M (BIT(21)) +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_V 0x1 +#define LCD_CAM_CAM_CONV_8BITS_DATA_INV_S 21 + +#define LCD_CAM_LCD_RGB_YUV_REG (DR_REG_LCD_CAM_BASE + 0x010) +/* LCD_CAM_LCD_CONV_BYPASS : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 0: Bypass converter. 1: Enable converter.*/ +#define LCD_CAM_LCD_CONV_BYPASS (BIT(31)) +#define LCD_CAM_LCD_CONV_BYPASS_M (BIT(31)) +#define LCD_CAM_LCD_CONV_BYPASS_V 0x1 +#define LCD_CAM_LCD_CONV_BYPASS_S 31 +/* LCD_CAM_LCD_CONV_TRANS_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: YUV to RGB. 1: RGB to YUV.*/ +#define LCD_CAM_LCD_CONV_TRANS_MODE (BIT(30)) +#define LCD_CAM_LCD_CONV_TRANS_MODE_M (BIT(30)) +#define LCD_CAM_LCD_CONV_TRANS_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_TRANS_MODE_S 30 +/* LCD_CAM_LCD_CONV_MODE_8BITS_ON : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 0: 16bits mode. 1: 8bits mode.*/ +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON (BIT(29)) +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_M (BIT(29)) +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_V 0x1 +#define LCD_CAM_LCD_CONV_MODE_8BITS_ON_S 29 +/* LCD_CAM_LCD_CONV_DATA_IN_MODE : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: LIMIT or FULL mode of Data in. 0: limit. 1: full*/ +#define LCD_CAM_LCD_CONV_DATA_IN_MODE (BIT(28)) +#define LCD_CAM_LCD_CONV_DATA_IN_MODE_M (BIT(28)) +#define LCD_CAM_LCD_CONV_DATA_IN_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_DATA_IN_MODE_S 28 +/* LCD_CAM_LCD_CONV_DATA_OUT_MODE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: LIMIT or FULL mode of Data out. 0: limit. 1: full*/ +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE (BIT(27)) +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_M (BIT(27)) +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_DATA_OUT_MODE_S 27 +/* LCD_CAM_LCD_CONV_PROTOCOL_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 0:BT601. 1:BT709.*/ +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE (BIT(26)) +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_M (BIT(26)) +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_V 0x1 +#define LCD_CAM_LCD_CONV_PROTOCOL_MODE_S 26 +/* LCD_CAM_LCD_CONV_YUV_MODE : R/W ;bitpos:[25:24] ;default: 2'b0 ; */ +/*description: 0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode + decides the yuv mode of Data_in*/ +#define LCD_CAM_LCD_CONV_YUV_MODE 0x00000003 +#define LCD_CAM_LCD_CONV_YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV_MODE_V) << (LCD_CAM_LCD_CONV_YUV_MODE_S)) +#define LCD_CAM_LCD_CONV_YUV_MODE_V 0x3 +#define LCD_CAM_LCD_CONV_YUV_MODE_S 24 +/* LCD_CAM_LCD_CONV_YUV2YUV_MODE : R/W ;bitpos:[23:22] ;default: 2'd3 ; */ +/*description: 0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable + yuv2yuv mode trans_mode must be set to 1.*/ +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE 0x00000003 +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_M ((LCD_CAM_LCD_CONV_YUV2YUV_MODE_V) << (LCD_CAM_LCD_CONV_YUV2YUV_MODE_S)) +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_V 0x3 +#define LCD_CAM_LCD_CONV_YUV2YUV_MODE_S 22 +/* LCD_CAM_LCD_CONV_TXTORX : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 0: txtorx mode off. 1: txtorx mode on.*/ +#define LCD_CAM_LCD_CONV_TXTORX (BIT(21)) +#define LCD_CAM_LCD_CONV_TXTORX_M (BIT(21)) +#define LCD_CAM_LCD_CONV_TXTORX_V 0x1 +#define LCD_CAM_LCD_CONV_TXTORX_S 21 +/* LCD_CAM_LCD_CONV_8BITS_DATA_INV : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: 1:invert every two 8bits input data. 2. disabled.*/ +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV (BIT(20)) +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_M (BIT(20)) +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_V 0x1 +#define LCD_CAM_LCD_CONV_8BITS_DATA_INV_S 20 + +#define LCD_CAM_LCD_USER_REG (DR_REG_LCD_CAM_BASE + 0x014) +/* LCD_CAM_LCD_CMD_2_CYCLE_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: The cycle length of command phase*/ +#define LCD_CAM_LCD_CMD_2_CYCLE_EN (BIT(31)) +#define LCD_CAM_LCD_CMD_2_CYCLE_EN_M (BIT(31)) +#define LCD_CAM_LCD_CMD_2_CYCLE_EN_V 0x1 +#define LCD_CAM_LCD_CMD_2_CYCLE_EN_S 31 +/* LCD_CAM_LCD_DUMMY_CYCLELEN : R/W ;bitpos:[30:29] ;default: 2'b0 ; */ +/*description: The dummy cycle length minus 1.*/ +#define LCD_CAM_LCD_DUMMY_CYCLELEN 0x00000003 +#define LCD_CAM_LCD_DUMMY_CYCLELEN_M ((LCD_CAM_LCD_DUMMY_CYCLELEN_V) << (LCD_CAM_LCD_DUMMY_CYCLELEN_S)) +#define LCD_CAM_LCD_DUMMY_CYCLELEN_V 0x3 +#define LCD_CAM_LCD_DUMMY_CYCLELEN_S 29 +/* LCD_CAM_LCD_RESET : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: The value of command.*/ +#define LCD_CAM_LCD_RESET (BIT(28)) +#define LCD_CAM_LCD_RESET_M (BIT(28)) +#define LCD_CAM_LCD_RESET_V 0x1 +#define LCD_CAM_LCD_RESET_S 28 +/* LCD_CAM_LCD_START : R/W ;bitpos:[27] ;default: 1'h0 ; */ +/*description: LCD start sending data enable signal valid in high level.*/ +#define LCD_CAM_LCD_START (BIT(27)) +#define LCD_CAM_LCD_START_M (BIT(27)) +#define LCD_CAM_LCD_START_V 0x1 +#define LCD_CAM_LCD_START_S 27 +/* LCD_CAM_LCD_CMD : R/W ;bitpos:[26] ;default: 1'h0 ; */ +/*description: 1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/ +#define LCD_CAM_LCD_CMD (BIT(26)) +#define LCD_CAM_LCD_CMD_M (BIT(26)) +#define LCD_CAM_LCD_CMD_V 0x1 +#define LCD_CAM_LCD_CMD_S 26 +/* LCD_CAM_LCD_DUMMY : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: 1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/ +#define LCD_CAM_LCD_DUMMY (BIT(25)) +#define LCD_CAM_LCD_DUMMY_M (BIT(25)) +#define LCD_CAM_LCD_DUMMY_V 0x1 +#define LCD_CAM_LCD_DUMMY_S 25 +/* LCD_CAM_LCD_DOUT : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: 1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/ +#define LCD_CAM_LCD_DOUT (BIT(24)) +#define LCD_CAM_LCD_DOUT_M (BIT(24)) +#define LCD_CAM_LCD_DOUT_V 0x1 +#define LCD_CAM_LCD_DOUT_S 24 +/* LCD_CAM_LCD_2BYTE_EN : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: 1: The bit number of output LCD data is 9~16. 0: The bit number + of output LCD data is 0~8.*/ +#define LCD_CAM_LCD_2BYTE_EN (BIT(23)) +#define LCD_CAM_LCD_2BYTE_EN_M (BIT(23)) +#define LCD_CAM_LCD_2BYTE_EN_V 0x1 +#define LCD_CAM_LCD_2BYTE_EN_S 23 +/* LCD_CAM_LCD_BYTE_ORDER : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: 1: invert data byte order only valid in 2 byte mode. 0: Not change.*/ +#define LCD_CAM_LCD_BYTE_ORDER (BIT(22)) +#define LCD_CAM_LCD_BYTE_ORDER_M (BIT(22)) +#define LCD_CAM_LCD_BYTE_ORDER_V 0x1 +#define LCD_CAM_LCD_BYTE_ORDER_S 22 +/* LCD_CAM_LCD_BIT_ORDER : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: 1: Change data bit order change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] + in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ +#define LCD_CAM_LCD_BIT_ORDER (BIT(21)) +#define LCD_CAM_LCD_BIT_ORDER_M (BIT(21)) +#define LCD_CAM_LCD_BIT_ORDER_V 0x1 +#define LCD_CAM_LCD_BIT_ORDER_S 21 +/* LCD_CAM_LCD_UPDATE_REG : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: 1: Update LCD registers will be cleared by hardware. 0 : Not care.*/ +#define LCD_CAM_LCD_UPDATE_REG (BIT(20)) +#define LCD_CAM_LCD_UPDATE_REG_M (BIT(20)) +#define LCD_CAM_LCD_UPDATE_REG_V 0x1 +#define LCD_CAM_LCD_UPDATE_REG_S 20 +/* LCD_CAM_LCD_8BITS_ORDER : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: 1: invert every two data byte valid in 1 byte mode. 0: Not change.*/ +#define LCD_CAM_LCD_8BITS_ORDER (BIT(19)) +#define LCD_CAM_LCD_8BITS_ORDER_M (BIT(19)) +#define LCD_CAM_LCD_8BITS_ORDER_V 0x1 +#define LCD_CAM_LCD_8BITS_ORDER_S 19 +/* LCD_CAM_LCD_ALWAYS_OUT_EN : R/W ;bitpos:[13] ;default: 1'h0 ; */ +/*description: LCD always output when LCD is in LCD_DOUT state unless reg_lcd_start + is cleared or reg_lcd_reset is set.*/ +#define LCD_CAM_LCD_ALWAYS_OUT_EN (BIT(13)) +#define LCD_CAM_LCD_ALWAYS_OUT_EN_M (BIT(13)) +#define LCD_CAM_LCD_ALWAYS_OUT_EN_V 0x1 +#define LCD_CAM_LCD_ALWAYS_OUT_EN_S 13 +/* LCD_CAM_LCD_DOUT_CYCLELEN : R/W ;bitpos:[12:0] ;default: 13'h1 ; */ +/*description: The output data cycles minus 1 of LCD module.*/ +#define LCD_CAM_LCD_DOUT_CYCLELEN 0x00001FFF +#define LCD_CAM_LCD_DOUT_CYCLELEN_M ((LCD_CAM_LCD_DOUT_CYCLELEN_V) << (LCD_CAM_LCD_DOUT_CYCLELEN_S)) +#define LCD_CAM_LCD_DOUT_CYCLELEN_V 0x1FFF +#define LCD_CAM_LCD_DOUT_CYCLELEN_S 0 + +#define LCD_CAM_LCD_MISC_REG (DR_REG_LCD_CAM_BASE + 0x018) +/* LCD_CAM_LCD_CD_IDLE_EDGE : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: The default value of LCD_CD.*/ +#define LCD_CAM_LCD_CD_IDLE_EDGE (BIT(31)) +#define LCD_CAM_LCD_CD_IDLE_EDGE_M (BIT(31)) +#define LCD_CAM_LCD_CD_IDLE_EDGE_V 0x1 +#define LCD_CAM_LCD_CD_IDLE_EDGE_S 31 +/* LCD_CAM_LCD_CD_CMD_SET : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD + state. 0: LCD_CD = reg_cd_idle_edge.*/ +#define LCD_CAM_LCD_CD_CMD_SET (BIT(30)) +#define LCD_CAM_LCD_CD_CMD_SET_M (BIT(30)) +#define LCD_CAM_LCD_CD_CMD_SET_V 0x1 +#define LCD_CAM_LCD_CD_CMD_SET_S 30 +/* LCD_CAM_LCD_CD_DUMMY_SET : R/W ;bitpos:[29] ;default: 1'h0 ; */ +/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY + state. 0: LCD_CD = reg_cd_idle_edge.*/ +#define LCD_CAM_LCD_CD_DUMMY_SET (BIT(29)) +#define LCD_CAM_LCD_CD_DUMMY_SET_M (BIT(29)) +#define LCD_CAM_LCD_CD_DUMMY_SET_V 0x1 +#define LCD_CAM_LCD_CD_DUMMY_SET_S 29 +/* LCD_CAM_LCD_CD_DATA_SET : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT + state. 0: LCD_CD = reg_cd_idle_edge.*/ +#define LCD_CAM_LCD_CD_DATA_SET (BIT(28)) +#define LCD_CAM_LCD_CD_DATA_SET_M (BIT(28)) +#define LCD_CAM_LCD_CD_DATA_SET_V 0x1 +#define LCD_CAM_LCD_CD_DATA_SET_S 28 +/* LCD_CAM_LCD_AFIFO_RESET : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: LCD AFIFO reset signal.*/ +#define LCD_CAM_LCD_AFIFO_RESET (BIT(27)) +#define LCD_CAM_LCD_AFIFO_RESET_M (BIT(27)) +#define LCD_CAM_LCD_AFIFO_RESET_V 0x1 +#define LCD_CAM_LCD_AFIFO_RESET_S 27 +/* LCD_CAM_LCD_BK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: Enable blank region when LCD sends data out. 0: No blank region.*/ +#define LCD_CAM_LCD_BK_EN (BIT(26)) +#define LCD_CAM_LCD_BK_EN_M (BIT(26)) +#define LCD_CAM_LCD_BK_EN_V 0x1 +#define LCD_CAM_LCD_BK_EN_S 26 +/* LCD_CAM_LCD_NEXT_FRAME_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: Send the next frame data when the current frame is sent out. + 0: LCD stops when the current frame is sent out.*/ +#define LCD_CAM_LCD_NEXT_FRAME_EN (BIT(25)) +#define LCD_CAM_LCD_NEXT_FRAME_EN_M (BIT(25)) +#define LCD_CAM_LCD_NEXT_FRAME_EN_V 0x1 +#define LCD_CAM_LCD_NEXT_FRAME_EN_S 25 +/* LCD_CAM_LCD_VBK_CYCLELEN : R/W ;bitpos:[24:12] ;default: 13'h0 ; */ +/*description: The vertical back blank region cycle length minus 1 in LCD RGB + mode or the hold time cycle length in LCD non-RGB mode.*/ +#define LCD_CAM_LCD_VBK_CYCLELEN 0x00001FFF +#define LCD_CAM_LCD_VBK_CYCLELEN_M ((LCD_CAM_LCD_VBK_CYCLELEN_V) << (LCD_CAM_LCD_VBK_CYCLELEN_S)) +#define LCD_CAM_LCD_VBK_CYCLELEN_V 0x1FFF +#define LCD_CAM_LCD_VBK_CYCLELEN_S 12 +/* LCD_CAM_LCD_VFK_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'h3 ; */ +/*description: The setup cycle length minus 1 in LCD non-RGB mode.*/ +#define LCD_CAM_LCD_VFK_CYCLELEN 0x0000003F +#define LCD_CAM_LCD_VFK_CYCLELEN_M ((LCD_CAM_LCD_VFK_CYCLELEN_V) << (LCD_CAM_LCD_VFK_CYCLELEN_S)) +#define LCD_CAM_LCD_VFK_CYCLELEN_V 0x3F +#define LCD_CAM_LCD_VFK_CYCLELEN_S 6 +/* LCD_CAM_LCD_AFIFO_THRESHOLD_NUM : R/W ;bitpos:[5:1] ;default: 5'd11 ; */ +/*description: The awfull threshold number of lcd_afifo.*/ +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM 0x0000001F +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_M ((LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V) << (LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S)) +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_V 0x1F +#define LCD_CAM_LCD_AFIFO_THRESHOLD_NUM_S 1 + +#define LCD_CAM_LCD_CTRL_REG (DR_REG_LCD_CAM_BASE + 0x01C) +/* LCD_CAM_LCD_RGB_MODE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: Enable reg mode input vsync*/ +#define LCD_CAM_LCD_RGB_MODE_EN (BIT(31)) +#define LCD_CAM_LCD_RGB_MODE_EN_M (BIT(31)) +#define LCD_CAM_LCD_RGB_MODE_EN_V 0x1 +#define LCD_CAM_LCD_RGB_MODE_EN_S 31 +/* LCD_CAM_LCD_VT_HEIGHT : R/W ;bitpos:[30:21] ;default: 10'd0 ; */ +/*description: It is the vertical total height of a frame.*/ +#define LCD_CAM_LCD_VT_HEIGHT 0x000003FF +#define LCD_CAM_LCD_VT_HEIGHT_M ((LCD_CAM_LCD_VT_HEIGHT_V) << (LCD_CAM_LCD_VT_HEIGHT_S)) +#define LCD_CAM_LCD_VT_HEIGHT_V 0x3FF +#define LCD_CAM_LCD_VT_HEIGHT_S 21 +/* LCD_CAM_LCD_VA_HEIGHT : R/W ;bitpos:[20:11] ;default: 10'd0 ; */ +/*description: It is the vertical active height of a frame.*/ +#define LCD_CAM_LCD_VA_HEIGHT 0x000003FF +#define LCD_CAM_LCD_VA_HEIGHT_M ((LCD_CAM_LCD_VA_HEIGHT_V) << (LCD_CAM_LCD_VA_HEIGHT_S)) +#define LCD_CAM_LCD_VA_HEIGHT_V 0x3FF +#define LCD_CAM_LCD_VA_HEIGHT_S 11 +/* LCD_CAM_LCD_HB_FRONT : R/W ;bitpos:[10:0] ;default: 11'd0 ; */ +/*description: It is the horizontal blank front porch of a frame.*/ +#define LCD_CAM_LCD_HB_FRONT 0x000007FF +#define LCD_CAM_LCD_HB_FRONT_M ((LCD_CAM_LCD_HB_FRONT_V) << (LCD_CAM_LCD_HB_FRONT_S)) +#define LCD_CAM_LCD_HB_FRONT_V 0x7FF +#define LCD_CAM_LCD_HB_FRONT_S 0 + +#define LCD_CAM_LCD_CTRL1_REG (DR_REG_LCD_CAM_BASE + 0x020) +/* LCD_CAM_LCD_HT_WIDTH : R/W ;bitpos:[31:20] ;default: 12'd0 ; */ +/*description: It is the horizontal total width of a frame.*/ +#define LCD_CAM_LCD_HT_WIDTH 0x00000FFF +#define LCD_CAM_LCD_HT_WIDTH_M ((LCD_CAM_LCD_HT_WIDTH_V) << (LCD_CAM_LCD_HT_WIDTH_S)) +#define LCD_CAM_LCD_HT_WIDTH_V 0xFFF +#define LCD_CAM_LCD_HT_WIDTH_S 20 +/* LCD_CAM_LCD_HA_WIDTH : R/W ;bitpos:[19:8] ;default: 12'd0 ; */ +/*description: It is the horizontal active width of a frame.*/ +#define LCD_CAM_LCD_HA_WIDTH 0x00000FFF +#define LCD_CAM_LCD_HA_WIDTH_M ((LCD_CAM_LCD_HA_WIDTH_V) << (LCD_CAM_LCD_HA_WIDTH_S)) +#define LCD_CAM_LCD_HA_WIDTH_V 0xFFF +#define LCD_CAM_LCD_HA_WIDTH_S 8 +/* LCD_CAM_LCD_VB_FRONT : R/W ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: It is the vertical blank front porch of a frame.*/ +#define LCD_CAM_LCD_VB_FRONT 0x000000FF +#define LCD_CAM_LCD_VB_FRONT_M ((LCD_CAM_LCD_VB_FRONT_V) << (LCD_CAM_LCD_VB_FRONT_S)) +#define LCD_CAM_LCD_VB_FRONT_V 0xFF +#define LCD_CAM_LCD_VB_FRONT_S 0 + +#define LCD_CAM_LCD_CTRL2_REG (DR_REG_LCD_CAM_BASE + 0x024) +/* LCD_CAM_LCD_HSYNC_POSITION : R/W ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: It is the position of LCD_HSYNC active pulse in a line.*/ +#define LCD_CAM_LCD_HSYNC_POSITION 0x000000FF +#define LCD_CAM_LCD_HSYNC_POSITION_M ((LCD_CAM_LCD_HSYNC_POSITION_V) << (LCD_CAM_LCD_HSYNC_POSITION_S)) +#define LCD_CAM_LCD_HSYNC_POSITION_V 0xFF +#define LCD_CAM_LCD_HSYNC_POSITION_S 24 +/* LCD_CAM_LCD_HSYNC_IDLE_POL : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: It is the idle value of LCD_HSYNC.*/ +#define LCD_CAM_LCD_HSYNC_IDLE_POL (BIT(23)) +#define LCD_CAM_LCD_HSYNC_IDLE_POL_M (BIT(23)) +#define LCD_CAM_LCD_HSYNC_IDLE_POL_V 0x1 +#define LCD_CAM_LCD_HSYNC_IDLE_POL_S 23 +/* LCD_CAM_LCD_HSYNC_WIDTH : R/W ;bitpos:[22:16] ;default: 7'd1 ; */ +/*description: It is the position of LCD_HSYNC active pulse in a line.*/ +#define LCD_CAM_LCD_HSYNC_WIDTH 0x0000007F +#define LCD_CAM_LCD_HSYNC_WIDTH_M ((LCD_CAM_LCD_HSYNC_WIDTH_V) << (LCD_CAM_LCD_HSYNC_WIDTH_S)) +#define LCD_CAM_LCD_HSYNC_WIDTH_V 0x7F +#define LCD_CAM_LCD_HSYNC_WIDTH_S 16 +/* LCD_CAM_LCD_HS_BLANK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB + mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode.*/ +#define LCD_CAM_LCD_HS_BLANK_EN (BIT(9)) +#define LCD_CAM_LCD_HS_BLANK_EN_M (BIT(9)) +#define LCD_CAM_LCD_HS_BLANK_EN_V 0x1 +#define LCD_CAM_LCD_HS_BLANK_EN_S 9 +/* LCD_CAM_LCD_DE_IDLE_POL : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: It is the idle value of LCD_DE.*/ +#define LCD_CAM_LCD_DE_IDLE_POL (BIT(8)) +#define LCD_CAM_LCD_DE_IDLE_POL_M (BIT(8)) +#define LCD_CAM_LCD_DE_IDLE_POL_V 0x1 +#define LCD_CAM_LCD_DE_IDLE_POL_S 8 +/* LCD_CAM_LCD_VSYNC_IDLE_POL : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: It is the idle value of LCD_VSYNC.*/ +#define LCD_CAM_LCD_VSYNC_IDLE_POL (BIT(7)) +#define LCD_CAM_LCD_VSYNC_IDLE_POL_M (BIT(7)) +#define LCD_CAM_LCD_VSYNC_IDLE_POL_V 0x1 +#define LCD_CAM_LCD_VSYNC_IDLE_POL_S 7 +/* LCD_CAM_LCD_VSYNC_WIDTH : R/W ;bitpos:[6:0] ;default: 7'd1 ; */ +/*description: It is the position of LCD_VSYNC active pulse in a line.*/ +#define LCD_CAM_LCD_VSYNC_WIDTH 0x0000007F +#define LCD_CAM_LCD_VSYNC_WIDTH_M ((LCD_CAM_LCD_VSYNC_WIDTH_V) << (LCD_CAM_LCD_VSYNC_WIDTH_S)) +#define LCD_CAM_LCD_VSYNC_WIDTH_V 0x7F +#define LCD_CAM_LCD_VSYNC_WIDTH_S 0 + +#define LCD_CAM_LCD_CMD_VAL_REG (DR_REG_LCD_CAM_BASE + 0x028) +/* LCD_CAM_LCD_CMD_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: The LCD write command value.*/ +#define LCD_CAM_LCD_CMD_VALUE 0xFFFFFFFF +#define LCD_CAM_LCD_CMD_VALUE_M ((LCD_CAM_LCD_CMD_VALUE_V) << (LCD_CAM_LCD_CMD_VALUE_S)) +#define LCD_CAM_LCD_CMD_VALUE_V 0xFFFFFFFF +#define LCD_CAM_LCD_CMD_VALUE_S 0 + +#define LCD_CAM_LCD_DLY_MODE_REG (DR_REG_LCD_CAM_BASE + 0x030) +/* LCD_CAM_LCD_VSYNC_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: The output LCD_VSYNC is delayed by module clock LCD_CLK*/ +#define LCD_CAM_LCD_VSYNC_MODE 0x00000003 +#define LCD_CAM_LCD_VSYNC_MODE_M ((LCD_CAM_LCD_VSYNC_MODE_V) << (LCD_CAM_LCD_VSYNC_MODE_S)) +#define LCD_CAM_LCD_VSYNC_MODE_V 0x3 +#define LCD_CAM_LCD_VSYNC_MODE_S 6 +/* LCD_CAM_LCD_HSYNC_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: The output LCD_HSYNC is delayed by module clock LCD_CLK*/ +#define LCD_CAM_LCD_HSYNC_MODE 0x00000003 +#define LCD_CAM_LCD_HSYNC_MODE_M ((LCD_CAM_LCD_HSYNC_MODE_V) << (LCD_CAM_LCD_HSYNC_MODE_S)) +#define LCD_CAM_LCD_HSYNC_MODE_V 0x3 +#define LCD_CAM_LCD_HSYNC_MODE_S 4 +/* LCD_CAM_LCD_DE_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: The output LCD_DE is delayed by module clock LCD_CLK*/ +#define LCD_CAM_LCD_DE_MODE 0x00000003 +#define LCD_CAM_LCD_DE_MODE_M ((LCD_CAM_LCD_DE_MODE_V) << (LCD_CAM_LCD_DE_MODE_S)) +#define LCD_CAM_LCD_DE_MODE_V 0x3 +#define LCD_CAM_LCD_DE_MODE_S 2 +/* LCD_CAM_LCD_CD_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: The output LCD_CD is delayed by module clock LCD_CLK*/ +#define LCD_CAM_LCD_CD_MODE 0x00000003 +#define LCD_CAM_LCD_CD_MODE_M ((LCD_CAM_LCD_CD_MODE_V) << (LCD_CAM_LCD_CD_MODE_S)) +#define LCD_CAM_LCD_CD_MODE_V 0x3 +#define LCD_CAM_LCD_CD_MODE_S 0 + +#define LCD_CAM_LCD_DATA_DOUT_MODE_REG (DR_REG_LCD_CAM_BASE + 0x038) +/* LCD_CAM_DOUT15_MODE : R/W ;bitpos:[31:30] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT15_MODE 0x00000003 +#define LCD_CAM_DOUT15_MODE_M ((LCD_CAM_DOUT15_MODE_V) << (LCD_CAM_DOUT15_MODE_S)) +#define LCD_CAM_DOUT15_MODE_V 0x3 +#define LCD_CAM_DOUT15_MODE_S 30 +/* LCD_CAM_DOUT14_MODE : R/W ;bitpos:[29:28] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT14_MODE 0x00000003 +#define LCD_CAM_DOUT14_MODE_M ((LCD_CAM_DOUT14_MODE_V) << (LCD_CAM_DOUT14_MODE_S)) +#define LCD_CAM_DOUT14_MODE_V 0x3 +#define LCD_CAM_DOUT14_MODE_S 28 +/* LCD_CAM_DOUT13_MODE : R/W ;bitpos:[27:26] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT13_MODE 0x00000003 +#define LCD_CAM_DOUT13_MODE_M ((LCD_CAM_DOUT13_MODE_V) << (LCD_CAM_DOUT13_MODE_S)) +#define LCD_CAM_DOUT13_MODE_V 0x3 +#define LCD_CAM_DOUT13_MODE_S 26 +/* LCD_CAM_DOUT12_MODE : R/W ;bitpos:[25:24] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT12_MODE 0x00000003 +#define LCD_CAM_DOUT12_MODE_M ((LCD_CAM_DOUT12_MODE_V) << (LCD_CAM_DOUT12_MODE_S)) +#define LCD_CAM_DOUT12_MODE_V 0x3 +#define LCD_CAM_DOUT12_MODE_S 24 +/* LCD_CAM_DOUT11_MODE : R/W ;bitpos:[23:22] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT11_MODE 0x00000003 +#define LCD_CAM_DOUT11_MODE_M ((LCD_CAM_DOUT11_MODE_V) << (LCD_CAM_DOUT11_MODE_S)) +#define LCD_CAM_DOUT11_MODE_V 0x3 +#define LCD_CAM_DOUT11_MODE_S 22 +/* LCD_CAM_DOUT10_MODE : R/W ;bitpos:[21:20] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT10_MODE 0x00000003 +#define LCD_CAM_DOUT10_MODE_M ((LCD_CAM_DOUT10_MODE_V) << (LCD_CAM_DOUT10_MODE_S)) +#define LCD_CAM_DOUT10_MODE_V 0x3 +#define LCD_CAM_DOUT10_MODE_S 20 +/* LCD_CAM_DOUT9_MODE : R/W ;bitpos:[19:18] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT9_MODE 0x00000003 +#define LCD_CAM_DOUT9_MODE_M ((LCD_CAM_DOUT9_MODE_V) << (LCD_CAM_DOUT9_MODE_S)) +#define LCD_CAM_DOUT9_MODE_V 0x3 +#define LCD_CAM_DOUT9_MODE_S 18 +/* LCD_CAM_DOUT8_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT8_MODE 0x00000003 +#define LCD_CAM_DOUT8_MODE_M ((LCD_CAM_DOUT8_MODE_V) << (LCD_CAM_DOUT8_MODE_S)) +#define LCD_CAM_DOUT8_MODE_V 0x3 +#define LCD_CAM_DOUT8_MODE_S 16 +/* LCD_CAM_DOUT7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT7_MODE 0x00000003 +#define LCD_CAM_DOUT7_MODE_M ((LCD_CAM_DOUT7_MODE_V) << (LCD_CAM_DOUT7_MODE_S)) +#define LCD_CAM_DOUT7_MODE_V 0x3 +#define LCD_CAM_DOUT7_MODE_S 14 +/* LCD_CAM_DOUT6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT6_MODE 0x00000003 +#define LCD_CAM_DOUT6_MODE_M ((LCD_CAM_DOUT6_MODE_V) << (LCD_CAM_DOUT6_MODE_S)) +#define LCD_CAM_DOUT6_MODE_V 0x3 +#define LCD_CAM_DOUT6_MODE_S 12 +/* LCD_CAM_DOUT5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT5_MODE 0x00000003 +#define LCD_CAM_DOUT5_MODE_M ((LCD_CAM_DOUT5_MODE_V) << (LCD_CAM_DOUT5_MODE_S)) +#define LCD_CAM_DOUT5_MODE_V 0x3 +#define LCD_CAM_DOUT5_MODE_S 10 +/* LCD_CAM_DOUT4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT4_MODE 0x00000003 +#define LCD_CAM_DOUT4_MODE_M ((LCD_CAM_DOUT4_MODE_V) << (LCD_CAM_DOUT4_MODE_S)) +#define LCD_CAM_DOUT4_MODE_V 0x3 +#define LCD_CAM_DOUT4_MODE_S 8 +/* LCD_CAM_DOUT3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT3_MODE 0x00000003 +#define LCD_CAM_DOUT3_MODE_M ((LCD_CAM_DOUT3_MODE_V) << (LCD_CAM_DOUT3_MODE_S)) +#define LCD_CAM_DOUT3_MODE_V 0x3 +#define LCD_CAM_DOUT3_MODE_S 6 +/* LCD_CAM_DOUT2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT2_MODE 0x00000003 +#define LCD_CAM_DOUT2_MODE_M ((LCD_CAM_DOUT2_MODE_V) << (LCD_CAM_DOUT2_MODE_S)) +#define LCD_CAM_DOUT2_MODE_V 0x3 +#define LCD_CAM_DOUT2_MODE_S 4 +/* LCD_CAM_DOUT1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT1_MODE 0x00000003 +#define LCD_CAM_DOUT1_MODE_M ((LCD_CAM_DOUT1_MODE_V) << (LCD_CAM_DOUT1_MODE_S)) +#define LCD_CAM_DOUT1_MODE_V 0x3 +#define LCD_CAM_DOUT1_MODE_S 2 +/* LCD_CAM_DOUT0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: The output data bit $n is delayed by module clock LCD_CLK*/ +#define LCD_CAM_DOUT0_MODE 0x00000003 +#define LCD_CAM_DOUT0_MODE_M ((LCD_CAM_DOUT0_MODE_V) << (LCD_CAM_DOUT0_MODE_S)) +#define LCD_CAM_DOUT0_MODE_V 0x3 +#define LCD_CAM_DOUT0_MODE_S 0 + +#define LCD_CAM_LC_DMA_INT_ENA_REG (DR_REG_LCD_CAM_BASE + 0x064) +/* LCD_CAM_CAM_HS_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for Camera line interrupt.*/ +#define LCD_CAM_CAM_HS_INT_ENA (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ENA_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ENA_V 0x1 +#define LCD_CAM_CAM_HS_INT_ENA_S 3 +/* LCD_CAM_CAM_VSYNC_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for Camera frame end interrupt.*/ +#define LCD_CAM_CAM_VSYNC_INT_ENA (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ENA_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ENA_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_ENA_S 2 +/* LCD_CAM_LCD_TRANS_DONE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for lcd transfer end interrupt.*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_ENA_S 1 +/* LCD_CAM_LCD_VSYNC_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for LCD frame end interrupt.*/ +#define LCD_CAM_LCD_VSYNC_INT_ENA (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ENA_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ENA_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_ENA_S 0 + +#define LCD_CAM_LC_DMA_INT_RAW_REG (DR_REG_LCD_CAM_BASE + 0x068) +/* LCD_CAM_CAM_HS_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for Camera line interrupt.*/ +#define LCD_CAM_CAM_HS_INT_RAW (BIT(3)) +#define LCD_CAM_CAM_HS_INT_RAW_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_RAW_V 0x1 +#define LCD_CAM_CAM_HS_INT_RAW_S 3 +/* LCD_CAM_CAM_VSYNC_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for Camera frame end interrupt.*/ +#define LCD_CAM_CAM_VSYNC_INT_RAW (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_RAW_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_RAW_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_RAW_S 2 +/* LCD_CAM_LCD_TRANS_DONE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The raw bit for lcd transfer end interrupt.*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_RAW_S 1 +/* LCD_CAM_LCD_VSYNC_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The raw bit for LCD frame end interrupt.*/ +#define LCD_CAM_LCD_VSYNC_INT_RAW (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_RAW_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_RAW_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_RAW_S 0 + +#define LCD_CAM_LC_DMA_INT_ST_REG (DR_REG_LCD_CAM_BASE + 0x06C) +/* LCD_CAM_CAM_HS_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for Camera transfer end interrupt.*/ +#define LCD_CAM_CAM_HS_INT_ST (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ST_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_ST_V 0x1 +#define LCD_CAM_CAM_HS_INT_ST_S 3 +/* LCD_CAM_CAM_VSYNC_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for Camera frame end interrupt.*/ +#define LCD_CAM_CAM_VSYNC_INT_ST (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ST_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_ST_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_ST_S 2 +/* LCD_CAM_LCD_TRANS_DONE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for lcd transfer end interrupt.*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_ST (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ST_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_ST_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_ST_S 1 +/* LCD_CAM_LCD_VSYNC_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for LCD frame end interrupt.*/ +#define LCD_CAM_LCD_VSYNC_INT_ST (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ST_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_ST_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_ST_S 0 + +#define LCD_CAM_LC_DMA_INT_CLR_REG (DR_REG_LCD_CAM_BASE + 0x070) +/* LCD_CAM_CAM_HS_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for Camera line interrupt.*/ +#define LCD_CAM_CAM_HS_INT_CLR (BIT(3)) +#define LCD_CAM_CAM_HS_INT_CLR_M (BIT(3)) +#define LCD_CAM_CAM_HS_INT_CLR_V 0x1 +#define LCD_CAM_CAM_HS_INT_CLR_S 3 +/* LCD_CAM_CAM_VSYNC_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for Camera frame end interrupt.*/ +#define LCD_CAM_CAM_VSYNC_INT_CLR (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_CLR_M (BIT(2)) +#define LCD_CAM_CAM_VSYNC_INT_CLR_V 0x1 +#define LCD_CAM_CAM_VSYNC_INT_CLR_S 2 +/* LCD_CAM_LCD_TRANS_DONE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for lcd transfer end interrupt.*/ +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_M (BIT(1)) +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_V 0x1 +#define LCD_CAM_LCD_TRANS_DONE_INT_CLR_S 1 +/* LCD_CAM_LCD_VSYNC_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for LCD frame end interrupt.*/ +#define LCD_CAM_LCD_VSYNC_INT_CLR (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_CLR_M (BIT(0)) +#define LCD_CAM_LCD_VSYNC_INT_CLR_V 0x1 +#define LCD_CAM_LCD_VSYNC_INT_CLR_S 0 + +#define LCD_CAM_LC_DATE_REG (DR_REG_LCD_CAM_BASE + 0x0FC) +/* LCD_CAM_LC_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003020 ; */ +/*description: LCD_CAM version control register*/ +#define LCD_CAM_LC_DATE 0x0FFFFFFF +#define LCD_CAM_LC_DATE_M ((LCD_CAM_LC_DATE_V) << (LCD_CAM_LC_DATE_S)) +#define LCD_CAM_LC_DATE_V 0xFFFFFFF +#define LCD_CAM_LC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/lcd_cam_struct.h b/components/soc/soc/esp32s3/include/soc/lcd_cam_struct.h new file mode 100644 index 000000000..397a89671 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/lcd_cam_struct.h @@ -0,0 +1,300 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t lcd_clkcnt_n: 6; /*f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1) when reg_clk_equ_sysclk is 0.*/ + uint32_t lcd_clk_equ_sysclk: 1; /*1: f_LCD_PCLK = f_LCD_CLK. 0: f_LCD_PCLK = f_LCD_CLK / (reg_clkcnt_N + 1).*/ + uint32_t lcd_ck_idle_edge: 1; /*1: LCD_PCLK line is high when idle 0: LCD_PCLK line is low when idle.*/ + uint32_t lcd_ck_out_edge: 1; + uint32_t lcd_clkm_div_num: 8; /*Integral LCD clock divider value*/ + uint32_t lcd_clkm_div_b: 6; /*Fractional clock divider numerator value*/ + uint32_t lcd_clkm_div_a: 6; /*Fractional clock divider denominator value*/ + uint32_t lcd_clk_sel: 2; /*Select LCD module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ + uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ + }; + uint32_t val; + } lcd_clock; + union { + struct { + uint32_t cam_stop_en: 1; /*Camera stop enable signal 1: camera stops when DMA Rx FIFO is full. 0: Not stop.*/ + uint32_t cam_vsync_filter_thres: 3; /*Filter threshold value for CAM_VSYNC signal.*/ + uint32_t cam_update: 1; /*1: Update Camera registers will be cleared by hardware. 0 : Not care.*/ + uint32_t cam_byte_order: 1; /*1: Change data bit order change CAM_DATA_in[7:0] to CAM_DATA_in[0:7] in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ + uint32_t cam_bit_order: 1; /*1: invert data byte order only valid in 2 byte mode. 0: Not change.*/ + uint32_t cam_line_int_en: 1; /*1: Enable to generate CAM_HS_INT. 0: Disable.*/ + uint32_t cam_vs_eof_en: 1; /*1: CAM_VSYNC to generate in_suc_eof. 0: in_suc_eof is controlled by reg_cam_rec_data_cyclelen.*/ + uint32_t cam_clkm_div_num: 8; /*Integral Camera clock divider value*/ + uint32_t cam_clkm_div_b: 6; /*Fractional clock divider numerator value*/ + uint32_t cam_clkm_div_a: 6; /*Fractional clock divider denominator value*/ + uint32_t cam_clk_sel: 2; /*Select Camera module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: no clock.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } cam_ctrl; + union { + struct { + uint32_t cam_rec_data_bytelen: 14; /*Camera receive data byte length minus 1 to set DMA in_suc_eof_int.*/ + uint32_t cam_line_int_num: 7; /*The line number minus 1 to generate cam_hs_int.*/ + uint32_t cam_clk_inv: 1; /*1: Invert the input signal CAM_PCLK. 0: Not invert.*/ + uint32_t reserved22: 1; + uint32_t cam_vsync_filter_en: 1; /*1: Enable CAM_VSYNC filter function. 0: bypass.*/ + uint32_t cam_2byte_en: 1; /*1: The bit number of input data is 9~16. 0: The bit number of input data is 0~8.*/ + uint32_t cam_de_inv: 1; /*CAM_DE invert enable signal valid in high level.*/ + uint32_t cam_hsync_inv: 1; /*CAM_HSYNC invert enable signal valid in high level.*/ + uint32_t cam_vsync_inv: 1; /*CAM_VSYNC invert enable signal valid in high level.*/ + uint32_t cam_vh_de_mode_en: 1; /*1: Input control signals are CAM_DE CAM_HSYNC and CAM_VSYNC is 1. 0: Input control signals are CAM_DE and CAM_VSYNC*/ + uint32_t cam_start: 1; /*Camera module start signal.*/ + uint32_t cam_reset: 1; /*Camera module reset signal.*/ + uint32_t cam_afifo_reset: 1; /*Camera AFIFO reset signal.*/ + }; + uint32_t val; + } cam_ctrl1; + union { + struct { + uint32_t reserved0: 21; /*reserved*/ + uint32_t cam_conv_8bits_data_inv: 1; /*1:invert every two 8bits input data. 2. disabled.*/ + uint32_t cam_conv_yuv2yuv_mode: 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode trans_mode must be set to 1.*/ + uint32_t cam_conv_yuv_mode: 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode decides the yuv mode of Data_in*/ + uint32_t cam_conv_protocol_mode: 1; /*0:BT601. 1:BT709.*/ + uint32_t cam_conv_data_out_mode: 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/ + uint32_t cam_conv_data_in_mode: 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/ + uint32_t cam_conv_mode_8bits_on: 1; /*0: 16bits mode. 1: 8bits mode.*/ + uint32_t cam_conv_trans_mode: 1; /*0: YUV to RGB. 1: RGB to YUV.*/ + uint32_t cam_conv_bypass: 1; /*0: Bypass converter. 1: Enable converter.*/ + }; + uint32_t val; + } cam_rgb_yuv; + union { + struct { + uint32_t reserved0: 20; /*reserved*/ + uint32_t lcd_conv_8bits_data_inv: 1; /*1:invert every two 8bits input data. 2. disabled.*/ + uint32_t lcd_conv_txtorx: 1; /*0: txtorx mode off. 1: txtorx mode on.*/ + uint32_t lcd_conv_yuv2yuv_mode: 2; /*0: to yuv422. 1: to yuv420. 2: to yuv411. 3: disabled. To enable yuv2yuv mode trans_mode must be set to 1.*/ + uint32_t lcd_conv_yuv_mode: 2; /*0: yuv422. 1: yuv420. 2: yuv411. When in yuv2yuv mode yuv_mode decides the yuv mode of Data_in*/ + uint32_t lcd_conv_protocol_mode: 1; /*0:BT601. 1:BT709.*/ + uint32_t lcd_conv_data_out_mode: 1; /*LIMIT or FULL mode of Data out. 0: limit. 1: full*/ + uint32_t lcd_conv_data_in_mode: 1; /*LIMIT or FULL mode of Data in. 0: limit. 1: full*/ + uint32_t lcd_conv_mode_8bits_on: 1; /*0: 16bits mode. 1: 8bits mode.*/ + uint32_t lcd_conv_trans_mode: 1; /*0: YUV to RGB. 1: RGB to YUV.*/ + uint32_t lcd_conv_bypass: 1; /*0: Bypass converter. 1: Enable converter.*/ + }; + uint32_t val; + } lcd_rgb_yuv; + union { + struct { + uint32_t lcd_dout_cyclelen: 13; /*The output data cycles minus 1 of LCD module.*/ + uint32_t lcd_always_out_en: 1; /*LCD always output when LCD is in LCD_DOUT state unless reg_lcd_start is cleared or reg_lcd_reset is set.*/ + uint32_t reserved14: 5; /*reserved*/ + uint32_t lcd_8bits_order: 1; /*1: invert every two data byte valid in 1 byte mode. 0: Not change.*/ + uint32_t lcd_update: 1; /*1: Update LCD registers will be cleared by hardware. 0 : Not care.*/ + uint32_t lcd_bit_order: 1; /*1: Change data bit order change LCD_DATA_out[7:0] to LCD_DATA_out[0:7] in one byte mode and bits[15:0] to bits[0:15] in two byte mode. 0: Not change.*/ + uint32_t lcd_byte_order: 1; /*1: invert data byte order only valid in 2 byte mode. 0: Not change.*/ + uint32_t lcd_2byte_en: 1; /*1: The bit number of output LCD data is 9~16. 0: The bit number of output LCD data is 0~8.*/ + uint32_t lcd_dout: 1; /*1: Be able to send data out in LCD sequence when LCD starts. 0: Disable.*/ + uint32_t lcd_dummy: 1; /*1: Enable DUMMY phase in LCD sequence when LCD starts. 0: Disable.*/ + uint32_t lcd_cmd: 1; /*1: Be able to send command in LCD sequence when LCD starts. 0: Disable.*/ + uint32_t lcd_start: 1; /*LCD start sending data enable signal valid in high level.*/ + uint32_t lcd_reset: 1; /*The value of command.*/ + uint32_t lcd_dummy_cyclelen: 2; /*The dummy cycle length minus 1.*/ + uint32_t lcd_cmd_2_cycle_en: 1; /*The cycle length of command phase*/ + }; + uint32_t val; + } lcd_user; + union { + struct { + uint32_t reserved0: 1; /*reserved*/ + uint32_t lcd_afifo_threshold_num: 5; /*The awfull threshold number of lcd_afifo.*/ + uint32_t lcd_vfk_cyclelen: 6; /*The setup cycle length minus 1 in LCD non-RGB mode.*/ + uint32_t lcd_vbk_cyclelen: 13; /*The vertical back blank region cycle length minus 1 in LCD RGB mode or the hold time cycle length in LCD non-RGB mode.*/ + uint32_t lcd_next_frame_en: 1; /*1: Send the next frame data when the current frame is sent out. 0: LCD stops when the current frame is sent out.*/ + uint32_t lcd_bk_en: 1; /*1: Enable blank region when LCD sends data out. 0: No blank region.*/ + uint32_t lcd_afifo_reset: 1; /*LCD AFIFO reset signal.*/ + uint32_t lcd_cd_data_set: 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DOUT state. 0: LCD_CD = reg_cd_idle_edge.*/ + uint32_t lcd_cd_dummy_set: 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_DUMMY state. 0: LCD_CD = reg_cd_idle_edge.*/ + uint32_t lcd_cd_cmd_set: 1; /*1: LCD_CD = !reg_cd_idle_edge when lcd_st[2:0] is in LCD_CMD state. 0: LCD_CD = reg_cd_idle_edge.*/ + uint32_t lcd_cd_idle_edge: 1; /*The default value of LCD_CD.*/ + }; + uint32_t val; + } lcd_misc; + union { + struct { + uint32_t lcd_hb_front: 11; /*It is the horizontal blank front porch of a frame.*/ + uint32_t lcd_va_height: 10; /*It is the vertical active height of a frame.*/ + uint32_t lcd_vt_height: 10; /*It is the vertical total height of a frame.*/ + uint32_t lcd_rgb_mode_en: 1; /*1: Enable reg mode input vsync*/ + }; + uint32_t val; + } lcd_ctrl; + union { + struct { + uint32_t lcd_vb_front: 8; /*It is the vertical blank front porch of a frame.*/ + uint32_t lcd_ha_width: 12; /*It is the horizontal active width of a frame.*/ + uint32_t lcd_ht_width: 12; /*It is the horizontal total width of a frame.*/ + }; + uint32_t val; + } lcd_ctrl1; + union { + struct { + uint32_t lcd_vsync_width: 7; /*It is the position of LCD_VSYNC active pulse in a line.*/ + uint32_t lcd_vsync_idle_pol: 1; /*It is the idle value of LCD_VSYNC.*/ + uint32_t lcd_de_idle_pol: 1; /*It is the idle value of LCD_DE.*/ + uint32_t lcd_hs_blank_en: 1; /*1: The pulse of LCD_HSYNC is out in vertical blanking lines RGB mode. 0: LCD_HSYNC pulse is valid only in active region lines in RGB mode.*/ + uint32_t reserved10: 6; /*reserved*/ + uint32_t lcd_hsync_width: 7; /*It is the position of LCD_HSYNC active pulse in a line.*/ + uint32_t lcd_hsync_idle_pol: 1; /*It is the idle value of LCD_HSYNC.*/ + uint32_t lcd_hsync_position: 8; /*It is the position of LCD_HSYNC active pulse in a line.*/ + }; + uint32_t val; + } lcd_ctrl2; + uint32_t lcd_cmd_val; /*The LCD write command value.*/ + uint32_t reserved_2c; + union { + struct { + uint32_t lcd_cd_mode: 2; /*The output LCD_CD is delayed by module clock LCD_CLK*/ + uint32_t lcd_de_mode: 2; /*The output LCD_DE is delayed by module clock LCD_CLK*/ + uint32_t lcd_hsync_mode: 2; /*The output LCD_HSYNC is delayed by module clock LCD_CLK*/ + uint32_t lcd_vsync_mode: 2; /*The output LCD_VSYNC is delayed by module clock LCD_CLK*/ + uint32_t reserved8: 24; /*reserved*/ + }; + uint32_t val; + } lcd_dly_mode; + uint32_t reserved_34; + union { + struct { + uint32_t dout0_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout1_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout2_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout3_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout4_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout5_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout6_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout7_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout8_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout9_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout10_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout11_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout12_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout13_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout14_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + uint32_t dout15_mode: 2; /*The output data bit $n is delayed by module clock LCD_CLK*/ + }; + uint32_t val; + } lcd_data_dout_mode; + uint32_t reserved_3c; + uint32_t reserved_40; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + union { + struct { + uint32_t lcd_vsync: 1; /*The enable bit for LCD frame end interrupt.*/ + uint32_t lcd_trans_done: 1; /*The enable bit for lcd transfer end interrupt.*/ + uint32_t cam_vsync: 1; /*The enable bit for Camera frame end interrupt.*/ + uint32_t cam_hs: 1; /*The enable bit for Camera line interrupt.*/ + uint32_t reserved4: 28; /*reserved*/ + }; + uint32_t val; + } lc_dma_int_ena; + union { + struct { + uint32_t lcd_vsync: 1; /*The raw bit for LCD frame end interrupt.*/ + uint32_t lcd_trans_done: 1; /*The raw bit for lcd transfer end interrupt.*/ + uint32_t cam_vsync: 1; /*The raw bit for Camera frame end interrupt.*/ + uint32_t cam_hs: 1; /*The raw bit for Camera line interrupt.*/ + uint32_t reserved4: 28; /*reserved*/ + }; + uint32_t val; + } lc_dma_int_raw; + union { + struct { + uint32_t lcd_vsync: 1; /*The status bit for LCD frame end interrupt.*/ + uint32_t lcd_trans_done: 1; /*The status bit for lcd transfer end interrupt.*/ + uint32_t cam_vsync: 1; /*The status bit for Camera frame end interrupt.*/ + uint32_t cam_hs: 1; /*The status bit for Camera transfer end interrupt.*/ + uint32_t reserved4: 28; /*reserved*/ + }; + uint32_t val; + } lc_dma_int_st; + union { + struct { + uint32_t lcd_vsync: 1; /*The clear bit for LCD frame end interrupt.*/ + uint32_t lcd_trans_done: 1; /*The clear bit for lcd transfer end interrupt.*/ + uint32_t cam_vsync: 1; /*The clear bit for Camera frame end interrupt.*/ + uint32_t cam_hs: 1; /*The clear bit for Camera line interrupt.*/ + uint32_t reserved4: 28; /*reserved*/ + }; + uint32_t val; + } lc_dma_int_clr; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + union { + struct { + uint32_t lc_date: 28; /*LCD_CAM version control register*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } lc_date; +} lcd_cam_dev_t; + +extern lcd_cam_dev_t LCD_CAM; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/ledc_caps.h b/components/soc/soc/esp32s3/include/soc/ledc_caps.h new file mode 100644 index 000000000..7feddd2c0 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/ledc_caps.h @@ -0,0 +1,24 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/ledc_reg.h b/components/soc/soc/esp32s3/include/soc/ledc_reg.h new file mode 100644 index 000000000..092735ecc --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/ledc_reg.h @@ -0,0 +1,1566 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define LEDC_LSCH0_CONF0_REG (DR_REG_LEDC_BASE + 0x0000) +/* LEDC_OVF_CNT_RESET_ST_LSCH0 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH0 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH0_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH0_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH0_S 17 +/* LEDC_OVF_CNT_RESET_LSCH0 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH0 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH0_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH0_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH0_S 16 +/* LEDC_OVF_CNT_EN_LSCH0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH0 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH0_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH0_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH0_S 15 +/* LEDC_OVF_NUM_LSCH0 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH0 0x000003FF +#define LEDC_OVF_NUM_LSCH0_M ((LEDC_OVF_NUM_LSCH0_V) << (LEDC_OVF_NUM_LSCH0_S)) +#define LEDC_OVF_NUM_LSCH0_V 0x3FF +#define LEDC_OVF_NUM_LSCH0_S 5 +/* LEDC_PARA_UP_LSCH0 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH0 (BIT(4)) +#define LEDC_PARA_UP_LSCH0_M (BIT(4)) +#define LEDC_PARA_UP_LSCH0_V 0x1 +#define LEDC_PARA_UP_LSCH0_S 4 +/* LEDC_IDLE_LV_LSCH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH0 (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH0_V 0x1 +#define LEDC_IDLE_LV_LSCH0_S 3 +/* LEDC_SIG_OUT_EN_LSCH0 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH0 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH0_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH0_S 2 +/* LEDC_TIMER_SEL_LSCH0 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH0 0x00000003 +#define LEDC_TIMER_SEL_LSCH0_M ((LEDC_TIMER_SEL_LSCH0_V) << (LEDC_TIMER_SEL_LSCH0_S)) +#define LEDC_TIMER_SEL_LSCH0_V 0x3 +#define LEDC_TIMER_SEL_LSCH0_S 0 + +#define LEDC_LSCH0_HPOINT_REG (DR_REG_LEDC_BASE + 0x0004) +/* LEDC_HPOINT_LSCH0 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH0 0x00003FFF +#define LEDC_HPOINT_LSCH0_M ((LEDC_HPOINT_LSCH0_V) << (LEDC_HPOINT_LSCH0_S)) +#define LEDC_HPOINT_LSCH0_V 0x3FFF +#define LEDC_HPOINT_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_REG (DR_REG_LEDC_BASE + 0x0008) +/* LEDC_DUTY_LSCH0 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH0 0x0007FFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V) << (LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x7FFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH0_CONF1_REG (DR_REG_LEDC_BASE + 0x000C) +/* LEDC_DUTY_START_LSCH0 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH0 (BIT(31)) +#define LEDC_DUTY_START_LSCH0_M (BIT(31)) +#define LEDC_DUTY_START_LSCH0_V 0x1 +#define LEDC_DUTY_START_LSCH0_S 31 +/* LEDC_DUTY_INC_LSCH0 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH0 (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH0_V 0x1 +#define LEDC_DUTY_INC_LSCH0_S 30 +/* LEDC_DUTY_NUM_LSCH0 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH0 0x000003FF +#define LEDC_DUTY_NUM_LSCH0_M ((LEDC_DUTY_NUM_LSCH0_V) << (LEDC_DUTY_NUM_LSCH0_S)) +#define LEDC_DUTY_NUM_LSCH0_V 0x3FF +#define LEDC_DUTY_NUM_LSCH0_S 20 +/* LEDC_DUTY_CYCLE_LSCH0 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH0 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH0_M ((LEDC_DUTY_CYCLE_LSCH0_V) << (LEDC_DUTY_CYCLE_LSCH0_S)) +#define LEDC_DUTY_CYCLE_LSCH0_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH0_S 10 +/* LEDC_DUTY_SCALE_LSCH0 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH0 0x000003FF +#define LEDC_DUTY_SCALE_LSCH0_M ((LEDC_DUTY_SCALE_LSCH0_V) << (LEDC_DUTY_SCALE_LSCH0_S)) +#define LEDC_DUTY_SCALE_LSCH0_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH0_S 0 + +#define LEDC_LSCH0_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0010) +/* LEDC_DUTY_LSCH0 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH0 0x0007FFFF +#define LEDC_DUTY_LSCH0_M ((LEDC_DUTY_LSCH0_V) << (LEDC_DUTY_LSCH0_S)) +#define LEDC_DUTY_LSCH0_V 0x7FFFF +#define LEDC_DUTY_LSCH0_S 0 + +#define LEDC_LSCH1_CONF0_REG (DR_REG_LEDC_BASE + 0x0014) +/* LEDC_OVF_CNT_RESET_ST_LSCH1 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH1 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH1_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH1_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH1_S 17 +/* LEDC_OVF_CNT_RESET_LSCH1 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH1 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH1_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH1_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH1_S 16 +/* LEDC_OVF_CNT_EN_LSCH1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH1 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH1_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH1_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH1_S 15 +/* LEDC_OVF_NUM_LSCH1 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH1 0x000003FF +#define LEDC_OVF_NUM_LSCH1_M ((LEDC_OVF_NUM_LSCH1_V) << (LEDC_OVF_NUM_LSCH1_S)) +#define LEDC_OVF_NUM_LSCH1_V 0x3FF +#define LEDC_OVF_NUM_LSCH1_S 5 +/* LEDC_PARA_UP_LSCH1 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH1 (BIT(4)) +#define LEDC_PARA_UP_LSCH1_M (BIT(4)) +#define LEDC_PARA_UP_LSCH1_V 0x1 +#define LEDC_PARA_UP_LSCH1_S 4 +/* LEDC_IDLE_LV_LSCH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH1 (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH1_V 0x1 +#define LEDC_IDLE_LV_LSCH1_S 3 +/* LEDC_SIG_OUT_EN_LSCH1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH1 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH1_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH1_S 2 +/* LEDC_TIMER_SEL_LSCH1 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH1 0x00000003 +#define LEDC_TIMER_SEL_LSCH1_M ((LEDC_TIMER_SEL_LSCH1_V) << (LEDC_TIMER_SEL_LSCH1_S)) +#define LEDC_TIMER_SEL_LSCH1_V 0x3 +#define LEDC_TIMER_SEL_LSCH1_S 0 + +#define LEDC_LSCH1_HPOINT_REG (DR_REG_LEDC_BASE + 0x0018) +/* LEDC_HPOINT_LSCH1 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH1 0x00003FFF +#define LEDC_HPOINT_LSCH1_M ((LEDC_HPOINT_LSCH1_V) << (LEDC_HPOINT_LSCH1_S)) +#define LEDC_HPOINT_LSCH1_V 0x3FFF +#define LEDC_HPOINT_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_REG (DR_REG_LEDC_BASE + 0x001C) +/* LEDC_DUTY_LSCH1 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH1 0x0007FFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V) << (LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x7FFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH1_CONF1_REG (DR_REG_LEDC_BASE + 0x0020) +/* LEDC_DUTY_START_LSCH1 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH1 (BIT(31)) +#define LEDC_DUTY_START_LSCH1_M (BIT(31)) +#define LEDC_DUTY_START_LSCH1_V 0x1 +#define LEDC_DUTY_START_LSCH1_S 31 +/* LEDC_DUTY_INC_LSCH1 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH1 (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH1_V 0x1 +#define LEDC_DUTY_INC_LSCH1_S 30 +/* LEDC_DUTY_NUM_LSCH1 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH1 0x000003FF +#define LEDC_DUTY_NUM_LSCH1_M ((LEDC_DUTY_NUM_LSCH1_V) << (LEDC_DUTY_NUM_LSCH1_S)) +#define LEDC_DUTY_NUM_LSCH1_V 0x3FF +#define LEDC_DUTY_NUM_LSCH1_S 20 +/* LEDC_DUTY_CYCLE_LSCH1 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH1 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH1_M ((LEDC_DUTY_CYCLE_LSCH1_V) << (LEDC_DUTY_CYCLE_LSCH1_S)) +#define LEDC_DUTY_CYCLE_LSCH1_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH1_S 10 +/* LEDC_DUTY_SCALE_LSCH1 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH1 0x000003FF +#define LEDC_DUTY_SCALE_LSCH1_M ((LEDC_DUTY_SCALE_LSCH1_V) << (LEDC_DUTY_SCALE_LSCH1_S)) +#define LEDC_DUTY_SCALE_LSCH1_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH1_S 0 + +#define LEDC_LSCH1_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0024) +/* LEDC_DUTY_LSCH1 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH1 0x0007FFFF +#define LEDC_DUTY_LSCH1_M ((LEDC_DUTY_LSCH1_V) << (LEDC_DUTY_LSCH1_S)) +#define LEDC_DUTY_LSCH1_V 0x7FFFF +#define LEDC_DUTY_LSCH1_S 0 + +#define LEDC_LSCH2_CONF0_REG (DR_REG_LEDC_BASE + 0x0028) +/* LEDC_OVF_CNT_RESET_ST_LSCH2 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH2 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH2_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH2_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH2_S 17 +/* LEDC_OVF_CNT_RESET_LSCH2 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH2 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH2_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH2_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH2_S 16 +/* LEDC_OVF_CNT_EN_LSCH2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH2 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH2_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH2_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH2_S 15 +/* LEDC_OVF_NUM_LSCH2 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH2 0x000003FF +#define LEDC_OVF_NUM_LSCH2_M ((LEDC_OVF_NUM_LSCH2_V) << (LEDC_OVF_NUM_LSCH2_S)) +#define LEDC_OVF_NUM_LSCH2_V 0x3FF +#define LEDC_OVF_NUM_LSCH2_S 5 +/* LEDC_PARA_UP_LSCH2 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH2 (BIT(4)) +#define LEDC_PARA_UP_LSCH2_M (BIT(4)) +#define LEDC_PARA_UP_LSCH2_V 0x1 +#define LEDC_PARA_UP_LSCH2_S 4 +/* LEDC_IDLE_LV_LSCH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH2 (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH2_V 0x1 +#define LEDC_IDLE_LV_LSCH2_S 3 +/* LEDC_SIG_OUT_EN_LSCH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH2 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH2_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH2_S 2 +/* LEDC_TIMER_SEL_LSCH2 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH2 0x00000003 +#define LEDC_TIMER_SEL_LSCH2_M ((LEDC_TIMER_SEL_LSCH2_V) << (LEDC_TIMER_SEL_LSCH2_S)) +#define LEDC_TIMER_SEL_LSCH2_V 0x3 +#define LEDC_TIMER_SEL_LSCH2_S 0 + +#define LEDC_LSCH2_HPOINT_REG (DR_REG_LEDC_BASE + 0x002C) +/* LEDC_HPOINT_LSCH2 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH2 0x00003FFF +#define LEDC_HPOINT_LSCH2_M ((LEDC_HPOINT_LSCH2_V) << (LEDC_HPOINT_LSCH2_S)) +#define LEDC_HPOINT_LSCH2_V 0x3FFF +#define LEDC_HPOINT_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_REG (DR_REG_LEDC_BASE + 0x0030) +/* LEDC_DUTY_LSCH2 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH2 0x0007FFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V) << (LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x7FFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH2_CONF1_REG (DR_REG_LEDC_BASE + 0x0034) +/* LEDC_DUTY_START_LSCH2 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH2 (BIT(31)) +#define LEDC_DUTY_START_LSCH2_M (BIT(31)) +#define LEDC_DUTY_START_LSCH2_V 0x1 +#define LEDC_DUTY_START_LSCH2_S 31 +/* LEDC_DUTY_INC_LSCH2 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH2 (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH2_V 0x1 +#define LEDC_DUTY_INC_LSCH2_S 30 +/* LEDC_DUTY_NUM_LSCH2 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH2 0x000003FF +#define LEDC_DUTY_NUM_LSCH2_M ((LEDC_DUTY_NUM_LSCH2_V) << (LEDC_DUTY_NUM_LSCH2_S)) +#define LEDC_DUTY_NUM_LSCH2_V 0x3FF +#define LEDC_DUTY_NUM_LSCH2_S 20 +/* LEDC_DUTY_CYCLE_LSCH2 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH2 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH2_M ((LEDC_DUTY_CYCLE_LSCH2_V) << (LEDC_DUTY_CYCLE_LSCH2_S)) +#define LEDC_DUTY_CYCLE_LSCH2_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH2_S 10 +/* LEDC_DUTY_SCALE_LSCH2 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH2 0x000003FF +#define LEDC_DUTY_SCALE_LSCH2_M ((LEDC_DUTY_SCALE_LSCH2_V) << (LEDC_DUTY_SCALE_LSCH2_S)) +#define LEDC_DUTY_SCALE_LSCH2_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH2_S 0 + +#define LEDC_LSCH2_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0038) +/* LEDC_DUTY_LSCH2 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH2 0x0007FFFF +#define LEDC_DUTY_LSCH2_M ((LEDC_DUTY_LSCH2_V) << (LEDC_DUTY_LSCH2_S)) +#define LEDC_DUTY_LSCH2_V 0x7FFFF +#define LEDC_DUTY_LSCH2_S 0 + +#define LEDC_LSCH3_CONF0_REG (DR_REG_LEDC_BASE + 0x003C) +/* LEDC_OVF_CNT_RESET_ST_LSCH3 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH3 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH3_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH3_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH3_S 17 +/* LEDC_OVF_CNT_RESET_LSCH3 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH3 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH3_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH3_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH3_S 16 +/* LEDC_OVF_CNT_EN_LSCH3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH3 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH3_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH3_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH3_S 15 +/* LEDC_OVF_NUM_LSCH3 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH3 0x000003FF +#define LEDC_OVF_NUM_LSCH3_M ((LEDC_OVF_NUM_LSCH3_V) << (LEDC_OVF_NUM_LSCH3_S)) +#define LEDC_OVF_NUM_LSCH3_V 0x3FF +#define LEDC_OVF_NUM_LSCH3_S 5 +/* LEDC_PARA_UP_LSCH3 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH3 (BIT(4)) +#define LEDC_PARA_UP_LSCH3_M (BIT(4)) +#define LEDC_PARA_UP_LSCH3_V 0x1 +#define LEDC_PARA_UP_LSCH3_S 4 +/* LEDC_IDLE_LV_LSCH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH3 (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH3_V 0x1 +#define LEDC_IDLE_LV_LSCH3_S 3 +/* LEDC_SIG_OUT_EN_LSCH3 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH3 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH3_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH3_S 2 +/* LEDC_TIMER_SEL_LSCH3 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH3 0x00000003 +#define LEDC_TIMER_SEL_LSCH3_M ((LEDC_TIMER_SEL_LSCH3_V) << (LEDC_TIMER_SEL_LSCH3_S)) +#define LEDC_TIMER_SEL_LSCH3_V 0x3 +#define LEDC_TIMER_SEL_LSCH3_S 0 + +#define LEDC_LSCH3_HPOINT_REG (DR_REG_LEDC_BASE + 0x0040) +/* LEDC_HPOINT_LSCH3 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH3 0x00003FFF +#define LEDC_HPOINT_LSCH3_M ((LEDC_HPOINT_LSCH3_V) << (LEDC_HPOINT_LSCH3_S)) +#define LEDC_HPOINT_LSCH3_V 0x3FFF +#define LEDC_HPOINT_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_REG (DR_REG_LEDC_BASE + 0x0044) +/* LEDC_DUTY_LSCH3 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH3 0x0007FFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V) << (LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x7FFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH3_CONF1_REG (DR_REG_LEDC_BASE + 0x0048) +/* LEDC_DUTY_START_LSCH3 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH3 (BIT(31)) +#define LEDC_DUTY_START_LSCH3_M (BIT(31)) +#define LEDC_DUTY_START_LSCH3_V 0x1 +#define LEDC_DUTY_START_LSCH3_S 31 +/* LEDC_DUTY_INC_LSCH3 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH3 (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH3_V 0x1 +#define LEDC_DUTY_INC_LSCH3_S 30 +/* LEDC_DUTY_NUM_LSCH3 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH3 0x000003FF +#define LEDC_DUTY_NUM_LSCH3_M ((LEDC_DUTY_NUM_LSCH3_V) << (LEDC_DUTY_NUM_LSCH3_S)) +#define LEDC_DUTY_NUM_LSCH3_V 0x3FF +#define LEDC_DUTY_NUM_LSCH3_S 20 +/* LEDC_DUTY_CYCLE_LSCH3 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH3 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH3_M ((LEDC_DUTY_CYCLE_LSCH3_V) << (LEDC_DUTY_CYCLE_LSCH3_S)) +#define LEDC_DUTY_CYCLE_LSCH3_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH3_S 10 +/* LEDC_DUTY_SCALE_LSCH3 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH3 0x000003FF +#define LEDC_DUTY_SCALE_LSCH3_M ((LEDC_DUTY_SCALE_LSCH3_V) << (LEDC_DUTY_SCALE_LSCH3_S)) +#define LEDC_DUTY_SCALE_LSCH3_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH3_S 0 + +#define LEDC_LSCH3_DUTY_R_REG (DR_REG_LEDC_BASE + 0x004C) +/* LEDC_DUTY_LSCH3 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH3 0x0007FFFF +#define LEDC_DUTY_LSCH3_M ((LEDC_DUTY_LSCH3_V) << (LEDC_DUTY_LSCH3_S)) +#define LEDC_DUTY_LSCH3_V 0x7FFFF +#define LEDC_DUTY_LSCH3_S 0 + +#define LEDC_LSCH4_CONF0_REG (DR_REG_LEDC_BASE + 0x0050) +/* LEDC_OVF_CNT_RESET_ST_LSCH4 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH4 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH4_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH4_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH4_S 17 +/* LEDC_OVF_CNT_RESET_LSCH4 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH4 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH4_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH4_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH4_S 16 +/* LEDC_OVF_CNT_EN_LSCH4 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH4 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH4_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH4_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH4_S 15 +/* LEDC_OVF_NUM_LSCH4 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH4 0x000003FF +#define LEDC_OVF_NUM_LSCH4_M ((LEDC_OVF_NUM_LSCH4_V) << (LEDC_OVF_NUM_LSCH4_S)) +#define LEDC_OVF_NUM_LSCH4_V 0x3FF +#define LEDC_OVF_NUM_LSCH4_S 5 +/* LEDC_PARA_UP_LSCH4 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH4 (BIT(4)) +#define LEDC_PARA_UP_LSCH4_M (BIT(4)) +#define LEDC_PARA_UP_LSCH4_V 0x1 +#define LEDC_PARA_UP_LSCH4_S 4 +/* LEDC_IDLE_LV_LSCH4 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH4 (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH4_V 0x1 +#define LEDC_IDLE_LV_LSCH4_S 3 +/* LEDC_SIG_OUT_EN_LSCH4 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH4 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH4_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH4_S 2 +/* LEDC_TIMER_SEL_LSCH4 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH4 0x00000003 +#define LEDC_TIMER_SEL_LSCH4_M ((LEDC_TIMER_SEL_LSCH4_V) << (LEDC_TIMER_SEL_LSCH4_S)) +#define LEDC_TIMER_SEL_LSCH4_V 0x3 +#define LEDC_TIMER_SEL_LSCH4_S 0 + +#define LEDC_LSCH4_HPOINT_REG (DR_REG_LEDC_BASE + 0x0054) +/* LEDC_HPOINT_LSCH4 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH4 0x00003FFF +#define LEDC_HPOINT_LSCH4_M ((LEDC_HPOINT_LSCH4_V) << (LEDC_HPOINT_LSCH4_S)) +#define LEDC_HPOINT_LSCH4_V 0x3FFF +#define LEDC_HPOINT_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_REG (DR_REG_LEDC_BASE + 0x0058) +/* LEDC_DUTY_LSCH4 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH4 0x0007FFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V) << (LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x7FFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH4_CONF1_REG (DR_REG_LEDC_BASE + 0x005C) +/* LEDC_DUTY_START_LSCH4 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH4 (BIT(31)) +#define LEDC_DUTY_START_LSCH4_M (BIT(31)) +#define LEDC_DUTY_START_LSCH4_V 0x1 +#define LEDC_DUTY_START_LSCH4_S 31 +/* LEDC_DUTY_INC_LSCH4 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH4 (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH4_V 0x1 +#define LEDC_DUTY_INC_LSCH4_S 30 +/* LEDC_DUTY_NUM_LSCH4 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH4 0x000003FF +#define LEDC_DUTY_NUM_LSCH4_M ((LEDC_DUTY_NUM_LSCH4_V) << (LEDC_DUTY_NUM_LSCH4_S)) +#define LEDC_DUTY_NUM_LSCH4_V 0x3FF +#define LEDC_DUTY_NUM_LSCH4_S 20 +/* LEDC_DUTY_CYCLE_LSCH4 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH4 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH4_M ((LEDC_DUTY_CYCLE_LSCH4_V) << (LEDC_DUTY_CYCLE_LSCH4_S)) +#define LEDC_DUTY_CYCLE_LSCH4_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH4_S 10 +/* LEDC_DUTY_SCALE_LSCH4 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH4 0x000003FF +#define LEDC_DUTY_SCALE_LSCH4_M ((LEDC_DUTY_SCALE_LSCH4_V) << (LEDC_DUTY_SCALE_LSCH4_S)) +#define LEDC_DUTY_SCALE_LSCH4_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH4_S 0 + +#define LEDC_LSCH4_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0060) +/* LEDC_DUTY_LSCH4 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH4 0x0007FFFF +#define LEDC_DUTY_LSCH4_M ((LEDC_DUTY_LSCH4_V) << (LEDC_DUTY_LSCH4_S)) +#define LEDC_DUTY_LSCH4_V 0x7FFFF +#define LEDC_DUTY_LSCH4_S 0 + +#define LEDC_LSCH5_CONF0_REG (DR_REG_LEDC_BASE + 0x0064) +/* LEDC_OVF_CNT_RESET_ST_LSCH5 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH5 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH5_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH5_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH5_S 17 +/* LEDC_OVF_CNT_RESET_LSCH5 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH5 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH5_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH5_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH5_S 16 +/* LEDC_OVF_CNT_EN_LSCH5 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH5 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH5_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH5_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH5_S 15 +/* LEDC_OVF_NUM_LSCH5 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH5 0x000003FF +#define LEDC_OVF_NUM_LSCH5_M ((LEDC_OVF_NUM_LSCH5_V) << (LEDC_OVF_NUM_LSCH5_S)) +#define LEDC_OVF_NUM_LSCH5_V 0x3FF +#define LEDC_OVF_NUM_LSCH5_S 5 +/* LEDC_PARA_UP_LSCH5 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH5 (BIT(4)) +#define LEDC_PARA_UP_LSCH5_M (BIT(4)) +#define LEDC_PARA_UP_LSCH5_V 0x1 +#define LEDC_PARA_UP_LSCH5_S 4 +/* LEDC_IDLE_LV_LSCH5 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH5 (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH5_V 0x1 +#define LEDC_IDLE_LV_LSCH5_S 3 +/* LEDC_SIG_OUT_EN_LSCH5 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH5 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH5_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH5_S 2 +/* LEDC_TIMER_SEL_LSCH5 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH5 0x00000003 +#define LEDC_TIMER_SEL_LSCH5_M ((LEDC_TIMER_SEL_LSCH5_V) << (LEDC_TIMER_SEL_LSCH5_S)) +#define LEDC_TIMER_SEL_LSCH5_V 0x3 +#define LEDC_TIMER_SEL_LSCH5_S 0 + +#define LEDC_LSCH5_HPOINT_REG (DR_REG_LEDC_BASE + 0x0068) +/* LEDC_HPOINT_LSCH5 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH5 0x00003FFF +#define LEDC_HPOINT_LSCH5_M ((LEDC_HPOINT_LSCH5_V) << (LEDC_HPOINT_LSCH5_S)) +#define LEDC_HPOINT_LSCH5_V 0x3FFF +#define LEDC_HPOINT_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_REG (DR_REG_LEDC_BASE + 0x006C) +/* LEDC_DUTY_LSCH5 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH5 0x0007FFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V) << (LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x7FFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH5_CONF1_REG (DR_REG_LEDC_BASE + 0x0070) +/* LEDC_DUTY_START_LSCH5 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH5 (BIT(31)) +#define LEDC_DUTY_START_LSCH5_M (BIT(31)) +#define LEDC_DUTY_START_LSCH5_V 0x1 +#define LEDC_DUTY_START_LSCH5_S 31 +/* LEDC_DUTY_INC_LSCH5 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH5 (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH5_V 0x1 +#define LEDC_DUTY_INC_LSCH5_S 30 +/* LEDC_DUTY_NUM_LSCH5 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH5 0x000003FF +#define LEDC_DUTY_NUM_LSCH5_M ((LEDC_DUTY_NUM_LSCH5_V) << (LEDC_DUTY_NUM_LSCH5_S)) +#define LEDC_DUTY_NUM_LSCH5_V 0x3FF +#define LEDC_DUTY_NUM_LSCH5_S 20 +/* LEDC_DUTY_CYCLE_LSCH5 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH5 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH5_M ((LEDC_DUTY_CYCLE_LSCH5_V) << (LEDC_DUTY_CYCLE_LSCH5_S)) +#define LEDC_DUTY_CYCLE_LSCH5_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH5_S 10 +/* LEDC_DUTY_SCALE_LSCH5 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH5 0x000003FF +#define LEDC_DUTY_SCALE_LSCH5_M ((LEDC_DUTY_SCALE_LSCH5_V) << (LEDC_DUTY_SCALE_LSCH5_S)) +#define LEDC_DUTY_SCALE_LSCH5_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH5_S 0 + +#define LEDC_LSCH5_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0074) +/* LEDC_DUTY_LSCH5 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH5 0x0007FFFF +#define LEDC_DUTY_LSCH5_M ((LEDC_DUTY_LSCH5_V) << (LEDC_DUTY_LSCH5_S)) +#define LEDC_DUTY_LSCH5_V 0x7FFFF +#define LEDC_DUTY_LSCH5_S 0 + +#define LEDC_LSCH6_CONF0_REG (DR_REG_LEDC_BASE + 0x0078) +/* LEDC_OVF_CNT_RESET_ST_LSCH6 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH6 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH6_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH6_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH6_S 17 +/* LEDC_OVF_CNT_RESET_LSCH6 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH6 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH6_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH6_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH6_S 16 +/* LEDC_OVF_CNT_EN_LSCH6 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH6 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH6_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH6_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH6_S 15 +/* LEDC_OVF_NUM_LSCH6 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH6 0x000003FF +#define LEDC_OVF_NUM_LSCH6_M ((LEDC_OVF_NUM_LSCH6_V) << (LEDC_OVF_NUM_LSCH6_S)) +#define LEDC_OVF_NUM_LSCH6_V 0x3FF +#define LEDC_OVF_NUM_LSCH6_S 5 +/* LEDC_PARA_UP_LSCH6 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH6 (BIT(4)) +#define LEDC_PARA_UP_LSCH6_M (BIT(4)) +#define LEDC_PARA_UP_LSCH6_V 0x1 +#define LEDC_PARA_UP_LSCH6_S 4 +/* LEDC_IDLE_LV_LSCH6 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH6 (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH6_V 0x1 +#define LEDC_IDLE_LV_LSCH6_S 3 +/* LEDC_SIG_OUT_EN_LSCH6 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH6 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH6_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH6_S 2 +/* LEDC_TIMER_SEL_LSCH6 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH6 0x00000003 +#define LEDC_TIMER_SEL_LSCH6_M ((LEDC_TIMER_SEL_LSCH6_V) << (LEDC_TIMER_SEL_LSCH6_S)) +#define LEDC_TIMER_SEL_LSCH6_V 0x3 +#define LEDC_TIMER_SEL_LSCH6_S 0 + +#define LEDC_LSCH6_HPOINT_REG (DR_REG_LEDC_BASE + 0x007C) +/* LEDC_HPOINT_LSCH6 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH6 0x00003FFF +#define LEDC_HPOINT_LSCH6_M ((LEDC_HPOINT_LSCH6_V) << (LEDC_HPOINT_LSCH6_S)) +#define LEDC_HPOINT_LSCH6_V 0x3FFF +#define LEDC_HPOINT_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_REG (DR_REG_LEDC_BASE + 0x0080) +/* LEDC_DUTY_LSCH6 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH6 0x0007FFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V) << (LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x7FFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH6_CONF1_REG (DR_REG_LEDC_BASE + 0x0084) +/* LEDC_DUTY_START_LSCH6 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH6 (BIT(31)) +#define LEDC_DUTY_START_LSCH6_M (BIT(31)) +#define LEDC_DUTY_START_LSCH6_V 0x1 +#define LEDC_DUTY_START_LSCH6_S 31 +/* LEDC_DUTY_INC_LSCH6 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH6 (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH6_V 0x1 +#define LEDC_DUTY_INC_LSCH6_S 30 +/* LEDC_DUTY_NUM_LSCH6 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH6 0x000003FF +#define LEDC_DUTY_NUM_LSCH6_M ((LEDC_DUTY_NUM_LSCH6_V) << (LEDC_DUTY_NUM_LSCH6_S)) +#define LEDC_DUTY_NUM_LSCH6_V 0x3FF +#define LEDC_DUTY_NUM_LSCH6_S 20 +/* LEDC_DUTY_CYCLE_LSCH6 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH6 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH6_M ((LEDC_DUTY_CYCLE_LSCH6_V) << (LEDC_DUTY_CYCLE_LSCH6_S)) +#define LEDC_DUTY_CYCLE_LSCH6_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH6_S 10 +/* LEDC_DUTY_SCALE_LSCH6 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH6 0x000003FF +#define LEDC_DUTY_SCALE_LSCH6_M ((LEDC_DUTY_SCALE_LSCH6_V) << (LEDC_DUTY_SCALE_LSCH6_S)) +#define LEDC_DUTY_SCALE_LSCH6_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH6_S 0 + +#define LEDC_LSCH6_DUTY_R_REG (DR_REG_LEDC_BASE + 0x0088) +/* LEDC_DUTY_LSCH6 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH6 0x0007FFFF +#define LEDC_DUTY_LSCH6_M ((LEDC_DUTY_LSCH6_V) << (LEDC_DUTY_LSCH6_S)) +#define LEDC_DUTY_LSCH6_V 0x7FFFF +#define LEDC_DUTY_LSCH6_S 0 + +#define LEDC_LSCH7_CONF0_REG (DR_REG_LEDC_BASE + 0x008C) +/* LEDC_OVF_CNT_RESET_ST_LSCH7 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_ST_LSCH7 (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH7_M (BIT(17)) +#define LEDC_OVF_CNT_RESET_ST_LSCH7_V 0x1 +#define LEDC_OVF_CNT_RESET_ST_LSCH7_S 17 +/* LEDC_OVF_CNT_RESET_LSCH7 : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_RESET_LSCH7 (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH7_M (BIT(16)) +#define LEDC_OVF_CNT_RESET_LSCH7_V 0x1 +#define LEDC_OVF_CNT_RESET_LSCH7_S 16 +/* LEDC_OVF_CNT_EN_LSCH7 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_EN_LSCH7 (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH7_M (BIT(15)) +#define LEDC_OVF_CNT_EN_LSCH7_V 0x1 +#define LEDC_OVF_CNT_EN_LSCH7_S 15 +/* LEDC_OVF_NUM_LSCH7 : R/W ;bitpos:[14:5] ;default: 10'b0 ; */ +/*description: */ +#define LEDC_OVF_NUM_LSCH7 0x000003FF +#define LEDC_OVF_NUM_LSCH7_M ((LEDC_OVF_NUM_LSCH7_V) << (LEDC_OVF_NUM_LSCH7_S)) +#define LEDC_OVF_NUM_LSCH7_V 0x3FF +#define LEDC_OVF_NUM_LSCH7_S 5 +/* LEDC_PARA_UP_LSCH7 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_PARA_UP_LSCH7 (BIT(4)) +#define LEDC_PARA_UP_LSCH7_M (BIT(4)) +#define LEDC_PARA_UP_LSCH7_V 0x1 +#define LEDC_PARA_UP_LSCH7_S 4 +/* LEDC_IDLE_LV_LSCH7 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_IDLE_LV_LSCH7 (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_M (BIT(3)) +#define LEDC_IDLE_LV_LSCH7_V 0x1 +#define LEDC_IDLE_LV_LSCH7_S 3 +/* LEDC_SIG_OUT_EN_LSCH7 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_SIG_OUT_EN_LSCH7 (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_M (BIT(2)) +#define LEDC_SIG_OUT_EN_LSCH7_V 0x1 +#define LEDC_SIG_OUT_EN_LSCH7_S 2 +/* LEDC_TIMER_SEL_LSCH7 : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define LEDC_TIMER_SEL_LSCH7 0x00000003 +#define LEDC_TIMER_SEL_LSCH7_M ((LEDC_TIMER_SEL_LSCH7_V) << (LEDC_TIMER_SEL_LSCH7_S)) +#define LEDC_TIMER_SEL_LSCH7_V 0x3 +#define LEDC_TIMER_SEL_LSCH7_S 0 + +#define LEDC_LSCH7_HPOINT_REG (DR_REG_LEDC_BASE + 0x0090) +/* LEDC_HPOINT_LSCH7 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: */ +#define LEDC_HPOINT_LSCH7 0x00003FFF +#define LEDC_HPOINT_LSCH7_M ((LEDC_HPOINT_LSCH7_V) << (LEDC_HPOINT_LSCH7_S)) +#define LEDC_HPOINT_LSCH7_V 0x3FFF +#define LEDC_HPOINT_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_REG (DR_REG_LEDC_BASE + 0x0094) +/* LEDC_DUTY_LSCH7 : R/W ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH7 0x0007FFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V) << (LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x7FFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_LSCH7_CONF1_REG (DR_REG_LEDC_BASE + 0x0098) +/* LEDC_DUTY_START_LSCH7 : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_START_LSCH7 (BIT(31)) +#define LEDC_DUTY_START_LSCH7_M (BIT(31)) +#define LEDC_DUTY_START_LSCH7_V 0x1 +#define LEDC_DUTY_START_LSCH7_S 31 +/* LEDC_DUTY_INC_LSCH7 : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_DUTY_INC_LSCH7 (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_M (BIT(30)) +#define LEDC_DUTY_INC_LSCH7_V 0x1 +#define LEDC_DUTY_INC_LSCH7_S 30 +/* LEDC_DUTY_NUM_LSCH7 : R/W ;bitpos:[29:20] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_NUM_LSCH7 0x000003FF +#define LEDC_DUTY_NUM_LSCH7_M ((LEDC_DUTY_NUM_LSCH7_V) << (LEDC_DUTY_NUM_LSCH7_S)) +#define LEDC_DUTY_NUM_LSCH7_V 0x3FF +#define LEDC_DUTY_NUM_LSCH7_S 20 +/* LEDC_DUTY_CYCLE_LSCH7 : R/W ;bitpos:[19:10] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_CYCLE_LSCH7 0x000003FF +#define LEDC_DUTY_CYCLE_LSCH7_M ((LEDC_DUTY_CYCLE_LSCH7_V) << (LEDC_DUTY_CYCLE_LSCH7_S)) +#define LEDC_DUTY_CYCLE_LSCH7_V 0x3FF +#define LEDC_DUTY_CYCLE_LSCH7_S 10 +/* LEDC_DUTY_SCALE_LSCH7 : R/W ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define LEDC_DUTY_SCALE_LSCH7 0x000003FF +#define LEDC_DUTY_SCALE_LSCH7_M ((LEDC_DUTY_SCALE_LSCH7_V) << (LEDC_DUTY_SCALE_LSCH7_S)) +#define LEDC_DUTY_SCALE_LSCH7_V 0x3FF +#define LEDC_DUTY_SCALE_LSCH7_S 0 + +#define LEDC_LSCH7_DUTY_R_REG (DR_REG_LEDC_BASE + 0x009C) +/* LEDC_DUTY_LSCH7 : RO ;bitpos:[18:0] ;default: 19'h0 ; */ +/*description: */ +#define LEDC_DUTY_LSCH7 0x0007FFFF +#define LEDC_DUTY_LSCH7_M ((LEDC_DUTY_LSCH7_V) << (LEDC_DUTY_LSCH7_S)) +#define LEDC_DUTY_LSCH7_V 0x7FFFF +#define LEDC_DUTY_LSCH7_S 0 + +#define LEDC_LSTIMER0_CONF_REG (DR_REG_LEDC_BASE + 0x00a0) +/* LEDC_LSTIMER0_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER0_PARA_UP (BIT(25)) +#define LEDC_LSTIMER0_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER0_PARA_UP_V 0x1 +#define LEDC_LSTIMER0_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER0 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER0 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER0_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER0_V 0x1 +#define LEDC_TICK_SEL_LSTIMER0_S 24 +/* LEDC_LSTIMER0_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER0_RST (BIT(23)) +#define LEDC_LSTIMER0_RST_M (BIT(23)) +#define LEDC_LSTIMER0_RST_V 0x1 +#define LEDC_LSTIMER0_RST_S 23 +/* LEDC_LSTIMER0_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_PAUSE (BIT(22)) +#define LEDC_LSTIMER0_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER0_PAUSE_V 0x1 +#define LEDC_LSTIMER0_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER0 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER0 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER0_M ((LEDC_CLK_DIV_LSTIMER0_V) << (LEDC_CLK_DIV_LSTIMER0_S)) +#define LEDC_CLK_DIV_LSTIMER0_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER0_S 4 +/* LEDC_LSTIMER0_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER0_DUTY_RES 0x0000000F +#define LEDC_LSTIMER0_DUTY_RES_M ((LEDC_LSTIMER0_DUTY_RES_V) << (LEDC_LSTIMER0_DUTY_RES_S)) +#define LEDC_LSTIMER0_DUTY_RES_V 0xF +#define LEDC_LSTIMER0_DUTY_RES_S 0 + +#define LEDC_LSTIMER0_VALUE_REG (DR_REG_LEDC_BASE + 0x00a4) +/* LEDC_LSTIMER0_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_CNT 0x00003FFF +#define LEDC_LSTIMER0_CNT_M ((LEDC_LSTIMER0_CNT_V) << (LEDC_LSTIMER0_CNT_S)) +#define LEDC_LSTIMER0_CNT_V 0x3FFF +#define LEDC_LSTIMER0_CNT_S 0 + +#define LEDC_LSTIMER1_CONF_REG (DR_REG_LEDC_BASE + 0x00a8) +/* LEDC_LSTIMER1_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER1_PARA_UP (BIT(25)) +#define LEDC_LSTIMER1_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER1_PARA_UP_V 0x1 +#define LEDC_LSTIMER1_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER1 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER1_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER1_V 0x1 +#define LEDC_TICK_SEL_LSTIMER1_S 24 +/* LEDC_LSTIMER1_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER1_RST (BIT(23)) +#define LEDC_LSTIMER1_RST_M (BIT(23)) +#define LEDC_LSTIMER1_RST_V 0x1 +#define LEDC_LSTIMER1_RST_S 23 +/* LEDC_LSTIMER1_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_PAUSE (BIT(22)) +#define LEDC_LSTIMER1_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER1_PAUSE_V 0x1 +#define LEDC_LSTIMER1_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER1 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER1 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER1_M ((LEDC_CLK_DIV_LSTIMER1_V) << (LEDC_CLK_DIV_LSTIMER1_S)) +#define LEDC_CLK_DIV_LSTIMER1_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER1_S 4 +/* LEDC_LSTIMER1_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER1_DUTY_RES 0x0000000F +#define LEDC_LSTIMER1_DUTY_RES_M ((LEDC_LSTIMER1_DUTY_RES_V) << (LEDC_LSTIMER1_DUTY_RES_S)) +#define LEDC_LSTIMER1_DUTY_RES_V 0xF +#define LEDC_LSTIMER1_DUTY_RES_S 0 + +#define LEDC_LSTIMER1_VALUE_REG (DR_REG_LEDC_BASE + 0x00aC) +/* LEDC_LSTIMER1_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_CNT 0x00003FFF +#define LEDC_LSTIMER1_CNT_M ((LEDC_LSTIMER1_CNT_V) << (LEDC_LSTIMER1_CNT_S)) +#define LEDC_LSTIMER1_CNT_V 0x3FFF +#define LEDC_LSTIMER1_CNT_S 0 + +#define LEDC_LSTIMER2_CONF_REG (DR_REG_LEDC_BASE + 0x00b0) +/* LEDC_LSTIMER2_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER2_PARA_UP (BIT(25)) +#define LEDC_LSTIMER2_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER2_PARA_UP_V 0x1 +#define LEDC_LSTIMER2_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER2 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER2 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER2_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER2_V 0x1 +#define LEDC_TICK_SEL_LSTIMER2_S 24 +/* LEDC_LSTIMER2_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER2_RST (BIT(23)) +#define LEDC_LSTIMER2_RST_M (BIT(23)) +#define LEDC_LSTIMER2_RST_V 0x1 +#define LEDC_LSTIMER2_RST_S 23 +/* LEDC_LSTIMER2_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_PAUSE (BIT(22)) +#define LEDC_LSTIMER2_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER2_PAUSE_V 0x1 +#define LEDC_LSTIMER2_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER2 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER2 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER2_M ((LEDC_CLK_DIV_LSTIMER2_V) << (LEDC_CLK_DIV_LSTIMER2_S)) +#define LEDC_CLK_DIV_LSTIMER2_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER2_S 4 +/* LEDC_LSTIMER2_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER2_DUTY_RES 0x0000000F +#define LEDC_LSTIMER2_DUTY_RES_M ((LEDC_LSTIMER2_DUTY_RES_V) << (LEDC_LSTIMER2_DUTY_RES_S)) +#define LEDC_LSTIMER2_DUTY_RES_V 0xF +#define LEDC_LSTIMER2_DUTY_RES_S 0 + +#define LEDC_LSTIMER2_VALUE_REG (DR_REG_LEDC_BASE + 0x00b4) +/* LEDC_LSTIMER2_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_CNT 0x00003FFF +#define LEDC_LSTIMER2_CNT_M ((LEDC_LSTIMER2_CNT_V) << (LEDC_LSTIMER2_CNT_S)) +#define LEDC_LSTIMER2_CNT_V 0x3FFF +#define LEDC_LSTIMER2_CNT_S 0 + +#define LEDC_LSTIMER3_CONF_REG (DR_REG_LEDC_BASE + 0x00b8) +/* LEDC_LSTIMER3_PARA_UP : WO ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_LSTIMER3_PARA_UP (BIT(25)) +#define LEDC_LSTIMER3_PARA_UP_M (BIT(25)) +#define LEDC_LSTIMER3_PARA_UP_V 0x1 +#define LEDC_LSTIMER3_PARA_UP_S 25 +/* LEDC_TICK_SEL_LSTIMER3 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_TICK_SEL_LSTIMER3 (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER3_M (BIT(24)) +#define LEDC_TICK_SEL_LSTIMER3_V 0x1 +#define LEDC_TICK_SEL_LSTIMER3_S 24 +/* LEDC_LSTIMER3_RST : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define LEDC_LSTIMER3_RST (BIT(23)) +#define LEDC_LSTIMER3_RST_M (BIT(23)) +#define LEDC_LSTIMER3_RST_V 0x1 +#define LEDC_LSTIMER3_RST_S 23 +/* LEDC_LSTIMER3_PAUSE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_PAUSE (BIT(22)) +#define LEDC_LSTIMER3_PAUSE_M (BIT(22)) +#define LEDC_LSTIMER3_PAUSE_V 0x1 +#define LEDC_LSTIMER3_PAUSE_S 22 +/* LEDC_CLK_DIV_LSTIMER3 : R/W ;bitpos:[21:4] ;default: 18'h0 ; */ +/*description: */ +#define LEDC_CLK_DIV_LSTIMER3 0x0003FFFF +#define LEDC_CLK_DIV_LSTIMER3_M ((LEDC_CLK_DIV_LSTIMER3_V) << (LEDC_CLK_DIV_LSTIMER3_S)) +#define LEDC_CLK_DIV_LSTIMER3_V 0x3FFFF +#define LEDC_CLK_DIV_LSTIMER3_S 4 +/* LEDC_LSTIMER3_DUTY_RES : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: */ +#define LEDC_LSTIMER3_DUTY_RES 0x0000000F +#define LEDC_LSTIMER3_DUTY_RES_M ((LEDC_LSTIMER3_DUTY_RES_V) << (LEDC_LSTIMER3_DUTY_RES_S)) +#define LEDC_LSTIMER3_DUTY_RES_V 0xF +#define LEDC_LSTIMER3_DUTY_RES_S 0 + +#define LEDC_LSTIMER3_VALUE_REG (DR_REG_LEDC_BASE + 0x00bC) +/* LEDC_LSTIMER3_CNT : RO ;bitpos:[13:0] ;default: 14'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_CNT 0x00003FFF +#define LEDC_LSTIMER3_CNT_M ((LEDC_LSTIMER3_CNT_V) << (LEDC_LSTIMER3_CNT_S)) +#define LEDC_LSTIMER3_CNT_V 0x3FFF +#define LEDC_LSTIMER3_CNT_S 0 + +#define LEDC_INT_RAW_REG (DR_REG_LEDC_BASE + 0x00c0) +/* LEDC_OVF_CNT_LSCH7_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_RAW (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_RAW_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_RAW_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_RAW (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_RAW_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_RAW_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_RAW (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_RAW_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_RAW_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_RAW (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_RAW_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_RAW_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_RAW (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_RAW_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_RAW_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_RAW (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_RAW_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_RAW_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_RAW (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_RAW_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_RAW_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_RAW (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_RAW_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_RAW_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_RAW_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_RAW_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_RAW_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_RAW_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_RAW_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_RAW_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_RAW_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_RAW_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_RAW_S 4 +/* LEDC_LSTIMER3_OVF_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_RAW (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_RAW_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_RAW_S 3 +/* LEDC_LSTIMER2_OVF_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_RAW (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_RAW_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_RAW_S 2 +/* LEDC_LSTIMER1_OVF_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_RAW (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_RAW_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_RAW_S 1 +/* LEDC_LSTIMER0_OVF_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_RAW (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_RAW_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_RAW_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_RAW_S 0 + +#define LEDC_INT_ST_REG (DR_REG_LEDC_BASE + 0x00c4) +/* LEDC_OVF_CNT_LSCH7_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_ST (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ST_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_ST_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_ST (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ST_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_ST_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_ST (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ST_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_ST_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_ST (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ST_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_ST_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_ST (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ST_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_ST_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_ST (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ST_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_ST_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_ST (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ST_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_ST_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_ST (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ST_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ST_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_ST_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ST : RO ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ST_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ST_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ST_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ST_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ST_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ST_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ST_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ST_S 4 +/* LEDC_LSTIMER3_OVF_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_ST (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ST_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ST_S 3 +/* LEDC_LSTIMER2_OVF_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_ST (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ST_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ST_S 2 +/* LEDC_LSTIMER1_OVF_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_ST (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ST_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ST_S 1 +/* LEDC_LSTIMER0_OVF_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_ST (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ST_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ST_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ST_S 0 + +#define LEDC_INT_ENA_REG (DR_REG_LEDC_BASE + 0x00c8) +/* LEDC_OVF_CNT_LSCH7_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_ENA (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ENA_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_ENA_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_ENA (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ENA_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_ENA_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_ENA (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ENA_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_ENA_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_ENA (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ENA_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_ENA_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_ENA (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ENA_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_ENA_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_ENA (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ENA_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_ENA_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_ENA (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ENA_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_ENA_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_ENA (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ENA_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_ENA_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_ENA_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_ENA : R/W ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_ENA_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_ENA_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_ENA_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_ENA_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_ENA_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_ENA_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_ENA_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_ENA_S 4 +/* LEDC_LSTIMER3_OVF_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_ENA (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ENA_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_ENA_S 3 +/* LEDC_LSTIMER2_OVF_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_ENA (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ENA_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_ENA_S 2 +/* LEDC_LSTIMER1_OVF_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_ENA (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ENA_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_ENA_S 1 +/* LEDC_LSTIMER0_OVF_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_ENA (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ENA_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_ENA_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_ENA_S 0 + +#define LEDC_INT_CLR_REG (DR_REG_LEDC_BASE + 0x00cC) +/* LEDC_OVF_CNT_LSCH7_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH7_INT_CLR (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_CLR_M (BIT(19)) +#define LEDC_OVF_CNT_LSCH7_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH7_INT_CLR_S 19 +/* LEDC_OVF_CNT_LSCH6_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH6_INT_CLR (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_CLR_M (BIT(18)) +#define LEDC_OVF_CNT_LSCH6_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH6_INT_CLR_S 18 +/* LEDC_OVF_CNT_LSCH5_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH5_INT_CLR (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_CLR_M (BIT(17)) +#define LEDC_OVF_CNT_LSCH5_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH5_INT_CLR_S 17 +/* LEDC_OVF_CNT_LSCH4_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH4_INT_CLR (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_CLR_M (BIT(16)) +#define LEDC_OVF_CNT_LSCH4_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH4_INT_CLR_S 16 +/* LEDC_OVF_CNT_LSCH3_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH3_INT_CLR (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_CLR_M (BIT(15)) +#define LEDC_OVF_CNT_LSCH3_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH3_INT_CLR_S 15 +/* LEDC_OVF_CNT_LSCH2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH2_INT_CLR (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_CLR_M (BIT(14)) +#define LEDC_OVF_CNT_LSCH2_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH2_INT_CLR_S 14 +/* LEDC_OVF_CNT_LSCH1_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH1_INT_CLR (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_CLR_M (BIT(13)) +#define LEDC_OVF_CNT_LSCH1_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH1_INT_CLR_S 13 +/* LEDC_OVF_CNT_LSCH0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_OVF_CNT_LSCH0_INT_CLR (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_CLR_M (BIT(12)) +#define LEDC_OVF_CNT_LSCH0_INT_CLR_V 0x1 +#define LEDC_OVF_CNT_LSCH0_INT_CLR_S 12 +/* LEDC_DUTY_CHNG_END_LSCH7_INT_CLR : WO ;bitpos:[11] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_M (BIT(11)) +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH7_INT_CLR_S 11 +/* LEDC_DUTY_CHNG_END_LSCH6_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_M (BIT(10)) +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH6_INT_CLR_S 10 +/* LEDC_DUTY_CHNG_END_LSCH5_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_M (BIT(9)) +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH5_INT_CLR_S 9 +/* LEDC_DUTY_CHNG_END_LSCH4_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_M (BIT(8)) +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH4_INT_CLR_S 8 +/* LEDC_DUTY_CHNG_END_LSCH3_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_M (BIT(7)) +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH3_INT_CLR_S 7 +/* LEDC_DUTY_CHNG_END_LSCH2_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_M (BIT(6)) +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH2_INT_CLR_S 6 +/* LEDC_DUTY_CHNG_END_LSCH1_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_M (BIT(5)) +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH1_INT_CLR_S 5 +/* LEDC_DUTY_CHNG_END_LSCH0_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_M (BIT(4)) +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_V 0x1 +#define LEDC_DUTY_CHNG_END_LSCH0_INT_CLR_S 4 +/* LEDC_LSTIMER3_OVF_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER3_OVF_INT_CLR (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_CLR_M (BIT(3)) +#define LEDC_LSTIMER3_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER3_OVF_INT_CLR_S 3 +/* LEDC_LSTIMER2_OVF_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER2_OVF_INT_CLR (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_CLR_M (BIT(2)) +#define LEDC_LSTIMER2_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER2_OVF_INT_CLR_S 2 +/* LEDC_LSTIMER1_OVF_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER1_OVF_INT_CLR (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_CLR_M (BIT(1)) +#define LEDC_LSTIMER1_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER1_OVF_INT_CLR_S 1 +/* LEDC_LSTIMER0_OVF_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define LEDC_LSTIMER0_OVF_INT_CLR (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_CLR_M (BIT(0)) +#define LEDC_LSTIMER0_OVF_INT_CLR_V 0x1 +#define LEDC_LSTIMER0_OVF_INT_CLR_S 0 + +#define LEDC_CONF_REG (DR_REG_LEDC_BASE + 0x00d0) +/* LEDC_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define LEDC_CLK_EN (BIT(31)) +#define LEDC_CLK_EN_M (BIT(31)) +#define LEDC_CLK_EN_V 0x1 +#define LEDC_CLK_EN_S 31 +/* LEDC_APB_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define LEDC_APB_CLK_SEL 0x00000003 +#define LEDC_APB_CLK_SEL_M ((LEDC_APB_CLK_SEL_V) << (LEDC_APB_CLK_SEL_S)) +#define LEDC_APB_CLK_SEL_V 0x3 +#define LEDC_APB_CLK_SEL_S 0 + +#define LEDC_DATE_REG (DR_REG_LEDC_BASE + 0x00FC) +/* LEDC_DATE : R/W ;bitpos:[31:0] ;default: 32'h19040200 ; */ +/*description: */ +#define LEDC_DATE 0xFFFFFFFF +#define LEDC_DATE_M ((LEDC_DATE_V) << (LEDC_DATE_S)) +#define LEDC_DATE_V 0xFFFFFFFF +#define LEDC_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/ledc_struct.h b/components/soc/soc/esp32s3/include/soc/ledc_struct.h new file mode 100644 index 000000000..20706219b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/ledc_struct.h @@ -0,0 +1,224 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + struct { + struct { + union { + struct { + uint32_t timer_sel: 2; + uint32_t sig_out_en: 1; + uint32_t idle_lv: 1; + uint32_t low_speed_update: 1; + uint32_t ovf_num: 10; + uint32_t ovf_cnt_en: 1; + uint32_t ovf_cnt_rst: 1; + uint32_t ovf_cnt_rst_st: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t hpoint: 14; + uint32_t reserved14: 18; + }; + uint32_t val; + } hpoint; + union { + struct { + uint32_t duty: 19; + uint32_t reserved19: 13; + }; + uint32_t val; + } duty; + union { + struct { + uint32_t duty_scale: 10; + uint32_t duty_cycle: 10; + uint32_t duty_num: 10; + uint32_t duty_inc: 1; + uint32_t duty_start: 1; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t duty_read: 19; + uint32_t reserved19: 13; + }; + uint32_t val; + } duty_rd; + } channel[8]; + } channel_group[1]; + struct { + struct { + union { + struct { + uint32_t duty_resolution: 4; + uint32_t clock_divider: 18; + uint32_t pause: 1; + uint32_t rst: 1; + uint32_t tick_sel: 1; + uint32_t low_speed_update: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } conf; + union { + struct { + uint32_t timer_cnt: 14; + uint32_t reserved14: 18; + }; + uint32_t val; + } value; + } timer[4]; + } timer_group[1]; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t lstimer0_ovf: 1; + uint32_t lstimer1_ovf: 1; + uint32_t lstimer2_ovf: 1; + uint32_t lstimer3_ovf: 1; + uint32_t duty_chng_end_lsch0: 1; + uint32_t duty_chng_end_lsch1: 1; + uint32_t duty_chng_end_lsch2: 1; + uint32_t duty_chng_end_lsch3: 1; + uint32_t duty_chng_end_lsch4: 1; + uint32_t duty_chng_end_lsch5: 1; + uint32_t duty_chng_end_lsch6: 1; + uint32_t duty_chng_end_lsch7: 1; + uint32_t ovf_cnt_lsch0: 1; + uint32_t ovf_cnt_lsch1: 1; + uint32_t ovf_cnt_lsch2: 1; + uint32_t ovf_cnt_lsch3: 1; + uint32_t ovf_cnt_lsch4: 1; + uint32_t ovf_cnt_lsch5: 1; + uint32_t ovf_cnt_lsch6: 1; + uint32_t ovf_cnt_lsch7: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t apb_clk_sel: 2; + uint32_t reserved2: 29; + uint32_t clk_en: 1; + }; + uint32_t val; + } conf; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} ledc_dev_t; + +extern ledc_dev_t LEDC; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/mcpwm_reg.h b/components/soc/soc/esp32s3/include/soc/mcpwm_reg.h new file mode 100644 index 000000000..3a3928775 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/mcpwm_reg.h @@ -0,0 +1,2902 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define MCPWM_CLK_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0000) +/* MCPWM_CLK_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define MCPWM_CLK_PRESCALE 0x000000FF +#define MCPWM_CLK_PRESCALE_M ((MCPWM_CLK_PRESCALE_V) << (MCPWM_CLK_PRESCALE_S)) +#define MCPWM_CLK_PRESCALE_V 0xFF +#define MCPWM_CLK_PRESCALE_S 0 + +#define MCPWM_TIMER0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0004) +/* MCPWM_TIMER0_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: 0: immediate 1: eqz 2: sync 3: eqz | sync*/ +#define MCPWM_TIMER0_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_M ((MCPWM_TIMER0_PERIOD_UPMETHOD_V) << (MCPWM_TIMER0_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER0_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER0_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER0_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: */ +#define MCPWM_TIMER0_PERIOD 0x0000FFFF +#define MCPWM_TIMER0_PERIOD_M ((MCPWM_TIMER0_PERIOD_V) << (MCPWM_TIMER0_PERIOD_S)) +#define MCPWM_TIMER0_PERIOD_V 0xFFFF +#define MCPWM_TIMER0_PERIOD_S 8 +/* MCPWM_TIMER0_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_PRESCALE 0x000000FF +#define MCPWM_TIMER0_PRESCALE_M ((MCPWM_TIMER0_PRESCALE_V) << (MCPWM_TIMER0_PRESCALE_S)) +#define MCPWM_TIMER0_PRESCALE_V 0xFF +#define MCPWM_TIMER0_PRESCALE_S 0 + +#define MCPWM_TIMER0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0008) +/* MCPWM_TIMER0_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: 0: freeze 1: inc 2: dec 3: up-down*/ +#define MCPWM_TIMER0_MOD 0x00000003 +#define MCPWM_TIMER0_MOD_M ((MCPWM_TIMER0_MOD_V) << (MCPWM_TIMER0_MOD_S)) +#define MCPWM_TIMER0_MOD_V 0x3 +#define MCPWM_TIMER0_MOD_S 3 +/* MCPWM_TIMER0_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: 0: stop @ eqz 1: stop @ eqp 2: free run 3: start and stop + @ next eqz 4: start and stop @ next eqp*/ +#define MCPWM_TIMER0_START 0x00000007 +#define MCPWM_TIMER0_START_M ((MCPWM_TIMER0_START_V) << (MCPWM_TIMER0_START_S)) +#define MCPWM_TIMER0_START_V 0x7 +#define MCPWM_TIMER0_START_S 0 + +#define MCPWM_TIMER0_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x000c) +/* MCPWM_TIMER0_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: */ +#define MCPWM_TIMER0_PHASE 0x0001FFFF +#define MCPWM_TIMER0_PHASE_M ((MCPWM_TIMER0_PHASE_V) << (MCPWM_TIMER0_PHASE_S)) +#define MCPWM_TIMER0_PHASE_V 0x1FFFF +#define MCPWM_TIMER0_PHASE_S 4 +/* MCPWM_TIMER0_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_TIMER0_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER0_SYNCO_SEL_M ((MCPWM_TIMER0_SYNCO_SEL_V) << (MCPWM_TIMER0_SYNCO_SEL_S)) +#define MCPWM_TIMER0_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER0_SYNCO_SEL_S 2 +/* MCPWM_TIMER0_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: write the negate value will trigger a sw sync*/ +#define MCPWM_TIMER0_SYNC_SW (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER0_SYNC_SW_V 0x1 +#define MCPWM_TIMER0_SYNC_SW_S 1 +/* MCPWM_TIMER0_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER0_SYNCI_EN_V 0x1 +#define MCPWM_TIMER0_SYNCI_EN_S 0 + +#define MCPWM_TIMER0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0010) +/* MCPWM_TIMER0_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TIMER0_DIRECTION (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER0_DIRECTION_V 0x1 +#define MCPWM_TIMER0_DIRECTION_S 16 +/* MCPWM_TIMER0_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_TIMER0_VALUE 0x0000FFFF +#define MCPWM_TIMER0_VALUE_M ((MCPWM_TIMER0_VALUE_V) << (MCPWM_TIMER0_VALUE_S)) +#define MCPWM_TIMER0_VALUE_V 0xFFFF +#define MCPWM_TIMER0_VALUE_S 0 + +#define MCPWM_TIMER1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0014) +/* MCPWM_TIMER1_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_TIMER1_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_M ((MCPWM_TIMER1_PERIOD_UPMETHOD_V) << (MCPWM_TIMER1_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER1_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER1_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER1_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: */ +#define MCPWM_TIMER1_PERIOD 0x0000FFFF +#define MCPWM_TIMER1_PERIOD_M ((MCPWM_TIMER1_PERIOD_V) << (MCPWM_TIMER1_PERIOD_S)) +#define MCPWM_TIMER1_PERIOD_V 0xFFFF +#define MCPWM_TIMER1_PERIOD_S 8 +/* MCPWM_TIMER1_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_PRESCALE 0x000000FF +#define MCPWM_TIMER1_PRESCALE_M ((MCPWM_TIMER1_PRESCALE_V) << (MCPWM_TIMER1_PRESCALE_S)) +#define MCPWM_TIMER1_PRESCALE_V 0xFF +#define MCPWM_TIMER1_PRESCALE_S 0 + +#define MCPWM_TIMER1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0018) +/* MCPWM_TIMER1_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: 0: freeze 1: inc 2: dec 3: up-down*/ +#define MCPWM_TIMER1_MOD 0x00000003 +#define MCPWM_TIMER1_MOD_M ((MCPWM_TIMER1_MOD_V) << (MCPWM_TIMER1_MOD_S)) +#define MCPWM_TIMER1_MOD_V 0x3 +#define MCPWM_TIMER1_MOD_S 3 +/* MCPWM_TIMER1_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_START 0x00000007 +#define MCPWM_TIMER1_START_M ((MCPWM_TIMER1_START_V) << (MCPWM_TIMER1_START_S)) +#define MCPWM_TIMER1_START_V 0x7 +#define MCPWM_TIMER1_START_S 0 + +#define MCPWM_TIMER1_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x001c) +/* MCPWM_TIMER1_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: */ +#define MCPWM_TIMER1_PHASE 0x0001FFFF +#define MCPWM_TIMER1_PHASE_M ((MCPWM_TIMER1_PHASE_V) << (MCPWM_TIMER1_PHASE_S)) +#define MCPWM_TIMER1_PHASE_V 0x1FFFF +#define MCPWM_TIMER1_PHASE_S 4 +/* MCPWM_TIMER1_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: 0: synci 1: tez 2: tep else 0*/ +#define MCPWM_TIMER1_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER1_SYNCO_SEL_M ((MCPWM_TIMER1_SYNCO_SEL_V) << (MCPWM_TIMER1_SYNCO_SEL_S)) +#define MCPWM_TIMER1_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER1_SYNCO_SEL_S 2 +/* MCPWM_TIMER1_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: write the negate value will trigger a sw sync*/ +#define MCPWM_TIMER1_SYNC_SW (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER1_SYNC_SW_V 0x1 +#define MCPWM_TIMER1_SYNC_SW_S 1 +/* MCPWM_TIMER1_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER1_SYNCI_EN_V 0x1 +#define MCPWM_TIMER1_SYNCI_EN_S 0 + +#define MCPWM_TIMER1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0020) +/* MCPWM_TIMER1_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TIMER1_DIRECTION (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER1_DIRECTION_V 0x1 +#define MCPWM_TIMER1_DIRECTION_S 16 +/* MCPWM_TIMER1_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_TIMER1_VALUE 0x0000FFFF +#define MCPWM_TIMER1_VALUE_M ((MCPWM_TIMER1_VALUE_V) << (MCPWM_TIMER1_VALUE_S)) +#define MCPWM_TIMER1_VALUE_V 0xFFFF +#define MCPWM_TIMER1_VALUE_S 0 + +#define MCPWM_TIMER2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0024) +/* MCPWM_TIMER2_PERIOD_UPMETHOD : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_TIMER2_PERIOD_UPMETHOD 0x00000003 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_M ((MCPWM_TIMER2_PERIOD_UPMETHOD_V) << (MCPWM_TIMER2_PERIOD_UPMETHOD_S)) +#define MCPWM_TIMER2_PERIOD_UPMETHOD_V 0x3 +#define MCPWM_TIMER2_PERIOD_UPMETHOD_S 24 +/* MCPWM_TIMER2_PERIOD : R/W ;bitpos:[23:8] ;default: 16'h00ff ; */ +/*description: */ +#define MCPWM_TIMER2_PERIOD 0x0000FFFF +#define MCPWM_TIMER2_PERIOD_M ((MCPWM_TIMER2_PERIOD_V) << (MCPWM_TIMER2_PERIOD_S)) +#define MCPWM_TIMER2_PERIOD_V 0xFFFF +#define MCPWM_TIMER2_PERIOD_S 8 +/* MCPWM_TIMER2_PRESCALE : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_PRESCALE 0x000000FF +#define MCPWM_TIMER2_PRESCALE_M ((MCPWM_TIMER2_PRESCALE_V) << (MCPWM_TIMER2_PRESCALE_S)) +#define MCPWM_TIMER2_PRESCALE_V 0xFF +#define MCPWM_TIMER2_PRESCALE_S 0 + +#define MCPWM_TIMER2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x0028) +/* MCPWM_TIMER2_MOD : R/W ;bitpos:[4:3] ;default: 2'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_MOD 0x00000003 +#define MCPWM_TIMER2_MOD_M ((MCPWM_TIMER2_MOD_V) << (MCPWM_TIMER2_MOD_S)) +#define MCPWM_TIMER2_MOD_V 0x3 +#define MCPWM_TIMER2_MOD_S 3 +/* MCPWM_TIMER2_START : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_START 0x00000007 +#define MCPWM_TIMER2_START_M ((MCPWM_TIMER2_START_V) << (MCPWM_TIMER2_START_S)) +#define MCPWM_TIMER2_START_V 0x7 +#define MCPWM_TIMER2_START_S 0 + +#define MCPWM_TIMER2_SYNC_REG(i) (REG_MCPWM_BASE(i) + 0x002c) +/* MCPWM_TIMER2_PHASE : R/W ;bitpos:[20:4] ;default: 17'd0 ; */ +/*description: */ +#define MCPWM_TIMER2_PHASE 0x0001FFFF +#define MCPWM_TIMER2_PHASE_M ((MCPWM_TIMER2_PHASE_V) << (MCPWM_TIMER2_PHASE_S)) +#define MCPWM_TIMER2_PHASE_V 0x1FFFF +#define MCPWM_TIMER2_PHASE_S 4 +/* MCPWM_TIMER2_SYNCO_SEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_TIMER2_SYNCO_SEL 0x00000003 +#define MCPWM_TIMER2_SYNCO_SEL_M ((MCPWM_TIMER2_SYNCO_SEL_V) << (MCPWM_TIMER2_SYNCO_SEL_S)) +#define MCPWM_TIMER2_SYNCO_SEL_V 0x3 +#define MCPWM_TIMER2_SYNCO_SEL_S 2 +/* MCPWM_TIMER2_SYNC_SW : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: write the negate value will trigger a sw sync*/ +#define MCPWM_TIMER2_SYNC_SW (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_M (BIT(1)) +#define MCPWM_TIMER2_SYNC_SW_V 0x1 +#define MCPWM_TIMER2_SYNC_SW_S 1 +/* MCPWM_TIMER2_SYNCI_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_SYNCI_EN (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_M (BIT(0)) +#define MCPWM_TIMER2_SYNCI_EN_V 0x1 +#define MCPWM_TIMER2_SYNCI_EN_S 0 + +#define MCPWM_TIMER2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0030) +/* MCPWM_TIMER2_DIRECTION : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TIMER2_DIRECTION (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_M (BIT(16)) +#define MCPWM_TIMER2_DIRECTION_V 0x1 +#define MCPWM_TIMER2_DIRECTION_S 16 +/* MCPWM_TIMER2_VALUE : RO ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_TIMER2_VALUE 0x0000FFFF +#define MCPWM_TIMER2_VALUE_M ((MCPWM_TIMER2_VALUE_V) << (MCPWM_TIMER2_VALUE_S)) +#define MCPWM_TIMER2_VALUE_V 0xFFFF +#define MCPWM_TIMER2_VALUE_S 0 + +#define MCPWM_TIMER_SYNCI_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0034) +/* MCPWM_EXTERNAL_SYNCI2_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_EXTERNAL_SYNCI2_INVERT (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_M (BIT(11)) +#define MCPWM_EXTERNAL_SYNCI2_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI2_INVERT_S 11 +/* MCPWM_EXTERNAL_SYNCI1_INVERT : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_EXTERNAL_SYNCI1_INVERT (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_M (BIT(10)) +#define MCPWM_EXTERNAL_SYNCI1_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI1_INVERT_S 10 +/* MCPWM_EXTERNAL_SYNCI0_INVERT : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_EXTERNAL_SYNCI0_INVERT (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_M (BIT(9)) +#define MCPWM_EXTERNAL_SYNCI0_INVERT_V 0x1 +#define MCPWM_EXTERNAL_SYNCI0_INVERT_S 9 +/* MCPWM_TIMER2_SYNCISEL : R/W ;bitpos:[8:6] ;default: 3'd0 ; */ +/*description: */ +#define MCPWM_TIMER2_SYNCISEL 0x00000007 +#define MCPWM_TIMER2_SYNCISEL_M ((MCPWM_TIMER2_SYNCISEL_V) << (MCPWM_TIMER2_SYNCISEL_S)) +#define MCPWM_TIMER2_SYNCISEL_V 0x7 +#define MCPWM_TIMER2_SYNCISEL_S 6 +/* MCPWM_TIMER1_SYNCISEL : R/W ;bitpos:[5:3] ;default: 3'd0 ; */ +/*description: */ +#define MCPWM_TIMER1_SYNCISEL 0x00000007 +#define MCPWM_TIMER1_SYNCISEL_M ((MCPWM_TIMER1_SYNCISEL_V) << (MCPWM_TIMER1_SYNCISEL_S)) +#define MCPWM_TIMER1_SYNCISEL_V 0x7 +#define MCPWM_TIMER1_SYNCISEL_S 3 +/* MCPWM_TIMER0_SYNCISEL : R/W ;bitpos:[2:0] ;default: 3'd0 ; */ +/*description: */ +#define MCPWM_TIMER0_SYNCISEL 0x00000007 +#define MCPWM_TIMER0_SYNCISEL_M ((MCPWM_TIMER0_SYNCISEL_V) << (MCPWM_TIMER0_SYNCISEL_S)) +#define MCPWM_TIMER0_SYNCISEL_V 0x7 +#define MCPWM_TIMER0_SYNCISEL_S 0 + +#define MCPWM_OPERATOR_TIMERSEL_REG(i) (REG_MCPWM_BASE(i) + 0x0038) +/* MCPWM_OPERATOR2_TIMERSEL : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR2_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR2_TIMERSEL_M ((MCPWM_OPERATOR2_TIMERSEL_V) << (MCPWM_OPERATOR2_TIMERSEL_S)) +#define MCPWM_OPERATOR2_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR2_TIMERSEL_S 4 +/* MCPWM_OPERATOR1_TIMERSEL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR1_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR1_TIMERSEL_M ((MCPWM_OPERATOR1_TIMERSEL_V) << (MCPWM_OPERATOR1_TIMERSEL_S)) +#define MCPWM_OPERATOR1_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR1_TIMERSEL_S 2 +/* MCPWM_OPERATOR0_TIMERSEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: 0: timer0 1: timer1 2: timer2*/ +#define MCPWM_OPERATOR0_TIMERSEL 0x00000003 +#define MCPWM_OPERATOR0_TIMERSEL_M ((MCPWM_OPERATOR0_TIMERSEL_V) << (MCPWM_OPERATOR0_TIMERSEL_S)) +#define MCPWM_OPERATOR0_TIMERSEL_V 0x3 +#define MCPWM_OPERATOR0_TIMERSEL_S 0 + +#define MCPWM_CMPR0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x003c) +/* MCPWM_CMPR0_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR0_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_CMPR0_B_SHDW_FULL_V 0x1 +#define MCPWM_CMPR0_B_SHDW_FULL_S 9 +/* MCPWM_CMPR0_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR0_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_CMPR0_A_SHDW_FULL_V 0x1 +#define MCPWM_CMPR0_A_SHDW_FULL_S 8 +/* MCPWM_CMPR0_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_CMPR0_B_UPMETHOD 0x0000000F +#define MCPWM_CMPR0_B_UPMETHOD_M ((MCPWM_CMPR0_B_UPMETHOD_V) << (MCPWM_CMPR0_B_UPMETHOD_S)) +#define MCPWM_CMPR0_B_UPMETHOD_V 0xF +#define MCPWM_CMPR0_B_UPMETHOD_S 4 +/* MCPWM_CMPR0_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_CMPR0_A_UPMETHOD 0x0000000F +#define MCPWM_CMPR0_A_UPMETHOD_M ((MCPWM_CMPR0_A_UPMETHOD_V) << (MCPWM_CMPR0_A_UPMETHOD_S)) +#define MCPWM_CMPR0_A_UPMETHOD_V 0xF +#define MCPWM_CMPR0_A_UPMETHOD_S 0 + +#define MCPWM_CMPR0_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x0040) +/* MCPWM_CMPR0_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_A 0x0000FFFF +#define MCPWM_CMPR0_A_M ((MCPWM_CMPR0_A_V) << (MCPWM_CMPR0_A_S)) +#define MCPWM_CMPR0_A_V 0xFFFF +#define MCPWM_CMPR0_A_S 0 + +#define MCPWM_CMPR0_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x0044) +/* MCPWM_CMPR0_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_B 0x0000FFFF +#define MCPWM_CMPR0_B_M ((MCPWM_CMPR0_B_V) << (MCPWM_CMPR0_B_S)) +#define MCPWM_CMPR0_B_V 0xFFFF +#define MCPWM_CMPR0_B_S 0 + +#define MCPWM_GEN0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0048) +/* MCPWM_GEN0_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ +#define MCPWM_GEN0_T1_SEL 0x00000007 +#define MCPWM_GEN0_T1_SEL_M ((MCPWM_GEN0_T1_SEL_V) << (MCPWM_GEN0_T1_SEL_S)) +#define MCPWM_GEN0_T1_SEL_V 0x7 +#define MCPWM_GEN0_T1_SEL_S 7 +/* MCPWM_GEN0_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ +#define MCPWM_GEN0_T0_SEL 0x00000007 +#define MCPWM_GEN0_T0_SEL_M ((MCPWM_GEN0_T0_SEL_V) << (MCPWM_GEN0_T0_SEL_S)) +#define MCPWM_GEN0_T0_SEL_V 0x7 +#define MCPWM_GEN0_T0_SEL_S 4 +/* MCPWM_GEN0_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ +#define MCPWM_GEN0_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN0_CFG_UPMETHOD_M ((MCPWM_GEN0_CFG_UPMETHOD_V) << (MCPWM_GEN0_CFG_UPMETHOD_S)) +#define MCPWM_GEN0_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN0_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN0_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x004c) +/* MCPWM_GEN0_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_NCIFORCE_MODE_M ((MCPWM_GEN0_B_NCIFORCE_MODE_V) << (MCPWM_GEN0_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN0_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: non-continuous immediate sw force a toggle will trigger a force event*/ +#define MCPWM_GEN0_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN0_B_NCIFORCE_V 0x1 +#define MCPWM_GEN0_B_NCIFORCE_S 13 +/* MCPWM_GEN0_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_NCIFORCE_MODE_M ((MCPWM_GEN0_A_NCIFORCE_MODE_V) << (MCPWM_GEN0_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN0_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN0_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: non-continuous immediate sw force a toggle will trigger a force event*/ +#define MCPWM_GEN0_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN0_A_NCIFORCE_V 0x1 +#define MCPWM_GEN0_A_NCIFORCE_S 10 +/* MCPWM_GEN0_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_M ((MCPWM_GEN0_B_CNTUFORCE_MODE_V) << (MCPWM_GEN0_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN0_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN0_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_M ((MCPWM_GEN0_A_CNTUFORCE_MODE_V) << (MCPWM_GEN0_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN0_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN0_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN0_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: + sync bit5: freeze*/ +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN0_CNTUFORCE_UPMETHOD_V) << (MCPWM_GEN0_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN0_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN0_A_REG(i) (REG_MCPWM_BASE(i) + 0x0050) +/* MCPWM_GEN0_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN0_A_DT1 0x00000003 +#define MCPWM_GEN0_A_DT1_M ((MCPWM_GEN0_A_DT1_V) << (MCPWM_GEN0_A_DT1_S)) +#define MCPWM_GEN0_A_DT1_V 0x3 +#define MCPWM_GEN0_A_DT1_S 22 +/* MCPWM_GEN0_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_DT0 0x00000003 +#define MCPWM_GEN0_A_DT0_M ((MCPWM_GEN0_A_DT0_V) << (MCPWM_GEN0_A_DT0_S)) +#define MCPWM_GEN0_A_DT0_V 0x3 +#define MCPWM_GEN0_A_DT0_S 20 +/* MCPWM_GEN0_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_DTEB 0x00000003 +#define MCPWM_GEN0_A_DTEB_M ((MCPWM_GEN0_A_DTEB_V) << (MCPWM_GEN0_A_DTEB_S)) +#define MCPWM_GEN0_A_DTEB_V 0x3 +#define MCPWM_GEN0_A_DTEB_S 18 +/* MCPWM_GEN0_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_DTEA 0x00000003 +#define MCPWM_GEN0_A_DTEA_M ((MCPWM_GEN0_A_DTEA_V) << (MCPWM_GEN0_A_DTEA_S)) +#define MCPWM_GEN0_A_DTEA_V 0x3 +#define MCPWM_GEN0_A_DTEA_S 16 +/* MCPWM_GEN0_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_DTEP 0x00000003 +#define MCPWM_GEN0_A_DTEP_M ((MCPWM_GEN0_A_DTEP_V) << (MCPWM_GEN0_A_DTEP_S)) +#define MCPWM_GEN0_A_DTEP_V 0x3 +#define MCPWM_GEN0_A_DTEP_S 14 +/* MCPWM_GEN0_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_DTEZ 0x00000003 +#define MCPWM_GEN0_A_DTEZ_M ((MCPWM_GEN0_A_DTEZ_V) << (MCPWM_GEN0_A_DTEZ_S)) +#define MCPWM_GEN0_A_DTEZ_V 0x3 +#define MCPWM_GEN0_A_DTEZ_S 12 +/* MCPWM_GEN0_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_UT1 0x00000003 +#define MCPWM_GEN0_A_UT1_M ((MCPWM_GEN0_A_UT1_V) << (MCPWM_GEN0_A_UT1_S)) +#define MCPWM_GEN0_A_UT1_V 0x3 +#define MCPWM_GEN0_A_UT1_S 10 +/* MCPWM_GEN0_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_UT0 0x00000003 +#define MCPWM_GEN0_A_UT0_M ((MCPWM_GEN0_A_UT0_V) << (MCPWM_GEN0_A_UT0_S)) +#define MCPWM_GEN0_A_UT0_V 0x3 +#define MCPWM_GEN0_A_UT0_S 8 +/* MCPWM_GEN0_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_UTEB 0x00000003 +#define MCPWM_GEN0_A_UTEB_M ((MCPWM_GEN0_A_UTEB_V) << (MCPWM_GEN0_A_UTEB_S)) +#define MCPWM_GEN0_A_UTEB_V 0x3 +#define MCPWM_GEN0_A_UTEB_S 6 +/* MCPWM_GEN0_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_UTEA 0x00000003 +#define MCPWM_GEN0_A_UTEA_M ((MCPWM_GEN0_A_UTEA_V) << (MCPWM_GEN0_A_UTEA_S)) +#define MCPWM_GEN0_A_UTEA_V 0x3 +#define MCPWM_GEN0_A_UTEA_S 4 +/* MCPWM_GEN0_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_UTEP 0x00000003 +#define MCPWM_GEN0_A_UTEP_M ((MCPWM_GEN0_A_UTEP_V) << (MCPWM_GEN0_A_UTEP_S)) +#define MCPWM_GEN0_A_UTEP_V 0x3 +#define MCPWM_GEN0_A_UTEP_S 2 +/* MCPWM_GEN0_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_A_UTEZ 0x00000003 +#define MCPWM_GEN0_A_UTEZ_M ((MCPWM_GEN0_A_UTEZ_V) << (MCPWM_GEN0_A_UTEZ_S)) +#define MCPWM_GEN0_A_UTEZ_V 0x3 +#define MCPWM_GEN0_A_UTEZ_S 0 + +#define MCPWM_GEN0_B_REG(i) (REG_MCPWM_BASE(i) + 0x0054) +/* MCPWM_GEN0_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_DT1 0x00000003 +#define MCPWM_GEN0_B_DT1_M ((MCPWM_GEN0_B_DT1_V) << (MCPWM_GEN0_B_DT1_S)) +#define MCPWM_GEN0_B_DT1_V 0x3 +#define MCPWM_GEN0_B_DT1_S 22 +/* MCPWM_GEN0_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_DT0 0x00000003 +#define MCPWM_GEN0_B_DT0_M ((MCPWM_GEN0_B_DT0_V) << (MCPWM_GEN0_B_DT0_S)) +#define MCPWM_GEN0_B_DT0_V 0x3 +#define MCPWM_GEN0_B_DT0_S 20 +/* MCPWM_GEN0_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_DTEB 0x00000003 +#define MCPWM_GEN0_B_DTEB_M ((MCPWM_GEN0_B_DTEB_V) << (MCPWM_GEN0_B_DTEB_S)) +#define MCPWM_GEN0_B_DTEB_V 0x3 +#define MCPWM_GEN0_B_DTEB_S 18 +/* MCPWM_GEN0_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_DTEA 0x00000003 +#define MCPWM_GEN0_B_DTEA_M ((MCPWM_GEN0_B_DTEA_V) << (MCPWM_GEN0_B_DTEA_S)) +#define MCPWM_GEN0_B_DTEA_V 0x3 +#define MCPWM_GEN0_B_DTEA_S 16 +/* MCPWM_GEN0_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_DTEP 0x00000003 +#define MCPWM_GEN0_B_DTEP_M ((MCPWM_GEN0_B_DTEP_V) << (MCPWM_GEN0_B_DTEP_S)) +#define MCPWM_GEN0_B_DTEP_V 0x3 +#define MCPWM_GEN0_B_DTEP_S 14 +/* MCPWM_GEN0_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_DTEZ 0x00000003 +#define MCPWM_GEN0_B_DTEZ_M ((MCPWM_GEN0_B_DTEZ_V) << (MCPWM_GEN0_B_DTEZ_S)) +#define MCPWM_GEN0_B_DTEZ_V 0x3 +#define MCPWM_GEN0_B_DTEZ_S 12 +/* MCPWM_GEN0_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_UT1 0x00000003 +#define MCPWM_GEN0_B_UT1_M ((MCPWM_GEN0_B_UT1_V) << (MCPWM_GEN0_B_UT1_S)) +#define MCPWM_GEN0_B_UT1_V 0x3 +#define MCPWM_GEN0_B_UT1_S 10 +/* MCPWM_GEN0_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_UT0 0x00000003 +#define MCPWM_GEN0_B_UT0_M ((MCPWM_GEN0_B_UT0_V) << (MCPWM_GEN0_B_UT0_S)) +#define MCPWM_GEN0_B_UT0_V 0x3 +#define MCPWM_GEN0_B_UT0_S 8 +/* MCPWM_GEN0_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_UTEB 0x00000003 +#define MCPWM_GEN0_B_UTEB_M ((MCPWM_GEN0_B_UTEB_V) << (MCPWM_GEN0_B_UTEB_S)) +#define MCPWM_GEN0_B_UTEB_V 0x3 +#define MCPWM_GEN0_B_UTEB_S 6 +/* MCPWM_GEN0_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_UTEA 0x00000003 +#define MCPWM_GEN0_B_UTEA_M ((MCPWM_GEN0_B_UTEA_V) << (MCPWM_GEN0_B_UTEA_S)) +#define MCPWM_GEN0_B_UTEA_V 0x3 +#define MCPWM_GEN0_B_UTEA_S 4 +/* MCPWM_GEN0_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_UTEP 0x00000003 +#define MCPWM_GEN0_B_UTEP_M ((MCPWM_GEN0_B_UTEP_V) << (MCPWM_GEN0_B_UTEP_S)) +#define MCPWM_GEN0_B_UTEP_V 0x3 +#define MCPWM_GEN0_B_UTEP_S 2 +/* MCPWM_GEN0_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN0_B_UTEZ 0x00000003 +#define MCPWM_GEN0_B_UTEZ_M ((MCPWM_GEN0_B_UTEZ_V) << (MCPWM_GEN0_B_UTEZ_S)) +#define MCPWM_GEN0_B_UTEZ_V 0x3 +#define MCPWM_GEN0_B_UTEZ_S 0 + +#define MCPWM_DB0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0058) +/* MCPWM_DB0_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB0_CLK_SEL (BIT(17)) +#define MCPWM_DB0_CLK_SEL_M (BIT(17)) +#define MCPWM_DB0_CLK_SEL_V 0x1 +#define MCPWM_DB0_CLK_SEL_S 17 +/* MCPWM_DB0_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_DB0_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB0_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DB0_B_OUTBYPASS_V 0x1 +#define MCPWM_DB0_B_OUTBYPASS_S 16 +/* MCPWM_DB0_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_DB0_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB0_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DB0_A_OUTBYPASS_V 0x1 +#define MCPWM_DB0_A_OUTBYPASS_S 15 +/* MCPWM_DB0_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB0_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB0_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DB0_FED_OUTINVERT_V 0x1 +#define MCPWM_DB0_FED_OUTINVERT_S 14 +/* MCPWM_DB0_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB0_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB0_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DB0_RED_OUTINVERT_V 0x1 +#define MCPWM_DB0_RED_OUTINVERT_S 13 +/* MCPWM_DB0_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB0_FED_INSEL (BIT(12)) +#define MCPWM_DB0_FED_INSEL_M (BIT(12)) +#define MCPWM_DB0_FED_INSEL_V 0x1 +#define MCPWM_DB0_FED_INSEL_S 12 +/* MCPWM_DB0_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB0_RED_INSEL (BIT(11)) +#define MCPWM_DB0_RED_INSEL_M (BIT(11)) +#define MCPWM_DB0_RED_INSEL_V 0x1 +#define MCPWM_DB0_RED_INSEL_S 11 +/* MCPWM_DB0_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB0_B_OUTSWAP (BIT(10)) +#define MCPWM_DB0_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DB0_B_OUTSWAP_V 0x1 +#define MCPWM_DB0_B_OUTSWAP_S 10 +/* MCPWM_DB0_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB0_A_OUTSWAP (BIT(9)) +#define MCPWM_DB0_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DB0_A_OUTSWAP_V 0x1 +#define MCPWM_DB0_A_OUTSWAP_S 9 +/* MCPWM_DB0_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: immediate dual-edge B mode 0: fed/red take effect on different + path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ +#define MCPWM_DB0_DEB_MODE (BIT(8)) +#define MCPWM_DB0_DEB_MODE_M (BIT(8)) +#define MCPWM_DB0_DEB_MODE_V 0x1 +#define MCPWM_DB0_DEB_MODE_S 8 +/* MCPWM_DB0_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_DB0_RED_UPMETHOD 0x0000000F +#define MCPWM_DB0_RED_UPMETHOD_M ((MCPWM_DB0_RED_UPMETHOD_V) << (MCPWM_DB0_RED_UPMETHOD_S)) +#define MCPWM_DB0_RED_UPMETHOD_V 0xF +#define MCPWM_DB0_RED_UPMETHOD_S 4 +/* MCPWM_DB0_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_DB0_FED_UPMETHOD 0x0000000F +#define MCPWM_DB0_FED_UPMETHOD_M ((MCPWM_DB0_FED_UPMETHOD_V) << (MCPWM_DB0_FED_UPMETHOD_S)) +#define MCPWM_DB0_FED_UPMETHOD_V 0xF +#define MCPWM_DB0_FED_UPMETHOD_S 0 + +#define MCPWM_DB0_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x005c) +/* MCPWM_DB0_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_DB0_FED 0x0000FFFF +#define MCPWM_DB0_FED_M ((MCPWM_DB0_FED_V) << (MCPWM_DB0_FED_S)) +#define MCPWM_DB0_FED_V 0xFFFF +#define MCPWM_DB0_FED_S 0 + +#define MCPWM_DB0_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0060) +/* MCPWM_DB0_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_DB0_RED 0x0000FFFF +#define MCPWM_DB0_RED_M ((MCPWM_DB0_RED_V) << (MCPWM_DB0_RED_S)) +#define MCPWM_DB0_RED_V 0xFFFF +#define MCPWM_DB0_RED_S 0 + +#define MCPWM_CHOPPER0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0064) +/* MCPWM_CHOPPER0_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER0_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER0_IN_INVERT_M (BIT(13)) +#define MCPWM_CHOPPER0_IN_INVERT_V 0x1 +#define MCPWM_CHOPPER0_IN_INVERT_S 13 +/* MCPWM_CHOPPER0_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER0_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER0_OUT_INVERT_M (BIT(12)) +#define MCPWM_CHOPPER0_OUT_INVERT_V 0x1 +#define MCPWM_CHOPPER0_OUT_INVERT_S 12 +/* MCPWM_CHOPPER0_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER0_OSHTWTH 0x0000000F +#define MCPWM_CHOPPER0_OSHTWTH_M ((MCPWM_CHOPPER0_OSHTWTH_V) << (MCPWM_CHOPPER0_OSHTWTH_S)) +#define MCPWM_CHOPPER0_OSHTWTH_V 0xF +#define MCPWM_CHOPPER0_OSHTWTH_S 8 +/* MCPWM_CHOPPER0_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER0_DUTY 0x00000007 +#define MCPWM_CHOPPER0_DUTY_M ((MCPWM_CHOPPER0_DUTY_V) << (MCPWM_CHOPPER0_DUTY_S)) +#define MCPWM_CHOPPER0_DUTY_V 0x7 +#define MCPWM_CHOPPER0_DUTY_S 5 +/* MCPWM_CHOPPER0_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER0_PRESCALE 0x0000000F +#define MCPWM_CHOPPER0_PRESCALE_M ((MCPWM_CHOPPER0_PRESCALE_V) << (MCPWM_CHOPPER0_PRESCALE_S)) +#define MCPWM_CHOPPER0_PRESCALE_V 0xF +#define MCPWM_CHOPPER0_PRESCALE_S 1 +/* MCPWM_CHOPPER0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER0_EN (BIT(0)) +#define MCPWM_CHOPPER0_EN_M (BIT(0)) +#define MCPWM_CHOPPER0_EN_V 0x1 +#define MCPWM_CHOPPER0_EN_S 0 + +#define MCPWM_TZ0_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0068) +/* MCPWM_TZ0_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_B_OST_U 0x00000003 +#define MCPWM_TZ0_B_OST_U_M ((MCPWM_TZ0_B_OST_U_V) << (MCPWM_TZ0_B_OST_U_S)) +#define MCPWM_TZ0_B_OST_U_V 0x3 +#define MCPWM_TZ0_B_OST_U_S 22 +/* MCPWM_TZ0_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_B_OST_D 0x00000003 +#define MCPWM_TZ0_B_OST_D_M ((MCPWM_TZ0_B_OST_D_V) << (MCPWM_TZ0_B_OST_D_S)) +#define MCPWM_TZ0_B_OST_D_V 0x3 +#define MCPWM_TZ0_B_OST_D_S 20 +/* MCPWM_TZ0_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_B_CBC_U 0x00000003 +#define MCPWM_TZ0_B_CBC_U_M ((MCPWM_TZ0_B_CBC_U_V) << (MCPWM_TZ0_B_CBC_U_S)) +#define MCPWM_TZ0_B_CBC_U_V 0x3 +#define MCPWM_TZ0_B_CBC_U_S 18 +/* MCPWM_TZ0_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_B_CBC_D 0x00000003 +#define MCPWM_TZ0_B_CBC_D_M ((MCPWM_TZ0_B_CBC_D_V) << (MCPWM_TZ0_B_CBC_D_S)) +#define MCPWM_TZ0_B_CBC_D_V 0x3 +#define MCPWM_TZ0_B_CBC_D_S 16 +/* MCPWM_TZ0_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_A_OST_U 0x00000003 +#define MCPWM_TZ0_A_OST_U_M ((MCPWM_TZ0_A_OST_U_V) << (MCPWM_TZ0_A_OST_U_S)) +#define MCPWM_TZ0_A_OST_U_V 0x3 +#define MCPWM_TZ0_A_OST_U_S 14 +/* MCPWM_TZ0_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_A_OST_D 0x00000003 +#define MCPWM_TZ0_A_OST_D_M ((MCPWM_TZ0_A_OST_D_V) << (MCPWM_TZ0_A_OST_D_S)) +#define MCPWM_TZ0_A_OST_D_V 0x3 +#define MCPWM_TZ0_A_OST_D_S 12 +/* MCPWM_TZ0_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_A_CBC_U 0x00000003 +#define MCPWM_TZ0_A_CBC_U_M ((MCPWM_TZ0_A_CBC_U_V) << (MCPWM_TZ0_A_CBC_U_S)) +#define MCPWM_TZ0_A_CBC_U_V 0x3 +#define MCPWM_TZ0_A_CBC_U_S 10 +/* MCPWM_TZ0_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ0_A_CBC_D 0x00000003 +#define MCPWM_TZ0_A_CBC_D_M ((MCPWM_TZ0_A_CBC_D_V) << (MCPWM_TZ0_A_CBC_D_S)) +#define MCPWM_TZ0_A_CBC_D_V 0x3 +#define MCPWM_TZ0_A_CBC_D_S 8 +/* MCPWM_TZ0_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_F0_OST (BIT(7)) +#define MCPWM_TZ0_F0_OST_M (BIT(7)) +#define MCPWM_TZ0_F0_OST_V 0x1 +#define MCPWM_TZ0_F0_OST_S 7 +/* MCPWM_TZ0_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_F1_OST (BIT(6)) +#define MCPWM_TZ0_F1_OST_M (BIT(6)) +#define MCPWM_TZ0_F1_OST_V 0x1 +#define MCPWM_TZ0_F1_OST_S 6 +/* MCPWM_TZ0_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_F2_OST (BIT(5)) +#define MCPWM_TZ0_F2_OST_M (BIT(5)) +#define MCPWM_TZ0_F2_OST_V 0x1 +#define MCPWM_TZ0_F2_OST_S 5 +/* MCPWM_TZ0_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_SW_OST (BIT(4)) +#define MCPWM_TZ0_SW_OST_M (BIT(4)) +#define MCPWM_TZ0_SW_OST_V 0x1 +#define MCPWM_TZ0_SW_OST_S 4 +/* MCPWM_TZ0_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_F0_CBC (BIT(3)) +#define MCPWM_TZ0_F0_CBC_M (BIT(3)) +#define MCPWM_TZ0_F0_CBC_V 0x1 +#define MCPWM_TZ0_F0_CBC_S 3 +/* MCPWM_TZ0_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_F1_CBC (BIT(2)) +#define MCPWM_TZ0_F1_CBC_M (BIT(2)) +#define MCPWM_TZ0_F1_CBC_V 0x1 +#define MCPWM_TZ0_F1_CBC_S 2 +/* MCPWM_TZ0_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_F2_CBC (BIT(1)) +#define MCPWM_TZ0_F2_CBC_M (BIT(1)) +#define MCPWM_TZ0_F2_CBC_V 0x1 +#define MCPWM_TZ0_F2_CBC_S 1 +/* MCPWM_TZ0_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ0_SW_CBC (BIT(0)) +#define MCPWM_TZ0_SW_CBC_M (BIT(0)) +#define MCPWM_TZ0_SW_CBC_V 0x1 +#define MCPWM_TZ0_SW_CBC_S 0 + +#define MCPWM_TZ0_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x006c) +/* MCPWM_TZ0_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: a toggle trigger a oneshot tripping*/ +#define MCPWM_TZ0_FORCE_OST (BIT(4)) +#define MCPWM_TZ0_FORCE_OST_M (BIT(4)) +#define MCPWM_TZ0_FORCE_OST_V 0x1 +#define MCPWM_TZ0_FORCE_OST_S 4 +/* MCPWM_TZ0_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: a toggle trigger a cycle-by-cycle tripping*/ +#define MCPWM_TZ0_FORCE_CBC (BIT(3)) +#define MCPWM_TZ0_FORCE_CBC_M (BIT(3)) +#define MCPWM_TZ0_FORCE_CBC_V 0x1 +#define MCPWM_TZ0_FORCE_CBC_S 3 +/* MCPWM_TZ0_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: bit0: tez bit1: tep*/ +#define MCPWM_TZ0_CBCPULSE 0x00000003 +#define MCPWM_TZ0_CBCPULSE_M ((MCPWM_TZ0_CBCPULSE_V) << (MCPWM_TZ0_CBCPULSE_S)) +#define MCPWM_TZ0_CBCPULSE_V 0x3 +#define MCPWM_TZ0_CBCPULSE_S 1 +/* MCPWM_TZ0_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: a toggle will clear oneshot tripping*/ +#define MCPWM_TZ0_CLR_OST (BIT(0)) +#define MCPWM_TZ0_CLR_OST_M (BIT(0)) +#define MCPWM_TZ0_CLR_OST_V 0x1 +#define MCPWM_TZ0_CLR_OST_S 0 + +#define MCPWM_TZ0_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0070) +/* MCPWM_TZ0_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_OST_ON (BIT(1)) +#define MCPWM_TZ0_OST_ON_M (BIT(1)) +#define MCPWM_TZ0_OST_ON_V 0x1 +#define MCPWM_TZ0_OST_ON_S 1 +/* MCPWM_TZ0_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_CBC_ON (BIT(0)) +#define MCPWM_TZ0_CBC_ON_M (BIT(0)) +#define MCPWM_TZ0_CBC_ON_V 0x1 +#define MCPWM_TZ0_CBC_ON_S 0 + +#define MCPWM_CMPR1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0074) +/* MCPWM_CMPR1_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR1_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_CMPR1_B_SHDW_FULL_V 0x1 +#define MCPWM_CMPR1_B_SHDW_FULL_S 9 +/* MCPWM_CMPR1_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR1_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_CMPR1_A_SHDW_FULL_V 0x1 +#define MCPWM_CMPR1_A_SHDW_FULL_S 8 +/* MCPWM_CMPR1_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_CMPR1_B_UPMETHOD 0x0000000F +#define MCPWM_CMPR1_B_UPMETHOD_M ((MCPWM_CMPR1_B_UPMETHOD_V) << (MCPWM_CMPR1_B_UPMETHOD_S)) +#define MCPWM_CMPR1_B_UPMETHOD_V 0xF +#define MCPWM_CMPR1_B_UPMETHOD_S 4 +/* MCPWM_CMPR1_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_CMPR1_A_UPMETHOD 0x0000000F +#define MCPWM_CMPR1_A_UPMETHOD_M ((MCPWM_CMPR1_A_UPMETHOD_V) << (MCPWM_CMPR1_A_UPMETHOD_S)) +#define MCPWM_CMPR1_A_UPMETHOD_V 0xF +#define MCPWM_CMPR1_A_UPMETHOD_S 0 + +#define MCPWM_CMPR1_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x0078) +/* MCPWM_CMPR1_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_A 0x0000FFFF +#define MCPWM_CMPR1_A_M ((MCPWM_CMPR1_A_V) << (MCPWM_CMPR1_A_S)) +#define MCPWM_CMPR1_A_V 0xFFFF +#define MCPWM_CMPR1_A_S 0 + +#define MCPWM_CMPR1_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x007c) +/* MCPWM_CMPR1_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_B 0x0000FFFF +#define MCPWM_CMPR1_B_M ((MCPWM_CMPR1_B_V) << (MCPWM_CMPR1_B_S)) +#define MCPWM_CMPR1_B_V 0xFFFF +#define MCPWM_CMPR1_B_S 0 + +#define MCPWM_GEN1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x0080) +/* MCPWM_GEN1_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ +#define MCPWM_GEN1_T1_SEL 0x00000007 +#define MCPWM_GEN1_T1_SEL_M ((MCPWM_GEN1_T1_SEL_V) << (MCPWM_GEN1_T1_SEL_S)) +#define MCPWM_GEN1_T1_SEL_V 0x7 +#define MCPWM_GEN1_T1_SEL_S 7 +/* MCPWM_GEN1_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ +#define MCPWM_GEN1_T0_SEL 0x00000007 +#define MCPWM_GEN1_T0_SEL_M ((MCPWM_GEN1_T0_SEL_V) << (MCPWM_GEN1_T0_SEL_S)) +#define MCPWM_GEN1_T0_SEL_V 0x7 +#define MCPWM_GEN1_T0_SEL_S 4 +/* MCPWM_GEN1_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ +#define MCPWM_GEN1_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN1_CFG_UPMETHOD_M ((MCPWM_GEN1_CFG_UPMETHOD_V) << (MCPWM_GEN1_CFG_UPMETHOD_S)) +#define MCPWM_GEN1_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN1_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN1_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x0084) +/* MCPWM_GEN1_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_NCIFORCE_MODE_M ((MCPWM_GEN1_B_NCIFORCE_MODE_V) << (MCPWM_GEN1_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN1_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: non-continuous immediate sw force a toggle will trigger a force event*/ +#define MCPWM_GEN1_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN1_B_NCIFORCE_V 0x1 +#define MCPWM_GEN1_B_NCIFORCE_S 13 +/* MCPWM_GEN1_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_NCIFORCE_MODE_M ((MCPWM_GEN1_A_NCIFORCE_MODE_V) << (MCPWM_GEN1_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN1_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN1_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: non-continuous immediate sw force a toggle will trigger a force event*/ +#define MCPWM_GEN1_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN1_A_NCIFORCE_V 0x1 +#define MCPWM_GEN1_A_NCIFORCE_S 10 +/* MCPWM_GEN1_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_M ((MCPWM_GEN1_B_CNTUFORCE_MODE_V) << (MCPWM_GEN1_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN1_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN1_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_M ((MCPWM_GEN1_A_CNTUFORCE_MODE_V) << (MCPWM_GEN1_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN1_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN1_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN1_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: + sync bit5: freeze*/ +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN1_CNTUFORCE_UPMETHOD_V) << (MCPWM_GEN1_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN1_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN1_A_REG(i) (REG_MCPWM_BASE(i) + 0x0088) +/* MCPWM_GEN1_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN1_A_DT1 0x00000003 +#define MCPWM_GEN1_A_DT1_M ((MCPWM_GEN1_A_DT1_V) << (MCPWM_GEN1_A_DT1_S)) +#define MCPWM_GEN1_A_DT1_V 0x3 +#define MCPWM_GEN1_A_DT1_S 22 +/* MCPWM_GEN1_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_DT0 0x00000003 +#define MCPWM_GEN1_A_DT0_M ((MCPWM_GEN1_A_DT0_V) << (MCPWM_GEN1_A_DT0_S)) +#define MCPWM_GEN1_A_DT0_V 0x3 +#define MCPWM_GEN1_A_DT0_S 20 +/* MCPWM_GEN1_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_DTEB 0x00000003 +#define MCPWM_GEN1_A_DTEB_M ((MCPWM_GEN1_A_DTEB_V) << (MCPWM_GEN1_A_DTEB_S)) +#define MCPWM_GEN1_A_DTEB_V 0x3 +#define MCPWM_GEN1_A_DTEB_S 18 +/* MCPWM_GEN1_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_DTEA 0x00000003 +#define MCPWM_GEN1_A_DTEA_M ((MCPWM_GEN1_A_DTEA_V) << (MCPWM_GEN1_A_DTEA_S)) +#define MCPWM_GEN1_A_DTEA_V 0x3 +#define MCPWM_GEN1_A_DTEA_S 16 +/* MCPWM_GEN1_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_DTEP 0x00000003 +#define MCPWM_GEN1_A_DTEP_M ((MCPWM_GEN1_A_DTEP_V) << (MCPWM_GEN1_A_DTEP_S)) +#define MCPWM_GEN1_A_DTEP_V 0x3 +#define MCPWM_GEN1_A_DTEP_S 14 +/* MCPWM_GEN1_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_DTEZ 0x00000003 +#define MCPWM_GEN1_A_DTEZ_M ((MCPWM_GEN1_A_DTEZ_V) << (MCPWM_GEN1_A_DTEZ_S)) +#define MCPWM_GEN1_A_DTEZ_V 0x3 +#define MCPWM_GEN1_A_DTEZ_S 12 +/* MCPWM_GEN1_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_UT1 0x00000003 +#define MCPWM_GEN1_A_UT1_M ((MCPWM_GEN1_A_UT1_V) << (MCPWM_GEN1_A_UT1_S)) +#define MCPWM_GEN1_A_UT1_V 0x3 +#define MCPWM_GEN1_A_UT1_S 10 +/* MCPWM_GEN1_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_UT0 0x00000003 +#define MCPWM_GEN1_A_UT0_M ((MCPWM_GEN1_A_UT0_V) << (MCPWM_GEN1_A_UT0_S)) +#define MCPWM_GEN1_A_UT0_V 0x3 +#define MCPWM_GEN1_A_UT0_S 8 +/* MCPWM_GEN1_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_UTEB 0x00000003 +#define MCPWM_GEN1_A_UTEB_M ((MCPWM_GEN1_A_UTEB_V) << (MCPWM_GEN1_A_UTEB_S)) +#define MCPWM_GEN1_A_UTEB_V 0x3 +#define MCPWM_GEN1_A_UTEB_S 6 +/* MCPWM_GEN1_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_UTEA 0x00000003 +#define MCPWM_GEN1_A_UTEA_M ((MCPWM_GEN1_A_UTEA_V) << (MCPWM_GEN1_A_UTEA_S)) +#define MCPWM_GEN1_A_UTEA_V 0x3 +#define MCPWM_GEN1_A_UTEA_S 4 +/* MCPWM_GEN1_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_UTEP 0x00000003 +#define MCPWM_GEN1_A_UTEP_M ((MCPWM_GEN1_A_UTEP_V) << (MCPWM_GEN1_A_UTEP_S)) +#define MCPWM_GEN1_A_UTEP_V 0x3 +#define MCPWM_GEN1_A_UTEP_S 2 +/* MCPWM_GEN1_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_A_UTEZ 0x00000003 +#define MCPWM_GEN1_A_UTEZ_M ((MCPWM_GEN1_A_UTEZ_V) << (MCPWM_GEN1_A_UTEZ_S)) +#define MCPWM_GEN1_A_UTEZ_V 0x3 +#define MCPWM_GEN1_A_UTEZ_S 0 + +#define MCPWM_GEN1_B_REG(i) (REG_MCPWM_BASE(i) + 0x008c) +/* MCPWM_GEN1_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_DT1 0x00000003 +#define MCPWM_GEN1_B_DT1_M ((MCPWM_GEN1_B_DT1_V) << (MCPWM_GEN1_B_DT1_S)) +#define MCPWM_GEN1_B_DT1_V 0x3 +#define MCPWM_GEN1_B_DT1_S 22 +/* MCPWM_GEN1_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_DT0 0x00000003 +#define MCPWM_GEN1_B_DT0_M ((MCPWM_GEN1_B_DT0_V) << (MCPWM_GEN1_B_DT0_S)) +#define MCPWM_GEN1_B_DT0_V 0x3 +#define MCPWM_GEN1_B_DT0_S 20 +/* MCPWM_GEN1_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_DTEB 0x00000003 +#define MCPWM_GEN1_B_DTEB_M ((MCPWM_GEN1_B_DTEB_V) << (MCPWM_GEN1_B_DTEB_S)) +#define MCPWM_GEN1_B_DTEB_V 0x3 +#define MCPWM_GEN1_B_DTEB_S 18 +/* MCPWM_GEN1_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_DTEA 0x00000003 +#define MCPWM_GEN1_B_DTEA_M ((MCPWM_GEN1_B_DTEA_V) << (MCPWM_GEN1_B_DTEA_S)) +#define MCPWM_GEN1_B_DTEA_V 0x3 +#define MCPWM_GEN1_B_DTEA_S 16 +/* MCPWM_GEN1_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_DTEP 0x00000003 +#define MCPWM_GEN1_B_DTEP_M ((MCPWM_GEN1_B_DTEP_V) << (MCPWM_GEN1_B_DTEP_S)) +#define MCPWM_GEN1_B_DTEP_V 0x3 +#define MCPWM_GEN1_B_DTEP_S 14 +/* MCPWM_GEN1_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_DTEZ 0x00000003 +#define MCPWM_GEN1_B_DTEZ_M ((MCPWM_GEN1_B_DTEZ_V) << (MCPWM_GEN1_B_DTEZ_S)) +#define MCPWM_GEN1_B_DTEZ_V 0x3 +#define MCPWM_GEN1_B_DTEZ_S 12 +/* MCPWM_GEN1_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_UT1 0x00000003 +#define MCPWM_GEN1_B_UT1_M ((MCPWM_GEN1_B_UT1_V) << (MCPWM_GEN1_B_UT1_S)) +#define MCPWM_GEN1_B_UT1_V 0x3 +#define MCPWM_GEN1_B_UT1_S 10 +/* MCPWM_GEN1_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_UT0 0x00000003 +#define MCPWM_GEN1_B_UT0_M ((MCPWM_GEN1_B_UT0_V) << (MCPWM_GEN1_B_UT0_S)) +#define MCPWM_GEN1_B_UT0_V 0x3 +#define MCPWM_GEN1_B_UT0_S 8 +/* MCPWM_GEN1_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_UTEB 0x00000003 +#define MCPWM_GEN1_B_UTEB_M ((MCPWM_GEN1_B_UTEB_V) << (MCPWM_GEN1_B_UTEB_S)) +#define MCPWM_GEN1_B_UTEB_V 0x3 +#define MCPWM_GEN1_B_UTEB_S 6 +/* MCPWM_GEN1_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_UTEA 0x00000003 +#define MCPWM_GEN1_B_UTEA_M ((MCPWM_GEN1_B_UTEA_V) << (MCPWM_GEN1_B_UTEA_S)) +#define MCPWM_GEN1_B_UTEA_V 0x3 +#define MCPWM_GEN1_B_UTEA_S 4 +/* MCPWM_GEN1_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_UTEP 0x00000003 +#define MCPWM_GEN1_B_UTEP_M ((MCPWM_GEN1_B_UTEP_V) << (MCPWM_GEN1_B_UTEP_S)) +#define MCPWM_GEN1_B_UTEP_V 0x3 +#define MCPWM_GEN1_B_UTEP_S 2 +/* MCPWM_GEN1_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN1_B_UTEZ 0x00000003 +#define MCPWM_GEN1_B_UTEZ_M ((MCPWM_GEN1_B_UTEZ_V) << (MCPWM_GEN1_B_UTEZ_S)) +#define MCPWM_GEN1_B_UTEZ_V 0x3 +#define MCPWM_GEN1_B_UTEZ_S 0 + +#define MCPWM_DB1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0090) +/* MCPWM_DB1_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_CLK_SEL (BIT(17)) +#define MCPWM_DB1_CLK_SEL_M (BIT(17)) +#define MCPWM_DB1_CLK_SEL_V 0x1 +#define MCPWM_DB1_CLK_SEL_S 17 +/* MCPWM_DB1_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_DB1_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB1_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DB1_B_OUTBYPASS_V 0x1 +#define MCPWM_DB1_B_OUTBYPASS_S 16 +/* MCPWM_DB1_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_DB1_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB1_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DB1_A_OUTBYPASS_V 0x1 +#define MCPWM_DB1_A_OUTBYPASS_S 15 +/* MCPWM_DB1_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB1_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DB1_FED_OUTINVERT_V 0x1 +#define MCPWM_DB1_FED_OUTINVERT_S 14 +/* MCPWM_DB1_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB1_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DB1_RED_OUTINVERT_V 0x1 +#define MCPWM_DB1_RED_OUTINVERT_S 13 +/* MCPWM_DB1_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_FED_INSEL (BIT(12)) +#define MCPWM_DB1_FED_INSEL_M (BIT(12)) +#define MCPWM_DB1_FED_INSEL_V 0x1 +#define MCPWM_DB1_FED_INSEL_S 12 +/* MCPWM_DB1_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_RED_INSEL (BIT(11)) +#define MCPWM_DB1_RED_INSEL_M (BIT(11)) +#define MCPWM_DB1_RED_INSEL_V 0x1 +#define MCPWM_DB1_RED_INSEL_S 11 +/* MCPWM_DB1_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_B_OUTSWAP (BIT(10)) +#define MCPWM_DB1_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DB1_B_OUTSWAP_V 0x1 +#define MCPWM_DB1_B_OUTSWAP_S 10 +/* MCPWM_DB1_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_A_OUTSWAP (BIT(9)) +#define MCPWM_DB1_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DB1_A_OUTSWAP_V 0x1 +#define MCPWM_DB1_A_OUTSWAP_S 9 +/* MCPWM_DB1_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB1_DEB_MODE (BIT(8)) +#define MCPWM_DB1_DEB_MODE_M (BIT(8)) +#define MCPWM_DB1_DEB_MODE_V 0x1 +#define MCPWM_DB1_DEB_MODE_S 8 +/* MCPWM_DB1_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_DB1_RED_UPMETHOD 0x0000000F +#define MCPWM_DB1_RED_UPMETHOD_M ((MCPWM_DB1_RED_UPMETHOD_V) << (MCPWM_DB1_RED_UPMETHOD_S)) +#define MCPWM_DB1_RED_UPMETHOD_V 0xF +#define MCPWM_DB1_RED_UPMETHOD_S 4 +/* MCPWM_DB1_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_DB1_FED_UPMETHOD 0x0000000F +#define MCPWM_DB1_FED_UPMETHOD_M ((MCPWM_DB1_FED_UPMETHOD_V) << (MCPWM_DB1_FED_UPMETHOD_S)) +#define MCPWM_DB1_FED_UPMETHOD_V 0xF +#define MCPWM_DB1_FED_UPMETHOD_S 0 + +#define MCPWM_DB1_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0094) +/* MCPWM_DB1_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_DB1_FED 0x0000FFFF +#define MCPWM_DB1_FED_M ((MCPWM_DB1_FED_V) << (MCPWM_DB1_FED_S)) +#define MCPWM_DB1_FED_V 0xFFFF +#define MCPWM_DB1_FED_S 0 + +#define MCPWM_DB1_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x0098) +/* MCPWM_DB1_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_DB1_RED 0x0000FFFF +#define MCPWM_DB1_RED_M ((MCPWM_DB1_RED_V) << (MCPWM_DB1_RED_S)) +#define MCPWM_DB1_RED_V 0xFFFF +#define MCPWM_DB1_RED_S 0 + +#define MCPWM_CHOPPER1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x009c) +/* MCPWM_CHOPPER1_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER1_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER1_IN_INVERT_M (BIT(13)) +#define MCPWM_CHOPPER1_IN_INVERT_V 0x1 +#define MCPWM_CHOPPER1_IN_INVERT_S 13 +/* MCPWM_CHOPPER1_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER1_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER1_OUT_INVERT_M (BIT(12)) +#define MCPWM_CHOPPER1_OUT_INVERT_V 0x1 +#define MCPWM_CHOPPER1_OUT_INVERT_S 12 +/* MCPWM_CHOPPER1_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER1_OSHTWTH 0x0000000F +#define MCPWM_CHOPPER1_OSHTWTH_M ((MCPWM_CHOPPER1_OSHTWTH_V) << (MCPWM_CHOPPER1_OSHTWTH_S)) +#define MCPWM_CHOPPER1_OSHTWTH_V 0xF +#define MCPWM_CHOPPER1_OSHTWTH_S 8 +/* MCPWM_CHOPPER1_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER1_DUTY 0x00000007 +#define MCPWM_CHOPPER1_DUTY_M ((MCPWM_CHOPPER1_DUTY_V) << (MCPWM_CHOPPER1_DUTY_S)) +#define MCPWM_CHOPPER1_DUTY_V 0x7 +#define MCPWM_CHOPPER1_DUTY_S 5 +/* MCPWM_CHOPPER1_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER1_PRESCALE 0x0000000F +#define MCPWM_CHOPPER1_PRESCALE_M ((MCPWM_CHOPPER1_PRESCALE_V) << (MCPWM_CHOPPER1_PRESCALE_S)) +#define MCPWM_CHOPPER1_PRESCALE_V 0xF +#define MCPWM_CHOPPER1_PRESCALE_S 1 +/* MCPWM_CHOPPER1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER1_EN (BIT(0)) +#define MCPWM_CHOPPER1_EN_M (BIT(0)) +#define MCPWM_CHOPPER1_EN_V 0x1 +#define MCPWM_CHOPPER1_EN_S 0 + +#define MCPWM_TZ1_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00a0) +/* MCPWM_TZ1_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_B_OST_U 0x00000003 +#define MCPWM_TZ1_B_OST_U_M ((MCPWM_TZ1_B_OST_U_V) << (MCPWM_TZ1_B_OST_U_S)) +#define MCPWM_TZ1_B_OST_U_V 0x3 +#define MCPWM_TZ1_B_OST_U_S 22 +/* MCPWM_TZ1_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_B_OST_D 0x00000003 +#define MCPWM_TZ1_B_OST_D_M ((MCPWM_TZ1_B_OST_D_V) << (MCPWM_TZ1_B_OST_D_S)) +#define MCPWM_TZ1_B_OST_D_V 0x3 +#define MCPWM_TZ1_B_OST_D_S 20 +/* MCPWM_TZ1_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_B_CBC_U 0x00000003 +#define MCPWM_TZ1_B_CBC_U_M ((MCPWM_TZ1_B_CBC_U_V) << (MCPWM_TZ1_B_CBC_U_S)) +#define MCPWM_TZ1_B_CBC_U_V 0x3 +#define MCPWM_TZ1_B_CBC_U_S 18 +/* MCPWM_TZ1_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_B_CBC_D 0x00000003 +#define MCPWM_TZ1_B_CBC_D_M ((MCPWM_TZ1_B_CBC_D_V) << (MCPWM_TZ1_B_CBC_D_S)) +#define MCPWM_TZ1_B_CBC_D_V 0x3 +#define MCPWM_TZ1_B_CBC_D_S 16 +/* MCPWM_TZ1_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_A_OST_U 0x00000003 +#define MCPWM_TZ1_A_OST_U_M ((MCPWM_TZ1_A_OST_U_V) << (MCPWM_TZ1_A_OST_U_S)) +#define MCPWM_TZ1_A_OST_U_V 0x3 +#define MCPWM_TZ1_A_OST_U_S 14 +/* MCPWM_TZ1_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_A_OST_D 0x00000003 +#define MCPWM_TZ1_A_OST_D_M ((MCPWM_TZ1_A_OST_D_V) << (MCPWM_TZ1_A_OST_D_S)) +#define MCPWM_TZ1_A_OST_D_V 0x3 +#define MCPWM_TZ1_A_OST_D_S 12 +/* MCPWM_TZ1_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_A_CBC_U 0x00000003 +#define MCPWM_TZ1_A_CBC_U_M ((MCPWM_TZ1_A_CBC_U_V) << (MCPWM_TZ1_A_CBC_U_S)) +#define MCPWM_TZ1_A_CBC_U_V 0x3 +#define MCPWM_TZ1_A_CBC_U_S 10 +/* MCPWM_TZ1_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ1_A_CBC_D 0x00000003 +#define MCPWM_TZ1_A_CBC_D_M ((MCPWM_TZ1_A_CBC_D_V) << (MCPWM_TZ1_A_CBC_D_S)) +#define MCPWM_TZ1_A_CBC_D_V 0x3 +#define MCPWM_TZ1_A_CBC_D_S 8 +/* MCPWM_TZ1_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_F0_OST (BIT(7)) +#define MCPWM_TZ1_F0_OST_M (BIT(7)) +#define MCPWM_TZ1_F0_OST_V 0x1 +#define MCPWM_TZ1_F0_OST_S 7 +/* MCPWM_TZ1_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_F1_OST (BIT(6)) +#define MCPWM_TZ1_F1_OST_M (BIT(6)) +#define MCPWM_TZ1_F1_OST_V 0x1 +#define MCPWM_TZ1_F1_OST_S 6 +/* MCPWM_TZ1_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_F2_OST (BIT(5)) +#define MCPWM_TZ1_F2_OST_M (BIT(5)) +#define MCPWM_TZ1_F2_OST_V 0x1 +#define MCPWM_TZ1_F2_OST_S 5 +/* MCPWM_TZ1_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_SW_OST (BIT(4)) +#define MCPWM_TZ1_SW_OST_M (BIT(4)) +#define MCPWM_TZ1_SW_OST_V 0x1 +#define MCPWM_TZ1_SW_OST_S 4 +/* MCPWM_TZ1_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_F0_CBC (BIT(3)) +#define MCPWM_TZ1_F0_CBC_M (BIT(3)) +#define MCPWM_TZ1_F0_CBC_V 0x1 +#define MCPWM_TZ1_F0_CBC_S 3 +/* MCPWM_TZ1_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_F1_CBC (BIT(2)) +#define MCPWM_TZ1_F1_CBC_M (BIT(2)) +#define MCPWM_TZ1_F1_CBC_V 0x1 +#define MCPWM_TZ1_F1_CBC_S 2 +/* MCPWM_TZ1_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_F2_CBC (BIT(1)) +#define MCPWM_TZ1_F2_CBC_M (BIT(1)) +#define MCPWM_TZ1_F2_CBC_V 0x1 +#define MCPWM_TZ1_F2_CBC_S 1 +/* MCPWM_TZ1_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ1_SW_CBC (BIT(0)) +#define MCPWM_TZ1_SW_CBC_M (BIT(0)) +#define MCPWM_TZ1_SW_CBC_V 0x1 +#define MCPWM_TZ1_SW_CBC_S 0 + +#define MCPWM_TZ1_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00a4) +/* MCPWM_TZ1_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: a toggle trigger a oneshot tripping*/ +#define MCPWM_TZ1_FORCE_OST (BIT(4)) +#define MCPWM_TZ1_FORCE_OST_M (BIT(4)) +#define MCPWM_TZ1_FORCE_OST_V 0x1 +#define MCPWM_TZ1_FORCE_OST_S 4 +/* MCPWM_TZ1_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: a toggle trigger a cycle-by-cycle tripping*/ +#define MCPWM_TZ1_FORCE_CBC (BIT(3)) +#define MCPWM_TZ1_FORCE_CBC_M (BIT(3)) +#define MCPWM_TZ1_FORCE_CBC_V 0x1 +#define MCPWM_TZ1_FORCE_CBC_S 3 +/* MCPWM_TZ1_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: bit0: tez bit1: tep*/ +#define MCPWM_TZ1_CBCPULSE 0x00000003 +#define MCPWM_TZ1_CBCPULSE_M ((MCPWM_TZ1_CBCPULSE_V) << (MCPWM_TZ1_CBCPULSE_S)) +#define MCPWM_TZ1_CBCPULSE_V 0x3 +#define MCPWM_TZ1_CBCPULSE_S 1 +/* MCPWM_TZ1_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: a toggle will clear oneshot tripping*/ +#define MCPWM_TZ1_CLR_OST (BIT(0)) +#define MCPWM_TZ1_CLR_OST_M (BIT(0)) +#define MCPWM_TZ1_CLR_OST_V 0x1 +#define MCPWM_TZ1_CLR_OST_S 0 + +#define MCPWM_TZ1_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00a8) +/* MCPWM_TZ1_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_OST_ON (BIT(1)) +#define MCPWM_TZ1_OST_ON_M (BIT(1)) +#define MCPWM_TZ1_OST_ON_V 0x1 +#define MCPWM_TZ1_OST_ON_S 1 +/* MCPWM_TZ1_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_CBC_ON (BIT(0)) +#define MCPWM_TZ1_CBC_ON_M (BIT(0)) +#define MCPWM_TZ1_CBC_ON_V 0x1 +#define MCPWM_TZ1_CBC_ON_S 0 + +#define MCPWM_CMPR2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00ac) +/* MCPWM_CMPR2_B_SHDW_FULL : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_B_SHDW_FULL (BIT(9)) +#define MCPWM_CMPR2_B_SHDW_FULL_M (BIT(9)) +#define MCPWM_CMPR2_B_SHDW_FULL_V 0x1 +#define MCPWM_CMPR2_B_SHDW_FULL_S 9 +/* MCPWM_CMPR2_A_SHDW_FULL : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_A_SHDW_FULL (BIT(8)) +#define MCPWM_CMPR2_A_SHDW_FULL_M (BIT(8)) +#define MCPWM_CMPR2_A_SHDW_FULL_V 0x1 +#define MCPWM_CMPR2_A_SHDW_FULL_S 8 +/* MCPWM_CMPR2_B_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_CMPR2_B_UPMETHOD 0x0000000F +#define MCPWM_CMPR2_B_UPMETHOD_M ((MCPWM_CMPR2_B_UPMETHOD_V) << (MCPWM_CMPR2_B_UPMETHOD_S)) +#define MCPWM_CMPR2_B_UPMETHOD_V 0xF +#define MCPWM_CMPR2_B_UPMETHOD_S 4 +/* MCPWM_CMPR2_A_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ +#define MCPWM_CMPR2_A_UPMETHOD 0x0000000F +#define MCPWM_CMPR2_A_UPMETHOD_M ((MCPWM_CMPR2_A_UPMETHOD_V) << (MCPWM_CMPR2_A_UPMETHOD_S)) +#define MCPWM_CMPR2_A_UPMETHOD_V 0xF +#define MCPWM_CMPR2_A_UPMETHOD_S 0 + +#define MCPWM_CMPR2_VALUE0_REG(i) (REG_MCPWM_BASE(i) + 0x00b0) +/* MCPWM_CMPR2_A : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_A 0x0000FFFF +#define MCPWM_CMPR2_A_M ((MCPWM_CMPR2_A_V) << (MCPWM_CMPR2_A_S)) +#define MCPWM_CMPR2_A_V 0xFFFF +#define MCPWM_CMPR2_A_S 0 + +#define MCPWM_CMPR2_VALUE1_REG(i) (REG_MCPWM_BASE(i) + 0x00b4) +/* MCPWM_CMPR2_B : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_B 0x0000FFFF +#define MCPWM_CMPR2_B_M ((MCPWM_CMPR2_B_V) << (MCPWM_CMPR2_B_S)) +#define MCPWM_CMPR2_B_V 0xFFFF +#define MCPWM_CMPR2_B_S 0 + +#define MCPWM_GEN2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00b8) +/* MCPWM_GEN2_T1_SEL : R/W ;bitpos:[9:7] ;default: 3'd0 ; */ +/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ +#define MCPWM_GEN2_T1_SEL 0x00000007 +#define MCPWM_GEN2_T1_SEL_M ((MCPWM_GEN2_T1_SEL_V) << (MCPWM_GEN2_T1_SEL_S)) +#define MCPWM_GEN2_T1_SEL_V 0x7 +#define MCPWM_GEN2_T1_SEL_S 7 +/* MCPWM_GEN2_T0_SEL : R/W ;bitpos:[6:4] ;default: 3'd0 ; */ +/*description: take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ +#define MCPWM_GEN2_T0_SEL 0x00000007 +#define MCPWM_GEN2_T0_SEL_M ((MCPWM_GEN2_T0_SEL_V) << (MCPWM_GEN2_T0_SEL_S)) +#define MCPWM_GEN2_T0_SEL_V 0x7 +#define MCPWM_GEN2_T0_SEL_S 4 +/* MCPWM_GEN2_CFG_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ +#define MCPWM_GEN2_CFG_UPMETHOD 0x0000000F +#define MCPWM_GEN2_CFG_UPMETHOD_M ((MCPWM_GEN2_CFG_UPMETHOD_V) << (MCPWM_GEN2_CFG_UPMETHOD_S)) +#define MCPWM_GEN2_CFG_UPMETHOD_V 0xF +#define MCPWM_GEN2_CFG_UPMETHOD_S 0 + +#define MCPWM_GEN2_FORCE_REG(i) (REG_MCPWM_BASE(i) + 0x00bc) +/* MCPWM_GEN2_B_NCIFORCE_MODE : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_B_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_NCIFORCE_MODE_M ((MCPWM_GEN2_B_NCIFORCE_MODE_V) << (MCPWM_GEN2_B_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_B_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_NCIFORCE_MODE_S 14 +/* MCPWM_GEN2_B_NCIFORCE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: non-continuous immediate sw force a toggle will trigger a force event*/ +#define MCPWM_GEN2_B_NCIFORCE (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_M (BIT(13)) +#define MCPWM_GEN2_B_NCIFORCE_V 0x1 +#define MCPWM_GEN2_B_NCIFORCE_S 13 +/* MCPWM_GEN2_A_NCIFORCE_MODE : R/W ;bitpos:[12:11] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_A_NCIFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_NCIFORCE_MODE_M ((MCPWM_GEN2_A_NCIFORCE_MODE_V) << (MCPWM_GEN2_A_NCIFORCE_MODE_S)) +#define MCPWM_GEN2_A_NCIFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_NCIFORCE_MODE_S 11 +/* MCPWM_GEN2_A_NCIFORCE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: non-continuous immediate sw force a toggle will trigger a force event*/ +#define MCPWM_GEN2_A_NCIFORCE (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_M (BIT(10)) +#define MCPWM_GEN2_A_NCIFORCE_V 0x1 +#define MCPWM_GEN2_A_NCIFORCE_S 10 +/* MCPWM_GEN2_B_CNTUFORCE_MODE : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_B_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_M ((MCPWM_GEN2_B_CNTUFORCE_MODE_V) << (MCPWM_GEN2_B_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_B_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_B_CNTUFORCE_MODE_S 8 +/* MCPWM_GEN2_A_CNTUFORCE_MODE : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: 0: disabled 1: low 2: high 3: disabled*/ +#define MCPWM_GEN2_A_CNTUFORCE_MODE 0x00000003 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_M ((MCPWM_GEN2_A_CNTUFORCE_MODE_V) << (MCPWM_GEN2_A_CNTUFORCE_MODE_S)) +#define MCPWM_GEN2_A_CNTUFORCE_MODE_V 0x3 +#define MCPWM_GEN2_A_CNTUFORCE_MODE_S 6 +/* MCPWM_GEN2_CNTUFORCE_UPMETHOD : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: 0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: + sync bit5: freeze*/ +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD 0x0000003F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_M ((MCPWM_GEN2_CNTUFORCE_UPMETHOD_V) << (MCPWM_GEN2_CNTUFORCE_UPMETHOD_S)) +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_V 0x3F +#define MCPWM_GEN2_CNTUFORCE_UPMETHOD_S 0 + +#define MCPWM_GEN2_A_REG(i) (REG_MCPWM_BASE(i) + 0x00c0) +/* MCPWM_GEN2_A_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: 0: no change 1: low 2: high 3: toggle*/ +#define MCPWM_GEN2_A_DT1 0x00000003 +#define MCPWM_GEN2_A_DT1_M ((MCPWM_GEN2_A_DT1_V) << (MCPWM_GEN2_A_DT1_S)) +#define MCPWM_GEN2_A_DT1_V 0x3 +#define MCPWM_GEN2_A_DT1_S 22 +/* MCPWM_GEN2_A_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_DT0 0x00000003 +#define MCPWM_GEN2_A_DT0_M ((MCPWM_GEN2_A_DT0_V) << (MCPWM_GEN2_A_DT0_S)) +#define MCPWM_GEN2_A_DT0_V 0x3 +#define MCPWM_GEN2_A_DT0_S 20 +/* MCPWM_GEN2_A_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_DTEB 0x00000003 +#define MCPWM_GEN2_A_DTEB_M ((MCPWM_GEN2_A_DTEB_V) << (MCPWM_GEN2_A_DTEB_S)) +#define MCPWM_GEN2_A_DTEB_V 0x3 +#define MCPWM_GEN2_A_DTEB_S 18 +/* MCPWM_GEN2_A_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_DTEA 0x00000003 +#define MCPWM_GEN2_A_DTEA_M ((MCPWM_GEN2_A_DTEA_V) << (MCPWM_GEN2_A_DTEA_S)) +#define MCPWM_GEN2_A_DTEA_V 0x3 +#define MCPWM_GEN2_A_DTEA_S 16 +/* MCPWM_GEN2_A_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_DTEP 0x00000003 +#define MCPWM_GEN2_A_DTEP_M ((MCPWM_GEN2_A_DTEP_V) << (MCPWM_GEN2_A_DTEP_S)) +#define MCPWM_GEN2_A_DTEP_V 0x3 +#define MCPWM_GEN2_A_DTEP_S 14 +/* MCPWM_GEN2_A_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_DTEZ 0x00000003 +#define MCPWM_GEN2_A_DTEZ_M ((MCPWM_GEN2_A_DTEZ_V) << (MCPWM_GEN2_A_DTEZ_S)) +#define MCPWM_GEN2_A_DTEZ_V 0x3 +#define MCPWM_GEN2_A_DTEZ_S 12 +/* MCPWM_GEN2_A_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_UT1 0x00000003 +#define MCPWM_GEN2_A_UT1_M ((MCPWM_GEN2_A_UT1_V) << (MCPWM_GEN2_A_UT1_S)) +#define MCPWM_GEN2_A_UT1_V 0x3 +#define MCPWM_GEN2_A_UT1_S 10 +/* MCPWM_GEN2_A_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_UT0 0x00000003 +#define MCPWM_GEN2_A_UT0_M ((MCPWM_GEN2_A_UT0_V) << (MCPWM_GEN2_A_UT0_S)) +#define MCPWM_GEN2_A_UT0_V 0x3 +#define MCPWM_GEN2_A_UT0_S 8 +/* MCPWM_GEN2_A_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_UTEB 0x00000003 +#define MCPWM_GEN2_A_UTEB_M ((MCPWM_GEN2_A_UTEB_V) << (MCPWM_GEN2_A_UTEB_S)) +#define MCPWM_GEN2_A_UTEB_V 0x3 +#define MCPWM_GEN2_A_UTEB_S 6 +/* MCPWM_GEN2_A_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_UTEA 0x00000003 +#define MCPWM_GEN2_A_UTEA_M ((MCPWM_GEN2_A_UTEA_V) << (MCPWM_GEN2_A_UTEA_S)) +#define MCPWM_GEN2_A_UTEA_V 0x3 +#define MCPWM_GEN2_A_UTEA_S 4 +/* MCPWM_GEN2_A_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_UTEP 0x00000003 +#define MCPWM_GEN2_A_UTEP_M ((MCPWM_GEN2_A_UTEP_V) << (MCPWM_GEN2_A_UTEP_S)) +#define MCPWM_GEN2_A_UTEP_V 0x3 +#define MCPWM_GEN2_A_UTEP_S 2 +/* MCPWM_GEN2_A_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_A_UTEZ 0x00000003 +#define MCPWM_GEN2_A_UTEZ_M ((MCPWM_GEN2_A_UTEZ_V) << (MCPWM_GEN2_A_UTEZ_S)) +#define MCPWM_GEN2_A_UTEZ_V 0x3 +#define MCPWM_GEN2_A_UTEZ_S 0 + +#define MCPWM_GEN2_B_REG(i) (REG_MCPWM_BASE(i) + 0x00c4) +/* MCPWM_GEN2_B_DT1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_DT1 0x00000003 +#define MCPWM_GEN2_B_DT1_M ((MCPWM_GEN2_B_DT1_V) << (MCPWM_GEN2_B_DT1_S)) +#define MCPWM_GEN2_B_DT1_V 0x3 +#define MCPWM_GEN2_B_DT1_S 22 +/* MCPWM_GEN2_B_DT0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_DT0 0x00000003 +#define MCPWM_GEN2_B_DT0_M ((MCPWM_GEN2_B_DT0_V) << (MCPWM_GEN2_B_DT0_S)) +#define MCPWM_GEN2_B_DT0_V 0x3 +#define MCPWM_GEN2_B_DT0_S 20 +/* MCPWM_GEN2_B_DTEB : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_DTEB 0x00000003 +#define MCPWM_GEN2_B_DTEB_M ((MCPWM_GEN2_B_DTEB_V) << (MCPWM_GEN2_B_DTEB_S)) +#define MCPWM_GEN2_B_DTEB_V 0x3 +#define MCPWM_GEN2_B_DTEB_S 18 +/* MCPWM_GEN2_B_DTEA : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_DTEA 0x00000003 +#define MCPWM_GEN2_B_DTEA_M ((MCPWM_GEN2_B_DTEA_V) << (MCPWM_GEN2_B_DTEA_S)) +#define MCPWM_GEN2_B_DTEA_V 0x3 +#define MCPWM_GEN2_B_DTEA_S 16 +/* MCPWM_GEN2_B_DTEP : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_DTEP 0x00000003 +#define MCPWM_GEN2_B_DTEP_M ((MCPWM_GEN2_B_DTEP_V) << (MCPWM_GEN2_B_DTEP_S)) +#define MCPWM_GEN2_B_DTEP_V 0x3 +#define MCPWM_GEN2_B_DTEP_S 14 +/* MCPWM_GEN2_B_DTEZ : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_DTEZ 0x00000003 +#define MCPWM_GEN2_B_DTEZ_M ((MCPWM_GEN2_B_DTEZ_V) << (MCPWM_GEN2_B_DTEZ_S)) +#define MCPWM_GEN2_B_DTEZ_V 0x3 +#define MCPWM_GEN2_B_DTEZ_S 12 +/* MCPWM_GEN2_B_UT1 : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_UT1 0x00000003 +#define MCPWM_GEN2_B_UT1_M ((MCPWM_GEN2_B_UT1_V) << (MCPWM_GEN2_B_UT1_S)) +#define MCPWM_GEN2_B_UT1_V 0x3 +#define MCPWM_GEN2_B_UT1_S 10 +/* MCPWM_GEN2_B_UT0 : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_UT0 0x00000003 +#define MCPWM_GEN2_B_UT0_M ((MCPWM_GEN2_B_UT0_V) << (MCPWM_GEN2_B_UT0_S)) +#define MCPWM_GEN2_B_UT0_V 0x3 +#define MCPWM_GEN2_B_UT0_S 8 +/* MCPWM_GEN2_B_UTEB : R/W ;bitpos:[7:6] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_UTEB 0x00000003 +#define MCPWM_GEN2_B_UTEB_M ((MCPWM_GEN2_B_UTEB_V) << (MCPWM_GEN2_B_UTEB_S)) +#define MCPWM_GEN2_B_UTEB_V 0x3 +#define MCPWM_GEN2_B_UTEB_S 6 +/* MCPWM_GEN2_B_UTEA : R/W ;bitpos:[5:4] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_UTEA 0x00000003 +#define MCPWM_GEN2_B_UTEA_M ((MCPWM_GEN2_B_UTEA_V) << (MCPWM_GEN2_B_UTEA_S)) +#define MCPWM_GEN2_B_UTEA_V 0x3 +#define MCPWM_GEN2_B_UTEA_S 4 +/* MCPWM_GEN2_B_UTEP : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_UTEP 0x00000003 +#define MCPWM_GEN2_B_UTEP_M ((MCPWM_GEN2_B_UTEP_V) << (MCPWM_GEN2_B_UTEP_S)) +#define MCPWM_GEN2_B_UTEP_V 0x3 +#define MCPWM_GEN2_B_UTEP_S 2 +/* MCPWM_GEN2_B_UTEZ : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_GEN2_B_UTEZ 0x00000003 +#define MCPWM_GEN2_B_UTEZ_M ((MCPWM_GEN2_B_UTEZ_V) << (MCPWM_GEN2_B_UTEZ_S)) +#define MCPWM_GEN2_B_UTEZ_V 0x3 +#define MCPWM_GEN2_B_UTEZ_S 0 + +#define MCPWM_DB2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00c8) +/* MCPWM_DB2_CLK_SEL : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_CLK_SEL (BIT(17)) +#define MCPWM_DB2_CLK_SEL_M (BIT(17)) +#define MCPWM_DB2_CLK_SEL_V 0x1 +#define MCPWM_DB2_CLK_SEL_S 17 +/* MCPWM_DB2_B_OUTBYPASS : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_DB2_B_OUTBYPASS (BIT(16)) +#define MCPWM_DB2_B_OUTBYPASS_M (BIT(16)) +#define MCPWM_DB2_B_OUTBYPASS_V 0x1 +#define MCPWM_DB2_B_OUTBYPASS_S 16 +/* MCPWM_DB2_A_OUTBYPASS : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_DB2_A_OUTBYPASS (BIT(15)) +#define MCPWM_DB2_A_OUTBYPASS_M (BIT(15)) +#define MCPWM_DB2_A_OUTBYPASS_V 0x1 +#define MCPWM_DB2_A_OUTBYPASS_S 15 +/* MCPWM_DB2_FED_OUTINVERT : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_FED_OUTINVERT (BIT(14)) +#define MCPWM_DB2_FED_OUTINVERT_M (BIT(14)) +#define MCPWM_DB2_FED_OUTINVERT_V 0x1 +#define MCPWM_DB2_FED_OUTINVERT_S 14 +/* MCPWM_DB2_RED_OUTINVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_RED_OUTINVERT (BIT(13)) +#define MCPWM_DB2_RED_OUTINVERT_M (BIT(13)) +#define MCPWM_DB2_RED_OUTINVERT_V 0x1 +#define MCPWM_DB2_RED_OUTINVERT_S 13 +/* MCPWM_DB2_FED_INSEL : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_FED_INSEL (BIT(12)) +#define MCPWM_DB2_FED_INSEL_M (BIT(12)) +#define MCPWM_DB2_FED_INSEL_V 0x1 +#define MCPWM_DB2_FED_INSEL_S 12 +/* MCPWM_DB2_RED_INSEL : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_RED_INSEL (BIT(11)) +#define MCPWM_DB2_RED_INSEL_M (BIT(11)) +#define MCPWM_DB2_RED_INSEL_V 0x1 +#define MCPWM_DB2_RED_INSEL_S 11 +/* MCPWM_DB2_B_OUTSWAP : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_B_OUTSWAP (BIT(10)) +#define MCPWM_DB2_B_OUTSWAP_M (BIT(10)) +#define MCPWM_DB2_B_OUTSWAP_V 0x1 +#define MCPWM_DB2_B_OUTSWAP_S 10 +/* MCPWM_DB2_A_OUTSWAP : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_A_OUTSWAP (BIT(9)) +#define MCPWM_DB2_A_OUTSWAP_M (BIT(9)) +#define MCPWM_DB2_A_OUTSWAP_V 0x1 +#define MCPWM_DB2_A_OUTSWAP_S 9 +/* MCPWM_DB2_DEB_MODE : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_DB2_DEB_MODE (BIT(8)) +#define MCPWM_DB2_DEB_MODE_M (BIT(8)) +#define MCPWM_DB2_DEB_MODE_V 0x1 +#define MCPWM_DB2_DEB_MODE_S 8 +/* MCPWM_DB2_RED_UPMETHOD : R/W ;bitpos:[7:4] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_DB2_RED_UPMETHOD 0x0000000F +#define MCPWM_DB2_RED_UPMETHOD_M ((MCPWM_DB2_RED_UPMETHOD_V) << (MCPWM_DB2_RED_UPMETHOD_S)) +#define MCPWM_DB2_RED_UPMETHOD_V 0xF +#define MCPWM_DB2_RED_UPMETHOD_S 4 +/* MCPWM_DB2_FED_UPMETHOD : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_DB2_FED_UPMETHOD 0x0000000F +#define MCPWM_DB2_FED_UPMETHOD_M ((MCPWM_DB2_FED_UPMETHOD_V) << (MCPWM_DB2_FED_UPMETHOD_S)) +#define MCPWM_DB2_FED_UPMETHOD_V 0xF +#define MCPWM_DB2_FED_UPMETHOD_S 0 + +#define MCPWM_DB2_FED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00cc) +/* MCPWM_DB2_FED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_DB2_FED 0x0000FFFF +#define MCPWM_DB2_FED_M ((MCPWM_DB2_FED_V) << (MCPWM_DB2_FED_S)) +#define MCPWM_DB2_FED_V 0xFFFF +#define MCPWM_DB2_FED_S 0 + +#define MCPWM_DB2_RED_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d0) +/* MCPWM_DB2_RED : R/W ;bitpos:[15:0] ;default: 16'd0 ; */ +/*description: */ +#define MCPWM_DB2_RED 0x0000FFFF +#define MCPWM_DB2_RED_M ((MCPWM_DB2_RED_V) << (MCPWM_DB2_RED_S)) +#define MCPWM_DB2_RED_V 0xFFFF +#define MCPWM_DB2_RED_S 0 + +#define MCPWM_CHOPPER2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00d4) +/* MCPWM_CHOPPER2_IN_INVERT : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER2_IN_INVERT (BIT(13)) +#define MCPWM_CHOPPER2_IN_INVERT_M (BIT(13)) +#define MCPWM_CHOPPER2_IN_INVERT_V 0x1 +#define MCPWM_CHOPPER2_IN_INVERT_S 13 +/* MCPWM_CHOPPER2_OUT_INVERT : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER2_OUT_INVERT (BIT(12)) +#define MCPWM_CHOPPER2_OUT_INVERT_M (BIT(12)) +#define MCPWM_CHOPPER2_OUT_INVERT_V 0x1 +#define MCPWM_CHOPPER2_OUT_INVERT_S 12 +/* MCPWM_CHOPPER2_OSHTWTH : R/W ;bitpos:[11:8] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER2_OSHTWTH 0x0000000F +#define MCPWM_CHOPPER2_OSHTWTH_M ((MCPWM_CHOPPER2_OSHTWTH_V) << (MCPWM_CHOPPER2_OSHTWTH_S)) +#define MCPWM_CHOPPER2_OSHTWTH_V 0xF +#define MCPWM_CHOPPER2_OSHTWTH_S 8 +/* MCPWM_CHOPPER2_DUTY : R/W ;bitpos:[7:5] ;default: 3'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER2_DUTY 0x00000007 +#define MCPWM_CHOPPER2_DUTY_M ((MCPWM_CHOPPER2_DUTY_V) << (MCPWM_CHOPPER2_DUTY_S)) +#define MCPWM_CHOPPER2_DUTY_V 0x7 +#define MCPWM_CHOPPER2_DUTY_S 5 +/* MCPWM_CHOPPER2_PRESCALE : R/W ;bitpos:[4:1] ;default: 4'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER2_PRESCALE 0x0000000F +#define MCPWM_CHOPPER2_PRESCALE_M ((MCPWM_CHOPPER2_PRESCALE_V) << (MCPWM_CHOPPER2_PRESCALE_S)) +#define MCPWM_CHOPPER2_PRESCALE_V 0xF +#define MCPWM_CHOPPER2_PRESCALE_S 1 +/* MCPWM_CHOPPER2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CHOPPER2_EN (BIT(0)) +#define MCPWM_CHOPPER2_EN_M (BIT(0)) +#define MCPWM_CHOPPER2_EN_V 0x1 +#define MCPWM_CHOPPER2_EN_S 0 + +#define MCPWM_TZ2_CFG0_REG(i) (REG_MCPWM_BASE(i) + 0x00d8) +/* MCPWM_TZ2_B_OST_U : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_B_OST_U 0x00000003 +#define MCPWM_TZ2_B_OST_U_M ((MCPWM_TZ2_B_OST_U_V) << (MCPWM_TZ2_B_OST_U_S)) +#define MCPWM_TZ2_B_OST_U_V 0x3 +#define MCPWM_TZ2_B_OST_U_S 22 +/* MCPWM_TZ2_B_OST_D : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_B_OST_D 0x00000003 +#define MCPWM_TZ2_B_OST_D_M ((MCPWM_TZ2_B_OST_D_V) << (MCPWM_TZ2_B_OST_D_S)) +#define MCPWM_TZ2_B_OST_D_V 0x3 +#define MCPWM_TZ2_B_OST_D_S 20 +/* MCPWM_TZ2_B_CBC_U : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_B_CBC_U 0x00000003 +#define MCPWM_TZ2_B_CBC_U_M ((MCPWM_TZ2_B_CBC_U_V) << (MCPWM_TZ2_B_CBC_U_S)) +#define MCPWM_TZ2_B_CBC_U_V 0x3 +#define MCPWM_TZ2_B_CBC_U_S 18 +/* MCPWM_TZ2_B_CBC_D : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_B_CBC_D 0x00000003 +#define MCPWM_TZ2_B_CBC_D_M ((MCPWM_TZ2_B_CBC_D_V) << (MCPWM_TZ2_B_CBC_D_S)) +#define MCPWM_TZ2_B_CBC_D_V 0x3 +#define MCPWM_TZ2_B_CBC_D_S 16 +/* MCPWM_TZ2_A_OST_U : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_A_OST_U 0x00000003 +#define MCPWM_TZ2_A_OST_U_M ((MCPWM_TZ2_A_OST_U_V) << (MCPWM_TZ2_A_OST_U_S)) +#define MCPWM_TZ2_A_OST_U_V 0x3 +#define MCPWM_TZ2_A_OST_U_S 14 +/* MCPWM_TZ2_A_OST_D : R/W ;bitpos:[13:12] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_A_OST_D 0x00000003 +#define MCPWM_TZ2_A_OST_D_M ((MCPWM_TZ2_A_OST_D_V) << (MCPWM_TZ2_A_OST_D_S)) +#define MCPWM_TZ2_A_OST_D_V 0x3 +#define MCPWM_TZ2_A_OST_D_S 12 +/* MCPWM_TZ2_A_CBC_U : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_A_CBC_U 0x00000003 +#define MCPWM_TZ2_A_CBC_U_M ((MCPWM_TZ2_A_CBC_U_V) << (MCPWM_TZ2_A_CBC_U_S)) +#define MCPWM_TZ2_A_CBC_U_V 0x3 +#define MCPWM_TZ2_A_CBC_U_S 10 +/* MCPWM_TZ2_A_CBC_D : R/W ;bitpos:[9:8] ;default: 2'd0 ; */ +/*description: 0: do nothing 1: force lo 2: force hi 3: toggle*/ +#define MCPWM_TZ2_A_CBC_D 0x00000003 +#define MCPWM_TZ2_A_CBC_D_M ((MCPWM_TZ2_A_CBC_D_V) << (MCPWM_TZ2_A_CBC_D_S)) +#define MCPWM_TZ2_A_CBC_D_V 0x3 +#define MCPWM_TZ2_A_CBC_D_S 8 +/* MCPWM_TZ2_F0_OST : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_F0_OST (BIT(7)) +#define MCPWM_TZ2_F0_OST_M (BIT(7)) +#define MCPWM_TZ2_F0_OST_V 0x1 +#define MCPWM_TZ2_F0_OST_S 7 +/* MCPWM_TZ2_F1_OST : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_F1_OST (BIT(6)) +#define MCPWM_TZ2_F1_OST_M (BIT(6)) +#define MCPWM_TZ2_F1_OST_V 0x1 +#define MCPWM_TZ2_F1_OST_S 6 +/* MCPWM_TZ2_F2_OST : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_F2_OST (BIT(5)) +#define MCPWM_TZ2_F2_OST_M (BIT(5)) +#define MCPWM_TZ2_F2_OST_V 0x1 +#define MCPWM_TZ2_F2_OST_S 5 +/* MCPWM_TZ2_SW_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_SW_OST (BIT(4)) +#define MCPWM_TZ2_SW_OST_M (BIT(4)) +#define MCPWM_TZ2_SW_OST_V 0x1 +#define MCPWM_TZ2_SW_OST_S 4 +/* MCPWM_TZ2_F0_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_F0_CBC (BIT(3)) +#define MCPWM_TZ2_F0_CBC_M (BIT(3)) +#define MCPWM_TZ2_F0_CBC_V 0x1 +#define MCPWM_TZ2_F0_CBC_S 3 +/* MCPWM_TZ2_F1_CBC : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_F1_CBC (BIT(2)) +#define MCPWM_TZ2_F1_CBC_M (BIT(2)) +#define MCPWM_TZ2_F1_CBC_V 0x1 +#define MCPWM_TZ2_F1_CBC_S 2 +/* MCPWM_TZ2_F2_CBC : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_F2_CBC (BIT(1)) +#define MCPWM_TZ2_F2_CBC_M (BIT(1)) +#define MCPWM_TZ2_F2_CBC_V 0x1 +#define MCPWM_TZ2_F2_CBC_S 1 +/* MCPWM_TZ2_SW_CBC : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: 0: disable 1: enable*/ +#define MCPWM_TZ2_SW_CBC (BIT(0)) +#define MCPWM_TZ2_SW_CBC_M (BIT(0)) +#define MCPWM_TZ2_SW_CBC_V 0x1 +#define MCPWM_TZ2_SW_CBC_S 0 + +#define MCPWM_TZ2_CFG1_REG(i) (REG_MCPWM_BASE(i) + 0x00dc) +/* MCPWM_TZ2_FORCE_OST : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: a toggle trigger a oneshot tripping*/ +#define MCPWM_TZ2_FORCE_OST (BIT(4)) +#define MCPWM_TZ2_FORCE_OST_M (BIT(4)) +#define MCPWM_TZ2_FORCE_OST_V 0x1 +#define MCPWM_TZ2_FORCE_OST_S 4 +/* MCPWM_TZ2_FORCE_CBC : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: a toggle trigger a cycle-by-cycle tripping*/ +#define MCPWM_TZ2_FORCE_CBC (BIT(3)) +#define MCPWM_TZ2_FORCE_CBC_M (BIT(3)) +#define MCPWM_TZ2_FORCE_CBC_V 0x1 +#define MCPWM_TZ2_FORCE_CBC_S 3 +/* MCPWM_TZ2_CBCPULSE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: bit0: tez bit1: tep*/ +#define MCPWM_TZ2_CBCPULSE 0x00000003 +#define MCPWM_TZ2_CBCPULSE_M ((MCPWM_TZ2_CBCPULSE_V) << (MCPWM_TZ2_CBCPULSE_S)) +#define MCPWM_TZ2_CBCPULSE_V 0x3 +#define MCPWM_TZ2_CBCPULSE_S 1 +/* MCPWM_TZ2_CLR_OST : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: a toggle will clear oneshot tripping*/ +#define MCPWM_TZ2_CLR_OST (BIT(0)) +#define MCPWM_TZ2_CLR_OST_M (BIT(0)) +#define MCPWM_TZ2_CLR_OST_V 0x1 +#define MCPWM_TZ2_CLR_OST_S 0 + +#define MCPWM_TZ2_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x00e0) +/* MCPWM_TZ2_OST_ON : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_OST_ON (BIT(1)) +#define MCPWM_TZ2_OST_ON_M (BIT(1)) +#define MCPWM_TZ2_OST_ON_V 0x1 +#define MCPWM_TZ2_OST_ON_S 1 +/* MCPWM_TZ2_CBC_ON : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_CBC_ON (BIT(0)) +#define MCPWM_TZ2_CBC_ON_M (BIT(0)) +#define MCPWM_TZ2_CBC_ON_V 0x1 +#define MCPWM_TZ2_CBC_ON_S 0 + +#define MCPWM_FAULT_DETECT_REG(i) (REG_MCPWM_BASE(i) + 0x00e4) +/* MCPWM_EVENT_F2 : RO ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_EVENT_F2 (BIT(8)) +#define MCPWM_EVENT_F2_M (BIT(8)) +#define MCPWM_EVENT_F2_V 0x1 +#define MCPWM_EVENT_F2_S 8 +/* MCPWM_EVENT_F1 : RO ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_EVENT_F1 (BIT(7)) +#define MCPWM_EVENT_F1_M (BIT(7)) +#define MCPWM_EVENT_F1_V 0x1 +#define MCPWM_EVENT_F1_S 7 +/* MCPWM_EVENT_F0 : RO ;bitpos:[6] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_EVENT_F0 (BIT(6)) +#define MCPWM_EVENT_F0_M (BIT(6)) +#define MCPWM_EVENT_F0_V 0x1 +#define MCPWM_EVENT_F0_S 6 +/* MCPWM_F2_POLE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_F2_POLE (BIT(5)) +#define MCPWM_F2_POLE_M (BIT(5)) +#define MCPWM_F2_POLE_V 0x1 +#define MCPWM_F2_POLE_S 5 +/* MCPWM_F1_POLE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_F1_POLE (BIT(4)) +#define MCPWM_F1_POLE_M (BIT(4)) +#define MCPWM_F1_POLE_V 0x1 +#define MCPWM_F1_POLE_S 4 +/* MCPWM_F0_POLE : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_F0_POLE (BIT(3)) +#define MCPWM_F0_POLE_M (BIT(3)) +#define MCPWM_F0_POLE_V 0x1 +#define MCPWM_F0_POLE_S 3 +/* MCPWM_F2_EN : R/W ;bitpos:[2] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_F2_EN (BIT(2)) +#define MCPWM_F2_EN_M (BIT(2)) +#define MCPWM_F2_EN_V 0x1 +#define MCPWM_F2_EN_S 2 +/* MCPWM_F1_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_F1_EN (BIT(1)) +#define MCPWM_F1_EN_M (BIT(1)) +#define MCPWM_F1_EN_V 0x1 +#define MCPWM_F1_EN_S 1 +/* MCPWM_F0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_F0_EN (BIT(0)) +#define MCPWM_F0_EN_M (BIT(0)) +#define MCPWM_F0_EN_V 0x1 +#define MCPWM_F0_EN_S 0 + +#define MCPWM_CAP_TIMER_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00e8) +/* MCPWM_CAP_SYNC_SW : WO ;bitpos:[5] ;default: 1'd0 ; */ +/*description: Write 1 will force a timer sync*/ +#define MCPWM_CAP_SYNC_SW (BIT(5)) +#define MCPWM_CAP_SYNC_SW_M (BIT(5)) +#define MCPWM_CAP_SYNC_SW_V 0x1 +#define MCPWM_CAP_SYNC_SW_S 5 +/* MCPWM_CAP_SYNCI_SEL : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: */ +#define MCPWM_CAP_SYNCI_SEL 0x00000007 +#define MCPWM_CAP_SYNCI_SEL_M ((MCPWM_CAP_SYNCI_SEL_V) << (MCPWM_CAP_SYNCI_SEL_S)) +#define MCPWM_CAP_SYNCI_SEL_V 0x7 +#define MCPWM_CAP_SYNCI_SEL_S 2 +/* MCPWM_CAP_SYNCI_EN : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP_SYNCI_EN (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_M (BIT(1)) +#define MCPWM_CAP_SYNCI_EN_V 0x1 +#define MCPWM_CAP_SYNCI_EN_S 1 +/* MCPWM_CAP_TIMER_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP_TIMER_EN (BIT(0)) +#define MCPWM_CAP_TIMER_EN_M (BIT(0)) +#define MCPWM_CAP_TIMER_EN_V 0x1 +#define MCPWM_CAP_TIMER_EN_S 0 + +#define MCPWM_CAP_TIMER_PHASE_REG(i) (REG_MCPWM_BASE(i) + 0x00ec) +/* MCPWM_CAP_PHASE : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define MCPWM_CAP_PHASE 0xFFFFFFFF +#define MCPWM_CAP_PHASE_M ((MCPWM_CAP_PHASE_V) << (MCPWM_CAP_PHASE_S)) +#define MCPWM_CAP_PHASE_V 0xFFFFFFFF +#define MCPWM_CAP_PHASE_S 0 + +#define MCPWM_CAP_CH0_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f0) +/* MCPWM_CAP0_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a sw capture*/ +#define MCPWM_CAP0_SW (BIT(12)) +#define MCPWM_CAP0_SW_M (BIT(12)) +#define MCPWM_CAP0_SW_V 0x1 +#define MCPWM_CAP0_SW_S 12 +/* MCPWM_CAP0_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP0_IN_INVERT (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP0_IN_INVERT_V 0x1 +#define MCPWM_CAP0_IN_INVERT_S 11 +/* MCPWM_CAP0_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: */ +#define MCPWM_CAP0_PRESCALE 0x000000FF +#define MCPWM_CAP0_PRESCALE_M ((MCPWM_CAP0_PRESCALE_V) << (MCPWM_CAP0_PRESCALE_S)) +#define MCPWM_CAP0_PRESCALE_V 0xFF +#define MCPWM_CAP0_PRESCALE_S 3 +/* MCPWM_CAP0_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: bit0: negedge cap en bit1: posedge cap en*/ +#define MCPWM_CAP0_MODE 0x00000003 +#define MCPWM_CAP0_MODE_M ((MCPWM_CAP0_MODE_V) << (MCPWM_CAP0_MODE_S)) +#define MCPWM_CAP0_MODE_V 0x3 +#define MCPWM_CAP0_MODE_S 1 +/* MCPWM_CAP0_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP0_EN (BIT(0)) +#define MCPWM_CAP0_EN_M (BIT(0)) +#define MCPWM_CAP0_EN_V 0x1 +#define MCPWM_CAP0_EN_S 0 + +#define MCPWM_CAP_CH1_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f4) +/* MCPWM_CAP1_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a sw capture*/ +#define MCPWM_CAP1_SW (BIT(12)) +#define MCPWM_CAP1_SW_M (BIT(12)) +#define MCPWM_CAP1_SW_V 0x1 +#define MCPWM_CAP1_SW_S 12 +/* MCPWM_CAP1_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP1_IN_INVERT (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP1_IN_INVERT_V 0x1 +#define MCPWM_CAP1_IN_INVERT_S 11 +/* MCPWM_CAP1_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: */ +#define MCPWM_CAP1_PRESCALE 0x000000FF +#define MCPWM_CAP1_PRESCALE_M ((MCPWM_CAP1_PRESCALE_V) << (MCPWM_CAP1_PRESCALE_S)) +#define MCPWM_CAP1_PRESCALE_V 0xFF +#define MCPWM_CAP1_PRESCALE_S 3 +/* MCPWM_CAP1_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_CAP1_MODE 0x00000003 +#define MCPWM_CAP1_MODE_M ((MCPWM_CAP1_MODE_V) << (MCPWM_CAP1_MODE_S)) +#define MCPWM_CAP1_MODE_V 0x3 +#define MCPWM_CAP1_MODE_S 1 +/* MCPWM_CAP1_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP1_EN (BIT(0)) +#define MCPWM_CAP1_EN_M (BIT(0)) +#define MCPWM_CAP1_EN_V 0x1 +#define MCPWM_CAP1_EN_S 0 + +#define MCPWM_CAP_CH2_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x00f8) +/* MCPWM_CAP2_SW : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: Write 1 will trigger a sw capture*/ +#define MCPWM_CAP2_SW (BIT(12)) +#define MCPWM_CAP2_SW_M (BIT(12)) +#define MCPWM_CAP2_SW_V 0x1 +#define MCPWM_CAP2_SW_S 12 +/* MCPWM_CAP2_IN_INVERT : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP2_IN_INVERT (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_M (BIT(11)) +#define MCPWM_CAP2_IN_INVERT_V 0x1 +#define MCPWM_CAP2_IN_INVERT_S 11 +/* MCPWM_CAP2_PRESCALE : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: */ +#define MCPWM_CAP2_PRESCALE 0x000000FF +#define MCPWM_CAP2_PRESCALE_M ((MCPWM_CAP2_PRESCALE_V) << (MCPWM_CAP2_PRESCALE_S)) +#define MCPWM_CAP2_PRESCALE_V 0xFF +#define MCPWM_CAP2_PRESCALE_S 3 +/* MCPWM_CAP2_MODE : R/W ;bitpos:[2:1] ;default: 2'd0 ; */ +/*description: */ +#define MCPWM_CAP2_MODE 0x00000003 +#define MCPWM_CAP2_MODE_M ((MCPWM_CAP2_MODE_V) << (MCPWM_CAP2_MODE_S)) +#define MCPWM_CAP2_MODE_V 0x3 +#define MCPWM_CAP2_MODE_S 1 +/* MCPWM_CAP2_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP2_EN (BIT(0)) +#define MCPWM_CAP2_EN_M (BIT(0)) +#define MCPWM_CAP2_EN_V 0x1 +#define MCPWM_CAP2_EN_S 0 + +#define MCPWM_CAP_CH0_REG(i) (REG_MCPWM_BASE(i) + 0x00fc) +/* MCPWM_CAP0_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define MCPWM_CAP0_VALUE 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_M ((MCPWM_CAP0_VALUE_V) << (MCPWM_CAP0_VALUE_S)) +#define MCPWM_CAP0_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP0_VALUE_S 0 + +#define MCPWM_CAP_CH1_REG(i) (REG_MCPWM_BASE(i) + 0x0100) +/* MCPWM_CAP1_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define MCPWM_CAP1_VALUE 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_M ((MCPWM_CAP1_VALUE_V) << (MCPWM_CAP1_VALUE_S)) +#define MCPWM_CAP1_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP1_VALUE_S 0 + +#define MCPWM_CAP_CH2_REG(i) (REG_MCPWM_BASE(i) + 0x0104) +/* MCPWM_CAP2_VALUE : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: */ +#define MCPWM_CAP2_VALUE 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_M ((MCPWM_CAP2_VALUE_V) << (MCPWM_CAP2_VALUE_S)) +#define MCPWM_CAP2_VALUE_V 0xFFFFFFFF +#define MCPWM_CAP2_VALUE_S 0 + +#define MCPWM_CAP_STATUS_REG(i) (REG_MCPWM_BASE(i) + 0x0108) +/* MCPWM_CAP2_EDGE : RO ;bitpos:[2] ;default: 1'd0 ; */ +/*description: cap trigger's edge 0: posedge 1: negedge*/ +#define MCPWM_CAP2_EDGE (BIT(2)) +#define MCPWM_CAP2_EDGE_M (BIT(2)) +#define MCPWM_CAP2_EDGE_V 0x1 +#define MCPWM_CAP2_EDGE_S 2 +/* MCPWM_CAP1_EDGE : RO ;bitpos:[1] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP1_EDGE (BIT(1)) +#define MCPWM_CAP1_EDGE_M (BIT(1)) +#define MCPWM_CAP1_EDGE_V 0x1 +#define MCPWM_CAP1_EDGE_S 1 +/* MCPWM_CAP0_EDGE : RO ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP0_EDGE (BIT(0)) +#define MCPWM_CAP0_EDGE_M (BIT(0)) +#define MCPWM_CAP0_EDGE_V 0x1 +#define MCPWM_CAP0_EDGE_S 0 + +#define MCPWM_UPDATE_CFG_REG(i) (REG_MCPWM_BASE(i) + 0x010c) +/* MCPWM_OP2_FORCE_UP : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: a toggle will trigger a force update*/ +#define MCPWM_OP2_FORCE_UP (BIT(7)) +#define MCPWM_OP2_FORCE_UP_M (BIT(7)) +#define MCPWM_OP2_FORCE_UP_V 0x1 +#define MCPWM_OP2_FORCE_UP_S 7 +/* MCPWM_OP2_UP_EN : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: reg update local enable*/ +#define MCPWM_OP2_UP_EN (BIT(6)) +#define MCPWM_OP2_UP_EN_M (BIT(6)) +#define MCPWM_OP2_UP_EN_V 0x1 +#define MCPWM_OP2_UP_EN_S 6 +/* MCPWM_OP1_FORCE_UP : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: a toggle will trigger a force update*/ +#define MCPWM_OP1_FORCE_UP (BIT(5)) +#define MCPWM_OP1_FORCE_UP_M (BIT(5)) +#define MCPWM_OP1_FORCE_UP_V 0x1 +#define MCPWM_OP1_FORCE_UP_S 5 +/* MCPWM_OP1_UP_EN : R/W ;bitpos:[4] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_OP1_UP_EN (BIT(4)) +#define MCPWM_OP1_UP_EN_M (BIT(4)) +#define MCPWM_OP1_UP_EN_V 0x1 +#define MCPWM_OP1_UP_EN_S 4 +/* MCPWM_OP0_FORCE_UP : R/W ;bitpos:[3] ;default: 1'd0 ; */ +/*description: a toggle will trigger a force update*/ +#define MCPWM_OP0_FORCE_UP (BIT(3)) +#define MCPWM_OP0_FORCE_UP_M (BIT(3)) +#define MCPWM_OP0_FORCE_UP_V 0x1 +#define MCPWM_OP0_FORCE_UP_S 3 +/* MCPWM_OP0_UP_EN : R/W ;bitpos:[2] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_OP0_UP_EN (BIT(2)) +#define MCPWM_OP0_UP_EN_M (BIT(2)) +#define MCPWM_OP0_UP_EN_V 0x1 +#define MCPWM_OP0_UP_EN_S 2 +/* MCPWM_GLOBAL_FORCE_UP : R/W ;bitpos:[1] ;default: 1'd0 ; */ +/*description: a toggle will trigger a force update all timers and operators + will update their active regs*/ +#define MCPWM_GLOBAL_FORCE_UP (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_M (BIT(1)) +#define MCPWM_GLOBAL_FORCE_UP_V 0x1 +#define MCPWM_GLOBAL_FORCE_UP_S 1 +/* MCPWM_GLOBAL_UP_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: */ +#define MCPWM_GLOBAL_UP_EN (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_M (BIT(0)) +#define MCPWM_GLOBAL_UP_EN_V 0x1 +#define MCPWM_GLOBAL_UP_EN_S 0 + +#define MCMCPWM_INT_ENA_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0110) +/* MCPWM_CAP2_INT_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP2_INT_ENA (BIT(29)) +#define MCPWM_CAP2_INT_ENA_M (BIT(29)) +#define MCPWM_CAP2_INT_ENA_V 0x1 +#define MCPWM_CAP2_INT_ENA_S 29 +/* MCPWM_CAP1_INT_ENA : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP1_INT_ENA (BIT(28)) +#define MCPWM_CAP1_INT_ENA_M (BIT(28)) +#define MCPWM_CAP1_INT_ENA_V 0x1 +#define MCPWM_CAP1_INT_ENA_S 28 +/* MCPWM_CAP0_INT_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP0_INT_ENA (BIT(27)) +#define MCPWM_CAP0_INT_ENA_M (BIT(27)) +#define MCPWM_CAP0_INT_ENA_V 0x1 +#define MCPWM_CAP0_INT_ENA_S 27 +/* MCPWM_TZ2_OST_INT_ENA : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_OST_INT_ENA (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_ENA_V 0x1 +#define MCPWM_TZ2_OST_INT_ENA_S 26 +/* MCPWM_TZ1_OST_INT_ENA : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_OST_INT_ENA (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_ENA_V 0x1 +#define MCPWM_TZ1_OST_INT_ENA_S 25 +/* MCPWM_TZ0_OST_INT_ENA : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_OST_INT_ENA (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_ENA_V 0x1 +#define MCPWM_TZ0_OST_INT_ENA_S 24 +/* MCPWM_TZ2_CBC_INT_ENA : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_CBC_INT_ENA (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ENA_V 0x1 +#define MCPWM_TZ2_CBC_INT_ENA_S 23 +/* MCPWM_TZ1_CBC_INT_ENA : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_CBC_INT_ENA (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ENA_V 0x1 +#define MCPWM_TZ1_CBC_INT_ENA_S 22 +/* MCPWM_TZ0_CBC_INT_ENA : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_CBC_INT_ENA (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ENA_V 0x1 +#define MCPWM_TZ0_CBC_INT_ENA_S 21 +/* MCPWM_CMPR2_TEB_INT_ENA : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEB_INT_ENA (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ENA_V 0x1 +#define MCPWM_CMPR2_TEB_INT_ENA_S 20 +/* MCPWM_CMPR1_TEB_INT_ENA : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEB_INT_ENA (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ENA_V 0x1 +#define MCPWM_CMPR1_TEB_INT_ENA_S 19 +/* MCPWM_CMPR0_TEB_INT_ENA : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEB_INT_ENA (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ENA_V 0x1 +#define MCPWM_CMPR0_TEB_INT_ENA_S 18 +/* MCPWM_CMPR2_TEA_INT_ENA : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEA_INT_ENA (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ENA_V 0x1 +#define MCPWM_CMPR2_TEA_INT_ENA_S 17 +/* MCPWM_CMPR1_TEA_INT_ENA : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEA_INT_ENA (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ENA_V 0x1 +#define MCPWM_CMPR1_TEA_INT_ENA_S 16 +/* MCPWM_CMPR0_TEA_INT_ENA : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEA_INT_ENA (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ENA_V 0x1 +#define MCPWM_CMPR0_TEA_INT_ENA_S 15 +/* MCPWM_FAULT2_CLR_INT_ENA : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_CLR_INT_ENA (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ENA_S 14 +/* MCPWM_FAULT1_CLR_INT_ENA : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_CLR_INT_ENA (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ENA_S 13 +/* MCPWM_FAULT0_CLR_INT_ENA : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_CLR_INT_ENA (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ENA_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ENA_S 12 +/* MCPWM_FAULT2_INT_ENA : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_INT_ENA (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_M (BIT(11)) +#define MCPWM_FAULT2_INT_ENA_V 0x1 +#define MCPWM_FAULT2_INT_ENA_S 11 +/* MCPWM_FAULT1_INT_ENA : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_INT_ENA (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_M (BIT(10)) +#define MCPWM_FAULT1_INT_ENA_V 0x1 +#define MCPWM_FAULT1_INT_ENA_S 10 +/* MCPWM_FAULT0_INT_ENA : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_INT_ENA (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_M (BIT(9)) +#define MCPWM_FAULT0_INT_ENA_V 0x1 +#define MCPWM_FAULT0_INT_ENA_S 9 +/* MCPWM_TIMER2_TEP_INT_ENA : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEP_INT_ENA (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ENA_S 8 +/* MCPWM_TIMER1_TEP_INT_ENA : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEP_INT_ENA (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ENA_S 7 +/* MCPWM_TIMER0_TEP_INT_ENA : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEP_INT_ENA (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ENA_S 6 +/* MCPWM_TIMER2_TEZ_INT_ENA : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEZ_INT_ENA (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ENA_S 5 +/* MCPWM_TIMER1_TEZ_INT_ENA : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEZ_INT_ENA (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ENA_S 4 +/* MCPWM_TIMER0_TEZ_INT_ENA : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEZ_INT_ENA (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ENA_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ENA_S 3 +/* MCPWM_TIMER2_STOP_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_STOP_INT_ENA (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ENA_S 2 +/* MCPWM_TIMER1_STOP_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_STOP_INT_ENA (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ENA_S 1 +/* MCPWM_TIMER0_STOP_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_STOP_INT_ENA (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ENA_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ENA_S 0 + +#define MCMCPWM_INT_RAW_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0114) +/* MCPWM_CAP2_INT_RAW : RO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP2_INT_RAW (BIT(29)) +#define MCPWM_CAP2_INT_RAW_M (BIT(29)) +#define MCPWM_CAP2_INT_RAW_V 0x1 +#define MCPWM_CAP2_INT_RAW_S 29 +/* MCPWM_CAP1_INT_RAW : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP1_INT_RAW (BIT(28)) +#define MCPWM_CAP1_INT_RAW_M (BIT(28)) +#define MCPWM_CAP1_INT_RAW_V 0x1 +#define MCPWM_CAP1_INT_RAW_S 28 +/* MCPWM_CAP0_INT_RAW : RO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP0_INT_RAW (BIT(27)) +#define MCPWM_CAP0_INT_RAW_M (BIT(27)) +#define MCPWM_CAP0_INT_RAW_V 0x1 +#define MCPWM_CAP0_INT_RAW_S 27 +/* MCPWM_TZ2_OST_INT_RAW : RO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_OST_INT_RAW (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_RAW_V 0x1 +#define MCPWM_TZ2_OST_INT_RAW_S 26 +/* MCPWM_TZ1_OST_INT_RAW : RO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_OST_INT_RAW (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_RAW_V 0x1 +#define MCPWM_TZ1_OST_INT_RAW_S 25 +/* MCPWM_TZ0_OST_INT_RAW : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_OST_INT_RAW (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_RAW_V 0x1 +#define MCPWM_TZ0_OST_INT_RAW_S 24 +/* MCPWM_TZ2_CBC_INT_RAW : RO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_CBC_INT_RAW (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_RAW_V 0x1 +#define MCPWM_TZ2_CBC_INT_RAW_S 23 +/* MCPWM_TZ1_CBC_INT_RAW : RO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_CBC_INT_RAW (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_RAW_V 0x1 +#define MCPWM_TZ1_CBC_INT_RAW_S 22 +/* MCPWM_TZ0_CBC_INT_RAW : RO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_CBC_INT_RAW (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_RAW_V 0x1 +#define MCPWM_TZ0_CBC_INT_RAW_S 21 +/* MCPWM_CMPR2_TEB_INT_RAW : RO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEB_INT_RAW (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_RAW_V 0x1 +#define MCPWM_CMPR2_TEB_INT_RAW_S 20 +/* MCPWM_CMPR1_TEB_INT_RAW : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEB_INT_RAW (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_RAW_V 0x1 +#define MCPWM_CMPR1_TEB_INT_RAW_S 19 +/* MCPWM_CMPR0_TEB_INT_RAW : RO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEB_INT_RAW (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_RAW_V 0x1 +#define MCPWM_CMPR0_TEB_INT_RAW_S 18 +/* MCPWM_CMPR2_TEA_INT_RAW : RO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEA_INT_RAW (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_RAW_V 0x1 +#define MCPWM_CMPR2_TEA_INT_RAW_S 17 +/* MCPWM_CMPR1_TEA_INT_RAW : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEA_INT_RAW (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_RAW_V 0x1 +#define MCPWM_CMPR1_TEA_INT_RAW_S 16 +/* MCPWM_CMPR0_TEA_INT_RAW : RO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEA_INT_RAW (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_RAW_V 0x1 +#define MCPWM_CMPR0_TEA_INT_RAW_S 15 +/* MCPWM_FAULT2_CLR_INT_RAW : RO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_CLR_INT_RAW (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT2_CLR_INT_RAW_S 14 +/* MCPWM_FAULT1_CLR_INT_RAW : RO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_CLR_INT_RAW (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT1_CLR_INT_RAW_S 13 +/* MCPWM_FAULT0_CLR_INT_RAW : RO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_CLR_INT_RAW (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_RAW_V 0x1 +#define MCPWM_FAULT0_CLR_INT_RAW_S 12 +/* MCPWM_FAULT2_INT_RAW : RO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_INT_RAW (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_M (BIT(11)) +#define MCPWM_FAULT2_INT_RAW_V 0x1 +#define MCPWM_FAULT2_INT_RAW_S 11 +/* MCPWM_FAULT1_INT_RAW : RO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_INT_RAW (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_M (BIT(10)) +#define MCPWM_FAULT1_INT_RAW_V 0x1 +#define MCPWM_FAULT1_INT_RAW_S 10 +/* MCPWM_FAULT0_INT_RAW : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_INT_RAW (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_M (BIT(9)) +#define MCPWM_FAULT0_INT_RAW_V 0x1 +#define MCPWM_FAULT0_INT_RAW_S 9 +/* MCPWM_TIMER2_TEP_INT_RAW : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEP_INT_RAW (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEP_INT_RAW_S 8 +/* MCPWM_TIMER1_TEP_INT_RAW : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEP_INT_RAW (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEP_INT_RAW_S 7 +/* MCPWM_TIMER0_TEP_INT_RAW : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEP_INT_RAW (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEP_INT_RAW_S 6 +/* MCPWM_TIMER2_TEZ_INT_RAW : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEZ_INT_RAW (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_RAW_S 5 +/* MCPWM_TIMER1_TEZ_INT_RAW : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEZ_INT_RAW (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_RAW_S 4 +/* MCPWM_TIMER0_TEZ_INT_RAW : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEZ_INT_RAW (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_RAW_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_RAW_S 3 +/* MCPWM_TIMER2_STOP_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_STOP_INT_RAW (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER2_STOP_INT_RAW_S 2 +/* MCPWM_TIMER1_STOP_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_STOP_INT_RAW (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER1_STOP_INT_RAW_S 1 +/* MCPWM_TIMER0_STOP_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_STOP_INT_RAW (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_RAW_V 0x1 +#define MCPWM_TIMER0_STOP_INT_RAW_S 0 + +#define MCMCPWM_INT_ST_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x0118) +/* MCPWM_CAP2_INT_ST : RO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP2_INT_ST (BIT(29)) +#define MCPWM_CAP2_INT_ST_M (BIT(29)) +#define MCPWM_CAP2_INT_ST_V 0x1 +#define MCPWM_CAP2_INT_ST_S 29 +/* MCPWM_CAP1_INT_ST : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP1_INT_ST (BIT(28)) +#define MCPWM_CAP1_INT_ST_M (BIT(28)) +#define MCPWM_CAP1_INT_ST_V 0x1 +#define MCPWM_CAP1_INT_ST_S 28 +/* MCPWM_CAP0_INT_ST : RO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP0_INT_ST (BIT(27)) +#define MCPWM_CAP0_INT_ST_M (BIT(27)) +#define MCPWM_CAP0_INT_ST_V 0x1 +#define MCPWM_CAP0_INT_ST_S 27 +/* MCPWM_TZ2_OST_INT_ST : RO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_OST_INT_ST (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_ST_V 0x1 +#define MCPWM_TZ2_OST_INT_ST_S 26 +/* MCPWM_TZ1_OST_INT_ST : RO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_OST_INT_ST (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_ST_V 0x1 +#define MCPWM_TZ1_OST_INT_ST_S 25 +/* MCPWM_TZ0_OST_INT_ST : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_OST_INT_ST (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_ST_V 0x1 +#define MCPWM_TZ0_OST_INT_ST_S 24 +/* MCPWM_TZ2_CBC_INT_ST : RO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_CBC_INT_ST (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_ST_V 0x1 +#define MCPWM_TZ2_CBC_INT_ST_S 23 +/* MCPWM_TZ1_CBC_INT_ST : RO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_CBC_INT_ST (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_ST_V 0x1 +#define MCPWM_TZ1_CBC_INT_ST_S 22 +/* MCPWM_TZ0_CBC_INT_ST : RO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_CBC_INT_ST (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_ST_V 0x1 +#define MCPWM_TZ0_CBC_INT_ST_S 21 +/* MCPWM_CMPR2_TEB_INT_ST : RO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEB_INT_ST (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_ST_V 0x1 +#define MCPWM_CMPR2_TEB_INT_ST_S 20 +/* MCPWM_CMPR1_TEB_INT_ST : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEB_INT_ST (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_ST_V 0x1 +#define MCPWM_CMPR1_TEB_INT_ST_S 19 +/* MCPWM_CMPR0_TEB_INT_ST : RO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEB_INT_ST (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_ST_V 0x1 +#define MCPWM_CMPR0_TEB_INT_ST_S 18 +/* MCPWM_CMPR2_TEA_INT_ST : RO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEA_INT_ST (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_ST_V 0x1 +#define MCPWM_CMPR2_TEA_INT_ST_S 17 +/* MCPWM_CMPR1_TEA_INT_ST : RO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEA_INT_ST (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_ST_V 0x1 +#define MCPWM_CMPR1_TEA_INT_ST_S 16 +/* MCPWM_CMPR0_TEA_INT_ST : RO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEA_INT_ST (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_ST_V 0x1 +#define MCPWM_CMPR0_TEA_INT_ST_S 15 +/* MCPWM_FAULT2_CLR_INT_ST : RO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_CLR_INT_ST (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT2_CLR_INT_ST_S 14 +/* MCPWM_FAULT1_CLR_INT_ST : RO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_CLR_INT_ST (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT1_CLR_INT_ST_S 13 +/* MCPWM_FAULT0_CLR_INT_ST : RO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_CLR_INT_ST (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_ST_V 0x1 +#define MCPWM_FAULT0_CLR_INT_ST_S 12 +/* MCPWM_FAULT2_INT_ST : RO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_INT_ST (BIT(11)) +#define MCPWM_FAULT2_INT_ST_M (BIT(11)) +#define MCPWM_FAULT2_INT_ST_V 0x1 +#define MCPWM_FAULT2_INT_ST_S 11 +/* MCPWM_FAULT1_INT_ST : RO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_INT_ST (BIT(10)) +#define MCPWM_FAULT1_INT_ST_M (BIT(10)) +#define MCPWM_FAULT1_INT_ST_V 0x1 +#define MCPWM_FAULT1_INT_ST_S 10 +/* MCPWM_FAULT0_INT_ST : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_INT_ST (BIT(9)) +#define MCPWM_FAULT0_INT_ST_M (BIT(9)) +#define MCPWM_FAULT0_INT_ST_V 0x1 +#define MCPWM_FAULT0_INT_ST_S 9 +/* MCPWM_TIMER2_TEP_INT_ST : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEP_INT_ST (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEP_INT_ST_S 8 +/* MCPWM_TIMER1_TEP_INT_ST : RO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEP_INT_ST (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEP_INT_ST_S 7 +/* MCPWM_TIMER0_TEP_INT_ST : RO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEP_INT_ST (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEP_INT_ST_S 6 +/* MCPWM_TIMER2_TEZ_INT_ST : RO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEZ_INT_ST (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_ST_S 5 +/* MCPWM_TIMER1_TEZ_INT_ST : RO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEZ_INT_ST (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_ST_S 4 +/* MCPWM_TIMER0_TEZ_INT_ST : RO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEZ_INT_ST (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_ST_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_ST_S 3 +/* MCPWM_TIMER2_STOP_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_STOP_INT_ST (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER2_STOP_INT_ST_S 2 +/* MCPWM_TIMER1_STOP_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_STOP_INT_ST (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER1_STOP_INT_ST_S 1 +/* MCPWM_TIMER0_STOP_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_STOP_INT_ST (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_ST_V 0x1 +#define MCPWM_TIMER0_STOP_INT_ST_S 0 + +#define MCMCPWM_INT_CLR_MCPWM_REG(i) (REG_MCPWM_BASE(i) + 0x011c) +/* MCPWM_CAP2_INT_CLR : WO ;bitpos:[29] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP2_INT_CLR (BIT(29)) +#define MCPWM_CAP2_INT_CLR_M (BIT(29)) +#define MCPWM_CAP2_INT_CLR_V 0x1 +#define MCPWM_CAP2_INT_CLR_S 29 +/* MCPWM_CAP1_INT_CLR : WO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP1_INT_CLR (BIT(28)) +#define MCPWM_CAP1_INT_CLR_M (BIT(28)) +#define MCPWM_CAP1_INT_CLR_V 0x1 +#define MCPWM_CAP1_INT_CLR_S 28 +/* MCPWM_CAP0_INT_CLR : WO ;bitpos:[27] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CAP0_INT_CLR (BIT(27)) +#define MCPWM_CAP0_INT_CLR_M (BIT(27)) +#define MCPWM_CAP0_INT_CLR_V 0x1 +#define MCPWM_CAP0_INT_CLR_S 27 +/* MCPWM_TZ2_OST_INT_CLR : WO ;bitpos:[26] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_OST_INT_CLR (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_M (BIT(26)) +#define MCPWM_TZ2_OST_INT_CLR_V 0x1 +#define MCPWM_TZ2_OST_INT_CLR_S 26 +/* MCPWM_TZ1_OST_INT_CLR : WO ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_OST_INT_CLR (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_M (BIT(25)) +#define MCPWM_TZ1_OST_INT_CLR_V 0x1 +#define MCPWM_TZ1_OST_INT_CLR_S 25 +/* MCPWM_TZ0_OST_INT_CLR : WO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_OST_INT_CLR (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_M (BIT(24)) +#define MCPWM_TZ0_OST_INT_CLR_V 0x1 +#define MCPWM_TZ0_OST_INT_CLR_S 24 +/* MCPWM_TZ2_CBC_INT_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ2_CBC_INT_CLR (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_M (BIT(23)) +#define MCPWM_TZ2_CBC_INT_CLR_V 0x1 +#define MCPWM_TZ2_CBC_INT_CLR_S 23 +/* MCPWM_TZ1_CBC_INT_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ1_CBC_INT_CLR (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_M (BIT(22)) +#define MCPWM_TZ1_CBC_INT_CLR_V 0x1 +#define MCPWM_TZ1_CBC_INT_CLR_S 22 +/* MCPWM_TZ0_CBC_INT_CLR : WO ;bitpos:[21] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_TZ0_CBC_INT_CLR (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_M (BIT(21)) +#define MCPWM_TZ0_CBC_INT_CLR_V 0x1 +#define MCPWM_TZ0_CBC_INT_CLR_S 21 +/* MCPWM_CMPR2_TEB_INT_CLR : WO ;bitpos:[20] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEB_INT_CLR (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_M (BIT(20)) +#define MCPWM_CMPR2_TEB_INT_CLR_V 0x1 +#define MCPWM_CMPR2_TEB_INT_CLR_S 20 +/* MCPWM_CMPR1_TEB_INT_CLR : WO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEB_INT_CLR (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_M (BIT(19)) +#define MCPWM_CMPR1_TEB_INT_CLR_V 0x1 +#define MCPWM_CMPR1_TEB_INT_CLR_S 19 +/* MCPWM_CMPR0_TEB_INT_CLR : WO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEB_INT_CLR (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_M (BIT(18)) +#define MCPWM_CMPR0_TEB_INT_CLR_V 0x1 +#define MCPWM_CMPR0_TEB_INT_CLR_S 18 +/* MCPWM_CMPR2_TEA_INT_CLR : WO ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR2_TEA_INT_CLR (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_M (BIT(17)) +#define MCPWM_CMPR2_TEA_INT_CLR_V 0x1 +#define MCPWM_CMPR2_TEA_INT_CLR_S 17 +/* MCPWM_CMPR1_TEA_INT_CLR : WO ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR1_TEA_INT_CLR (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_M (BIT(16)) +#define MCPWM_CMPR1_TEA_INT_CLR_V 0x1 +#define MCPWM_CMPR1_TEA_INT_CLR_S 16 +/* MCPWM_CMPR0_TEA_INT_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CMPR0_TEA_INT_CLR (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_M (BIT(15)) +#define MCPWM_CMPR0_TEA_INT_CLR_V 0x1 +#define MCPWM_CMPR0_TEA_INT_CLR_S 15 +/* MCPWM_FAULT2_CLR_INT_CLR : WO ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_CLR_INT_CLR (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_M (BIT(14)) +#define MCPWM_FAULT2_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT2_CLR_INT_CLR_S 14 +/* MCPWM_FAULT1_CLR_INT_CLR : WO ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_CLR_INT_CLR (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_M (BIT(13)) +#define MCPWM_FAULT1_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT1_CLR_INT_CLR_S 13 +/* MCPWM_FAULT0_CLR_INT_CLR : WO ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_CLR_INT_CLR (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_M (BIT(12)) +#define MCPWM_FAULT0_CLR_INT_CLR_V 0x1 +#define MCPWM_FAULT0_CLR_INT_CLR_S 12 +/* MCPWM_FAULT2_INT_CLR : WO ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT2_INT_CLR (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_M (BIT(11)) +#define MCPWM_FAULT2_INT_CLR_V 0x1 +#define MCPWM_FAULT2_INT_CLR_S 11 +/* MCPWM_FAULT1_INT_CLR : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT1_INT_CLR (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_M (BIT(10)) +#define MCPWM_FAULT1_INT_CLR_V 0x1 +#define MCPWM_FAULT1_INT_CLR_S 10 +/* MCPWM_FAULT0_INT_CLR : WO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_FAULT0_INT_CLR (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_M (BIT(9)) +#define MCPWM_FAULT0_INT_CLR_V 0x1 +#define MCPWM_FAULT0_INT_CLR_S 9 +/* MCPWM_TIMER2_TEP_INT_CLR : WO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEP_INT_CLR (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_M (BIT(8)) +#define MCPWM_TIMER2_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEP_INT_CLR_S 8 +/* MCPWM_TIMER1_TEP_INT_CLR : WO ;bitpos:[7] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEP_INT_CLR (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_M (BIT(7)) +#define MCPWM_TIMER1_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEP_INT_CLR_S 7 +/* MCPWM_TIMER0_TEP_INT_CLR : WO ;bitpos:[6] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEP_INT_CLR (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_M (BIT(6)) +#define MCPWM_TIMER0_TEP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEP_INT_CLR_S 6 +/* MCPWM_TIMER2_TEZ_INT_CLR : WO ;bitpos:[5] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_TEZ_INT_CLR (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_M (BIT(5)) +#define MCPWM_TIMER2_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER2_TEZ_INT_CLR_S 5 +/* MCPWM_TIMER1_TEZ_INT_CLR : WO ;bitpos:[4] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_TEZ_INT_CLR (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_M (BIT(4)) +#define MCPWM_TIMER1_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER1_TEZ_INT_CLR_S 4 +/* MCPWM_TIMER0_TEZ_INT_CLR : WO ;bitpos:[3] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_TEZ_INT_CLR (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_M (BIT(3)) +#define MCPWM_TIMER0_TEZ_INT_CLR_V 0x1 +#define MCPWM_TIMER0_TEZ_INT_CLR_S 3 +/* MCPWM_TIMER2_STOP_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER2_STOP_INT_CLR (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_M (BIT(2)) +#define MCPWM_TIMER2_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER2_STOP_INT_CLR_S 2 +/* MCPWM_TIMER1_STOP_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER1_STOP_INT_CLR (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_M (BIT(1)) +#define MCPWM_TIMER1_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER1_STOP_INT_CLR_S 1 +/* MCPWM_TIMER0_STOP_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define MCPWM_TIMER0_STOP_INT_CLR (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_M (BIT(0)) +#define MCPWM_TIMER0_STOP_INT_CLR_V 0x1 +#define MCPWM_TIMER0_STOP_INT_CLR_S 0 + +#define MCPWM_CLK_REG(i) (REG_MCPWM_BASE(i) + 0x0120) +/* MCPWM_CLK_EN : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define MCPWM_CLK_EN (BIT(0)) +#define MCPWM_CLK_EN_M (BIT(0)) +#define MCPWM_CLK_EN_V 0x1 +#define MCPWM_CLK_EN_S 0 + +#define MCPWM_VERSION_REG(i) (REG_MCPWM_BASE(i) + 0x0124) +/* MCPWM_DATE : R/W ;bitpos:[27:0] ;default: 28'h1509110 ; */ +/*description: */ +#define MCPWM_DATE 0x0FFFFFFF +#define MCPWM_DATE_M ((MCPWM_DATE_V) << (MCPWM_DATE_S)) +#define MCPWM_DATE_V 0xFFFFFFF +#define MCPWM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/mcpwm_struct.h b/components/soc/soc/esp32s3/include/soc/mcpwm_struct.h new file mode 100644 index 000000000..d20604022 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/mcpwm_struct.h @@ -0,0 +1,457 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t prescale: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } clk_cfg; + struct { + union { + struct { + uint32_t prescale: 8; + uint32_t period: 16; + uint32_t upmethod: 2; /*0: immediate 1: eqz 2: sync 3: eqz | sync*/ + uint32_t reserved26: 6; + }; + uint32_t val; + } period; + union { + struct { + uint32_t start: 3; /*0: stop @ eqz 1: stop @ eqp 2: free run 3: start and stop @ next eqz 4: start and stop @ next eqp*/ + uint32_t mode: 2; /*0: freeze 1: inc 2: dec 3: up-down*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } mode; + union { + struct { + uint32_t in_en: 1; + uint32_t sync_sw: 1; /*write the negate value will trigger a sw sync*/ + uint32_t out_sel: 2; + uint32_t timer_phase: 17; + uint32_t reserved21: 11; + }; + uint32_t val; + } sync; + union { + struct { + uint32_t value: 16; + uint32_t direction: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } status; + } timer[3]; + union { + struct { + uint32_t t0_in_sel: 3; + uint32_t t1_in_sel: 3; + uint32_t t2_in_sel: 3; + uint32_t ext_in0_inv: 1; + uint32_t ext_in1_inv: 1; + uint32_t ext_in2_inv: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } timer_synci_cfg; + union { + struct { + uint32_t operator0_sel: 2; /*0: timer0 1: timer1 2: timer2*/ + uint32_t operator1_sel: 2; /*0: timer0 1: timer1 2: timer2*/ + uint32_t operator2_sel: 2; /*0: timer0 1: timer1 2: timer2*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } timer_sel; + struct { + union { + struct { + uint32_t a_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t b_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t a_shdw_full: 1; + uint32_t b_shdw_full: 1; + uint32_t reserved10: 22; + }; + uint32_t val; + } cmpr_cfg; + union { + struct { + uint32_t cmpr_val: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } cmpr_value[2]; + union { + struct { + uint32_t upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync. bit3: freeze*/ + uint32_t t0_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ + uint32_t t1_sel: 3; /*take effect immediately 0: extra0 1: extra1 2: extra2 3: sync_taken 4: none*/ + uint32_t reserved10: 22; + }; + uint32_t val; + } gen_cfg0; + union { + struct { + uint32_t cntu_force_upmethod: 6; /*0: immediate bit0: tez bit1: tep bit2: tea bit3: teb bit4: sync bit5: freeze*/ + uint32_t a_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ + uint32_t b_cntuforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ + uint32_t a_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/ + uint32_t a_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ + uint32_t b_nciforce: 1; /*non-continuous immediate sw force a toggle will trigger a force event*/ + uint32_t b_nciforce_mode: 2; /*0: disabled 1: low 2: high 3: disabled*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } gen_force; + union { + struct { + uint32_t utez: 2; + uint32_t utep: 2; + uint32_t utea: 2; + uint32_t uteb: 2; + uint32_t ut0: 2; + uint32_t ut1: 2; + uint32_t dtez: 2; + uint32_t dtep: 2; + uint32_t dtea: 2; + uint32_t dteb: 2; + uint32_t dt0: 2; + uint32_t dt1: 2; /*0: no change 1: low 2: high 3: toggle*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } generator[2]; + union { + struct { + uint32_t fed_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t red_upmethod: 4; /*0: immediate bit0: tez bit1: tep bit2: sync bit3: freeze*/ + uint32_t deb_mode: 1; /*immediate dual-edge B mode 0: fed/red take effect on different path separately 1: fed/red take effect on B path A out is in bypass or dulpB mode*/ + uint32_t a_outswap: 1; + uint32_t b_outswap: 1; + uint32_t red_insel: 1; + uint32_t fed_insel: 1; + uint32_t red_outinvert: 1; + uint32_t fed_outinvert: 1; + uint32_t a_outbypass: 1; + uint32_t b_outbypass: 1; + uint32_t clk_sel: 1; + uint32_t reserved18: 14; + }; + uint32_t val; + } db_cfg; + union { + struct { + uint32_t fed: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } db_fed_cfg; + union { + struct { + uint32_t red: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } db_red_cfg; + union { + struct { + uint32_t en: 1; + uint32_t prescale: 4; + uint32_t duty: 3; + uint32_t oshtwth: 4; + uint32_t out_invert: 1; + uint32_t in_invert: 1; + uint32_t reserved14: 18; + }; + uint32_t val; + } carrier_cfg; + union { + struct { + uint32_t sw_cbc: 1; /*0: disable 1: enable*/ + uint32_t f2_cbc: 1; /*0: disable 1: enable*/ + uint32_t f1_cbc: 1; /*0: disable 1: enable*/ + uint32_t f0_cbc: 1; /*0: disable 1: enable*/ + uint32_t sw_ost: 1; /*0: disable 1: enable*/ + uint32_t f2_ost: 1; /*0: disable 1: enable*/ + uint32_t f1_ost: 1; /*0: disable 1: enable*/ + uint32_t f0_ost: 1; /*0: disable 1: enable*/ + uint32_t a_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t a_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_cbc_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_cbc_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_ost_d: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t b_ost_u: 2; /*0: do nothing 1: force lo 2: force hi 3: toggle*/ + uint32_t reserved24: 8; + }; + uint32_t val; + } tz_cfg0; + union { + struct { + uint32_t clr_ost: 1; /*a toggle will clear oneshot tripping*/ + uint32_t cbcpulse: 2; /*bit0: tez bit1: tep*/ + uint32_t force_cbc: 1; /*a toggle trigger a cycle-by-cycle tripping*/ + uint32_t force_ost: 1; /*a toggle trigger a oneshot tripping*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } tz_cfg1; + union { + struct { + uint32_t cbc_on: 1; + uint32_t ost_on: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } tz_status; + } channel[3]; + union { + struct { + uint32_t f0_en: 1; + uint32_t f1_en: 1; + uint32_t f2_en: 1; + uint32_t f0_pole: 1; + uint32_t f1_pole: 1; + uint32_t f2_pole: 1; + uint32_t event_f0: 1; + uint32_t event_f1: 1; + uint32_t event_f2: 1; + uint32_t reserved9: 23; + }; + uint32_t val; + } fault_detect; + union { + struct { + uint32_t timer_en: 1; + uint32_t synci_en: 1; + uint32_t synci_sel: 3; + uint32_t sync_sw: 1; /*Write 1 will force a timer sync*/ + uint32_t reserved6: 26; + }; + uint32_t val; + } cap_timer_cfg; + uint32_t cap_timer_phase; /**/ + union { + struct { + uint32_t en: 1; + uint32_t mode: 2; /*bit0: negedge cap en bit1: posedge cap en*/ + uint32_t prescale: 8; + uint32_t in_invert: 1; + uint32_t sw: 1; /*Write 1 will trigger a sw capture*/ + uint32_t reserved13: 19; + }; + uint32_t val; + } cap_cfg_ch[3]; + uint32_t cap_val_ch[3]; /**/ + union { + struct { + uint32_t cap0_edge: 1; + uint32_t cap1_edge: 1; + uint32_t cap2_edge: 1; /*cap trigger's edge 0: posedge 1: negedge*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } cap_status; + union { + struct { + uint32_t global_up_en: 1; + uint32_t global_force_up: 1; /*a toggle will trigger a force update all timers and operators will update their active regs*/ + uint32_t op0_up_en: 1; + uint32_t op0_force_up: 1; /*a toggle will trigger a force update*/ + uint32_t op1_up_en: 1; + uint32_t op1_force_up: 1; /*a toggle will trigger a force update*/ + uint32_t op2_up_en: 1; /*reg update local enable*/ + uint32_t op2_force_up: 1; /*a toggle will trigger a force update*/ + uint32_t reserved8: 24; + }; + uint32_t val; + } update_cfg; + union { + struct { + uint32_t timer0_stop: 1; + uint32_t timer1_stop: 1; + uint32_t timer2_stop: 1; + uint32_t timer0_tez: 1; + uint32_t timer1_tez: 1; + uint32_t timer2_tez: 1; + uint32_t timer0_tep: 1; + uint32_t timer1_tep: 1; + uint32_t timer2_tep: 1; + uint32_t fault0: 1; + uint32_t fault1: 1; + uint32_t fault2: 1; + uint32_t fault0_clr: 1; + uint32_t fault1_clr: 1; + uint32_t fault2_clr: 1; + uint32_t cmpr0_tea: 1; + uint32_t cmpr1_tea: 1; + uint32_t cmpr2_tea: 1; + uint32_t cmpr0_teb: 1; + uint32_t cmpr1_teb: 1; + uint32_t cmpr2_teb: 1; + uint32_t tz0_cbc: 1; + uint32_t tz1_cbc: 1; + uint32_t tz2_cbc: 1; + uint32_t tz0_ost: 1; + uint32_t tz1_ost: 1; + uint32_t tz2_ost: 1; + uint32_t cap0: 1; + uint32_t cap1: 1; + uint32_t cap2: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t timer0_stop: 1; + uint32_t timer1_stop: 1; + uint32_t timer2_stop: 1; + uint32_t timer0_tez: 1; + uint32_t timer1_tez: 1; + uint32_t timer2_tez: 1; + uint32_t timer0_tep: 1; + uint32_t timer1_tep: 1; + uint32_t timer2_tep: 1; + uint32_t fault0: 1; + uint32_t fault1: 1; + uint32_t fault2: 1; + uint32_t fault0_clr: 1; + uint32_t fault1_clr: 1; + uint32_t fault2_clr: 1; + uint32_t cmpr0_tea: 1; + uint32_t cmpr1_tea: 1; + uint32_t cmpr2_tea: 1; + uint32_t cmpr0_teb: 1; + uint32_t cmpr1_teb: 1; + uint32_t cmpr2_teb: 1; + uint32_t tz0_cbc: 1; + uint32_t tz1_cbc: 1; + uint32_t tz2_cbc: 1; + uint32_t tz0_ost: 1; + uint32_t tz1_ost: 1; + uint32_t tz2_ost: 1; + uint32_t cap0: 1; + uint32_t cap1: 1; + uint32_t cap2: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t timer0_stop: 1; + uint32_t timer1_stop: 1; + uint32_t timer2_stop: 1; + uint32_t timer0_tez: 1; + uint32_t timer1_tez: 1; + uint32_t timer2_tez: 1; + uint32_t timer0_tep: 1; + uint32_t timer1_tep: 1; + uint32_t timer2_tep: 1; + uint32_t fault0: 1; + uint32_t fault1: 1; + uint32_t fault2: 1; + uint32_t fault0_clr: 1; + uint32_t fault1_clr: 1; + uint32_t fault2_clr: 1; + uint32_t cmpr0_tea: 1; + uint32_t cmpr1_tea: 1; + uint32_t cmpr2_tea: 1; + uint32_t cmpr0_teb: 1; + uint32_t cmpr1_teb: 1; + uint32_t cmpr2_teb: 1; + uint32_t tz0_cbc: 1; + uint32_t tz1_cbc: 1; + uint32_t tz2_cbc: 1; + uint32_t tz0_ost: 1; + uint32_t tz1_ost: 1; + uint32_t tz2_ost: 1; + uint32_t cap0: 1; + uint32_t cap1: 1; + uint32_t cap2: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t timer0_stop: 1; + uint32_t timer1_stop: 1; + uint32_t timer2_stop: 1; + uint32_t timer0_tez: 1; + uint32_t timer1_tez: 1; + uint32_t timer2_tez: 1; + uint32_t timer0_tep: 1; + uint32_t timer1_tep: 1; + uint32_t timer2_tep: 1; + uint32_t fault0: 1; + uint32_t fault1: 1; + uint32_t fault2: 1; + uint32_t fault0_clr: 1; + uint32_t fault1_clr: 1; + uint32_t fault2_clr: 1; + uint32_t cmpr0_tea: 1; + uint32_t cmpr1_tea: 1; + uint32_t cmpr2_tea: 1; + uint32_t cmpr0_teb: 1; + uint32_t cmpr1_teb: 1; + uint32_t cmpr2_teb: 1; + uint32_t tz0_cbc: 1; + uint32_t tz1_cbc: 1; + uint32_t tz2_cbc: 1; + uint32_t tz0_ost: 1; + uint32_t tz1_ost: 1; + uint32_t tz2_ost: 1; + uint32_t cap0: 1; + uint32_t cap1: 1; + uint32_t cap2: 1; + uint32_t reserved30: 2; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } reg_clk; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } version; +} mcpwm_dev_t; + +extern mcpwm_dev_t MCPWM0; +extern mcpwm_dev_t MCPWM1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/mpu_caps.h b/components/soc/soc/esp32s3/include/soc/mpu_caps.h new file mode 100644 index 000000000..8e12a2b13 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/mpu_caps.h @@ -0,0 +1,21 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_MPU_CONFIGURABLE_REGIONS_SUPPORTED 0 +#define SOC_MPU_MIN_REGION_SIZE 0x20000000 +#define SOC_MPU_REGIONS_MAX_NUM 8 +#define SOC_MPU_REGION_RO_SUPPORTED 0 +#define SOC_MPU_REGION_WO_SUPPORTED 0 \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/nrx_reg.h b/components/soc/soc/esp32s3/include/soc/nrx_reg.h new file mode 100644 index 000000000..d80cb2a17 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/nrx_reg.h @@ -0,0 +1,55 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc/soc.h" + +/* Some of the WiFi RX control registers. + * PU/PD fields defined here are used in sleep related functions. + */ + +#define NRXPD_CTRL (DR_REG_NRX_BASE + 0x00d4) +#define NRX_CHAN_EST_FORCE_PU (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_M (BIT(7)) +#define NRX_CHAN_EST_FORCE_PU_V 1 +#define NRX_CHAN_EST_FORCE_PU_S 7 +#define NRX_CHAN_EST_FORCE_PD (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_M (BIT(6)) +#define NRX_CHAN_EST_FORCE_PD_V 1 +#define NRX_CHAN_EST_FORCE_PD_S 6 +#define NRX_RX_ROT_FORCE_PU (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_M (BIT(5)) +#define NRX_RX_ROT_FORCE_PU_V 1 +#define NRX_RX_ROT_FORCE_PU_S 5 +#define NRX_RX_ROT_FORCE_PD (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_M (BIT(4)) +#define NRX_RX_ROT_FORCE_PD_V 1 +#define NRX_RX_ROT_FORCE_PD_S 4 +#define NRX_VIT_FORCE_PU (BIT(3)) +#define NRX_VIT_FORCE_PU_M (BIT(3)) +#define NRX_VIT_FORCE_PU_V 1 +#define NRX_VIT_FORCE_PU_S 3 +#define NRX_VIT_FORCE_PD (BIT(2)) +#define NRX_VIT_FORCE_PD_M (BIT(2)) +#define NRX_VIT_FORCE_PD_V 1 +#define NRX_VIT_FORCE_PD_S 2 +#define NRX_DEMAP_FORCE_PU (BIT(1)) +#define NRX_DEMAP_FORCE_PU_M (BIT(1)) +#define NRX_DEMAP_FORCE_PU_V 1 +#define NRX_DEMAP_FORCE_PU_S 1 +#define NRX_DEMAP_FORCE_PD (BIT(0)) +#define NRX_DEMAP_FORCE_PD_M (BIT(0)) +#define NRX_DEMAP_FORCE_PD_V 1 +#define NRX_DEMAP_FORCE_PD_S 0 diff --git a/components/soc/soc/esp32s3/include/soc/pcnt_caps.h b/components/soc/soc/esp32s3/include/soc/pcnt_caps.h new file mode 100644 index 000000000..b72d302c2 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/pcnt_caps.h @@ -0,0 +1,26 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_PCNT_PORT_NUM (1) +#define SOC_PCNT_UNIT_NUM (4) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/pcnt_reg.h b/components/soc/soc/esp32s3/include/soc/pcnt_reg.h new file mode 100644 index 000000000..0cd636f7f --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/pcnt_reg.h @@ -0,0 +1,856 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define PCNT_U0_CONF0_REG (DR_REG_PCNT_BASE + 0x0000) +/* PCNT_CH1_LCTRL_MODE_U0 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U0_M ((PCNT_CH1_LCTRL_MODE_U0_V) << (PCNT_CH1_LCTRL_MODE_U0_S)) +#define PCNT_CH1_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U0_S 30 +/* PCNT_CH1_HCTRL_MODE_U0 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U0_M ((PCNT_CH1_HCTRL_MODE_U0_V) << (PCNT_CH1_HCTRL_MODE_U0_S)) +#define PCNT_CH1_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U0_S 28 +/* PCNT_CH1_POS_MODE_U0 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_POS_MODE_U0 0x00000003 +#define PCNT_CH1_POS_MODE_U0_M ((PCNT_CH1_POS_MODE_U0_V) << (PCNT_CH1_POS_MODE_U0_S)) +#define PCNT_CH1_POS_MODE_U0_V 0x3 +#define PCNT_CH1_POS_MODE_U0_S 26 +/* PCNT_CH1_NEG_MODE_U0 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_NEG_MODE_U0 0x00000003 +#define PCNT_CH1_NEG_MODE_U0_M ((PCNT_CH1_NEG_MODE_U0_V) << (PCNT_CH1_NEG_MODE_U0_S)) +#define PCNT_CH1_NEG_MODE_U0_V 0x3 +#define PCNT_CH1_NEG_MODE_U0_S 24 +/* PCNT_CH0_LCTRL_MODE_U0 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_LCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U0_M ((PCNT_CH0_LCTRL_MODE_U0_V) << (PCNT_CH0_LCTRL_MODE_U0_S)) +#define PCNT_CH0_LCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U0_S 22 +/* PCNT_CH0_HCTRL_MODE_U0 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_HCTRL_MODE_U0 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U0_M ((PCNT_CH0_HCTRL_MODE_U0_V) << (PCNT_CH0_HCTRL_MODE_U0_S)) +#define PCNT_CH0_HCTRL_MODE_U0_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U0_S 20 +/* PCNT_CH0_POS_MODE_U0 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_POS_MODE_U0 0x00000003 +#define PCNT_CH0_POS_MODE_U0_M ((PCNT_CH0_POS_MODE_U0_V) << (PCNT_CH0_POS_MODE_U0_S)) +#define PCNT_CH0_POS_MODE_U0_V 0x3 +#define PCNT_CH0_POS_MODE_U0_S 18 +/* PCNT_CH0_NEG_MODE_U0 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_NEG_MODE_U0 0x00000003 +#define PCNT_CH0_NEG_MODE_U0_M ((PCNT_CH0_NEG_MODE_U0_V) << (PCNT_CH0_NEG_MODE_U0_S)) +#define PCNT_CH0_NEG_MODE_U0_V 0x3 +#define PCNT_CH0_NEG_MODE_U0_S 16 +/* PCNT_THR_THRES1_EN_U0 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES1_EN_U0 (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U0_V 0x1 +#define PCNT_THR_THRES1_EN_U0_S 15 +/* PCNT_THR_THRES0_EN_U0 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES0_EN_U0 (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U0_V 0x1 +#define PCNT_THR_THRES0_EN_U0_S 14 +/* PCNT_THR_L_LIM_EN_U0 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_L_LIM_EN_U0 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U0_V 0x1 +#define PCNT_THR_L_LIM_EN_U0_S 13 +/* PCNT_THR_H_LIM_EN_U0 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_H_LIM_EN_U0 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U0_V 0x1 +#define PCNT_THR_H_LIM_EN_U0_S 12 +/* PCNT_THR_ZERO_EN_U0 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_ZERO_EN_U0 (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U0_V 0x1 +#define PCNT_THR_ZERO_EN_U0_S 11 +/* PCNT_FILTER_EN_U0 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_FILTER_EN_U0 (BIT(10)) +#define PCNT_FILTER_EN_U0_M (BIT(10)) +#define PCNT_FILTER_EN_U0_V 0x1 +#define PCNT_FILTER_EN_U0_S 10 +/* PCNT_FILTER_THRES_U0 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: */ +#define PCNT_FILTER_THRES_U0 0x000003FF +#define PCNT_FILTER_THRES_U0_M ((PCNT_FILTER_THRES_U0_V) << (PCNT_FILTER_THRES_U0_S)) +#define PCNT_FILTER_THRES_U0_V 0x3FF +#define PCNT_FILTER_THRES_U0_S 0 + +#define PCNT_U0_CONF1_REG (DR_REG_PCNT_BASE + 0x0004) +/* PCNT_CNT_THRES1_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES1_U0 0x0000FFFF +#define PCNT_CNT_THRES1_U0_M ((PCNT_CNT_THRES1_U0_V) << (PCNT_CNT_THRES1_U0_S)) +#define PCNT_CNT_THRES1_U0_V 0xFFFF +#define PCNT_CNT_THRES1_U0_S 16 +/* PCNT_CNT_THRES0_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES0_U0 0x0000FFFF +#define PCNT_CNT_THRES0_U0_M ((PCNT_CNT_THRES0_U0_V) << (PCNT_CNT_THRES0_U0_S)) +#define PCNT_CNT_THRES0_U0_V 0xFFFF +#define PCNT_CNT_THRES0_U0_S 0 + +#define PCNT_U0_CONF2_REG (DR_REG_PCNT_BASE + 0x0008) +/* PCNT_CNT_L_LIM_U0 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_L_LIM_U0 0x0000FFFF +#define PCNT_CNT_L_LIM_U0_M ((PCNT_CNT_L_LIM_U0_V) << (PCNT_CNT_L_LIM_U0_S)) +#define PCNT_CNT_L_LIM_U0_V 0xFFFF +#define PCNT_CNT_L_LIM_U0_S 16 +/* PCNT_CNT_H_LIM_U0 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_H_LIM_U0 0x0000FFFF +#define PCNT_CNT_H_LIM_U0_M ((PCNT_CNT_H_LIM_U0_V) << (PCNT_CNT_H_LIM_U0_S)) +#define PCNT_CNT_H_LIM_U0_V 0xFFFF +#define PCNT_CNT_H_LIM_U0_S 0 + +#define PCNT_U1_CONF0_REG (DR_REG_PCNT_BASE + 0x000c) +/* PCNT_CH1_LCTRL_MODE_U1 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U1_M ((PCNT_CH1_LCTRL_MODE_U1_V) << (PCNT_CH1_LCTRL_MODE_U1_S)) +#define PCNT_CH1_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U1_S 30 +/* PCNT_CH1_HCTRL_MODE_U1 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U1_M ((PCNT_CH1_HCTRL_MODE_U1_V) << (PCNT_CH1_HCTRL_MODE_U1_S)) +#define PCNT_CH1_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U1_S 28 +/* PCNT_CH1_POS_MODE_U1 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_POS_MODE_U1 0x00000003 +#define PCNT_CH1_POS_MODE_U1_M ((PCNT_CH1_POS_MODE_U1_V) << (PCNT_CH1_POS_MODE_U1_S)) +#define PCNT_CH1_POS_MODE_U1_V 0x3 +#define PCNT_CH1_POS_MODE_U1_S 26 +/* PCNT_CH1_NEG_MODE_U1 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_NEG_MODE_U1 0x00000003 +#define PCNT_CH1_NEG_MODE_U1_M ((PCNT_CH1_NEG_MODE_U1_V) << (PCNT_CH1_NEG_MODE_U1_S)) +#define PCNT_CH1_NEG_MODE_U1_V 0x3 +#define PCNT_CH1_NEG_MODE_U1_S 24 +/* PCNT_CH0_LCTRL_MODE_U1 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_LCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U1_M ((PCNT_CH0_LCTRL_MODE_U1_V) << (PCNT_CH0_LCTRL_MODE_U1_S)) +#define PCNT_CH0_LCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U1_S 22 +/* PCNT_CH0_HCTRL_MODE_U1 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_HCTRL_MODE_U1 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U1_M ((PCNT_CH0_HCTRL_MODE_U1_V) << (PCNT_CH0_HCTRL_MODE_U1_S)) +#define PCNT_CH0_HCTRL_MODE_U1_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U1_S 20 +/* PCNT_CH0_POS_MODE_U1 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_POS_MODE_U1 0x00000003 +#define PCNT_CH0_POS_MODE_U1_M ((PCNT_CH0_POS_MODE_U1_V) << (PCNT_CH0_POS_MODE_U1_S)) +#define PCNT_CH0_POS_MODE_U1_V 0x3 +#define PCNT_CH0_POS_MODE_U1_S 18 +/* PCNT_CH0_NEG_MODE_U1 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_NEG_MODE_U1 0x00000003 +#define PCNT_CH0_NEG_MODE_U1_M ((PCNT_CH0_NEG_MODE_U1_V) << (PCNT_CH0_NEG_MODE_U1_S)) +#define PCNT_CH0_NEG_MODE_U1_V 0x3 +#define PCNT_CH0_NEG_MODE_U1_S 16 +/* PCNT_THR_THRES1_EN_U1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES1_EN_U1 (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U1_V 0x1 +#define PCNT_THR_THRES1_EN_U1_S 15 +/* PCNT_THR_THRES0_EN_U1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES0_EN_U1 (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U1_V 0x1 +#define PCNT_THR_THRES0_EN_U1_S 14 +/* PCNT_THR_L_LIM_EN_U1 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_L_LIM_EN_U1 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U1_V 0x1 +#define PCNT_THR_L_LIM_EN_U1_S 13 +/* PCNT_THR_H_LIM_EN_U1 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_H_LIM_EN_U1 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U1_V 0x1 +#define PCNT_THR_H_LIM_EN_U1_S 12 +/* PCNT_THR_ZERO_EN_U1 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_ZERO_EN_U1 (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U1_V 0x1 +#define PCNT_THR_ZERO_EN_U1_S 11 +/* PCNT_FILTER_EN_U1 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_FILTER_EN_U1 (BIT(10)) +#define PCNT_FILTER_EN_U1_M (BIT(10)) +#define PCNT_FILTER_EN_U1_V 0x1 +#define PCNT_FILTER_EN_U1_S 10 +/* PCNT_FILTER_THRES_U1 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: */ +#define PCNT_FILTER_THRES_U1 0x000003FF +#define PCNT_FILTER_THRES_U1_M ((PCNT_FILTER_THRES_U1_V) << (PCNT_FILTER_THRES_U1_S)) +#define PCNT_FILTER_THRES_U1_V 0x3FF +#define PCNT_FILTER_THRES_U1_S 0 + +#define PCNT_U1_CONF1_REG (DR_REG_PCNT_BASE + 0x0010) +/* PCNT_CNT_THRES1_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES1_U1 0x0000FFFF +#define PCNT_CNT_THRES1_U1_M ((PCNT_CNT_THRES1_U1_V) << (PCNT_CNT_THRES1_U1_S)) +#define PCNT_CNT_THRES1_U1_V 0xFFFF +#define PCNT_CNT_THRES1_U1_S 16 +/* PCNT_CNT_THRES0_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES0_U1 0x0000FFFF +#define PCNT_CNT_THRES0_U1_M ((PCNT_CNT_THRES0_U1_V) << (PCNT_CNT_THRES0_U1_S)) +#define PCNT_CNT_THRES0_U1_V 0xFFFF +#define PCNT_CNT_THRES0_U1_S 0 + +#define PCNT_U1_CONF2_REG (DR_REG_PCNT_BASE + 0x0014) +/* PCNT_CNT_L_LIM_U1 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_L_LIM_U1 0x0000FFFF +#define PCNT_CNT_L_LIM_U1_M ((PCNT_CNT_L_LIM_U1_V) << (PCNT_CNT_L_LIM_U1_S)) +#define PCNT_CNT_L_LIM_U1_V 0xFFFF +#define PCNT_CNT_L_LIM_U1_S 16 +/* PCNT_CNT_H_LIM_U1 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_H_LIM_U1 0x0000FFFF +#define PCNT_CNT_H_LIM_U1_M ((PCNT_CNT_H_LIM_U1_V) << (PCNT_CNT_H_LIM_U1_S)) +#define PCNT_CNT_H_LIM_U1_V 0xFFFF +#define PCNT_CNT_H_LIM_U1_S 0 + +#define PCNT_U2_CONF0_REG (DR_REG_PCNT_BASE + 0x0018) +/* PCNT_CH1_LCTRL_MODE_U2 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U2_M ((PCNT_CH1_LCTRL_MODE_U2_V) << (PCNT_CH1_LCTRL_MODE_U2_S)) +#define PCNT_CH1_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U2_S 30 +/* PCNT_CH1_HCTRL_MODE_U2 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U2_M ((PCNT_CH1_HCTRL_MODE_U2_V) << (PCNT_CH1_HCTRL_MODE_U2_S)) +#define PCNT_CH1_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U2_S 28 +/* PCNT_CH1_POS_MODE_U2 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_POS_MODE_U2 0x00000003 +#define PCNT_CH1_POS_MODE_U2_M ((PCNT_CH1_POS_MODE_U2_V) << (PCNT_CH1_POS_MODE_U2_S)) +#define PCNT_CH1_POS_MODE_U2_V 0x3 +#define PCNT_CH1_POS_MODE_U2_S 26 +/* PCNT_CH1_NEG_MODE_U2 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_NEG_MODE_U2 0x00000003 +#define PCNT_CH1_NEG_MODE_U2_M ((PCNT_CH1_NEG_MODE_U2_V) << (PCNT_CH1_NEG_MODE_U2_S)) +#define PCNT_CH1_NEG_MODE_U2_V 0x3 +#define PCNT_CH1_NEG_MODE_U2_S 24 +/* PCNT_CH0_LCTRL_MODE_U2 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_LCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U2_M ((PCNT_CH0_LCTRL_MODE_U2_V) << (PCNT_CH0_LCTRL_MODE_U2_S)) +#define PCNT_CH0_LCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U2_S 22 +/* PCNT_CH0_HCTRL_MODE_U2 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_HCTRL_MODE_U2 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U2_M ((PCNT_CH0_HCTRL_MODE_U2_V) << (PCNT_CH0_HCTRL_MODE_U2_S)) +#define PCNT_CH0_HCTRL_MODE_U2_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U2_S 20 +/* PCNT_CH0_POS_MODE_U2 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_POS_MODE_U2 0x00000003 +#define PCNT_CH0_POS_MODE_U2_M ((PCNT_CH0_POS_MODE_U2_V) << (PCNT_CH0_POS_MODE_U2_S)) +#define PCNT_CH0_POS_MODE_U2_V 0x3 +#define PCNT_CH0_POS_MODE_U2_S 18 +/* PCNT_CH0_NEG_MODE_U2 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_NEG_MODE_U2 0x00000003 +#define PCNT_CH0_NEG_MODE_U2_M ((PCNT_CH0_NEG_MODE_U2_V) << (PCNT_CH0_NEG_MODE_U2_S)) +#define PCNT_CH0_NEG_MODE_U2_V 0x3 +#define PCNT_CH0_NEG_MODE_U2_S 16 +/* PCNT_THR_THRES1_EN_U2 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES1_EN_U2 (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U2_V 0x1 +#define PCNT_THR_THRES1_EN_U2_S 15 +/* PCNT_THR_THRES0_EN_U2 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES0_EN_U2 (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U2_V 0x1 +#define PCNT_THR_THRES0_EN_U2_S 14 +/* PCNT_THR_L_LIM_EN_U2 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_L_LIM_EN_U2 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U2_V 0x1 +#define PCNT_THR_L_LIM_EN_U2_S 13 +/* PCNT_THR_H_LIM_EN_U2 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_H_LIM_EN_U2 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U2_V 0x1 +#define PCNT_THR_H_LIM_EN_U2_S 12 +/* PCNT_THR_ZERO_EN_U2 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_ZERO_EN_U2 (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U2_V 0x1 +#define PCNT_THR_ZERO_EN_U2_S 11 +/* PCNT_FILTER_EN_U2 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_FILTER_EN_U2 (BIT(10)) +#define PCNT_FILTER_EN_U2_M (BIT(10)) +#define PCNT_FILTER_EN_U2_V 0x1 +#define PCNT_FILTER_EN_U2_S 10 +/* PCNT_FILTER_THRES_U2 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: */ +#define PCNT_FILTER_THRES_U2 0x000003FF +#define PCNT_FILTER_THRES_U2_M ((PCNT_FILTER_THRES_U2_V) << (PCNT_FILTER_THRES_U2_S)) +#define PCNT_FILTER_THRES_U2_V 0x3FF +#define PCNT_FILTER_THRES_U2_S 0 + +#define PCNT_U2_CONF1_REG (DR_REG_PCNT_BASE + 0x001c) +/* PCNT_CNT_THRES1_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES1_U2 0x0000FFFF +#define PCNT_CNT_THRES1_U2_M ((PCNT_CNT_THRES1_U2_V) << (PCNT_CNT_THRES1_U2_S)) +#define PCNT_CNT_THRES1_U2_V 0xFFFF +#define PCNT_CNT_THRES1_U2_S 16 +/* PCNT_CNT_THRES0_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES0_U2 0x0000FFFF +#define PCNT_CNT_THRES0_U2_M ((PCNT_CNT_THRES0_U2_V) << (PCNT_CNT_THRES0_U2_S)) +#define PCNT_CNT_THRES0_U2_V 0xFFFF +#define PCNT_CNT_THRES0_U2_S 0 + +#define PCNT_U2_CONF2_REG (DR_REG_PCNT_BASE + 0x0020) +/* PCNT_CNT_L_LIM_U2 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_L_LIM_U2 0x0000FFFF +#define PCNT_CNT_L_LIM_U2_M ((PCNT_CNT_L_LIM_U2_V) << (PCNT_CNT_L_LIM_U2_S)) +#define PCNT_CNT_L_LIM_U2_V 0xFFFF +#define PCNT_CNT_L_LIM_U2_S 16 +/* PCNT_CNT_H_LIM_U2 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_H_LIM_U2 0x0000FFFF +#define PCNT_CNT_H_LIM_U2_M ((PCNT_CNT_H_LIM_U2_V) << (PCNT_CNT_H_LIM_U2_S)) +#define PCNT_CNT_H_LIM_U2_V 0xFFFF +#define PCNT_CNT_H_LIM_U2_S 0 + +#define PCNT_U3_CONF0_REG (DR_REG_PCNT_BASE + 0x0024) +/* PCNT_CH1_LCTRL_MODE_U3 : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_LCTRL_MODE_U3_M ((PCNT_CH1_LCTRL_MODE_U3_V) << (PCNT_CH1_LCTRL_MODE_U3_S)) +#define PCNT_CH1_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_LCTRL_MODE_U3_S 30 +/* PCNT_CH1_HCTRL_MODE_U3 : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH1_HCTRL_MODE_U3_M ((PCNT_CH1_HCTRL_MODE_U3_V) << (PCNT_CH1_HCTRL_MODE_U3_S)) +#define PCNT_CH1_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH1_HCTRL_MODE_U3_S 28 +/* PCNT_CH1_POS_MODE_U3 : R/W ;bitpos:[27:26] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_POS_MODE_U3 0x00000003 +#define PCNT_CH1_POS_MODE_U3_M ((PCNT_CH1_POS_MODE_U3_V) << (PCNT_CH1_POS_MODE_U3_S)) +#define PCNT_CH1_POS_MODE_U3_V 0x3 +#define PCNT_CH1_POS_MODE_U3_S 26 +/* PCNT_CH1_NEG_MODE_U3 : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH1_NEG_MODE_U3 0x00000003 +#define PCNT_CH1_NEG_MODE_U3_M ((PCNT_CH1_NEG_MODE_U3_V) << (PCNT_CH1_NEG_MODE_U3_S)) +#define PCNT_CH1_NEG_MODE_U3_V 0x3 +#define PCNT_CH1_NEG_MODE_U3_S 24 +/* PCNT_CH0_LCTRL_MODE_U3 : R/W ;bitpos:[23:22] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_LCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_LCTRL_MODE_U3_M ((PCNT_CH0_LCTRL_MODE_U3_V) << (PCNT_CH0_LCTRL_MODE_U3_S)) +#define PCNT_CH0_LCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_LCTRL_MODE_U3_S 22 +/* PCNT_CH0_HCTRL_MODE_U3 : R/W ;bitpos:[21:20] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_HCTRL_MODE_U3 0x00000003 +#define PCNT_CH0_HCTRL_MODE_U3_M ((PCNT_CH0_HCTRL_MODE_U3_V) << (PCNT_CH0_HCTRL_MODE_U3_S)) +#define PCNT_CH0_HCTRL_MODE_U3_V 0x3 +#define PCNT_CH0_HCTRL_MODE_U3_S 20 +/* PCNT_CH0_POS_MODE_U3 : R/W ;bitpos:[19:18] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_POS_MODE_U3 0x00000003 +#define PCNT_CH0_POS_MODE_U3_M ((PCNT_CH0_POS_MODE_U3_V) << (PCNT_CH0_POS_MODE_U3_S)) +#define PCNT_CH0_POS_MODE_U3_V 0x3 +#define PCNT_CH0_POS_MODE_U3_S 18 +/* PCNT_CH0_NEG_MODE_U3 : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: */ +#define PCNT_CH0_NEG_MODE_U3 0x00000003 +#define PCNT_CH0_NEG_MODE_U3_M ((PCNT_CH0_NEG_MODE_U3_V) << (PCNT_CH0_NEG_MODE_U3_S)) +#define PCNT_CH0_NEG_MODE_U3_V 0x3 +#define PCNT_CH0_NEG_MODE_U3_S 16 +/* PCNT_THR_THRES1_EN_U3 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES1_EN_U3 (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_M (BIT(15)) +#define PCNT_THR_THRES1_EN_U3_V 0x1 +#define PCNT_THR_THRES1_EN_U3_S 15 +/* PCNT_THR_THRES0_EN_U3 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_THR_THRES0_EN_U3 (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_M (BIT(14)) +#define PCNT_THR_THRES0_EN_U3_V 0x1 +#define PCNT_THR_THRES0_EN_U3_S 14 +/* PCNT_THR_L_LIM_EN_U3 : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_L_LIM_EN_U3 (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_M (BIT(13)) +#define PCNT_THR_L_LIM_EN_U3_V 0x1 +#define PCNT_THR_L_LIM_EN_U3_S 13 +/* PCNT_THR_H_LIM_EN_U3 : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_H_LIM_EN_U3 (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_M (BIT(12)) +#define PCNT_THR_H_LIM_EN_U3_V 0x1 +#define PCNT_THR_H_LIM_EN_U3_S 12 +/* PCNT_THR_ZERO_EN_U3 : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_THR_ZERO_EN_U3 (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_M (BIT(11)) +#define PCNT_THR_ZERO_EN_U3_V 0x1 +#define PCNT_THR_ZERO_EN_U3_S 11 +/* PCNT_FILTER_EN_U3 : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_FILTER_EN_U3 (BIT(10)) +#define PCNT_FILTER_EN_U3_M (BIT(10)) +#define PCNT_FILTER_EN_U3_V 0x1 +#define PCNT_FILTER_EN_U3_S 10 +/* PCNT_FILTER_THRES_U3 : R/W ;bitpos:[9:0] ;default: 10'h10 ; */ +/*description: */ +#define PCNT_FILTER_THRES_U3 0x000003FF +#define PCNT_FILTER_THRES_U3_M ((PCNT_FILTER_THRES_U3_V) << (PCNT_FILTER_THRES_U3_S)) +#define PCNT_FILTER_THRES_U3_V 0x3FF +#define PCNT_FILTER_THRES_U3_S 0 + +#define PCNT_U3_CONF1_REG (DR_REG_PCNT_BASE + 0x0028) +/* PCNT_CNT_THRES1_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES1_U3 0x0000FFFF +#define PCNT_CNT_THRES1_U3_M ((PCNT_CNT_THRES1_U3_V) << (PCNT_CNT_THRES1_U3_S)) +#define PCNT_CNT_THRES1_U3_V 0xFFFF +#define PCNT_CNT_THRES1_U3_S 16 +/* PCNT_CNT_THRES0_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_THRES0_U3 0x0000FFFF +#define PCNT_CNT_THRES0_U3_M ((PCNT_CNT_THRES0_U3_V) << (PCNT_CNT_THRES0_U3_S)) +#define PCNT_CNT_THRES0_U3_V 0xFFFF +#define PCNT_CNT_THRES0_U3_S 0 + +#define PCNT_U3_CONF2_REG (DR_REG_PCNT_BASE + 0x002c) +/* PCNT_CNT_L_LIM_U3 : R/W ;bitpos:[31:16] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_L_LIM_U3 0x0000FFFF +#define PCNT_CNT_L_LIM_U3_M ((PCNT_CNT_L_LIM_U3_V) << (PCNT_CNT_L_LIM_U3_S)) +#define PCNT_CNT_L_LIM_U3_V 0xFFFF +#define PCNT_CNT_L_LIM_U3_S 16 +/* PCNT_CNT_H_LIM_U3 : R/W ;bitpos:[15:0] ;default: 10'h0 ; */ +/*description: */ +#define PCNT_CNT_H_LIM_U3 0x0000FFFF +#define PCNT_CNT_H_LIM_U3_M ((PCNT_CNT_H_LIM_U3_V) << (PCNT_CNT_H_LIM_U3_S)) +#define PCNT_CNT_H_LIM_U3_V 0xFFFF +#define PCNT_CNT_H_LIM_U3_S 0 + +#define PCNT_U0_CNT_REG (DR_REG_PCNT_BASE + 0x0030) +/* PCNT_PULSE_CNT_U0 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define PCNT_PULSE_CNT_U0 0x0000FFFF +#define PCNT_PULSE_CNT_U0_M ((PCNT_PULSE_CNT_U0_V) << (PCNT_PULSE_CNT_U0_S)) +#define PCNT_PULSE_CNT_U0_V 0xFFFF +#define PCNT_PULSE_CNT_U0_S 0 + +#define PCNT_U1_CNT_REG (DR_REG_PCNT_BASE + 0x0034) +/* PCNT_PULSE_CNT_U1 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define PCNT_PULSE_CNT_U1 0x0000FFFF +#define PCNT_PULSE_CNT_U1_M ((PCNT_PULSE_CNT_U1_V) << (PCNT_PULSE_CNT_U1_S)) +#define PCNT_PULSE_CNT_U1_V 0xFFFF +#define PCNT_PULSE_CNT_U1_S 0 + +#define PCNT_U2_CNT_REG (DR_REG_PCNT_BASE + 0x0038) +/* PCNT_PULSE_CNT_U2 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define PCNT_PULSE_CNT_U2 0x0000FFFF +#define PCNT_PULSE_CNT_U2_M ((PCNT_PULSE_CNT_U2_V) << (PCNT_PULSE_CNT_U2_S)) +#define PCNT_PULSE_CNT_U2_V 0xFFFF +#define PCNT_PULSE_CNT_U2_S 0 + +#define PCNT_U3_CNT_REG (DR_REG_PCNT_BASE + 0x003c) +/* PCNT_PULSE_CNT_U3 : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define PCNT_PULSE_CNT_U3 0x0000FFFF +#define PCNT_PULSE_CNT_U3_M ((PCNT_PULSE_CNT_U3_V) << (PCNT_PULSE_CNT_U3_S)) +#define PCNT_PULSE_CNT_U3_V 0xFFFF +#define PCNT_PULSE_CNT_U3_S 0 + +#define PCNT_INT_RAW_REG (DR_REG_PCNT_BASE + 0x0040) +/* PCNT_CNT_THR_EVENT_U3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U3_INT_RAW (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_RAW_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U2_INT_RAW (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_RAW_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U1_INT_RAW (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_RAW_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U0_INT_RAW (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_RAW_S 0 + +#define PCNT_INT_ST_REG (DR_REG_PCNT_BASE + 0x0044) +/* PCNT_CNT_THR_EVENT_U3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U3_INT_ST (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ST_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U2_INT_ST (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ST_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U1_INT_ST (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ST_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U0_INT_ST (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ST_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ST_S 0 + +#define PCNT_INT_ENA_REG (DR_REG_PCNT_BASE + 0x0048) +/* PCNT_CNT_THR_EVENT_U3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U3_INT_ENA (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_ENA_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U2_INT_ENA (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_ENA_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U1_INT_ENA (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_ENA_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U0_INT_ENA (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_ENA_S 0 + +#define PCNT_INT_CLR_REG (DR_REG_PCNT_BASE + 0x004c) +/* PCNT_CNT_THR_EVENT_U3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U3_INT_CLR (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_M (BIT(3)) +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U3_INT_CLR_S 3 +/* PCNT_CNT_THR_EVENT_U2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U2_INT_CLR (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_M (BIT(2)) +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U2_INT_CLR_S 2 +/* PCNT_CNT_THR_EVENT_U1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U1_INT_CLR (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_M (BIT(1)) +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U1_INT_CLR_S 1 +/* PCNT_CNT_THR_EVENT_U0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_EVENT_U0_INT_CLR (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_M (BIT(0)) +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_V 0x1 +#define PCNT_CNT_THR_EVENT_U0_INT_CLR_S 0 + +#define PCNT_U0_STATUS_REG (DR_REG_PCNT_BASE + 0x0050) +/* PCNT_CNT_THR_ZERO_LAT_U0 : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_LAT_U0 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U0_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U0_S 6 +/* PCNT_CNT_THR_H_LIM_LAT_U0 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_H_LIM_LAT_U0 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U0_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U0_S 5 +/* PCNT_CNT_THR_L_LIM_LAT_U0 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_L_LIM_LAT_U0 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U0_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U0_S 4 +/* PCNT_CNT_THR_THRES0_LAT_U0 : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES0_LAT_U0 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U0_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U0_S 3 +/* PCNT_CNT_THR_THRES1_LAT_U0 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES1_LAT_U0 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U0_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U0_S 2 +/* PCNT_CNT_THR_ZERO_MODE_U0 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_MODE_U0 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U0_M ((PCNT_CNT_THR_ZERO_MODE_U0_V) << (PCNT_CNT_THR_ZERO_MODE_U0_S)) +#define PCNT_CNT_THR_ZERO_MODE_U0_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U0_S 0 + +#define PCNT_U1_STATUS_REG (DR_REG_PCNT_BASE + 0x0054) +/* PCNT_CNT_THR_ZERO_LAT_U1 : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_LAT_U1 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U1_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U1_S 6 +/* PCNT_CNT_THR_H_LIM_LAT_U1 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_H_LIM_LAT_U1 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U1_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U1_S 5 +/* PCNT_CNT_THR_L_LIM_LAT_U1 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_L_LIM_LAT_U1 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U1_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U1_S 4 +/* PCNT_CNT_THR_THRES0_LAT_U1 : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES0_LAT_U1 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U1_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U1_S 3 +/* PCNT_CNT_THR_THRES1_LAT_U1 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES1_LAT_U1 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U1_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U1_S 2 +/* PCNT_CNT_THR_ZERO_MODE_U1 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_MODE_U1 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U1_M ((PCNT_CNT_THR_ZERO_MODE_U1_V) << (PCNT_CNT_THR_ZERO_MODE_U1_S)) +#define PCNT_CNT_THR_ZERO_MODE_U1_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U1_S 0 + +#define PCNT_U2_STATUS_REG (DR_REG_PCNT_BASE + 0x0058) +/* PCNT_CNT_THR_ZERO_LAT_U2 : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_LAT_U2 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U2_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U2_S 6 +/* PCNT_CNT_THR_H_LIM_LAT_U2 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_H_LIM_LAT_U2 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U2_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U2_S 5 +/* PCNT_CNT_THR_L_LIM_LAT_U2 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_L_LIM_LAT_U2 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U2_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U2_S 4 +/* PCNT_CNT_THR_THRES0_LAT_U2 : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES0_LAT_U2 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U2_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U2_S 3 +/* PCNT_CNT_THR_THRES1_LAT_U2 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES1_LAT_U2 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U2_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U2_S 2 +/* PCNT_CNT_THR_ZERO_MODE_U2 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_MODE_U2 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U2_M ((PCNT_CNT_THR_ZERO_MODE_U2_V) << (PCNT_CNT_THR_ZERO_MODE_U2_S)) +#define PCNT_CNT_THR_ZERO_MODE_U2_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U2_S 0 + +#define PCNT_U3_STATUS_REG (DR_REG_PCNT_BASE + 0x005c) +/* PCNT_CNT_THR_ZERO_LAT_U3 : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_LAT_U3 (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_M (BIT(6)) +#define PCNT_CNT_THR_ZERO_LAT_U3_V 0x1 +#define PCNT_CNT_THR_ZERO_LAT_U3_S 6 +/* PCNT_CNT_THR_H_LIM_LAT_U3 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_H_LIM_LAT_U3 (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_M (BIT(5)) +#define PCNT_CNT_THR_H_LIM_LAT_U3_V 0x1 +#define PCNT_CNT_THR_H_LIM_LAT_U3_S 5 +/* PCNT_CNT_THR_L_LIM_LAT_U3 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_L_LIM_LAT_U3 (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_M (BIT(4)) +#define PCNT_CNT_THR_L_LIM_LAT_U3_V 0x1 +#define PCNT_CNT_THR_L_LIM_LAT_U3_S 4 +/* PCNT_CNT_THR_THRES0_LAT_U3 : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES0_LAT_U3 (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_M (BIT(3)) +#define PCNT_CNT_THR_THRES0_LAT_U3_V 0x1 +#define PCNT_CNT_THR_THRES0_LAT_U3_S 3 +/* PCNT_CNT_THR_THRES1_LAT_U3 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_THRES1_LAT_U3 (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_M (BIT(2)) +#define PCNT_CNT_THR_THRES1_LAT_U3_V 0x1 +#define PCNT_CNT_THR_THRES1_LAT_U3_S 2 +/* PCNT_CNT_THR_ZERO_MODE_U3 : RO ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define PCNT_CNT_THR_ZERO_MODE_U3 0x00000003 +#define PCNT_CNT_THR_ZERO_MODE_U3_M ((PCNT_CNT_THR_ZERO_MODE_U3_V) << (PCNT_CNT_THR_ZERO_MODE_U3_S)) +#define PCNT_CNT_THR_ZERO_MODE_U3_V 0x3 +#define PCNT_CNT_THR_ZERO_MODE_U3_S 0 + +#define PCNT_CTRL_REG (DR_REG_PCNT_BASE + 0x0060) +/* PCNT_CLK_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CLK_EN (BIT(16)) +#define PCNT_CLK_EN_M (BIT(16)) +#define PCNT_CLK_EN_V 0x1 +#define PCNT_CLK_EN_S 16 +/* PCNT_CNT_PAUSE_U3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_PAUSE_U3 (BIT(7)) +#define PCNT_CNT_PAUSE_U3_M (BIT(7)) +#define PCNT_CNT_PAUSE_U3_V 0x1 +#define PCNT_CNT_PAUSE_U3_S 7 +/* PCNT_PULSE_CNT_RST_U3 : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_PULSE_CNT_RST_U3 (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_M (BIT(6)) +#define PCNT_PULSE_CNT_RST_U3_V 0x1 +#define PCNT_PULSE_CNT_RST_U3_S 6 +/* PCNT_CNT_PAUSE_U2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_PAUSE_U2 (BIT(5)) +#define PCNT_CNT_PAUSE_U2_M (BIT(5)) +#define PCNT_CNT_PAUSE_U2_V 0x1 +#define PCNT_CNT_PAUSE_U2_S 5 +/* PCNT_PULSE_CNT_RST_U2 : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_PULSE_CNT_RST_U2 (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_M (BIT(4)) +#define PCNT_PULSE_CNT_RST_U2_V 0x1 +#define PCNT_PULSE_CNT_RST_U2_S 4 +/* PCNT_CNT_PAUSE_U1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_PAUSE_U1 (BIT(3)) +#define PCNT_CNT_PAUSE_U1_M (BIT(3)) +#define PCNT_CNT_PAUSE_U1_V 0x1 +#define PCNT_CNT_PAUSE_U1_S 3 +/* PCNT_PULSE_CNT_RST_U1 : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_PULSE_CNT_RST_U1 (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_M (BIT(2)) +#define PCNT_PULSE_CNT_RST_U1_V 0x1 +#define PCNT_PULSE_CNT_RST_U1_S 2 +/* PCNT_CNT_PAUSE_U0 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define PCNT_CNT_PAUSE_U0 (BIT(1)) +#define PCNT_CNT_PAUSE_U0_M (BIT(1)) +#define PCNT_CNT_PAUSE_U0_V 0x1 +#define PCNT_CNT_PAUSE_U0_S 1 +/* PCNT_PULSE_CNT_RST_U0 : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define PCNT_PULSE_CNT_RST_U0 (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_M (BIT(0)) +#define PCNT_PULSE_CNT_RST_U0_V 0x1 +#define PCNT_PULSE_CNT_RST_U0_S 0 + +#define PCNT_DATE_REG (DR_REG_PCNT_BASE + 0x00fc) +/* PCNT_DATE : R/W ;bitpos:[31:0] ;default: 32'h18072600 ; */ +/*description: */ +#define PCNT_DATE 0xFFFFFFFF +#define PCNT_DATE_M ((PCNT_DATE_V) << (PCNT_DATE_S)) +#define PCNT_DATE_V 0xFFFFFFFF +#define PCNT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/pcnt_struct.h b/components/soc/soc/esp32s3/include/soc/pcnt_struct.h new file mode 100644 index 000000000..d01aa09ff --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/pcnt_struct.h @@ -0,0 +1,179 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + struct { + union { + struct { + uint32_t filter_thres: 10; + uint32_t filter_en: 1; + uint32_t thr_zero_en: 1; + uint32_t thr_h_lim_en: 1; + uint32_t thr_l_lim_en: 1; + uint32_t thr_thres0_en: 1; + uint32_t thr_thres1_en: 1; + uint32_t ch0_neg_mode: 2; + uint32_t ch0_pos_mode: 2; + uint32_t ch0_hctrl_mode: 2; + uint32_t ch0_lctrl_mode: 2; + uint32_t ch1_neg_mode: 2; + uint32_t ch1_pos_mode: 2; + uint32_t ch1_hctrl_mode: 2; + uint32_t ch1_lctrl_mode: 2; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t cnt_thres0: 16; + uint32_t cnt_thres1: 16; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t cnt_h_lim: 16; + uint32_t cnt_l_lim: 16; + }; + uint32_t val; + } conf2; + } conf_unit[4]; + union { + struct { + uint32_t cnt_val: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } cnt_unit[4]; + union { + struct { + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t cnt_thr_event_u0: 1; + uint32_t cnt_thr_event_u1: 1; + uint32_t cnt_thr_event_u2: 1; + uint32_t cnt_thr_event_u3: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t cnt_mode: 2; + uint32_t thres1_lat: 1; + uint32_t thres0_lat: 1; + uint32_t l_lim_lat: 1; + uint32_t h_lim_lat: 1; + uint32_t zero_lat: 1; + uint32_t reserved7: 25; + }; + uint32_t val; + } status_unit[4]; + union { + struct { + uint32_t cnt_rst_u0: 1; + uint32_t cnt_pause_u0: 1; + uint32_t cnt_rst_u1: 1; + uint32_t cnt_pause_u1: 1; + uint32_t cnt_rst_u2: 1; + uint32_t cnt_pause_u2: 1; + uint32_t cnt_rst_u3: 1; + uint32_t cnt_pause_u3: 1; + uint32_t reserved8: 8; + uint32_t clk_en: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } ctrl; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t date; /**/ +} pcnt_dev_t; + +extern pcnt_dev_t PCNT; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/periph_defs.h b/components/soc/soc/esp32s3/include/soc/periph_defs.h new file mode 100644 index 000000000..273048bac --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/periph_defs.h @@ -0,0 +1,169 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum { + PERIPH_LEDC_MODULE = 0, + PERIPH_UART0_MODULE, + PERIPH_UART1_MODULE, + PERIPH_UART2_MODULE, + PERIPH_USB_MODULE, + PERIPH_I2C0_MODULE, + PERIPH_I2C1_MODULE, + PERIPH_I2S0_MODULE, + PERIPH_I2S1_MODULE, + PERIPH_TIMG0_MODULE, + PERIPH_TIMG1_MODULE, + PERIPH_PWM0_MODULE, + PERIPH_PWM1_MODULE, + PERIPH_PWM2_MODULE, + PERIPH_PWM3_MODULE, + PERIPH_UHCI0_MODULE, + PERIPH_UHCI1_MODULE, + PERIPH_RMT_MODULE, + PERIPH_PCNT_MODULE, + PERIPH_SPI_MODULE, //SPI1 + PERIPH_FSPI_MODULE, //SPI2 + PERIPH_HSPI_MODULE, //SPI3 + PERIPH_VSPI_MODULE, //SPI4 + PERIPH_SPI2_DMA_MODULE, + PERIPH_SPI3_DMA_MODULE, + PERIPH_SPI_SHARED_DMA_MODULE, //this DMA is shared by SPI1 and SPI4 + PERIPH_SDMMC_MODULE, + PERIPH_TWAI_MODULE, + PERIPH_RNG_MODULE, + PERIPH_WIFI_MODULE, + PERIPH_BT_MODULE, + PERIPH_WIFI_BT_COMMON_MODULE, + PERIPH_BT_BASEBAND_MODULE, + PERIPH_BT_LC_MODULE, + PERIPH_AES_MODULE, + PERIPH_SHA_MODULE, + PERIPH_RSA_MODULE, + PERIPH_CRYPTO_DMA_MODULE, //this DMA is shared between AES and SHA + PERIPH_AES_DMA_MODULE, + PERIPH_SHA_DMA_MODULE, + PERIPH_MODULE_MAX +} periph_module_t; + +typedef enum { + ETS_WIFI_MAC_INTR_SOURCE = 0, /**< interrupt of WiFi MAC, level*/ + ETS_WIFI_MAC_NMI_SOURCE, /**< interrupt of WiFi MAC, NMI, use if MAC have bug to fix in NMI*/ + ETS_WIFI_PWR_INTR_SOURCE, /**< */ + ETS_WIFI_BB_INTR_SOURCE, /**< interrupt of WiFi BB, level, we can do some calibartion*/ + ETS_BT_MAC_INTR_SOURCE, /**< will be cancelled*/ + ETS_BT_BB_INTR_SOURCE, /**< interrupt of BT BB, level*/ + ETS_BT_BB_NMI_SOURCE, /**< interrupt of BT BB, NMI, use if BB have bug to fix in NMI*/ + ETS_RWBT_INTR_SOURCE, /**< interrupt of RWBT, level*/ + ETS_RWBLE_INTR_SOURCE, /**< interrupt of RWBLE, level*/ + ETS_RWBT_NMI_SOURCE, /**< interrupt of RWBT, NMI, use if RWBT have bug to fix in NMI*/ + ETS_RWBLE_NMI_SOURCE, /**< interrupt of RWBLE, NMI, use if RWBT have bug to fix in NMI*/ + ETS_I2C_MASTER_SOURCE, /**< interrupt of I2C Master, level*/ + ETS_SLC0_INTR_SOURCE, /**< interrupt of SLC0, level*/ + ETS_SLC1_INTR_SOURCE, /**< interrupt of SLC1, level*/ + ETS_UHCI0_INTR_SOURCE, /**< interrupt of UHCI0, level*/ + ETS_UHCI1_INTR_SOURCE, /**< interrupt of UHCI1, level*/ + + ETS_TG0_T0_LEVEL_INTR_SOURCE = 16, /**< interrupt of TIMER_GROUP0, TIMER0, level, we would like use EDGE for timer if permission*/ + ETS_TG0_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG0_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCHDOG, level*/ + ETS_TG0_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, level*/ + ETS_TG1_T0_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, level, we would like use EDGE for timer if permission*/ + ETS_TG1_T1_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, level, we would like use EDGE for timer if permission*/ + ETS_TG1_WDT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, WATCHDOG, level*/ + ETS_TG1_LACT_LEVEL_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, LACT, level*/ + ETS_GPIO_INTR_SOURCE, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE, /**< interrupt of GPIO, NMI*/ + ETS_GPIO_INTR_SOURCE2, /**< interrupt of GPIO, level*/ + ETS_GPIO_NMI_SOURCE2, /**< interrupt of GPIO, NMI*/ + ETS_SPI1_INTR_SOURCE, /**< interrupt of SPI1, level, SPI1 is for flash read/write, do not use this*/ + ETS_SPI2_INTR_SOURCE, /**< interrupt of SPI2, level*/ + ETS_SPI3_INTR_SOURCE, /**< interrupt of SPI3, level*/ + ETS_SPI4_INTR_SOURCE, /**< interrupt of SPI4, level*/ + + ETS_LCD_CAM_INTR_SOURCE = 32, /**< interrupt of LCD camera, level*/ + ETS_I2S0_INTR_SOURCE, /**< interrupt of I2S0, level*/ + ETS_I2S1_INTR_SOURCE, /**< interrupt of I2S1, level*/ + ETS_UART0_INTR_SOURCE, /**< interrupt of UART0, level*/ + ETS_UART1_INTR_SOURCE, /**< interrupt of UART1, level*/ + ETS_UART2_INTR_SOURCE, /**< interrupt of UART2, level*/ + ETS_SDIO_HOST_INTR_SOURCE, /**< interrupt of SD/SDIO/MMC HOST, level*/ + ETS_PWM0_INTR_SOURCE, /**< interrupt of PWM0, level, Reserved*/ + ETS_PWM1_INTR_SOURCE, /**< interrupt of PWM1, level, Reserved*/ + ETS_PWM2_INTR_SOURCE, /**< interrupt of PWM2, level*/ + ETS_PWM3_INTR_SOURCE, /**< interruot of PWM3, level*/ + ETS_LEDC_INTR_SOURCE, /**< interrupt of LED PWM, level*/ + ETS_EFUSE_INTR_SOURCE, /**< interrupt of efuse, level, not likely to use*/ + ETS_TWAI_INTR_SOURCE, /**< interrupt of TWAI, level*/ + ETS_USB_INTR_SOURCE, /**< interrupt of USB, level*/ + ETS_RTC_CORE_INTR_SOURCE, /**< interrupt of rtc core, level, include rtc watchdog*/ + + ETS_RMT_INTR_SOURCE = 48, /**< interrupt of remote controller, level*/ + ETS_PCNT_INTR_SOURCE, /**< interrupt of pluse count, level*/ + ETS_I2C_EXT0_INTR_SOURCE, /**< interrupt of I2C controller1, level*/ + ETS_I2C_EXT1_INTR_SOURCE, /**< interrupt of I2C controller0, level*/ + ETS_SPI2_DMA_INTR_SOURCE, /**< interrupt of SPI2 DMA, level*/ + ETS_SPI3_DMA_INTR_SOURCE, /**< interrupt of SPI3 DMA, level*/ + ETS_SPI4_DMA_INTR_SOURCE, /**< interrupt of SPI4 DMA, level*/ + ETS_WDT_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER1_INTR_SOURCE, /**< will be cancelled*/ + ETS_TIMER2_INTR_SOURCE, /**< will be cancelled*/ + ETS_TG0_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER0, EDGE*/ + ETS_TG0_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, TIMER1, EDGE*/ + ETS_TG0_WDT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, WATCH DOG, EDGE*/ + ETS_TG0_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_TG1_T0_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER0, EDGE*/ + ETS_TG1_T1_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP1, TIMER1, EDGE*/ + + ETS_TG1_WDT_EDGE_INTR_SOURCE = 64, /**< interrupt of TIMER_GROUP1, WATCHDOG, EDGE*/ + ETS_TG1_LACT_EDGE_INTR_SOURCE, /**< interrupt of TIMER_GROUP0, LACT, EDGE*/ + ETS_CACHE_IA_INTR_SOURCE, /**< interrupt of Cache Invalied Access, LEVEL*/ + ETS_SYSTIMER_TARGET0_EDGE_INTR_SOURCE, /**< interrupt of system timer 0, EDGE*/ + ETS_SYSTIMER_TARGET1_EDGE_INTR_SOURCE, /**< interrupt of system timer 1, EDGE*/ + ETS_SYSTIMER_TARGET2_EDGE_INTR_SOURCE, /**< interrupt of system timer 2, EDGE*/ + ETS_SPI_MEM_REJECT_CACHE_INTR_SOURCE, /**< interrupt of SPI0 Cache access and SPI1 access rejected, LEVEL*/ + ETS_DCACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ + ETS_ICACHE_PRELOAD0_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_DCACHE_SYNC0_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ + ETS_ICACHE_SYNC0_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + ETS_APB_ADC_INTR_SOURCE, /**< interrupt of APB ADC, LEVEL*/ + ETS_CRYPTO_DMA_INTR_SOURCE, /**< interrupt of encrypted DMA, LEVEL*/ + ETS_RSA_INTR_SOURCE, /**< interrupt of RSA accelerator, level*/ + ETS_SHA_INTR_SOURCE, /**< interrupt of SHA accelerator, level*/ + ETS_AES_INTR_SOURCE, /**< interrupt of AES accelerator, level*/ + + ETS_FROM_CPU_INTR0_SOURCE = 80, /**< interrupt0 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR1_SOURCE, /**< interrupt1 generated from a CPU, level*/ /* Used for FreeRTOS */ + ETS_FROM_CPU_INTR2_SOURCE, /**< interrupt2 generated from a CPU, level*/ /* Used for DPORT Access */ + ETS_FROM_CPU_INTR3_SOURCE, /**< interrupt3 generated from a CPU, level*/ /* Used for DPORT Access */ + ETS_DMA_COPY_INTR_SOURCE, /**< interrupt of DMA copy, LEVEL*/ + ETS_ASSIST_DEBUG_INTR_SOURCE, /**< interrupt of Assist debug module, LEVEL*/ + ETS_DEDICATED_GPIO_INTR_SOURCE, /**< interrupt of dedicated GPIO, level*/ + ETS_DCACHE_PRELOAD1_INTR_SOURCE, /**< interrupt of DCache preload operation, LEVEL*/ + ETS_ICACHE_PRELOAD1_INTR_SOURCE, /**< interrupt of ICache perload operation, LEVEL*/ + ETS_DCACHE_SYNC1_INTR_SOURCE, /**< interrupt of data cache sync done, LEVEL*/ + ETS_ICACHE_SYNC1_INTR_SOURCE, /**< interrupt of instruction cache sync done, LEVEL*/ + + ETS_MAX_INTR_SOURCE, /**< number of interrupt sources */ + +} periph_interrput_t; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rmt_caps.h b/components/soc/soc/esp32s3/include/soc/rmt_caps.h new file mode 100644 index 000000000..43c45b9e1 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rmt_caps.h @@ -0,0 +1,30 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_RMT_CHANNEL_MEM_WORDS (64) /*!< Each channel owns 64 words memory (1 word = 4 Bytes) */ +#define SOC_RMT_CHANNELS_NUM (4) /*!< Total 4 channels */ +#define SOC_RMT_SUPPORT_RX_PINGPONG (1) /*!< Support Ping-Pong mode on RX path */ +#define SOC_RMT_SUPPORT_RX_DEMODULATION (1) /*!< Support signal demodulation on RX path (i.e. remove carrier) */ +#define SOC_RMT_SUPPORT_TX_LOOP_COUNT (1) /*!< Support transmit specified number of cycles in loop mode */ +#define SOC_RMT_SUPPORT_TX_GROUP (1) /*!< Support a group of TX channels to transmit simultaneously */ + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rmt_reg.h b/components/soc/soc/esp32s3/include/soc/rmt_reg.h new file mode 100644 index 000000000..bddf00227 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rmt_reg.h @@ -0,0 +1,2120 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define RMT_CH0DATA_REG (DR_REG_RMT_BASE + 0x0000) + +#define RMT_CH1DATA_REG (DR_REG_RMT_BASE + 0x0004) + +#define RMT_CH2DATA_REG (DR_REG_RMT_BASE + 0x0008) + +#define RMT_CH3DATA_REG (DR_REG_RMT_BASE + 0x000c) + +#define RMT_CH4DATA_REG (DR_REG_RMT_BASE + 0x0010) + +#define RMT_CH5DATA_REG (DR_REG_RMT_BASE + 0x0014) + +#define RMT_CH6DATA_REG (DR_REG_RMT_BASE + 0x0018) + +#define RMT_CH7DATA_REG (DR_REG_RMT_BASE + 0x001c) + +#define RMT_CH0CONF0_REG (DR_REG_RMT_BASE + 0x0020) +/* RMT_CONF_UPDATE_CH0 : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH0 (BIT(24)) +#define RMT_CONF_UPDATE_CH0_M (BIT(24)) +#define RMT_CONF_UPDATE_CH0_V 0x1 +#define RMT_CONF_UPDATE_CH0_S 24 +/* RMT_AFIFO_RST_CH0 : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH0 (BIT(23)) +#define RMT_AFIFO_RST_CH0_M (BIT(23)) +#define RMT_AFIFO_RST_CH0_V 0x1 +#define RMT_AFIFO_RST_CH0_S 23 +/* RMT_CARRIER_OUT_LV_CH0 : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH0 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH0_V 0x1 +#define RMT_CARRIER_OUT_LV_CH0_S 22 +/* RMT_CARRIER_EN_CH0 : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH0 (BIT(21)) +#define RMT_CARRIER_EN_CH0_M (BIT(21)) +#define RMT_CARRIER_EN_CH0_V 0x1 +#define RMT_CARRIER_EN_CH0_S 21 +/* RMT_CARRIER_EFF_EN_CH0 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH0 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH0_V 0x1 +#define RMT_CARRIER_EFF_EN_CH0_S 20 +/* RMT_MEM_SIZE_CH0 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH0 0x0000000F +#define RMT_MEM_SIZE_CH0_M ((RMT_MEM_SIZE_CH0_V) << (RMT_MEM_SIZE_CH0_S)) +#define RMT_MEM_SIZE_CH0_V 0xF +#define RMT_MEM_SIZE_CH0_S 16 +/* RMT_DIV_CNT_CH0 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH0 0x000000FF +#define RMT_DIV_CNT_CH0_M ((RMT_DIV_CNT_CH0_V) << (RMT_DIV_CNT_CH0_S)) +#define RMT_DIV_CNT_CH0_V 0xFF +#define RMT_DIV_CNT_CH0_S 8 +/* RMT_TX_STOP_CH0 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_STOP_CH0 (BIT(7)) +#define RMT_TX_STOP_CH0_M (BIT(7)) +#define RMT_TX_STOP_CH0_V 0x1 +#define RMT_TX_STOP_CH0_S 7 +/* RMT_IDLE_OUT_EN_CH0 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_EN_CH0 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH0_V 0x1 +#define RMT_IDLE_OUT_EN_CH0_S 6 +/* RMT_IDLE_OUT_LV_CH0 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_LV_CH0 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH0_V 0x1 +#define RMT_IDLE_OUT_LV_CH0_S 5 +/* RMT_MEM_TX_WRAP_EN_CH0 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_TX_WRAP_EN_CH0 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH0_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH0_S 4 +/* RMT_TX_CONTI_MODE_CH0 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_CONTI_MODE_CH0 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH0_V 0x1 +#define RMT_TX_CONTI_MODE_CH0_S 3 +/* RMT_APB_MEM_RST_CH0 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH0 (BIT(2)) +#define RMT_APB_MEM_RST_CH0_M (BIT(2)) +#define RMT_APB_MEM_RST_CH0_V 0x1 +#define RMT_APB_MEM_RST_CH0_S 2 +/* RMT_MEM_RD_RST_CH0 : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RD_RST_CH0 (BIT(1)) +#define RMT_MEM_RD_RST_CH0_M (BIT(1)) +#define RMT_MEM_RD_RST_CH0_V 0x1 +#define RMT_MEM_RD_RST_CH0_S 1 +/* RMT_TX_START_CH0 : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_TX_START_CH0 (BIT(0)) +#define RMT_TX_START_CH0_M (BIT(0)) +#define RMT_TX_START_CH0_V 0x1 +#define RMT_TX_START_CH0_S 0 + +#define RMT_CH1CONF0_REG (DR_REG_RMT_BASE + 0x0024) +/* RMT_CONF_UPDATE_CH1 : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH1 (BIT(24)) +#define RMT_CONF_UPDATE_CH1_M (BIT(24)) +#define RMT_CONF_UPDATE_CH1_V 0x1 +#define RMT_CONF_UPDATE_CH1_S 24 +/* RMT_AFIFO_RST_CH1 : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH1 (BIT(23)) +#define RMT_AFIFO_RST_CH1_M (BIT(23)) +#define RMT_AFIFO_RST_CH1_V 0x1 +#define RMT_AFIFO_RST_CH1_S 23 +/* RMT_CARRIER_OUT_LV_CH1 : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH1 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH1_V 0x1 +#define RMT_CARRIER_OUT_LV_CH1_S 22 +/* RMT_CARRIER_EN_CH1 : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH1 (BIT(21)) +#define RMT_CARRIER_EN_CH1_M (BIT(21)) +#define RMT_CARRIER_EN_CH1_V 0x1 +#define RMT_CARRIER_EN_CH1_S 21 +/* RMT_CARRIER_EFF_EN_CH1 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH1 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH1_V 0x1 +#define RMT_CARRIER_EFF_EN_CH1_S 20 +/* RMT_MEM_SIZE_CH1 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH1 0x0000000F +#define RMT_MEM_SIZE_CH1_M ((RMT_MEM_SIZE_CH1_V) << (RMT_MEM_SIZE_CH1_S)) +#define RMT_MEM_SIZE_CH1_V 0xF +#define RMT_MEM_SIZE_CH1_S 16 +/* RMT_DIV_CNT_CH1 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH1 0x000000FF +#define RMT_DIV_CNT_CH1_M ((RMT_DIV_CNT_CH1_V) << (RMT_DIV_CNT_CH1_S)) +#define RMT_DIV_CNT_CH1_V 0xFF +#define RMT_DIV_CNT_CH1_S 8 +/* RMT_TX_STOP_CH1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_STOP_CH1 (BIT(7)) +#define RMT_TX_STOP_CH1_M (BIT(7)) +#define RMT_TX_STOP_CH1_V 0x1 +#define RMT_TX_STOP_CH1_S 7 +/* RMT_IDLE_OUT_EN_CH1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_EN_CH1 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH1_V 0x1 +#define RMT_IDLE_OUT_EN_CH1_S 6 +/* RMT_IDLE_OUT_LV_CH1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_LV_CH1 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH1_V 0x1 +#define RMT_IDLE_OUT_LV_CH1_S 5 +/* RMT_MEM_TX_WRAP_EN_CH1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_TX_WRAP_EN_CH1 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH1_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH1_S 4 +/* RMT_TX_CONTI_MODE_CH1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_CONTI_MODE_CH1 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH1_V 0x1 +#define RMT_TX_CONTI_MODE_CH1_S 3 +/* RMT_APB_MEM_RST_CH1 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH1 (BIT(2)) +#define RMT_APB_MEM_RST_CH1_M (BIT(2)) +#define RMT_APB_MEM_RST_CH1_V 0x1 +#define RMT_APB_MEM_RST_CH1_S 2 +/* RMT_MEM_RD_RST_CH1 : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RD_RST_CH1 (BIT(1)) +#define RMT_MEM_RD_RST_CH1_M (BIT(1)) +#define RMT_MEM_RD_RST_CH1_V 0x1 +#define RMT_MEM_RD_RST_CH1_S 1 +/* RMT_TX_START_CH1 : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_TX_START_CH1 (BIT(0)) +#define RMT_TX_START_CH1_M (BIT(0)) +#define RMT_TX_START_CH1_V 0x1 +#define RMT_TX_START_CH1_S 0 + +#define RMT_CH2CONF0_REG (DR_REG_RMT_BASE + 0x0028) +/* RMT_CONF_UPDATE_CH2 : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH2 (BIT(24)) +#define RMT_CONF_UPDATE_CH2_M (BIT(24)) +#define RMT_CONF_UPDATE_CH2_V 0x1 +#define RMT_CONF_UPDATE_CH2_S 24 +/* RMT_AFIFO_RST_CH2 : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH2 (BIT(23)) +#define RMT_AFIFO_RST_CH2_M (BIT(23)) +#define RMT_AFIFO_RST_CH2_V 0x1 +#define RMT_AFIFO_RST_CH2_S 23 +/* RMT_CARRIER_OUT_LV_CH2 : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH2 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH2_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH2_V 0x1 +#define RMT_CARRIER_OUT_LV_CH2_S 22 +/* RMT_CARRIER_EN_CH2 : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH2 (BIT(21)) +#define RMT_CARRIER_EN_CH2_M (BIT(21)) +#define RMT_CARRIER_EN_CH2_V 0x1 +#define RMT_CARRIER_EN_CH2_S 21 +/* RMT_CARRIER_EFF_EN_CH2 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH2 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH2_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH2_V 0x1 +#define RMT_CARRIER_EFF_EN_CH2_S 20 +/* RMT_MEM_SIZE_CH2 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH2 0x0000000F +#define RMT_MEM_SIZE_CH2_M ((RMT_MEM_SIZE_CH2_V) << (RMT_MEM_SIZE_CH2_S)) +#define RMT_MEM_SIZE_CH2_V 0xF +#define RMT_MEM_SIZE_CH2_S 16 +/* RMT_DIV_CNT_CH2 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH2 0x000000FF +#define RMT_DIV_CNT_CH2_M ((RMT_DIV_CNT_CH2_V) << (RMT_DIV_CNT_CH2_S)) +#define RMT_DIV_CNT_CH2_V 0xFF +#define RMT_DIV_CNT_CH2_S 8 +/* RMT_TX_STOP_CH2 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_STOP_CH2 (BIT(7)) +#define RMT_TX_STOP_CH2_M (BIT(7)) +#define RMT_TX_STOP_CH2_V 0x1 +#define RMT_TX_STOP_CH2_S 7 +/* RMT_IDLE_OUT_EN_CH2 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_EN_CH2 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH2_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH2_V 0x1 +#define RMT_IDLE_OUT_EN_CH2_S 6 +/* RMT_IDLE_OUT_LV_CH2 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_LV_CH2 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH2_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH2_V 0x1 +#define RMT_IDLE_OUT_LV_CH2_S 5 +/* RMT_MEM_TX_WRAP_EN_CH2 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_TX_WRAP_EN_CH2 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH2_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH2_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH2_S 4 +/* RMT_TX_CONTI_MODE_CH2 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_CONTI_MODE_CH2 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH2_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH2_V 0x1 +#define RMT_TX_CONTI_MODE_CH2_S 3 +/* RMT_APB_MEM_RST_CH2 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH2 (BIT(2)) +#define RMT_APB_MEM_RST_CH2_M (BIT(2)) +#define RMT_APB_MEM_RST_CH2_V 0x1 +#define RMT_APB_MEM_RST_CH2_S 2 +/* RMT_MEM_RD_RST_CH2 : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RD_RST_CH2 (BIT(1)) +#define RMT_MEM_RD_RST_CH2_M (BIT(1)) +#define RMT_MEM_RD_RST_CH2_V 0x1 +#define RMT_MEM_RD_RST_CH2_S 1 +/* RMT_TX_START_CH2 : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_TX_START_CH2 (BIT(0)) +#define RMT_TX_START_CH2_M (BIT(0)) +#define RMT_TX_START_CH2_V 0x1 +#define RMT_TX_START_CH2_S 0 + +#define RMT_CH3CONF0_REG (DR_REG_RMT_BASE + 0x002c) +/* RMT_CONF_UPDATE_CH3 : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH3 (BIT(24)) +#define RMT_CONF_UPDATE_CH3_M (BIT(24)) +#define RMT_CONF_UPDATE_CH3_V 0x1 +#define RMT_CONF_UPDATE_CH3_S 24 +/* RMT_AFIFO_RST_CH3 : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH3 (BIT(23)) +#define RMT_AFIFO_RST_CH3_M (BIT(23)) +#define RMT_AFIFO_RST_CH3_V 0x1 +#define RMT_AFIFO_RST_CH3_S 23 +/* RMT_CARRIER_OUT_LV_CH3 : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH3 (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH3_M (BIT(22)) +#define RMT_CARRIER_OUT_LV_CH3_V 0x1 +#define RMT_CARRIER_OUT_LV_CH3_S 22 +/* RMT_CARRIER_EN_CH3 : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH3 (BIT(21)) +#define RMT_CARRIER_EN_CH3_M (BIT(21)) +#define RMT_CARRIER_EN_CH3_V 0x1 +#define RMT_CARRIER_EN_CH3_S 21 +/* RMT_CARRIER_EFF_EN_CH3 : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EFF_EN_CH3 (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH3_M (BIT(20)) +#define RMT_CARRIER_EFF_EN_CH3_V 0x1 +#define RMT_CARRIER_EFF_EN_CH3_S 20 +/* RMT_MEM_SIZE_CH3 : R/W ;bitpos:[19:16] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH3 0x0000000F +#define RMT_MEM_SIZE_CH3_M ((RMT_MEM_SIZE_CH3_V) << (RMT_MEM_SIZE_CH3_S)) +#define RMT_MEM_SIZE_CH3_V 0xF +#define RMT_MEM_SIZE_CH3_S 16 +/* RMT_DIV_CNT_CH3 : R/W ;bitpos:[15:8] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH3 0x000000FF +#define RMT_DIV_CNT_CH3_M ((RMT_DIV_CNT_CH3_V) << (RMT_DIV_CNT_CH3_S)) +#define RMT_DIV_CNT_CH3_V 0xFF +#define RMT_DIV_CNT_CH3_S 8 +/* RMT_TX_STOP_CH3 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_STOP_CH3 (BIT(7)) +#define RMT_TX_STOP_CH3_M (BIT(7)) +#define RMT_TX_STOP_CH3_V 0x1 +#define RMT_TX_STOP_CH3_S 7 +/* RMT_IDLE_OUT_EN_CH3 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_EN_CH3 (BIT(6)) +#define RMT_IDLE_OUT_EN_CH3_M (BIT(6)) +#define RMT_IDLE_OUT_EN_CH3_V 0x1 +#define RMT_IDLE_OUT_EN_CH3_S 6 +/* RMT_IDLE_OUT_LV_CH3 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_IDLE_OUT_LV_CH3 (BIT(5)) +#define RMT_IDLE_OUT_LV_CH3_M (BIT(5)) +#define RMT_IDLE_OUT_LV_CH3_V 0x1 +#define RMT_IDLE_OUT_LV_CH3_S 5 +/* RMT_MEM_TX_WRAP_EN_CH3 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_TX_WRAP_EN_CH3 (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH3_M (BIT(4)) +#define RMT_MEM_TX_WRAP_EN_CH3_V 0x1 +#define RMT_MEM_TX_WRAP_EN_CH3_S 4 +/* RMT_TX_CONTI_MODE_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_CONTI_MODE_CH3 (BIT(3)) +#define RMT_TX_CONTI_MODE_CH3_M (BIT(3)) +#define RMT_TX_CONTI_MODE_CH3_V 0x1 +#define RMT_TX_CONTI_MODE_CH3_S 3 +/* RMT_APB_MEM_RST_CH3 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH3 (BIT(2)) +#define RMT_APB_MEM_RST_CH3_M (BIT(2)) +#define RMT_APB_MEM_RST_CH3_V 0x1 +#define RMT_APB_MEM_RST_CH3_S 2 +/* RMT_MEM_RD_RST_CH3 : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RD_RST_CH3 (BIT(1)) +#define RMT_MEM_RD_RST_CH3_M (BIT(1)) +#define RMT_MEM_RD_RST_CH3_V 0x1 +#define RMT_MEM_RD_RST_CH3_S 1 +/* RMT_TX_START_CH3 : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_TX_START_CH3 (BIT(0)) +#define RMT_TX_START_CH3_M (BIT(0)) +#define RMT_TX_START_CH3_V 0x1 +#define RMT_TX_START_CH3_S 0 + +#define RMT_CH4CONF0_REG (DR_REG_RMT_BASE + 0x0030) +/* RMT_CARRIER_OUT_LV_CH4 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH4 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH4_V 0x1 +#define RMT_CARRIER_OUT_LV_CH4_S 29 +/* RMT_CARRIER_EN_CH4 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH4 (BIT(28)) +#define RMT_CARRIER_EN_CH4_M (BIT(28)) +#define RMT_CARRIER_EN_CH4_V 0x1 +#define RMT_CARRIER_EN_CH4_S 28 +/* RMT_MEM_SIZE_CH4 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH4 0x0000000F +#define RMT_MEM_SIZE_CH4_M ((RMT_MEM_SIZE_CH4_V) << (RMT_MEM_SIZE_CH4_S)) +#define RMT_MEM_SIZE_CH4_V 0xF +#define RMT_MEM_SIZE_CH4_S 24 +/* RMT_IDLE_THRES_CH4 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ +/*description: */ +#define RMT_IDLE_THRES_CH4 0x00007FFF +#define RMT_IDLE_THRES_CH4_M ((RMT_IDLE_THRES_CH4_V) << (RMT_IDLE_THRES_CH4_S)) +#define RMT_IDLE_THRES_CH4_V 0x7FFF +#define RMT_IDLE_THRES_CH4_S 8 +/* RMT_DIV_CNT_CH4 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH4 0x000000FF +#define RMT_DIV_CNT_CH4_M ((RMT_DIV_CNT_CH4_V) << (RMT_DIV_CNT_CH4_S)) +#define RMT_DIV_CNT_CH4_V 0xFF +#define RMT_DIV_CNT_CH4_S 0 + +#define RMT_CH4CONF1_REG (DR_REG_RMT_BASE + 0x0034) +/* RMT_CONF_UPDATE_CH4 : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH4 (BIT(15)) +#define RMT_CONF_UPDATE_CH4_M (BIT(15)) +#define RMT_CONF_UPDATE_CH4_V 0x1 +#define RMT_CONF_UPDATE_CH4_S 15 +/* RMT_AFIFO_RST_CH4 : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH4 (BIT(14)) +#define RMT_AFIFO_RST_CH4_M (BIT(14)) +#define RMT_AFIFO_RST_CH4_V 0x1 +#define RMT_AFIFO_RST_CH4_S 14 +/* RMT_MEM_RX_WRAP_EN_CH4 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RX_WRAP_EN_CH4 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH4_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH4_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH4_S 13 +/* RMT_RX_FILTER_THRES_CH4 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ +/*description: */ +#define RMT_RX_FILTER_THRES_CH4 0x000000FF +#define RMT_RX_FILTER_THRES_CH4_M ((RMT_RX_FILTER_THRES_CH4_V) << (RMT_RX_FILTER_THRES_CH4_S)) +#define RMT_RX_FILTER_THRES_CH4_V 0xFF +#define RMT_RX_FILTER_THRES_CH4_S 5 +/* RMT_RX_FILTER_EN_CH4 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_RX_FILTER_EN_CH4 (BIT(4)) +#define RMT_RX_FILTER_EN_CH4_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH4_V 0x1 +#define RMT_RX_FILTER_EN_CH4_S 4 +/* RMT_MEM_OWNER_CH4 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define RMT_MEM_OWNER_CH4 (BIT(3)) +#define RMT_MEM_OWNER_CH4_M (BIT(3)) +#define RMT_MEM_OWNER_CH4_V 0x1 +#define RMT_MEM_OWNER_CH4_S 3 +/* RMT_APB_MEM_RST_CH4 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH4 (BIT(2)) +#define RMT_APB_MEM_RST_CH4_M (BIT(2)) +#define RMT_APB_MEM_RST_CH4_V 0x1 +#define RMT_APB_MEM_RST_CH4_S 2 +/* RMT_MEM_WR_RST_CH4 : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define RMT_MEM_WR_RST_CH4 (BIT(1)) +#define RMT_MEM_WR_RST_CH4_M (BIT(1)) +#define RMT_MEM_WR_RST_CH4_V 0x1 +#define RMT_MEM_WR_RST_CH4_S 1 +/* RMT_RX_EN_CH4 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_RX_EN_CH4 (BIT(0)) +#define RMT_RX_EN_CH4_M (BIT(0)) +#define RMT_RX_EN_CH4_V 0x1 +#define RMT_RX_EN_CH4_S 0 + +#define RMT_CH5CONF0_REG (DR_REG_RMT_BASE + 0x0038) +/* RMT_CARRIER_OUT_LV_CH5 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH5 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH5_V 0x1 +#define RMT_CARRIER_OUT_LV_CH5_S 29 +/* RMT_CARRIER_EN_CH5 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH5 (BIT(28)) +#define RMT_CARRIER_EN_CH5_M (BIT(28)) +#define RMT_CARRIER_EN_CH5_V 0x1 +#define RMT_CARRIER_EN_CH5_S 28 +/* RMT_MEM_SIZE_CH5 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH5 0x0000000F +#define RMT_MEM_SIZE_CH5_M ((RMT_MEM_SIZE_CH5_V) << (RMT_MEM_SIZE_CH5_S)) +#define RMT_MEM_SIZE_CH5_V 0xF +#define RMT_MEM_SIZE_CH5_S 24 +/* RMT_IDLE_THRES_CH5 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ +/*description: */ +#define RMT_IDLE_THRES_CH5 0x00007FFF +#define RMT_IDLE_THRES_CH5_M ((RMT_IDLE_THRES_CH5_V) << (RMT_IDLE_THRES_CH5_S)) +#define RMT_IDLE_THRES_CH5_V 0x7FFF +#define RMT_IDLE_THRES_CH5_S 8 +/* RMT_DIV_CNT_CH5 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH5 0x000000FF +#define RMT_DIV_CNT_CH5_M ((RMT_DIV_CNT_CH5_V) << (RMT_DIV_CNT_CH5_S)) +#define RMT_DIV_CNT_CH5_V 0xFF +#define RMT_DIV_CNT_CH5_S 0 + +#define RMT_CH5CONF1_REG (DR_REG_RMT_BASE + 0x003c) +/* RMT_CONF_UPDATE_CH5 : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH5 (BIT(15)) +#define RMT_CONF_UPDATE_CH5_M (BIT(15)) +#define RMT_CONF_UPDATE_CH5_V 0x1 +#define RMT_CONF_UPDATE_CH5_S 15 +/* RMT_AFIFO_RST_CH5 : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH5 (BIT(14)) +#define RMT_AFIFO_RST_CH5_M (BIT(14)) +#define RMT_AFIFO_RST_CH5_V 0x1 +#define RMT_AFIFO_RST_CH5_S 14 +/* RMT_MEM_RX_WRAP_EN_CH5 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RX_WRAP_EN_CH5 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH5_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH5_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH5_S 13 +/* RMT_RX_FILTER_THRES_CH5 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ +/*description: */ +#define RMT_RX_FILTER_THRES_CH5 0x000000FF +#define RMT_RX_FILTER_THRES_CH5_M ((RMT_RX_FILTER_THRES_CH5_V) << (RMT_RX_FILTER_THRES_CH5_S)) +#define RMT_RX_FILTER_THRES_CH5_V 0xFF +#define RMT_RX_FILTER_THRES_CH5_S 5 +/* RMT_RX_FILTER_EN_CH5 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_RX_FILTER_EN_CH5 (BIT(4)) +#define RMT_RX_FILTER_EN_CH5_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH5_V 0x1 +#define RMT_RX_FILTER_EN_CH5_S 4 +/* RMT_MEM_OWNER_CH5 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define RMT_MEM_OWNER_CH5 (BIT(3)) +#define RMT_MEM_OWNER_CH5_M (BIT(3)) +#define RMT_MEM_OWNER_CH5_V 0x1 +#define RMT_MEM_OWNER_CH5_S 3 +/* RMT_APB_MEM_RST_CH5 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH5 (BIT(2)) +#define RMT_APB_MEM_RST_CH5_M (BIT(2)) +#define RMT_APB_MEM_RST_CH5_V 0x1 +#define RMT_APB_MEM_RST_CH5_S 2 +/* RMT_MEM_WR_RST_CH5 : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define RMT_MEM_WR_RST_CH5 (BIT(1)) +#define RMT_MEM_WR_RST_CH5_M (BIT(1)) +#define RMT_MEM_WR_RST_CH5_V 0x1 +#define RMT_MEM_WR_RST_CH5_S 1 +/* RMT_RX_EN_CH5 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_RX_EN_CH5 (BIT(0)) +#define RMT_RX_EN_CH5_M (BIT(0)) +#define RMT_RX_EN_CH5_V 0x1 +#define RMT_RX_EN_CH5_S 0 + +#define RMT_CH6CONF0_REG (DR_REG_RMT_BASE + 0x0040) +/* RMT_CARRIER_OUT_LV_CH6 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH6 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH6_V 0x1 +#define RMT_CARRIER_OUT_LV_CH6_S 29 +/* RMT_CARRIER_EN_CH6 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH6 (BIT(28)) +#define RMT_CARRIER_EN_CH6_M (BIT(28)) +#define RMT_CARRIER_EN_CH6_V 0x1 +#define RMT_CARRIER_EN_CH6_S 28 +/* RMT_MEM_SIZE_CH6 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH6 0x0000000F +#define RMT_MEM_SIZE_CH6_M ((RMT_MEM_SIZE_CH6_V) << (RMT_MEM_SIZE_CH6_S)) +#define RMT_MEM_SIZE_CH6_V 0xF +#define RMT_MEM_SIZE_CH6_S 24 +/* RMT_IDLE_THRES_CH6 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ +/*description: */ +#define RMT_IDLE_THRES_CH6 0x00007FFF +#define RMT_IDLE_THRES_CH6_M ((RMT_IDLE_THRES_CH6_V) << (RMT_IDLE_THRES_CH6_S)) +#define RMT_IDLE_THRES_CH6_V 0x7FFF +#define RMT_IDLE_THRES_CH6_S 8 +/* RMT_DIV_CNT_CH6 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH6 0x000000FF +#define RMT_DIV_CNT_CH6_M ((RMT_DIV_CNT_CH6_V) << (RMT_DIV_CNT_CH6_S)) +#define RMT_DIV_CNT_CH6_V 0xFF +#define RMT_DIV_CNT_CH6_S 0 + +#define RMT_CH6CONF1_REG (DR_REG_RMT_BASE + 0x0044) +/* RMT_CONF_UPDATE_CH6 : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH6 (BIT(15)) +#define RMT_CONF_UPDATE_CH6_M (BIT(15)) +#define RMT_CONF_UPDATE_CH6_V 0x1 +#define RMT_CONF_UPDATE_CH6_S 15 +/* RMT_AFIFO_RST_CH6 : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH6 (BIT(14)) +#define RMT_AFIFO_RST_CH6_M (BIT(14)) +#define RMT_AFIFO_RST_CH6_V 0x1 +#define RMT_AFIFO_RST_CH6_S 14 +/* RMT_MEM_RX_WRAP_EN_CH6 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RX_WRAP_EN_CH6 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH6_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH6_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH6_S 13 +/* RMT_RX_FILTER_THRES_CH6 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ +/*description: */ +#define RMT_RX_FILTER_THRES_CH6 0x000000FF +#define RMT_RX_FILTER_THRES_CH6_M ((RMT_RX_FILTER_THRES_CH6_V) << (RMT_RX_FILTER_THRES_CH6_S)) +#define RMT_RX_FILTER_THRES_CH6_V 0xFF +#define RMT_RX_FILTER_THRES_CH6_S 5 +/* RMT_RX_FILTER_EN_CH6 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_RX_FILTER_EN_CH6 (BIT(4)) +#define RMT_RX_FILTER_EN_CH6_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH6_V 0x1 +#define RMT_RX_FILTER_EN_CH6_S 4 +/* RMT_MEM_OWNER_CH6 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define RMT_MEM_OWNER_CH6 (BIT(3)) +#define RMT_MEM_OWNER_CH6_M (BIT(3)) +#define RMT_MEM_OWNER_CH6_V 0x1 +#define RMT_MEM_OWNER_CH6_S 3 +/* RMT_APB_MEM_RST_CH6 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH6 (BIT(2)) +#define RMT_APB_MEM_RST_CH6_M (BIT(2)) +#define RMT_APB_MEM_RST_CH6_V 0x1 +#define RMT_APB_MEM_RST_CH6_S 2 +/* RMT_MEM_WR_RST_CH6 : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define RMT_MEM_WR_RST_CH6 (BIT(1)) +#define RMT_MEM_WR_RST_CH6_M (BIT(1)) +#define RMT_MEM_WR_RST_CH6_V 0x1 +#define RMT_MEM_WR_RST_CH6_S 1 +/* RMT_RX_EN_CH6 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_RX_EN_CH6 (BIT(0)) +#define RMT_RX_EN_CH6_M (BIT(0)) +#define RMT_RX_EN_CH6_V 0x1 +#define RMT_RX_EN_CH6_S 0 + +#define RMT_CH7CONF0_REG (DR_REG_RMT_BASE + 0x0048) +/* RMT_CARRIER_OUT_LV_CH7 : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_OUT_LV_CH7 (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_M (BIT(29)) +#define RMT_CARRIER_OUT_LV_CH7_V 0x1 +#define RMT_CARRIER_OUT_LV_CH7_S 29 +/* RMT_CARRIER_EN_CH7 : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define RMT_CARRIER_EN_CH7 (BIT(28)) +#define RMT_CARRIER_EN_CH7_M (BIT(28)) +#define RMT_CARRIER_EN_CH7_V 0x1 +#define RMT_CARRIER_EN_CH7_S 28 +/* RMT_MEM_SIZE_CH7 : R/W ;bitpos:[27:24] ;default: 4'h1 ; */ +/*description: */ +#define RMT_MEM_SIZE_CH7 0x0000000F +#define RMT_MEM_SIZE_CH7_M ((RMT_MEM_SIZE_CH7_V) << (RMT_MEM_SIZE_CH7_S)) +#define RMT_MEM_SIZE_CH7_V 0xF +#define RMT_MEM_SIZE_CH7_S 24 +/* RMT_IDLE_THRES_CH7 : R/W ;bitpos:[22:8] ;default: 15'h7fff ; */ +/*description: */ +#define RMT_IDLE_THRES_CH7 0x00007FFF +#define RMT_IDLE_THRES_CH7_M ((RMT_IDLE_THRES_CH7_V) << (RMT_IDLE_THRES_CH7_S)) +#define RMT_IDLE_THRES_CH7_V 0x7FFF +#define RMT_IDLE_THRES_CH7_S 8 +/* RMT_DIV_CNT_CH7 : R/W ;bitpos:[7:0] ;default: 8'h2 ; */ +/*description: */ +#define RMT_DIV_CNT_CH7 0x000000FF +#define RMT_DIV_CNT_CH7_M ((RMT_DIV_CNT_CH7_V) << (RMT_DIV_CNT_CH7_S)) +#define RMT_DIV_CNT_CH7_V 0xFF +#define RMT_DIV_CNT_CH7_S 0 + +#define RMT_CH7CONF1_REG (DR_REG_RMT_BASE + 0x004c) +/* RMT_CONF_UPDATE_CH7 : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CONF_UPDATE_CH7 (BIT(15)) +#define RMT_CONF_UPDATE_CH7_M (BIT(15)) +#define RMT_CONF_UPDATE_CH7_V 0x1 +#define RMT_CONF_UPDATE_CH7_S 15 +/* RMT_AFIFO_RST_CH7 : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_AFIFO_RST_CH7 (BIT(14)) +#define RMT_AFIFO_RST_CH7_M (BIT(14)) +#define RMT_AFIFO_RST_CH7_V 0x1 +#define RMT_AFIFO_RST_CH7_S 14 +/* RMT_MEM_RX_WRAP_EN_CH7 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_RX_WRAP_EN_CH7 (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH7_M (BIT(13)) +#define RMT_MEM_RX_WRAP_EN_CH7_V 0x1 +#define RMT_MEM_RX_WRAP_EN_CH7_S 13 +/* RMT_RX_FILTER_THRES_CH7 : R/W ;bitpos:[12:5] ;default: 8'hf ; */ +/*description: */ +#define RMT_RX_FILTER_THRES_CH7 0x000000FF +#define RMT_RX_FILTER_THRES_CH7_M ((RMT_RX_FILTER_THRES_CH7_V) << (RMT_RX_FILTER_THRES_CH7_S)) +#define RMT_RX_FILTER_THRES_CH7_V 0xFF +#define RMT_RX_FILTER_THRES_CH7_S 5 +/* RMT_RX_FILTER_EN_CH7 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_RX_FILTER_EN_CH7 (BIT(4)) +#define RMT_RX_FILTER_EN_CH7_M (BIT(4)) +#define RMT_RX_FILTER_EN_CH7_V 0x1 +#define RMT_RX_FILTER_EN_CH7_S 4 +/* RMT_MEM_OWNER_CH7 : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define RMT_MEM_OWNER_CH7 (BIT(3)) +#define RMT_MEM_OWNER_CH7_M (BIT(3)) +#define RMT_MEM_OWNER_CH7_V 0x1 +#define RMT_MEM_OWNER_CH7_S 3 +/* RMT_APB_MEM_RST_CH7 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RST_CH7 (BIT(2)) +#define RMT_APB_MEM_RST_CH7_M (BIT(2)) +#define RMT_APB_MEM_RST_CH7_V 0x1 +#define RMT_APB_MEM_RST_CH7_S 2 +/* RMT_MEM_WR_RST_CH7 : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define RMT_MEM_WR_RST_CH7 (BIT(1)) +#define RMT_MEM_WR_RST_CH7_M (BIT(1)) +#define RMT_MEM_WR_RST_CH7_V 0x1 +#define RMT_MEM_WR_RST_CH7_S 1 +/* RMT_RX_EN_CH7 : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_RX_EN_CH7 (BIT(0)) +#define RMT_RX_EN_CH7_M (BIT(0)) +#define RMT_RX_EN_CH7_V 0x1 +#define RMT_RX_EN_CH7_S 0 + +#define RMT_CH0STATUS_REG (DR_REG_RMT_BASE + 0x0050) +/* RMT_APB_MEM_WR_ERR_CH0 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WR_ERR_CH0 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH0_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH0_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH0_S 26 +/* RMT_MEM_EMPTY_CH0 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_EMPTY_CH0 (BIT(25)) +#define RMT_MEM_EMPTY_CH0_M (BIT(25)) +#define RMT_MEM_EMPTY_CH0_V 0x1 +#define RMT_MEM_EMPTY_CH0_S 25 +/* RMT_STATE_CH0 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH0 0x00000007 +#define RMT_STATE_CH0_M ((RMT_STATE_CH0_V) << (RMT_STATE_CH0_S)) +#define RMT_STATE_CH0_V 0x7 +#define RMT_STATE_CH0_S 22 +/* RMT_APB_MEM_WADDR_CH0 : RO ;bitpos:[20:11] ;default: 10'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WADDR_CH0 0x000003FF +#define RMT_APB_MEM_WADDR_CH0_M ((RMT_APB_MEM_WADDR_CH0_V) << (RMT_APB_MEM_WADDR_CH0_S)) +#define RMT_APB_MEM_WADDR_CH0_V 0x3FF +#define RMT_APB_MEM_WADDR_CH0_S 11 +/* RMT_MEM_RADDR_EX_CH0 : RO ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define RMT_MEM_RADDR_EX_CH0 0x000003FF +#define RMT_MEM_RADDR_EX_CH0_M ((RMT_MEM_RADDR_EX_CH0_V) << (RMT_MEM_RADDR_EX_CH0_S)) +#define RMT_MEM_RADDR_EX_CH0_V 0x3FF +#define RMT_MEM_RADDR_EX_CH0_S 0 + +#define RMT_CH1STATUS_REG (DR_REG_RMT_BASE + 0x0054) +/* RMT_APB_MEM_WR_ERR_CH1 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WR_ERR_CH1 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH1_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH1_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH1_S 26 +/* RMT_MEM_EMPTY_CH1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_EMPTY_CH1 (BIT(25)) +#define RMT_MEM_EMPTY_CH1_M (BIT(25)) +#define RMT_MEM_EMPTY_CH1_V 0x1 +#define RMT_MEM_EMPTY_CH1_S 25 +/* RMT_STATE_CH1 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH1 0x00000007 +#define RMT_STATE_CH1_M ((RMT_STATE_CH1_V) << (RMT_STATE_CH1_S)) +#define RMT_STATE_CH1_V 0x7 +#define RMT_STATE_CH1_S 22 +/* RMT_APB_MEM_WADDR_CH1 : RO ;bitpos:[20:11] ;default: 10'h30 ; */ +/*description: */ +#define RMT_APB_MEM_WADDR_CH1 0x000003FF +#define RMT_APB_MEM_WADDR_CH1_M ((RMT_APB_MEM_WADDR_CH1_V) << (RMT_APB_MEM_WADDR_CH1_S)) +#define RMT_APB_MEM_WADDR_CH1_V 0x3FF +#define RMT_APB_MEM_WADDR_CH1_S 11 +/* RMT_MEM_RADDR_EX_CH1 : RO ;bitpos:[9:0] ;default: 10'h30 ; */ +/*description: */ +#define RMT_MEM_RADDR_EX_CH1 0x000003FF +#define RMT_MEM_RADDR_EX_CH1_M ((RMT_MEM_RADDR_EX_CH1_V) << (RMT_MEM_RADDR_EX_CH1_S)) +#define RMT_MEM_RADDR_EX_CH1_V 0x3FF +#define RMT_MEM_RADDR_EX_CH1_S 0 + +#define RMT_CH2STATUS_REG (DR_REG_RMT_BASE + 0x0058) +/* RMT_APB_MEM_WR_ERR_CH2 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WR_ERR_CH2 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH2_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH2_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH2_S 26 +/* RMT_MEM_EMPTY_CH2 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_EMPTY_CH2 (BIT(25)) +#define RMT_MEM_EMPTY_CH2_M (BIT(25)) +#define RMT_MEM_EMPTY_CH2_V 0x1 +#define RMT_MEM_EMPTY_CH2_S 25 +/* RMT_STATE_CH2 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH2 0x00000007 +#define RMT_STATE_CH2_M ((RMT_STATE_CH2_V) << (RMT_STATE_CH2_S)) +#define RMT_STATE_CH2_V 0x7 +#define RMT_STATE_CH2_S 22 +/* RMT_APB_MEM_WADDR_CH2 : RO ;bitpos:[20:11] ;default: 10'h60 ; */ +/*description: */ +#define RMT_APB_MEM_WADDR_CH2 0x000003FF +#define RMT_APB_MEM_WADDR_CH2_M ((RMT_APB_MEM_WADDR_CH2_V) << (RMT_APB_MEM_WADDR_CH2_S)) +#define RMT_APB_MEM_WADDR_CH2_V 0x3FF +#define RMT_APB_MEM_WADDR_CH2_S 11 +/* RMT_MEM_RADDR_EX_CH2 : RO ;bitpos:[9:0] ;default: 10'h60 ; */ +/*description: */ +#define RMT_MEM_RADDR_EX_CH2 0x000003FF +#define RMT_MEM_RADDR_EX_CH2_M ((RMT_MEM_RADDR_EX_CH2_V) << (RMT_MEM_RADDR_EX_CH2_S)) +#define RMT_MEM_RADDR_EX_CH2_V 0x3FF +#define RMT_MEM_RADDR_EX_CH2_S 0 + +#define RMT_CH3STATUS_REG (DR_REG_RMT_BASE + 0x005c) +/* RMT_APB_MEM_WR_ERR_CH3 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_WR_ERR_CH3 (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH3_M (BIT(26)) +#define RMT_APB_MEM_WR_ERR_CH3_V 0x1 +#define RMT_APB_MEM_WR_ERR_CH3_S 26 +/* RMT_MEM_EMPTY_CH3 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_EMPTY_CH3 (BIT(25)) +#define RMT_MEM_EMPTY_CH3_M (BIT(25)) +#define RMT_MEM_EMPTY_CH3_V 0x1 +#define RMT_MEM_EMPTY_CH3_S 25 +/* RMT_STATE_CH3 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH3 0x00000007 +#define RMT_STATE_CH3_M ((RMT_STATE_CH3_V) << (RMT_STATE_CH3_S)) +#define RMT_STATE_CH3_V 0x7 +#define RMT_STATE_CH3_S 22 +/* RMT_APB_MEM_WADDR_CH3 : RO ;bitpos:[20:11] ;default: 10'h90 ; */ +/*description: */ +#define RMT_APB_MEM_WADDR_CH3 0x000003FF +#define RMT_APB_MEM_WADDR_CH3_M ((RMT_APB_MEM_WADDR_CH3_V) << (RMT_APB_MEM_WADDR_CH3_S)) +#define RMT_APB_MEM_WADDR_CH3_V 0x3FF +#define RMT_APB_MEM_WADDR_CH3_S 11 +/* RMT_MEM_RADDR_EX_CH3 : RO ;bitpos:[9:0] ;default: 10'h90 ; */ +/*description: */ +#define RMT_MEM_RADDR_EX_CH3 0x000003FF +#define RMT_MEM_RADDR_EX_CH3_M ((RMT_MEM_RADDR_EX_CH3_V) << (RMT_MEM_RADDR_EX_CH3_S)) +#define RMT_MEM_RADDR_EX_CH3_V 0x3FF +#define RMT_MEM_RADDR_EX_CH3_S 0 + +#define RMT_CH4STATUS_REG (DR_REG_RMT_BASE + 0x0060) +/* RMT_APB_MEM_RD_ERR_CH4 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH4 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH4_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH4_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH4_S 27 +/* RMT_MEM_FULL_CH4 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FULL_CH4 (BIT(26)) +#define RMT_MEM_FULL_CH4_M (BIT(26)) +#define RMT_MEM_FULL_CH4_V 0x1 +#define RMT_MEM_FULL_CH4_S 26 +/* RMT_MEM_OWNER_ERR_CH4 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_OWNER_ERR_CH4 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH4_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH4_V 0x1 +#define RMT_MEM_OWNER_ERR_CH4_S 25 +/* RMT_STATE_CH4 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH4 0x00000007 +#define RMT_STATE_CH4_M ((RMT_STATE_CH4_V) << (RMT_STATE_CH4_S)) +#define RMT_STATE_CH4_V 0x7 +#define RMT_STATE_CH4_S 22 +/* RMT_APB_MEM_RADDR_CH4 : RO ;bitpos:[20:11] ;default: 10'hc0 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH4 0x000003FF +#define RMT_APB_MEM_RADDR_CH4_M ((RMT_APB_MEM_RADDR_CH4_V) << (RMT_APB_MEM_RADDR_CH4_S)) +#define RMT_APB_MEM_RADDR_CH4_V 0x3FF +#define RMT_APB_MEM_RADDR_CH4_S 11 +/* RMT_MEM_WADDR_EX_CH4 : RO ;bitpos:[9:0] ;default: 10'hc0 ; */ +/*description: */ +#define RMT_MEM_WADDR_EX_CH4 0x000003FF +#define RMT_MEM_WADDR_EX_CH4_M ((RMT_MEM_WADDR_EX_CH4_V) << (RMT_MEM_WADDR_EX_CH4_S)) +#define RMT_MEM_WADDR_EX_CH4_V 0x3FF +#define RMT_MEM_WADDR_EX_CH4_S 0 + +#define RMT_CH5STATUS_REG (DR_REG_RMT_BASE + 0x0064) +/* RMT_APB_MEM_RD_ERR_CH5 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH5 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH5_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH5_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH5_S 27 +/* RMT_MEM_FULL_CH5 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FULL_CH5 (BIT(26)) +#define RMT_MEM_FULL_CH5_M (BIT(26)) +#define RMT_MEM_FULL_CH5_V 0x1 +#define RMT_MEM_FULL_CH5_S 26 +/* RMT_MEM_OWNER_ERR_CH5 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_OWNER_ERR_CH5 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH5_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH5_V 0x1 +#define RMT_MEM_OWNER_ERR_CH5_S 25 +/* RMT_STATE_CH5 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH5 0x00000007 +#define RMT_STATE_CH5_M ((RMT_STATE_CH5_V) << (RMT_STATE_CH5_S)) +#define RMT_STATE_CH5_V 0x7 +#define RMT_STATE_CH5_S 22 +/* RMT_APB_MEM_RADDR_CH5 : RO ;bitpos:[20:11] ;default: 10'hf0 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH5 0x000003FF +#define RMT_APB_MEM_RADDR_CH5_M ((RMT_APB_MEM_RADDR_CH5_V) << (RMT_APB_MEM_RADDR_CH5_S)) +#define RMT_APB_MEM_RADDR_CH5_V 0x3FF +#define RMT_APB_MEM_RADDR_CH5_S 11 +/* RMT_MEM_WADDR_EX_CH5 : RO ;bitpos:[9:0] ;default: 10'hf0 ; */ +/*description: */ +#define RMT_MEM_WADDR_EX_CH5 0x000003FF +#define RMT_MEM_WADDR_EX_CH5_M ((RMT_MEM_WADDR_EX_CH5_V) << (RMT_MEM_WADDR_EX_CH5_S)) +#define RMT_MEM_WADDR_EX_CH5_V 0x3FF +#define RMT_MEM_WADDR_EX_CH5_S 0 + +#define RMT_CH6STATUS_REG (DR_REG_RMT_BASE + 0x0068) +/* RMT_APB_MEM_RD_ERR_CH6 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH6 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH6_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH6_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH6_S 27 +/* RMT_MEM_FULL_CH6 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FULL_CH6 (BIT(26)) +#define RMT_MEM_FULL_CH6_M (BIT(26)) +#define RMT_MEM_FULL_CH6_V 0x1 +#define RMT_MEM_FULL_CH6_S 26 +/* RMT_MEM_OWNER_ERR_CH6 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_OWNER_ERR_CH6 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH6_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH6_V 0x1 +#define RMT_MEM_OWNER_ERR_CH6_S 25 +/* RMT_STATE_CH6 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH6 0x00000007 +#define RMT_STATE_CH6_M ((RMT_STATE_CH6_V) << (RMT_STATE_CH6_S)) +#define RMT_STATE_CH6_V 0x7 +#define RMT_STATE_CH6_S 22 +/* RMT_APB_MEM_RADDR_CH6 : RO ;bitpos:[20:11] ;default: 10'h120 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH6 0x000003FF +#define RMT_APB_MEM_RADDR_CH6_M ((RMT_APB_MEM_RADDR_CH6_V) << (RMT_APB_MEM_RADDR_CH6_S)) +#define RMT_APB_MEM_RADDR_CH6_V 0x3FF +#define RMT_APB_MEM_RADDR_CH6_S 11 +/* RMT_MEM_WADDR_EX_CH6 : RO ;bitpos:[9:0] ;default: 10'h120 ; */ +/*description: */ +#define RMT_MEM_WADDR_EX_CH6 0x000003FF +#define RMT_MEM_WADDR_EX_CH6_M ((RMT_MEM_WADDR_EX_CH6_V) << (RMT_MEM_WADDR_EX_CH6_S)) +#define RMT_MEM_WADDR_EX_CH6_V 0x3FF +#define RMT_MEM_WADDR_EX_CH6_S 0 + +#define RMT_CH7STATUS_REG (DR_REG_RMT_BASE + 0x006c) +/* RMT_APB_MEM_RD_ERR_CH7 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_APB_MEM_RD_ERR_CH7 (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH7_M (BIT(27)) +#define RMT_APB_MEM_RD_ERR_CH7_V 0x1 +#define RMT_APB_MEM_RD_ERR_CH7_S 27 +/* RMT_MEM_FULL_CH7 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FULL_CH7 (BIT(26)) +#define RMT_MEM_FULL_CH7_M (BIT(26)) +#define RMT_MEM_FULL_CH7_V 0x1 +#define RMT_MEM_FULL_CH7_S 26 +/* RMT_MEM_OWNER_ERR_CH7 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_OWNER_ERR_CH7 (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH7_M (BIT(25)) +#define RMT_MEM_OWNER_ERR_CH7_V 0x1 +#define RMT_MEM_OWNER_ERR_CH7_S 25 +/* RMT_STATE_CH7 : RO ;bitpos:[24:22] ;default: 3'b0 ; */ +/*description: */ +#define RMT_STATE_CH7 0x00000007 +#define RMT_STATE_CH7_M ((RMT_STATE_CH7_V) << (RMT_STATE_CH7_S)) +#define RMT_STATE_CH7_V 0x7 +#define RMT_STATE_CH7_S 22 +/* RMT_APB_MEM_RADDR_CH7 : RO ;bitpos:[20:11] ;default: 10'h150 ; */ +/*description: */ +#define RMT_APB_MEM_RADDR_CH7 0x000003FF +#define RMT_APB_MEM_RADDR_CH7_M ((RMT_APB_MEM_RADDR_CH7_V) << (RMT_APB_MEM_RADDR_CH7_S)) +#define RMT_APB_MEM_RADDR_CH7_V 0x3FF +#define RMT_APB_MEM_RADDR_CH7_S 11 +/* RMT_MEM_WADDR_EX_CH7 : RO ;bitpos:[9:0] ;default: 10'h150 ; */ +/*description: */ +#define RMT_MEM_WADDR_EX_CH7 0x000003FF +#define RMT_MEM_WADDR_EX_CH7_M ((RMT_MEM_WADDR_EX_CH7_V) << (RMT_MEM_WADDR_EX_CH7_S)) +#define RMT_MEM_WADDR_EX_CH7_V 0x3FF +#define RMT_MEM_WADDR_EX_CH7_S 0 + +#define RMT_INT_RAW_REG (DR_REG_RMT_BASE + 0x0070) +/* RMT_CH7_RX_THR_EVENT_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_THR_EVENT_INT_RAW (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_RAW_S 27 +/* RMT_CH6_RX_THR_EVENT_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_THR_EVENT_INT_RAW (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_RAW_S 26 +/* RMT_CH5_RX_THR_EVENT_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_THR_EVENT_INT_RAW (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_RAW_S 25 +/* RMT_CH4_RX_THR_EVENT_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_THR_EVENT_INT_RAW (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_RAW_S 24 +/* RMT_CH7_ERR_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_ERR_INT_RAW (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_M (BIT(23)) +#define RMT_CH7_ERR_INT_RAW_V 0x1 +#define RMT_CH7_ERR_INT_RAW_S 23 +/* RMT_CH6_ERR_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_ERR_INT_RAW (BIT(22)) +#define RMT_CH6_ERR_INT_RAW_M (BIT(22)) +#define RMT_CH6_ERR_INT_RAW_V 0x1 +#define RMT_CH6_ERR_INT_RAW_S 22 +/* RMT_CH5_ERR_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_ERR_INT_RAW (BIT(21)) +#define RMT_CH5_ERR_INT_RAW_M (BIT(21)) +#define RMT_CH5_ERR_INT_RAW_V 0x1 +#define RMT_CH5_ERR_INT_RAW_S 21 +/* RMT_CH4_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_ERR_INT_RAW (BIT(20)) +#define RMT_CH4_ERR_INT_RAW_M (BIT(20)) +#define RMT_CH4_ERR_INT_RAW_V 0x1 +#define RMT_CH4_ERR_INT_RAW_S 20 +/* RMT_CH7_RX_END_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_END_INT_RAW (BIT(19)) +#define RMT_CH7_RX_END_INT_RAW_M (BIT(19)) +#define RMT_CH7_RX_END_INT_RAW_V 0x1 +#define RMT_CH7_RX_END_INT_RAW_S 19 +/* RMT_CH6_RX_END_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_END_INT_RAW (BIT(18)) +#define RMT_CH6_RX_END_INT_RAW_M (BIT(18)) +#define RMT_CH6_RX_END_INT_RAW_V 0x1 +#define RMT_CH6_RX_END_INT_RAW_S 18 +/* RMT_CH5_RX_END_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_END_INT_RAW (BIT(17)) +#define RMT_CH5_RX_END_INT_RAW_M (BIT(17)) +#define RMT_CH5_RX_END_INT_RAW_V 0x1 +#define RMT_CH5_RX_END_INT_RAW_S 17 +/* RMT_CH4_RX_END_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_END_INT_RAW (BIT(16)) +#define RMT_CH4_RX_END_INT_RAW_M (BIT(16)) +#define RMT_CH4_RX_END_INT_RAW_V 0x1 +#define RMT_CH4_RX_END_INT_RAW_S 16 +/* RMT_CH3_TX_LOOP_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_LOOP_INT_RAW (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_RAW_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH3_TX_LOOP_INT_RAW_S 15 +/* RMT_CH2_TX_LOOP_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_LOOP_INT_RAW (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_RAW_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH2_TX_LOOP_INT_RAW_S 14 +/* RMT_CH1_TX_LOOP_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_RAW (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH1_TX_LOOP_INT_RAW_S 13 +/* RMT_CH0_TX_LOOP_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_RAW (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_RAW_V 0x1 +#define RMT_CH0_TX_LOOP_INT_RAW_S 12 +/* RMT_CH3_TX_THR_EVENT_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_THR_EVENT_INT_RAW (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_RAW_S 11 +/* RMT_CH2_TX_THR_EVENT_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_THR_EVENT_INT_RAW (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_RAW_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_RAW (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_RAW_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_RAW (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_RAW_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_RAW_S 8 +/* RMT_CH3_ERR_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_RAW (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_M (BIT(7)) +#define RMT_CH3_ERR_INT_RAW_V 0x1 +#define RMT_CH3_ERR_INT_RAW_S 7 +/* RMT_CH2_ERR_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_RAW (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_M (BIT(6)) +#define RMT_CH2_ERR_INT_RAW_V 0x1 +#define RMT_CH2_ERR_INT_RAW_S 6 +/* RMT_CH1_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_RAW (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_M (BIT(5)) +#define RMT_CH1_ERR_INT_RAW_V 0x1 +#define RMT_CH1_ERR_INT_RAW_S 5 +/* RMT_CH0_ERR_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_RAW (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_M (BIT(4)) +#define RMT_CH0_ERR_INT_RAW_V 0x1 +#define RMT_CH0_ERR_INT_RAW_S 4 +/* RMT_CH3_TX_END_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_END_INT_RAW (BIT(3)) +#define RMT_CH3_TX_END_INT_RAW_M (BIT(3)) +#define RMT_CH3_TX_END_INT_RAW_V 0x1 +#define RMT_CH3_TX_END_INT_RAW_S 3 +/* RMT_CH2_TX_END_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_END_INT_RAW (BIT(2)) +#define RMT_CH2_TX_END_INT_RAW_M (BIT(2)) +#define RMT_CH2_TX_END_INT_RAW_V 0x1 +#define RMT_CH2_TX_END_INT_RAW_S 2 +/* RMT_CH1_TX_END_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_RAW (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_M (BIT(1)) +#define RMT_CH1_TX_END_INT_RAW_V 0x1 +#define RMT_CH1_TX_END_INT_RAW_S 1 +/* RMT_CH0_TX_END_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_RAW (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_M (BIT(0)) +#define RMT_CH0_TX_END_INT_RAW_V 0x1 +#define RMT_CH0_TX_END_INT_RAW_S 0 + +#define RMT_INT_ST_REG (DR_REG_RMT_BASE + 0x0074) +/* RMT_CH7_RX_THR_EVENT_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_THR_EVENT_INT_ST (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ST_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_ST_S 27 +/* RMT_CH6_RX_THR_EVENT_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_THR_EVENT_INT_ST (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ST_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_ST_S 26 +/* RMT_CH5_RX_THR_EVENT_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_THR_EVENT_INT_ST (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ST_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_ST_S 25 +/* RMT_CH4_RX_THR_EVENT_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_THR_EVENT_INT_ST (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ST_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_ST_S 24 +/* RMT_CH7_ERR_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_ERR_INT_ST (BIT(23)) +#define RMT_CH7_ERR_INT_ST_M (BIT(23)) +#define RMT_CH7_ERR_INT_ST_V 0x1 +#define RMT_CH7_ERR_INT_ST_S 23 +/* RMT_CH6_ERR_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_ERR_INT_ST (BIT(22)) +#define RMT_CH6_ERR_INT_ST_M (BIT(22)) +#define RMT_CH6_ERR_INT_ST_V 0x1 +#define RMT_CH6_ERR_INT_ST_S 22 +/* RMT_CH5_ERR_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_ERR_INT_ST (BIT(21)) +#define RMT_CH5_ERR_INT_ST_M (BIT(21)) +#define RMT_CH5_ERR_INT_ST_V 0x1 +#define RMT_CH5_ERR_INT_ST_S 21 +/* RMT_CH4_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_ERR_INT_ST (BIT(20)) +#define RMT_CH4_ERR_INT_ST_M (BIT(20)) +#define RMT_CH4_ERR_INT_ST_V 0x1 +#define RMT_CH4_ERR_INT_ST_S 20 +/* RMT_CH7_RX_END_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_END_INT_ST (BIT(19)) +#define RMT_CH7_RX_END_INT_ST_M (BIT(19)) +#define RMT_CH7_RX_END_INT_ST_V 0x1 +#define RMT_CH7_RX_END_INT_ST_S 19 +/* RMT_CH6_RX_END_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_END_INT_ST (BIT(18)) +#define RMT_CH6_RX_END_INT_ST_M (BIT(18)) +#define RMT_CH6_RX_END_INT_ST_V 0x1 +#define RMT_CH6_RX_END_INT_ST_S 18 +/* RMT_CH5_RX_END_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_END_INT_ST (BIT(17)) +#define RMT_CH5_RX_END_INT_ST_M (BIT(17)) +#define RMT_CH5_RX_END_INT_ST_V 0x1 +#define RMT_CH5_RX_END_INT_ST_S 17 +/* RMT_CH4_RX_END_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_END_INT_ST (BIT(16)) +#define RMT_CH4_RX_END_INT_ST_M (BIT(16)) +#define RMT_CH4_RX_END_INT_ST_V 0x1 +#define RMT_CH4_RX_END_INT_ST_S 16 +/* RMT_CH3_TX_LOOP_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_LOOP_INT_ST (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ST_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH3_TX_LOOP_INT_ST_S 15 +/* RMT_CH2_TX_LOOP_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_LOOP_INT_ST (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ST_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH2_TX_LOOP_INT_ST_S 14 +/* RMT_CH1_TX_LOOP_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_ST (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH1_TX_LOOP_INT_ST_S 13 +/* RMT_CH0_TX_LOOP_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_ST (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ST_V 0x1 +#define RMT_CH0_TX_LOOP_INT_ST_S 12 +/* RMT_CH3_TX_THR_EVENT_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_THR_EVENT_INT_ST (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ST_S 11 +/* RMT_CH2_TX_THR_EVENT_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_THR_EVENT_INT_ST (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ST_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_ST (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ST_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_ST (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ST_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ST_S 8 +/* RMT_CH3_ERR_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_ST (BIT(7)) +#define RMT_CH3_ERR_INT_ST_M (BIT(7)) +#define RMT_CH3_ERR_INT_ST_V 0x1 +#define RMT_CH3_ERR_INT_ST_S 7 +/* RMT_CH2_ERR_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_ST (BIT(6)) +#define RMT_CH2_ERR_INT_ST_M (BIT(6)) +#define RMT_CH2_ERR_INT_ST_V 0x1 +#define RMT_CH2_ERR_INT_ST_S 6 +/* RMT_CH1_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_ST (BIT(5)) +#define RMT_CH1_ERR_INT_ST_M (BIT(5)) +#define RMT_CH1_ERR_INT_ST_V 0x1 +#define RMT_CH1_ERR_INT_ST_S 5 +/* RMT_CH0_ERR_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_ST (BIT(4)) +#define RMT_CH0_ERR_INT_ST_M (BIT(4)) +#define RMT_CH0_ERR_INT_ST_V 0x1 +#define RMT_CH0_ERR_INT_ST_S 4 +/* RMT_CH3_TX_END_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_END_INT_ST (BIT(3)) +#define RMT_CH3_TX_END_INT_ST_M (BIT(3)) +#define RMT_CH3_TX_END_INT_ST_V 0x1 +#define RMT_CH3_TX_END_INT_ST_S 3 +/* RMT_CH2_TX_END_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_END_INT_ST (BIT(2)) +#define RMT_CH2_TX_END_INT_ST_M (BIT(2)) +#define RMT_CH2_TX_END_INT_ST_V 0x1 +#define RMT_CH2_TX_END_INT_ST_S 2 +/* RMT_CH1_TX_END_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_ST (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_M (BIT(1)) +#define RMT_CH1_TX_END_INT_ST_V 0x1 +#define RMT_CH1_TX_END_INT_ST_S 1 +/* RMT_CH0_TX_END_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_ST (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ST_V 0x1 +#define RMT_CH0_TX_END_INT_ST_S 0 + +#define RMT_INT_ENA_REG (DR_REG_RMT_BASE + 0x0078) +/* RMT_CH7_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_THR_EVENT_INT_ENA (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_ENA_S 27 +/* RMT_CH6_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_THR_EVENT_INT_ENA (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_ENA_S 26 +/* RMT_CH5_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_THR_EVENT_INT_ENA (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_ENA_S 25 +/* RMT_CH4_RX_THR_EVENT_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_THR_EVENT_INT_ENA (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_ENA_S 24 +/* RMT_CH7_ERR_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_ERR_INT_ENA (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_M (BIT(23)) +#define RMT_CH7_ERR_INT_ENA_V 0x1 +#define RMT_CH7_ERR_INT_ENA_S 23 +/* RMT_CH6_ERR_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_ERR_INT_ENA (BIT(22)) +#define RMT_CH6_ERR_INT_ENA_M (BIT(22)) +#define RMT_CH6_ERR_INT_ENA_V 0x1 +#define RMT_CH6_ERR_INT_ENA_S 22 +/* RMT_CH5_ERR_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_ERR_INT_ENA (BIT(21)) +#define RMT_CH5_ERR_INT_ENA_M (BIT(21)) +#define RMT_CH5_ERR_INT_ENA_V 0x1 +#define RMT_CH5_ERR_INT_ENA_S 21 +/* RMT_CH4_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_ERR_INT_ENA (BIT(20)) +#define RMT_CH4_ERR_INT_ENA_M (BIT(20)) +#define RMT_CH4_ERR_INT_ENA_V 0x1 +#define RMT_CH4_ERR_INT_ENA_S 20 +/* RMT_CH7_RX_END_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_END_INT_ENA (BIT(19)) +#define RMT_CH7_RX_END_INT_ENA_M (BIT(19)) +#define RMT_CH7_RX_END_INT_ENA_V 0x1 +#define RMT_CH7_RX_END_INT_ENA_S 19 +/* RMT_CH6_RX_END_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_END_INT_ENA (BIT(18)) +#define RMT_CH6_RX_END_INT_ENA_M (BIT(18)) +#define RMT_CH6_RX_END_INT_ENA_V 0x1 +#define RMT_CH6_RX_END_INT_ENA_S 18 +/* RMT_CH5_RX_END_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_END_INT_ENA (BIT(17)) +#define RMT_CH5_RX_END_INT_ENA_M (BIT(17)) +#define RMT_CH5_RX_END_INT_ENA_V 0x1 +#define RMT_CH5_RX_END_INT_ENA_S 17 +/* RMT_CH4_RX_END_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_END_INT_ENA (BIT(16)) +#define RMT_CH4_RX_END_INT_ENA_M (BIT(16)) +#define RMT_CH4_RX_END_INT_ENA_V 0x1 +#define RMT_CH4_RX_END_INT_ENA_S 16 +/* RMT_CH3_TX_LOOP_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_LOOP_INT_ENA (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ENA_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH3_TX_LOOP_INT_ENA_S 15 +/* RMT_CH2_TX_LOOP_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_LOOP_INT_ENA (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ENA_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH2_TX_LOOP_INT_ENA_S 14 +/* RMT_CH1_TX_LOOP_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_ENA (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH1_TX_LOOP_INT_ENA_S 13 +/* RMT_CH0_TX_LOOP_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_ENA (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_ENA_V 0x1 +#define RMT_CH0_TX_LOOP_INT_ENA_S 12 +/* RMT_CH3_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_THR_EVENT_INT_ENA (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_ENA_S 11 +/* RMT_CH2_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_THR_EVENT_INT_ENA (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_ENA_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_ENA (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_ENA_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_ENA (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_ENA_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_ENA_S 8 +/* RMT_CH3_ERR_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_ENA (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_M (BIT(7)) +#define RMT_CH3_ERR_INT_ENA_V 0x1 +#define RMT_CH3_ERR_INT_ENA_S 7 +/* RMT_CH2_ERR_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_ENA (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_M (BIT(6)) +#define RMT_CH2_ERR_INT_ENA_V 0x1 +#define RMT_CH2_ERR_INT_ENA_S 6 +/* RMT_CH1_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_ENA (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_M (BIT(5)) +#define RMT_CH1_ERR_INT_ENA_V 0x1 +#define RMT_CH1_ERR_INT_ENA_S 5 +/* RMT_CH0_ERR_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_ENA (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_M (BIT(4)) +#define RMT_CH0_ERR_INT_ENA_V 0x1 +#define RMT_CH0_ERR_INT_ENA_S 4 +/* RMT_CH3_TX_END_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_END_INT_ENA (BIT(3)) +#define RMT_CH3_TX_END_INT_ENA_M (BIT(3)) +#define RMT_CH3_TX_END_INT_ENA_V 0x1 +#define RMT_CH3_TX_END_INT_ENA_S 3 +/* RMT_CH2_TX_END_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_END_INT_ENA (BIT(2)) +#define RMT_CH2_TX_END_INT_ENA_M (BIT(2)) +#define RMT_CH2_TX_END_INT_ENA_V 0x1 +#define RMT_CH2_TX_END_INT_ENA_S 2 +/* RMT_CH1_TX_END_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_ENA (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_M (BIT(1)) +#define RMT_CH1_TX_END_INT_ENA_V 0x1 +#define RMT_CH1_TX_END_INT_ENA_S 1 +/* RMT_CH0_TX_END_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_ENA (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_M (BIT(0)) +#define RMT_CH0_TX_END_INT_ENA_V 0x1 +#define RMT_CH0_TX_END_INT_ENA_S 0 + +#define RMT_INT_CLR_REG (DR_REG_RMT_BASE + 0x007c) +/* RMT_CH7_RX_THR_EVENT_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_THR_EVENT_INT_CLR (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_M (BIT(27)) +#define RMT_CH7_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH7_RX_THR_EVENT_INT_CLR_S 27 +/* RMT_CH6_RX_THR_EVENT_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_THR_EVENT_INT_CLR (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_M (BIT(26)) +#define RMT_CH6_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH6_RX_THR_EVENT_INT_CLR_S 26 +/* RMT_CH5_RX_THR_EVENT_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_THR_EVENT_INT_CLR (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_M (BIT(25)) +#define RMT_CH5_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH5_RX_THR_EVENT_INT_CLR_S 25 +/* RMT_CH4_RX_THR_EVENT_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_THR_EVENT_INT_CLR (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_M (BIT(24)) +#define RMT_CH4_RX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH4_RX_THR_EVENT_INT_CLR_S 24 +/* RMT_CH7_ERR_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_ERR_INT_CLR (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_M (BIT(23)) +#define RMT_CH7_ERR_INT_CLR_V 0x1 +#define RMT_CH7_ERR_INT_CLR_S 23 +/* RMT_CH6_ERR_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_ERR_INT_CLR (BIT(22)) +#define RMT_CH6_ERR_INT_CLR_M (BIT(22)) +#define RMT_CH6_ERR_INT_CLR_V 0x1 +#define RMT_CH6_ERR_INT_CLR_S 22 +/* RMT_CH5_ERR_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_ERR_INT_CLR (BIT(21)) +#define RMT_CH5_ERR_INT_CLR_M (BIT(21)) +#define RMT_CH5_ERR_INT_CLR_V 0x1 +#define RMT_CH5_ERR_INT_CLR_S 21 +/* RMT_CH4_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_ERR_INT_CLR (BIT(20)) +#define RMT_CH4_ERR_INT_CLR_M (BIT(20)) +#define RMT_CH4_ERR_INT_CLR_V 0x1 +#define RMT_CH4_ERR_INT_CLR_S 20 +/* RMT_CH7_RX_END_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH7_RX_END_INT_CLR (BIT(19)) +#define RMT_CH7_RX_END_INT_CLR_M (BIT(19)) +#define RMT_CH7_RX_END_INT_CLR_V 0x1 +#define RMT_CH7_RX_END_INT_CLR_S 19 +/* RMT_CH6_RX_END_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH6_RX_END_INT_CLR (BIT(18)) +#define RMT_CH6_RX_END_INT_CLR_M (BIT(18)) +#define RMT_CH6_RX_END_INT_CLR_V 0x1 +#define RMT_CH6_RX_END_INT_CLR_S 18 +/* RMT_CH5_RX_END_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH5_RX_END_INT_CLR (BIT(17)) +#define RMT_CH5_RX_END_INT_CLR_M (BIT(17)) +#define RMT_CH5_RX_END_INT_CLR_V 0x1 +#define RMT_CH5_RX_END_INT_CLR_S 17 +/* RMT_CH4_RX_END_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH4_RX_END_INT_CLR (BIT(16)) +#define RMT_CH4_RX_END_INT_CLR_M (BIT(16)) +#define RMT_CH4_RX_END_INT_CLR_V 0x1 +#define RMT_CH4_RX_END_INT_CLR_S 16 +/* RMT_CH3_TX_LOOP_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_LOOP_INT_CLR (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_CLR_M (BIT(15)) +#define RMT_CH3_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH3_TX_LOOP_INT_CLR_S 15 +/* RMT_CH2_TX_LOOP_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_LOOP_INT_CLR (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_CLR_M (BIT(14)) +#define RMT_CH2_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH2_TX_LOOP_INT_CLR_S 14 +/* RMT_CH1_TX_LOOP_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_LOOP_INT_CLR (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_M (BIT(13)) +#define RMT_CH1_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH1_TX_LOOP_INT_CLR_S 13 +/* RMT_CH0_TX_LOOP_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_LOOP_INT_CLR (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_M (BIT(12)) +#define RMT_CH0_TX_LOOP_INT_CLR_V 0x1 +#define RMT_CH0_TX_LOOP_INT_CLR_S 12 +/* RMT_CH3_TX_THR_EVENT_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_THR_EVENT_INT_CLR (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_M (BIT(11)) +#define RMT_CH3_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH3_TX_THR_EVENT_INT_CLR_S 11 +/* RMT_CH2_TX_THR_EVENT_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_THR_EVENT_INT_CLR (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_M (BIT(10)) +#define RMT_CH2_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH2_TX_THR_EVENT_INT_CLR_S 10 +/* RMT_CH1_TX_THR_EVENT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_THR_EVENT_INT_CLR (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_M (BIT(9)) +#define RMT_CH1_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH1_TX_THR_EVENT_INT_CLR_S 9 +/* RMT_CH0_TX_THR_EVENT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_THR_EVENT_INT_CLR (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_M (BIT(8)) +#define RMT_CH0_TX_THR_EVENT_INT_CLR_V 0x1 +#define RMT_CH0_TX_THR_EVENT_INT_CLR_S 8 +/* RMT_CH3_ERR_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_ERR_INT_CLR (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_M (BIT(7)) +#define RMT_CH3_ERR_INT_CLR_V 0x1 +#define RMT_CH3_ERR_INT_CLR_S 7 +/* RMT_CH2_ERR_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_ERR_INT_CLR (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_M (BIT(6)) +#define RMT_CH2_ERR_INT_CLR_V 0x1 +#define RMT_CH2_ERR_INT_CLR_S 6 +/* RMT_CH1_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_ERR_INT_CLR (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_M (BIT(5)) +#define RMT_CH1_ERR_INT_CLR_V 0x1 +#define RMT_CH1_ERR_INT_CLR_S 5 +/* RMT_CH0_ERR_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_ERR_INT_CLR (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_M (BIT(4)) +#define RMT_CH0_ERR_INT_CLR_V 0x1 +#define RMT_CH0_ERR_INT_CLR_S 4 +/* RMT_CH3_TX_END_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH3_TX_END_INT_CLR (BIT(3)) +#define RMT_CH3_TX_END_INT_CLR_M (BIT(3)) +#define RMT_CH3_TX_END_INT_CLR_V 0x1 +#define RMT_CH3_TX_END_INT_CLR_S 3 +/* RMT_CH2_TX_END_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH2_TX_END_INT_CLR (BIT(2)) +#define RMT_CH2_TX_END_INT_CLR_M (BIT(2)) +#define RMT_CH2_TX_END_INT_CLR_V 0x1 +#define RMT_CH2_TX_END_INT_CLR_S 2 +/* RMT_CH1_TX_END_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH1_TX_END_INT_CLR (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_M (BIT(1)) +#define RMT_CH1_TX_END_INT_CLR_V 0x1 +#define RMT_CH1_TX_END_INT_CLR_S 1 +/* RMT_CH0_TX_END_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_CH0_TX_END_INT_CLR (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_M (BIT(0)) +#define RMT_CH0_TX_END_INT_CLR_V 0x1 +#define RMT_CH0_TX_END_INT_CLR_S 0 + +#define RMT_CH0CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0080) +/* RMT_CARRIER_HIGH_CH0 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_CH0 0x0000FFFF +#define RMT_CARRIER_HIGH_CH0_M ((RMT_CARRIER_HIGH_CH0_V) << (RMT_CARRIER_HIGH_CH0_S)) +#define RMT_CARRIER_HIGH_CH0_V 0xFFFF +#define RMT_CARRIER_HIGH_CH0_S 16 +/* RMT_CARRIER_LOW_CH0 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_LOW_CH0 0x0000FFFF +#define RMT_CARRIER_LOW_CH0_M ((RMT_CARRIER_LOW_CH0_V) << (RMT_CARRIER_LOW_CH0_S)) +#define RMT_CARRIER_LOW_CH0_V 0xFFFF +#define RMT_CARRIER_LOW_CH0_S 0 + +#define RMT_CH1CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0084) +/* RMT_CARRIER_HIGH_CH1 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_CH1 0x0000FFFF +#define RMT_CARRIER_HIGH_CH1_M ((RMT_CARRIER_HIGH_CH1_V) << (RMT_CARRIER_HIGH_CH1_S)) +#define RMT_CARRIER_HIGH_CH1_V 0xFFFF +#define RMT_CARRIER_HIGH_CH1_S 16 +/* RMT_CARRIER_LOW_CH1 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_LOW_CH1 0x0000FFFF +#define RMT_CARRIER_LOW_CH1_M ((RMT_CARRIER_LOW_CH1_V) << (RMT_CARRIER_LOW_CH1_S)) +#define RMT_CARRIER_LOW_CH1_V 0xFFFF +#define RMT_CARRIER_LOW_CH1_S 0 + +#define RMT_CH2CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x0088) +/* RMT_CARRIER_HIGH_CH2 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_CH2 0x0000FFFF +#define RMT_CARRIER_HIGH_CH2_M ((RMT_CARRIER_HIGH_CH2_V) << (RMT_CARRIER_HIGH_CH2_S)) +#define RMT_CARRIER_HIGH_CH2_V 0xFFFF +#define RMT_CARRIER_HIGH_CH2_S 16 +/* RMT_CARRIER_LOW_CH2 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_LOW_CH2 0x0000FFFF +#define RMT_CARRIER_LOW_CH2_M ((RMT_CARRIER_LOW_CH2_V) << (RMT_CARRIER_LOW_CH2_S)) +#define RMT_CARRIER_LOW_CH2_V 0xFFFF +#define RMT_CARRIER_LOW_CH2_S 0 + +#define RMT_CH3CARRIER_DUTY_REG (DR_REG_RMT_BASE + 0x008c) +/* RMT_CARRIER_HIGH_CH3 : R/W ;bitpos:[31:16] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_CH3 0x0000FFFF +#define RMT_CARRIER_HIGH_CH3_M ((RMT_CARRIER_HIGH_CH3_V) << (RMT_CARRIER_HIGH_CH3_S)) +#define RMT_CARRIER_HIGH_CH3_V 0xFFFF +#define RMT_CARRIER_HIGH_CH3_S 16 +/* RMT_CARRIER_LOW_CH3 : R/W ;bitpos:[15:0] ;default: 16'h40 ; */ +/*description: */ +#define RMT_CARRIER_LOW_CH3 0x0000FFFF +#define RMT_CARRIER_LOW_CH3_M ((RMT_CARRIER_LOW_CH3_V) << (RMT_CARRIER_LOW_CH3_S)) +#define RMT_CARRIER_LOW_CH3_V 0xFFFF +#define RMT_CARRIER_LOW_CH3_S 0 + +#define RMT_CH4_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0090) +/* RMT_CARRIER_HIGH_THRES_CH4 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH4 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH4_M ((RMT_CARRIER_HIGH_THRES_CH4_V) << (RMT_CARRIER_HIGH_THRES_CH4_S)) +#define RMT_CARRIER_HIGH_THRES_CH4_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH4_S 16 +/* RMT_CARRIER_LOW_THRES_CH4 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH4 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH4_M ((RMT_CARRIER_LOW_THRES_CH4_V) << (RMT_CARRIER_LOW_THRES_CH4_S)) +#define RMT_CARRIER_LOW_THRES_CH4_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH4_S 0 + +#define RMT_CH5_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0094) +/* RMT_CARRIER_HIGH_THRES_CH5 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH5 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH5_M ((RMT_CARRIER_HIGH_THRES_CH5_V) << (RMT_CARRIER_HIGH_THRES_CH5_S)) +#define RMT_CARRIER_HIGH_THRES_CH5_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH5_S 16 +/* RMT_CARRIER_LOW_THRES_CH5 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH5 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH5_M ((RMT_CARRIER_LOW_THRES_CH5_V) << (RMT_CARRIER_LOW_THRES_CH5_S)) +#define RMT_CARRIER_LOW_THRES_CH5_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH5_S 0 + +#define RMT_CH6_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x0098) +/* RMT_CARRIER_HIGH_THRES_CH6 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH6 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH6_M ((RMT_CARRIER_HIGH_THRES_CH6_V) << (RMT_CARRIER_HIGH_THRES_CH6_S)) +#define RMT_CARRIER_HIGH_THRES_CH6_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH6_S 16 +/* RMT_CARRIER_LOW_THRES_CH6 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH6 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH6_M ((RMT_CARRIER_LOW_THRES_CH6_V) << (RMT_CARRIER_LOW_THRES_CH6_S)) +#define RMT_CARRIER_LOW_THRES_CH6_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH6_S 0 + +#define RMT_CH7_RX_CARRIER_RM_REG (DR_REG_RMT_BASE + 0x009c) +/* RMT_CARRIER_HIGH_THRES_CH7 : R/W ;bitpos:[31:16] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_HIGH_THRES_CH7 0x0000FFFF +#define RMT_CARRIER_HIGH_THRES_CH7_M ((RMT_CARRIER_HIGH_THRES_CH7_V) << (RMT_CARRIER_HIGH_THRES_CH7_S)) +#define RMT_CARRIER_HIGH_THRES_CH7_V 0xFFFF +#define RMT_CARRIER_HIGH_THRES_CH7_S 16 +/* RMT_CARRIER_LOW_THRES_CH7 : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: */ +#define RMT_CARRIER_LOW_THRES_CH7 0x0000FFFF +#define RMT_CARRIER_LOW_THRES_CH7_M ((RMT_CARRIER_LOW_THRES_CH7_V) << (RMT_CARRIER_LOW_THRES_CH7_S)) +#define RMT_CARRIER_LOW_THRES_CH7_V 0xFFFF +#define RMT_CARRIER_LOW_THRES_CH7_S 0 + +#define RMT_CH0_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a0) +/* RMT_LOOP_COUNT_RESET_CH0 : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_LOOP_COUNT_RESET_CH0 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH0_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH0_S 20 +/* RMT_TX_LOOP_CNT_EN_CH0 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_CNT_EN_CH0 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH0_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH0_S 19 +/* RMT_TX_LOOP_NUM_CH0 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_NUM_CH0 0x000003FF +#define RMT_TX_LOOP_NUM_CH0_M ((RMT_TX_LOOP_NUM_CH0_V) << (RMT_TX_LOOP_NUM_CH0_S)) +#define RMT_TX_LOOP_NUM_CH0_V 0x3FF +#define RMT_TX_LOOP_NUM_CH0_S 9 +/* RMT_TX_LIM_CH0 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_TX_LIM_CH0 0x000001FF +#define RMT_TX_LIM_CH0_M ((RMT_TX_LIM_CH0_V) << (RMT_TX_LIM_CH0_S)) +#define RMT_TX_LIM_CH0_V 0x1FF +#define RMT_TX_LIM_CH0_S 0 + +#define RMT_CH1_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a4) +/* RMT_LOOP_COUNT_RESET_CH1 : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_LOOP_COUNT_RESET_CH1 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH1_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH1_S 20 +/* RMT_TX_LOOP_CNT_EN_CH1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_CNT_EN_CH1 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH1_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH1_S 19 +/* RMT_TX_LOOP_NUM_CH1 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_NUM_CH1 0x000003FF +#define RMT_TX_LOOP_NUM_CH1_M ((RMT_TX_LOOP_NUM_CH1_V) << (RMT_TX_LOOP_NUM_CH1_S)) +#define RMT_TX_LOOP_NUM_CH1_V 0x3FF +#define RMT_TX_LOOP_NUM_CH1_S 9 +/* RMT_TX_LIM_CH1 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_TX_LIM_CH1 0x000001FF +#define RMT_TX_LIM_CH1_M ((RMT_TX_LIM_CH1_V) << (RMT_TX_LIM_CH1_S)) +#define RMT_TX_LIM_CH1_V 0x1FF +#define RMT_TX_LIM_CH1_S 0 + +#define RMT_CH2_TX_LIM_REG (DR_REG_RMT_BASE + 0x00a8) +/* RMT_LOOP_COUNT_RESET_CH2 : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_LOOP_COUNT_RESET_CH2 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH2_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH2_S 20 +/* RMT_TX_LOOP_CNT_EN_CH2 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_CNT_EN_CH2 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH2_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH2_S 19 +/* RMT_TX_LOOP_NUM_CH2 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_NUM_CH2 0x000003FF +#define RMT_TX_LOOP_NUM_CH2_M ((RMT_TX_LOOP_NUM_CH2_V) << (RMT_TX_LOOP_NUM_CH2_S)) +#define RMT_TX_LOOP_NUM_CH2_V 0x3FF +#define RMT_TX_LOOP_NUM_CH2_S 9 +/* RMT_TX_LIM_CH2 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_TX_LIM_CH2 0x000001FF +#define RMT_TX_LIM_CH2_M ((RMT_TX_LIM_CH2_V) << (RMT_TX_LIM_CH2_S)) +#define RMT_TX_LIM_CH2_V 0x1FF +#define RMT_TX_LIM_CH2_S 0 + +#define RMT_CH3_TX_LIM_REG (DR_REG_RMT_BASE + 0x00ac) +/* RMT_LOOP_COUNT_RESET_CH3 : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RMT_LOOP_COUNT_RESET_CH3 (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_M (BIT(20)) +#define RMT_LOOP_COUNT_RESET_CH3_V 0x1 +#define RMT_LOOP_COUNT_RESET_CH3_S 20 +/* RMT_TX_LOOP_CNT_EN_CH3 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_CNT_EN_CH3 (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_M (BIT(19)) +#define RMT_TX_LOOP_CNT_EN_CH3_V 0x1 +#define RMT_TX_LOOP_CNT_EN_CH3_S 19 +/* RMT_TX_LOOP_NUM_CH3 : R/W ;bitpos:[18:9] ;default: 10'b0 ; */ +/*description: */ +#define RMT_TX_LOOP_NUM_CH3 0x000003FF +#define RMT_TX_LOOP_NUM_CH3_M ((RMT_TX_LOOP_NUM_CH3_V) << (RMT_TX_LOOP_NUM_CH3_S)) +#define RMT_TX_LOOP_NUM_CH3_V 0x3FF +#define RMT_TX_LOOP_NUM_CH3_S 9 +/* RMT_TX_LIM_CH3 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_TX_LIM_CH3 0x000001FF +#define RMT_TX_LIM_CH3_M ((RMT_TX_LIM_CH3_V) << (RMT_TX_LIM_CH3_S)) +#define RMT_TX_LIM_CH3_V 0x1FF +#define RMT_TX_LIM_CH3_S 0 + +#define RMT_CH4_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b0) +/* RMT_RX_LIM_CH4 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_RX_LIM_CH4 0x000001FF +#define RMT_RX_LIM_CH4_M ((RMT_RX_LIM_CH4_V) << (RMT_RX_LIM_CH4_S)) +#define RMT_RX_LIM_CH4_V 0x1FF +#define RMT_RX_LIM_CH4_S 0 + +#define RMT_CH5_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b4) +/* RMT_RX_LIM_CH5 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_RX_LIM_CH5 0x000001FF +#define RMT_RX_LIM_CH5_M ((RMT_RX_LIM_CH5_V) << (RMT_RX_LIM_CH5_S)) +#define RMT_RX_LIM_CH5_V 0x1FF +#define RMT_RX_LIM_CH5_S 0 + +#define RMT_CH6_RX_LIM_REG (DR_REG_RMT_BASE + 0x00b8) +/* RMT_RX_LIM_CH6 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_RX_LIM_CH6 0x000001FF +#define RMT_RX_LIM_CH6_M ((RMT_RX_LIM_CH6_V) << (RMT_RX_LIM_CH6_S)) +#define RMT_RX_LIM_CH6_V 0x1FF +#define RMT_RX_LIM_CH6_S 0 + +#define RMT_CH7_RX_LIM_REG (DR_REG_RMT_BASE + 0x00bc) +/* RMT_RX_LIM_CH7 : R/W ;bitpos:[8:0] ;default: 9'h80 ; */ +/*description: */ +#define RMT_RX_LIM_CH7 0x000001FF +#define RMT_RX_LIM_CH7_M ((RMT_RX_LIM_CH7_V) << (RMT_RX_LIM_CH7_S)) +#define RMT_RX_LIM_CH7_V 0x1FF +#define RMT_RX_LIM_CH7_S 0 + +#define RMT_SYS_CONF_REG (DR_REG_RMT_BASE + 0x00c0) +/* RMT_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define RMT_CLK_EN (BIT(31)) +#define RMT_CLK_EN_M (BIT(31)) +#define RMT_CLK_EN_V 0x1 +#define RMT_CLK_EN_S 31 +/* RMT_SCLK_ACTIVE : R/W ;bitpos:[26] ;default: 1'h1 ; */ +/*description: */ +#define RMT_SCLK_ACTIVE (BIT(26)) +#define RMT_SCLK_ACTIVE_M (BIT(26)) +#define RMT_SCLK_ACTIVE_V 0x1 +#define RMT_SCLK_ACTIVE_S 26 +/* RMT_SCLK_SEL : R/W ;bitpos:[25:24] ;default: 2'h1 ; */ +/*description: */ +#define RMT_SCLK_SEL 0x00000003 +#define RMT_SCLK_SEL_M ((RMT_SCLK_SEL_V) << (RMT_SCLK_SEL_S)) +#define RMT_SCLK_SEL_V 0x3 +#define RMT_SCLK_SEL_S 24 +/* RMT_SCLK_DIV_B : R/W ;bitpos:[23:18] ;default: 6'h0 ; */ +/*description: */ +#define RMT_SCLK_DIV_B 0x0000003F +#define RMT_SCLK_DIV_B_M ((RMT_SCLK_DIV_B_V) << (RMT_SCLK_DIV_B_S)) +#define RMT_SCLK_DIV_B_V 0x3F +#define RMT_SCLK_DIV_B_S 18 +/* RMT_SCLK_DIV_A : R/W ;bitpos:[17:12] ;default: 6'h0 ; */ +/*description: */ +#define RMT_SCLK_DIV_A 0x0000003F +#define RMT_SCLK_DIV_A_M ((RMT_SCLK_DIV_A_V) << (RMT_SCLK_DIV_A_S)) +#define RMT_SCLK_DIV_A_V 0x3F +#define RMT_SCLK_DIV_A_S 12 +/* RMT_SCLK_DIV_NUM : R/W ;bitpos:[11:4] ;default: 8'h1 ; */ +/*description: */ +#define RMT_SCLK_DIV_NUM 0x000000FF +#define RMT_SCLK_DIV_NUM_M ((RMT_SCLK_DIV_NUM_V) << (RMT_SCLK_DIV_NUM_S)) +#define RMT_SCLK_DIV_NUM_V 0xFF +#define RMT_SCLK_DIV_NUM_S 4 +/* RMT_MEM_FORCE_PU : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FORCE_PU (BIT(3)) +#define RMT_MEM_FORCE_PU_M (BIT(3)) +#define RMT_MEM_FORCE_PU_V 0x1 +#define RMT_MEM_FORCE_PU_S 3 +/* RMT_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_FORCE_PD (BIT(2)) +#define RMT_MEM_FORCE_PD_M (BIT(2)) +#define RMT_MEM_FORCE_PD_V 0x1 +#define RMT_MEM_FORCE_PD_S 2 +/* RMT_MEM_CLK_FORCE_ON : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_MEM_CLK_FORCE_ON (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_M (BIT(1)) +#define RMT_MEM_CLK_FORCE_ON_V 0x1 +#define RMT_MEM_CLK_FORCE_ON_S 1 +/* RMT_APB_FIFO_MASK : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define RMT_APB_FIFO_MASK (BIT(0)) +#define RMT_APB_FIFO_MASK_M (BIT(0)) +#define RMT_APB_FIFO_MASK_V 0x1 +#define RMT_APB_FIFO_MASK_S 0 + +#define RMT_TX_SIM_REG (DR_REG_RMT_BASE + 0x00c4) +/* RMT_TX_SIM_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_EN (BIT(4)) +#define RMT_TX_SIM_EN_M (BIT(4)) +#define RMT_TX_SIM_EN_V 0x1 +#define RMT_TX_SIM_EN_S 4 +/* RMT_TX_SIM_CH3 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_CH3 (BIT(3)) +#define RMT_TX_SIM_CH3_M (BIT(3)) +#define RMT_TX_SIM_CH3_V 0x1 +#define RMT_TX_SIM_CH3_S 3 +/* RMT_TX_SIM_CH2 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_CH2 (BIT(2)) +#define RMT_TX_SIM_CH2_M (BIT(2)) +#define RMT_TX_SIM_CH2_V 0x1 +#define RMT_TX_SIM_CH2_S 2 +/* RMT_TX_SIM_CH1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_CH1 (BIT(1)) +#define RMT_TX_SIM_CH1_M (BIT(1)) +#define RMT_TX_SIM_CH1_V 0x1 +#define RMT_TX_SIM_CH1_S 1 +/* RMT_TX_SIM_CH0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_TX_SIM_CH0 (BIT(0)) +#define RMT_TX_SIM_CH0_M (BIT(0)) +#define RMT_TX_SIM_CH0_V 0x1 +#define RMT_TX_SIM_CH0_S 0 + +#define RMT_REF_CNT_RST_REG (DR_REG_RMT_BASE + 0x00c8) +/* RMT_REF_CNT_RST_CH7 : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH7 (BIT(7)) +#define RMT_REF_CNT_RST_CH7_M (BIT(7)) +#define RMT_REF_CNT_RST_CH7_V 0x1 +#define RMT_REF_CNT_RST_CH7_S 7 +/* RMT_REF_CNT_RST_CH6 : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH6 (BIT(6)) +#define RMT_REF_CNT_RST_CH6_M (BIT(6)) +#define RMT_REF_CNT_RST_CH6_V 0x1 +#define RMT_REF_CNT_RST_CH6_S 6 +/* RMT_REF_CNT_RST_CH5 : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH5 (BIT(5)) +#define RMT_REF_CNT_RST_CH5_M (BIT(5)) +#define RMT_REF_CNT_RST_CH5_V 0x1 +#define RMT_REF_CNT_RST_CH5_S 5 +/* RMT_REF_CNT_RST_CH4 : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH4 (BIT(4)) +#define RMT_REF_CNT_RST_CH4_M (BIT(4)) +#define RMT_REF_CNT_RST_CH4_V 0x1 +#define RMT_REF_CNT_RST_CH4_S 4 +/* RMT_REF_CNT_RST_CH3 : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH3 (BIT(3)) +#define RMT_REF_CNT_RST_CH3_M (BIT(3)) +#define RMT_REF_CNT_RST_CH3_V 0x1 +#define RMT_REF_CNT_RST_CH3_S 3 +/* RMT_REF_CNT_RST_CH2 : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH2 (BIT(2)) +#define RMT_REF_CNT_RST_CH2_M (BIT(2)) +#define RMT_REF_CNT_RST_CH2_V 0x1 +#define RMT_REF_CNT_RST_CH2_S 2 +/* RMT_REF_CNT_RST_CH1 : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH1 (BIT(1)) +#define RMT_REF_CNT_RST_CH1_M (BIT(1)) +#define RMT_REF_CNT_RST_CH1_V 0x1 +#define RMT_REF_CNT_RST_CH1_S 1 +/* RMT_REF_CNT_RST_CH0 : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RMT_REF_CNT_RST_CH0 (BIT(0)) +#define RMT_REF_CNT_RST_CH0_M (BIT(0)) +#define RMT_REF_CNT_RST_CH0_V 0x1 +#define RMT_REF_CNT_RST_CH0_S 0 + +#define RMT_DATE_REG (DR_REG_RMT_BASE + 0x00cc) +/* RMT_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003041 ; */ +/*description: */ +#define RMT_DATE 0x0FFFFFFF +#define RMT_DATE_M ((RMT_DATE_V) << (RMT_DATE_S)) +#define RMT_DATE_V 0xFFFFFFF +#define RMT_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rmt_struct.h b/components/soc/soc/esp32s3/include/soc/rmt_struct.h new file mode 100644 index 000000000..dd5284753 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rmt_struct.h @@ -0,0 +1,300 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + uint32_t data_ch[8]; /**/ + union { + struct { + uint32_t mem_raddr_ex: 10; + uint32_t reserved10: 1; + uint32_t waddr: 10; + uint32_t reserved21: 1; + uint32_t state: 3; + uint32_t mem_empty: 1; + uint32_t apb_mem_wr_err: 1; + uint32_t reserved27: 5; + }; + uint32_t val; + } status_ch[8]; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_tx_end: 1; + uint32_t ch3_tx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_tx_thr_event: 1; + uint32_t ch3_tx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t ch2_tx_loop: 1; + uint32_t ch3_tx_loop: 1; + uint32_t ch4_rx_end: 1; + uint32_t ch5_rx_end: 1; + uint32_t ch6_rx_end: 1; + uint32_t ch7_rx_end: 1; + uint32_t ch4_err: 1; + uint32_t ch5_err: 1; + uint32_t ch6_err: 1; + uint32_t ch7_err: 1; + uint32_t ch4_rx_thr_event: 1; + uint32_t ch5_rx_thr_event: 1; + uint32_t ch6_rx_thr_event: 1; + uint32_t ch7_rx_thr_event: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_tx_end: 1; + uint32_t ch3_tx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_tx_thr_event: 1; + uint32_t ch3_tx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t ch2_tx_loop: 1; + uint32_t ch3_tx_loop: 1; + uint32_t ch4_rx_end: 1; + uint32_t ch5_rx_end: 1; + uint32_t ch6_rx_end: 1; + uint32_t ch7_rx_end: 1; + uint32_t ch4_err: 1; + uint32_t ch5_err: 1; + uint32_t ch6_err: 1; + uint32_t ch7_err: 1; + uint32_t ch4_rx_thr_event: 1; + uint32_t ch5_rx_thr_event: 1; + uint32_t ch6_rx_thr_event: 1; + uint32_t ch7_rx_thr_event: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_tx_end: 1; + uint32_t ch3_tx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_tx_thr_event: 1; + uint32_t ch3_tx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t ch2_tx_loop: 1; + uint32_t ch3_tx_loop: 1; + uint32_t ch4_rx_end: 1; + uint32_t ch5_rx_end: 1; + uint32_t ch6_rx_end: 1; + uint32_t ch7_rx_end: 1; + uint32_t ch4_err: 1; + uint32_t ch5_err: 1; + uint32_t ch6_err: 1; + uint32_t ch7_err: 1; + uint32_t ch4_rx_thr_event: 1; + uint32_t ch5_rx_thr_event: 1; + uint32_t ch6_rx_thr_event: 1; + uint32_t ch7_rx_thr_event: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t ch0_tx_end: 1; + uint32_t ch1_tx_end: 1; + uint32_t ch2_tx_end: 1; + uint32_t ch3_tx_end: 1; + uint32_t ch0_err: 1; + uint32_t ch1_err: 1; + uint32_t ch2_err: 1; + uint32_t ch3_err: 1; + uint32_t ch0_tx_thr_event: 1; + uint32_t ch1_tx_thr_event: 1; + uint32_t ch2_tx_thr_event: 1; + uint32_t ch3_tx_thr_event: 1; + uint32_t ch0_tx_loop: 1; + uint32_t ch1_tx_loop: 1; + uint32_t ch2_tx_loop: 1; + uint32_t ch3_tx_loop: 1; + uint32_t ch4_rx_end: 1; + uint32_t ch5_rx_end: 1; + uint32_t ch6_rx_end: 1; + uint32_t ch7_rx_end: 1; + uint32_t ch4_err: 1; + uint32_t ch5_err: 1; + uint32_t ch6_err: 1; + uint32_t ch7_err: 1; + uint32_t ch4_rx_thr_event: 1; + uint32_t ch5_rx_thr_event: 1; + uint32_t ch6_rx_thr_event: 1; + uint32_t ch7_rx_thr_event: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t low: 16; + uint32_t high: 16; + }; + uint32_t val; + } carrier_duty_ch[8]; + union { + struct { + uint32_t carrier_low_thres_ch4: 16; + uint32_t carrier_high_thres_ch4: 16; + }; + uint32_t val; + } ch4_rx_carrier_rm; + union { + struct { + uint32_t carrier_low_thres_ch5: 16; + uint32_t carrier_high_thres_ch5: 16; + }; + uint32_t val; + } ch5_rx_carrier_rm; + union { + struct { + uint32_t carrier_low_thres_ch6: 16; + uint32_t carrier_high_thres_ch6: 16; + }; + uint32_t val; + } ch6_rx_carrier_rm; + union { + struct { + uint32_t carrier_low_thres_ch7: 16; + uint32_t carrier_high_thres_ch7: 16; + }; + uint32_t val; + } ch7_rx_carrier_rm; + union { + struct { + uint32_t limit: 9; + uint32_t tx_loop_num: 10; + uint32_t tx_loop_cnt_en: 1; + uint32_t loop_count_reset: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } tx_lim_ch[8]; + union { + struct { + uint32_t rx_lim_ch4: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } ch4_rx_lim; + union { + struct { + uint32_t rx_lim_ch5: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } ch5_rx_lim; + union { + struct { + uint32_t rx_lim_ch6: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } ch6_rx_lim; + union { + struct { + uint32_t rx_lim_ch7: 9; + uint32_t reserved9: 23; + }; + uint32_t val; + } ch7_rx_lim; + union { + struct { + uint32_t fifo_mask: 1; + uint32_t mem_clk_force_on: 1; + uint32_t mem_force_pd: 1; + uint32_t mem_force_pu: 1; + uint32_t sclk_div_num: 8; + uint32_t sclk_div_a: 6; + uint32_t sclk_div_b: 6; + uint32_t sclk_sel: 2; + uint32_t sclk_active: 1; + uint32_t reserved27: 4; + uint32_t clk_en: 1; + }; + uint32_t val; + } sys_conf; + union { + struct { + uint32_t ch0: 1; + uint32_t ch1: 1; + uint32_t ch2: 1; + uint32_t ch3: 1; + uint32_t en: 1; + uint32_t reserved5: 27; + }; + uint32_t val; + } tx_sim; + union { + struct { + uint32_t ch0: 1; + uint32_t ch1: 1; + uint32_t ch2: 1; + uint32_t ch3: 1; + uint32_t ch4: 1; + uint32_t ch5: 1; + uint32_t ch6: 1; + uint32_t ch7: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } ref_cnt_rst; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rmt_dev_t; + +extern rmt_dev_t RMT; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rtc.h b/components/soc/soc/esp32s3/include/soc/rtc.h new file mode 100644 index 000000000..548b38ee6 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc.h @@ -0,0 +1,819 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include +#include +#include +#include "soc/soc.h" + +#ifdef __cplusplus +extern "C" { +#endif + +/** + * @file rtc.h + * @brief Low-level RTC power, clock, and sleep functions. + * + * Functions in this file facilitate configuration of ESP32's RTC_CNTL peripheral. + * RTC_CNTL peripheral handles many functions: + * - enables/disables clocks and power to various parts of the chip; this is + * done using direct register access (forcing power up or power down) or by + * allowing state machines to control power and clocks automatically + * - handles sleep and wakeup functions + * - maintains a 48-bit counter which can be used for timekeeping + * + * These functions are not thread safe, and should not be viewed as high level + * APIs. For example, while this file provides a function which can switch + * CPU frequency, this function is on its own is not sufficient to implement + * frequency switching in ESP-IDF context: some coordination with RTOS, + * peripheral drivers, and WiFi/BT stacks is also required. + * + * These functions will normally not be used in applications directly. + * ESP-IDF provides, or will provide, drivers and other facilities to use + * RTC subsystem functionality. + * + * The functions are loosely split into the following groups: + * - rtc_clk: clock switching, calibration + * - rtc_time: reading RTC counter, conversion between counter values and time + * - rtc_sleep: entry into sleep modes + * - rtc_init: initialization + */ + +#define MHZ (1000000) + +#define RTC_SLOW_CLK_X32K_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_8MD256_CAL_TIMEOUT_THRES(cycles) (cycles << 12) +#define RTC_SLOW_CLK_150K_CAL_TIMEOUT_THRES(cycles) (cycles << 10) + +#define RTC_SLOW_CLK_FREQ_90K 90000 +#define RTC_SLOW_CLK_FREQ_8MD256 (RTC_FAST_CLK_FREQ_APPROX / 256) +#define RTC_SLOW_CLK_FREQ_32K 32768 + +#define OTHER_BLOCKS_POWERUP 1 +#define OTHER_BLOCKS_WAIT 1 + +/* Approximate mapping of voltages to RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_SLP, + * RTC_CNTL_DIG_DBIAS_WAK, RTC_CNTL_DIG_DBIAS_SLP values. + * Valid if RTC_CNTL_DBG_ATTEN is 0. + */ +#define RTC_CNTL_DBIAS_0V90 0 +#define RTC_CNTL_DBIAS_0V95 1 +#define RTC_CNTL_DBIAS_1V00 2 +#define RTC_CNTL_DBIAS_1V05 3 +#define RTC_CNTL_DBIAS_1V10 4 +#define RTC_CNTL_DBIAS_1V15 5 +#define RTC_CNTL_DBIAS_1V20 6 +#define RTC_CNTL_DBIAS_1V25 7 + +#define DELAY_FAST_CLK_SWITCH 3 +#define DELAY_SLOW_CLK_SWITCH 300 +#define DELAY_8M_ENABLE 50 + +/* Number of 8M/256 clock cycles to use for XTAL frequency estimation. + * 10 cycles will take approximately 300 microseconds. + */ +#define XTAL_FREQ_EST_CYCLES 10 + +/* Core voltage needs to be increased in two cases: + * 1. running at 240 MHz + * 2. running with 80MHz Flash frequency + */ +#ifdef CONFIG_ESPTOOLPY_FLASHFREQ_80M +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V25 +#else +#define DIG_DBIAS_80M_160M RTC_CNTL_DBIAS_1V10 +#endif +#define DIG_DBIAS_240M RTC_CNTL_DBIAS_1V25 +#define DIG_DBIAS_XTAL RTC_CNTL_DBIAS_1V10 +#define DIG_DBIAS_2M RTC_CNTL_DBIAS_1V00 + +#define RTC_CNTL_PLL_BUF_WAIT_DEFAULT 20 +#define RTC_CNTL_XTL_BUF_WAIT_DEFAULT 100 +#define RTC_CNTL_CK8M_WAIT_DEFAULT 20 +#define RTC_CK8M_ENABLE_WAIT_DEFAULT 1 + +#define RTC_CNTL_CK8M_DFREQ_DEFAULT 172 +#define RTC_CNTL_SCK_DCAP_DEFAULT 255 + +/* +set sleep_init default param +*/ +#define RTC_CNTL_DBG_ATTEN_LIGHTSLEEP_DEFAULT 6 +#define RTC_CNTL_DBG_ATTEN_DEEPSLEEP_DEFAULT 15 +#define RTC_CNTL_DBG_ATTEN_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_MONITOR_DEFAULT 0 +#define RTC_CNTL_BIASSLP_SLEEP_DEFAULT 1 +#define RTC_CNTL_PD_CUR_MONITOR_DEFAULT 0 +#define RTC_CNTL_PD_CUR_SLEEP_DEFAULT 1 + +#define APLL_SDM_STOP_VAL_1 0x09 +#define APLL_SDM_STOP_VAL_2_REV0 0x69 +#define APLL_SDM_STOP_VAL_2_REV1 0x49 +#define APLL_CAL_DELAY_1 0x0f +#define APLL_CAL_DELAY_2 0x3f +#define APLL_CAL_DELAY_3 0x1f + +#define i2c_ulp_block 0x61 +#define i2c_ulp_hostid 0x1 +#define i2c_ulp_ir_resetb 0 +#define i2c_ulp_ir_resetb_msb 0 +#define i2c_ulp_ir_resetb_lsb 0 + +/** + * @brief Possible main XTAL frequency values. + * + * Enum values should be equal to frequency in MHz. + */ +typedef enum { + RTC_XTAL_FREQ_40M = 40, //!< 40 MHz XTAL +} rtc_xtal_freq_t; + +/** + * @brief CPU frequency values + */ +typedef enum { + RTC_CPU_FREQ_XTAL = 0, //!< Main XTAL frequency + RTC_CPU_FREQ_80M = 1, //!< 80 MHz + RTC_CPU_FREQ_160M = 2, //!< 160 MHz + RTC_CPU_FREQ_240M = 3, //!< 240 MHz + RTC_CPU_FREQ_2M = 4, //!< 2 MHz + RTC_CPU_320M_80M = 5, //!< for test + RTC_CPU_320M_160M = 6, //!< for test + RTC_CPU_FREQ_XTAL_DIV2 = 7, //!< XTAL/2 after reset +} rtc_cpu_freq_t; + +/** + * @brief CPU clock source + */ +typedef enum { + RTC_CPU_FREQ_SRC_XTAL, //!< XTAL + RTC_CPU_FREQ_SRC_PLL, //!< PLL (480M or 320M) + RTC_CPU_FREQ_SRC_8M, //!< Internal 8M RTC oscillator + RTC_CPU_FREQ_SRC_APLL //!< APLL +} rtc_cpu_freq_src_t; + +/** + * @brief CPU clock configuration structure + */ +typedef struct rtc_cpu_freq_config_s { + rtc_cpu_freq_src_t source; //!< The clock from which CPU clock is derived + uint32_t source_freq_mhz; //!< Source clock frequency + uint32_t div; //!< Divider, freq_mhz = source_freq_mhz / div + uint32_t freq_mhz; //!< CPU clock frequency +} rtc_cpu_freq_config_t; + +/** + * @brief RTC SLOW_CLK frequency values + */ +typedef enum { + RTC_SLOW_FREQ_RTC = 0, //!< Internal 150 kHz RC oscillator + RTC_SLOW_FREQ_32K_XTAL = 1, //!< External 32 kHz XTAL + RTC_SLOW_FREQ_8MD256 = 2, //!< Internal 8 MHz RC oscillator, divided by 256 +} rtc_slow_freq_t; + +/** + * @brief RTC FAST_CLK frequency values + */ +typedef enum { + RTC_FAST_FREQ_XTALD4 = 0, //!< Main XTAL, divided by 4 + RTC_FAST_FREQ_8M = 1, //!< Internal 8 MHz RC oscillator +} rtc_fast_freq_t; + +/* With the default value of CK8M_DFREQ, 8M clock frequency is 8.5 MHz +/- 7% */ +#define RTC_FAST_CLK_FREQ_APPROX 8500000 + +#define RTC_CLK_CAL_FRACT 19 //!< Number of fractional bits in values returned by rtc_clk_cal + +#define RTC_VDDSDIO_TIEH_1_8V 0 //!< TIEH field value for 1.8V VDDSDIO +#define RTC_VDDSDIO_TIEH_3_3V 1 //!< TIEH field value for 3.3V VDDSDIO + +/** + * @brief Clock source to be calibrated using rtc_clk_cal function + */ +typedef enum { + RTC_CAL_RTC_MUX = 0, //!< Currently selected RTC SLOW_CLK + RTC_CAL_8MD256 = 1, //!< Internal 8 MHz RC oscillator, divided by 256 + RTC_CAL_32K_XTAL = 2 //!< External 32 kHz XTAL +} rtc_cal_sel_t; + +/** + * Initialization parameters for rtc_clk_init + */ +typedef struct { + rtc_xtal_freq_t xtal_freq : 8; //!< Main XTAL frequency + uint32_t cpu_freq_mhz : 10; //!< CPU frequency to set, in MHz + rtc_fast_freq_t fast_freq : 1; //!< RTC_FAST_CLK frequency to set + rtc_slow_freq_t slow_freq : 2; //!< RTC_SLOW_CLK frequency to set + uint32_t clk_rtc_clk_div : 8; + uint32_t clk_8m_clk_div : 3; //!< RTC 8M clock divider (division is by clk_8m_div+1, i.e. 0 means 8MHz frequency) + uint32_t slow_clk_dcap : 8; //!< RTC 150k clock adjustment parameter (higher value leads to lower frequency) + uint32_t clk_8m_dfreq : 8; //!< RTC 8m clock adjustment parameter (higher value leads to higher frequency) +} rtc_clk_config_t; + +/** + * Default initializer for rtc_clk_config_t + */ +#define RTC_CLK_CONFIG_DEFAULT() { \ + .xtal_freq = RTC_XTAL_FREQ_40M, \ + .cpu_freq_mhz = 80, \ + .fast_freq = RTC_FAST_FREQ_8M, \ + .slow_freq = RTC_SLOW_FREQ_RTC, \ + .clk_rtc_clk_div = 0, \ + .clk_8m_clk_div = 0, \ + .slow_clk_dcap = RTC_CNTL_SCK_DCAP_DEFAULT, \ + .clk_8m_dfreq = RTC_CNTL_CK8M_DFREQ_DEFAULT, \ +} + +typedef struct { + uint32_t dac : 6; + uint32_t dres : 3; + uint32_t dgm : 3; + uint32_t dbuf: 1; +} x32k_config_t; + +#define X32K_CONFIG_DEFAULT() { \ + .dac = 1, \ + .dres = 3, \ + .dgm = 0, \ + .dbuf = 1, \ +} + +#if 0 +#define X32K_CONFIG_BOOTSTRAP_DEFAULT() { \ + .dac = 3, \ + .dres = 3, \ + .dgm = 0, \ +} + +typedef struct { + x32k_config_t x32k_cfg; + uint32_t bt_lpck_div_num : 12; + uint32_t bt_lpck_div_a : 12; + uint32_t bt_lpck_div_b : 12; +} x32k_bootstrap_config_t; + +#define X32K_BOOTSTRAP_CONFIG_DEFAULT() { \ + .x32k_cfg = X32K_CONFIG_BOOTSTRAP_DEFAULT(), \ + .bt_lpck_div_num = 2441, \ + .bt_lpck_div_a = 32, \ + .bt_lpck_div_b = 13, \ +} +#endif + +typedef struct { + uint16_t wifi_powerup_cycles : 7; + uint16_t wifi_wait_cycles : 9; + uint16_t rtc_powerup_cycles : 7; + uint16_t rtc_wait_cycles : 9; + uint16_t dg_wrap_powerup_cycles : 7; + uint16_t dg_wrap_wait_cycles : 9; + uint16_t rtc_mem_powerup_cycles : 7; + uint16_t rtc_mem_wait_cycles : 9; +} rtc_init_config_t; + +#define RTC_INIT_CONFIG_DEFAULT() { \ + .wifi_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .wifi_wait_cycles = OTHER_BLOCKS_WAIT, \ + .rtc_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .rtc_wait_cycles = OTHER_BLOCKS_WAIT, \ + .dg_wrap_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .dg_wrap_wait_cycles = OTHER_BLOCKS_WAIT, \ + .rtc_mem_powerup_cycles = OTHER_BLOCKS_POWERUP, \ + .rtc_mem_wait_cycles = OTHER_BLOCKS_WAIT, \ +} + +void rtc_clk_divider_set(uint32_t div); + +void rtc_clk_8m_divider_set(uint32_t div); + +/** + * Initialize clocks and set CPU frequency + * + * @param cfg clock configuration as rtc_clk_config_t + */ +void rtc_clk_init(rtc_clk_config_t cfg); + +/** + * @brief Get main XTAL frequency + * + * This is the value stored in RTC register RTC_XTAL_FREQ_REG by the bootloader. As passed to + * rtc_clk_init function + * + * @return XTAL frequency, one of rtc_xtal_freq_t + */ +rtc_xtal_freq_t rtc_clk_xtal_freq_get(void); + +/** + * @brief Update XTAL frequency + * + * Updates the XTAL value stored in RTC_XTAL_FREQ_REG. Usually this value is ignored + * after startup. + * + * @param xtal_freq New frequency value + */ +void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq); + +/** + * @brief Enable or disable 32 kHz XTAL oscillator + * @param en true to enable, false to disable + */ +void rtc_clk_32k_enable(bool en); + +/** + * @brief Configure 32 kHz XTAL oscillator to accept external clock signal + */ +void rtc_clk_32k_enable_external(void); + +/** + * @brief Get the state of 32k XTAL oscillator + * @return true if 32k XTAL oscillator has been enabled + */ +bool rtc_clk_32k_enabled(void); + +/** + * @brief Enable 32k oscillator, configuring it for fast startup time. + * Note: to achieve higher frequency stability, rtc_clk_32k_enable function + * must be called one the 32k XTAL oscillator has started up. This function + * will initially disable the 32k XTAL oscillator, so it should not be called + * when the system is using 32k XTAL as RTC_SLOW_CLK. + * + * @param cycle Number of 32kHz cycles to bootstrap external crystal. + * If 0, no square wave will be used to bootstrap crystal oscillation. + */ +void rtc_clk_32k_bootstrap(uint32_t cycle); + +/** + * @brief Enable or disable 8 MHz internal oscillator + * + * Output from 8 MHz internal oscillator is passed into a configurable + * divider, which by default divides the input clock frequency by 256. + * Output of the divider may be used as RTC_SLOW_CLK source. + * Output of the divider is referred to in register descriptions and code as + * 8md256 or simply d256. Divider values other than 256 may be configured, but + * this facility is not currently needed, so is not exposed in the code. + * + * When 8MHz/256 divided output is not needed, the divider should be disabled + * to reduce power consumption. + * + * @param clk_8m_en true to enable 8MHz generator + * @param d256_en true to enable /256 divider + */ +void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en); + +/** + * @brief Get the state of 8 MHz internal oscillator + * @return true if the oscillator is enabled + */ +bool rtc_clk_8m_enabled(void); + +/** + * @brief Get the state of /256 divider which is applied to 8MHz clock + * @return true if the divided output is enabled + */ +bool rtc_clk_8md256_enabled(void); + +/** + * @brief Enable or disable APLL + * + * Output frequency is given by the formula: + * apll_freq = xtal_freq * (4 + sdm2 + sdm1/256 + sdm0/65536)/((o_div + 2) * 2) + * + * The dividend in this expression should be in the range of 240 - 600 MHz. + * + * In rev. 0 of ESP32, sdm0 and sdm1 are unused and always set to 0. + * + * @param enable true to enable, false to disable + * @param sdm0 frequency adjustment parameter, 0..255 + * @param sdm1 frequency adjustment parameter, 0..255 + * @param sdm2 frequency adjustment parameter, 0..63 + * @param o_div frequency divider, 0..31 + */ +void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div); + +/** + * @brief Set XTAL wait cycles by RTC slow clock's period + */ +void rtc_clk_set_xtal_wait(void); + +/** + * @brief Select source for RTC_SLOW_CLK + * @param slow_freq clock source (one of rtc_slow_freq_t values) + */ +void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq); + +/** + * @brief Get the RTC_SLOW_CLK source + * @return currently selected clock source (one of rtc_slow_freq_t values) + */ +rtc_slow_freq_t rtc_clk_slow_freq_get(void); + +/** + * @brief Get the approximate frequency of RTC_SLOW_CLK, in Hz + * + * - if RTC_SLOW_FREQ_RTC is selected, returns ~150000 + * - if RTC_SLOW_FREQ_32K_XTAL is selected, returns 32768 + * - if RTC_SLOW_FREQ_8MD256 is selected, returns ~33000 + * + * rtc_clk_cal function can be used to get more precise value by comparing + * RTC_SLOW_CLK frequency to the frequency of main XTAL. + * + * @return RTC_SLOW_CLK frequency, in Hz + */ +uint32_t rtc_clk_slow_freq_get_hz(void); + +/** + * @brief Select source for RTC_FAST_CLK + * @param fast_freq clock source (one of rtc_fast_freq_t values) + */ +void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq); + +/** + * @brief Get the RTC_FAST_CLK source + * @return currently selected clock source (one of rtc_fast_freq_t values) + */ +rtc_fast_freq_t rtc_clk_fast_freq_get(void); + +/** + * @brief Get CPU frequency config for a given frequency + * @param freq_mhz Frequency in MHz + * @param[out] out_config Output, CPU frequency configuration structure + * @return true if frequency can be obtained, false otherwise + */ +bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU frequency + * + * This function sets CPU frequency according to the given configuration + * structure. It enables PLLs, if necessary. + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config); + +/** + * @brief Switch CPU frequency (optimized for speed) + * + * This function is a faster equivalent of rtc_clk_cpu_freq_set_config. + * It works faster because it does not disable PLLs when switching from PLL to + * XTAL and does not enabled them when switching back. If PLL is not already + * enabled when this function is called to switch from XTAL to PLL frequency, + * or the PLL which is enabled is the wrong one, this function will fall back + * to calling rtc_clk_cpu_freq_set_config. + * + * Unlike rtc_clk_cpu_freq_set_config, this function relies on static data, + * so it is less safe to use it e.g. from a panic handler (when memory might + * be corrupted). + * + * @note This function in not intended to be called by applications in FreeRTOS + * environment. This is because it does not adjust various timers based on the + * new CPU frequency. + * + * @param config CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config); + +/** + * @brief Get the currently used CPU frequency configuration + * @param[out] out_config Output, CPU frequency configuration structure + */ +void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config); + +/** + * @brief Switch CPU clock source to XTAL + * + * Short form for filling in rtc_cpu_freq_config_t structure and calling + * rtc_clk_cpu_freq_set_config when a switch to XTAL is needed. + * Assumes that XTAL frequency has been determined — don't call in startup code. + */ +void rtc_clk_cpu_freq_set_xtal(void); + +/** + * @brief Store new APB frequency value into RTC_APB_FREQ_REG + * + * This function doesn't change any hardware clocks. + * + * Functions which perform frequency switching and change APB frequency call + * this function to update the value of APB frequency stored in RTC_APB_FREQ_REG + * (one of RTC general purpose retention registers). This should not normally + * be called from application code. + * + * @param apb_freq new APB frequency, in Hz + */ +void rtc_clk_apb_freq_update(uint32_t apb_freq); + +/** + * @brief Get the current stored APB frequency. + * @return The APB frequency value as last set via rtc_clk_apb_freq_update(), in Hz. + */ +uint32_t rtc_clk_apb_freq_get(void); + +uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles); + +/** + * @brief Measure RTC slow clock's period, based on main XTAL frequency + * + * This function will time out and return 0 if the time for the given number + * of cycles to be counted exceeds the expected time twice. This may happen if + * 32k XTAL is being calibrated, but the oscillator has not started up (due to + * incorrect loading capacitance, board design issue, or lack of 32 XTAL on board). + * + * @param cal_clk clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average slow clock period in microseconds, Q13.19 fixed point format, + * or 0 if calibration has timed out + */ +uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Measure ratio between XTAL frequency and RTC slow clock frequency + * @param cal_clk slow clock to be measured + * @param slow_clk_cycles number of slow clock cycles to average + * @return average ratio between XTAL frequency and slow clock frequency, + * Q13.19 fixed point format, or 0 if calibration has timed out. + */ +uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slow_clk_cycles); + +/** + * @brief Convert time interval from microseconds to RTC_SLOW_CLK cycles + * @param time_in_us Time interval in microseconds + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return number of slow clock cycles + */ +uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period); + +/** + * @brief Convert time interval from RTC_SLOW_CLK to microseconds + * @param time_in_us Time interval in RTC_SLOW_CLK cycles + * @param slow_clk_period Period of slow clock in microseconds, Q13.19 + * fixed point format (as returned by rtc_slowck_cali). + * @return time interval in microseconds + */ +uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period); + +/** + * @brief Get current value of RTC counter + * + * RTC has a 48-bit counter which is incremented by 2 every 2 RTC_SLOW_CLK + * cycles. Counter value is not writable by software. The value is not adjusted + * when switching to a different RTC_SLOW_CLK source. + * + * Note: this function may take up to 1 RTC_SLOW_CLK cycle to execute + * + * @return current value of RTC counter + */ +uint64_t rtc_time_get(void); + +uint64_t rtc_light_slp_time_get(void); + +uint64_t rtc_deep_slp_time_get(void); + +/** + * @brief Busy loop until next RTC_SLOW_CLK cycle + * + * This function returns not earlier than the next RTC_SLOW_CLK clock cycle. + * In some cases (e.g. when RTC_SLOW_CLK cycle is very close), it may return + * one RTC_SLOW_CLK cycle later. + */ +void rtc_clk_wait_for_slow_cycle(void); + +/** + * @brief Power down flags for rtc_sleep_pd function + */ +typedef struct { + uint32_t dig_fpu : 1; //!< Set to 1 to power down digital part in sleep + uint32_t rtc_fpu : 1; //!< Set to 1 to power down RTC memories in sleep + uint32_t cpu_fpu : 1; //!< Set to 1 to power down digital memories and CPU in sleep + uint32_t i2s_fpu : 1; //!< Set to 1 to power down I2S in sleep + uint32_t bb_fpu : 1; //!< Set to 1 to power down WiFi in sleep + uint32_t nrx_fpu : 1; //!< Set to 1 to power down WiFi in sleep + uint32_t fe_fpu : 1; //!< Set to 1 to power down WiFi in sleep +} rtc_sleep_pd_config_t; + +/** + * Initializer for rtc_sleep_pd_config_t which sets all flags to the same value + */ +#define RTC_SLEEP_PD_CONFIG_ALL(val) {\ + .dig_fpu = (val), \ + .rtc_fpu = (val), \ + .cpu_fpu = (val), \ + .i2s_fpu = (val), \ + .bb_fpu = (val), \ + .nrx_fpu = (val), \ + .fe_fpu = (val), \ +} + +void rtc_sleep_pd(rtc_sleep_pd_config_t cfg); + +/** + * @brief sleep configuration for rtc_sleep_init function + */ +typedef struct { + uint32_t lslp_mem_inf_fpu : 1; //!< force normal voltage in sleep mode (digital domain memory) + uint32_t rtc_mem_inf_follow_cpu : 1;//!< keep low voltage in sleep mode (even if ULP/touch is used) + uint32_t rtc_fastmem_pd_en : 1; //!< power down RTC fast memory + uint32_t rtc_slowmem_pd_en : 1; //!< power down RTC slow memory + uint32_t rtc_peri_pd_en : 1; //!< power down RTC peripherals + uint32_t wifi_pd_en : 1; //!< power down WiFi + uint32_t deep_slp : 1; //!< power down digital domain + uint32_t wdt_flashboot_mod_en : 1; //!< enable WDT flashboot mode + uint32_t dig_dbias_wak : 3; //!< set bias for digital domain, in active mode + uint32_t dig_dbias_slp : 3; //!< set bias for digital domain, in sleep mode + uint32_t rtc_dbias_wak : 3; //!< set bias for RTC domain, in active mode + uint32_t rtc_dbias_slp : 3; //!< set bias for RTC domain, in sleep mode + uint32_t vddsdio_pd_en : 1; //!< power down VDDSDIO regulator + uint32_t deep_slp_reject : 1; + uint32_t light_slp_reject : 1; +} rtc_sleep_config_t; + +/** + * Default initializer for rtc_sleep_config_t + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use) based on a combination of RTC_SLEEP_PD_x flags. + * + * @param RTC_SLEEP_PD_x flags combined using bitwise OR + */ +#define RTC_SLEEP_CONFIG_DEFAULT(sleep_flags) { \ + .lslp_mem_inf_fpu = 0, \ + .rtc_mem_inf_follow_cpu = ((sleep_flags) & RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU) ? 1 : 0, \ + .rtc_fastmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_FAST_MEM) ? 1 : 0, \ + .rtc_slowmem_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_SLOW_MEM) ? 1 : 0, \ + .rtc_peri_pd_en = ((sleep_flags) & RTC_SLEEP_PD_RTC_PERIPH) ? 1 : 0, \ + .wifi_pd_en = ((sleep_flags) & RTC_SLEEP_PD_WIFI) ? 1 : 0, \ + .deep_slp = ((sleep_flags) & RTC_SLEEP_PD_DIG) ? 1 : 0, \ + .wdt_flashboot_mod_en = 0, \ + .dig_dbias_wak = RTC_CNTL_DIG_DBIAS_1V10, \ + .dig_dbias_slp = RTC_CNTL_DIG_DBIAS_0V90, \ + .rtc_dbias_wak = RTC_CNTL_DBIAS_1V10, \ + .rtc_dbias_slp = RTC_CNTL_DBIAS_1V00, \ + .vddsdio_pd_en = ((sleep_flags) & RTC_SLEEP_PD_VDDSDIO) ? 1 : 0, \ + .deep_slp_reject = 1, \ + .light_slp_reject = 1 \ +}; + +#define RTC_SLEEP_PD_DIG BIT(0) //!< Deep sleep (power down digital domain) +#define RTC_SLEEP_PD_RTC_PERIPH BIT(1) //!< Power down RTC peripherals +#define RTC_SLEEP_PD_RTC_SLOW_MEM BIT(2) //!< Power down RTC SLOW memory +#define RTC_SLEEP_PD_RTC_FAST_MEM BIT(3) //!< Power down RTC FAST memory +#define RTC_SLEEP_PD_RTC_MEM_FOLLOW_CPU BIT(4) //!< RTC FAST and SLOW memories are automatically powered up and down along with the CPU +#define RTC_SLEEP_PD_VDDSDIO BIT(5) //!< Power down VDDSDIO regulator +#define RTC_SLEEP_PD_WIFI BIT(6) + +/** + * @brief Prepare the chip to enter sleep mode + * + * This function configures various power control state machines to handle + * entry into light sleep or deep sleep mode, switches APB and CPU clock source + * (usually to XTAL), and sets bias voltages for digital and RTC power domains. + * + * This function does not actually enter sleep mode; this is done using + * rtc_sleep_start function. Software may do some other actions between + * rtc_sleep_init and rtc_sleep_start, such as set wakeup timer and configure + * wakeup sources. + * @param cfg sleep mode configuration + */ +void rtc_sleep_init(rtc_sleep_config_t cfg); + + +/** + * @brief Set target value of RTC counter for RTC_TIMER_TRIG_EN wakeup source + * @param t value of RTC counter at which wakeup from sleep will happen; + * only the lower 48 bits are used + */ +void rtc_sleep_set_wakeup_time(uint64_t t); + + +#define RTC_EXT0_TRIG_EN BIT(0) //!< EXT0 GPIO wakeup +#define RTC_EXT1_TRIG_EN BIT(1) //!< EXT1 GPIO wakeup +#define RTC_GPIO_TRIG_EN BIT(2) //!< GPIO wakeup (light sleep only) +#define RTC_TIMER_TRIG_EN BIT(3) //!< Timer wakeup +#define RTC_SDIO_TRIG_EN BIT(4) //!< SDIO wakeup (light sleep only) +#define RTC_MAC_TRIG_EN BIT(5) //!< MAC wakeup (light sleep only) +#define RTC_UART0_TRIG_EN BIT(6) //!< UART0 wakeup (light sleep only) +#define RTC_UART1_TRIG_EN BIT(7) //!< UART1 wakeup (light sleep only) +#define RTC_TOUCH_TRIG_EN BIT(8) //!< Touch wakeup +#define RTC_ULP_TRIG_EN BIT(9) //!< ULP wakeup +#define RTC_BT_TRIG_EN BIT(10) //!< BT wakeup (light sleep only) +#define RTC_COCPU_TRIG_EN BIT(11) +#define RTC_XTAL32K_DEAD_TRIG_EN BIT(12) +#define RTC_COCPU_TRAP_TRIG_EN BIT(13) +#define RTC_USB_TRIG_EN BIT(14) + +/** + * @brief Enter deep or light sleep mode + * + * This function enters the sleep mode previously configured using rtc_sleep_init + * function. Before entering sleep, software should configure wake up sources + * appropriately (set up GPIO wakeup registers, timer wakeup registers, + * and so on). + * + * If deep sleep mode was configured using rtc_sleep_init, and sleep is not + * rejected by hardware (based on reject_opt flags), this function never returns. + * When the chip wakes up from deep sleep, CPU is reset and execution starts + * from ROM bootloader. + * + * If light sleep mode was configured using rtc_sleep_init, this function + * returns on wakeup, or if sleep is rejected by hardware. + * + * @param wakeup_opt bit mask wake up reasons to enable (RTC_xxx_TRIG_EN flags + * combined with OR) + * @param reject_opt bit mask of sleep reject reasons: + * - RTC_CNTL_GPIO_REJECT_EN + * - RTC_CNTL_SDIO_REJECT_EN + * These flags are used to prevent entering sleep when e.g. + * an external host is communicating via SDIO slave + * @return non-zero if sleep was rejected by hardware + */ +uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu); + +/** + * RTC power and clock control initialization settings + */ +typedef struct { + uint32_t ck8m_wait : 8; //!< Number of rtc_fast_clk cycles to wait for 8M clock to be ready + uint32_t xtal_wait : 8; //!< Number of rtc_fast_clk cycles to wait for XTAL clock to be ready + uint32_t pll_wait : 8; //!< Number of rtc_fast_clk cycles to wait for PLL to be ready + uint32_t clkctl_init : 1; //!< Perform clock control related initialization + uint32_t pwrctl_init : 1; //!< Perform power control related initialization + uint32_t rtc_dboost_fpd : 1; //!< Force power down RTC_DBOOST + uint32_t xtal_fpu : 1; + uint32_t bbpll_fpu : 1; + uint32_t cpu_waiti_clk_gate : 1; +} rtc_config_t; + +/** + * Default initializer of rtc_config_t. + * + * This initializer sets all fields to "reasonable" values (e.g. suggested for + * production use). + */ +#define RTC_CONFIG_DEFAULT() {\ + .ck8m_wait = RTC_CNTL_CK8M_WAIT_DEFAULT, \ + .xtal_wait = RTC_CNTL_XTL_BUF_WAIT_DEFAULT, \ + .pll_wait = RTC_CNTL_PLL_BUF_WAIT_DEFAULT, \ + .clkctl_init = 1, \ + .pwrctl_init = 1, \ + .rtc_dboost_fpd = 1, \ + .xtal_fpu = 0, \ + .bbpll_fpu = 0, \ + .cpu_waiti_clk_gate = 1\ +} + +/** + * Initialize RTC clock and power control related functions + * @param cfg configuration options as rtc_config_t + */ +void rtc_init(rtc_config_t cfg); + +/** + * Structure describing vddsdio configuration + */ +typedef struct { + uint32_t force : 1; //!< If 1, use configuration from RTC registers; if 0, use EFUSE/bootstrapping pins. + uint32_t enable : 1; //!< Enable VDDSDIO regulator + uint32_t tieh : 1; //!< Select VDDSDIO voltage. One of RTC_VDDSDIO_TIEH_1_8V, RTC_VDDSDIO_TIEH_3_3V + uint32_t drefh : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefm : 2; //!< Tuning parameter for VDDSDIO regulator + uint32_t drefl : 2; //!< Tuning parameter for VDDSDIO regulator +} rtc_vddsdio_config_t; + +/** + * Get current VDDSDIO configuration + * If VDDSDIO configuration is overridden by RTC, get values from RTC + * Otherwise, if VDDSDIO is configured by EFUSE, get values from EFUSE + * Otherwise, use default values and the level of MTDI bootstrapping pin. + * @return currently used VDDSDIO configuration + */ +rtc_vddsdio_config_t rtc_vddsdio_get_config(void); + +/** + * Set new VDDSDIO configuration using RTC registers. + * If config.force == 1, this overrides configuration done using bootstrapping + * pins and EFUSE. + * + * @param config new VDDSDIO configuration + */ +void rtc_vddsdio_set_config(rtc_vddsdio_config_t config); + +#ifdef __cplusplus +} +#endif + diff --git a/components/soc/soc/esp32s3/include/soc/rtc_cntl_reg.h b/components/soc/soc/esp32s3/include/soc/rtc_cntl_reg.h new file mode 100644 index 000000000..3717d6f2a --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_cntl_reg.h @@ -0,0 +1,3588 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define RTC_CNTL_OPTIONS0_REG (DR_REG_RTCCNTL_BASE + 0x0000) +/* RTC_CNTL_SW_SYS_RST : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: SW system reset*/ +#define RTC_CNTL_SW_SYS_RST (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_M (BIT(31)) +#define RTC_CNTL_SW_SYS_RST_V 0x1 +#define RTC_CNTL_SW_SYS_RST_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_NORST : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force no reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_NORST (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_NORST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NORST_S 30 +/* RTC_CNTL_DG_WRAP_FORCE_RST : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: digital wrap force reset in deep sleep*/ +#define RTC_CNTL_DG_WRAP_FORCE_RST (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_M (BIT(29)) +#define RTC_CNTL_DG_WRAP_FORCE_RST_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_RST_S 29 +/* RTC_CNTL_ANALOG_FORCE_NOISO : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_NOISO (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_M (BIT(28)) +#define RTC_CNTL_ANALOG_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_NOISO_S 28 +/* RTC_CNTL_PLL_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_PLL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_NOISO_S 27 +/* RTC_CNTL_XTL_FORCE_NOISO : R/W ;bitpos:[26] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_NOISO (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_M (BIT(26)) +#define RTC_CNTL_XTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_NOISO_S 26 +/* RTC_CNTL_ANALOG_FORCE_ISO : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ANALOG_FORCE_ISO (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_M (BIT(25)) +#define RTC_CNTL_ANALOG_FORCE_ISO_V 0x1 +#define RTC_CNTL_ANALOG_FORCE_ISO_S 25 +/* RTC_CNTL_PLL_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_FORCE_ISO (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_PLL_FORCE_ISO_V 0x1 +#define RTC_CNTL_PLL_FORCE_ISO_S 24 +/* RTC_CNTL_XTL_FORCE_ISO : R/W ;bitpos:[23] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XTL_FORCE_ISO (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_M (BIT(23)) +#define RTC_CNTL_XTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_XTL_FORCE_ISO_S 23 +/* RTC_CNTL_XTL_EN_WAIT : R/W ;bitpos:[17:14] ;default: 4'd2 ; */ +/*description: wait bias_sleep and current source wakeup*/ +#define RTC_CNTL_XTL_EN_WAIT 0x0000000F +#define RTC_CNTL_XTL_EN_WAIT_M ((RTC_CNTL_XTL_EN_WAIT_V) << (RTC_CNTL_XTL_EN_WAIT_S)) +#define RTC_CNTL_XTL_EN_WAIT_V 0xF +#define RTC_CNTL_XTL_EN_WAIT_S 14 +/* RTC_CNTL_XTL_FORCE_PU : R/W ;bitpos:[13] ;default: 1'd1 ; */ +/*description: crystall force power up*/ +#define RTC_CNTL_XTL_FORCE_PU (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_XTL_FORCE_PU_V 0x1 +#define RTC_CNTL_XTL_FORCE_PU_S 13 +/* RTC_CNTL_XTL_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: crystall force power down*/ +#define RTC_CNTL_XTL_FORCE_PD (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_XTL_FORCE_PD_V 0x1 +#define RTC_CNTL_XTL_FORCE_PD_S 12 +/* RTC_CNTL_BBPLL_FORCE_PU : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: BB_PLL force power up*/ +#define RTC_CNTL_BBPLL_FORCE_PU (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_M (BIT(11)) +#define RTC_CNTL_BBPLL_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PU_S 11 +/* RTC_CNTL_BBPLL_FORCE_PD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: BB_PLL force power down*/ +#define RTC_CNTL_BBPLL_FORCE_PD (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_M (BIT(10)) +#define RTC_CNTL_BBPLL_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_FORCE_PD_S 10 +/* RTC_CNTL_BBPLL_I2C_FORCE_PU : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: BB_PLL_I2C force power up*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PU (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_M (BIT(9)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PU_S 9 +/* RTC_CNTL_BBPLL_I2C_FORCE_PD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: BB_PLL _I2C force power down*/ +#define RTC_CNTL_BBPLL_I2C_FORCE_PD (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_M (BIT(8)) +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BBPLL_I2C_FORCE_PD_S 8 +/* RTC_CNTL_BB_I2C_FORCE_PU : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: BB_I2C force power up*/ +#define RTC_CNTL_BB_I2C_FORCE_PU (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_M (BIT(7)) +#define RTC_CNTL_BB_I2C_FORCE_PU_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PU_S 7 +/* RTC_CNTL_BB_I2C_FORCE_PD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: BB_I2C force power down*/ +#define RTC_CNTL_BB_I2C_FORCE_PD (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_M (BIT(6)) +#define RTC_CNTL_BB_I2C_FORCE_PD_V 0x1 +#define RTC_CNTL_BB_I2C_FORCE_PD_S 6 +/* RTC_CNTL_SW_PROCPU_RST : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: PRO CPU SW reset*/ +#define RTC_CNTL_SW_PROCPU_RST (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_M (BIT(5)) +#define RTC_CNTL_SW_PROCPU_RST_V 0x1 +#define RTC_CNTL_SW_PROCPU_RST_S 5 +/* RTC_CNTL_SW_APPCPU_RST : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: APP CPU SW reset*/ +#define RTC_CNTL_SW_APPCPU_RST (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_M (BIT(4)) +#define RTC_CNTL_SW_APPCPU_RST_V 0x1 +#define RTC_CNTL_SW_APPCPU_RST_S 4 +/* RTC_CNTL_SW_STALL_PROCPU_C0 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == + 0x86 will stall PRO CPU*/ +#define RTC_CNTL_SW_STALL_PROCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_PROCPU_C0_M ((RTC_CNTL_SW_STALL_PROCPU_C0_V) << (RTC_CNTL_SW_STALL_PROCPU_C0_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_PROCPU_C0_S 2 +/* RTC_CNTL_SW_STALL_APPCPU_C0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == + 0x86 will stall APP CPU*/ +#define RTC_CNTL_SW_STALL_APPCPU_C0 0x00000003 +#define RTC_CNTL_SW_STALL_APPCPU_C0_M ((RTC_CNTL_SW_STALL_APPCPU_C0_V) << (RTC_CNTL_SW_STALL_APPCPU_C0_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C0_V 0x3 +#define RTC_CNTL_SW_STALL_APPCPU_C0_S 0 + +#define RTC_CNTL_SLP_TIMER0_REG (DR_REG_RTCCNTL_BASE + 0x0004) +/* RTC_CNTL_SLP_VAL_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define RTC_CNTL_SLP_VAL_LO 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_M ((RTC_CNTL_SLP_VAL_LO_V) << (RTC_CNTL_SLP_VAL_LO_S)) +#define RTC_CNTL_SLP_VAL_LO_V 0xFFFFFFFF +#define RTC_CNTL_SLP_VAL_LO_S 0 + +#define RTC_CNTL_SLP_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x0008) +/* RTC_CNTL_MAIN_TIMER_ALARM_EN : WO ;bitpos:[16] ;default: 1'h0 ; */ +/*description: timer alarm enable bit*/ +#define RTC_CNTL_MAIN_TIMER_ALARM_EN (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_M (BIT(16)) +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_V 0x1 +#define RTC_CNTL_MAIN_TIMER_ALARM_EN_S 16 +/* RTC_CNTL_SLP_VAL_HI : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC sleep timer high 16 bits*/ +#define RTC_CNTL_SLP_VAL_HI 0x0000FFFF +#define RTC_CNTL_SLP_VAL_HI_M ((RTC_CNTL_SLP_VAL_HI_V) << (RTC_CNTL_SLP_VAL_HI_S)) +#define RTC_CNTL_SLP_VAL_HI_V 0xFFFF +#define RTC_CNTL_SLP_VAL_HI_S 0 + +#define RTC_CNTL_TIME_UPDATE_REG (DR_REG_RTCCNTL_BASE + 0x000C) +/* RTC_CNTL_TIME_UPDATE : WO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: Set 1: to update register with RTC timer*/ +#define RTC_CNTL_TIME_UPDATE (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_M (BIT(31)) +#define RTC_CNTL_TIME_UPDATE_V 0x1 +#define RTC_CNTL_TIME_UPDATE_S 31 +/* RTC_CNTL_TIMER_SYS_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: enable to record system reset time*/ +#define RTC_CNTL_TIMER_SYS_RST (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_M (BIT(29)) +#define RTC_CNTL_TIMER_SYS_RST_V 0x1 +#define RTC_CNTL_TIMER_SYS_RST_S 29 +/* RTC_CNTL_TIMER_XTL_OFF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Enable to record 40M XTAL OFF time*/ +#define RTC_CNTL_TIMER_XTL_OFF (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_M (BIT(28)) +#define RTC_CNTL_TIMER_XTL_OFF_V 0x1 +#define RTC_CNTL_TIMER_XTL_OFF_S 28 +/* RTC_CNTL_TIMER_SYS_STALL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Enable to record system stall time*/ +#define RTC_CNTL_TIMER_SYS_STALL (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_M (BIT(27)) +#define RTC_CNTL_TIMER_SYS_STALL_V 0x1 +#define RTC_CNTL_TIMER_SYS_STALL_S 27 + +#define RTC_CNTL_TIME_LOW0_REG (DR_REG_RTCCNTL_BASE + 0x0010) +/* RTC_CNTL_TIMER_VALUE0_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE0_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_M ((RTC_CNTL_TIMER_VALUE0_LOW_V) << (RTC_CNTL_TIMER_VALUE0_LOW_S)) +#define RTC_CNTL_TIMER_VALUE0_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE0_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH0_REG (DR_REG_RTCCNTL_BASE + 0x0014) +/* RTC_CNTL_TIMER_VALUE0_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE0_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_M ((RTC_CNTL_TIMER_VALUE0_HIGH_V) << (RTC_CNTL_TIMER_VALUE0_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE0_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE0_HIGH_S 0 + +#define RTC_CNTL_STATE0_REG (DR_REG_RTCCNTL_BASE + 0x0018) +/* RTC_CNTL_SLEEP_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: sleep enable bit*/ +#define RTC_CNTL_SLEEP_EN (BIT(31)) +#define RTC_CNTL_SLEEP_EN_M (BIT(31)) +#define RTC_CNTL_SLEEP_EN_V 0x1 +#define RTC_CNTL_SLEEP_EN_S 31 +/* RTC_CNTL_SLP_REJECT : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: leep reject bit*/ +#define RTC_CNTL_SLP_REJECT (BIT(30)) +#define RTC_CNTL_SLP_REJECT_M (BIT(30)) +#define RTC_CNTL_SLP_REJECT_V 0x1 +#define RTC_CNTL_SLP_REJECT_S 30 +/* RTC_CNTL_SLP_WAKEUP : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: leep wakeup bit*/ +#define RTC_CNTL_SLP_WAKEUP (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_M (BIT(29)) +#define RTC_CNTL_SLP_WAKEUP_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_S 29 +/* RTC_CNTL_SDIO_ACTIVE_IND : RO ;bitpos:[28] ;default: 1'd0 ; */ +/*description: SDIO active indication*/ +#define RTC_CNTL_SDIO_ACTIVE_IND (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_M (BIT(28)) +#define RTC_CNTL_SDIO_ACTIVE_IND_V 0x1 +#define RTC_CNTL_SDIO_ACTIVE_IND_S 28 +/* RTC_CNTL_APB2RTC_BRIDGE_SEL : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: APB to RTC using bridge*/ +#define RTC_CNTL_APB2RTC_BRIDGE_SEL (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_M (BIT(22)) +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_V 0x1 +#define RTC_CNTL_APB2RTC_BRIDGE_SEL_S 22 +/* RTC_CNTL_SLP_REJECT_CAUSE_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear rtc sleep reject cause*/ +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_CAUSE_CLR_S 1 +/* RTC_CNTL_SW_CPU_INT : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rtc software interrupt to main cpu*/ +#define RTC_CNTL_SW_CPU_INT (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_M (BIT(0)) +#define RTC_CNTL_SW_CPU_INT_V 0x1 +#define RTC_CNTL_SW_CPU_INT_S 0 + +#define RTC_CNTL_TIMER1_REG (DR_REG_RTCCNTL_BASE + 0x001C) +/* RTC_CNTL_PLL_BUF_WAIT : R/W ;bitpos:[31:24] ;default: 8'd40 ; */ +/*description: PLL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_PLL_BUF_WAIT 0x000000FF +#define RTC_CNTL_PLL_BUF_WAIT_M ((RTC_CNTL_PLL_BUF_WAIT_V) << (RTC_CNTL_PLL_BUF_WAIT_S)) +#define RTC_CNTL_PLL_BUF_WAIT_V 0xFF +#define RTC_CNTL_PLL_BUF_WAIT_S 24 +/* RTC_CNTL_XTL_BUF_WAIT : R/W ;bitpos:[23:14] ;default: 10'd80 ; */ +/*description: XTAL wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_XTL_BUF_WAIT 0x000003FF +#define RTC_CNTL_XTL_BUF_WAIT_M ((RTC_CNTL_XTL_BUF_WAIT_V) << (RTC_CNTL_XTL_BUF_WAIT_S)) +#define RTC_CNTL_XTL_BUF_WAIT_V 0x3FF +#define RTC_CNTL_XTL_BUF_WAIT_S 14 +/* RTC_CNTL_CK8M_WAIT : R/W ;bitpos:[13:6] ;default: 8'h10 ; */ +/*description: CK8M wait cycles in slow_clk_rtc*/ +#define RTC_CNTL_CK8M_WAIT 0x000000FF +#define RTC_CNTL_CK8M_WAIT_M ((RTC_CNTL_CK8M_WAIT_V) << (RTC_CNTL_CK8M_WAIT_S)) +#define RTC_CNTL_CK8M_WAIT_V 0xFF +#define RTC_CNTL_CK8M_WAIT_S 6 +/* RTC_CNTL_CPU_STALL_WAIT : R/W ;bitpos:[5:1] ;default: 5'd1 ; */ +/*description: CPU stall wait cycles in fast_clk_rtc*/ +#define RTC_CNTL_CPU_STALL_WAIT 0x0000001F +#define RTC_CNTL_CPU_STALL_WAIT_M ((RTC_CNTL_CPU_STALL_WAIT_V) << (RTC_CNTL_CPU_STALL_WAIT_S)) +#define RTC_CNTL_CPU_STALL_WAIT_V 0x1F +#define RTC_CNTL_CPU_STALL_WAIT_S 1 +/* RTC_CNTL_CPU_STALL_EN : R/W ;bitpos:[0] ;default: 1'd1 ; */ +/*description: CPU stall enable bit*/ +#define RTC_CNTL_CPU_STALL_EN (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_M (BIT(0)) +#define RTC_CNTL_CPU_STALL_EN_V 0x1 +#define RTC_CNTL_CPU_STALL_EN_S 0 + +#define RTC_CNTL_TIMER2_REG (DR_REG_RTCCNTL_BASE + 0x0020) +/* RTC_CNTL_MIN_TIME_CK8M_OFF : R/W ;bitpos:[31:24] ;default: 8'h1 ; */ +/*description: minimal cycles in slow_clk_rtc for CK8M in power down state*/ +#define RTC_CNTL_MIN_TIME_CK8M_OFF 0x000000FF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_M ((RTC_CNTL_MIN_TIME_CK8M_OFF_V) << (RTC_CNTL_MIN_TIME_CK8M_OFF_S)) +#define RTC_CNTL_MIN_TIME_CK8M_OFF_V 0xFF +#define RTC_CNTL_MIN_TIME_CK8M_OFF_S 24 +/* RTC_CNTL_ULPCP_TOUCH_START_WAIT : R/W ;bitpos:[23:15] ;default: 9'h10 ; */ +/*description: wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller + start to work*/ +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT 0x000001FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_M ((RTC_CNTL_ULPCP_TOUCH_START_WAIT_V) << (RTC_CNTL_ULPCP_TOUCH_START_WAIT_S)) +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_V 0x1FF +#define RTC_CNTL_ULPCP_TOUCH_START_WAIT_S 15 + +#define RTC_CNTL_TIMER3_REG (DR_REG_RTCCNTL_BASE + 0x0024) +/* RTC_CNTL_ROM_RAM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'd10 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_M ((RTC_CNTL_ROM_RAM_POWERUP_TIMER_V) << (RTC_CNTL_ROM_RAM_POWERUP_TIMER_S)) +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_ROM_RAM_POWERUP_TIMER_S 25 +/* RTC_CNTL_ROM_RAM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h16 ; */ +/*description: */ +#define RTC_CNTL_ROM_RAM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_M ((RTC_CNTL_ROM_RAM_WAIT_TIMER_V) << (RTC_CNTL_ROM_RAM_WAIT_TIMER_S)) +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_ROM_RAM_WAIT_TIMER_S 16 +/* RTC_CNTL_WIFI_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_WIFI_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_WIFI_POWERUP_TIMER_M ((RTC_CNTL_WIFI_POWERUP_TIMER_V) << (RTC_CNTL_WIFI_POWERUP_TIMER_S)) +#define RTC_CNTL_WIFI_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_WIFI_POWERUP_TIMER_S 9 +/* RTC_CNTL_WIFI_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WIFI_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WIFI_WAIT_TIMER_M ((RTC_CNTL_WIFI_WAIT_TIMER_V) << (RTC_CNTL_WIFI_WAIT_TIMER_S)) +#define RTC_CNTL_WIFI_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WIFI_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER4_REG (DR_REG_RTCCNTL_BASE + 0x0028) +/* RTC_CNTL_DG_WRAP_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_M ((RTC_CNTL_DG_WRAP_POWERUP_TIMER_V) << (RTC_CNTL_DG_WRAP_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_WRAP_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_WRAP_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_M ((RTC_CNTL_DG_WRAP_WAIT_TIMER_V) << (RTC_CNTL_DG_WRAP_WAIT_TIMER_S)) +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_WRAP_WAIT_TIMER_S 16 +/* RTC_CNTL_POWERUP_TIMER : R/W ;bitpos:[15:9] ;default: 7'h5 ; */ +/*description: */ +#define RTC_CNTL_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_POWERUP_TIMER_M ((RTC_CNTL_POWERUP_TIMER_V) << (RTC_CNTL_POWERUP_TIMER_S)) +#define RTC_CNTL_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_POWERUP_TIMER_S 9 +/* RTC_CNTL_WAIT_TIMER : R/W ;bitpos:[8:0] ;default: 9'h8 ; */ +/*description: */ +#define RTC_CNTL_WAIT_TIMER 0x000001FF +#define RTC_CNTL_WAIT_TIMER_M ((RTC_CNTL_WAIT_TIMER_V) << (RTC_CNTL_WAIT_TIMER_S)) +#define RTC_CNTL_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_WAIT_TIMER_S 0 + +#define RTC_CNTL_TIMER5_REG (DR_REG_RTCCNTL_BASE + 0x002C) +/* RTC_CNTL_RTCMEM_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h9 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_M ((RTC_CNTL_RTCMEM_POWERUP_TIMER_V) << (RTC_CNTL_RTCMEM_POWERUP_TIMER_S)) +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_RTCMEM_POWERUP_TIMER_S 25 +/* RTC_CNTL_RTCMEM_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h14 ; */ +/*description: */ +#define RTC_CNTL_RTCMEM_WAIT_TIMER 0x000001FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_M ((RTC_CNTL_RTCMEM_WAIT_TIMER_V) << (RTC_CNTL_RTCMEM_WAIT_TIMER_S)) +#define RTC_CNTL_RTCMEM_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_RTCMEM_WAIT_TIMER_S 16 +/* RTC_CNTL_MIN_SLP_VAL : R/W ;bitpos:[15:8] ;default: 8'h80 ; */ +/*description: minimal sleep cycles in slow_clk_rtc*/ +#define RTC_CNTL_MIN_SLP_VAL 0x000000FF +#define RTC_CNTL_MIN_SLP_VAL_M ((RTC_CNTL_MIN_SLP_VAL_V) << (RTC_CNTL_MIN_SLP_VAL_S)) +#define RTC_CNTL_MIN_SLP_VAL_V 0xFF +#define RTC_CNTL_MIN_SLP_VAL_S 8 + +#define RTC_CNTL_TIMER6_REG (DR_REG_RTCCNTL_BASE + 0x0030) +/* RTC_CNTL_DG_DCDC_POWERUP_TIMER : R/W ;bitpos:[31:25] ;default: 7'h8 ; */ +/*description: */ +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER 0x0000007F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_M ((RTC_CNTL_DG_DCDC_POWERUP_TIMER_V) << (RTC_CNTL_DG_DCDC_POWERUP_TIMER_S)) +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_V 0x7F +#define RTC_CNTL_DG_DCDC_POWERUP_TIMER_S 25 +/* RTC_CNTL_DG_DCDC_WAIT_TIMER : R/W ;bitpos:[24:16] ;default: 9'h20 ; */ +/*description: */ +#define RTC_CNTL_DG_DCDC_WAIT_TIMER 0x000001FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_M ((RTC_CNTL_DG_DCDC_WAIT_TIMER_V) << (RTC_CNTL_DG_DCDC_WAIT_TIMER_S)) +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_V 0x1FF +#define RTC_CNTL_DG_DCDC_WAIT_TIMER_S 16 + +#define RTC_CNTL_ANA_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0034) +/* RTC_CNTL_PLL_I2C_PU : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_PLL_I2C_PU (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_M (BIT(31)) +#define RTC_CNTL_PLL_I2C_PU_V 0x1 +#define RTC_CNTL_PLL_I2C_PU_S 31 +/* RTC_CNTL_CKGEN_I2C_PU : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: CKGEN_I2C power up*/ +#define RTC_CNTL_CKGEN_I2C_PU (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_M (BIT(30)) +#define RTC_CNTL_CKGEN_I2C_PU_V 0x1 +#define RTC_CNTL_CKGEN_I2C_PU_S 30 +/* RTC_CNTL_RFRX_PBUS_PU : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: 1: RFRX_PBUS power up*/ +#define RTC_CNTL_RFRX_PBUS_PU (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_M (BIT(28)) +#define RTC_CNTL_RFRX_PBUS_PU_V 0x1 +#define RTC_CNTL_RFRX_PBUS_PU_S 28 +/* RTC_CNTL_TXRF_I2C_PU : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: 1: TXRF_I2C power up*/ +#define RTC_CNTL_TXRF_I2C_PU (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_M (BIT(27)) +#define RTC_CNTL_TXRF_I2C_PU_V 0x1 +#define RTC_CNTL_TXRF_I2C_PU_S 27 +/* RTC_CNTL_PVTMON_PU : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: 1: PVTMON power up*/ +#define RTC_CNTL_PVTMON_PU (BIT(26)) +#define RTC_CNTL_PVTMON_PU_M (BIT(26)) +#define RTC_CNTL_PVTMON_PU_V 0x1 +#define RTC_CNTL_PVTMON_PU_S 26 +/* RTC_CNTL_BBPLL_CAL_SLP_START : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: start BBPLL calibration during sleep*/ +#define RTC_CNTL_BBPLL_CAL_SLP_START (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_M (BIT(25)) +#define RTC_CNTL_BBPLL_CAL_SLP_START_V 0x1 +#define RTC_CNTL_BBPLL_CAL_SLP_START_S 25 +/* RTC_CNTL_PLLA_FORCE_PU : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_PLLA_FORCE_PU (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_M (BIT(24)) +#define RTC_CNTL_PLLA_FORCE_PU_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PU_S 24 +/* RTC_CNTL_PLLA_FORCE_PD : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: PLLA force power down*/ +#define RTC_CNTL_PLLA_FORCE_PD (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_M (BIT(23)) +#define RTC_CNTL_PLLA_FORCE_PD_V 0x1 +#define RTC_CNTL_PLLA_FORCE_PD_S 23 +/* RTC_CNTL_SAR_I2C_PU : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: PLLA force power up*/ +#define RTC_CNTL_SAR_I2C_PU (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_M (BIT(22)) +#define RTC_CNTL_SAR_I2C_PU_V 0x1 +#define RTC_CNTL_SAR_I2C_PU_S 22 +/* RTC_CNTL_GLITCH_RST_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_GLITCH_RST_EN (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_M (BIT(20)) +#define RTC_CNTL_GLITCH_RST_EN_V 0x1 +#define RTC_CNTL_GLITCH_RST_EN_S 20 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PU : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PU_S 19 +/* RTC_CNTL_I2C_RESET_POR_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_V 0x1 +#define RTC_CNTL_I2C_RESET_POR_FORCE_PD_S 18 + +#define RTC_CNTL_RESET_STATE_REG (DR_REG_RTCCNTL_BASE + 0x0038) +/* RTC_CNTL_PRO_DRESET_MASK : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PRO_DRESET_MASK (BIT(25)) +#define RTC_CNTL_PRO_DRESET_MASK_M (BIT(25)) +#define RTC_CNTL_PRO_DRESET_MASK_V 0x1 +#define RTC_CNTL_PRO_DRESET_MASK_S 25 +/* RTC_CNTL_APP_DRESET_MASK : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_APP_DRESET_MASK (BIT(24)) +#define RTC_CNTL_APP_DRESET_MASK_M (BIT(24)) +#define RTC_CNTL_APP_DRESET_MASK_V 0x1 +#define RTC_CNTL_APP_DRESET_MASK_S 24 +/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR (BIT(23)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_M (BIT(23)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_CLR_S 23 +/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR (BIT(22)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_M (BIT(22)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_CLR_S 22 +/* RTC_CNTL_RESET_FLAG_JTAG_APPCPU : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU (BIT(21)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_M (BIT(21)) +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_APPCPU_S 21 +/* RTC_CNTL_RESET_FLAG_JTAG_PROCPU : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU (BIT(20)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_M (BIT(20)) +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_JTAG_PROCPU_S 20 +/* RTC_CNTL_PROCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: PROCPU OcdHaltOnReset*/ +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET (BIT(19)) +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_M (BIT(19)) +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_V 0x1 +#define RTC_CNTL_PROCPU_OCD_HALT_ON_RESET_S 19 +/* RTC_CNTL_APPCPU_OCD_HALT_ON_RESET : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: APPCPU OcdHaltOnReset*/ +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET (BIT(18)) +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_M (BIT(18)) +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_V 0x1 +#define RTC_CNTL_APPCPU_OCD_HALT_ON_RESET_S 18 +/* RTC_CNTL_RESET_FLAG_APPCPU_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: clear APP CPU reset flag*/ +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR (BIT(17)) +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_M (BIT(17)) +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_APPCPU_CLR_S 17 +/* RTC_CNTL_RESET_FLAG_PROCPU_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: clear PRO CPU reset_flag*/ +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR (BIT(16)) +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_M (BIT(16)) +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_V 0x1 +#define RTC_CNTL_RESET_FLAG_PROCPU_CLR_S 16 +/* RTC_CNTL_RESET_FLAG_APPCPU : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: APP CPU reset flag*/ +#define RTC_CNTL_RESET_FLAG_APPCPU (BIT(15)) +#define RTC_CNTL_RESET_FLAG_APPCPU_M (BIT(15)) +#define RTC_CNTL_RESET_FLAG_APPCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_APPCPU_S 15 +/* RTC_CNTL_RESET_FLAG_PROCPU : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: PRO CPU reset_flag*/ +#define RTC_CNTL_RESET_FLAG_PROCPU (BIT(14)) +#define RTC_CNTL_RESET_FLAG_PROCPU_M (BIT(14)) +#define RTC_CNTL_RESET_FLAG_PROCPU_V 0x1 +#define RTC_CNTL_RESET_FLAG_PROCPU_S 14 +/* RTC_CNTL_PROCPU_STAT_VECTOR_SEL : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: PRO CPU state vector sel*/ +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_M (BIT(13)) +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_PROCPU_STAT_VECTOR_SEL_S 13 +/* RTC_CNTL_APPCPU_STAT_VECTOR_SEL : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: APP CPU state vector sel*/ +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_M (BIT(12)) +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_V 0x1 +#define RTC_CNTL_APPCPU_STAT_VECTOR_SEL_S 12 +/* RTC_CNTL_RESET_CAUSE_APPCPU : RO ;bitpos:[11:6] ;default: 0 ; */ +/*description: reset cause of APP CPU*/ +#define RTC_CNTL_RESET_CAUSE_APPCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_APPCPU_M ((RTC_CNTL_RESET_CAUSE_APPCPU_V) << (RTC_CNTL_RESET_CAUSE_APPCPU_S)) +#define RTC_CNTL_RESET_CAUSE_APPCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_APPCPU_S 6 +/* RTC_CNTL_RESET_CAUSE_PROCPU : RO ;bitpos:[5:0] ;default: 0 ; */ +/*description: reset cause of PRO CPU*/ +#define RTC_CNTL_RESET_CAUSE_PROCPU 0x0000003F +#define RTC_CNTL_RESET_CAUSE_PROCPU_M ((RTC_CNTL_RESET_CAUSE_PROCPU_V) << (RTC_CNTL_RESET_CAUSE_PROCPU_S)) +#define RTC_CNTL_RESET_CAUSE_PROCPU_V 0x3F +#define RTC_CNTL_RESET_CAUSE_PROCPU_S 0 + +#define RTC_CNTL_WAKEUP_STATE_REG (DR_REG_RTCCNTL_BASE + 0x003C) +/* RTC_CNTL_WAKEUP_ENA : R/W ;bitpos:[31:15] ;default: 17'b1100 ; */ +/*description: wakeup enable bitmap*/ +#define RTC_CNTL_WAKEUP_ENA 0x0001FFFF +#define RTC_CNTL_WAKEUP_ENA_M ((RTC_CNTL_WAKEUP_ENA_V) << (RTC_CNTL_WAKEUP_ENA_S)) +#define RTC_CNTL_WAKEUP_ENA_V 0x1FFFF +#define RTC_CNTL_WAKEUP_ENA_S 15 + +#define RTC_CNTL_INT_ENA_REG (DR_REG_RTCCNTL_BASE + 0x0040) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable cocpu trap interrupt*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_S 16 +/* RTC_CNTL_SWD_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_S 15 +/* RTC_CNTL_SARADC2_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable saradc2 interrupt*/ +#define RTC_CNTL_SARADC2_INT_ENA (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_S 14 +/* RTC_CNTL_COCPU_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: enable riscV cocpu interrupt*/ +#define RTC_CNTL_COCPU_INT_ENA (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_S 13 +/* RTC_CNTL_TSENS_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable tsens interrupt*/ +#define RTC_CNTL_TSENS_INT_ENA (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_S 12 +/* RTC_CNTL_SARADC1_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: enable saradc1 interrupt*/ +#define RTC_CNTL_SARADC1_INT_ENA (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable touch inactive interrupt*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable touch active interrupt*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch done interrupt*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_S 4 +/* RTC_CNTL_WDT_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_S 0 + +#define RTC_CNTL_INT_RAW_REG (DR_REG_RTCCNTL_BASE + 0x0044) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 20 +/* RTC_CNTL_GLITCH_DET_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt_raw*/ +#define RTC_CNTL_GLITCH_DET_INT_RAW (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_RAW_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_RAW_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: touch timeout interrupt raw*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_RAW_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: cocpu trap interrupt raw*/ +#define RTC_CNTL_COCPU_TRAP_INT_RAW (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_RAW_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt raw*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_RAW_S 16 +/* RTC_CNTL_SWD_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt raw*/ +#define RTC_CNTL_SWD_INT_RAW (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_M (BIT(15)) +#define RTC_CNTL_SWD_INT_RAW_V 0x1 +#define RTC_CNTL_SWD_INT_RAW_S 15 +/* RTC_CNTL_SARADC2_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: saradc2 interrupt raw*/ +#define RTC_CNTL_SARADC2_INT_RAW (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC2_INT_RAW_S 14 +/* RTC_CNTL_COCPU_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: riscV cocpu interrupt raw*/ +#define RTC_CNTL_COCPU_INT_RAW (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_RAW_V 0x1 +#define RTC_CNTL_COCPU_INT_RAW_S 13 +/* RTC_CNTL_TSENS_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: tsens interrupt raw*/ +#define RTC_CNTL_TSENS_INT_RAW (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_RAW_V 0x1 +#define RTC_CNTL_TSENS_INT_RAW_S 12 +/* RTC_CNTL_SARADC1_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: saradc1 interrupt raw*/ +#define RTC_CNTL_SARADC1_INT_RAW (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_RAW_V 0x1 +#define RTC_CNTL_SARADC1_INT_RAW_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt raw*/ +#define RTC_CNTL_MAIN_TIMER_INT_RAW (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_RAW_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_RAW_S 10 +/* RTC_CNTL_BROWN_OUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt raw*/ +#define RTC_CNTL_BROWN_OUT_INT_RAW (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_RAW_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_RAW_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: touch inactive interrupt raw*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_RAW_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: touch active interrupt raw*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_RAW_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch interrupt raw*/ +#define RTC_CNTL_TOUCH_DONE_INT_RAW (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_RAW_S 6 +/* RTC_CNTL_ULP_CP_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt raw*/ +#define RTC_CNTL_ULP_CP_INT_RAW (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_RAW_V 0x1 +#define RTC_CNTL_ULP_CP_INT_RAW_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_RAW_S 4 +/* RTC_CNTL_WDT_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt raw*/ +#define RTC_CNTL_WDT_INT_RAW (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_M (BIT(3)) +#define RTC_CNTL_WDT_INT_RAW_V 0x1 +#define RTC_CNTL_WDT_INT_RAW_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt raw*/ +#define RTC_CNTL_SDIO_IDLE_INT_RAW (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_RAW_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_RAW_S 2 +/* RTC_CNTL_SLP_REJECT_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt raw*/ +#define RTC_CNTL_SLP_REJECT_INT_RAW (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_RAW_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt raw*/ +#define RTC_CNTL_SLP_WAKEUP_INT_RAW (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_RAW_S 0 + +#define RTC_CNTL_INT_ST_REG (DR_REG_RTCCNTL_BASE + 0x0048) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: glitch_det_interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_ST (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ST_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ST_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ST_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: cocpu trap interrupt state*/ +#define RTC_CNTL_COCPU_TRAP_INT_ST (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ST_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: xtal32k dead detection interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ST (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ST_S 16 +/* RTC_CNTL_SWD_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_ST (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ST_V 0x1 +#define RTC_CNTL_SWD_INT_ST_S 15 +/* RTC_CNTL_SARADC2_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: saradc2 interrupt state*/ +#define RTC_CNTL_SARADC2_INT_ST (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ST_V 0x1 +#define RTC_CNTL_SARADC2_INT_ST_S 14 +/* RTC_CNTL_COCPU_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: riscV cocpu interrupt state*/ +#define RTC_CNTL_COCPU_INT_ST (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ST_V 0x1 +#define RTC_CNTL_COCPU_INT_ST_S 13 +/* RTC_CNTL_TSENS_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: tsens interrupt state*/ +#define RTC_CNTL_TSENS_INT_ST (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ST_V 0x1 +#define RTC_CNTL_TSENS_INT_ST_S 12 +/* RTC_CNTL_SARADC1_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: saradc1 interrupt state*/ +#define RTC_CNTL_SARADC1_INT_ST (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ST_V 0x1 +#define RTC_CNTL_SARADC1_INT_ST_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_ST (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ST_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ST_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_ST (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ST_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ST_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: touch inactive interrupt state*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ST_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: touch active interrupt state*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ST_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: touch done interrupt state*/ +#define RTC_CNTL_TOUCH_DONE_INT_ST (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ST_S 6 +/* RTC_CNTL_ULP_CP_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ULP-coprocessor interrupt state*/ +#define RTC_CNTL_ULP_CP_INT_ST (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ST_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ST_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ST_S 4 +/* RTC_CNTL_WDT_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_ST (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ST_V 0x1 +#define RTC_CNTL_WDT_INT_ST_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_ST (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ST_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ST_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_ST (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ST_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ST_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ST (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ST_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ST_S 0 + +#define RTC_CNTL_INT_CLR_REG (DR_REG_RTCCNTL_BASE + 0x004C) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 20 +/* RTC_CNTL_GLITCH_DET_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: Clear glitch det interrupt state*/ +#define RTC_CNTL_GLITCH_DET_INT_CLR (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_CLR_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_CLR_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Clear touch timeout interrupt state*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_CLR_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Clear cocpu trap interrupt state*/ +#define RTC_CNTL_COCPU_TRAP_INT_CLR (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_CLR_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_CLR_S 16 +/* RTC_CNTL_SWD_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: Clear super watch dog interrupt state*/ +#define RTC_CNTL_SWD_INT_CLR (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_M (BIT(15)) +#define RTC_CNTL_SWD_INT_CLR_V 0x1 +#define RTC_CNTL_SWD_INT_CLR_S 15 +/* RTC_CNTL_SARADC2_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Clear saradc2 interrupt state*/ +#define RTC_CNTL_SARADC2_INT_CLR (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC2_INT_CLR_S 14 +/* RTC_CNTL_COCPU_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: Clear riscV cocpu interrupt state*/ +#define RTC_CNTL_COCPU_INT_CLR (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_CLR_V 0x1 +#define RTC_CNTL_COCPU_INT_CLR_S 13 +/* RTC_CNTL_TSENS_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Clear tsens interrupt state*/ +#define RTC_CNTL_TSENS_INT_CLR (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_CLR_V 0x1 +#define RTC_CNTL_TSENS_INT_CLR_S 12 +/* RTC_CNTL_SARADC1_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: Clear saradc1 interrupt state*/ +#define RTC_CNTL_SARADC1_INT_CLR (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_CLR_V 0x1 +#define RTC_CNTL_SARADC1_INT_CLR_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Clear RTC main timer interrupt state*/ +#define RTC_CNTL_MAIN_TIMER_INT_CLR (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_CLR_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_CLR_S 10 +/* RTC_CNTL_BROWN_OUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Clear brown out interrupt state*/ +#define RTC_CNTL_BROWN_OUT_INT_CLR (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_CLR_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Clear touch inactive interrupt state*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_CLR_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Clear touch active interrupt state*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_CLR_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Clear touch done interrupt state*/ +#define RTC_CNTL_TOUCH_DONE_INT_CLR (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_CLR_S 6 +/* RTC_CNTL_ULP_CP_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Clear ULP-coprocessor interrupt state*/ +#define RTC_CNTL_ULP_CP_INT_CLR (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_INT_CLR_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_CLR_S 4 +/* RTC_CNTL_WDT_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Clear RTC WDT interrupt state*/ +#define RTC_CNTL_WDT_INT_CLR (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_M (BIT(3)) +#define RTC_CNTL_WDT_INT_CLR_V 0x1 +#define RTC_CNTL_WDT_INT_CLR_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Clear SDIO idle interrupt state*/ +#define RTC_CNTL_SDIO_IDLE_INT_CLR (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_CLR_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_CLR_S 2 +/* RTC_CNTL_SLP_REJECT_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Clear sleep reject interrupt state*/ +#define RTC_CNTL_SLP_REJECT_INT_CLR (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_CLR_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Clear sleep wakeup interrupt state*/ +#define RTC_CNTL_SLP_WAKEUP_INT_CLR (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_CLR_S 0 + +#define RTC_CNTL_STORE0_REG (DR_REG_RTCCNTL_BASE + 0x0050) +/* RTC_CNTL_SCRATCH0 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH0 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_M ((RTC_CNTL_SCRATCH0_V) << (RTC_CNTL_SCRATCH0_S)) +#define RTC_CNTL_SCRATCH0_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH0_S 0 + +#define RTC_CNTL_STORE1_REG (DR_REG_RTCCNTL_BASE + 0x0054) +/* RTC_CNTL_SCRATCH1 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH1 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_M ((RTC_CNTL_SCRATCH1_V) << (RTC_CNTL_SCRATCH1_S)) +#define RTC_CNTL_SCRATCH1_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH1_S 0 + +#define RTC_CNTL_STORE2_REG (DR_REG_RTCCNTL_BASE + 0x0058) +/* RTC_CNTL_SCRATCH2 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH2 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_M ((RTC_CNTL_SCRATCH2_V) << (RTC_CNTL_SCRATCH2_S)) +#define RTC_CNTL_SCRATCH2_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH2_S 0 + +#define RTC_CNTL_STORE3_REG (DR_REG_RTCCNTL_BASE + 0x005C) +/* RTC_CNTL_SCRATCH3 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH3 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_M ((RTC_CNTL_SCRATCH3_V) << (RTC_CNTL_SCRATCH3_S)) +#define RTC_CNTL_SCRATCH3_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH3_S 0 + +#define RTC_CNTL_EXT_XTL_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0060) +/* RTC_CNTL_XTL_EXT_CTR_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_XTL_EXT_CTR_EN (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_M (BIT(31)) +#define RTC_CNTL_XTL_EXT_CTR_EN_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_EN_S 31 +/* RTC_CNTL_XTL_EXT_CTR_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: power down XTAL at high level*/ +#define RTC_CNTL_XTL_EXT_CTR_LV (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_M (BIT(30)) +#define RTC_CNTL_XTL_EXT_CTR_LV_V 0x1 +#define RTC_CNTL_XTL_EXT_CTR_LV_S 30 +/* RTC_CNTL_XTAL32K_GPIO_SEL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: XTAL_32K sel. 0: external XTAL_32K*/ +#define RTC_CNTL_XTAL32K_GPIO_SEL (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_M (BIT(23)) +#define RTC_CNTL_XTAL32K_GPIO_SEL_V 0x1 +#define RTC_CNTL_XTAL32K_GPIO_SEL_S 23 +/* RTC_CNTL_WDT_STATE : RO ;bitpos:[22:20] ;default: 3'h0 ; */ +/*description: state of 32k_wdt*/ +#define RTC_CNTL_WDT_STATE 0x00000007 +#define RTC_CNTL_WDT_STATE_M ((RTC_CNTL_WDT_STATE_V) << (RTC_CNTL_WDT_STATE_S)) +#define RTC_CNTL_WDT_STATE_V 0x7 +#define RTC_CNTL_WDT_STATE_S 20 +/* RTC_CNTL_DAC_XTAL_32K : R/W ;bitpos:[19:17] ;default: 3'd3 ; */ +/*description: DAC_XTAL_32K*/ +#define RTC_CNTL_DAC_XTAL_32K 0x00000007 +#define RTC_CNTL_DAC_XTAL_32K_M ((RTC_CNTL_DAC_XTAL_32K_V) << (RTC_CNTL_DAC_XTAL_32K_S)) +#define RTC_CNTL_DAC_XTAL_32K_V 0x7 +#define RTC_CNTL_DAC_XTAL_32K_S 17 +/* RTC_CNTL_XPD_XTAL_32K : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: XPD_XTAL_32K*/ +#define RTC_CNTL_XPD_XTAL_32K (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_M (BIT(16)) +#define RTC_CNTL_XPD_XTAL_32K_V 0x1 +#define RTC_CNTL_XPD_XTAL_32K_S 16 +/* RTC_CNTL_DRES_XTAL_32K : R/W ;bitpos:[15:13] ;default: 3'd3 ; */ +/*description: DRES_XTAL_32K*/ +#define RTC_CNTL_DRES_XTAL_32K 0x00000007 +#define RTC_CNTL_DRES_XTAL_32K_M ((RTC_CNTL_DRES_XTAL_32K_V) << (RTC_CNTL_DRES_XTAL_32K_S)) +#define RTC_CNTL_DRES_XTAL_32K_V 0x7 +#define RTC_CNTL_DRES_XTAL_32K_S 13 +/* RTC_CNTL_DGM_XTAL_32K : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: xtal_32k gm control*/ +#define RTC_CNTL_DGM_XTAL_32K 0x00000007 +#define RTC_CNTL_DGM_XTAL_32K_M ((RTC_CNTL_DGM_XTAL_32K_V) << (RTC_CNTL_DGM_XTAL_32K_S)) +#define RTC_CNTL_DGM_XTAL_32K_V 0x7 +#define RTC_CNTL_DGM_XTAL_32K_S 10 +/* RTC_CNTL_DBUF_XTAL_32K : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 0: single-end buffer 1: differential buffer*/ +#define RTC_CNTL_DBUF_XTAL_32K (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_M (BIT(9)) +#define RTC_CNTL_DBUF_XTAL_32K_V 0x1 +#define RTC_CNTL_DBUF_XTAL_32K_S 9 +/* RTC_CNTL_ENCKINIT_XTAL_32K : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: apply an internal clock to help xtal 32k to start*/ +#define RTC_CNTL_ENCKINIT_XTAL_32K (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_M (BIT(8)) +#define RTC_CNTL_ENCKINIT_XTAL_32K_V 0x1 +#define RTC_CNTL_ENCKINIT_XTAL_32K_S 8 +/* RTC_CNTL_XTAL32K_XPD_FORCE : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: Xtal 32k xpd control by sw or fsm*/ +#define RTC_CNTL_XTAL32K_XPD_FORCE (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_M (BIT(7)) +#define RTC_CNTL_XTAL32K_XPD_FORCE_V 0x1 +#define RTC_CNTL_XTAL32K_XPD_FORCE_S 7 +/* RTC_CNTL_XTAL32K_AUTO_RETURN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: xtal 32k switch back xtal when xtal is restarted*/ +#define RTC_CNTL_XTAL32K_AUTO_RETURN (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_M (BIT(6)) +#define RTC_CNTL_XTAL32K_AUTO_RETURN_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RETURN_S 6 +/* RTC_CNTL_XTAL32K_AUTO_RESTART : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: xtal 32k restart xtal when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_RESTART (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_M (BIT(5)) +#define RTC_CNTL_XTAL32K_AUTO_RESTART_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_RESTART_S 5 +/* RTC_CNTL_XTAL32K_AUTO_BACKUP : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: xtal 32k switch to back up clock when xtal is dead*/ +#define RTC_CNTL_XTAL32K_AUTO_BACKUP (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_M (BIT(4)) +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_V 0x1 +#define RTC_CNTL_XTAL32K_AUTO_BACKUP_S 4 +/* RTC_CNTL_XTAL32K_EXT_CLK_FO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: xtal 32k external xtal clock force on*/ +#define RTC_CNTL_XTAL32K_EXT_CLK_FO (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_M (BIT(3)) +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_EXT_CLK_FO_S 3 +/* RTC_CNTL_XTAL32K_WDT_RESET : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog sw reset*/ +#define RTC_CNTL_XTAL32K_WDT_RESET (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_M (BIT(2)) +#define RTC_CNTL_XTAL32K_WDT_RESET_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_RESET_S 2 +/* RTC_CNTL_XTAL32K_WDT_CLK_FO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog clock force on*/ +#define RTC_CNTL_XTAL32K_WDT_CLK_FO (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_M (BIT(1)) +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_CLK_FO_S 1 +/* RTC_CNTL_XTAL32K_WDT_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: xtal 32k watch dog enable*/ +#define RTC_CNTL_XTAL32K_WDT_EN (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_M (BIT(0)) +#define RTC_CNTL_XTAL32K_WDT_EN_V 0x1 +#define RTC_CNTL_XTAL32K_WDT_EN_S 0 + +#define RTC_CNTL_EXT_WAKEUP_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0064) +/* RTC_CNTL_EXT_WAKEUP1_LV : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_EXT_WAKEUP1_LV (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_M (BIT(31)) +#define RTC_CNTL_EXT_WAKEUP1_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_LV_S 31 +/* RTC_CNTL_EXT_WAKEUP0_LV : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: 0: external wakeup at low level*/ +#define RTC_CNTL_EXT_WAKEUP0_LV (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_M (BIT(30)) +#define RTC_CNTL_EXT_WAKEUP0_LV_V 0x1 +#define RTC_CNTL_EXT_WAKEUP0_LV_S 30 +/* RTC_CNTL_GPIO_WAKEUP_FILTER : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: enable filter for gpio wakeup event*/ +#define RTC_CNTL_GPIO_WAKEUP_FILTER (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_M (BIT(29)) +#define RTC_CNTL_GPIO_WAKEUP_FILTER_V 0x1 +#define RTC_CNTL_GPIO_WAKEUP_FILTER_S 29 + +#define RTC_CNTL_SLP_REJECT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0068) +/* RTC_CNTL_DEEP_SLP_REJECT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: enable reject for deep sleep*/ +#define RTC_CNTL_DEEP_SLP_REJECT_EN (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_M (BIT(31)) +#define RTC_CNTL_DEEP_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_DEEP_SLP_REJECT_EN_S 31 +/* RTC_CNTL_LIGHT_SLP_REJECT_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: enable reject for light sleep*/ +#define RTC_CNTL_LIGHT_SLP_REJECT_EN (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_M (BIT(30)) +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_V 0x1 +#define RTC_CNTL_LIGHT_SLP_REJECT_EN_S 30 +/* RTC_CNTL_SLEEP_REJECT_ENA : R/W ;bitpos:[29:12] ;default: 17'd0 ; */ +/*description: sleep reject enable*/ +#define RTC_CNTL_SLEEP_REJECT_ENA 0x0003FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_M ((RTC_CNTL_SLEEP_REJECT_ENA_V) << (RTC_CNTL_SLEEP_REJECT_ENA_S)) +#define RTC_CNTL_SLEEP_REJECT_ENA_V 0x3FFFF +#define RTC_CNTL_SLEEP_REJECT_ENA_S 12 + +#define RTC_CNTL_CPU_PERIOD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x006C) +/* RTC_CNTL_CPUPERIOD_SEL : R/W ;bitpos:[31:30] ;default: 2'b00 ; */ +/*description: */ +#define RTC_CNTL_CPUPERIOD_SEL 0x00000003 +#define RTC_CNTL_CPUPERIOD_SEL_M ((RTC_CNTL_CPUPERIOD_SEL_V) << (RTC_CNTL_CPUPERIOD_SEL_S)) +#define RTC_CNTL_CPUPERIOD_SEL_V 0x3 +#define RTC_CNTL_CPUPERIOD_SEL_S 30 +/* RTC_CNTL_CPUSEL_CONF : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: CPU sel option*/ +#define RTC_CNTL_CPUSEL_CONF (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_M (BIT(29)) +#define RTC_CNTL_CPUSEL_CONF_V 0x1 +#define RTC_CNTL_CPUSEL_CONF_S 29 + +#define RTC_CNTL_SDIO_ACT_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0070) +/* RTC_CNTL_SDIO_ACT_DNUM : R/W ;bitpos:[31:22] ;default: 10'b0 ; */ +/*description: */ +#define RTC_CNTL_SDIO_ACT_DNUM 0x000003FF +#define RTC_CNTL_SDIO_ACT_DNUM_M ((RTC_CNTL_SDIO_ACT_DNUM_V) << (RTC_CNTL_SDIO_ACT_DNUM_S)) +#define RTC_CNTL_SDIO_ACT_DNUM_V 0x3FF +#define RTC_CNTL_SDIO_ACT_DNUM_S 22 + +#define RTC_CNTL_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0074) +/* RTC_CNTL_ANA_CLK_RTC_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_RTC_SEL 0x00000003 +#define RTC_CNTL_ANA_CLK_RTC_SEL_M ((RTC_CNTL_ANA_CLK_RTC_SEL_V) << (RTC_CNTL_ANA_CLK_RTC_SEL_S)) +#define RTC_CNTL_ANA_CLK_RTC_SEL_V 0x3 +#define RTC_CNTL_ANA_CLK_RTC_SEL_S 30 +/* RTC_CNTL_FAST_CLK_RTC_SEL : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: fast_clk_rtc sel. 0: XTAL div 4*/ +#define RTC_CNTL_FAST_CLK_RTC_SEL (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_M (BIT(29)) +#define RTC_CNTL_FAST_CLK_RTC_SEL_V 0x1 +#define RTC_CNTL_FAST_CLK_RTC_SEL_S 29 +/* RTC_CNTL_CK8M_FORCE_PU : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: CK8M force power up*/ +#define RTC_CNTL_CK8M_FORCE_PU (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_M (BIT(26)) +#define RTC_CNTL_CK8M_FORCE_PU_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PU_S 26 +/* RTC_CNTL_CK8M_FORCE_PD : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: CK8M force power down*/ +#define RTC_CNTL_CK8M_FORCE_PD (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_M (BIT(25)) +#define RTC_CNTL_CK8M_FORCE_PD_V 0x1 +#define RTC_CNTL_CK8M_FORCE_PD_S 25 +/* RTC_CNTL_CK8M_DFREQ : R/W ;bitpos:[24:17] ;default: 8'd172 ; */ +/*description: CK8M_DFREQ*/ +#define RTC_CNTL_CK8M_DFREQ 0x000000FF +#define RTC_CNTL_CK8M_DFREQ_M ((RTC_CNTL_CK8M_DFREQ_V) << (RTC_CNTL_CK8M_DFREQ_S)) +#define RTC_CNTL_CK8M_DFREQ_V 0xFF +#define RTC_CNTL_CK8M_DFREQ_S 17 +/* RTC_CNTL_CK8M_FORCE_NOGATING : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: CK8M force no gating during sleep*/ +#define RTC_CNTL_CK8M_FORCE_NOGATING (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_M (BIT(16)) +#define RTC_CNTL_CK8M_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_CK8M_FORCE_NOGATING_S 16 +/* RTC_CNTL_XTAL_FORCE_NOGATING : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: XTAL force no gating during sleep*/ +#define RTC_CNTL_XTAL_FORCE_NOGATING (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_M (BIT(15)) +#define RTC_CNTL_XTAL_FORCE_NOGATING_V 0x1 +#define RTC_CNTL_XTAL_FORCE_NOGATING_S 15 +/* RTC_CNTL_CK8M_DIV_SEL : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: divider = reg_ck8m_div_sel + 1*/ +#define RTC_CNTL_CK8M_DIV_SEL 0x00000007 +#define RTC_CNTL_CK8M_DIV_SEL_M ((RTC_CNTL_CK8M_DIV_SEL_V) << (RTC_CNTL_CK8M_DIV_SEL_S)) +#define RTC_CNTL_CK8M_DIV_SEL_V 0x7 +#define RTC_CNTL_CK8M_DIV_SEL_S 12 +/* RTC_CNTL_DIG_CLK8M_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable CK8M for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_EN (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_M (BIT(10)) +#define RTC_CNTL_DIG_CLK8M_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_EN_S 10 +/* RTC_CNTL_DIG_CLK8M_D256_EN : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_CLK8M_D256_EN (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_M (BIT(9)) +#define RTC_CNTL_DIG_CLK8M_D256_EN_V 0x1 +#define RTC_CNTL_DIG_CLK8M_D256_EN_S 9 +/* RTC_CNTL_DIG_XTAL32K_EN : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ +#define RTC_CNTL_DIG_XTAL32K_EN (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_M (BIT(8)) +#define RTC_CNTL_DIG_XTAL32K_EN_V 0x1 +#define RTC_CNTL_DIG_XTAL32K_EN_S 8 +/* RTC_CNTL_ENB_CK8M_DIV : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: 1: CK8M_D256_OUT is actually CK8M*/ +#define RTC_CNTL_ENB_CK8M_DIV (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_M (BIT(7)) +#define RTC_CNTL_ENB_CK8M_DIV_V 0x1 +#define RTC_CNTL_ENB_CK8M_DIV_S 7 +/* RTC_CNTL_ENB_CK8M : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: disable CK8M and CK8M_D256_OUT*/ +#define RTC_CNTL_ENB_CK8M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_M (BIT(6)) +#define RTC_CNTL_ENB_CK8M_V 0x1 +#define RTC_CNTL_ENB_CK8M_S 6 +/* RTC_CNTL_CK8M_DIV : R/W ;bitpos:[5:4] ;default: 2'b01 ; */ +/*description: CK8M_D256_OUT divider. 00: div128*/ +#define RTC_CNTL_CK8M_DIV 0x00000003 +#define RTC_CNTL_CK8M_DIV_M ((RTC_CNTL_CK8M_DIV_V) << (RTC_CNTL_CK8M_DIV_S)) +#define RTC_CNTL_CK8M_DIV_V 0x3 +#define RTC_CNTL_CK8M_DIV_S 4 +/* RTC_CNTL_CK8M_DIV_SEL_VLD : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ +#define RTC_CNTL_CK8M_DIV_SEL_VLD (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_M (BIT(3)) +#define RTC_CNTL_CK8M_DIV_SEL_VLD_V 0x1 +#define RTC_CNTL_CK8M_DIV_SEL_VLD_S 3 + +#define RTC_CNTL_SLOW_CLK_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0078) +/* RTC_CNTL_SLOW_CLK_NEXT_EDGE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_M (BIT(31)) +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_V 0x1 +#define RTC_CNTL_SLOW_CLK_NEXT_EDGE_S 31 +/* RTC_CNTL_ANA_CLK_DIV : R/W ;bitpos:[30:23] ;default: 8'd0 ; */ +/*description: */ +#define RTC_CNTL_ANA_CLK_DIV 0x000000FF +#define RTC_CNTL_ANA_CLK_DIV_M ((RTC_CNTL_ANA_CLK_DIV_V) << (RTC_CNTL_ANA_CLK_DIV_S)) +#define RTC_CNTL_ANA_CLK_DIV_V 0xFF +#define RTC_CNTL_ANA_CLK_DIV_S 23 +/* RTC_CNTL_ANA_CLK_DIV_VLD : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ +#define RTC_CNTL_ANA_CLK_DIV_VLD (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_M (BIT(22)) +#define RTC_CNTL_ANA_CLK_DIV_VLD_V 0x1 +#define RTC_CNTL_ANA_CLK_DIV_VLD_S 22 + +#define RTC_CNTL_SDIO_CONF_REG (DR_REG_RTCCNTL_BASE + 0x007C) +/* RTC_CNTL_XPD_SDIO_REG : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_XPD_SDIO_REG (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_M (BIT(31)) +#define RTC_CNTL_XPD_SDIO_REG_V 0x1 +#define RTC_CNTL_XPD_SDIO_REG_S 31 +/* RTC_CNTL_DREFH_SDIO : R/W ;bitpos:[30:29] ;default: 2'b00 ; */ +/*description: SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFH_SDIO 0x00000003 +#define RTC_CNTL_DREFH_SDIO_M ((RTC_CNTL_DREFH_SDIO_V) << (RTC_CNTL_DREFH_SDIO_S)) +#define RTC_CNTL_DREFH_SDIO_V 0x3 +#define RTC_CNTL_DREFH_SDIO_S 29 +/* RTC_CNTL_DREFM_SDIO : R/W ;bitpos:[28:27] ;default: 2'b01 ; */ +/*description: SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFM_SDIO 0x00000003 +#define RTC_CNTL_DREFM_SDIO_M ((RTC_CNTL_DREFM_SDIO_V) << (RTC_CNTL_DREFM_SDIO_S)) +#define RTC_CNTL_DREFM_SDIO_V 0x3 +#define RTC_CNTL_DREFM_SDIO_S 27 +/* RTC_CNTL_DREFL_SDIO : R/W ;bitpos:[26:25] ;default: 2'b01 ; */ +/*description: SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_DREFL_SDIO 0x00000003 +#define RTC_CNTL_DREFL_SDIO_M ((RTC_CNTL_DREFL_SDIO_V) << (RTC_CNTL_DREFL_SDIO_S)) +#define RTC_CNTL_DREFL_SDIO_V 0x3 +#define RTC_CNTL_DREFL_SDIO_S 25 +/* RTC_CNTL_REG1P8_READY : RO ;bitpos:[24] ;default: 1'd0 ; */ +/*description: read only register for REG1P8_READY*/ +#define RTC_CNTL_REG1P8_READY (BIT(24)) +#define RTC_CNTL_REG1P8_READY_M (BIT(24)) +#define RTC_CNTL_REG1P8_READY_V 0x1 +#define RTC_CNTL_REG1P8_READY_S 24 +/* RTC_CNTL_SDIO_TIEH : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ +#define RTC_CNTL_SDIO_TIEH (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_M (BIT(23)) +#define RTC_CNTL_SDIO_TIEH_V 0x1 +#define RTC_CNTL_SDIO_TIEH_S 23 +/* RTC_CNTL_SDIO_FORCE : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: 1: use SW option to control SDIO_REG*/ +#define RTC_CNTL_SDIO_FORCE (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_M (BIT(22)) +#define RTC_CNTL_SDIO_FORCE_V 0x1 +#define RTC_CNTL_SDIO_FORCE_S 22 +/* RTC_CNTL_SDIO_PD_EN : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ +#define RTC_CNTL_SDIO_PD_EN (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_M (BIT(21)) +#define RTC_CNTL_SDIO_PD_EN_V 0x1 +#define RTC_CNTL_SDIO_PD_EN_S 21 +/* RTC_CNTL_SDIO_ENCURLIM : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: enable current limit*/ +#define RTC_CNTL_SDIO_ENCURLIM (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_M (BIT(20)) +#define RTC_CNTL_SDIO_ENCURLIM_V 0x1 +#define RTC_CNTL_SDIO_ENCURLIM_S 20 +/* RTC_CNTL_SDIO_MODECURLIM : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: select current limit mode*/ +#define RTC_CNTL_SDIO_MODECURLIM (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_M (BIT(19)) +#define RTC_CNTL_SDIO_MODECURLIM_V 0x1 +#define RTC_CNTL_SDIO_MODECURLIM_S 19 +/* RTC_CNTL_SDIO_DCURLIM : R/W ;bitpos:[18:16] ;default: 3'd0 ; */ +/*description: tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ +#define RTC_CNTL_SDIO_DCURLIM 0x00000007 +#define RTC_CNTL_SDIO_DCURLIM_M ((RTC_CNTL_SDIO_DCURLIM_V) << (RTC_CNTL_SDIO_DCURLIM_S)) +#define RTC_CNTL_SDIO_DCURLIM_V 0x7 +#define RTC_CNTL_SDIO_DCURLIM_S 16 +/* RTC_CNTL_SDIO_EN_INITI : R/W ;bitpos:[15] ;default: 1'd1 ; */ +/*description: 0 to set init[1:0]=0*/ +#define RTC_CNTL_SDIO_EN_INITI (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_M (BIT(15)) +#define RTC_CNTL_SDIO_EN_INITI_V 0x1 +#define RTC_CNTL_SDIO_EN_INITI_S 15 +/* RTC_CNTL_SDIO_INITI : R/W ;bitpos:[14:13] ;default: 2'd1 ; */ +/*description: add resistor from ldo output to ground. 0: no res*/ +#define RTC_CNTL_SDIO_INITI 0x00000003 +#define RTC_CNTL_SDIO_INITI_M ((RTC_CNTL_SDIO_INITI_V) << (RTC_CNTL_SDIO_INITI_S)) +#define RTC_CNTL_SDIO_INITI_V 0x3 +#define RTC_CNTL_SDIO_INITI_S 13 +/* RTC_CNTL_SDIO_DCAP : R/W ;bitpos:[12:11] ;default: 2'b11 ; */ +/*description: ability to prevent LDO from overshoot*/ +#define RTC_CNTL_SDIO_DCAP 0x00000003 +#define RTC_CNTL_SDIO_DCAP_M ((RTC_CNTL_SDIO_DCAP_V) << (RTC_CNTL_SDIO_DCAP_S)) +#define RTC_CNTL_SDIO_DCAP_V 0x3 +#define RTC_CNTL_SDIO_DCAP_S 11 +/* RTC_CNTL_SDIO_DTHDRV : R/W ;bitpos:[10:9] ;default: 2'b11 ; */ +/*description: Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ +#define RTC_CNTL_SDIO_DTHDRV 0x00000003 +#define RTC_CNTL_SDIO_DTHDRV_M ((RTC_CNTL_SDIO_DTHDRV_V) << (RTC_CNTL_SDIO_DTHDRV_S)) +#define RTC_CNTL_SDIO_DTHDRV_V 0x3 +#define RTC_CNTL_SDIO_DTHDRV_S 9 +/* RTC_CNTL_SDIO_TIMER_TARGET : R/W ;bitpos:[7:0] ;default: 8'd10 ; */ +/*description: timer count to apply reg_sdio_dcap after sdio power on*/ +#define RTC_CNTL_SDIO_TIMER_TARGET 0x000000FF +#define RTC_CNTL_SDIO_TIMER_TARGET_M ((RTC_CNTL_SDIO_TIMER_TARGET_V) << (RTC_CNTL_SDIO_TIMER_TARGET_S)) +#define RTC_CNTL_SDIO_TIMER_TARGET_V 0xFF +#define RTC_CNTL_SDIO_TIMER_TARGET_S 0 + +#define RTC_CNTL_BIAS_CONF_REG (DR_REG_RTCCNTL_BASE + 0x0080) +/* RTC_CNTL_DBG_ATTEN_MONITOR : R/W ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in monitor state*/ +#define RTC_CNTL_DBG_ATTEN_MONITOR 0x0000000F +#define RTC_CNTL_DBG_ATTEN_MONITOR_M ((RTC_CNTL_DBG_ATTEN_MONITOR_V) << (RTC_CNTL_DBG_ATTEN_MONITOR_S)) +#define RTC_CNTL_DBG_ATTEN_MONITOR_V 0xF +#define RTC_CNTL_DBG_ATTEN_MONITOR_S 22 +/* RTC_CNTL_DBG_ATTEN_DEEP_SLP : R/W ;bitpos:[21:18] ;default: 4'd0 ; */ +/*description: DBG_ATTEN when rtc in sleep state*/ +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP 0x0000000F +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_M ((RTC_CNTL_DBG_ATTEN_DEEP_SLP_V) << (RTC_CNTL_DBG_ATTEN_DEEP_SLP_S)) +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_V 0xF +#define RTC_CNTL_DBG_ATTEN_DEEP_SLP_S 18 +/* RTC_CNTL_BIAS_SLEEP_MONITOR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: bias_sleep when rtc in monitor state*/ +#define RTC_CNTL_BIAS_SLEEP_MONITOR (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_M (BIT(17)) +#define RTC_CNTL_BIAS_SLEEP_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_MONITOR_S 17 +/* RTC_CNTL_BIAS_SLEEP_DEEP_SLP : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: bias_sleep when rtc in sleep_state*/ +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_M (BIT(16)) +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_SLEEP_DEEP_SLP_S 16 +/* RTC_CNTL_PD_CUR_MONITOR : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in monitor state*/ +#define RTC_CNTL_PD_CUR_MONITOR (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_M (BIT(15)) +#define RTC_CNTL_PD_CUR_MONITOR_V 0x1 +#define RTC_CNTL_PD_CUR_MONITOR_S 15 +/* RTC_CNTL_PD_CUR_DEEP_SLP : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: xpd cur when rtc in sleep_state*/ +#define RTC_CNTL_PD_CUR_DEEP_SLP (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_M (BIT(14)) +#define RTC_CNTL_PD_CUR_DEEP_SLP_V 0x1 +#define RTC_CNTL_PD_CUR_DEEP_SLP_S 14 +/* RTC_CNTL_BIAS_BUF_MONITOR : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_MONITOR (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_M (BIT(13)) +#define RTC_CNTL_BIAS_BUF_MONITOR_V 0x1 +#define RTC_CNTL_BIAS_BUF_MONITOR_S 13 +/* RTC_CNTL_BIAS_BUF_DEEP_SLP : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_DEEP_SLP (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_M (BIT(12)) +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_V 0x1 +#define RTC_CNTL_BIAS_BUF_DEEP_SLP_S 12 +/* RTC_CNTL_BIAS_BUF_WAKE : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_WAKE (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_M (BIT(11)) +#define RTC_CNTL_BIAS_BUF_WAKE_V 0x1 +#define RTC_CNTL_BIAS_BUF_WAKE_S 11 +/* RTC_CNTL_BIAS_BUF_IDLE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BIAS_BUF_IDLE (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_M (BIT(10)) +#define RTC_CNTL_BIAS_BUF_IDLE_V 0x1 +#define RTC_CNTL_BIAS_BUF_IDLE_S 10 + +#define RTC_CNTL_REG (DR_REG_RTCCNTL_BASE + 0x0084) +/* RTC_CNTL_REGULATOR_FORCE_PU : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_REGULATOR_FORCE_PU (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_M (BIT(31)) +#define RTC_CNTL_REGULATOR_FORCE_PU_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PU_S 31 +/* RTC_CNTL_REGULATOR_FORCE_PD : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: RTC_REG force power down (for RTC_REG power down means decrease + the voltage to 0.8v or lower )*/ +#define RTC_CNTL_REGULATOR_FORCE_PD (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_M (BIT(30)) +#define RTC_CNTL_REGULATOR_FORCE_PD_V 0x1 +#define RTC_CNTL_REGULATOR_FORCE_PD_S 30 +/* RTC_CNTL_DBOOST_FORCE_PU : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: RTC_DBOOST force power up*/ +#define RTC_CNTL_DBOOST_FORCE_PU (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_M (BIT(29)) +#define RTC_CNTL_DBOOST_FORCE_PU_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PU_S 29 +/* RTC_CNTL_DBOOST_FORCE_PD : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RTC_DBOOST force power down*/ +#define RTC_CNTL_DBOOST_FORCE_PD (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_M (BIT(28)) +#define RTC_CNTL_DBOOST_FORCE_PD_V 0x1 +#define RTC_CNTL_DBOOST_FORCE_PD_S 28 +/* RTC_CNTL_SCK_DCAP : R/W ;bitpos:[21:14] ;default: 8'd0 ; */ +/*description: SCK_DCAP*/ +#define RTC_CNTL_SCK_DCAP 0x000000FF +#define RTC_CNTL_SCK_DCAP_M ((RTC_CNTL_SCK_DCAP_V) << (RTC_CNTL_SCK_DCAP_S)) +#define RTC_CNTL_SCK_DCAP_V 0xFF +#define RTC_CNTL_SCK_DCAP_S 14 +/* RTC_CNTL_DIG_CAL_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_CAL_EN (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_M (BIT(7)) +#define RTC_CNTL_DIG_CAL_EN_V 0x1 +#define RTC_CNTL_DIG_CAL_EN_S 7 + +#define RTC_CNTL_PWC_REG (DR_REG_RTCCNTL_BASE + 0x0088) +/* RTC_CNTL_PAD_FORCE_HOLD : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: rtc pad force hold*/ +#define RTC_CNTL_PAD_FORCE_HOLD (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_PAD_FORCE_HOLD_S 21 +/* RTC_CNTL_PD_EN : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: enable power down rtc_peri in sleep*/ +#define RTC_CNTL_PD_EN (BIT(20)) +#define RTC_CNTL_PD_EN_M (BIT(20)) +#define RTC_CNTL_PD_EN_V 0x1 +#define RTC_CNTL_PD_EN_S 20 +/* RTC_CNTL_FORCE_PU : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: rtc_peri force power up*/ +#define RTC_CNTL_FORCE_PU (BIT(19)) +#define RTC_CNTL_FORCE_PU_M (BIT(19)) +#define RTC_CNTL_FORCE_PU_V 0x1 +#define RTC_CNTL_FORCE_PU_S 19 +/* RTC_CNTL_FORCE_PD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc_peri force power down*/ +#define RTC_CNTL_FORCE_PD (BIT(18)) +#define RTC_CNTL_FORCE_PD_M (BIT(18)) +#define RTC_CNTL_FORCE_PD_V 0x1 +#define RTC_CNTL_FORCE_PD_S 18 +/* RTC_CNTL_SLOWMEM_PD_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable power down RTC memory in sleep*/ +#define RTC_CNTL_SLOWMEM_PD_EN (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_M (BIT(17)) +#define RTC_CNTL_SLOWMEM_PD_EN_V 0x1 +#define RTC_CNTL_SLOWMEM_PD_EN_S 17 +/* RTC_CNTL_SLOWMEM_FORCE_PU : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: RTC memory force power up*/ +#define RTC_CNTL_SLOWMEM_FORCE_PU (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_SLOWMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PU_S 16 +/* RTC_CNTL_SLOWMEM_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: RTC memory force power down*/ +#define RTC_CNTL_SLOWMEM_FORCE_PD (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_SLOWMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_PD_S 15 +/* RTC_CNTL_FASTMEM_PD_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable power down fast RTC memory in sleep*/ +#define RTC_CNTL_FASTMEM_PD_EN (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_M (BIT(14)) +#define RTC_CNTL_FASTMEM_PD_EN_V 0x1 +#define RTC_CNTL_FASTMEM_PD_EN_S 14 +/* RTC_CNTL_FASTMEM_FORCE_PU : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: Fast RTC memory force power up*/ +#define RTC_CNTL_FASTMEM_FORCE_PU (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_M (BIT(13)) +#define RTC_CNTL_FASTMEM_FORCE_PU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PU_S 13 +/* RTC_CNTL_FASTMEM_FORCE_PD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: Fast RTC memory force power down*/ +#define RTC_CNTL_FASTMEM_FORCE_PD (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_M (BIT(12)) +#define RTC_CNTL_FASTMEM_FORCE_PD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_PD_S 12 +/* RTC_CNTL_SLOWMEM_FORCE_LPU : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: RTC memory force no PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPU (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_M (BIT(11)) +#define RTC_CNTL_SLOWMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPU_S 11 +/* RTC_CNTL_SLOWMEM_FORCE_LPD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: RTC memory force PD*/ +#define RTC_CNTL_SLOWMEM_FORCE_LPD (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_M (BIT(10)) +#define RTC_CNTL_SLOWMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_LPD_S 10 +/* RTC_CNTL_SLOWMEM_FOLW_CPU : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: RTC memory PD following CPU*/ +#define RTC_CNTL_SLOWMEM_FOLW_CPU (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_M (BIT(9)) +#define RTC_CNTL_SLOWMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_SLOWMEM_FOLW_CPU_S 9 +/* RTC_CNTL_FASTMEM_FORCE_LPU : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPU (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_M (BIT(8)) +#define RTC_CNTL_FASTMEM_FORCE_LPU_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPU_S 8 +/* RTC_CNTL_FASTMEM_FORCE_LPD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Fast RTC memory force PD*/ +#define RTC_CNTL_FASTMEM_FORCE_LPD (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_M (BIT(7)) +#define RTC_CNTL_FASTMEM_FORCE_LPD_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_LPD_S 7 +/* RTC_CNTL_FASTMEM_FOLW_CPU : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: Fast RTC memory PD following CPU*/ +#define RTC_CNTL_FASTMEM_FOLW_CPU (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_M (BIT(6)) +#define RTC_CNTL_FASTMEM_FOLW_CPU_V 0x1 +#define RTC_CNTL_FASTMEM_FOLW_CPU_S 6 +/* RTC_CNTL_FORCE_NOISO : R/W ;bitpos:[5] ;default: 1'd1 ; */ +/*description: rtc_peri force no ISO*/ +#define RTC_CNTL_FORCE_NOISO (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_M (BIT(5)) +#define RTC_CNTL_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FORCE_NOISO_S 5 +/* RTC_CNTL_FORCE_ISO : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: rtc_peri force ISO*/ +#define RTC_CNTL_FORCE_ISO (BIT(4)) +#define RTC_CNTL_FORCE_ISO_M (BIT(4)) +#define RTC_CNTL_FORCE_ISO_V 0x1 +#define RTC_CNTL_FORCE_ISO_S 4 +/* RTC_CNTL_SLOWMEM_FORCE_ISO : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: RTC memory force ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_ISO (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_M (BIT(3)) +#define RTC_CNTL_SLOWMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_ISO_S 3 +/* RTC_CNTL_SLOWMEM_FORCE_NOISO : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: RTC memory force no ISO*/ +#define RTC_CNTL_SLOWMEM_FORCE_NOISO (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_M (BIT(2)) +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_SLOWMEM_FORCE_NOISO_S 2 +/* RTC_CNTL_FASTMEM_FORCE_ISO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Fast RTC memory force ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_ISO (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_M (BIT(1)) +#define RTC_CNTL_FASTMEM_FORCE_ISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_ISO_S 1 +/* RTC_CNTL_FASTMEM_FORCE_NOISO : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Fast RTC memory force no ISO*/ +#define RTC_CNTL_FASTMEM_FORCE_NOISO (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_M (BIT(0)) +#define RTC_CNTL_FASTMEM_FORCE_NOISO_V 0x1 +#define RTC_CNTL_FASTMEM_FORCE_NOISO_S 0 + +#define RTC_CNTL_DIG_PWC_REG (DR_REG_RTCCNTL_BASE + 0x008C) +/* RTC_CNTL_DG_WRAP_PD_EN : R/W ;bitpos:[31] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_PD_EN (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_PD_EN_V 0x1 +#define RTC_CNTL_DG_WRAP_PD_EN_S 31 +/* RTC_CNTL_WIFI_PD_EN : R/W ;bitpos:[30] ;default: 0 ; */ +/*description: enable power down wifi in sleep*/ +#define RTC_CNTL_WIFI_PD_EN (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_M (BIT(30)) +#define RTC_CNTL_WIFI_PD_EN_V 0x1 +#define RTC_CNTL_WIFI_PD_EN_S 30 +/* RTC_CNTL_INTER_RAM4_PD_EN : R/W ;bitpos:[29] ;default: 0 ; */ +/*description: enable power down internal SRAM 4 in sleep*/ +#define RTC_CNTL_INTER_RAM4_PD_EN (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_M (BIT(29)) +#define RTC_CNTL_INTER_RAM4_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM4_PD_EN_S 29 +/* RTC_CNTL_INTER_RAM3_PD_EN : R/W ;bitpos:[28] ;default: 0 ; */ +/*description: enable power down internal SRAM 3 in sleep*/ +#define RTC_CNTL_INTER_RAM3_PD_EN (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_M (BIT(28)) +#define RTC_CNTL_INTER_RAM3_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM3_PD_EN_S 28 +/* RTC_CNTL_INTER_RAM2_PD_EN : R/W ;bitpos:[27] ;default: 0 ; */ +/*description: enable power down internal SRAM 2 in sleep*/ +#define RTC_CNTL_INTER_RAM2_PD_EN (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_M (BIT(27)) +#define RTC_CNTL_INTER_RAM2_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM2_PD_EN_S 27 +/* RTC_CNTL_INTER_RAM1_PD_EN : R/W ;bitpos:[26] ;default: 0 ; */ +/*description: enable power down internal SRAM 1 in sleep*/ +#define RTC_CNTL_INTER_RAM1_PD_EN (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_M (BIT(26)) +#define RTC_CNTL_INTER_RAM1_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM1_PD_EN_S 26 +/* RTC_CNTL_INTER_RAM0_PD_EN : R/W ;bitpos:[25] ;default: 0 ; */ +/*description: enable power down internal SRAM 0 in sleep*/ +#define RTC_CNTL_INTER_RAM0_PD_EN (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_M (BIT(25)) +#define RTC_CNTL_INTER_RAM0_PD_EN_V 0x1 +#define RTC_CNTL_INTER_RAM0_PD_EN_S 25 +/* RTC_CNTL_ROM0_PD_EN : R/W ;bitpos:[24] ;default: 0 ; */ +/*description: enable power down ROM in sleep*/ +#define RTC_CNTL_ROM0_PD_EN (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_M (BIT(24)) +#define RTC_CNTL_ROM0_PD_EN_V 0x1 +#define RTC_CNTL_ROM0_PD_EN_S 24 +/* RTC_CNTL_DG_DCDC_PD_EN : R/W ;bitpos:[23] ;default: 0 ; */ +/*description: enable power down digital dcdc in sleep*/ +#define RTC_CNTL_DG_DCDC_PD_EN (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_M (BIT(23)) +#define RTC_CNTL_DG_DCDC_PD_EN_V 0x1 +#define RTC_CNTL_DG_DCDC_PD_EN_S 23 +/* RTC_CNTL_DG_DCDC_FORCE_PU : R/W ;bitpos:[22] ;default: 1'd1 ; */ +/*description: digital dcdc force power up*/ +#define RTC_CNTL_DG_DCDC_FORCE_PU (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_M (BIT(22)) +#define RTC_CNTL_DG_DCDC_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_DCDC_FORCE_PU_S 22 +/* RTC_CNTL_DG_DCDC_FORCE_PD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: digital dcdc force power down*/ +#define RTC_CNTL_DG_DCDC_FORCE_PD (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_M (BIT(21)) +#define RTC_CNTL_DG_DCDC_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_DCDC_FORCE_PD_S 21 +/* RTC_CNTL_DG_WRAP_FORCE_PU : R/W ;bitpos:[20] ;default: 1'd1 ; */ +/*description: digital core force power up*/ +#define RTC_CNTL_DG_WRAP_FORCE_PU (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_M (BIT(20)) +#define RTC_CNTL_DG_WRAP_FORCE_PU_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PU_S 20 +/* RTC_CNTL_DG_WRAP_FORCE_PD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: digital core force power down*/ +#define RTC_CNTL_DG_WRAP_FORCE_PD (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_M (BIT(19)) +#define RTC_CNTL_DG_WRAP_FORCE_PD_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_PD_S 19 +/* RTC_CNTL_WIFI_FORCE_PU : R/W ;bitpos:[18] ;default: 1'd1 ; */ +/*description: wifi force power up*/ +#define RTC_CNTL_WIFI_FORCE_PU (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_M (BIT(18)) +#define RTC_CNTL_WIFI_FORCE_PU_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PU_S 18 +/* RTC_CNTL_WIFI_FORCE_PD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: wifi force power down*/ +#define RTC_CNTL_WIFI_FORCE_PD (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_M (BIT(17)) +#define RTC_CNTL_WIFI_FORCE_PD_V 0x1 +#define RTC_CNTL_WIFI_FORCE_PD_S 17 +/* RTC_CNTL_INTER_RAM4_FORCE_PU : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force power up*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PU (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_M (BIT(16)) +#define RTC_CNTL_INTER_RAM4_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PU_S 16 +/* RTC_CNTL_INTER_RAM4_FORCE_PD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: internal SRAM 4 force power down*/ +#define RTC_CNTL_INTER_RAM4_FORCE_PD (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_M (BIT(15)) +#define RTC_CNTL_INTER_RAM4_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_PD_S 15 +/* RTC_CNTL_INTER_RAM3_FORCE_PU : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force power up*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PU (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_M (BIT(14)) +#define RTC_CNTL_INTER_RAM3_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PU_S 14 +/* RTC_CNTL_INTER_RAM3_FORCE_PD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: internal SRAM 3 force power down*/ +#define RTC_CNTL_INTER_RAM3_FORCE_PD (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_M (BIT(13)) +#define RTC_CNTL_INTER_RAM3_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_PD_S 13 +/* RTC_CNTL_INTER_RAM2_FORCE_PU : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force power up*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PU (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_M (BIT(12)) +#define RTC_CNTL_INTER_RAM2_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PU_S 12 +/* RTC_CNTL_INTER_RAM2_FORCE_PD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: internal SRAM 2 force power down*/ +#define RTC_CNTL_INTER_RAM2_FORCE_PD (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_M (BIT(11)) +#define RTC_CNTL_INTER_RAM2_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_PD_S 11 +/* RTC_CNTL_INTER_RAM1_FORCE_PU : R/W ;bitpos:[10] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force power up*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PU (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_M (BIT(10)) +#define RTC_CNTL_INTER_RAM1_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PU_S 10 +/* RTC_CNTL_INTER_RAM1_FORCE_PD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: internal SRAM 1 force power down*/ +#define RTC_CNTL_INTER_RAM1_FORCE_PD (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_M (BIT(9)) +#define RTC_CNTL_INTER_RAM1_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_PD_S 9 +/* RTC_CNTL_INTER_RAM0_FORCE_PU : R/W ;bitpos:[8] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force power up*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PU (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_M (BIT(8)) +#define RTC_CNTL_INTER_RAM0_FORCE_PU_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PU_S 8 +/* RTC_CNTL_INTER_RAM0_FORCE_PD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: internal SRAM 0 force power down*/ +#define RTC_CNTL_INTER_RAM0_FORCE_PD (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_M (BIT(7)) +#define RTC_CNTL_INTER_RAM0_FORCE_PD_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_PD_S 7 +/* RTC_CNTL_ROM0_FORCE_PU : R/W ;bitpos:[6] ;default: 1'd1 ; */ +/*description: ROM force power up*/ +#define RTC_CNTL_ROM0_FORCE_PU (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_M (BIT(6)) +#define RTC_CNTL_ROM0_FORCE_PU_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PU_S 6 +/* RTC_CNTL_ROM0_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ROM force power down*/ +#define RTC_CNTL_ROM0_FORCE_PD (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_M (BIT(5)) +#define RTC_CNTL_ROM0_FORCE_PD_V 0x1 +#define RTC_CNTL_ROM0_FORCE_PD_S 5 +/* RTC_CNTL_LSLP_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: memories in digital core force no PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PU (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_M (BIT(4)) +#define RTC_CNTL_LSLP_MEM_FORCE_PU_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PU_S 4 +/* RTC_CNTL_LSLP_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: memories in digital core force PD in sleep*/ +#define RTC_CNTL_LSLP_MEM_FORCE_PD (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_M (BIT(3)) +#define RTC_CNTL_LSLP_MEM_FORCE_PD_V 0x1 +#define RTC_CNTL_LSLP_MEM_FORCE_PD_S 3 + +#define RTC_CNTL_DIG_ISO_REG (DR_REG_RTCCNTL_BASE + 0x0090) +/* RTC_CNTL_DG_WRAP_FORCE_NOISO : R/W ;bitpos:[31] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DG_WRAP_FORCE_NOISO (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_M (BIT(31)) +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_NOISO_S 31 +/* RTC_CNTL_DG_WRAP_FORCE_ISO : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: digital core force ISO*/ +#define RTC_CNTL_DG_WRAP_FORCE_ISO (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_M (BIT(30)) +#define RTC_CNTL_DG_WRAP_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_WRAP_FORCE_ISO_S 30 +/* RTC_CNTL_WIFI_FORCE_NOISO : R/W ;bitpos:[29] ;default: 1'd1 ; */ +/*description: wifi force no ISO*/ +#define RTC_CNTL_WIFI_FORCE_NOISO (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_M (BIT(29)) +#define RTC_CNTL_WIFI_FORCE_NOISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_NOISO_S 29 +/* RTC_CNTL_WIFI_FORCE_ISO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: wifi force ISO*/ +#define RTC_CNTL_WIFI_FORCE_ISO (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_M (BIT(28)) +#define RTC_CNTL_WIFI_FORCE_ISO_V 0x1 +#define RTC_CNTL_WIFI_FORCE_ISO_S 28 +/* RTC_CNTL_INTER_RAM4_FORCE_NOISO : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: internal SRAM 4 force no ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_M (BIT(27)) +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_NOISO_S 27 +/* RTC_CNTL_INTER_RAM4_FORCE_ISO : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: internal SRAM 4 force ISO*/ +#define RTC_CNTL_INTER_RAM4_FORCE_ISO (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_M (BIT(26)) +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM4_FORCE_ISO_S 26 +/* RTC_CNTL_INTER_RAM3_FORCE_NOISO : R/W ;bitpos:[25] ;default: 1'd1 ; */ +/*description: internal SRAM 3 force no ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_M (BIT(25)) +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_NOISO_S 25 +/* RTC_CNTL_INTER_RAM3_FORCE_ISO : R/W ;bitpos:[24] ;default: 1'd0 ; */ +/*description: internal SRAM 3 force ISO*/ +#define RTC_CNTL_INTER_RAM3_FORCE_ISO (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_M (BIT(24)) +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM3_FORCE_ISO_S 24 +/* RTC_CNTL_INTER_RAM2_FORCE_NOISO : R/W ;bitpos:[23] ;default: 1'd1 ; */ +/*description: internal SRAM 2 force no ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_M (BIT(23)) +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_NOISO_S 23 +/* RTC_CNTL_INTER_RAM2_FORCE_ISO : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: internal SRAM 2 force ISO*/ +#define RTC_CNTL_INTER_RAM2_FORCE_ISO (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_M (BIT(22)) +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM2_FORCE_ISO_S 22 +/* RTC_CNTL_INTER_RAM1_FORCE_NOISO : R/W ;bitpos:[21] ;default: 1'd1 ; */ +/*description: internal SRAM 1 force no ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_M (BIT(21)) +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_NOISO_S 21 +/* RTC_CNTL_INTER_RAM1_FORCE_ISO : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: internal SRAM 1 force ISO*/ +#define RTC_CNTL_INTER_RAM1_FORCE_ISO (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_M (BIT(20)) +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM1_FORCE_ISO_S 20 +/* RTC_CNTL_INTER_RAM0_FORCE_NOISO : R/W ;bitpos:[19] ;default: 1'd1 ; */ +/*description: internal SRAM 0 force no ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_M (BIT(19)) +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_NOISO_S 19 +/* RTC_CNTL_INTER_RAM0_FORCE_ISO : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: internal SRAM 0 force ISO*/ +#define RTC_CNTL_INTER_RAM0_FORCE_ISO (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_M (BIT(18)) +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_INTER_RAM0_FORCE_ISO_S 18 +/* RTC_CNTL_ROM0_FORCE_NOISO : R/W ;bitpos:[17] ;default: 1'd1 ; */ +/*description: ROM force no ISO*/ +#define RTC_CNTL_ROM0_FORCE_NOISO (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_M (BIT(17)) +#define RTC_CNTL_ROM0_FORCE_NOISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_NOISO_S 17 +/* RTC_CNTL_ROM0_FORCE_ISO : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: ROM force ISO*/ +#define RTC_CNTL_ROM0_FORCE_ISO (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_M (BIT(16)) +#define RTC_CNTL_ROM0_FORCE_ISO_V 0x1 +#define RTC_CNTL_ROM0_FORCE_ISO_S 16 +/* RTC_CNTL_DG_PAD_FORCE_HOLD : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: digital pad force hold*/ +#define RTC_CNTL_DG_PAD_FORCE_HOLD (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_M (BIT(15)) +#define RTC_CNTL_DG_PAD_FORCE_HOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_HOLD_S 15 +/* RTC_CNTL_DG_PAD_FORCE_UNHOLD : R/W ;bitpos:[14] ;default: 1'd1 ; */ +/*description: digital pad force un-hold*/ +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_M (BIT(14)) +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_UNHOLD_S 14 +/* RTC_CNTL_DG_PAD_FORCE_ISO : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: digital pad force ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_ISO (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_M (BIT(13)) +#define RTC_CNTL_DG_PAD_FORCE_ISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_ISO_S 13 +/* RTC_CNTL_DG_PAD_FORCE_NOISO : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: digital pad force no ISO*/ +#define RTC_CNTL_DG_PAD_FORCE_NOISO (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_M (BIT(12)) +#define RTC_CNTL_DG_PAD_FORCE_NOISO_V 0x1 +#define RTC_CNTL_DG_PAD_FORCE_NOISO_S 12 +/* RTC_CNTL_DG_PAD_AUTOHOLD_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: digital pad enable auto-hold*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_M (BIT(11)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_EN_S 11 +/* RTC_CNTL_CLR_DG_PAD_AUTOHOLD : WO ;bitpos:[10] ;default: 1'd0 ; */ +/*description: wtite only register to clear digital pad auto-hold*/ +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_M (BIT(10)) +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_CLR_DG_PAD_AUTOHOLD_S 10 +/* RTC_CNTL_DG_PAD_AUTOHOLD : RO ;bitpos:[9] ;default: 1'd0 ; */ +/*description: read only register to indicate digital pad auto-hold status*/ +#define RTC_CNTL_DG_PAD_AUTOHOLD (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_M (BIT(9)) +#define RTC_CNTL_DG_PAD_AUTOHOLD_V 0x1 +#define RTC_CNTL_DG_PAD_AUTOHOLD_S 9 +/* RTC_CNTL_DIG_ISO_FORCE_ON : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_ON (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_M (BIT(8)) +#define RTC_CNTL_DIG_ISO_FORCE_ON_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_ON_S 8 +/* RTC_CNTL_DIG_ISO_FORCE_OFF : R/W ;bitpos:[7] ;default: 1'd1 ; */ +/*description: */ +#define RTC_CNTL_DIG_ISO_FORCE_OFF (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_FORCE_OFF_V 0x1 +#define RTC_CNTL_DIG_ISO_FORCE_OFF_S 7 + +#define RTC_CNTL_WDTCONFIG0_REG (DR_REG_RTCCNTL_BASE + 0x0094) +/* RTC_CNTL_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define RTC_CNTL_WDT_EN (BIT(31)) +#define RTC_CNTL_WDT_EN_M (BIT(31)) +#define RTC_CNTL_WDT_EN_V 0x1 +#define RTC_CNTL_WDT_EN_S 31 +/* RTC_CNTL_WDT_STG0 : R/W ;bitpos:[30:28] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG0 0x00000007 +#define RTC_CNTL_WDT_STG0_M ((RTC_CNTL_WDT_STG0_V) << (RTC_CNTL_WDT_STG0_S)) +#define RTC_CNTL_WDT_STG0_V 0x7 +#define RTC_CNTL_WDT_STG0_S 28 +/* RTC_CNTL_WDT_STG1 : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG1 0x00000007 +#define RTC_CNTL_WDT_STG1_M ((RTC_CNTL_WDT_STG1_V) << (RTC_CNTL_WDT_STG1_S)) +#define RTC_CNTL_WDT_STG1_V 0x7 +#define RTC_CNTL_WDT_STG1_S 25 +/* RTC_CNTL_WDT_STG2 : R/W ;bitpos:[24:22] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG2 0x00000007 +#define RTC_CNTL_WDT_STG2_M ((RTC_CNTL_WDT_STG2_V) << (RTC_CNTL_WDT_STG2_S)) +#define RTC_CNTL_WDT_STG2_V 0x7 +#define RTC_CNTL_WDT_STG2_S 22 +/* RTC_CNTL_WDT_STG3 : R/W ;bitpos:[21:19] ;default: 3'h0 ; */ +/*description: 1: interrupt stage en*/ +#define RTC_CNTL_WDT_STG3 0x00000007 +#define RTC_CNTL_WDT_STG3_M ((RTC_CNTL_WDT_STG3_V) << (RTC_CNTL_WDT_STG3_S)) +#define RTC_CNTL_WDT_STG3_V 0x7 +#define RTC_CNTL_WDT_STG3_S 19 +/* RTC_CNTL_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[18:16] ;default: 3'h1 ; */ +/*description: CPU reset counter length*/ +#define RTC_CNTL_WDT_CPU_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_M ((RTC_CNTL_WDT_CPU_RESET_LENGTH_V) << (RTC_CNTL_WDT_CPU_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_CPU_RESET_LENGTH_S 16 +/* RTC_CNTL_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[15:13] ;default: 3'h1 ; */ +/*description: system reset counter length*/ +#define RTC_CNTL_WDT_SYS_RESET_LENGTH 0x00000007 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_M ((RTC_CNTL_WDT_SYS_RESET_LENGTH_V) << (RTC_CNTL_WDT_SYS_RESET_LENGTH_S)) +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_V 0x7 +#define RTC_CNTL_WDT_SYS_RESET_LENGTH_S 13 +/* RTC_CNTL_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: enable WDT in flash boot*/ +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_M (BIT(12)) +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define RTC_CNTL_WDT_FLASHBOOT_MOD_EN_S 12 +/* RTC_CNTL_WDT_PROCPU_RESET_EN : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: enable WDT reset PRO CPU*/ +#define RTC_CNTL_WDT_PROCPU_RESET_EN (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_M (BIT(11)) +#define RTC_CNTL_WDT_PROCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_PROCPU_RESET_EN_S 11 +/* RTC_CNTL_WDT_APPCPU_RESET_EN : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: enable WDT reset APP CPU*/ +#define RTC_CNTL_WDT_APPCPU_RESET_EN (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_M (BIT(10)) +#define RTC_CNTL_WDT_APPCPU_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_APPCPU_RESET_EN_S 10 +/* RTC_CNTL_WDT_PAUSE_IN_SLP : R/W ;bitpos:[9] ;default: 1'd1 ; */ +/*description: pause WDT in sleep*/ +#define RTC_CNTL_WDT_PAUSE_IN_SLP (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_M (BIT(9)) +#define RTC_CNTL_WDT_PAUSE_IN_SLP_V 0x1 +#define RTC_CNTL_WDT_PAUSE_IN_SLP_S 9 +/* RTC_CNTL_WDT_CHIP_RESET_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: wdt reset whole chip enable*/ +#define RTC_CNTL_WDT_CHIP_RESET_EN (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_M (BIT(8)) +#define RTC_CNTL_WDT_CHIP_RESET_EN_V 0x1 +#define RTC_CNTL_WDT_CHIP_RESET_EN_S 8 +/* RTC_CNTL_WDT_CHIP_RESET_WIDTH : R/W ;bitpos:[7:0] ;default: 8'd20 ; */ +/*description: chip reset siginal pulse width*/ +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH 0x000000FF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_M ((RTC_CNTL_WDT_CHIP_RESET_WIDTH_V) << (RTC_CNTL_WDT_CHIP_RESET_WIDTH_S)) +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_V 0xFF +#define RTC_CNTL_WDT_CHIP_RESET_WIDTH_S 0 + +#define RTC_CNTL_WDTCONFIG1_REG (DR_REG_RTCCNTL_BASE + 0x0098) +/* RTC_CNTL_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd200000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG0_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_M ((RTC_CNTL_WDT_STG0_HOLD_V) << (RTC_CNTL_WDT_STG0_HOLD_S)) +#define RTC_CNTL_WDT_STG0_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG0_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG2_REG (DR_REG_RTCCNTL_BASE + 0x009C) +/* RTC_CNTL_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'd80000 ; */ +/*description: */ +#define RTC_CNTL_WDT_STG1_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_M ((RTC_CNTL_WDT_STG1_HOLD_V) << (RTC_CNTL_WDT_STG1_HOLD_S)) +#define RTC_CNTL_WDT_STG1_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG1_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG3_REG (DR_REG_RTCCNTL_BASE + 0x00A0) +/* RTC_CNTL_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG2_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_M ((RTC_CNTL_WDT_STG2_HOLD_V) << (RTC_CNTL_WDT_STG2_HOLD_S)) +#define RTC_CNTL_WDT_STG2_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG2_HOLD_S 0 + +#define RTC_CNTL_WDTCONFIG4_REG (DR_REG_RTCCNTL_BASE + 0x00A4) +/* RTC_CNTL_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfff ; */ +/*description: */ +#define RTC_CNTL_WDT_STG3_HOLD 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_M ((RTC_CNTL_WDT_STG3_HOLD_V) << (RTC_CNTL_WDT_STG3_HOLD_S)) +#define RTC_CNTL_WDT_STG3_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_WDT_STG3_HOLD_S 0 + +#define RTC_CNTL_WDTFEED_REG (DR_REG_RTCCNTL_BASE + 0x00A8) +/* RTC_CNTL_WDT_FEED : WO ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_WDT_FEED (BIT(31)) +#define RTC_CNTL_WDT_FEED_M (BIT(31)) +#define RTC_CNTL_WDT_FEED_V 0x1 +#define RTC_CNTL_WDT_FEED_S 31 + +#define RTC_CNTL_WDTWPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00AC) +/* RTC_CNTL_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define RTC_CNTL_WDT_WKEY 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_M ((RTC_CNTL_WDT_WKEY_V) << (RTC_CNTL_WDT_WKEY_S)) +#define RTC_CNTL_WDT_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_WDT_WKEY_S 0 + +#define RTC_CNTL_SWD_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00B0) +/* RTC_CNTL_SWD_AUTO_FEED_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: automatically feed swd when int comes*/ +#define RTC_CNTL_SWD_AUTO_FEED_EN (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_M (BIT(31)) +#define RTC_CNTL_SWD_AUTO_FEED_EN_V 0x1 +#define RTC_CNTL_SWD_AUTO_FEED_EN_S 31 +/* RTC_CNTL_SWD_DISABLE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: disabel SWD*/ +#define RTC_CNTL_SWD_DISABLE (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_M (BIT(30)) +#define RTC_CNTL_SWD_DISABLE_V 0x1 +#define RTC_CNTL_SWD_DISABLE_S 30 +/* RTC_CNTL_SWD_FEED : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Sw feed swd*/ +#define RTC_CNTL_SWD_FEED (BIT(29)) +#define RTC_CNTL_SWD_FEED_M (BIT(29)) +#define RTC_CNTL_SWD_FEED_V 0x1 +#define RTC_CNTL_SWD_FEED_S 29 +/* RTC_CNTL_SWD_RST_FLAG_CLR : WO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: reset swd reset flag*/ +#define RTC_CNTL_SWD_RST_FLAG_CLR (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_M (BIT(28)) +#define RTC_CNTL_SWD_RST_FLAG_CLR_V 0x1 +#define RTC_CNTL_SWD_RST_FLAG_CLR_S 28 +/* RTC_CNTL_SWD_SIGNAL_WIDTH : R/W ;bitpos:[27:18] ;default: 10'd300 ; */ +/*description: adjust signal width send to swd*/ +#define RTC_CNTL_SWD_SIGNAL_WIDTH 0x000003FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_M ((RTC_CNTL_SWD_SIGNAL_WIDTH_V) << (RTC_CNTL_SWD_SIGNAL_WIDTH_S)) +#define RTC_CNTL_SWD_SIGNAL_WIDTH_V 0x3FF +#define RTC_CNTL_SWD_SIGNAL_WIDTH_S 18 +/* RTC_CNTL_SWD_BYPASS_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_SWD_BYPASS_RST (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_M (BIT(17)) +#define RTC_CNTL_SWD_BYPASS_RST_V 0x1 +#define RTC_CNTL_SWD_BYPASS_RST_S 17 +/* RTC_CNTL_SWD_FEED_INT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: swd interrupt for feeding*/ +#define RTC_CNTL_SWD_FEED_INT (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_M (BIT(1)) +#define RTC_CNTL_SWD_FEED_INT_V 0x1 +#define RTC_CNTL_SWD_FEED_INT_S 1 +/* RTC_CNTL_SWD_RESET_FLAG : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: swd reset flag*/ +#define RTC_CNTL_SWD_RESET_FLAG (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_M (BIT(0)) +#define RTC_CNTL_SWD_RESET_FLAG_V 0x1 +#define RTC_CNTL_SWD_RESET_FLAG_S 0 + +#define RTC_CNTL_SWD_WPROTECT_REG (DR_REG_RTCCNTL_BASE + 0x00B4) +/* RTC_CNTL_SWD_WKEY : R/W ;bitpos:[31:0] ;default: 32'h8f1d312a ; */ +/*description: */ +#define RTC_CNTL_SWD_WKEY 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_M ((RTC_CNTL_SWD_WKEY_V) << (RTC_CNTL_SWD_WKEY_S)) +#define RTC_CNTL_SWD_WKEY_V 0xFFFFFFFF +#define RTC_CNTL_SWD_WKEY_S 0 + +#define RTC_CNTL_SW_CPU_STALL_REG (DR_REG_RTCCNTL_BASE + 0x00B8) +/* RTC_CNTL_SW_STALL_PROCPU_C1 : R/W ;bitpos:[31:26] ;default: 6'b0 ; */ +/*description: */ +#define RTC_CNTL_SW_STALL_PROCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_PROCPU_C1_M ((RTC_CNTL_SW_STALL_PROCPU_C1_V) << (RTC_CNTL_SW_STALL_PROCPU_C1_S)) +#define RTC_CNTL_SW_STALL_PROCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_PROCPU_C1_S 26 +/* RTC_CNTL_SW_STALL_APPCPU_C1 : R/W ;bitpos:[25:20] ;default: 6'b0 ; */ +/*description: {reg_sw_stall_appcpu_c1[5:0]*/ +#define RTC_CNTL_SW_STALL_APPCPU_C1 0x0000003F +#define RTC_CNTL_SW_STALL_APPCPU_C1_M ((RTC_CNTL_SW_STALL_APPCPU_C1_V) << (RTC_CNTL_SW_STALL_APPCPU_C1_S)) +#define RTC_CNTL_SW_STALL_APPCPU_C1_V 0x3F +#define RTC_CNTL_SW_STALL_APPCPU_C1_S 20 + +#define RTC_CNTL_STORE4_REG (DR_REG_RTCCNTL_BASE + 0x00BC) +/* RTC_CNTL_SCRATCH4 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH4 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_M ((RTC_CNTL_SCRATCH4_V) << (RTC_CNTL_SCRATCH4_S)) +#define RTC_CNTL_SCRATCH4_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH4_S 0 + +#define RTC_CNTL_STORE5_REG (DR_REG_RTCCNTL_BASE + 0x00C0) +/* RTC_CNTL_SCRATCH5 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH5 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_M ((RTC_CNTL_SCRATCH5_V) << (RTC_CNTL_SCRATCH5_S)) +#define RTC_CNTL_SCRATCH5_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH5_S 0 + +#define RTC_CNTL_STORE6_REG (DR_REG_RTCCNTL_BASE + 0x00C4) +/* RTC_CNTL_SCRATCH6 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH6 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_M ((RTC_CNTL_SCRATCH6_V) << (RTC_CNTL_SCRATCH6_S)) +#define RTC_CNTL_SCRATCH6_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH6_S 0 + +#define RTC_CNTL_STORE7_REG (DR_REG_RTCCNTL_BASE + 0x00C8) +/* RTC_CNTL_SCRATCH7 : R/W ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_SCRATCH7 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_M ((RTC_CNTL_SCRATCH7_V) << (RTC_CNTL_SCRATCH7_S)) +#define RTC_CNTL_SCRATCH7_V 0xFFFFFFFF +#define RTC_CNTL_SCRATCH7_S 0 + +#define RTC_CNTL_LOW_POWER_ST_REG (DR_REG_RTCCNTL_BASE + 0x00CC) +/* RTC_CNTL_MAIN_STATE : RO ;bitpos:[31:28] ;default: 4'd0 ; */ +/*description: rtc main state machine status*/ +#define RTC_CNTL_MAIN_STATE 0x0000000F +#define RTC_CNTL_MAIN_STATE_M ((RTC_CNTL_MAIN_STATE_V) << (RTC_CNTL_MAIN_STATE_S)) +#define RTC_CNTL_MAIN_STATE_V 0xF +#define RTC_CNTL_MAIN_STATE_S 28 +/* RTC_CNTL_MAIN_STATE_IN_IDLE : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: rtc main state machine is in idle state*/ +#define RTC_CNTL_MAIN_STATE_IN_IDLE (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_M (BIT(27)) +#define RTC_CNTL_MAIN_STATE_IN_IDLE_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_IDLE_S 27 +/* RTC_CNTL_MAIN_STATE_IN_SLP : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: rtc main state machine is in sleep state*/ +#define RTC_CNTL_MAIN_STATE_IN_SLP (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_M (BIT(26)) +#define RTC_CNTL_MAIN_STATE_IN_SLP_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_SLP_S 26 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_XTL : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait xtal state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_M (BIT(25)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_XTL_S 25 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_PLL : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait pll state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_M (BIT(24)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_PLL_S 24 +/* RTC_CNTL_MAIN_STATE_IN_WAIT_8M : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: rtc main state machine is in wait 8m state*/ +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_M (BIT(23)) +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_V 0x1 +#define RTC_CNTL_MAIN_STATE_IN_WAIT_8M_S 23 +/* RTC_CNTL_IN_LOW_POWER_STATE : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of low power*/ +#define RTC_CNTL_IN_LOW_POWER_STATE (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_M (BIT(22)) +#define RTC_CNTL_IN_LOW_POWER_STATE_V 0x1 +#define RTC_CNTL_IN_LOW_POWER_STATE_S 22 +/* RTC_CNTL_IN_WAKEUP_STATE : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: rtc main state machine is in the states of wakeup process*/ +#define RTC_CNTL_IN_WAKEUP_STATE (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_M (BIT(21)) +#define RTC_CNTL_IN_WAKEUP_STATE_V 0x1 +#define RTC_CNTL_IN_WAKEUP_STATE_S 21 +/* RTC_CNTL_MAIN_STATE_WAIT_END : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: rtc main state machine has been waited for some cycles*/ +#define RTC_CNTL_MAIN_STATE_WAIT_END (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_M (BIT(20)) +#define RTC_CNTL_MAIN_STATE_WAIT_END_V 0x1 +#define RTC_CNTL_MAIN_STATE_WAIT_END_S 20 +/* RTC_CNTL_RDY_FOR_WAKEUP : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: rtc is ready to receive wake up trigger from wake up source*/ +#define RTC_CNTL_RDY_FOR_WAKEUP (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_M (BIT(19)) +#define RTC_CNTL_RDY_FOR_WAKEUP_V 0x1 +#define RTC_CNTL_RDY_FOR_WAKEUP_S 19 +/* RTC_CNTL_MAIN_STATE_PLL_ON : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: rtc main state machine is in states that pll should be running*/ +#define RTC_CNTL_MAIN_STATE_PLL_ON (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_M (BIT(18)) +#define RTC_CNTL_MAIN_STATE_PLL_ON_V 0x1 +#define RTC_CNTL_MAIN_STATE_PLL_ON_S 18 +/* RTC_CNTL_MAIN_STATE_XTAL_ISO : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: no use any more*/ +#define RTC_CNTL_MAIN_STATE_XTAL_ISO (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_M (BIT(17)) +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_V 0x1 +#define RTC_CNTL_MAIN_STATE_XTAL_ISO_S 17 +/* RTC_CNTL_COCPU_STATE_DONE : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: ulp/cocpu is done*/ +#define RTC_CNTL_COCPU_STATE_DONE (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_M (BIT(16)) +#define RTC_CNTL_COCPU_STATE_DONE_V 0x1 +#define RTC_CNTL_COCPU_STATE_DONE_S 16 +/* RTC_CNTL_COCPU_STATE_SLP : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: ulp/cocpu is in sleep state*/ +#define RTC_CNTL_COCPU_STATE_SLP (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_M (BIT(15)) +#define RTC_CNTL_COCPU_STATE_SLP_V 0x1 +#define RTC_CNTL_COCPU_STATE_SLP_S 15 +/* RTC_CNTL_COCPU_STATE_SWITCH : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: ulp/cocpu is about to working. Switch rtc main state*/ +#define RTC_CNTL_COCPU_STATE_SWITCH (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_M (BIT(14)) +#define RTC_CNTL_COCPU_STATE_SWITCH_V 0x1 +#define RTC_CNTL_COCPU_STATE_SWITCH_S 14 +/* RTC_CNTL_COCPU_STATE_START : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: ulp/cocpu should start to work*/ +#define RTC_CNTL_COCPU_STATE_START (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_M (BIT(13)) +#define RTC_CNTL_COCPU_STATE_START_V 0x1 +#define RTC_CNTL_COCPU_STATE_START_S 13 +/* RTC_CNTL_TOUCH_STATE_DONE : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: touch is done*/ +#define RTC_CNTL_TOUCH_STATE_DONE (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_M (BIT(12)) +#define RTC_CNTL_TOUCH_STATE_DONE_V 0x1 +#define RTC_CNTL_TOUCH_STATE_DONE_S 12 +/* RTC_CNTL_TOUCH_STATE_SLP : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: touch is in sleep state*/ +#define RTC_CNTL_TOUCH_STATE_SLP (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_M (BIT(11)) +#define RTC_CNTL_TOUCH_STATE_SLP_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SLP_S 11 +/* RTC_CNTL_TOUCH_STATE_SWITCH : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: touch is about to working. Switch rtc main state*/ +#define RTC_CNTL_TOUCH_STATE_SWITCH (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_M (BIT(10)) +#define RTC_CNTL_TOUCH_STATE_SWITCH_V 0x1 +#define RTC_CNTL_TOUCH_STATE_SWITCH_S 10 +/* RTC_CNTL_TOUCH_STATE_START : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch should start to work*/ +#define RTC_CNTL_TOUCH_STATE_START (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_M (BIT(9)) +#define RTC_CNTL_TOUCH_STATE_START_V 0x1 +#define RTC_CNTL_TOUCH_STATE_START_S 9 +/* RTC_CNTL_XPD_DIG : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: digital wrap power down*/ +#define RTC_CNTL_XPD_DIG (BIT(8)) +#define RTC_CNTL_XPD_DIG_M (BIT(8)) +#define RTC_CNTL_XPD_DIG_V 0x1 +#define RTC_CNTL_XPD_DIG_S 8 +/* RTC_CNTL_DIG_ISO : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: digital wrap iso*/ +#define RTC_CNTL_DIG_ISO (BIT(7)) +#define RTC_CNTL_DIG_ISO_M (BIT(7)) +#define RTC_CNTL_DIG_ISO_V 0x1 +#define RTC_CNTL_DIG_ISO_S 7 +/* RTC_CNTL_XPD_WIFI : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: wifi wrap power down*/ +#define RTC_CNTL_XPD_WIFI (BIT(6)) +#define RTC_CNTL_XPD_WIFI_M (BIT(6)) +#define RTC_CNTL_XPD_WIFI_V 0x1 +#define RTC_CNTL_XPD_WIFI_S 6 +/* RTC_CNTL_WIFI_ISO : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: wifi iso*/ +#define RTC_CNTL_WIFI_ISO (BIT(5)) +#define RTC_CNTL_WIFI_ISO_M (BIT(5)) +#define RTC_CNTL_WIFI_ISO_V 0x1 +#define RTC_CNTL_WIFI_ISO_S 5 +/* RTC_CNTL_XPD_RTC_PERI : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc peripheral power down*/ +#define RTC_CNTL_XPD_RTC_PERI (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_M (BIT(4)) +#define RTC_CNTL_XPD_RTC_PERI_V 0x1 +#define RTC_CNTL_XPD_RTC_PERI_S 4 +/* RTC_CNTL_PERI_ISO : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc peripheral iso*/ +#define RTC_CNTL_PERI_ISO (BIT(3)) +#define RTC_CNTL_PERI_ISO_M (BIT(3)) +#define RTC_CNTL_PERI_ISO_V 0x1 +#define RTC_CNTL_PERI_ISO_S 3 +/* RTC_CNTL_XPD_DIG_DCDC : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: External DCDC power down*/ +#define RTC_CNTL_XPD_DIG_DCDC (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_M (BIT(2)) +#define RTC_CNTL_XPD_DIG_DCDC_V 0x1 +#define RTC_CNTL_XPD_DIG_DCDC_S 2 +/* RTC_CNTL_XPD_ROM0 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: rom0 power down*/ +#define RTC_CNTL_XPD_ROM0 (BIT(0)) +#define RTC_CNTL_XPD_ROM0_M (BIT(0)) +#define RTC_CNTL_XPD_ROM0_V 0x1 +#define RTC_CNTL_XPD_ROM0_S 0 + +#define RTC_CNTL_DIAG0_REG (DR_REG_RTCCNTL_BASE + 0x00D0) +/* RTC_CNTL_LOW_POWER_DIAG1 : RO ;bitpos:[31:0] ;default: 0 ; */ +/*description: */ +#define RTC_CNTL_LOW_POWER_DIAG1 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_M ((RTC_CNTL_LOW_POWER_DIAG1_V) << (RTC_CNTL_LOW_POWER_DIAG1_S)) +#define RTC_CNTL_LOW_POWER_DIAG1_V 0xFFFFFFFF +#define RTC_CNTL_LOW_POWER_DIAG1_S 0 + +#define RTC_CNTL_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D4) +/* RTC_CNTL_PAD21_HOLD : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PAD21_HOLD (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_M (BIT(21)) +#define RTC_CNTL_PAD21_HOLD_V 0x1 +#define RTC_CNTL_PAD21_HOLD_S 21 +/* RTC_CNTL_PAD20_HOLD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PAD20_HOLD (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_M (BIT(20)) +#define RTC_CNTL_PAD20_HOLD_V 0x1 +#define RTC_CNTL_PAD20_HOLD_S 20 +/* RTC_CNTL_PAD19_HOLD : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PAD19_HOLD (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_M (BIT(19)) +#define RTC_CNTL_PAD19_HOLD_V 0x1 +#define RTC_CNTL_PAD19_HOLD_S 19 +/* RTC_CNTL_PDAC2_HOLD : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC2_HOLD (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_M (BIT(18)) +#define RTC_CNTL_PDAC2_HOLD_V 0x1 +#define RTC_CNTL_PDAC2_HOLD_S 18 +/* RTC_CNTL_PDAC1_HOLD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_PDAC1_HOLD (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_M (BIT(17)) +#define RTC_CNTL_PDAC1_HOLD_V 0x1 +#define RTC_CNTL_PDAC1_HOLD_S 17 +/* RTC_CNTL_X32N_HOLD : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32N_HOLD (BIT(16)) +#define RTC_CNTL_X32N_HOLD_M (BIT(16)) +#define RTC_CNTL_X32N_HOLD_V 0x1 +#define RTC_CNTL_X32N_HOLD_S 16 +/* RTC_CNTL_X32P_HOLD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_X32P_HOLD (BIT(15)) +#define RTC_CNTL_X32P_HOLD_M (BIT(15)) +#define RTC_CNTL_X32P_HOLD_V 0x1 +#define RTC_CNTL_X32P_HOLD_S 15 +/* RTC_CNTL_TOUCH_PAD14_HOLD : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD14_HOLD (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_M (BIT(14)) +#define RTC_CNTL_TOUCH_PAD14_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD14_HOLD_S 14 +/* RTC_CNTL_TOUCH_PAD13_HOLD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD13_HOLD (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_M (BIT(13)) +#define RTC_CNTL_TOUCH_PAD13_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD13_HOLD_S 13 +/* RTC_CNTL_TOUCH_PAD12_HOLD : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD12_HOLD (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_M (BIT(12)) +#define RTC_CNTL_TOUCH_PAD12_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD12_HOLD_S 12 +/* RTC_CNTL_TOUCH_PAD11_HOLD : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD11_HOLD (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_M (BIT(11)) +#define RTC_CNTL_TOUCH_PAD11_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD11_HOLD_S 11 +/* RTC_CNTL_TOUCH_PAD10_HOLD : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD10_HOLD (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_M (BIT(10)) +#define RTC_CNTL_TOUCH_PAD10_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD10_HOLD_S 10 +/* RTC_CNTL_TOUCH_PAD9_HOLD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD9_HOLD (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_M (BIT(9)) +#define RTC_CNTL_TOUCH_PAD9_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD9_HOLD_S 9 +/* RTC_CNTL_TOUCH_PAD8_HOLD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD8_HOLD (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_M (BIT(8)) +#define RTC_CNTL_TOUCH_PAD8_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD8_HOLD_S 8 +/* RTC_CNTL_TOUCH_PAD7_HOLD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD7_HOLD (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_M (BIT(7)) +#define RTC_CNTL_TOUCH_PAD7_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD7_HOLD_S 7 +/* RTC_CNTL_TOUCH_PAD6_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD6_HOLD (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_M (BIT(6)) +#define RTC_CNTL_TOUCH_PAD6_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD6_HOLD_S 6 +/* RTC_CNTL_TOUCH_PAD5_HOLD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD5_HOLD (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_M (BIT(5)) +#define RTC_CNTL_TOUCH_PAD5_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD5_HOLD_S 5 +/* RTC_CNTL_TOUCH_PAD4_HOLD : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD4_HOLD (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_M (BIT(4)) +#define RTC_CNTL_TOUCH_PAD4_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD4_HOLD_S 4 +/* RTC_CNTL_TOUCH_PAD3_HOLD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD3_HOLD (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_M (BIT(3)) +#define RTC_CNTL_TOUCH_PAD3_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD3_HOLD_S 3 +/* RTC_CNTL_TOUCH_PAD2_HOLD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD2_HOLD (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_M (BIT(2)) +#define RTC_CNTL_TOUCH_PAD2_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD2_HOLD_S 2 +/* RTC_CNTL_TOUCH_PAD1_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD1_HOLD (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_M (BIT(1)) +#define RTC_CNTL_TOUCH_PAD1_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD1_HOLD_S 1 +/* RTC_CNTL_TOUCH_PAD0_HOLD : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_PAD0_HOLD (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_M (BIT(0)) +#define RTC_CNTL_TOUCH_PAD0_HOLD_V 0x1 +#define RTC_CNTL_TOUCH_PAD0_HOLD_S 0 + +#define RTC_CNTL_DIG_PAD_HOLD_REG (DR_REG_RTCCNTL_BASE + 0x00D8) +/* RTC_CNTL_DIG_PAD_HOLD : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define RTC_CNTL_DIG_PAD_HOLD 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_M ((RTC_CNTL_DIG_PAD_HOLD_V) << (RTC_CNTL_DIG_PAD_HOLD_S)) +#define RTC_CNTL_DIG_PAD_HOLD_V 0xFFFFFFFF +#define RTC_CNTL_DIG_PAD_HOLD_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_REG (DR_REG_RTCCNTL_BASE + 0x00DC) +/* RTC_CNTL_EXT_WAKEUP1_STATUS_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: clear ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_M (BIT(22)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_V 0x1 +#define RTC_CNTL_EXT_WAKEUP1_STATUS_CLR_S 22 +/* RTC_CNTL_EXT_WAKEUP1_SEL : R/W ;bitpos:[21:0] ;default: 22'd0 ; */ +/*description: Bitmap to select RTC pads for ext wakeup1*/ +#define RTC_CNTL_EXT_WAKEUP1_SEL 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_M ((RTC_CNTL_EXT_WAKEUP1_SEL_V) << (RTC_CNTL_EXT_WAKEUP1_SEL_S)) +#define RTC_CNTL_EXT_WAKEUP1_SEL_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_SEL_S 0 + +#define RTC_CNTL_EXT_WAKEUP1_STATUS_REG (DR_REG_RTCCNTL_BASE + 0x00E0) +/* RTC_CNTL_EXT_WAKEUP1_STATUS : RO ;bitpos:[21:0] ;default: 22'd0 ; */ +/*description: ext wakeup1 status*/ +#define RTC_CNTL_EXT_WAKEUP1_STATUS 0x003FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_M ((RTC_CNTL_EXT_WAKEUP1_STATUS_V) << (RTC_CNTL_EXT_WAKEUP1_STATUS_S)) +#define RTC_CNTL_EXT_WAKEUP1_STATUS_V 0x3FFFFF +#define RTC_CNTL_EXT_WAKEUP1_STATUS_S 0 + +#define RTC_CNTL_BROWN_OUT_REG (DR_REG_RTCCNTL_BASE + 0x00E4) +/* RTC_CNTL_BROWN_OUT_DET : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BROWN_OUT_DET (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_M (BIT(31)) +#define RTC_CNTL_BROWN_OUT_DET_V 0x1 +#define RTC_CNTL_BROWN_OUT_DET_S 31 +/* RTC_CNTL_BROWN_OUT_ENA : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: enable brown out*/ +#define RTC_CNTL_BROWN_OUT_ENA (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_M (BIT(30)) +#define RTC_CNTL_BROWN_OUT_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_ENA_S 30 +/* RTC_CNTL_BROWN_OUT_CNT_CLR : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: clear brown out counter*/ +#define RTC_CNTL_BROWN_OUT_CNT_CLR (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_M (BIT(29)) +#define RTC_CNTL_BROWN_OUT_CNT_CLR_V 0x1 +#define RTC_CNTL_BROWN_OUT_CNT_CLR_S 29 +/* RTC_CNTL_BROWN_OUT_ANA_RST_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_M (BIT(28)) +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_V 0x1 +#define RTC_CNTL_BROWN_OUT_ANA_RST_EN_S 28 +/* RTC_CNTL_BROWN_OUT_RST_SEL : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: 1: 4-pos reset*/ +#define RTC_CNTL_BROWN_OUT_RST_SEL (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_M (BIT(27)) +#define RTC_CNTL_BROWN_OUT_RST_SEL_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_SEL_S 27 +/* RTC_CNTL_BROWN_OUT_RST_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: enable brown out reset*/ +#define RTC_CNTL_BROWN_OUT_RST_ENA (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_M (BIT(26)) +#define RTC_CNTL_BROWN_OUT_RST_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_RST_ENA_S 26 +/* RTC_CNTL_BROWN_OUT_RST_WAIT : R/W ;bitpos:[25:16] ;default: 10'h3ff ; */ +/*description: brown out reset wait cycles*/ +#define RTC_CNTL_BROWN_OUT_RST_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_M ((RTC_CNTL_BROWN_OUT_RST_WAIT_V) << (RTC_CNTL_BROWN_OUT_RST_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_RST_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_RST_WAIT_S 16 +/* RTC_CNTL_BROWN_OUT_PD_RF_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable power down RF when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_M (BIT(15)) +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_PD_RF_ENA_S 15 +/* RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable close flash when brown out happens*/ +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_M (BIT(14)) +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_V 0x1 +#define RTC_CNTL_BROWN_OUT_CLOSE_FLASH_ENA_S 14 +/* RTC_CNTL_BROWN_OUT_INT_WAIT : R/W ;bitpos:[13:4] ;default: 10'h1 ; */ +/*description: brown out interrupt wait cycles*/ +#define RTC_CNTL_BROWN_OUT_INT_WAIT 0x000003FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_M ((RTC_CNTL_BROWN_OUT_INT_WAIT_V) << (RTC_CNTL_BROWN_OUT_INT_WAIT_S)) +#define RTC_CNTL_BROWN_OUT_INT_WAIT_V 0x3FF +#define RTC_CNTL_BROWN_OUT_INT_WAIT_S 4 + +#define RTC_CNTL_TIME_LOW1_REG (DR_REG_RTCCNTL_BASE + 0x00E8) +/* RTC_CNTL_TIMER_VALUE1_LOW : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: RTC timer low 32 bits*/ +#define RTC_CNTL_TIMER_VALUE1_LOW 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_M ((RTC_CNTL_TIMER_VALUE1_LOW_V) << (RTC_CNTL_TIMER_VALUE1_LOW_S)) +#define RTC_CNTL_TIMER_VALUE1_LOW_V 0xFFFFFFFF +#define RTC_CNTL_TIMER_VALUE1_LOW_S 0 + +#define RTC_CNTL_TIME_HIGH1_REG (DR_REG_RTCCNTL_BASE + 0x00EC) +/* RTC_CNTL_TIMER_VALUE1_HIGH : RO ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: RTC timer high 16 bits*/ +#define RTC_CNTL_TIMER_VALUE1_HIGH 0x0000FFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_M ((RTC_CNTL_TIMER_VALUE1_HIGH_V) << (RTC_CNTL_TIMER_VALUE1_HIGH_S)) +#define RTC_CNTL_TIMER_VALUE1_HIGH_V 0xFFFF +#define RTC_CNTL_TIMER_VALUE1_HIGH_S 0 + +#define RTC_CNTL_XTAL32K_CLK_FACTOR_REG (DR_REG_RTCCNTL_BASE + 0x00F0) +/* RTC_CNTL_XTAL32K_CLK_FACTOR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: xtal 32k watch dog backup clock factor*/ +#define RTC_CNTL_XTAL32K_CLK_FACTOR 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_M ((RTC_CNTL_XTAL32K_CLK_FACTOR_V) << (RTC_CNTL_XTAL32K_CLK_FACTOR_S)) +#define RTC_CNTL_XTAL32K_CLK_FACTOR_V 0xFFFFFFFF +#define RTC_CNTL_XTAL32K_CLK_FACTOR_S 0 + +#define RTC_CNTL_XTAL32K_CONF_REG (DR_REG_RTCCNTL_BASE + 0x00F4) +/* RTC_CNTL_XTAL32K_STABLE_THRES : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: if restarted xtal32k period is smaller than this*/ +#define RTC_CNTL_XTAL32K_STABLE_THRES 0x0000000F +#define RTC_CNTL_XTAL32K_STABLE_THRES_M ((RTC_CNTL_XTAL32K_STABLE_THRES_V) << (RTC_CNTL_XTAL32K_STABLE_THRES_S)) +#define RTC_CNTL_XTAL32K_STABLE_THRES_V 0xF +#define RTC_CNTL_XTAL32K_STABLE_THRES_S 28 +/* RTC_CNTL_XTAL32K_WDT_TIMEOUT : R/W ;bitpos:[27:20] ;default: 8'hff ; */ +/*description: If no clock detected for this amount of time*/ +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT 0x000000FF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_M ((RTC_CNTL_XTAL32K_WDT_TIMEOUT_V) << (RTC_CNTL_XTAL32K_WDT_TIMEOUT_S)) +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_V 0xFF +#define RTC_CNTL_XTAL32K_WDT_TIMEOUT_S 20 +/* RTC_CNTL_XTAL32K_RESTART_WAIT : R/W ;bitpos:[19:4] ;default: 16'h0 ; */ +/*description: cycles to wait to repower on xtal 32k*/ +#define RTC_CNTL_XTAL32K_RESTART_WAIT 0x0000FFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_M ((RTC_CNTL_XTAL32K_RESTART_WAIT_V) << (RTC_CNTL_XTAL32K_RESTART_WAIT_S)) +#define RTC_CNTL_XTAL32K_RESTART_WAIT_V 0xFFFF +#define RTC_CNTL_XTAL32K_RESTART_WAIT_S 4 +/* RTC_CNTL_XTAL32K_RETURN_WAIT : R/W ;bitpos:[3:0] ;default: 4'h0 ; */ +/*description: cycles to wait to return noral xtal 32k*/ +#define RTC_CNTL_XTAL32K_RETURN_WAIT 0x0000000F +#define RTC_CNTL_XTAL32K_RETURN_WAIT_M ((RTC_CNTL_XTAL32K_RETURN_WAIT_V) << (RTC_CNTL_XTAL32K_RETURN_WAIT_S)) +#define RTC_CNTL_XTAL32K_RETURN_WAIT_V 0xF +#define RTC_CNTL_XTAL32K_RETURN_WAIT_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_REG (DR_REG_RTCCNTL_BASE + 0x00F8) +/* RTC_CNTL_ULP_CP_SLP_TIMER_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: ULP-coprocessor timer enable bit*/ +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_M (BIT(31)) +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_ULP_CP_SLP_TIMER_EN_S 31 +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR : WO ;bitpos:[30] ;default: 1'd0 ; */ +/*description: ULP-coprocessor wakeup by GPIO state clear*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_M (BIT(30)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_CLR_S 30 +/* RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ULP-coprocessor wakeup by GPIO enable*/ +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_M (BIT(29)) +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_V 0x1 +#define RTC_CNTL_ULP_CP_GPIO_WAKEUP_ENA_S 29 +/* RTC_CNTL_ULP_CP_PC_INIT : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ +/*description: ULP-coprocessor PC initial address*/ +#define RTC_CNTL_ULP_CP_PC_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_PC_INIT_M ((RTC_CNTL_ULP_CP_PC_INIT_V) << (RTC_CNTL_ULP_CP_PC_INIT_S)) +#define RTC_CNTL_ULP_CP_PC_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_PC_INIT_S 0 + +#define RTC_CNTL_ULP_CP_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x00FC) +/* RTC_CNTL_ULP_CP_START_TOP : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: Write 1 to start ULP-coprocessor*/ +#define RTC_CNTL_ULP_CP_START_TOP (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_M (BIT(31)) +#define RTC_CNTL_ULP_CP_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_START_TOP_S 31 +/* RTC_CNTL_ULP_CP_FORCE_START_TOP : R/W ;bitpos:[30] ;default: 1'd0 ; */ +/*description: 1: ULP-coprocessor is started by SW*/ +#define RTC_CNTL_ULP_CP_FORCE_START_TOP (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_M (BIT(30)) +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_V 0x1 +#define RTC_CNTL_ULP_CP_FORCE_START_TOP_S 30 +/* RTC_CNTL_ULP_CP_RESET : R/W ;bitpos:[29] ;default: 1'd0 ; */ +/*description: ulp coprocessor clk software reset*/ +#define RTC_CNTL_ULP_CP_RESET (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_M (BIT(29)) +#define RTC_CNTL_ULP_CP_RESET_V 0x1 +#define RTC_CNTL_ULP_CP_RESET_S 29 +/* RTC_CNTL_ULP_CP_CLK_FO : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: ulp coprocessor clk force on*/ +#define RTC_CNTL_ULP_CP_CLK_FO (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_M (BIT(28)) +#define RTC_CNTL_ULP_CP_CLK_FO_V 0x1 +#define RTC_CNTL_ULP_CP_CLK_FO_S 28 +/* RTC_CNTL_ULP_CP_MEM_OFFST_CLR : WO ;bitpos:[22] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_M (BIT(22)) +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_V 0x1 +#define RTC_CNTL_ULP_CP_MEM_OFFST_CLR_S 22 +/* RTC_CNTL_ULP_CP_MEM_ADDR_SIZE : R/W ;bitpos:[21:11] ;default: 11'd512 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_M ((RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V) << (RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_SIZE_S 11 +/* RTC_CNTL_ULP_CP_MEM_ADDR_INIT : R/W ;bitpos:[10:0] ;default: 11'd512 ; */ +/*description: */ +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT 0x000007FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_M ((RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V) << (RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S)) +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_V 0x7FF +#define RTC_CNTL_ULP_CP_MEM_ADDR_INIT_S 0 + +#define RTC_CNTL_COCPU_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0100) +/* RTC_CNTL_COCPU_CLKGATE_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_COCPU_CLKGATE_EN (BIT(27)) +#define RTC_CNTL_COCPU_CLKGATE_EN_M (BIT(27)) +#define RTC_CNTL_COCPU_CLKGATE_EN_V 0x1 +#define RTC_CNTL_COCPU_CLKGATE_EN_S 27 +/* RTC_CNTL_COCPU_SW_INT_TRIGGER : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: trigger cocpu register interrupt*/ +#define RTC_CNTL_COCPU_SW_INT_TRIGGER (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_M (BIT(26)) +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_V 0x1 +#define RTC_CNTL_COCPU_SW_INT_TRIGGER_S 26 +/* RTC_CNTL_COCPU_DONE : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: done signal used by riscv to control timer.*/ +#define RTC_CNTL_COCPU_DONE (BIT(25)) +#define RTC_CNTL_COCPU_DONE_M (BIT(25)) +#define RTC_CNTL_COCPU_DONE_V 0x1 +#define RTC_CNTL_COCPU_DONE_S 25 +/* RTC_CNTL_COCPU_DONE_FORCE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: select riscv done 0: select ulp done*/ +#define RTC_CNTL_COCPU_DONE_FORCE (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_M (BIT(24)) +#define RTC_CNTL_COCPU_DONE_FORCE_V 0x1 +#define RTC_CNTL_COCPU_DONE_FORCE_S 24 +/* RTC_CNTL_COCPU_SEL : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: 1: old ULP 0: new riscV*/ +#define RTC_CNTL_COCPU_SEL (BIT(23)) +#define RTC_CNTL_COCPU_SEL_M (BIT(23)) +#define RTC_CNTL_COCPU_SEL_V 0x1 +#define RTC_CNTL_COCPU_SEL_S 23 +/* RTC_CNTL_COCPU_SHUT_RESET_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: to reset cocpu*/ +#define RTC_CNTL_COCPU_SHUT_RESET_EN (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_M (BIT(22)) +#define RTC_CNTL_COCPU_SHUT_RESET_EN_V 0x1 +#define RTC_CNTL_COCPU_SHUT_RESET_EN_S 22 +/* RTC_CNTL_COCPU_SHUT_2_CLK_DIS : R/W ;bitpos:[21:14] ;default: 8'd40 ; */ +/*description: time from shut cocpu to disable clk*/ +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS 0x000000FF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_M ((RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V) << (RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S)) +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_V 0xFF +#define RTC_CNTL_COCPU_SHUT_2_CLK_DIS_S 14 +/* RTC_CNTL_COCPU_SHUT : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: to shut cocpu*/ +#define RTC_CNTL_COCPU_SHUT (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_M (BIT(13)) +#define RTC_CNTL_COCPU_SHUT_V 0x1 +#define RTC_CNTL_COCPU_SHUT_S 13 +/* RTC_CNTL_COCPU_START_2_INTR_EN : R/W ;bitpos:[12:7] ;default: 6'd16 ; */ +/*description: time from start cocpu to give start interrupt*/ +#define RTC_CNTL_COCPU_START_2_INTR_EN 0x0000003F +#define RTC_CNTL_COCPU_START_2_INTR_EN_M ((RTC_CNTL_COCPU_START_2_INTR_EN_V) << (RTC_CNTL_COCPU_START_2_INTR_EN_S)) +#define RTC_CNTL_COCPU_START_2_INTR_EN_V 0x3F +#define RTC_CNTL_COCPU_START_2_INTR_EN_S 7 +/* RTC_CNTL_COCPU_START_2_RESET_DIS : R/W ;bitpos:[6:1] ;default: 6'd8 ; */ +/*description: time from start cocpu to pull down reset*/ +#define RTC_CNTL_COCPU_START_2_RESET_DIS 0x0000003F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_M ((RTC_CNTL_COCPU_START_2_RESET_DIS_V) << (RTC_CNTL_COCPU_START_2_RESET_DIS_S)) +#define RTC_CNTL_COCPU_START_2_RESET_DIS_V 0x3F +#define RTC_CNTL_COCPU_START_2_RESET_DIS_S 1 +/* RTC_CNTL_COCPU_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: cocpu clk force on*/ +#define RTC_CNTL_COCPU_CLK_FO (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_M (BIT(0)) +#define RTC_CNTL_COCPU_CLK_FO_V 0x1 +#define RTC_CNTL_COCPU_CLK_FO_S 0 + +#define RTC_CNTL_TOUCH_CTRL1_REG (DR_REG_RTCCNTL_BASE + 0x0104) +/* RTC_CNTL_TOUCH_MEAS_NUM : R/W ;bitpos:[31:16] ;default: 16'h1000 ; */ +/*description: the meas length (in 8MHz)*/ +#define RTC_CNTL_TOUCH_MEAS_NUM 0x0000FFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_M ((RTC_CNTL_TOUCH_MEAS_NUM_V) << (RTC_CNTL_TOUCH_MEAS_NUM_S)) +#define RTC_CNTL_TOUCH_MEAS_NUM_V 0xFFFF +#define RTC_CNTL_TOUCH_MEAS_NUM_S 16 +/* RTC_CNTL_TOUCH_SLEEP_CYCLES : R/W ;bitpos:[15:0] ;default: 16'h100 ; */ +/*description: sleep cycles for timer*/ +#define RTC_CNTL_TOUCH_SLEEP_CYCLES 0x0000FFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_M ((RTC_CNTL_TOUCH_SLEEP_CYCLES_V) << (RTC_CNTL_TOUCH_SLEEP_CYCLES_S)) +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_V 0xFFFF +#define RTC_CNTL_TOUCH_SLEEP_CYCLES_S 0 + +#define RTC_CNTL_TOUCH_CTRL2_REG (DR_REG_RTCCNTL_BASE + 0x0108) +/* RTC_CNTL_TOUCH_CLKGATE_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: touch clock enable*/ +#define RTC_CNTL_TOUCH_CLKGATE_EN (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_CLKGATE_EN_V 0x1 +#define RTC_CNTL_TOUCH_CLKGATE_EN_S 31 +/* RTC_CNTL_TOUCH_CLK_FO : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: touch clock force on*/ +#define RTC_CNTL_TOUCH_CLK_FO (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_M (BIT(30)) +#define RTC_CNTL_TOUCH_CLK_FO_V 0x1 +#define RTC_CNTL_TOUCH_CLK_FO_S 30 +/* RTC_CNTL_TOUCH_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: reset upgrade touch*/ +#define RTC_CNTL_TOUCH_RESET (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_M (BIT(29)) +#define RTC_CNTL_TOUCH_RESET_V 0x1 +#define RTC_CNTL_TOUCH_RESET_S 29 +/* RTC_CNTL_TOUCH_TIMER_FORCE_DONE : R/W ;bitpos:[28:27] ;default: 2'b0 ; */ +/*description: force touch timer done*/ +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE 0x00000003 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_M ((RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V) << (RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S)) +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_V 0x3 +#define RTC_CNTL_TOUCH_TIMER_FORCE_DONE_S 27 +/* RTC_CNTL_TOUCH_SLP_CYC_DIV : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ +/*description: when a touch pad is active*/ +#define RTC_CNTL_TOUCH_SLP_CYC_DIV 0x00000003 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_M ((RTC_CNTL_TOUCH_SLP_CYC_DIV_V) << (RTC_CNTL_TOUCH_SLP_CYC_DIV_S)) +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_V 0x3 +#define RTC_CNTL_TOUCH_SLP_CYC_DIV_S 25 +/* RTC_CNTL_TOUCH_XPD_WAIT : R/W ;bitpos:[24:17] ;default: 8'h4 ; */ +/*description: the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ +#define RTC_CNTL_TOUCH_XPD_WAIT 0x000000FF +#define RTC_CNTL_TOUCH_XPD_WAIT_M ((RTC_CNTL_TOUCH_XPD_WAIT_V) << (RTC_CNTL_TOUCH_XPD_WAIT_S)) +#define RTC_CNTL_TOUCH_XPD_WAIT_V 0xFF +#define RTC_CNTL_TOUCH_XPD_WAIT_S 17 +/* RTC_CNTL_TOUCH_START_FORCE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1: to start touch fsm by SW*/ +#define RTC_CNTL_TOUCH_START_FORCE (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_M (BIT(16)) +#define RTC_CNTL_TOUCH_START_FORCE_V 0x1 +#define RTC_CNTL_TOUCH_START_FORCE_S 16 +/* RTC_CNTL_TOUCH_START_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: start touch fsm*/ +#define RTC_CNTL_TOUCH_START_EN (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_M (BIT(15)) +#define RTC_CNTL_TOUCH_START_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_EN_S 15 +/* RTC_CNTL_TOUCH_START_FSM_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: 1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ +#define RTC_CNTL_TOUCH_START_FSM_EN (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_M (BIT(14)) +#define RTC_CNTL_TOUCH_START_FSM_EN_V 0x1 +#define RTC_CNTL_TOUCH_START_FSM_EN_S 14 +/* RTC_CNTL_TOUCH_SLP_TIMER_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: touch timer enable bit*/ +#define RTC_CNTL_TOUCH_SLP_TIMER_EN (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_M (BIT(13)) +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_TIMER_EN_S 13 +/* RTC_CNTL_TOUCH_DBIAS : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: 1:use self bias 0:use bandgap bias*/ +#define RTC_CNTL_TOUCH_DBIAS (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_M (BIT(12)) +#define RTC_CNTL_TOUCH_DBIAS_V 0x1 +#define RTC_CNTL_TOUCH_DBIAS_S 12 +/* RTC_CNTL_TOUCH_REFC : R/W ;bitpos:[11:9] ;default: 3'h0 ; */ +/*description: TOUCH pad0 reference cap*/ +#define RTC_CNTL_TOUCH_REFC 0x00000007 +#define RTC_CNTL_TOUCH_REFC_M ((RTC_CNTL_TOUCH_REFC_V) << (RTC_CNTL_TOUCH_REFC_S)) +#define RTC_CNTL_TOUCH_REFC_V 0x7 +#define RTC_CNTL_TOUCH_REFC_S 9 +/* RTC_CNTL_TOUCH_XPD_BIAS : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: TOUCH_XPD_BIAS*/ +#define RTC_CNTL_TOUCH_XPD_BIAS (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_M (BIT(8)) +#define RTC_CNTL_TOUCH_XPD_BIAS_V 0x1 +#define RTC_CNTL_TOUCH_XPD_BIAS_S 8 +/* RTC_CNTL_TOUCH_DREFH : R/W ;bitpos:[7:6] ;default: 2'b11 ; */ +/*description: TOUCH_DREFH*/ +#define RTC_CNTL_TOUCH_DREFH 0x00000003 +#define RTC_CNTL_TOUCH_DREFH_M ((RTC_CNTL_TOUCH_DREFH_V) << (RTC_CNTL_TOUCH_DREFH_S)) +#define RTC_CNTL_TOUCH_DREFH_V 0x3 +#define RTC_CNTL_TOUCH_DREFH_S 6 +/* RTC_CNTL_TOUCH_DREFL : R/W ;bitpos:[5:4] ;default: 2'b00 ; */ +/*description: TOUCH_DREFL*/ +#define RTC_CNTL_TOUCH_DREFL 0x00000003 +#define RTC_CNTL_TOUCH_DREFL_M ((RTC_CNTL_TOUCH_DREFL_V) << (RTC_CNTL_TOUCH_DREFL_S)) +#define RTC_CNTL_TOUCH_DREFL_V 0x3 +#define RTC_CNTL_TOUCH_DREFL_S 4 +/* RTC_CNTL_TOUCH_DRANGE : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: TOUCH_DRANGE*/ +#define RTC_CNTL_TOUCH_DRANGE 0x00000003 +#define RTC_CNTL_TOUCH_DRANGE_M ((RTC_CNTL_TOUCH_DRANGE_V) << (RTC_CNTL_TOUCH_DRANGE_S)) +#define RTC_CNTL_TOUCH_DRANGE_V 0x3 +#define RTC_CNTL_TOUCH_DRANGE_S 2 + +#define RTC_CNTL_TOUCH_SCAN_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x010C) +/* RTC_CNTL_TOUCH_OUT_RING : R/W ;bitpos:[31:28] ;default: 4'hf ; */ +/*description: select out ring pad*/ +#define RTC_CNTL_TOUCH_OUT_RING 0x0000000F +#define RTC_CNTL_TOUCH_OUT_RING_M ((RTC_CNTL_TOUCH_OUT_RING_V) << (RTC_CNTL_TOUCH_OUT_RING_S)) +#define RTC_CNTL_TOUCH_OUT_RING_V 0xF +#define RTC_CNTL_TOUCH_OUT_RING_S 28 +/* RTC_CNTL_TOUCH_BUFDRV : R/W ;bitpos:[27:25] ;default: 3'h0 ; */ +/*description: touch7 buffer driver strength*/ +#define RTC_CNTL_TOUCH_BUFDRV 0x00000007 +#define RTC_CNTL_TOUCH_BUFDRV_M ((RTC_CNTL_TOUCH_BUFDRV_V) << (RTC_CNTL_TOUCH_BUFDRV_S)) +#define RTC_CNTL_TOUCH_BUFDRV_V 0x7 +#define RTC_CNTL_TOUCH_BUFDRV_S 25 +/* RTC_CNTL_TOUCH_SCAN_PAD_MAP : R/W ;bitpos:[24:10] ;default: 15'h0 ; */ +/*description: touch scan mode pad enable map*/ +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP 0x00007FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_M ((RTC_CNTL_TOUCH_SCAN_PAD_MAP_V) << (RTC_CNTL_TOUCH_SCAN_PAD_MAP_S)) +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_V 0x7FFF +#define RTC_CNTL_TOUCH_SCAN_PAD_MAP_S 10 +/* RTC_CNTL_TOUCH_SHIELD_PAD_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: touch pad14 will be used as shield*/ +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_M (BIT(9)) +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_V 0x1 +#define RTC_CNTL_TOUCH_SHIELD_PAD_EN_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_CONNECTION : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: inactive touch pads connect to 1: gnd 0: HighZ*/ +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_CONNECTION_S 8 +/* RTC_CNTL_TOUCH_DENOISE_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: touch pad0 will be used to de-noise*/ +#define RTC_CNTL_TOUCH_DENOISE_EN (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_M (BIT(2)) +#define RTC_CNTL_TOUCH_DENOISE_EN_V 0x1 +#define RTC_CNTL_TOUCH_DENOISE_EN_S 2 +/* RTC_CNTL_TOUCH_DENOISE_RES : R/W ;bitpos:[1:0] ;default: 2'd2 ; */ +/*description: De-noise resolution: 12/10/8/4 bit*/ +#define RTC_CNTL_TOUCH_DENOISE_RES 0x00000003 +#define RTC_CNTL_TOUCH_DENOISE_RES_M ((RTC_CNTL_TOUCH_DENOISE_RES_V) << (RTC_CNTL_TOUCH_DENOISE_RES_S)) +#define RTC_CNTL_TOUCH_DENOISE_RES_V 0x3 +#define RTC_CNTL_TOUCH_DENOISE_RES_S 0 + +#define RTC_CNTL_TOUCH_SLP_THRES_REG (DR_REG_RTCCNTL_BASE + 0x0110) +/* RTC_CNTL_TOUCH_SLP_PAD : R/W ;bitpos:[31:27] ;default: 4'hF ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SLP_PAD 0x0000001F +#define RTC_CNTL_TOUCH_SLP_PAD_M ((RTC_CNTL_TOUCH_SLP_PAD_V) << (RTC_CNTL_TOUCH_SLP_PAD_S)) +#define RTC_CNTL_TOUCH_SLP_PAD_V 0x1F +#define RTC_CNTL_TOUCH_SLP_PAD_S 27 +/* RTC_CNTL_TOUCH_SLP_APPROACH_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: sleep pad approach function enable*/ +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_M (BIT(26)) +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_V 0x1 +#define RTC_CNTL_TOUCH_SLP_APPROACH_EN_S 26 +/* RTC_CNTL_TOUCH_SLP_TH : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the threshold for sleep touch pad*/ +#define RTC_CNTL_TOUCH_SLP_TH 0x003FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_M ((RTC_CNTL_TOUCH_SLP_TH_V) << (RTC_CNTL_TOUCH_SLP_TH_S)) +#define RTC_CNTL_TOUCH_SLP_TH_V 0x3FFFFF +#define RTC_CNTL_TOUCH_SLP_TH_S 0 + +#define RTC_CNTL_TOUCH_APPROACH_REG (DR_REG_RTCCNTL_BASE + 0x0114) +/* RTC_CNTL_TOUCH_APPROACH_MEAS_TIME : R/W ;bitpos:[31:24] ;default: 8'd80 ; */ +/*description: approach pads total meas times*/ +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME 0x000000FF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_M ((RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V) << (RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S)) +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_V 0xFF +#define RTC_CNTL_TOUCH_APPROACH_MEAS_TIME_S 24 +/* RTC_CNTL_TOUCH_SLP_CHANNEL_CLR : WO ;bitpos:[23] ;default: 1'd0 ; */ +/*description: clear touch slp channel*/ +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_M (BIT(23)) +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_V 0x1 +#define RTC_CNTL_TOUCH_SLP_CHANNEL_CLR_S 23 + +#define RTC_CNTL_TOUCH_FILTER_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0118) +/* RTC_CNTL_TOUCH_FILTER_EN : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: touch filter enable*/ +#define RTC_CNTL_TOUCH_FILTER_EN (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_M (BIT(31)) +#define RTC_CNTL_TOUCH_FILTER_EN_V 0x1 +#define RTC_CNTL_TOUCH_FILTER_EN_S 31 +/* RTC_CNTL_TOUCH_FILTER_MODE : R/W ;bitpos:[30:28] ;default: 3'd1 ; */ +/*description: 0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ +#define RTC_CNTL_TOUCH_FILTER_MODE 0x00000007 +#define RTC_CNTL_TOUCH_FILTER_MODE_M ((RTC_CNTL_TOUCH_FILTER_MODE_V) << (RTC_CNTL_TOUCH_FILTER_MODE_S)) +#define RTC_CNTL_TOUCH_FILTER_MODE_V 0x7 +#define RTC_CNTL_TOUCH_FILTER_MODE_S 28 +/* RTC_CNTL_TOUCH_DEBOUNCE : R/W ;bitpos:[27:25] ;default: 3'd3 ; */ +/*description: debounce counter*/ +#define RTC_CNTL_TOUCH_DEBOUNCE 0x00000007 +#define RTC_CNTL_TOUCH_DEBOUNCE_M ((RTC_CNTL_TOUCH_DEBOUNCE_V) << (RTC_CNTL_TOUCH_DEBOUNCE_S)) +#define RTC_CNTL_TOUCH_DEBOUNCE_V 0x7 +#define RTC_CNTL_TOUCH_DEBOUNCE_S 25 +/* RTC_CNTL_TOUCH_HYSTERESIS : R/W ;bitpos:[24:23] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_HYSTERESIS 0x00000003 +#define RTC_CNTL_TOUCH_HYSTERESIS_M ((RTC_CNTL_TOUCH_HYSTERESIS_V) << (RTC_CNTL_TOUCH_HYSTERESIS_S)) +#define RTC_CNTL_TOUCH_HYSTERESIS_V 0x3 +#define RTC_CNTL_TOUCH_HYSTERESIS_S 23 +/* RTC_CNTL_TOUCH_NOISE_THRES : R/W ;bitpos:[22:21] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NOISE_THRES_M ((RTC_CNTL_TOUCH_NOISE_THRES_V) << (RTC_CNTL_TOUCH_NOISE_THRES_S)) +#define RTC_CNTL_TOUCH_NOISE_THRES_V 0x3 +#define RTC_CNTL_TOUCH_NOISE_THRES_S 21 +/* RTC_CNTL_TOUCH_NEG_NOISE_THRES : R/W ;bitpos:[20:19] ;default: 2'd1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES 0x00000003 +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_M ((RTC_CNTL_TOUCH_NEG_NOISE_THRES_V) << (RTC_CNTL_TOUCH_NEG_NOISE_THRES_S)) +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_V 0x3 +#define RTC_CNTL_TOUCH_NEG_NOISE_THRES_S 19 +/* RTC_CNTL_TOUCH_NEG_NOISE_LIMIT : R/W ;bitpos:[18:15] ;default: 4'd5 ; */ +/*description: negative threshold counter limit*/ +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT 0x0000000F +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_M ((RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V) << (RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S)) +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_V 0xF +#define RTC_CNTL_TOUCH_NEG_NOISE_LIMIT_S 15 +/* RTC_CNTL_TOUCH_JITTER_STEP : R/W ;bitpos:[14:11] ;default: 4'd1 ; */ +/*description: touch jitter step*/ +#define RTC_CNTL_TOUCH_JITTER_STEP 0x0000000F +#define RTC_CNTL_TOUCH_JITTER_STEP_M ((RTC_CNTL_TOUCH_JITTER_STEP_V) << (RTC_CNTL_TOUCH_JITTER_STEP_S)) +#define RTC_CNTL_TOUCH_JITTER_STEP_V 0xF +#define RTC_CNTL_TOUCH_JITTER_STEP_S 11 +/* RTC_CNTL_TOUCH_SMOOTH_LVL : R/W ;bitpos:[10:9] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_SMOOTH_LVL 0x00000003 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_M ((RTC_CNTL_TOUCH_SMOOTH_LVL_V) << (RTC_CNTL_TOUCH_SMOOTH_LVL_S)) +#define RTC_CNTL_TOUCH_SMOOTH_LVL_V 0x3 +#define RTC_CNTL_TOUCH_SMOOTH_LVL_S 9 +/* RTC_CNTL_TOUCH_BYPASS_NOISE_THRES : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES (BIT(8)) +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_M (BIT(8)) +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_V 0x1 +#define RTC_CNTL_TOUCH_BYPASS_NOISE_THRES_S 8 +/* RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES (BIT(7)) +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_M (BIT(7)) +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_V 0x1 +#define RTC_CNTL_TOUCH_BYPASS_NEG_NOISE_THRES_S 7 + +#define RTC_CNTL_USB_CONF_REG (DR_REG_RTCCNTL_BASE + 0x011C) +/* RTC_CNTL_IO_MUX_RESET_DISABLE : R/W ;bitpos:[18] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_IO_MUX_RESET_DISABLE (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_M (BIT(18)) +#define RTC_CNTL_IO_MUX_RESET_DISABLE_V 0x1 +#define RTC_CNTL_IO_MUX_RESET_DISABLE_S 18 +/* RTC_CNTL_USB_RESET_DISABLE : R/W ;bitpos:[17] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_RESET_DISABLE (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_M (BIT(17)) +#define RTC_CNTL_USB_RESET_DISABLE_V 0x1 +#define RTC_CNTL_USB_RESET_DISABLE_S 17 +/* RTC_CNTL_USB_TX_EN_OVERRIDE : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TX_EN_OVERRIDE (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_M (BIT(16)) +#define RTC_CNTL_USB_TX_EN_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_TX_EN_OVERRIDE_S 16 +/* RTC_CNTL_USB_TX_EN : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TX_EN (BIT(15)) +#define RTC_CNTL_USB_TX_EN_M (BIT(15)) +#define RTC_CNTL_USB_TX_EN_V 0x1 +#define RTC_CNTL_USB_TX_EN_S 15 +/* RTC_CNTL_USB_TXP : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TXP (BIT(14)) +#define RTC_CNTL_USB_TXP_M (BIT(14)) +#define RTC_CNTL_USB_TXP_V 0x1 +#define RTC_CNTL_USB_TXP_S 14 +/* RTC_CNTL_USB_TXM : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_TXM (BIT(13)) +#define RTC_CNTL_USB_TXM_M (BIT(13)) +#define RTC_CNTL_USB_TXM_V 0x1 +#define RTC_CNTL_USB_TXM_S 13 +/* RTC_CNTL_USB_PAD_ENABLE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PAD_ENABLE (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_M (BIT(12)) +#define RTC_CNTL_USB_PAD_ENABLE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_S 12 +/* RTC_CNTL_USB_PAD_ENABLE_OVERRIDE : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_M (BIT(11)) +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_ENABLE_OVERRIDE_S 11 +/* RTC_CNTL_USB_PULLUP_VALUE : R/W ;bitpos:[10] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PULLUP_VALUE (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_M (BIT(10)) +#define RTC_CNTL_USB_PULLUP_VALUE_V 0x1 +#define RTC_CNTL_USB_PULLUP_VALUE_S 10 +/* RTC_CNTL_USB_DM_PULLDOWN : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DM_PULLDOWN (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_M (BIT(9)) +#define RTC_CNTL_USB_DM_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DM_PULLDOWN_S 9 +/* RTC_CNTL_USB_DM_PULLUP : R/W ;bitpos:[8] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DM_PULLUP (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_M (BIT(8)) +#define RTC_CNTL_USB_DM_PULLUP_V 0x1 +#define RTC_CNTL_USB_DM_PULLUP_S 8 +/* RTC_CNTL_USB_DP_PULLDOWN : R/W ;bitpos:[7] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DP_PULLDOWN (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_M (BIT(7)) +#define RTC_CNTL_USB_DP_PULLDOWN_V 0x1 +#define RTC_CNTL_USB_DP_PULLDOWN_S 7 +/* RTC_CNTL_USB_DP_PULLUP : R/W ;bitpos:[6] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_DP_PULLUP (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_M (BIT(6)) +#define RTC_CNTL_USB_DP_PULLUP_V 0x1 +#define RTC_CNTL_USB_DP_PULLUP_S 6 +/* RTC_CNTL_USB_PAD_PULL_OVERRIDE : R/W ;bitpos:[5] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_M (BIT(5)) +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_PAD_PULL_OVERRIDE_S 5 +/* RTC_CNTL_USB_VREF_OVERRIDE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_VREF_OVERRIDE (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_M (BIT(4)) +#define RTC_CNTL_USB_VREF_OVERRIDE_V 0x1 +#define RTC_CNTL_USB_VREF_OVERRIDE_S 4 +/* RTC_CNTL_USB_VREFL : R/W ;bitpos:[3:2] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_VREFL 0x00000003 +#define RTC_CNTL_USB_VREFL_M ((RTC_CNTL_USB_VREFL_V) << (RTC_CNTL_USB_VREFL_S)) +#define RTC_CNTL_USB_VREFL_V 0x3 +#define RTC_CNTL_USB_VREFL_S 2 +/* RTC_CNTL_USB_VREFH : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: */ +#define RTC_CNTL_USB_VREFH 0x00000003 +#define RTC_CNTL_USB_VREFH_M ((RTC_CNTL_USB_VREFH_V) << (RTC_CNTL_USB_VREFH_S)) +#define RTC_CNTL_USB_VREFH_V 0x3 +#define RTC_CNTL_USB_VREFH_S 0 + +#define RTC_CNTL_TOUCH_TIMEOUT_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x0120) +/* RTC_CNTL_TOUCH_TIMEOUT_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_EN (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_M (BIT(22)) +#define RTC_CNTL_TOUCH_TIMEOUT_EN_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_EN_S 22 +/* RTC_CNTL_TOUCH_TIMEOUT_NUM : R/W ;bitpos:[21:0] ;default: 22'h3fffff ; */ +/*description: */ +#define RTC_CNTL_TOUCH_TIMEOUT_NUM 0x003FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_M ((RTC_CNTL_TOUCH_TIMEOUT_NUM_V) << (RTC_CNTL_TOUCH_TIMEOUT_NUM_S)) +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_V 0x3FFFFF +#define RTC_CNTL_TOUCH_TIMEOUT_NUM_S 0 + +#define RTC_CNTL_SLP_REJECT_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x0124) +/* RTC_CNTL_REJECT_CAUSE : RO ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: sleep reject cause*/ +#define RTC_CNTL_REJECT_CAUSE 0x0003FFFF +#define RTC_CNTL_REJECT_CAUSE_M ((RTC_CNTL_REJECT_CAUSE_V) << (RTC_CNTL_REJECT_CAUSE_S)) +#define RTC_CNTL_REJECT_CAUSE_V 0x3FFFF +#define RTC_CNTL_REJECT_CAUSE_S 0 + +#define RTC_CNTL_OPTION1_REG (DR_REG_RTCCNTL_BASE + 0x0128) +/* RTC_CNTL_FORCE_DOWNLOAD_BOOT : R/W ;bitpos:[0] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_M (BIT(0)) +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_V 0x1 +#define RTC_CNTL_FORCE_DOWNLOAD_BOOT_S 0 + +#define RTC_CNTL_SLP_WAKEUP_CAUSE_REG (DR_REG_RTCCNTL_BASE + 0x012C) +/* RTC_CNTL_WAKEUP_CAUSE : RO ;bitpos:[16:0] ;default: 17'd0 ; */ +/*description: sleep wakeup cause*/ +#define RTC_CNTL_WAKEUP_CAUSE 0x0001FFFF +#define RTC_CNTL_WAKEUP_CAUSE_M ((RTC_CNTL_WAKEUP_CAUSE_V) << (RTC_CNTL_WAKEUP_CAUSE_S)) +#define RTC_CNTL_WAKEUP_CAUSE_V 0x1FFFF +#define RTC_CNTL_WAKEUP_CAUSE_S 0 + +#define RTC_CNTL_ULP_CP_TIMER_1_REG (DR_REG_RTCCNTL_BASE + 0x0130) +/* RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE : R/W ;bitpos:[31:8] ;default: 24'd200 ; */ +/*description: sleep cycles for ULP-coprocessor timer*/ +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE 0x00FFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_M ((RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V) << (RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S)) +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_V 0xFFFFFF +#define RTC_CNTL_ULP_CP_TIMER_SLP_CYCLE_S 8 + +#define RTC_CNTL_INT_ENA_W1TS_REG (DR_REG_RTCCNTL_BASE + 0x0134) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TS : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TS_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TS_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable cocpu trap interrupt*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TS_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TS_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TS : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TS (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TS_S 15 +/* RTC_CNTL_SARADC2_INT_ENA_W1TS : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable saradc2 interrupt*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TS (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_W1TS_S 14 +/* RTC_CNTL_COCPU_INT_ENA_W1TS : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: enable riscV cocpu interrupt*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TS (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TS_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_W1TS_S 13 +/* RTC_CNTL_TSENS_INT_ENA_W1TS : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable tsens interrupt*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TS (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TS_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_W1TS_S 12 +/* RTC_CNTL_SARADC1_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: enable saradc1 interrupt*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TS (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_W1TS_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TS_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TS_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable touch inactive interrupt*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TS_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable touch active interrupt*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TS_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch done interrupt*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TS_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_W1TS_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 4 +/* RTC_CNTL_WDT_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TS (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TS_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TS_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TS_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TS_S 0 + +#define RTC_CNTL_INT_ENA_W1TC_REG (DR_REG_RTCCNTL_BASE + 0x0138) +/* RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(20)) +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 20 +/* RTC_CNTL_GLITCH_DET_INT_ENA_W1TC : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: enbale gitch det interrupt*/ +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_M (BIT(19)) +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_GLITCH_DET_INT_ENA_W1TC_S 19 +/* RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: enable touch timeout interrupt*/ +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(18)) +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_TIMEOUT_INT_ENA_W1TC_S 18 +/* RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: enable cocpu trap interrupt*/ +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_M (BIT(17)) +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_COCPU_TRAP_INT_ENA_W1TC_S 17 +/* RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: enable xtal32k_dead interrupt*/ +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_M (BIT(16)) +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_XTAL32K_DEAD_INT_ENA_W1TC_S 16 +/* RTC_CNTL_SWD_INT_ENA_W1TC : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: enable super watch dog interrupt*/ +#define RTC_CNTL_SWD_INT_ENA_W1TC (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_M (BIT(15)) +#define RTC_CNTL_SWD_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SWD_INT_ENA_W1TC_S 15 +/* RTC_CNTL_SARADC2_INT_ENA_W1TC : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: enable saradc2 interrupt*/ +#define RTC_CNTL_SARADC2_INT_ENA_W1TC (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_M (BIT(14)) +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SARADC2_INT_ENA_W1TC_S 14 +/* RTC_CNTL_COCPU_INT_ENA_W1TC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: enable riscV cocpu interrupt*/ +#define RTC_CNTL_COCPU_INT_ENA_W1TC (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TC_M (BIT(13)) +#define RTC_CNTL_COCPU_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_COCPU_INT_ENA_W1TC_S 13 +/* RTC_CNTL_TSENS_INT_ENA_W1TC : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: enable tsens interrupt*/ +#define RTC_CNTL_TSENS_INT_ENA_W1TC (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TC_M (BIT(12)) +#define RTC_CNTL_TSENS_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TSENS_INT_ENA_W1TC_S 12 +/* RTC_CNTL_SARADC1_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: enable saradc1 interrupt*/ +#define RTC_CNTL_SARADC1_INT_ENA_W1TC (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_M (BIT(11)) +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SARADC1_INT_ENA_W1TC_S 11 +/* RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: enable RTC main timer interrupt*/ +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_M (BIT(10)) +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_MAIN_TIMER_INT_ENA_W1TC_S 10 +/* RTC_CNTL_BROWN_OUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: enable brown out interrupt*/ +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_M (BIT(9)) +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_BROWN_OUT_INT_ENA_W1TC_S 9 +/* RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable touch inactive interrupt*/ +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(8)) +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_INACTIVE_INT_ENA_W1TC_S 8 +/* RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable touch active interrupt*/ +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(7)) +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_ACTIVE_INT_ENA_W1TC_S 7 +/* RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable touch done interrupt*/ +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_M (BIT(6)) +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_DONE_INT_ENA_W1TC_S 6 +/* RTC_CNTL_ULP_CP_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable ULP-coprocessor interrupt*/ +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_M (BIT(5)) +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_ULP_CP_INT_ENA_W1TC_S 5 +/* RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable touch scan done interrupt*/ +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(4)) +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 4 +/* RTC_CNTL_WDT_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable RTC WDT interrupt*/ +#define RTC_CNTL_WDT_INT_ENA_W1TC (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_M (BIT(3)) +#define RTC_CNTL_WDT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_WDT_INT_ENA_W1TC_S 3 +/* RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable SDIO idle interrupt*/ +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_M (BIT(2)) +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SDIO_IDLE_INT_ENA_W1TC_S 2 +/* RTC_CNTL_SLP_REJECT_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable sleep reject interrupt*/ +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_M (BIT(1)) +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_REJECT_INT_ENA_W1TC_S 1 +/* RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable sleep wakeup interrupt*/ +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_M (BIT(0)) +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_V 0x1 +#define RTC_CNTL_SLP_WAKEUP_INT_ENA_W1TC_S 0 + +#define RTC_CNTL_RETENTION_CTRL_REG (DR_REG_RTCCNTL_BASE + 0x013c) +/* RTC_CNTL_RETENTION_WAIT : R/W ;bitpos:[31:27] ;default: 5'd20 ; */ +/*description: wait cycles for rention operation*/ +#define RTC_CNTL_RETENTION_WAIT 0x0000001F +#define RTC_CNTL_RETENTION_WAIT_M ((RTC_CNTL_RETENTION_WAIT_V) << (RTC_CNTL_RETENTION_WAIT_S)) +#define RTC_CNTL_RETENTION_WAIT_V 0x1F +#define RTC_CNTL_RETENTION_WAIT_S 27 +/* RTC_CNTL_RETENTION_EN : R/W ;bitpos:[26] ;default: 1'd0 ; */ +/*description: */ +#define RTC_CNTL_RETENTION_EN (BIT(26)) +#define RTC_CNTL_RETENTION_EN_M (BIT(26)) +#define RTC_CNTL_RETENTION_EN_V 0x1 +#define RTC_CNTL_RETENTION_EN_S 26 + +#define RTC_CNTL_FIB_SEL_REG (DR_REG_RTCCNTL_BASE + 0x0140) +/* RTC_CNTL_FIB_SEL : R/W ;bitpos:[2:0] ;default: 3'd7 ; */ +/*description: select use analog fib signal*/ +#define RTC_CNTL_FIB_SEL 0x00000007 +#define RTC_CNTL_FIB_SEL_M ((RTC_CNTL_FIB_SEL_V) << (RTC_CNTL_FIB_SEL_S)) +#define RTC_CNTL_FIB_SEL_V 0x7 +#define RTC_CNTL_FIB_SEL_S 0 + +#define RTC_CNTL_DATE_REG (DR_REG_RTCCNTL_BASE + 0x0144) +/* RTC_CNTL_CNTL_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003251 ; */ +/*description: */ +#define RTC_CNTL_CNTL_DATE 0x0FFFFFFF +#define RTC_CNTL_CNTL_DATE_M ((RTC_CNTL_CNTL_DATE_V) << (RTC_CNTL_CNTL_DATE_S)) +#define RTC_CNTL_CNTL_DATE_V 0xFFFFFFF +#define RTC_CNTL_CNTL_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rtc_cntl_struct.h b/components/soc/soc/esp32s3/include/soc/rtc_cntl_struct.h new file mode 100644 index 000000000..4f81dc22f --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_cntl_struct.h @@ -0,0 +1,967 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/ + uint32_t sw_stall_procpu_c0: 2; /*{reg_sw_stall_procpu_c1[5:0] reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU*/ + uint32_t sw_appcpu_rst: 1; /*APP CPU SW reset*/ + uint32_t sw_procpu_rst: 1; /*PRO CPU SW reset*/ + uint32_t bb_i2c_force_pd: 1; /*BB_I2C force power down*/ + uint32_t bb_i2c_force_pu: 1; /*BB_I2C force power up*/ + uint32_t bbpll_i2c_force_pd: 1; /*BB_PLL _I2C force power down*/ + uint32_t bbpll_i2c_force_pu: 1; /*BB_PLL_I2C force power up*/ + uint32_t bbpll_force_pd: 1; /*BB_PLL force power down*/ + uint32_t bbpll_force_pu: 1; /*BB_PLL force power up*/ + uint32_t xtl_force_pd: 1; /*crystall force power down*/ + uint32_t xtl_force_pu: 1; /*crystall force power up*/ + uint32_t xtl_en_wait: 4; /*wait bias_sleep and current source wakeup*/ + uint32_t reserved18: 5; + uint32_t xtl_force_iso: 1; + uint32_t pll_force_iso: 1; + uint32_t analog_force_iso: 1; + uint32_t xtl_force_noiso: 1; + uint32_t pll_force_noiso: 1; + uint32_t analog_force_noiso: 1; + uint32_t dg_wrap_force_rst: 1; /*digital wrap force reset in deep sleep*/ + uint32_t dg_wrap_force_norst: 1; /*digital core force no reset in deep sleep*/ + uint32_t sw_sys_rst: 1; /*SW system reset*/ + }; + uint32_t val; + } options0; + uint32_t slp_timer0; /**/ + union { + struct { + uint32_t slp_val_hi: 16; /*RTC sleep timer high 16 bits*/ + uint32_t main_timer_alarm_en: 1; /*timer alarm enable bit*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_timer1; + union { + struct { + uint32_t reserved0: 27; + uint32_t timer_sys_stall: 1; /*Enable to record system stall time*/ + uint32_t timer_xtl_off: 1; /*Enable to record 40M XTAL OFF time*/ + uint32_t timer_sys_rst: 1; /*enable to record system reset time*/ + uint32_t reserved30: 1; + uint32_t update: 1; /*Set 1: to update register with RTC timer*/ + }; + uint32_t val; + } time_update; + uint32_t time_low0; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t rtc_timer_value0_high: 16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time_high0; + union { + struct { + uint32_t rtc_sw_cpu_int: 1; /*rtc software interrupt to main cpu*/ + uint32_t rtc_slp_reject_cause_clr: 1; /*clear rtc sleep reject cause*/ + uint32_t reserved2: 20; + uint32_t apb2rtc_bridge_sel: 1; /*1: APB to RTC using bridge*/ + uint32_t reserved23: 5; + uint32_t sdio_active_ind: 1; /*SDIO active indication*/ + uint32_t slp_wakeup: 1; /*leep wakeup bit*/ + uint32_t slp_reject: 1; /*leep reject bit*/ + uint32_t sleep_en: 1; /*sleep enable bit*/ + }; + uint32_t val; + } state0; + union { + struct { + uint32_t cpu_stall_en: 1; /*CPU stall enable bit*/ + uint32_t cpu_stall_wait: 5; /*CPU stall wait cycles in fast_clk_rtc*/ + uint32_t ck8m_wait: 8; /*CK8M wait cycles in slow_clk_rtc*/ + uint32_t xtl_buf_wait: 10; /*XTAL wait cycles in slow_clk_rtc*/ + uint32_t pll_buf_wait: 8; /*PLL wait cycles in slow_clk_rtc*/ + }; + uint32_t val; + } timer1; + union { + struct { + uint32_t reserved0: 15; + uint32_t ulpcp_touch_start_wait: 9; /*wait cycles in slow_clk_rtc before ULP-coprocessor / touch controller start to work*/ + uint32_t min_time_ck8m_off: 8; /*minimal cycles in slow_clk_rtc for CK8M in power down state*/ + }; + uint32_t val; + } timer2; + union { + struct { + uint32_t wifi_wait_timer: 9; + uint32_t wifi_powerup_timer: 7; + uint32_t rom_ram_wait_timer: 9; + uint32_t rom_ram_powerup_timer: 7; + }; + uint32_t val; + } timer3; + union { + struct { + uint32_t rtc_wait_timer: 9; + uint32_t rtc_powerup_timer: 7; + uint32_t dg_wrap_wait_timer: 9; + uint32_t dg_wrap_powerup_timer: 7; + }; + uint32_t val; + } timer4; + union { + struct { + uint32_t reserved0: 8; + uint32_t min_slp_val: 8; /*minimal sleep cycles in slow_clk_rtc*/ + uint32_t rtcmem_wait_timer: 9; + uint32_t rtcmem_powerup_timer: 7; + }; + uint32_t val; + } timer5; + union { + struct { + uint32_t reserved0: 16; + uint32_t dg_dcdc_wait_timer: 9; + uint32_t dg_dcdc_powerup_timer: 7; + }; + uint32_t val; + } timer6; + union { + struct { + uint32_t reserved0: 18; + uint32_t i2c_reset_por_force_pd: 1; + uint32_t i2c_reset_por_force_pu: 1; + uint32_t glitch_rst_en: 1; + uint32_t reserved21: 1; /*PLLA force power down*/ + uint32_t sar_i2c_pu: 1; /*PLLA force power up*/ + uint32_t plla_force_pd: 1; /*PLLA force power down*/ + uint32_t plla_force_pu: 1; /*PLLA force power up*/ + uint32_t bbpll_cal_slp_start: 1; /*start BBPLL calibration during sleep*/ + uint32_t pvtmon_pu: 1; /*1: PVTMON power up*/ + uint32_t txrf_i2c_pu: 1; /*1: TXRF_I2C power up*/ + uint32_t rfrx_pbus_pu: 1; /*1: RFRX_PBUS power up*/ + uint32_t reserved29: 1; + uint32_t ckgen_i2c_pu: 1; /*1: CKGEN_I2C power up*/ + uint32_t pll_i2c_pu: 1; + }; + uint32_t val; + } ana_conf; + union { + struct { + uint32_t reset_cause_procpu: 6; /*reset cause of PRO CPU*/ + uint32_t reset_cause_appcpu: 6; /*reset cause of APP CPU*/ + uint32_t appcpu_stat_vector_sel: 1; /*APP CPU state vector sel*/ + uint32_t procpu_stat_vector_sel: 1; /*PRO CPU state vector sel*/ + uint32_t reset_flag_procpu: 1; /*PRO CPU reset_flag*/ + uint32_t reset_flag_appcpu: 1; /*APP CPU reset flag*/ + uint32_t reset_flag_procpu_clr: 1; /*clear PRO CPU reset_flag*/ + uint32_t reset_flag_appcpu_clr: 1; /*clear APP CPU reset flag*/ + uint32_t appcpu_ocd_halt_on_reset: 1; /*APPCPU OcdHaltOnReset*/ + uint32_t procpu_ocd_halt_on_reset: 1; /*PROCPU OcdHaltOnReset*/ + uint32_t reset_flag_jtag_procpu: 1; + uint32_t reset_flag_jtag_appcpu: 1; + uint32_t reset_flag_jtag_procpu_clr: 1; + uint32_t reset_flag_jtag_appcpu_clr: 1; + uint32_t rtc_app_dreset_mask: 1; + uint32_t rtc_pro_dreset_mask: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } reset_state; + union { + struct { + uint32_t reserved0: 15; + uint32_t rtc_wakeup_ena: 17; /*wakeup enable bitmap*/ + }; + uint32_t val; + } wakeup_state; + union { + struct { + uint32_t slp_wakeup: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done: 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done: 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active: 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive: 1; /*enable touch inactive interrupt*/ + uint32_t rtc_brown_out: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer: 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1: 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens: 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu: 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2: 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead: 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap: 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout: 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt raw*/ + uint32_t slp_reject: 1; /*sleep reject interrupt raw*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt raw*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt raw*/ + uint32_t rtc_touch_scan_done: 1; + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt raw*/ + uint32_t rtc_touch_done: 1; /*touch interrupt raw*/ + uint32_t rtc_touch_active: 1; /*touch active interrupt raw*/ + uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt raw*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt raw*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt raw*/ + uint32_t rtc_saradc1: 1; /*saradc1 interrupt raw*/ + uint32_t rtc_tsens: 1; /*tsens interrupt raw*/ + uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt raw*/ + uint32_t rtc_saradc2: 1; /*saradc2 interrupt raw*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt raw*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt raw*/ + uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt raw*/ + uint32_t rtc_touch_timeout: 1; /*touch timeout interrupt raw*/ + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt_raw*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slp_wakeup: 1; /*sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*RTC WDT interrupt state*/ + uint32_t rtc_touch_scan_done: 1; + uint32_t rtc_ulp_cp: 1; /*ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done: 1; /*touch done interrupt state*/ + uint32_t rtc_touch_active: 1; /*touch active interrupt state*/ + uint32_t rtc_touch_inactive: 1; /*touch inactive interrupt state*/ + uint32_t rtc_brown_out: 1; /*brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*RTC main timer interrupt state*/ + uint32_t rtc_saradc1: 1; /*saradc1 interrupt state*/ + uint32_t rtc_tsens: 1; /*tsens interrupt state*/ + uint32_t rtc_cocpu: 1; /*riscV cocpu interrupt state*/ + uint32_t rtc_saradc2: 1; /*saradc2 interrupt state*/ + uint32_t rtc_swd: 1; /*super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*xtal32k dead detection interrupt state*/ + uint32_t rtc_cocpu_trap: 1; /*cocpu trap interrupt state*/ + uint32_t rtc_touch_timeout: 1; /*Touch timeout interrupt state*/ + uint32_t rtc_glitch_det: 1; /*glitch_det_interrupt state*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slp_wakeup: 1; /*Clear sleep wakeup interrupt state*/ + uint32_t slp_reject: 1; /*Clear sleep reject interrupt state*/ + uint32_t sdio_idle: 1; /*Clear SDIO idle interrupt state*/ + uint32_t rtc_wdt: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_touch_scan_done: 1; + uint32_t rtc_ulp_cp: 1; /*Clear ULP-coprocessor interrupt state*/ + uint32_t rtc_touch_done: 1; /*Clear touch done interrupt state*/ + uint32_t rtc_touch_active: 1; /*Clear touch active interrupt state*/ + uint32_t rtc_touch_inactive: 1; /*Clear touch inactive interrupt state*/ + uint32_t rtc_brown_out: 1; /*Clear brown out interrupt state*/ + uint32_t rtc_main_timer: 1; /*Clear RTC main timer interrupt state*/ + uint32_t rtc_saradc1: 1; /*Clear saradc1 interrupt state*/ + uint32_t rtc_tsens: 1; /*Clear tsens interrupt state*/ + uint32_t rtc_cocpu: 1; /*Clear riscV cocpu interrupt state*/ + uint32_t rtc_saradc2: 1; /*Clear saradc2 interrupt state*/ + uint32_t rtc_swd: 1; /*Clear super watch dog interrupt state*/ + uint32_t rtc_xtal32k_dead: 1; /*Clear RTC WDT interrupt state*/ + uint32_t rtc_cocpu_trap: 1; /*Clear cocpu trap interrupt state*/ + uint32_t rtc_touch_timeout: 1; /*Clear touch timeout interrupt state*/ + uint32_t rtc_glitch_det: 1; /*Clear glitch det interrupt state*/ + uint32_t rtc_touch_approach_loop_done: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_clr; + uint32_t store[4]; /**/ + union { + struct { + uint32_t xtal32k_wdt_en: 1; /*xtal 32k watch dog enable*/ + uint32_t xtal32k_wdt_clk_fo: 1; /*xtal 32k watch dog clock force on*/ + uint32_t xtal32k_wdt_reset: 1; /*xtal 32k watch dog sw reset*/ + uint32_t xtal32k_ext_clk_fo: 1; /*xtal 32k external xtal clock force on*/ + uint32_t xtal32k_auto_backup: 1; /*xtal 32k switch to back up clock when xtal is dead*/ + uint32_t xtal32k_auto_restart: 1; /*xtal 32k restart xtal when xtal is dead*/ + uint32_t xtal32k_auto_return: 1; /*xtal 32k switch back xtal when xtal is restarted*/ + uint32_t xtal32k_xpd_force: 1; /*Xtal 32k xpd control by sw or fsm*/ + uint32_t enckinit_xtal_32k: 1; /*apply an internal clock to help xtal 32k to start*/ + uint32_t dbuf_xtal_32k: 1; /*0: single-end buffer 1: differential buffer*/ + uint32_t dgm_xtal_32k: 3; /*xtal_32k gm control*/ + uint32_t dres_xtal_32k: 3; /*DRES_XTAL_32K*/ + uint32_t xpd_xtal_32k: 1; /*XPD_XTAL_32K*/ + uint32_t dac_xtal_32k: 3; /*DAC_XTAL_32K*/ + uint32_t rtc_wdt_state: 3; /*state of 32k_wdt*/ + uint32_t rtc_xtal32k_gpio_sel: 1; /*XTAL_32K sel. 0: external XTAL_32K*/ + uint32_t reserved24: 6; + uint32_t ctr_lv: 1; /*0: power down XTAL at high level*/ + uint32_t ctr_en: 1; + }; + uint32_t val; + } ext_xtl_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t gpio_wakeup_filter: 1; /*enable filter for gpio wakeup event*/ + uint32_t wakeup0_lv: 1; /*0: external wakeup at low level*/ + uint32_t wakeup1_lv: 1; + }; + uint32_t val; + } ext_wakeup_conf; + union { + struct { + uint32_t reserved0: 12; + uint32_t rtc_sleep_reject_ena: 18; /*sleep reject enable*/ + uint32_t light_slp_reject_en: 1; /*enable reject for light sleep*/ + uint32_t deep_slp_reject_en: 1; /*enable reject for deep sleep*/ + }; + uint32_t val; + } slp_reject_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t cpusel_conf: 1; /*CPU sel option*/ + uint32_t cpuperiod_sel: 2; + }; + uint32_t val; + } cpu_period_conf; + union { + struct { + uint32_t reserved0: 22; + uint32_t sdio_act_dnum: 10; + }; + uint32_t val; + } sdio_act_conf; + union { + struct { + uint32_t reserved0: 3; + uint32_t ck8m_div_sel_vld: 1; /*used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel*/ + uint32_t ck8m_div: 2; /*CK8M_D256_OUT divider. 00: div128*/ + uint32_t enb_ck8m: 1; /*disable CK8M and CK8M_D256_OUT*/ + uint32_t enb_ck8m_div: 1; /*1: CK8M_D256_OUT is actually CK8M*/ + uint32_t dig_xtal32k_en: 1; /*enable CK_XTAL_32K for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_d256_en: 1; /*enable CK8M_D256_OUT for digital core (no relationship with RTC core)*/ + uint32_t dig_clk8m_en: 1; /*enable CK8M for digital core (no relationship with RTC core)*/ + uint32_t reserved11: 1; + uint32_t ck8m_div_sel: 3; /*divider = reg_ck8m_div_sel + 1*/ + uint32_t xtal_force_nogating: 1; /*XTAL force no gating during sleep*/ + uint32_t ck8m_force_nogating: 1; /*CK8M force no gating during sleep*/ + uint32_t ck8m_dfreq: 8; /*CK8M_DFREQ*/ + uint32_t ck8m_force_pd: 1; /*CK8M force power down*/ + uint32_t ck8m_force_pu: 1; /*CK8M force power up*/ + uint32_t reserved27: 2; + uint32_t fast_clk_rtc_sel: 1; /*fast_clk_rtc sel. 0: XTAL div 4*/ + uint32_t ana_clk_rtc_sel: 2; + }; + uint32_t val; + } clk_conf; + union { + struct { + uint32_t reserved0: 22; + uint32_t rtc_ana_clk_div_vld: 1; /*used to sync div bus. clear vld before set reg_rtc_ana_clk_div*/ + uint32_t rtc_ana_clk_div: 8; + uint32_t slow_clk_next_edge: 1; + }; + uint32_t val; + } slow_clk_conf; + union { + struct { + uint32_t sdio_timer_target: 8; /*timer count to apply reg_sdio_dcap after sdio power on*/ + uint32_t reserved8: 1; + uint32_t sdio_dthdrv: 2; /*Tieh = 1 mode drive ability. Initially set to 0 to limit charge current*/ + uint32_t sdio_dcap: 2; /*ability to prevent LDO from overshoot*/ + uint32_t sdio_initi: 2; /*add resistor from ldo output to ground. 0: no res*/ + uint32_t sdio_en_initi: 1; /*0 to set init[1:0]=0*/ + uint32_t sdio_dcurlim: 3; /*tune current limit threshold when tieh = 0. About 800mA/(8+d)*/ + uint32_t sdio_modecurlim: 1; /*select current limit mode*/ + uint32_t sdio_encurlim: 1; /*enable current limit*/ + uint32_t sdio_pd_en: 1; /*power down SDIO_REG in sleep. Only active when reg_sdio_force = 0*/ + uint32_t sdio_force: 1; /*1: use SW option to control SDIO_REG*/ + uint32_t sdio_tieh: 1; /*SW option for SDIO_TIEH. Only active when reg_sdio_force = 1*/ + uint32_t reg1p8_ready: 1; /*read only register for REG1P8_READY*/ + uint32_t drefl_sdio: 2; /*SW option for DREFL_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefm_sdio: 2; /*SW option for DREFM_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t drefh_sdio: 2; /*SW option for DREFH_SDIO. Only active when reg_sdio_force = 1*/ + uint32_t xpd_sdio: 1; + }; + uint32_t val; + } sdio_conf; + union { + struct { + uint32_t reserved0: 10; + uint32_t bias_buf_idle: 1; + uint32_t bias_buf_wake: 1; + uint32_t bias_buf_deep_slp: 1; + uint32_t bias_buf_monitor: 1; + uint32_t pd_cur_deep_slp: 1; /*xpd cur when rtc in sleep_state*/ + uint32_t pd_cur_monitor: 1; /*xpd cur when rtc in monitor state*/ + uint32_t bias_sleep_deep_slp: 1; /*bias_sleep when rtc in sleep_state*/ + uint32_t bias_sleep_monitor: 1; /*bias_sleep when rtc in monitor state*/ + uint32_t dbg_atten_deep_slp: 4; /*DBG_ATTEN when rtc in sleep state*/ + uint32_t dbg_atten_monitor: 4; /*DBG_ATTEN when rtc in monitor state*/ + uint32_t reserved26: 6; + }; + uint32_t val; + } bias_conf; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_cal_en: 1; + uint32_t reserved8: 6; + uint32_t sck_dcap: 8; /*SCK_DCAP*/ + uint32_t reserved22: 6; + uint32_t rtc_dboost_force_pd: 1; /*RTC_DBOOST force power down*/ + uint32_t rtc_dboost_force_pu: 1; /*RTC_DBOOST force power up*/ + uint32_t rtculator_force_pd: 1; /*RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )*/ + uint32_t rtculator_force_pu: 1; + }; + uint32_t val; + } rtc; + union { + struct { + uint32_t fastmem_force_noiso: 1; /*Fast RTC memory force no ISO*/ + uint32_t fastmem_force_iso: 1; /*Fast RTC memory force ISO*/ + uint32_t slowmem_force_noiso: 1; /*RTC memory force no ISO*/ + uint32_t slowmem_force_iso: 1; /*RTC memory force ISO*/ + uint32_t rtc_force_iso: 1; /*rtc_peri force ISO*/ + uint32_t rtc_force_noiso: 1; /*rtc_peri force no ISO*/ + uint32_t fastmem_folw_cpu: 1; /*1: Fast RTC memory PD following CPU*/ + uint32_t fastmem_force_lpd: 1; /*Fast RTC memory force PD*/ + uint32_t fastmem_force_lpu: 1; /*Fast RTC memory force no PD*/ + uint32_t slowmem_folw_cpu: 1; /*1: RTC memory PD following CPU*/ + uint32_t slowmem_force_lpd: 1; /*RTC memory force PD*/ + uint32_t slowmem_force_lpu: 1; /*RTC memory force no PD*/ + uint32_t fastmem_force_pd: 1; /*Fast RTC memory force power down*/ + uint32_t fastmem_force_pu: 1; /*Fast RTC memory force power up*/ + uint32_t fastmem_pd_en: 1; /*enable power down fast RTC memory in sleep*/ + uint32_t slowmem_force_pd: 1; /*RTC memory force power down*/ + uint32_t slowmem_force_pu: 1; /*RTC memory force power up*/ + uint32_t slowmem_pd_en: 1; /*enable power down RTC memory in sleep*/ + uint32_t rtc_force_pd: 1; /*rtc_peri force power down*/ + uint32_t rtc_force_pu: 1; /*rtc_peri force power up*/ + uint32_t rtc_pd_en: 1; /*enable power down rtc_peri in sleep*/ + uint32_t rtc_pad_force_hold: 1; /*rtc pad force hold*/ + uint32_t reserved22: 10; + }; + uint32_t val; + } rtc_pwc; + union { + struct { + uint32_t reserved0: 3; + uint32_t lslp_mem_force_pd: 1; /*memories in digital core force PD in sleep*/ + uint32_t lslp_mem_force_pu: 1; /*memories in digital core force no PD in sleep*/ + uint32_t rom0_force_pd: 1; /*ROM force power down*/ + uint32_t rom0_force_pu: 1; /*ROM force power up*/ + uint32_t inter_ram0_force_pd: 1; /*internal SRAM 0 force power down*/ + uint32_t inter_ram0_force_pu: 1; /*internal SRAM 0 force power up*/ + uint32_t inter_ram1_force_pd: 1; /*internal SRAM 1 force power down*/ + uint32_t inter_ram1_force_pu: 1; /*internal SRAM 1 force power up*/ + uint32_t inter_ram2_force_pd: 1; /*internal SRAM 2 force power down*/ + uint32_t inter_ram2_force_pu: 1; /*internal SRAM 2 force power up*/ + uint32_t inter_ram3_force_pd: 1; /*internal SRAM 3 force power down*/ + uint32_t inter_ram3_force_pu: 1; /*internal SRAM 3 force power up*/ + uint32_t inter_ram4_force_pd: 1; /*internal SRAM 4 force power down*/ + uint32_t inter_ram4_force_pu: 1; /*internal SRAM 4 force power up*/ + uint32_t wifi_force_pd: 1; /*wifi force power down*/ + uint32_t wifi_force_pu: 1; /*wifi force power up*/ + uint32_t dg_wrap_force_pd: 1; /*digital core force power down*/ + uint32_t dg_wrap_force_pu: 1; /*digital core force power up*/ + uint32_t dg_dcdc_force_pd: 1; /*digital dcdc force power down*/ + uint32_t dg_dcdc_force_pu: 1; /*digital dcdc force power up*/ + uint32_t dg_dcdc_pd_en: 1; /*enable power down digital dcdc in sleep*/ + uint32_t rom0_pd_en: 1; /*enable power down ROM in sleep*/ + uint32_t inter_ram0_pd_en: 1; /*enable power down internal SRAM 0 in sleep*/ + uint32_t inter_ram1_pd_en: 1; /*enable power down internal SRAM 1 in sleep*/ + uint32_t inter_ram2_pd_en: 1; /*enable power down internal SRAM 2 in sleep*/ + uint32_t inter_ram3_pd_en: 1; /*enable power down internal SRAM 3 in sleep*/ + uint32_t inter_ram4_pd_en: 1; /*enable power down internal SRAM 4 in sleep*/ + uint32_t wifi_pd_en: 1; /*enable power down wifi in sleep*/ + uint32_t dg_wrap_pd_en: 1; + }; + uint32_t val; + } dig_pwc; + union { + struct { + uint32_t reserved0: 7; + uint32_t dig_iso_force_off: 1; + uint32_t dig_iso_force_on: 1; + uint32_t dg_pad_autohold: 1; /*read only register to indicate digital pad auto-hold status*/ + uint32_t clr_dg_pad_autohold: 1; /*wtite only register to clear digital pad auto-hold*/ + uint32_t dg_pad_autohold_en: 1; /*digital pad enable auto-hold*/ + uint32_t dg_pad_force_noiso: 1; /*digital pad force no ISO*/ + uint32_t dg_pad_force_iso: 1; /*digital pad force ISO*/ + uint32_t dg_pad_force_unhold: 1; /*digital pad force un-hold*/ + uint32_t dg_pad_force_hold: 1; /*digital pad force hold*/ + uint32_t rom0_force_iso: 1; /*ROM force ISO*/ + uint32_t rom0_force_noiso: 1; /*ROM force no ISO*/ + uint32_t inter_ram0_force_iso: 1; /*internal SRAM 0 force ISO*/ + uint32_t inter_ram0_force_noiso: 1; /*internal SRAM 0 force no ISO*/ + uint32_t inter_ram1_force_iso: 1; /*internal SRAM 1 force ISO*/ + uint32_t inter_ram1_force_noiso: 1; /*internal SRAM 1 force no ISO*/ + uint32_t inter_ram2_force_iso: 1; /*internal SRAM 2 force ISO*/ + uint32_t inter_ram2_force_noiso: 1; /*internal SRAM 2 force no ISO*/ + uint32_t inter_ram3_force_iso: 1; /*internal SRAM 3 force ISO*/ + uint32_t inter_ram3_force_noiso: 1; /*internal SRAM 3 force no ISO*/ + uint32_t inter_ram4_force_iso: 1; /*internal SRAM 4 force ISO*/ + uint32_t inter_ram4_force_noiso: 1; /*internal SRAM 4 force no ISO*/ + uint32_t wifi_force_iso: 1; /*wifi force ISO*/ + uint32_t wifi_force_noiso: 1; /*wifi force no ISO*/ + uint32_t dg_wrap_force_iso: 1; /*digital core force ISO*/ + uint32_t dg_wrap_force_noiso: 1; + }; + uint32_t val; + } dig_iso; + union { + struct { + uint32_t chip_reset_width: 8; /*chip reset siginal pulse width*/ + uint32_t chip_reset_en: 1; /*wdt reset whole chip enable*/ + uint32_t pause_in_slp: 1; /*pause WDT in sleep*/ + uint32_t appcpu_reset_en: 1; /*enable WDT reset APP CPU*/ + uint32_t procpu_reset_en: 1; /*enable WDT reset PRO CPU*/ + uint32_t flashboot_mod_en: 1; /*enable WDT in flash boot*/ + uint32_t sys_reset_length: 3; /*system reset counter length*/ + uint32_t cpu_reset_length: 3; /*CPU reset counter length*/ + uint32_t stg3: 3; /*1: interrupt stage en*/ + uint32_t stg2: 3; /*1: interrupt stage en*/ + uint32_t stg1: 3; /*1: interrupt stage en*/ + uint32_t stg0: 3; /*1: interrupt stage en*/ + uint32_t en: 1; + }; + uint32_t val; + } wdt_config0; + uint32_t wdt_config1; /**/ + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + union { + struct { + uint32_t reserved0: 31; + uint32_t feed: 1; + }; + uint32_t val; + } wdt_feed; + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t swd_reset_flag: 1; /*swd reset flag*/ + uint32_t swd_feed_int: 1; /*swd interrupt for feeding*/ + uint32_t reserved2: 15; + uint32_t swd_bypass_rst: 1; + uint32_t swd_signal_width: 10; /*adjust signal width send to swd*/ + uint32_t swd_rst_flag_clr: 1; /*reset swd reset flag*/ + uint32_t swd_feed: 1; /*Sw feed swd*/ + uint32_t swd_disable: 1; /*disabel SWD*/ + uint32_t swd_auto_feed_en: 1; /*automatically feed swd when int comes*/ + }; + uint32_t val; + } swd_conf; + uint32_t swd_wprotect; /**/ + union { + struct { + uint32_t reserved0: 20; + uint32_t appcpu_c1: 6; /*{reg_sw_stall_appcpu_c1[5:0]*/ + uint32_t procpu_c1: 6; + }; + uint32_t val; + } sw_cpu_stall; + uint32_t store4; /**/ + uint32_t store5; /**/ + uint32_t store6; /**/ + uint32_t store7; /**/ + union { + struct { + uint32_t xpd_rom0: 1; /*rom0 power down*/ + uint32_t reserved1: 1; + uint32_t xpd_dig_dcdc: 1; /*External DCDC power down*/ + uint32_t rtc_peri_iso: 1; /*rtc peripheral iso*/ + uint32_t xpd_rtc_peri: 1; /*rtc peripheral power down*/ + uint32_t wifi_iso: 1; /*wifi iso*/ + uint32_t xpd_wifi: 1; /*wifi wrap power down*/ + uint32_t dig_iso: 1; /*digital wrap iso*/ + uint32_t xpd_dig: 1; /*digital wrap power down*/ + uint32_t rtc_touch_state_start: 1; /*touch should start to work*/ + uint32_t rtc_touch_state_switch: 1; /*touch is about to working. Switch rtc main state*/ + uint32_t rtc_touch_state_slp: 1; /*touch is in sleep state*/ + uint32_t rtc_touch_state_done: 1; /*touch is done*/ + uint32_t rtc_cocpu_state_start: 1; /*ulp/cocpu should start to work*/ + uint32_t rtc_cocpu_state_switch: 1; /*ulp/cocpu is about to working. Switch rtc main state*/ + uint32_t rtc_cocpu_state_slp: 1; /*ulp/cocpu is in sleep state*/ + uint32_t rtc_cocpu_state_done: 1; /*ulp/cocpu is done*/ + uint32_t rtc_main_state_xtal_iso: 1; /*no use any more*/ + uint32_t rtc_main_state_pll_on: 1; /*rtc main state machine is in states that pll should be running*/ + uint32_t rtc_rdy_for_wakeup: 1; /*rtc is ready to receive wake up trigger from wake up source*/ + uint32_t rtc_main_state_wait_end: 1; /*rtc main state machine has been waited for some cycles*/ + uint32_t rtc_in_wakeup_state: 1; /*rtc main state machine is in the states of wakeup process*/ + uint32_t rtc_in_low_power_state: 1; /*rtc main state machine is in the states of low power*/ + uint32_t rtc_main_state_in_wait_8m: 1; /*rtc main state machine is in wait 8m state*/ + uint32_t rtc_main_state_in_wait_pll: 1; /*rtc main state machine is in wait pll state*/ + uint32_t rtc_main_state_in_wait_xtl: 1; /*rtc main state machine is in wait xtal state*/ + uint32_t rtc_main_state_in_slp: 1; /*rtc main state machine is in sleep state*/ + uint32_t rtc_main_state_in_idle: 1; /*rtc main state machine is in idle state*/ + uint32_t rtc_main_state: 4; /*rtc main state machine status*/ + }; + uint32_t val; + } low_power_st; + uint32_t diag0; /**/ + union { + struct { + uint32_t touch_pad0_hold: 1; + uint32_t touch_pad1_hold: 1; + uint32_t touch_pad2_hold: 1; + uint32_t touch_pad3_hold: 1; + uint32_t touch_pad4_hold: 1; + uint32_t touch_pad5_hold: 1; + uint32_t touch_pad6_hold: 1; + uint32_t touch_pad7_hold: 1; + uint32_t touch_pad8_hold: 1; + uint32_t touch_pad9_hold: 1; + uint32_t touch_pad10_hold: 1; + uint32_t touch_pad11_hold: 1; + uint32_t touch_pad12_hold: 1; + uint32_t touch_pad13_hold: 1; + uint32_t touch_pad14_hold: 1; + uint32_t x32p_hold: 1; + uint32_t x32n_hold: 1; + uint32_t pdac1_hold: 1; + uint32_t pdac2_hold: 1; + uint32_t rtc_pad19_hold: 1; + uint32_t rtc_pad20_hold: 1; + uint32_t rtc_pad21_hold: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } pad_hold; + uint32_t dig_pad_hold; /**/ + union { + struct { + uint32_t sel: 22; /*Bitmap to select RTC pads for ext wakeup1*/ + uint32_t status_clr: 1; /*clear ext wakeup1 status*/ + uint32_t reserved23: 9; + }; + uint32_t val; + } ext_wakeup1; + union { + struct { + uint32_t status: 22; /*ext wakeup1 status*/ + uint32_t reserved22: 10; + }; + uint32_t val; + } ext_wakeup1_status; + union { + struct { + uint32_t reserved0: 4; + uint32_t int_wait: 10; /*brown out interrupt wait cycles*/ + uint32_t close_flash_ena: 1; /*enable close flash when brown out happens*/ + uint32_t pd_rf_ena: 1; /*enable power down RF when brown out happens*/ + uint32_t rst_wait: 10; /*brown out reset wait cycles*/ + uint32_t rst_ena: 1; /*enable brown out reset*/ + uint32_t rst_sel: 1; /*1: 4-pos reset*/ + uint32_t ana_rst_en: 1; + uint32_t cnt_clr: 1; /*clear brown out counter*/ + uint32_t ena: 1; /*enable brown out*/ + uint32_t det: 1; + }; + uint32_t val; + } brown_out; + uint32_t time_low1; /*RTC timer low 32 bits*/ + union { + struct { + uint32_t rtc_timer_value1_high: 16; /*RTC timer high 16 bits*/ + uint32_t reserved16: 16; + }; + uint32_t val; + } time_high1; + uint32_t xtal32k_clk_factor; /*xtal 32k watch dog backup clock factor*/ + union { + struct { + uint32_t xtal32k_return_wait: 4; /*cycles to wait to return noral xtal 32k*/ + uint32_t xtal32k_restart_wait: 16; /*cycles to wait to repower on xtal 32k*/ + uint32_t xtal32k_wdt_timeout: 8; /*If no clock detected for this amount of time*/ + uint32_t xtal32k_stable_thres: 4; /*if restarted xtal32k period is smaller than this*/ + }; + uint32_t val; + } xtal32k_conf; + union { + struct { + uint32_t ulp_cp_pc_init: 11; /*ULP-coprocessor PC initial address*/ + uint32_t reserved11: 18; + uint32_t ulp_cp_gpio_wakeup_ena: 1; /*ULP-coprocessor wakeup by GPIO enable*/ + uint32_t ulp_cp_gpio_wakeup_clr: 1; /*ULP-coprocessor wakeup by GPIO state clear*/ + uint32_t ulp_cp_slp_timer_en: 1; /*ULP-coprocessor timer enable bit*/ + }; + uint32_t val; + } ulp_cp_timer; + union { + struct { + uint32_t ulp_cp_mem_addr_init: 11; + uint32_t ulp_cp_mem_addr_size: 11; + uint32_t ulp_cp_mem_offst_clr: 1; + uint32_t reserved23: 5; + uint32_t ulp_cp_clk_fo: 1; /*ulp coprocessor clk force on*/ + uint32_t ulp_cp_reset: 1; /*ulp coprocessor clk software reset*/ + uint32_t ulp_cp_force_start_top: 1; /*1: ULP-coprocessor is started by SW*/ + uint32_t ulp_cp_start_top: 1; /*Write 1 to start ULP-coprocessor*/ + }; + uint32_t val; + } ulp_cp_ctrl; + union { + struct { + uint32_t cocpu_clk_fo: 1; /*cocpu clk force on*/ + uint32_t cocpu_start_2_reset_dis: 6; /*time from start cocpu to pull down reset*/ + uint32_t cocpu_start_2_intr_en: 6; /*time from start cocpu to give start interrupt*/ + uint32_t cocpu_shut: 1; /*to shut cocpu*/ + uint32_t cocpu_shut_2_clk_dis: 8; /*time from shut cocpu to disable clk*/ + uint32_t cocpu_shut_reset_en: 1; /*to reset cocpu*/ + uint32_t cocpu_sel: 1; /*1: old ULP 0: new riscV*/ + uint32_t cocpu_done_force: 1; /*1: select riscv done 0: select ulp done*/ + uint32_t cocpu_done: 1; /*done signal used by riscv to control timer.*/ + uint32_t cocpu_sw_int_trigger: 1; /*trigger cocpu register interrupt*/ + uint32_t cocpu_clkgate_en: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } cocpu_ctrl; + union { + struct { + uint32_t touch_sleep_cycles: 16; /*sleep cycles for timer*/ + uint32_t touch_meas_num: 16; /*the meas length (in 8MHz)*/ + }; + uint32_t val; + } touch_ctrl1; + union { + struct { + uint32_t reserved0: 2; + uint32_t touch_drange: 2; /*TOUCH_DRANGE*/ + uint32_t touch_drefl: 2; /*TOUCH_DREFL*/ + uint32_t touch_drefh: 2; /*TOUCH_DREFH*/ + uint32_t touch_xpd_bias: 1; /*TOUCH_XPD_BIAS*/ + uint32_t touch_refc: 3; /*TOUCH pad0 reference cap*/ + uint32_t touch_dbias: 1; /*1:use self bias 0:use bandgap bias*/ + uint32_t touch_slp_timer_en: 1; /*touch timer enable bit*/ + uint32_t touch_start_fsm_en: 1; /*1: TOUCH_START & TOUCH_XPD is controlled by touch fsm*/ + uint32_t touch_start_en: 1; /*1: start touch fsm*/ + uint32_t touch_start_force: 1; /*1: to start touch fsm by SW*/ + uint32_t touch_xpd_wait: 8; /*the waiting cycles (in 8MHz) between TOUCH_START and TOUCH_XPD*/ + uint32_t touch_slp_cyc_div: 2; /*when a touch pad is active*/ + uint32_t touch_timer_force_done: 2; /*force touch timer done*/ + uint32_t touch_reset: 1; /*reset upgrade touch*/ + uint32_t touch_clk_fo: 1; /*touch clock force on*/ + uint32_t touch_clkgate_en: 1; /*touch clock enable*/ + }; + uint32_t val; + } touch_ctrl2; + union { + struct { + uint32_t touch_denoise_res: 2; /*De-noise resolution: 12/10/8/4 bit*/ + uint32_t touch_denoise_en: 1; /*touch pad0 will be used to de-noise*/ + uint32_t reserved3: 5; + uint32_t touch_inactive_connection: 1; /*inactive touch pads connect to 1: gnd 0: HighZ*/ + uint32_t touch_shield_pad_en: 1; /*touch pad14 will be used as shield*/ + uint32_t touch_scan_pad_map: 15; /*touch scan mode pad enable map*/ + uint32_t touch_bufdrv: 3; /*touch7 buffer driver strength*/ + uint32_t touch_out_ring: 4; /*select out ring pad*/ + }; + uint32_t val; + } touch_scan_ctrl; + union { + struct { + uint32_t touch_slp_th: 22; /*the threshold for sleep touch pad*/ + uint32_t reserved22: 4; + uint32_t touch_slp_approach_en: 1; /*sleep pad approach function enable*/ + uint32_t touch_slp_pad: 5; + }; + uint32_t val; + } touch_slp_thres; + union { + struct { + uint32_t reserved0: 23; + uint32_t touch_slp_channel_clr: 1; /*clear touch slp channel*/ + uint32_t touch_approach_meas_time: 8; /*approach pads total meas times*/ + }; + uint32_t val; + } touch_approach; + union { + struct { + uint32_t reserved0: 7; + uint32_t touch_bypass_neg_noise_thres: 1; + uint32_t touch_bypass_noise_thres: 1; + uint32_t touch_smooth_lvl: 2; + uint32_t touch_jitter_step: 4; /*touch jitter step*/ + uint32_t touch_neg_noise_limit: 4; /*negative threshold counter limit*/ + uint32_t touch_neg_noise_thres: 2; + uint32_t touch_noise_thres: 2; + uint32_t touch_hysteresis: 2; + uint32_t touch_debounce: 3; /*debounce counter*/ + uint32_t touch_filter_mode: 3; /*0: IIR ? 1: IIR ? 2: IIR 1/8 3: Jitter*/ + uint32_t touch_filter_en: 1; /*touch filter enable*/ + }; + uint32_t val; + } touch_filter_ctrl; + union { + struct { + uint32_t usb_vrefh: 2; + uint32_t usb_vrefl: 2; + uint32_t usb_vref_override: 1; + uint32_t usb_pad_pull_override: 1; + uint32_t usb_dp_pullup: 1; + uint32_t usb_dp_pulldown: 1; + uint32_t usb_dm_pullup: 1; + uint32_t usb_dm_pulldown: 1; + uint32_t usb_pullup_value: 1; + uint32_t usb_pad_enable_override: 1; + uint32_t usb_pad_enable: 1; + uint32_t usb_txm: 1; + uint32_t usb_txp: 1; + uint32_t usb_tx_en: 1; + uint32_t usb_tx_en_override: 1; + uint32_t usb_reset_disable: 1; + uint32_t io_mux_reset_disable: 1; + uint32_t reserved19: 13; + }; + uint32_t val; + } usb_conf; + union { + struct { + uint32_t touch_timeout_num: 22; + uint32_t touch_timeout_en: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } touch_timeout_ctrl; + union { + struct { + uint32_t reject_cause: 18; /*sleep reject cause*/ + uint32_t reserved18: 14; + }; + uint32_t val; + } slp_reject_cause; + union { + struct { + uint32_t force_download_boot: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } option1; + union { + struct { + uint32_t wakeup_cause: 17; /*sleep wakeup cause*/ + uint32_t reserved17: 15; + }; + uint32_t val; + } slp_wakeup_cause; + union { + struct { + uint32_t reserved0: 8; + uint32_t ulp_cp_timer_slp_cycle: 24; /*sleep cycles for ULP-coprocessor timer*/ + }; + uint32_t val; + } ulp_cp_timer_1; + union { + struct { + uint32_t slp_wakeup_w1ts: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1ts: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle_w1ts: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt_w1ts: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done_w1ts: 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp_w1ts: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done_w1ts: 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active_w1ts: 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive_w1ts: 1; /*enable touch inactive interrupt*/ + uint32_t w1ts: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1ts: 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1_w1ts: 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens_w1ts: 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu_w1ts: 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2_w1ts: 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd_w1ts: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1ts: 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap_w1ts: 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout_w1ts: 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det_w1ts: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done_w1ts: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_ena_w1ts; + union { + struct { + uint32_t slp_wakeup_w1tc: 1; /*enable sleep wakeup interrupt*/ + uint32_t slp_reject_w1tc: 1; /*enable sleep reject interrupt*/ + uint32_t sdio_idle_w1tc: 1; /*enable SDIO idle interrupt*/ + uint32_t rtc_wdt_w1tc: 1; /*enable RTC WDT interrupt*/ + uint32_t rtc_touch_scan_done_w1tc: 1; /*enable touch scan done interrupt*/ + uint32_t rtc_ulp_cp_w1tc: 1; /*enable ULP-coprocessor interrupt*/ + uint32_t rtc_touch_done_w1tc: 1; /*enable touch done interrupt*/ + uint32_t rtc_touch_active_w1tc: 1; /*enable touch active interrupt*/ + uint32_t rtc_touch_inactive_w1tc: 1; /*enable touch inactive interrupt*/ + uint32_t w1tc: 1; /*enable brown out interrupt*/ + uint32_t rtc_main_timer_w1tc: 1; /*enable RTC main timer interrupt*/ + uint32_t rtc_saradc1_w1tc: 1; /*enable saradc1 interrupt*/ + uint32_t rtc_tsens_w1tc: 1; /*enable tsens interrupt*/ + uint32_t rtc_cocpu_w1tc: 1; /*enable riscV cocpu interrupt*/ + uint32_t rtc_saradc2_w1tc: 1; /*enable saradc2 interrupt*/ + uint32_t rtc_swd_w1tc: 1; /*enable super watch dog interrupt*/ + uint32_t rtc_xtal32k_dead_w1tc: 1; /*enable xtal32k_dead interrupt*/ + uint32_t rtc_cocpu_trap_w1tc: 1; /*enable cocpu trap interrupt*/ + uint32_t rtc_touch_timeout_w1tc: 1; /*enable touch timeout interrupt*/ + uint32_t rtc_glitch_det_w1tc: 1; /*enbale gitch det interrupt*/ + uint32_t rtc_touch_approach_loop_done_w1tc: 1; + uint32_t reserved21: 11; + }; + uint32_t val; + } int_ena_w1tc; + union { + struct { + uint32_t reserved0: 26; + uint32_t retention_en: 1; + uint32_t retention_wait: 5; /*wait cycles for rention operation*/ + }; + uint32_t val; + } retention_ctrl; + union { + struct { + uint32_t rtc_fib_sel: 3; /*select use analog fib signal*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } fib_sel; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_cntl_dev_t; + +extern rtc_cntl_dev_t RTCCNTL; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rtc_gpio_channel.h b/components/soc/soc/esp32s3/include/soc/rtc_gpio_channel.h new file mode 100644 index 000000000..4d35b1123 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_gpio_channel.h @@ -0,0 +1,70 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +//RTC GPIO channels +#define RTCIO_GPIO36_CHANNEL 0 //RTCIO_CHANNEL_0 +#define RTCIO_CHANNEL_0_GPIO_NUM 36 + +#define RTCIO_GPIO37_CHANNEL 1 //RTCIO_CHANNEL_1 +#define RTCIO_CHANNEL_1_GPIO_NUM 37 + +#define RTCIO_GPIO38_CHANNEL 2 //RTCIO_CHANNEL_2 +#define RTCIO_CHANNEL_2_GPIO_NUM 38 + +#define RTCIO_GPIO39_CHANNEL 3 //RTCIO_CHANNEL_3 +#define RTCIO_CHANNEL_3_GPIO_NUM 39 + +#define RTCIO_GPIO34_CHANNEL 4 //RTCIO_CHANNEL_4 +#define RTCIO_CHANNEL_4_GPIO_NUM 34 + +#define RTCIO_GPIO35_CHANNEL 5 //RTCIO_CHANNEL_5 +#define RTCIO_CHANNEL_5_GPIO_NUM 35 + +#define RTCIO_GPIO25_CHANNEL 6 //RTCIO_CHANNEL_6 +#define RTCIO_CHANNEL_6_GPIO_NUM 25 + +#define RTCIO_GPIO26_CHANNEL 7 //RTCIO_CHANNEL_7 +#define RTCIO_CHANNEL_7_GPIO_NUM 26 + +#define RTCIO_GPIO33_CHANNEL 8 //RTCIO_CHANNEL_8 +#define RTCIO_CHANNEL_8_GPIO_NUM 33 + +#define RTCIO_GPIO32_CHANNEL 9 //RTCIO_CHANNEL_9 +#define RTCIO_CHANNEL_9_GPIO_NUM 32 + +#define RTCIO_GPIO4_CHANNEL 10 //RTCIO_CHANNEL_10 +#define RTCIO_CHANNEL_10_GPIO_NUM 4 + +#define RTCIO_GPIO0_CHANNEL 11 //RTCIO_CHANNEL_11 +#define RTCIO_CHANNEL_11_GPIO_NUM 0 + +#define RTCIO_GPIO2_CHANNEL 12 //RTCIO_CHANNEL_12 +#define RTCIO_CHANNEL_12_GPIO_NUM 2 + +#define RTCIO_GPIO15_CHANNEL 13 //RTCIO_CHANNEL_13 +#define RTCIO_CHANNEL_13_GPIO_NUM 15 + +#define RTCIO_GPIO13_CHANNEL 14 //RTCIO_CHANNEL_14 +#define RTCIO_CHANNEL_14_GPIO_NUM 13 + +#define RTCIO_GPIO12_CHANNEL 15 //RTCIO_CHANNEL_15 +#define RTCIO_CHANNEL_15_GPIO_NUM 12 + +#define RTCIO_GPIO14_CHANNEL 16 //RTCIO_CHANNEL_16 +#define RTCIO_CHANNEL_16_GPIO_NUM 14 + +#define RTCIO_GPIO27_CHANNEL 17 //RTCIO_CHANNEL_17 +#define RTCIO_CHANNEL_17_GPIO_NUM 27 diff --git a/components/soc/soc/esp32s3/include/soc/rtc_i2c_reg.h b/components/soc/soc/esp32s3/include/soc/rtc_i2c_reg.h new file mode 100644 index 000000000..9b7540059 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_i2c_reg.h @@ -0,0 +1,680 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define RTC_I2C_SCL_LOW_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0000) +/* RTC_I2C_SCL_LOW_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ +/*description: time period that scl = 0*/ +#define RTC_I2C_SCL_LOW_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_LOW_PERIOD_M ((RTC_I2C_SCL_LOW_PERIOD_V) << (RTC_I2C_SCL_LOW_PERIOD_S)) +#define RTC_I2C_SCL_LOW_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_LOW_PERIOD_S 0 + +#define RTC_I2C_CTRL_REG (DR_REG_RTC_I2C_BASE + 0x0004) +/* RTC_I2C_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: rtc i2c reg clk gating*/ +#define RTC_I2C_CLK_EN (BIT(31)) +#define RTC_I2C_CLK_EN_M (BIT(31)) +#define RTC_I2C_CLK_EN_V 0x1 +#define RTC_I2C_CLK_EN_S 31 +/* RTC_I2C_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: rtc i2c sw reset*/ +#define RTC_I2C_RESET (BIT(30)) +#define RTC_I2C_RESET_M (BIT(30)) +#define RTC_I2C_RESET_V 0x1 +#define RTC_I2C_RESET_S 30 +/* RTC_I2C_CTRL_CLK_GATE_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define RTC_I2C_CTRL_CLK_GATE_EN (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_M (BIT(29)) +#define RTC_I2C_CTRL_CLK_GATE_EN_V 0x1 +#define RTC_I2C_CTRL_CLK_GATE_EN_S 29 +/* RTC_I2C_RX_LSB_FIRST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: receive lsb first*/ +#define RTC_I2C_RX_LSB_FIRST (BIT(5)) +#define RTC_I2C_RX_LSB_FIRST_M (BIT(5)) +#define RTC_I2C_RX_LSB_FIRST_V 0x1 +#define RTC_I2C_RX_LSB_FIRST_S 5 +/* RTC_I2C_TX_LSB_FIRST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: transit lsb first*/ +#define RTC_I2C_TX_LSB_FIRST (BIT(4)) +#define RTC_I2C_TX_LSB_FIRST_M (BIT(4)) +#define RTC_I2C_TX_LSB_FIRST_V 0x1 +#define RTC_I2C_TX_LSB_FIRST_S 4 +/* RTC_I2C_TRANS_START : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: force start*/ +#define RTC_I2C_TRANS_START (BIT(3)) +#define RTC_I2C_TRANS_START_M (BIT(3)) +#define RTC_I2C_TRANS_START_V 0x1 +#define RTC_I2C_TRANS_START_S 3 +/* RTC_I2C_MS_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: 1=master 0=slave*/ +#define RTC_I2C_MS_MODE (BIT(2)) +#define RTC_I2C_MS_MODE_M (BIT(2)) +#define RTC_I2C_MS_MODE_V 0x1 +#define RTC_I2C_MS_MODE_S 2 +/* RTC_I2C_SCL_FORCE_OUT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1=push pull 0=open drain*/ +#define RTC_I2C_SCL_FORCE_OUT (BIT(1)) +#define RTC_I2C_SCL_FORCE_OUT_M (BIT(1)) +#define RTC_I2C_SCL_FORCE_OUT_V 0x1 +#define RTC_I2C_SCL_FORCE_OUT_S 1 +/* RTC_I2C_SDA_FORCE_OUT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1=push pull 0=open drain*/ +#define RTC_I2C_SDA_FORCE_OUT (BIT(0)) +#define RTC_I2C_SDA_FORCE_OUT_M (BIT(0)) +#define RTC_I2C_SDA_FORCE_OUT_V 0x1 +#define RTC_I2C_SDA_FORCE_OUT_S 0 + +#define RTC_I2C_STATUS_REG (DR_REG_RTC_I2C_BASE + 0x0008) +/* RTC_I2C_SCL_STATE_LAST : RO ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: scl last status*/ +#define RTC_I2C_SCL_STATE_LAST 0x00000007 +#define RTC_I2C_SCL_STATE_LAST_M ((RTC_I2C_SCL_STATE_LAST_V) << (RTC_I2C_SCL_STATE_LAST_S)) +#define RTC_I2C_SCL_STATE_LAST_V 0x7 +#define RTC_I2C_SCL_STATE_LAST_S 28 +/* RTC_I2C_SCL_MAIN_STATE_LAST : RO ;bitpos:[26:24] ;default: 3'b0 ; */ +/*description: i2c last main status*/ +#define RTC_I2C_SCL_MAIN_STATE_LAST 0x00000007 +#define RTC_I2C_SCL_MAIN_STATE_LAST_M ((RTC_I2C_SCL_MAIN_STATE_LAST_V) << (RTC_I2C_SCL_MAIN_STATE_LAST_S)) +#define RTC_I2C_SCL_MAIN_STATE_LAST_V 0x7 +#define RTC_I2C_SCL_MAIN_STATE_LAST_S 24 +/* RTC_I2C_SHIFT : RO ;bitpos:[23:16] ;default: 8'b0 ; */ +/*description: shifter content*/ +#define RTC_I2C_SHIFT 0x000000FF +#define RTC_I2C_SHIFT_M ((RTC_I2C_SHIFT_V) << (RTC_I2C_SHIFT_S)) +#define RTC_I2C_SHIFT_V 0xFF +#define RTC_I2C_SHIFT_S 16 +/* RTC_I2C_OP_CNT : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: which operation is working*/ +#define RTC_I2C_OP_CNT 0x00000003 +#define RTC_I2C_OP_CNT_M ((RTC_I2C_OP_CNT_V) << (RTC_I2C_OP_CNT_S)) +#define RTC_I2C_OP_CNT_V 0x3 +#define RTC_I2C_OP_CNT_S 6 +/* RTC_I2C_BYTE_TRANS : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: One byte transit done*/ +#define RTC_I2C_BYTE_TRANS (BIT(5)) +#define RTC_I2C_BYTE_TRANS_M (BIT(5)) +#define RTC_I2C_BYTE_TRANS_V 0x1 +#define RTC_I2C_BYTE_TRANS_S 5 +/* RTC_I2C_SLAVE_ADDRESSED : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: slave reg sub address*/ +#define RTC_I2C_SLAVE_ADDRESSED (BIT(4)) +#define RTC_I2C_SLAVE_ADDRESSED_M (BIT(4)) +#define RTC_I2C_SLAVE_ADDRESSED_V 0x1 +#define RTC_I2C_SLAVE_ADDRESSED_S 4 +/* RTC_I2C_BUS_BUSY : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: bus is busy*/ +#define RTC_I2C_BUS_BUSY (BIT(3)) +#define RTC_I2C_BUS_BUSY_M (BIT(3)) +#define RTC_I2C_BUS_BUSY_V 0x1 +#define RTC_I2C_BUS_BUSY_S 3 +/* RTC_I2C_ARB_LOST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: arbitration is lost*/ +#define RTC_I2C_ARB_LOST (BIT(2)) +#define RTC_I2C_ARB_LOST_M (BIT(2)) +#define RTC_I2C_ARB_LOST_V 0x1 +#define RTC_I2C_ARB_LOST_S 2 +/* RTC_I2C_SLAVE_RW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: slave read or write*/ +#define RTC_I2C_SLAVE_RW (BIT(1)) +#define RTC_I2C_SLAVE_RW_M (BIT(1)) +#define RTC_I2C_SLAVE_RW_V 0x1 +#define RTC_I2C_SLAVE_RW_S 1 +/* RTC_I2C_ACK_REC : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: ack response*/ +#define RTC_I2C_ACK_REC (BIT(0)) +#define RTC_I2C_ACK_REC_M (BIT(0)) +#define RTC_I2C_ACK_REC_V 0x1 +#define RTC_I2C_ACK_REC_S 0 + +#define RTC_I2C_TIMEOUT_REG (DR_REG_RTC_I2C_BASE + 0x000c) +/* RTC_I2C_TIMEOUT : R/W ;bitpos:[19:0] ;default: 20'h10000 ; */ +/*description: time out threshold*/ +#define RTC_I2C_TIMEOUT 0x000FFFFF +#define RTC_I2C_TIMEOUT_M ((RTC_I2C_TIMEOUT_V) << (RTC_I2C_TIMEOUT_S)) +#define RTC_I2C_TIMEOUT_V 0xFFFFF +#define RTC_I2C_TIMEOUT_S 0 + +#define RTC_I2C_SLAVE_ADDR_REG (DR_REG_RTC_I2C_BASE + 0x0010) +/* RTC_I2C_ADDR_10BIT_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: i2c 10bit mode enable*/ +#define RTC_I2C_ADDR_10BIT_EN (BIT(31)) +#define RTC_I2C_ADDR_10BIT_EN_M (BIT(31)) +#define RTC_I2C_ADDR_10BIT_EN_V 0x1 +#define RTC_I2C_ADDR_10BIT_EN_S 31 +/* RTC_I2C_SLAVE_ADDR : R/W ;bitpos:[14:0] ;default: 15'b0 ; */ +/*description: slave address*/ +#define RTC_I2C_SLAVE_ADDR 0x00007FFF +#define RTC_I2C_SLAVE_ADDR_M ((RTC_I2C_SLAVE_ADDR_V) << (RTC_I2C_SLAVE_ADDR_S)) +#define RTC_I2C_SLAVE_ADDR_V 0x7FFF +#define RTC_I2C_SLAVE_ADDR_S 0 + +#define RTC_I2C_SCL_HIGH_REG (DR_REG_RTC_I2C_BASE + 0x0014) +/* RTC_I2C_SCL_HIGH_PERIOD : R/W ;bitpos:[19:0] ;default: 20'h100 ; */ +/*description: time period that scl = 1*/ +#define RTC_I2C_SCL_HIGH_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_M ((RTC_I2C_SCL_HIGH_PERIOD_V) << (RTC_I2C_SCL_HIGH_PERIOD_S)) +#define RTC_I2C_SCL_HIGH_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_HIGH_PERIOD_S 0 + +#define RTC_I2C_SDA_DUTY_REG (DR_REG_RTC_I2C_BASE + 0x0018) +/* RTC_I2C_SDA_DUTY_NUM : R/W ;bitpos:[19:0] ;default: 20'h10 ; */ +/*description: time period for SDA to toggle after SCL goes low*/ +#define RTC_I2C_SDA_DUTY_NUM 0x000FFFFF +#define RTC_I2C_SDA_DUTY_NUM_M ((RTC_I2C_SDA_DUTY_NUM_V) << (RTC_I2C_SDA_DUTY_NUM_S)) +#define RTC_I2C_SDA_DUTY_NUM_V 0xFFFFF +#define RTC_I2C_SDA_DUTY_NUM_S 0 + +#define RTC_I2C_SCL_START_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x001c) +/* RTC_I2C_SCL_START_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ +/*description: time period for SCL to toggle after I2C start is triggered*/ +#define RTC_I2C_SCL_START_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_START_PERIOD_M ((RTC_I2C_SCL_START_PERIOD_V) << (RTC_I2C_SCL_START_PERIOD_S)) +#define RTC_I2C_SCL_START_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_START_PERIOD_S 0 + +#define RTC_I2C_SCL_STOP_PERIOD_REG (DR_REG_RTC_I2C_BASE + 0x0020) +/* RTC_I2C_SCL_STOP_PERIOD : R/W ;bitpos:[19:0] ;default: 20'b1000 ; */ +/*description: time period for SCL to stop after I2C end is triggered*/ +#define RTC_I2C_SCL_STOP_PERIOD 0x000FFFFF +#define RTC_I2C_SCL_STOP_PERIOD_M ((RTC_I2C_SCL_STOP_PERIOD_V) << (RTC_I2C_SCL_STOP_PERIOD_S)) +#define RTC_I2C_SCL_STOP_PERIOD_V 0xFFFFF +#define RTC_I2C_SCL_STOP_PERIOD_S 0 + +#define RTC_I2C_INT_CLR_REG (DR_REG_RTC_I2C_BASE + 0x0024) +/* RTC_I2C_DETECT_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: clear detect start interrupt*/ +#define RTC_I2C_DETECT_START_INT_CLR (BIT(8)) +#define RTC_I2C_DETECT_START_INT_CLR_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_CLR_V 0x1 +#define RTC_I2C_DETECT_START_INT_CLR_S 8 +/* RTC_I2C_TX_DATA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: clear transit load data complete interrupt*/ +#define RTC_I2C_TX_DATA_INT_CLR (BIT(7)) +#define RTC_I2C_TX_DATA_INT_CLR_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_CLR_V 0x1 +#define RTC_I2C_TX_DATA_INT_CLR_S 7 +/* RTC_I2C_RX_DATA_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: clear receive data interrupt*/ +#define RTC_I2C_RX_DATA_INT_CLR (BIT(6)) +#define RTC_I2C_RX_DATA_INT_CLR_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_CLR_V 0x1 +#define RTC_I2C_RX_DATA_INT_CLR_S 6 +/* RTC_I2C_ACK_ERR_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: clear ack error interrupt*/ +#define RTC_I2C_ACK_ERR_INT_CLR (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_CLR_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_CLR_V 0x1 +#define RTC_I2C_ACK_ERR_INT_CLR_S 5 +/* RTC_I2C_TIMEOUT_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: clear time out interrupt*/ +#define RTC_I2C_TIMEOUT_INT_CLR (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_CLR_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_CLR_V 0x1 +#define RTC_I2C_TIMEOUT_INT_CLR_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: clear transit complete interrupt*/ +#define RTC_I2C_TRANS_COMPLETE_INT_CLR (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_CLR_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: clear master transit complete interrupt*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_CLR_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: clear arbitration lost interrupt*/ +#define RTC_I2C_ARBITRATION_LOST_INT_CLR (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_CLR_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: clear slave transit complete interrupt*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_CLR_S 0 + +#define RTC_I2C_INT_RAW_REG (DR_REG_RTC_I2C_BASE + 0x0028) +/* RTC_I2C_DETECT_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: detect start interrupt raw*/ +#define RTC_I2C_DETECT_START_INT_RAW (BIT(8)) +#define RTC_I2C_DETECT_START_INT_RAW_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_RAW_V 0x1 +#define RTC_I2C_DETECT_START_INT_RAW_S 8 +/* RTC_I2C_TX_DATA_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: transit data interrupt raw*/ +#define RTC_I2C_TX_DATA_INT_RAW (BIT(7)) +#define RTC_I2C_TX_DATA_INT_RAW_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_RAW_V 0x1 +#define RTC_I2C_TX_DATA_INT_RAW_S 7 +/* RTC_I2C_RX_DATA_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: receive data interrupt raw*/ +#define RTC_I2C_RX_DATA_INT_RAW (BIT(6)) +#define RTC_I2C_RX_DATA_INT_RAW_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_RAW_V 0x1 +#define RTC_I2C_RX_DATA_INT_RAW_S 6 +/* RTC_I2C_ACK_ERR_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ack error interrupt raw*/ +#define RTC_I2C_ACK_ERR_INT_RAW (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_RAW_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_RAW_V 0x1 +#define RTC_I2C_ACK_ERR_INT_RAW_S 5 +/* RTC_I2C_TIMEOUT_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: time out interrupt raw*/ +#define RTC_I2C_TIMEOUT_INT_RAW (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_RAW_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_RAW_V 0x1 +#define RTC_I2C_TIMEOUT_INT_RAW_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: transit complete interrupt raw*/ +#define RTC_I2C_TRANS_COMPLETE_INT_RAW (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_RAW_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: master transit complete interrupt raw*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_RAW_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: arbitration lost interrupt raw*/ +#define RTC_I2C_ARBITRATION_LOST_INT_RAW (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_RAW_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: slave transit complete interrupt raw*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_RAW_S 0 + +#define RTC_I2C_INT_ST_REG (DR_REG_RTC_I2C_BASE + 0x002c) +/* RTC_I2C_DETECT_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: detect start interrupt state*/ +#define RTC_I2C_DETECT_START_INT_ST (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ST_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ST_V 0x1 +#define RTC_I2C_DETECT_START_INT_ST_S 8 +/* RTC_I2C_TX_DATA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: transit data interrupt state*/ +#define RTC_I2C_TX_DATA_INT_ST (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ST_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ST_V 0x1 +#define RTC_I2C_TX_DATA_INT_ST_S 7 +/* RTC_I2C_RX_DATA_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: receive data interrupt state*/ +#define RTC_I2C_RX_DATA_INT_ST (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ST_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ST_V 0x1 +#define RTC_I2C_RX_DATA_INT_ST_S 6 +/* RTC_I2C_ACK_ERR_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: ack error interrupt state*/ +#define RTC_I2C_ACK_ERR_INT_ST (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ST_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ST_V 0x1 +#define RTC_I2C_ACK_ERR_INT_ST_S 5 +/* RTC_I2C_TIMEOUT_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: time out interrupt state*/ +#define RTC_I2C_TIMEOUT_INT_ST (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ST_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ST_V 0x1 +#define RTC_I2C_TIMEOUT_INT_ST_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: transit complete interrupt state*/ +#define RTC_I2C_TRANS_COMPLETE_INT_ST (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ST_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_ST_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: master transit complete interrupt state*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_ST_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: arbitration lost interrupt state*/ +#define RTC_I2C_ARBITRATION_LOST_INT_ST (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ST_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_ST_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: slave transit complete interrupt state*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ST_S 0 + +#define RTC_I2C_INT_ENA_REG (DR_REG_RTC_I2C_BASE + 0x0030) +/* RTC_I2C_DETECT_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: enable detect start interrupt*/ +#define RTC_I2C_DETECT_START_INT_ENA (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ENA_M (BIT(8)) +#define RTC_I2C_DETECT_START_INT_ENA_V 0x1 +#define RTC_I2C_DETECT_START_INT_ENA_S 8 +/* RTC_I2C_TX_DATA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: enable transit data interrupt*/ +#define RTC_I2C_TX_DATA_INT_ENA (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ENA_M (BIT(7)) +#define RTC_I2C_TX_DATA_INT_ENA_V 0x1 +#define RTC_I2C_TX_DATA_INT_ENA_S 7 +/* RTC_I2C_RX_DATA_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: enable receive data interrupt*/ +#define RTC_I2C_RX_DATA_INT_ENA (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ENA_M (BIT(6)) +#define RTC_I2C_RX_DATA_INT_ENA_V 0x1 +#define RTC_I2C_RX_DATA_INT_ENA_S 6 +/* RTC_I2C_ACK_ERR_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: enable eack error interrupt*/ +#define RTC_I2C_ACK_ERR_INT_ENA (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ENA_M (BIT(5)) +#define RTC_I2C_ACK_ERR_INT_ENA_V 0x1 +#define RTC_I2C_ACK_ERR_INT_ENA_S 5 +/* RTC_I2C_TIMEOUT_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: enable time out interrupt*/ +#define RTC_I2C_TIMEOUT_INT_ENA (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ENA_M (BIT(4)) +#define RTC_I2C_TIMEOUT_INT_ENA_V 0x1 +#define RTC_I2C_TIMEOUT_INT_ENA_S 4 +/* RTC_I2C_TRANS_COMPLETE_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: enable transit complete interrupt*/ +#define RTC_I2C_TRANS_COMPLETE_INT_ENA (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_M (BIT(3)) +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_V 0x1 +#define RTC_I2C_TRANS_COMPLETE_INT_ENA_S 3 +/* RTC_I2C_MASTER_TRAN_COMP_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: enable master transit complete interrupt*/ +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_M (BIT(2)) +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_V 0x1 +#define RTC_I2C_MASTER_TRAN_COMP_INT_ENA_S 2 +/* RTC_I2C_ARBITRATION_LOST_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: enable arbitration lost interrupt*/ +#define RTC_I2C_ARBITRATION_LOST_INT_ENA (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_M (BIT(1)) +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_V 0x1 +#define RTC_I2C_ARBITRATION_LOST_INT_ENA_S 1 +/* RTC_I2C_SLAVE_TRAN_COMP_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: enable slave transit complete interrupt*/ +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_M (BIT(0)) +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_V 0x1 +#define RTC_I2C_SLAVE_TRAN_COMP_INT_ENA_S 0 + +#define RTC_I2C_DATA_REG (DR_REG_RTC_I2C_BASE + 0x0034) +/* RTC_I2C_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: i2c done*/ +#define RTC_I2C_DONE (BIT(31)) +#define RTC_I2C_DONE_M (BIT(31)) +#define RTC_I2C_DONE_V 0x1 +#define RTC_I2C_DONE_S 31 +/* RTC_I2C_SLAVE_TX_DATA : R/W ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: data sent by slave*/ +#define RTC_I2C_SLAVE_TX_DATA 0x000000FF +#define RTC_I2C_SLAVE_TX_DATA_M ((RTC_I2C_SLAVE_TX_DATA_V) << (RTC_I2C_SLAVE_TX_DATA_S)) +#define RTC_I2C_SLAVE_TX_DATA_V 0xFF +#define RTC_I2C_SLAVE_TX_DATA_S 8 +/* RTC_I2C_RDATA : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: data received*/ +#define RTC_I2C_RDATA 0x000000FF +#define RTC_I2C_RDATA_M ((RTC_I2C_RDATA_V) << (RTC_I2C_RDATA_S)) +#define RTC_I2C_RDATA_V 0xFF +#define RTC_I2C_RDATA_S 0 + +#define RTC_I2C_CMD0_REG (DR_REG_RTC_I2C_BASE + 0x0038) +/* RTC_I2C_COMMAND0_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command0_done*/ +#define RTC_I2C_COMMAND0_DONE (BIT(31)) +#define RTC_I2C_COMMAND0_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND0_DONE_V 0x1 +#define RTC_I2C_COMMAND0_DONE_S 31 +/* RTC_I2C_COMMAND0 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ +/*description: command0*/ +#define RTC_I2C_COMMAND0 0x00003FFF +#define RTC_I2C_COMMAND0_M ((RTC_I2C_COMMAND0_V) << (RTC_I2C_COMMAND0_S)) +#define RTC_I2C_COMMAND0_V 0x3FFF +#define RTC_I2C_COMMAND0_S 0 + +#define RTC_I2C_CMD1_REG (DR_REG_RTC_I2C_BASE + 0x003c) +/* RTC_I2C_COMMAND1_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command1_done*/ +#define RTC_I2C_COMMAND1_DONE (BIT(31)) +#define RTC_I2C_COMMAND1_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND1_DONE_V 0x1 +#define RTC_I2C_COMMAND1_DONE_S 31 +/* RTC_I2C_COMMAND1 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command1*/ +#define RTC_I2C_COMMAND1 0x00003FFF +#define RTC_I2C_COMMAND1_M ((RTC_I2C_COMMAND1_V) << (RTC_I2C_COMMAND1_S)) +#define RTC_I2C_COMMAND1_V 0x3FFF +#define RTC_I2C_COMMAND1_S 0 + +#define RTC_I2C_CMD2_REG (DR_REG_RTC_I2C_BASE + 0x0040) +/* RTC_I2C_COMMAND2_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command2_done*/ +#define RTC_I2C_COMMAND2_DONE (BIT(31)) +#define RTC_I2C_COMMAND2_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND2_DONE_V 0x1 +#define RTC_I2C_COMMAND2_DONE_S 31 +/* RTC_I2C_COMMAND2 : R/W ;bitpos:[13:0] ;default: 14'h0902 ; */ +/*description: command2*/ +#define RTC_I2C_COMMAND2 0x00003FFF +#define RTC_I2C_COMMAND2_M ((RTC_I2C_COMMAND2_V) << (RTC_I2C_COMMAND2_S)) +#define RTC_I2C_COMMAND2_V 0x3FFF +#define RTC_I2C_COMMAND2_S 0 + +#define RTC_I2C_CMD3_REG (DR_REG_RTC_I2C_BASE + 0x0044) +/* RTC_I2C_COMMAND3_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command3_done*/ +#define RTC_I2C_COMMAND3_DONE (BIT(31)) +#define RTC_I2C_COMMAND3_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND3_DONE_V 0x1 +#define RTC_I2C_COMMAND3_DONE_S 31 +/* RTC_I2C_COMMAND3 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ +/*description: command3*/ +#define RTC_I2C_COMMAND3 0x00003FFF +#define RTC_I2C_COMMAND3_M ((RTC_I2C_COMMAND3_V) << (RTC_I2C_COMMAND3_S)) +#define RTC_I2C_COMMAND3_V 0x3FFF +#define RTC_I2C_COMMAND3_S 0 + +#define RTC_I2C_CMD4_REG (DR_REG_RTC_I2C_BASE + 0x0048) +/* RTC_I2C_COMMAND4_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command4_done*/ +#define RTC_I2C_COMMAND4_DONE (BIT(31)) +#define RTC_I2C_COMMAND4_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND4_DONE_V 0x1 +#define RTC_I2C_COMMAND4_DONE_S 31 +/* RTC_I2C_COMMAND4 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ +/*description: command4*/ +#define RTC_I2C_COMMAND4 0x00003FFF +#define RTC_I2C_COMMAND4_M ((RTC_I2C_COMMAND4_V) << (RTC_I2C_COMMAND4_S)) +#define RTC_I2C_COMMAND4_V 0x3FFF +#define RTC_I2C_COMMAND4_S 0 + +#define RTC_I2C_CMD5_REG (DR_REG_RTC_I2C_BASE + 0x004c) +/* RTC_I2C_COMMAND5_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command5_done*/ +#define RTC_I2C_COMMAND5_DONE (BIT(31)) +#define RTC_I2C_COMMAND5_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND5_DONE_V 0x1 +#define RTC_I2C_COMMAND5_DONE_S 31 +/* RTC_I2C_COMMAND5 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ +/*description: command5*/ +#define RTC_I2C_COMMAND5 0x00003FFF +#define RTC_I2C_COMMAND5_M ((RTC_I2C_COMMAND5_V) << (RTC_I2C_COMMAND5_S)) +#define RTC_I2C_COMMAND5_V 0x3FFF +#define RTC_I2C_COMMAND5_S 0 + +#define RTC_I2C_CMD6_REG (DR_REG_RTC_I2C_BASE + 0x0050) +/* RTC_I2C_COMMAND6_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command6_done*/ +#define RTC_I2C_COMMAND6_DONE (BIT(31)) +#define RTC_I2C_COMMAND6_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND6_DONE_V 0x1 +#define RTC_I2C_COMMAND6_DONE_S 31 +/* RTC_I2C_COMMAND6 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command6*/ +#define RTC_I2C_COMMAND6 0x00003FFF +#define RTC_I2C_COMMAND6_M ((RTC_I2C_COMMAND6_V) << (RTC_I2C_COMMAND6_S)) +#define RTC_I2C_COMMAND6_V 0x3FFF +#define RTC_I2C_COMMAND6_S 0 + +#define RTC_I2C_CMD7_REG (DR_REG_RTC_I2C_BASE + 0x0054) +/* RTC_I2C_COMMAND7_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command7_done*/ +#define RTC_I2C_COMMAND7_DONE (BIT(31)) +#define RTC_I2C_COMMAND7_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND7_DONE_V 0x1 +#define RTC_I2C_COMMAND7_DONE_S 31 +/* RTC_I2C_COMMAND7 : R/W ;bitpos:[13:0] ;default: 14'h0904 ; */ +/*description: command7*/ +#define RTC_I2C_COMMAND7 0x00003FFF +#define RTC_I2C_COMMAND7_M ((RTC_I2C_COMMAND7_V) << (RTC_I2C_COMMAND7_S)) +#define RTC_I2C_COMMAND7_V 0x3FFF +#define RTC_I2C_COMMAND7_S 0 + +#define RTC_I2C_CMD8_REG (DR_REG_RTC_I2C_BASE + 0x0058) +/* RTC_I2C_COMMAND8_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command8_done*/ +#define RTC_I2C_COMMAND8_DONE (BIT(31)) +#define RTC_I2C_COMMAND8_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND8_DONE_V 0x1 +#define RTC_I2C_COMMAND8_DONE_S 31 +/* RTC_I2C_COMMAND8 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command8*/ +#define RTC_I2C_COMMAND8 0x00003FFF +#define RTC_I2C_COMMAND8_M ((RTC_I2C_COMMAND8_V) << (RTC_I2C_COMMAND8_S)) +#define RTC_I2C_COMMAND8_V 0x3FFF +#define RTC_I2C_COMMAND8_S 0 + +#define RTC_I2C_CMD9_REG (DR_REG_RTC_I2C_BASE + 0x005c) +/* RTC_I2C_COMMAND9_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command9_done*/ +#define RTC_I2C_COMMAND9_DONE (BIT(31)) +#define RTC_I2C_COMMAND9_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND9_DONE_V 0x1 +#define RTC_I2C_COMMAND9_DONE_S 31 +/* RTC_I2C_COMMAND9 : R/W ;bitpos:[13:0] ;default: 14'h0903 ; */ +/*description: command9*/ +#define RTC_I2C_COMMAND9 0x00003FFF +#define RTC_I2C_COMMAND9_M ((RTC_I2C_COMMAND9_V) << (RTC_I2C_COMMAND9_S)) +#define RTC_I2C_COMMAND9_V 0x3FFF +#define RTC_I2C_COMMAND9_S 0 + +#define RTC_I2C_CMD10_REG (DR_REG_RTC_I2C_BASE + 0x0060) +/* RTC_I2C_COMMAND10_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command10_done*/ +#define RTC_I2C_COMMAND10_DONE (BIT(31)) +#define RTC_I2C_COMMAND10_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND10_DONE_V 0x1 +#define RTC_I2C_COMMAND10_DONE_S 31 +/* RTC_I2C_COMMAND10 : R/W ;bitpos:[13:0] ;default: 14'h0101 ; */ +/*description: command10*/ +#define RTC_I2C_COMMAND10 0x00003FFF +#define RTC_I2C_COMMAND10_M ((RTC_I2C_COMMAND10_V) << (RTC_I2C_COMMAND10_S)) +#define RTC_I2C_COMMAND10_V 0x3FFF +#define RTC_I2C_COMMAND10_S 0 + +#define RTC_I2C_CMD11_REG (DR_REG_RTC_I2C_BASE + 0x0064) +/* RTC_I2C_COMMAND11_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command11_done*/ +#define RTC_I2C_COMMAND11_DONE (BIT(31)) +#define RTC_I2C_COMMAND11_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND11_DONE_V 0x1 +#define RTC_I2C_COMMAND11_DONE_S 31 +/* RTC_I2C_COMMAND11 : R/W ;bitpos:[13:0] ;default: 14'h0901 ; */ +/*description: command11*/ +#define RTC_I2C_COMMAND11 0x00003FFF +#define RTC_I2C_COMMAND11_M ((RTC_I2C_COMMAND11_V) << (RTC_I2C_COMMAND11_S)) +#define RTC_I2C_COMMAND11_V 0x3FFF +#define RTC_I2C_COMMAND11_S 0 + +#define RTC_I2C_CMD12_REG (DR_REG_RTC_I2C_BASE + 0x0068) +/* RTC_I2C_COMMAND12_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command12_done*/ +#define RTC_I2C_COMMAND12_DONE (BIT(31)) +#define RTC_I2C_COMMAND12_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND12_DONE_V 0x1 +#define RTC_I2C_COMMAND12_DONE_S 31 +/* RTC_I2C_COMMAND12 : R/W ;bitpos:[13:0] ;default: 14'h1701 ; */ +/*description: command12*/ +#define RTC_I2C_COMMAND12 0x00003FFF +#define RTC_I2C_COMMAND12_M ((RTC_I2C_COMMAND12_V) << (RTC_I2C_COMMAND12_S)) +#define RTC_I2C_COMMAND12_V 0x3FFF +#define RTC_I2C_COMMAND12_S 0 + +#define RTC_I2C_CMD13_REG (DR_REG_RTC_I2C_BASE + 0x006c) +/* RTC_I2C_COMMAND13_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command13_done*/ +#define RTC_I2C_COMMAND13_DONE (BIT(31)) +#define RTC_I2C_COMMAND13_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND13_DONE_V 0x1 +#define RTC_I2C_COMMAND13_DONE_S 31 +/* RTC_I2C_COMMAND13 : R/W ;bitpos:[13:0] ;default: 14'h1901 ; */ +/*description: command13*/ +#define RTC_I2C_COMMAND13 0x00003FFF +#define RTC_I2C_COMMAND13_M ((RTC_I2C_COMMAND13_V) << (RTC_I2C_COMMAND13_S)) +#define RTC_I2C_COMMAND13_V 0x3FFF +#define RTC_I2C_COMMAND13_S 0 + +#define RTC_I2C_CMD14_REG (DR_REG_RTC_I2C_BASE + 0x0070) +/* RTC_I2C_COMMAND14_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command14_done*/ +#define RTC_I2C_COMMAND14_DONE (BIT(31)) +#define RTC_I2C_COMMAND14_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND14_DONE_V 0x1 +#define RTC_I2C_COMMAND14_DONE_S 31 +/* RTC_I2C_COMMAND14 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: command14*/ +#define RTC_I2C_COMMAND14 0x00003FFF +#define RTC_I2C_COMMAND14_M ((RTC_I2C_COMMAND14_V) << (RTC_I2C_COMMAND14_S)) +#define RTC_I2C_COMMAND14_V 0x3FFF +#define RTC_I2C_COMMAND14_S 0 + +#define RTC_I2C_CMD15_REG (DR_REG_RTC_I2C_BASE + 0x0074) +/* RTC_I2C_COMMAND15_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: command15_done*/ +#define RTC_I2C_COMMAND15_DONE (BIT(31)) +#define RTC_I2C_COMMAND15_DONE_M (BIT(31)) +#define RTC_I2C_COMMAND15_DONE_V 0x1 +#define RTC_I2C_COMMAND15_DONE_S 31 +/* RTC_I2C_COMMAND15 : R/W ;bitpos:[13:0] ;default: 14'h0 ; */ +/*description: command15*/ +#define RTC_I2C_COMMAND15 0x00003FFF +#define RTC_I2C_COMMAND15_M ((RTC_I2C_COMMAND15_V) << (RTC_I2C_COMMAND15_S)) +#define RTC_I2C_COMMAND15_V 0x3FFF +#define RTC_I2C_COMMAND15_S 0 + +#define RTC_I2C_DATE_REG (DR_REG_RTC_I2C_BASE + 0x00FC) +/* RTC_I2C_DATE : R/W ;bitpos:[27:0] ;default: 28'h1905310 ; */ +/*description: */ +#define RTC_I2C_DATE 0x0FFFFFFF +#define RTC_I2C_DATE_M ((RTC_I2C_DATE_V) << (RTC_I2C_DATE_S)) +#define RTC_I2C_DATE_V 0xFFFFFFF +#define RTC_I2C_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rtc_i2c_struct.h b/components/soc/soc/esp32s3/include/soc/rtc_i2c_struct.h new file mode 100644 index 000000000..26b4e62f8 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_i2c_struct.h @@ -0,0 +1,229 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t period: 20; /*time period that scl = 0*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_low; + union { + struct { + uint32_t sda_force_out: 1; /*1=push pull 0=open drain*/ + uint32_t scl_force_out: 1; /*1=push pull 0=open drain*/ + uint32_t ms_mode: 1; /*1=master 0=slave*/ + uint32_t trans_start: 1; /*force start*/ + uint32_t tx_lsb_first: 1; /*transit lsb first*/ + uint32_t rx_lsb_first: 1; /*receive lsb first*/ + uint32_t reserved6: 23; + uint32_t i2c_ctrl_clk_gate_en: 1; + uint32_t i2c_reset: 1; /*rtc i2c sw reset*/ + uint32_t i2cclk_en: 1; /*rtc i2c reg clk gating*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t ack_rec: 1; /*ack response*/ + uint32_t slave_rw: 1; /*slave read or write*/ + uint32_t arb_lost: 1; /*arbitration is lost*/ + uint32_t bus_busy: 1; /*bus is busy*/ + uint32_t slave_addressed: 1; /*slave reg sub address*/ + uint32_t byte_trans: 1; /*One byte transit done*/ + uint32_t op_cnt: 2; /*which operation is working*/ + uint32_t reserved8: 8; + uint32_t shift: 8; /*shifter content*/ + uint32_t scl_main_state_last: 3; /*i2c last main status*/ + uint32_t reserved27: 1; + uint32_t scl_state_last: 3; /*scl last status*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } status; + union { + struct { + uint32_t time_out: 20; /*time out threshold*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } timeout; + union { + struct { + uint32_t addr: 15; /*slave address*/ + uint32_t reserved15: 16; + uint32_t en_10bit: 1; /*i2c 10bit mode enable*/ + }; + uint32_t val; + } slave_addr; + union { + struct { + uint32_t period: 20; /*time period that scl = 1*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_high; + union { + struct { + uint32_t sda_duty_num: 20; /*time period for SDA to toggle after SCL goes low*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } sda_duty; + union { + struct { + uint32_t scl_start_period: 20; /*time period for SCL to toggle after I2C start is triggered*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_start_period; + union { + struct { + uint32_t scl_stop_period: 20; /*time period for SCL to stop after I2C end is triggered*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } scl_stop_period; + union { + struct { + uint32_t slave_tran_comp: 1; /*clear slave transit complete interrupt*/ + uint32_t arbitration_lost: 1; /*clear arbitration lost interrupt*/ + uint32_t master_tran_comp: 1; /*clear master transit complete interrupt*/ + uint32_t trans_complete: 1; /*clear transit complete interrupt*/ + uint32_t time_out: 1; /*clear time out interrupt*/ + uint32_t ack_err: 1; /*clear ack error interrupt*/ + uint32_t rx_data: 1; /*clear receive data interrupt*/ + uint32_t tx_data: 1; /*clear transit load data complete interrupt*/ + uint32_t detect_start: 1; /*clear detect start interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t slave_tran_comp: 1; /*slave transit complete interrupt raw*/ + uint32_t arbitration_lost: 1; /*arbitration lost interrupt raw*/ + uint32_t master_tran_comp: 1; /*master transit complete interrupt raw*/ + uint32_t trans_complete: 1; /*transit complete interrupt raw*/ + uint32_t time_out: 1; /*time out interrupt raw*/ + uint32_t ack_err: 1; /*ack error interrupt raw*/ + uint32_t rx_data: 1; /*receive data interrupt raw*/ + uint32_t tx_data: 1; /*transit data interrupt raw*/ + uint32_t detect_start: 1; /*detect start interrupt raw*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t slave_tran_comp: 1; /*slave transit complete interrupt state*/ + uint32_t arbitration_lost: 1; /*arbitration lost interrupt state*/ + uint32_t master_tran_comp: 1; /*master transit complete interrupt state*/ + uint32_t trans_complete: 1; /*transit complete interrupt state*/ + uint32_t time_out: 1; /*time out interrupt state*/ + uint32_t ack_err: 1; /*ack error interrupt state*/ + uint32_t rx_data: 1; /*receive data interrupt state*/ + uint32_t tx_data: 1; /*transit data interrupt state*/ + uint32_t detect_start: 1; /*detect start interrupt state*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t slave_tran_comp: 1; /*enable slave transit complete interrupt*/ + uint32_t arbitration_lost: 1; /*enable arbitration lost interrupt*/ + uint32_t master_tran_comp: 1; /*enable master transit complete interrupt*/ + uint32_t trans_complete: 1; /*enable transit complete interrupt*/ + uint32_t time_out: 1; /*enable time out interrupt*/ + uint32_t ack_err: 1; /*enable eack error interrupt*/ + uint32_t rx_data: 1; /*enable receive data interrupt*/ + uint32_t tx_data: 1; /*enable transit data interrupt*/ + uint32_t detect_start: 1; /*enable detect start interrupt*/ + uint32_t reserved9: 23; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t i2c_rdata: 8; /*data received*/ + uint32_t slave_tx_data: 8; /*data sent by slave*/ + uint32_t reserved16: 15; + uint32_t i2c_done: 1; /*i2c done*/ + }; + uint32_t val; + } fifo_data; + union { + struct { + uint32_t command0: 14; /*command0*/ + uint32_t reserved14: 17; + uint32_t done: 1; /*command0_done*/ + }; + uint32_t val; + } command[16]; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + union { + struct { + uint32_t i2c_date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_i2c_dev_t; + +extern rtc_i2c_dev_t RTC_I2C; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rtc_io_caps.h b/components/soc/soc/esp32s3/include/soc/rtc_io_caps.h new file mode 100644 index 000000000..20f34d6fe --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_io_caps.h @@ -0,0 +1,18 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_RTC_IO_PIN_COUNT 22 +#define SOC_PIN_FUNC_RTC_IO 0 \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/rtc_io_channel.h b/components/soc/soc/esp32s3/include/soc/rtc_io_channel.h new file mode 100644 index 000000000..3190348fe --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_io_channel.h @@ -0,0 +1,84 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define RTC_GPIO_NUMBER 22 + +//RTC GPIO channels +#define RTCIO_GPIO0_CHANNEL 0 //RTCIO_CHANNEL_0 +#define RTCIO_CHANNEL_0_GPIO_NUM 0 + +#define RTCIO_GPIO1_CHANNEL 1 //RTCIO_CHANNEL_1 +#define RTCIO_CHANNEL_1_GPIO_NUM 1 + +#define RTCIO_GPIO2_CHANNEL 2 //RTCIO_CHANNEL_2 +#define RTCIO_CHANNEL_2_GPIO_NUM 2 + +#define RTCIO_GPIO3_CHANNEL 3 //RTCIO_CHANNEL_3 +#define RTCIO_CHANNEL_3_GPIO_NUM 3 + +#define RTCIO_GPIO4_CHANNEL 4 //RTCIO_CHANNEL_4 +#define RTCIO_CHANNEL_4_GPIO_NUM 4 + +#define RTCIO_GPIO5_CHANNEL 5 //RTCIO_CHANNEL_5 +#define RTCIO_CHANNEL_5_GPIO_NUM 5 + +#define RTCIO_GPIO6_CHANNEL 6 //RTCIO_CHANNEL_6 +#define RTCIO_CHANNEL_6_GPIO_NUM 6 + +#define RTCIO_GPIO7_CHANNEL 7 //RTCIO_CHANNEL_7 +#define RTCIO_CHANNEL_7_GPIO_NUM 7 + +#define RTCIO_GPIO8_CHANNEL 8 //RTCIO_CHANNEL_8 +#define RTCIO_CHANNEL_8_GPIO_NUM 8 + +#define RTCIO_GPIO9_CHANNEL 9 //RTCIO_CHANNEL_9 +#define RTCIO_CHANNEL_9_GPIO_NUM 9 + +#define RTCIO_GPIO10_CHANNEL 10 //RTCIO_CHANNEL_10 +#define RTCIO_CHANNEL_10_GPIO_NUM 10 + +#define RTCIO_GPIO11_CHANNEL 11 //RTCIO_CHANNEL_11 +#define RTCIO_CHANNEL_11_GPIO_NUM 11 + +#define RTCIO_GPIO12_CHANNEL 12 //RTCIO_CHANNEL_12 +#define RTCIO_CHANNEL_12_GPIO_NUM 12 + +#define RTCIO_GPIO13_CHANNEL 13 //RTCIO_CHANNEL_13 +#define RTCIO_CHANNEL_13_GPIO_NUM 13 + +#define RTCIO_GPIO14_CHANNEL 14 //RTCIO_CHANNEL_14 +#define RTCIO_CHANNEL_14_GPIO_NUM 14 + +#define RTCIO_GPIO15_CHANNEL 15 //RTCIO_CHANNEL_15 +#define RTCIO_CHANNEL_15_GPIO_NUM 15 + +#define RTCIO_GPIO16_CHANNEL 16 //RTCIO_CHANNEL_16 +#define RTCIO_CHANNEL_16_GPIO_NUM 16 + +#define RTCIO_GPIO17_CHANNEL 17 //RTCIO_CHANNEL_17 +#define RTCIO_CHANNEL_17_GPIO_NUM 17 + +#define RTCIO_GPIO18_CHANNEL 18 //RTCIO_CHANNEL_18 +#define RTCIO_CHANNEL_18_GPIO_NUM 18 + +#define RTCIO_GPIO19_CHANNEL 19 //RTCIO_CHANNEL_19 +#define RTCIO_CHANNEL_19_GPIO_NUM 19 + +#define RTCIO_GPIO20_CHANNEL 20 //RTCIO_CHANNEL_20 +#define RTCIO_CHANNEL_20_GPIO_NUM 20 + +#define RTCIO_GPIO21_CHANNEL 21 //RTCIO_CHANNEL_21 +#define RTCIO_CHANNEL_21_GPIO_NUM 21 diff --git a/components/soc/soc/esp32s3/include/soc/rtc_io_reg.h b/components/soc/soc/esp32s3/include/soc/rtc_io_reg.h new file mode 100644 index 000000000..acd455d21 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_io_reg.h @@ -0,0 +1,2292 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define RTC_GPIO_OUT_REG (DR_REG_RTCIO_BASE + 0x0) +/* RTC_GPIO_OUT_DATA : R/W ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 output data*/ +#define RTC_GPIO_OUT_DATA 0x003FFFFF +#define RTC_GPIO_OUT_DATA_M ((RTC_GPIO_OUT_DATA_V) << (RTC_GPIO_OUT_DATA_S)) +#define RTC_GPIO_OUT_DATA_V 0x3FFFFF +#define RTC_GPIO_OUT_DATA_S 10 + +#define RTC_GPIO_OUT_W1TS_REG (DR_REG_RTCIO_BASE + 0x4) +/* RTC_GPIO_OUT_DATA_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 output data write 1 to set*/ +#define RTC_GPIO_OUT_DATA_W1TS 0x003FFFFF +#define RTC_GPIO_OUT_DATA_W1TS_M ((RTC_GPIO_OUT_DATA_W1TS_V) << (RTC_GPIO_OUT_DATA_W1TS_S)) +#define RTC_GPIO_OUT_DATA_W1TS_V 0x3FFFFF +#define RTC_GPIO_OUT_DATA_W1TS_S 10 + +#define RTC_GPIO_OUT_W1TC_REG (DR_REG_RTCIO_BASE + 0x8) +/* RTC_GPIO_OUT_DATA_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 output data write 1 to clear*/ +#define RTC_GPIO_OUT_DATA_W1TC 0x003FFFFF +#define RTC_GPIO_OUT_DATA_W1TC_M ((RTC_GPIO_OUT_DATA_W1TC_V) << (RTC_GPIO_OUT_DATA_W1TC_S)) +#define RTC_GPIO_OUT_DATA_W1TC_V 0x3FFFFF +#define RTC_GPIO_OUT_DATA_W1TC_S 10 + +#define RTC_GPIO_ENABLE_REG (DR_REG_RTCIO_BASE + 0xC) +/* RTC_GPIO_ENABLE : R/W ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 enable*/ +#define RTC_GPIO_ENABLE 0x003FFFFF +#define RTC_GPIO_ENABLE_M ((RTC_GPIO_ENABLE_V) << (RTC_GPIO_ENABLE_S)) +#define RTC_GPIO_ENABLE_V 0x3FFFFF +#define RTC_GPIO_ENABLE_S 10 + +#define RTC_GPIO_ENABLE_W1TS_REG (DR_REG_RTCIO_BASE + 0x10) +/* RTC_GPIO_ENABLE_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 enable write 1 to set*/ +#define RTC_GPIO_ENABLE_W1TS 0x003FFFFF +#define RTC_GPIO_ENABLE_W1TS_M ((RTC_GPIO_ENABLE_W1TS_V) << (RTC_GPIO_ENABLE_W1TS_S)) +#define RTC_GPIO_ENABLE_W1TS_V 0x3FFFFF +#define RTC_GPIO_ENABLE_W1TS_S 10 + +#define RTC_GPIO_ENABLE_W1TC_REG (DR_REG_RTCIO_BASE + 0x14) +/* RTC_GPIO_ENABLE_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 enable write 1 to clear*/ +#define RTC_GPIO_ENABLE_W1TC 0x003FFFFF +#define RTC_GPIO_ENABLE_W1TC_M ((RTC_GPIO_ENABLE_W1TC_V) << (RTC_GPIO_ENABLE_W1TC_S)) +#define RTC_GPIO_ENABLE_W1TC_V 0x3FFFFF +#define RTC_GPIO_ENABLE_W1TC_S 10 + +#define RTC_GPIO_STATUS_REG (DR_REG_RTCIO_BASE + 0x18) +/* RTC_GPIO_STATUS_INT : R/W ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 interrupt status*/ +#define RTC_GPIO_STATUS_INT 0x003FFFFF +#define RTC_GPIO_STATUS_INT_M ((RTC_GPIO_STATUS_INT_V) << (RTC_GPIO_STATUS_INT_S)) +#define RTC_GPIO_STATUS_INT_V 0x3FFFFF +#define RTC_GPIO_STATUS_INT_S 10 + +#define RTC_GPIO_STATUS_W1TS_REG (DR_REG_RTCIO_BASE + 0x1C) +/* RTC_GPIO_STATUS_INT_W1TS : WO ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to set*/ +#define RTC_GPIO_STATUS_INT_W1TS 0x003FFFFF +#define RTC_GPIO_STATUS_INT_W1TS_M ((RTC_GPIO_STATUS_INT_W1TS_V) << (RTC_GPIO_STATUS_INT_W1TS_S)) +#define RTC_GPIO_STATUS_INT_W1TS_V 0x3FFFFF +#define RTC_GPIO_STATUS_INT_W1TS_S 10 + +#define RTC_GPIO_STATUS_W1TC_REG (DR_REG_RTCIO_BASE + 0x20) +/* RTC_GPIO_STATUS_INT_W1TC : WO ;bitpos:[31:10] ;default: 0 ; */ +/*description: RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/ +#define RTC_GPIO_STATUS_INT_W1TC 0x003FFFFF +#define RTC_GPIO_STATUS_INT_W1TC_M ((RTC_GPIO_STATUS_INT_W1TC_V) << (RTC_GPIO_STATUS_INT_W1TC_S)) +#define RTC_GPIO_STATUS_INT_W1TC_V 0x3FFFFF +#define RTC_GPIO_STATUS_INT_W1TC_S 10 + +#define RTC_GPIO_IN_REG (DR_REG_RTCIO_BASE + 0x24) +/* RTC_GPIO_IN_NEXT : RO ;bitpos:[31:10] ;default: ; */ +/*description: RTC GPIO input data*/ +#define RTC_GPIO_IN_NEXT 0x003FFFFF +#define RTC_GPIO_IN_NEXT_M ((RTC_GPIO_IN_NEXT_V) << (RTC_GPIO_IN_NEXT_S)) +#define RTC_GPIO_IN_NEXT_V 0x3FFFFF +#define RTC_GPIO_IN_NEXT_S 10 + +#define RTC_GPIO_PIN0_REG (DR_REG_RTCIO_BASE + 0x28) +/* RTC_GPIO_PIN0_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN0_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN0_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN0_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN0_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN0_INT_TYPE_M ((RTC_GPIO_PIN0_INT_TYPE_V) << (RTC_GPIO_PIN0_INT_TYPE_S)) +#define RTC_GPIO_PIN0_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN0_INT_TYPE_S 7 +/* RTC_GPIO_PIN0_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN0_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN0_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN0_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN1_REG (DR_REG_RTCIO_BASE + 0x2C) +/* RTC_GPIO_PIN1_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN1_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN1_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN1_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN1_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN1_INT_TYPE_M ((RTC_GPIO_PIN1_INT_TYPE_V) << (RTC_GPIO_PIN1_INT_TYPE_S)) +#define RTC_GPIO_PIN1_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN1_INT_TYPE_S 7 +/* RTC_GPIO_PIN1_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN1_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN1_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN1_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN2_REG (DR_REG_RTCIO_BASE + 0x30) +/* RTC_GPIO_PIN2_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN2_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN2_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN2_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN2_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN2_INT_TYPE_M ((RTC_GPIO_PIN2_INT_TYPE_V) << (RTC_GPIO_PIN2_INT_TYPE_S)) +#define RTC_GPIO_PIN2_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN2_INT_TYPE_S 7 +/* RTC_GPIO_PIN2_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN2_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN2_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN2_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN3_REG (DR_REG_RTCIO_BASE + 0x34) +/* RTC_GPIO_PIN3_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN3_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN3_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN3_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN3_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN3_INT_TYPE_M ((RTC_GPIO_PIN3_INT_TYPE_V) << (RTC_GPIO_PIN3_INT_TYPE_S)) +#define RTC_GPIO_PIN3_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN3_INT_TYPE_S 7 +/* RTC_GPIO_PIN3_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN3_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN3_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN3_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN4_REG (DR_REG_RTCIO_BASE + 0x38) +/* RTC_GPIO_PIN4_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN4_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN4_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN4_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN4_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN4_INT_TYPE_M ((RTC_GPIO_PIN4_INT_TYPE_V) << (RTC_GPIO_PIN4_INT_TYPE_S)) +#define RTC_GPIO_PIN4_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN4_INT_TYPE_S 7 +/* RTC_GPIO_PIN4_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN4_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN4_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN4_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN5_REG (DR_REG_RTCIO_BASE + 0x3C) +/* RTC_GPIO_PIN5_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN5_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN5_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN5_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN5_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN5_INT_TYPE_M ((RTC_GPIO_PIN5_INT_TYPE_V) << (RTC_GPIO_PIN5_INT_TYPE_S)) +#define RTC_GPIO_PIN5_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN5_INT_TYPE_S 7 +/* RTC_GPIO_PIN5_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN5_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN5_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN5_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN6_REG (DR_REG_RTCIO_BASE + 0x40) +/* RTC_GPIO_PIN6_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN6_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN6_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN6_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN6_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN6_INT_TYPE_M ((RTC_GPIO_PIN6_INT_TYPE_V) << (RTC_GPIO_PIN6_INT_TYPE_S)) +#define RTC_GPIO_PIN6_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN6_INT_TYPE_S 7 +/* RTC_GPIO_PIN6_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN6_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN6_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN6_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN7_REG (DR_REG_RTCIO_BASE + 0x44) +/* RTC_GPIO_PIN7_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN7_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN7_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN7_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN7_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN7_INT_TYPE_M ((RTC_GPIO_PIN7_INT_TYPE_V) << (RTC_GPIO_PIN7_INT_TYPE_S)) +#define RTC_GPIO_PIN7_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN7_INT_TYPE_S 7 +/* RTC_GPIO_PIN7_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN7_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN7_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN7_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN8_REG (DR_REG_RTCIO_BASE + 0x48) +/* RTC_GPIO_PIN8_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN8_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN8_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN8_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN8_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN8_INT_TYPE_M ((RTC_GPIO_PIN8_INT_TYPE_V) << (RTC_GPIO_PIN8_INT_TYPE_S)) +#define RTC_GPIO_PIN8_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN8_INT_TYPE_S 7 +/* RTC_GPIO_PIN8_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN8_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN8_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN8_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN9_REG (DR_REG_RTCIO_BASE + 0x4C) +/* RTC_GPIO_PIN9_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN9_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN9_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN9_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN9_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN9_INT_TYPE_M ((RTC_GPIO_PIN9_INT_TYPE_V) << (RTC_GPIO_PIN9_INT_TYPE_S)) +#define RTC_GPIO_PIN9_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN9_INT_TYPE_S 7 +/* RTC_GPIO_PIN9_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN9_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN9_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN9_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN10_REG (DR_REG_RTCIO_BASE + 0x50) +/* RTC_GPIO_PIN10_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN10_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN10_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN10_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN10_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN10_INT_TYPE_M ((RTC_GPIO_PIN10_INT_TYPE_V) << (RTC_GPIO_PIN10_INT_TYPE_S)) +#define RTC_GPIO_PIN10_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN10_INT_TYPE_S 7 +/* RTC_GPIO_PIN10_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN10_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN10_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN10_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN11_REG (DR_REG_RTCIO_BASE + 0x54) +/* RTC_GPIO_PIN11_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN11_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN11_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN11_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN11_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN11_INT_TYPE_M ((RTC_GPIO_PIN11_INT_TYPE_V) << (RTC_GPIO_PIN11_INT_TYPE_S)) +#define RTC_GPIO_PIN11_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN11_INT_TYPE_S 7 +/* RTC_GPIO_PIN11_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN11_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN11_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN11_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN12_REG (DR_REG_RTCIO_BASE + 0x58) +/* RTC_GPIO_PIN12_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN12_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN12_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN12_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN12_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN12_INT_TYPE_M ((RTC_GPIO_PIN12_INT_TYPE_V) << (RTC_GPIO_PIN12_INT_TYPE_S)) +#define RTC_GPIO_PIN12_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN12_INT_TYPE_S 7 +/* RTC_GPIO_PIN12_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN12_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN12_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN12_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN13_REG (DR_REG_RTCIO_BASE + 0x5C) +/* RTC_GPIO_PIN13_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN13_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN13_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN13_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN13_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN13_INT_TYPE_M ((RTC_GPIO_PIN13_INT_TYPE_V) << (RTC_GPIO_PIN13_INT_TYPE_S)) +#define RTC_GPIO_PIN13_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN13_INT_TYPE_S 7 +/* RTC_GPIO_PIN13_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN13_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN13_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN13_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN14_REG (DR_REG_RTCIO_BASE + 0x60) +/* RTC_GPIO_PIN14_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN14_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN14_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN14_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN14_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN14_INT_TYPE_M ((RTC_GPIO_PIN14_INT_TYPE_V) << (RTC_GPIO_PIN14_INT_TYPE_S)) +#define RTC_GPIO_PIN14_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN14_INT_TYPE_S 7 +/* RTC_GPIO_PIN14_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN14_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN14_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN14_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN15_REG (DR_REG_RTCIO_BASE + 0x64) +/* RTC_GPIO_PIN15_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN15_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN15_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN15_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN15_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN15_INT_TYPE_M ((RTC_GPIO_PIN15_INT_TYPE_V) << (RTC_GPIO_PIN15_INT_TYPE_S)) +#define RTC_GPIO_PIN15_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN15_INT_TYPE_S 7 +/* RTC_GPIO_PIN15_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN15_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN15_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN15_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN16_REG (DR_REG_RTCIO_BASE + 0x68) +/* RTC_GPIO_PIN16_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN16_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN16_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN16_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN16_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN16_INT_TYPE_M ((RTC_GPIO_PIN16_INT_TYPE_V) << (RTC_GPIO_PIN16_INT_TYPE_S)) +#define RTC_GPIO_PIN16_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN16_INT_TYPE_S 7 +/* RTC_GPIO_PIN16_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN16_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN16_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN16_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN17_REG (DR_REG_RTCIO_BASE + 0x6C) +/* RTC_GPIO_PIN17_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN17_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN17_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN17_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN17_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN17_INT_TYPE_M ((RTC_GPIO_PIN17_INT_TYPE_V) << (RTC_GPIO_PIN17_INT_TYPE_S)) +#define RTC_GPIO_PIN17_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN17_INT_TYPE_S 7 +/* RTC_GPIO_PIN17_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN17_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN17_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN17_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN18_REG (DR_REG_RTCIO_BASE + 0x70) +/* RTC_GPIO_PIN18_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN18_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN18_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN18_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN18_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN18_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN18_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN18_INT_TYPE_M ((RTC_GPIO_PIN18_INT_TYPE_V) << (RTC_GPIO_PIN18_INT_TYPE_S)) +#define RTC_GPIO_PIN18_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN18_INT_TYPE_S 7 +/* RTC_GPIO_PIN18_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN18_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN18_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN18_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN18_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN19_REG (DR_REG_RTCIO_BASE + 0x74) +/* RTC_GPIO_PIN19_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN19_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN19_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN19_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN19_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN19_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN19_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN19_INT_TYPE_M ((RTC_GPIO_PIN19_INT_TYPE_V) << (RTC_GPIO_PIN19_INT_TYPE_S)) +#define RTC_GPIO_PIN19_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN19_INT_TYPE_S 7 +/* RTC_GPIO_PIN19_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN19_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN19_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN19_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN19_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN20_REG (DR_REG_RTCIO_BASE + 0x78) +/* RTC_GPIO_PIN20_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN20_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN20_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN20_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN20_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN20_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN20_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN20_INT_TYPE_M ((RTC_GPIO_PIN20_INT_TYPE_V) << (RTC_GPIO_PIN20_INT_TYPE_S)) +#define RTC_GPIO_PIN20_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN20_INT_TYPE_S 7 +/* RTC_GPIO_PIN20_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN20_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN20_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN20_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN20_PAD_DRIVER_S 2 + +#define RTC_GPIO_PIN21_REG (DR_REG_RTCIO_BASE + 0x7C) +/* RTC_GPIO_PIN21_WAKEUP_ENABLE : R/W ;bitpos:[10] ;default: 0 ; */ +/*description: RTC GPIO wakeup enable bit*/ +#define RTC_GPIO_PIN21_WAKEUP_ENABLE (BIT(10)) +#define RTC_GPIO_PIN21_WAKEUP_ENABLE_M (BIT(10)) +#define RTC_GPIO_PIN21_WAKEUP_ENABLE_V 0x1 +#define RTC_GPIO_PIN21_WAKEUP_ENABLE_S 10 +/* RTC_GPIO_PIN21_INT_TYPE : R/W ;bitpos:[9:7] ;default: 0 ; */ +/*description: if set to 0: GPIO interrupt disable if set to 1: rising edge + trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ +#define RTC_GPIO_PIN21_INT_TYPE 0x00000007 +#define RTC_GPIO_PIN21_INT_TYPE_M ((RTC_GPIO_PIN21_INT_TYPE_V) << (RTC_GPIO_PIN21_INT_TYPE_S)) +#define RTC_GPIO_PIN21_INT_TYPE_V 0x7 +#define RTC_GPIO_PIN21_INT_TYPE_S 7 +/* RTC_GPIO_PIN21_PAD_DRIVER : R/W ;bitpos:[2] ;default: 0 ; */ +/*description: if set to 0: normal output if set to 1: open drain*/ +#define RTC_GPIO_PIN21_PAD_DRIVER (BIT(2)) +#define RTC_GPIO_PIN21_PAD_DRIVER_M (BIT(2)) +#define RTC_GPIO_PIN21_PAD_DRIVER_V 0x1 +#define RTC_GPIO_PIN21_PAD_DRIVER_S 2 + +#define RTC_IO_RTC_DEBUG_SEL_REG (DR_REG_RTCIO_BASE + 0x80) +/* RTC_IO_DEBUG_12M_NO_GATING : R/W ;bitpos:[25] ;default: 1'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_12M_NO_GATING (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_M (BIT(25)) +#define RTC_IO_DEBUG_12M_NO_GATING_V 0x1 +#define RTC_IO_DEBUG_12M_NO_GATING_S 25 +/* RTC_IO_DEBUG_SEL4 : R/W ;bitpos:[24:20] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL4 0x0000001F +#define RTC_IO_DEBUG_SEL4_M ((RTC_IO_DEBUG_SEL4_V) << (RTC_IO_DEBUG_SEL4_S)) +#define RTC_IO_DEBUG_SEL4_V 0x1F +#define RTC_IO_DEBUG_SEL4_S 20 +/* RTC_IO_DEBUG_SEL3 : R/W ;bitpos:[19:15] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL3 0x0000001F +#define RTC_IO_DEBUG_SEL3_M ((RTC_IO_DEBUG_SEL3_V) << (RTC_IO_DEBUG_SEL3_S)) +#define RTC_IO_DEBUG_SEL3_V 0x1F +#define RTC_IO_DEBUG_SEL3_S 15 +/* RTC_IO_DEBUG_SEL2 : R/W ;bitpos:[14:10] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL2 0x0000001F +#define RTC_IO_DEBUG_SEL2_M ((RTC_IO_DEBUG_SEL2_V) << (RTC_IO_DEBUG_SEL2_S)) +#define RTC_IO_DEBUG_SEL2_V 0x1F +#define RTC_IO_DEBUG_SEL2_S 10 +/* RTC_IO_DEBUG_SEL1 : R/W ;bitpos:[9:5] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL1 0x0000001F +#define RTC_IO_DEBUG_SEL1_M ((RTC_IO_DEBUG_SEL1_V) << (RTC_IO_DEBUG_SEL1_S)) +#define RTC_IO_DEBUG_SEL1_V 0x1F +#define RTC_IO_DEBUG_SEL1_S 5 +/* RTC_IO_DEBUG_SEL0 : R/W ;bitpos:[4:0] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_DEBUG_SEL0 0x0000001F +#define RTC_IO_DEBUG_SEL0_M ((RTC_IO_DEBUG_SEL0_V) << (RTC_IO_DEBUG_SEL0_S)) +#define RTC_IO_DEBUG_SEL0_V 0x1F +#define RTC_IO_DEBUG_SEL0_S 0 + +#define RTC_IO_TOUCH_PAD0_REG (DR_REG_RTCIO_BASE + 0x84) +/* RTC_IO_TOUCH_PAD0_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD0_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD0_DRV_M ((RTC_IO_TOUCH_PAD0_DRV_V) << (RTC_IO_TOUCH_PAD0_DRV_S)) +#define RTC_IO_TOUCH_PAD0_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD0_DRV_S 29 +/* RTC_IO_TOUCH_PAD0_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD0_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD0_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RDE_S 28 +/* RTC_IO_TOUCH_PAD0_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD0_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD0_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD0_RUE_S 27 +/* RTC_IO_TOUCH_PAD0_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD0_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD0_DAC_M ((RTC_IO_TOUCH_PAD0_DAC_V) << (RTC_IO_TOUCH_PAD0_DAC_S)) +#define RTC_IO_TOUCH_PAD0_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD0_DAC_S 23 +/* RTC_IO_TOUCH_PAD0_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD0_START (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD0_START_V 0x1 +#define RTC_IO_TOUCH_PAD0_START_S 22 +/* RTC_IO_TOUCH_PAD0_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD0_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD0_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD0_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD0_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD0_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD0_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD0_XPD_S 20 +/* RTC_IO_TOUCH_PAD0_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD0_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD0_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD0_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD0_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_M ((RTC_IO_TOUCH_PAD0_FUN_SEL_V) << (RTC_IO_TOUCH_PAD0_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD0_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD0_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD0_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD0_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD0_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD0_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD0_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD0_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD0_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD0_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD0_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD0_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD0_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD0_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD0_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD0_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD1_REG (DR_REG_RTCIO_BASE + 0x88) +/* RTC_IO_TOUCH_PAD1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD1_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD1_DRV_M ((RTC_IO_TOUCH_PAD1_DRV_V) << (RTC_IO_TOUCH_PAD1_DRV_S)) +#define RTC_IO_TOUCH_PAD1_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD1_DRV_S 29 +/* RTC_IO_TOUCH_PAD1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD1_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD1_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RDE_S 28 +/* RTC_IO_TOUCH_PAD1_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD1_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD1_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD1_RUE_S 27 +/* RTC_IO_TOUCH_PAD1_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD1_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD1_DAC_M ((RTC_IO_TOUCH_PAD1_DAC_V) << (RTC_IO_TOUCH_PAD1_DAC_S)) +#define RTC_IO_TOUCH_PAD1_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD1_DAC_S 23 +/* RTC_IO_TOUCH_PAD1_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD1_START (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD1_START_V 0x1 +#define RTC_IO_TOUCH_PAD1_START_S 22 +/* RTC_IO_TOUCH_PAD1_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD1_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD1_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD1_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD1_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD1_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD1_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD1_XPD_S 20 +/* RTC_IO_TOUCH_PAD1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD1_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD1_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD1_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_M ((RTC_IO_TOUCH_PAD1_FUN_SEL_V) << (RTC_IO_TOUCH_PAD1_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD1_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD1_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD1_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD1_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD1_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD1_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD1_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD1_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD1_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD1_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD1_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD1_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD2_REG (DR_REG_RTCIO_BASE + 0x8C) +/* RTC_IO_TOUCH_PAD2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD2_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD2_DRV_M ((RTC_IO_TOUCH_PAD2_DRV_V) << (RTC_IO_TOUCH_PAD2_DRV_S)) +#define RTC_IO_TOUCH_PAD2_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD2_DRV_S 29 +/* RTC_IO_TOUCH_PAD2_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD2_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD2_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RDE_S 28 +/* RTC_IO_TOUCH_PAD2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD2_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD2_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD2_RUE_S 27 +/* RTC_IO_TOUCH_PAD2_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD2_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD2_DAC_M ((RTC_IO_TOUCH_PAD2_DAC_V) << (RTC_IO_TOUCH_PAD2_DAC_S)) +#define RTC_IO_TOUCH_PAD2_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD2_DAC_S 23 +/* RTC_IO_TOUCH_PAD2_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD2_START (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD2_START_V 0x1 +#define RTC_IO_TOUCH_PAD2_START_S 22 +/* RTC_IO_TOUCH_PAD2_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD2_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD2_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD2_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD2_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD2_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD2_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD2_XPD_S 20 +/* RTC_IO_TOUCH_PAD2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD2_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD2_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD2_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_M ((RTC_IO_TOUCH_PAD2_FUN_SEL_V) << (RTC_IO_TOUCH_PAD2_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD2_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD2_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD2_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD2_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD2_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD2_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD2_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD2_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD2_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD2_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD2_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD2_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD3_REG (DR_REG_RTCIO_BASE + 0x90) +/* RTC_IO_TOUCH_PAD3_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD3_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD3_DRV_M ((RTC_IO_TOUCH_PAD3_DRV_V) << (RTC_IO_TOUCH_PAD3_DRV_S)) +#define RTC_IO_TOUCH_PAD3_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD3_DRV_S 29 +/* RTC_IO_TOUCH_PAD3_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD3_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD3_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RDE_S 28 +/* RTC_IO_TOUCH_PAD3_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD3_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD3_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD3_RUE_S 27 +/* RTC_IO_TOUCH_PAD3_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD3_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD3_DAC_M ((RTC_IO_TOUCH_PAD3_DAC_V) << (RTC_IO_TOUCH_PAD3_DAC_S)) +#define RTC_IO_TOUCH_PAD3_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD3_DAC_S 23 +/* RTC_IO_TOUCH_PAD3_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD3_START (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD3_START_V 0x1 +#define RTC_IO_TOUCH_PAD3_START_S 22 +/* RTC_IO_TOUCH_PAD3_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD3_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD3_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD3_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD3_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD3_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD3_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD3_XPD_S 20 +/* RTC_IO_TOUCH_PAD3_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD3_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD3_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD3_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD3_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_M ((RTC_IO_TOUCH_PAD3_FUN_SEL_V) << (RTC_IO_TOUCH_PAD3_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD3_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD3_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD3_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD3_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD3_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD3_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD3_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD3_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD3_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD3_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD3_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD3_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD3_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD3_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD3_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD3_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD4_REG (DR_REG_RTCIO_BASE + 0x94) +/* RTC_IO_TOUCH_PAD4_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD4_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD4_DRV_M ((RTC_IO_TOUCH_PAD4_DRV_V) << (RTC_IO_TOUCH_PAD4_DRV_S)) +#define RTC_IO_TOUCH_PAD4_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD4_DRV_S 29 +/* RTC_IO_TOUCH_PAD4_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD4_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD4_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RDE_S 28 +/* RTC_IO_TOUCH_PAD4_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD4_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD4_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD4_RUE_S 27 +/* RTC_IO_TOUCH_PAD4_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD4_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD4_DAC_M ((RTC_IO_TOUCH_PAD4_DAC_V) << (RTC_IO_TOUCH_PAD4_DAC_S)) +#define RTC_IO_TOUCH_PAD4_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD4_DAC_S 23 +/* RTC_IO_TOUCH_PAD4_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD4_START (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD4_START_V 0x1 +#define RTC_IO_TOUCH_PAD4_START_S 22 +/* RTC_IO_TOUCH_PAD4_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD4_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD4_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD4_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD4_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD4_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD4_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD4_XPD_S 20 +/* RTC_IO_TOUCH_PAD4_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD4_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD4_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD4_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD4_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_M ((RTC_IO_TOUCH_PAD4_FUN_SEL_V) << (RTC_IO_TOUCH_PAD4_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD4_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD4_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD4_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD4_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD4_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD4_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD4_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD4_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD4_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD4_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD4_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD4_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD4_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD4_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD4_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD4_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD5_REG (DR_REG_RTCIO_BASE + 0x98) +/* RTC_IO_TOUCH_PAD5_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD5_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD5_DRV_M ((RTC_IO_TOUCH_PAD5_DRV_V) << (RTC_IO_TOUCH_PAD5_DRV_S)) +#define RTC_IO_TOUCH_PAD5_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD5_DRV_S 29 +/* RTC_IO_TOUCH_PAD5_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD5_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD5_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RDE_S 28 +/* RTC_IO_TOUCH_PAD5_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD5_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD5_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD5_RUE_S 27 +/* RTC_IO_TOUCH_PAD5_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD5_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD5_DAC_M ((RTC_IO_TOUCH_PAD5_DAC_V) << (RTC_IO_TOUCH_PAD5_DAC_S)) +#define RTC_IO_TOUCH_PAD5_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD5_DAC_S 23 +/* RTC_IO_TOUCH_PAD5_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD5_START (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD5_START_V 0x1 +#define RTC_IO_TOUCH_PAD5_START_S 22 +/* RTC_IO_TOUCH_PAD5_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD5_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD5_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD5_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD5_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD5_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD5_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD5_XPD_S 20 +/* RTC_IO_TOUCH_PAD5_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD5_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD5_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD5_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD5_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_M ((RTC_IO_TOUCH_PAD5_FUN_SEL_V) << (RTC_IO_TOUCH_PAD5_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD5_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD5_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD5_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD5_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD5_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD5_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD5_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD5_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD5_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD5_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD5_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD5_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD5_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD5_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD5_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD5_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD6_REG (DR_REG_RTCIO_BASE + 0x9C) +/* RTC_IO_TOUCH_PAD6_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD6_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD6_DRV_M ((RTC_IO_TOUCH_PAD6_DRV_V) << (RTC_IO_TOUCH_PAD6_DRV_S)) +#define RTC_IO_TOUCH_PAD6_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD6_DRV_S 29 +/* RTC_IO_TOUCH_PAD6_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD6_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD6_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RDE_S 28 +/* RTC_IO_TOUCH_PAD6_RUE : R/W ;bitpos:[27] ;default: 1'd1 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD6_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD6_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD6_RUE_S 27 +/* RTC_IO_TOUCH_PAD6_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD6_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD6_DAC_M ((RTC_IO_TOUCH_PAD6_DAC_V) << (RTC_IO_TOUCH_PAD6_DAC_S)) +#define RTC_IO_TOUCH_PAD6_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD6_DAC_S 23 +/* RTC_IO_TOUCH_PAD6_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD6_START (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD6_START_V 0x1 +#define RTC_IO_TOUCH_PAD6_START_S 22 +/* RTC_IO_TOUCH_PAD6_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD6_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD6_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD6_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD6_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD6_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD6_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD6_XPD_S 20 +/* RTC_IO_TOUCH_PAD6_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD6_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD6_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD6_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD6_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_M ((RTC_IO_TOUCH_PAD6_FUN_SEL_V) << (RTC_IO_TOUCH_PAD6_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD6_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD6_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD6_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD6_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD6_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD6_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD6_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD6_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD6_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD6_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD6_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD6_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD6_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD6_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD6_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD6_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD7_REG (DR_REG_RTCIO_BASE + 0xA0) +/* RTC_IO_TOUCH_PAD7_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD7_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD7_DRV_M ((RTC_IO_TOUCH_PAD7_DRV_V) << (RTC_IO_TOUCH_PAD7_DRV_S)) +#define RTC_IO_TOUCH_PAD7_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD7_DRV_S 29 +/* RTC_IO_TOUCH_PAD7_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD7_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD7_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RDE_S 28 +/* RTC_IO_TOUCH_PAD7_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD7_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD7_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD7_RUE_S 27 +/* RTC_IO_TOUCH_PAD7_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD7_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD7_DAC_M ((RTC_IO_TOUCH_PAD7_DAC_V) << (RTC_IO_TOUCH_PAD7_DAC_S)) +#define RTC_IO_TOUCH_PAD7_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD7_DAC_S 23 +/* RTC_IO_TOUCH_PAD7_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD7_START (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD7_START_V 0x1 +#define RTC_IO_TOUCH_PAD7_START_S 22 +/* RTC_IO_TOUCH_PAD7_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD7_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD7_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD7_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD7_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD7_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD7_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD7_XPD_S 20 +/* RTC_IO_TOUCH_PAD7_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD7_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD7_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD7_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD7_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_M ((RTC_IO_TOUCH_PAD7_FUN_SEL_V) << (RTC_IO_TOUCH_PAD7_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD7_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD7_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD7_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD7_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD7_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD7_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD7_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD7_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD7_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD7_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD7_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD7_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD7_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD7_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD7_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD7_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD8_REG (DR_REG_RTCIO_BASE + 0xA4) +/* RTC_IO_TOUCH_PAD8_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD8_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD8_DRV_M ((RTC_IO_TOUCH_PAD8_DRV_V) << (RTC_IO_TOUCH_PAD8_DRV_S)) +#define RTC_IO_TOUCH_PAD8_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD8_DRV_S 29 +/* RTC_IO_TOUCH_PAD8_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD8_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD8_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD8_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD8_RDE_S 28 +/* RTC_IO_TOUCH_PAD8_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD8_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD8_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD8_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD8_RUE_S 27 +/* RTC_IO_TOUCH_PAD8_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD8_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD8_DAC_M ((RTC_IO_TOUCH_PAD8_DAC_V) << (RTC_IO_TOUCH_PAD8_DAC_S)) +#define RTC_IO_TOUCH_PAD8_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD8_DAC_S 23 +/* RTC_IO_TOUCH_PAD8_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD8_START (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD8_START_V 0x1 +#define RTC_IO_TOUCH_PAD8_START_S 22 +/* RTC_IO_TOUCH_PAD8_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD8_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD8_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD8_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD8_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD8_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD8_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD8_XPD_S 20 +/* RTC_IO_TOUCH_PAD8_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD8_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD8_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD8_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD8_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD8_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD8_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD8_FUN_SEL_M ((RTC_IO_TOUCH_PAD8_FUN_SEL_V) << (RTC_IO_TOUCH_PAD8_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD8_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD8_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD8_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD8_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD8_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD8_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD8_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD8_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD8_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD8_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD8_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD8_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD8_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD8_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD8_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD8_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD8_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD8_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD8_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD8_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD8_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD8_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD9_REG (DR_REG_RTCIO_BASE + 0xA8) +/* RTC_IO_TOUCH_PAD9_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD9_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD9_DRV_M ((RTC_IO_TOUCH_PAD9_DRV_V) << (RTC_IO_TOUCH_PAD9_DRV_S)) +#define RTC_IO_TOUCH_PAD9_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD9_DRV_S 29 +/* RTC_IO_TOUCH_PAD9_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD9_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD9_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD9_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD9_RDE_S 28 +/* RTC_IO_TOUCH_PAD9_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD9_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD9_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD9_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD9_RUE_S 27 +/* RTC_IO_TOUCH_PAD9_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD9_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD9_DAC_M ((RTC_IO_TOUCH_PAD9_DAC_V) << (RTC_IO_TOUCH_PAD9_DAC_S)) +#define RTC_IO_TOUCH_PAD9_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD9_DAC_S 23 +/* RTC_IO_TOUCH_PAD9_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD9_START (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD9_START_V 0x1 +#define RTC_IO_TOUCH_PAD9_START_S 22 +/* RTC_IO_TOUCH_PAD9_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD9_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD9_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD9_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD9_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD9_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD9_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD9_XPD_S 20 +/* RTC_IO_TOUCH_PAD9_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD9_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD9_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD9_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD9_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD9_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD9_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD9_FUN_SEL_M ((RTC_IO_TOUCH_PAD9_FUN_SEL_V) << (RTC_IO_TOUCH_PAD9_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD9_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD9_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD9_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD9_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD9_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD9_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD9_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD9_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD9_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD9_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD9_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD9_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD9_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD9_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD9_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD9_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD9_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD9_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD9_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD9_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD9_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD9_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD10_REG (DR_REG_RTCIO_BASE + 0xAC) +/* RTC_IO_TOUCH_PAD10_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD10_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD10_DRV_M ((RTC_IO_TOUCH_PAD10_DRV_V) << (RTC_IO_TOUCH_PAD10_DRV_S)) +#define RTC_IO_TOUCH_PAD10_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD10_DRV_S 29 +/* RTC_IO_TOUCH_PAD10_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD10_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD10_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD10_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD10_RDE_S 28 +/* RTC_IO_TOUCH_PAD10_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD10_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD10_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD10_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD10_RUE_S 27 +/* RTC_IO_TOUCH_PAD10_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD10_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD10_DAC_M ((RTC_IO_TOUCH_PAD10_DAC_V) << (RTC_IO_TOUCH_PAD10_DAC_S)) +#define RTC_IO_TOUCH_PAD10_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD10_DAC_S 23 +/* RTC_IO_TOUCH_PAD10_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD10_START (BIT(22)) +#define RTC_IO_TOUCH_PAD10_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD10_START_V 0x1 +#define RTC_IO_TOUCH_PAD10_START_S 22 +/* RTC_IO_TOUCH_PAD10_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD10_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD10_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD10_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD10_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD10_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD10_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD10_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD10_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD10_XPD_S 20 +/* RTC_IO_TOUCH_PAD10_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD10_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD10_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD10_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD10_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD10_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD10_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD10_FUN_SEL_M ((RTC_IO_TOUCH_PAD10_FUN_SEL_V) << (RTC_IO_TOUCH_PAD10_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD10_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD10_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD10_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD10_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD10_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD10_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD10_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD10_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD10_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD10_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD10_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD10_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD10_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD10_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD10_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD10_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD10_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD10_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD10_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD10_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD10_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD10_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD11_REG (DR_REG_RTCIO_BASE + 0xB0) +/* RTC_IO_TOUCH_PAD11_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD11_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD11_DRV_M ((RTC_IO_TOUCH_PAD11_DRV_V) << (RTC_IO_TOUCH_PAD11_DRV_S)) +#define RTC_IO_TOUCH_PAD11_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD11_DRV_S 29 +/* RTC_IO_TOUCH_PAD11_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD11_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD11_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD11_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD11_RDE_S 28 +/* RTC_IO_TOUCH_PAD11_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD11_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD11_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD11_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD11_RUE_S 27 +/* RTC_IO_TOUCH_PAD11_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD11_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD11_DAC_M ((RTC_IO_TOUCH_PAD11_DAC_V) << (RTC_IO_TOUCH_PAD11_DAC_S)) +#define RTC_IO_TOUCH_PAD11_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD11_DAC_S 23 +/* RTC_IO_TOUCH_PAD11_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD11_START (BIT(22)) +#define RTC_IO_TOUCH_PAD11_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD11_START_V 0x1 +#define RTC_IO_TOUCH_PAD11_START_S 22 +/* RTC_IO_TOUCH_PAD11_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD11_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD11_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD11_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD11_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD11_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD11_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD11_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD11_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD11_XPD_S 20 +/* RTC_IO_TOUCH_PAD11_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD11_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD11_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD11_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD11_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD11_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD11_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD11_FUN_SEL_M ((RTC_IO_TOUCH_PAD11_FUN_SEL_V) << (RTC_IO_TOUCH_PAD11_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD11_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD11_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD11_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD11_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD11_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD11_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD11_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD11_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD11_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD11_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD11_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD11_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD11_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD11_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD11_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD11_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD11_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD11_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD11_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD11_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD11_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD11_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD12_REG (DR_REG_RTCIO_BASE + 0xB4) +/* RTC_IO_TOUCH_PAD12_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD12_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD12_DRV_M ((RTC_IO_TOUCH_PAD12_DRV_V) << (RTC_IO_TOUCH_PAD12_DRV_S)) +#define RTC_IO_TOUCH_PAD12_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD12_DRV_S 29 +/* RTC_IO_TOUCH_PAD12_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD12_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD12_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD12_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD12_RDE_S 28 +/* RTC_IO_TOUCH_PAD12_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD12_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD12_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD12_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD12_RUE_S 27 +/* RTC_IO_TOUCH_PAD12_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD12_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD12_DAC_M ((RTC_IO_TOUCH_PAD12_DAC_V) << (RTC_IO_TOUCH_PAD12_DAC_S)) +#define RTC_IO_TOUCH_PAD12_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD12_DAC_S 23 +/* RTC_IO_TOUCH_PAD12_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD12_START (BIT(22)) +#define RTC_IO_TOUCH_PAD12_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD12_START_V 0x1 +#define RTC_IO_TOUCH_PAD12_START_S 22 +/* RTC_IO_TOUCH_PAD12_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD12_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD12_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD12_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD12_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD12_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD12_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD12_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD12_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD12_XPD_S 20 +/* RTC_IO_TOUCH_PAD12_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD12_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD12_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD12_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD12_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD12_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD12_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD12_FUN_SEL_M ((RTC_IO_TOUCH_PAD12_FUN_SEL_V) << (RTC_IO_TOUCH_PAD12_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD12_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD12_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD12_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD12_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD12_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD12_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD12_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD12_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD12_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD12_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD12_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD12_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD12_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD12_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD12_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD12_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD12_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD12_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD12_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD12_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD12_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD12_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD13_REG (DR_REG_RTCIO_BASE + 0xB8) +/* RTC_IO_TOUCH_PAD13_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD13_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD13_DRV_M ((RTC_IO_TOUCH_PAD13_DRV_V) << (RTC_IO_TOUCH_PAD13_DRV_S)) +#define RTC_IO_TOUCH_PAD13_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD13_DRV_S 29 +/* RTC_IO_TOUCH_PAD13_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD13_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD13_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD13_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD13_RDE_S 28 +/* RTC_IO_TOUCH_PAD13_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD13_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD13_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD13_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD13_RUE_S 27 +/* RTC_IO_TOUCH_PAD13_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD13_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD13_DAC_M ((RTC_IO_TOUCH_PAD13_DAC_V) << (RTC_IO_TOUCH_PAD13_DAC_S)) +#define RTC_IO_TOUCH_PAD13_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD13_DAC_S 23 +/* RTC_IO_TOUCH_PAD13_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD13_START (BIT(22)) +#define RTC_IO_TOUCH_PAD13_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD13_START_V 0x1 +#define RTC_IO_TOUCH_PAD13_START_S 22 +/* RTC_IO_TOUCH_PAD13_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD13_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD13_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD13_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD13_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD13_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD13_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD13_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD13_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD13_XPD_S 20 +/* RTC_IO_TOUCH_PAD13_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD13_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD13_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD13_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD13_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD13_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD13_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD13_FUN_SEL_M ((RTC_IO_TOUCH_PAD13_FUN_SEL_V) << (RTC_IO_TOUCH_PAD13_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD13_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD13_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD13_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD13_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD13_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD13_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD13_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD13_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD13_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD13_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD13_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD13_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD13_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD13_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD13_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD13_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD13_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD13_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD13_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD13_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD13_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD13_FUN_IE_S 13 + +#define RTC_IO_TOUCH_PAD14_REG (DR_REG_RTCIO_BASE + 0xBC) +/* RTC_IO_TOUCH_PAD14_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_TOUCH_PAD14_DRV 0x00000003 +#define RTC_IO_TOUCH_PAD14_DRV_M ((RTC_IO_TOUCH_PAD14_DRV_V) << (RTC_IO_TOUCH_PAD14_DRV_S)) +#define RTC_IO_TOUCH_PAD14_DRV_V 0x3 +#define RTC_IO_TOUCH_PAD14_DRV_S 29 +/* RTC_IO_TOUCH_PAD14_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_TOUCH_PAD14_RDE (BIT(28)) +#define RTC_IO_TOUCH_PAD14_RDE_M (BIT(28)) +#define RTC_IO_TOUCH_PAD14_RDE_V 0x1 +#define RTC_IO_TOUCH_PAD14_RDE_S 28 +/* RTC_IO_TOUCH_PAD14_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_TOUCH_PAD14_RUE (BIT(27)) +#define RTC_IO_TOUCH_PAD14_RUE_M (BIT(27)) +#define RTC_IO_TOUCH_PAD14_RUE_V 0x1 +#define RTC_IO_TOUCH_PAD14_RUE_S 27 +/* RTC_IO_TOUCH_PAD14_DAC : R/W ;bitpos:[25:23] ;default: 3'h4 ; */ +/*description: TOUCH_DAC*/ +#define RTC_IO_TOUCH_PAD14_DAC 0x00000007 +#define RTC_IO_TOUCH_PAD14_DAC_M ((RTC_IO_TOUCH_PAD14_DAC_V) << (RTC_IO_TOUCH_PAD14_DAC_S)) +#define RTC_IO_TOUCH_PAD14_DAC_V 0x7 +#define RTC_IO_TOUCH_PAD14_DAC_S 23 +/* RTC_IO_TOUCH_PAD14_START : R/W ;bitpos:[22] ;default: 1'd0 ; */ +/*description: TOUCH_START*/ +#define RTC_IO_TOUCH_PAD14_START (BIT(22)) +#define RTC_IO_TOUCH_PAD14_START_M (BIT(22)) +#define RTC_IO_TOUCH_PAD14_START_V 0x1 +#define RTC_IO_TOUCH_PAD14_START_S 22 +/* RTC_IO_TOUCH_PAD14_TIE_OPT : R/W ;bitpos:[21] ;default: 1'd0 ; */ +/*description: TOUCH_TIE_OPT*/ +#define RTC_IO_TOUCH_PAD14_TIE_OPT (BIT(21)) +#define RTC_IO_TOUCH_PAD14_TIE_OPT_M (BIT(21)) +#define RTC_IO_TOUCH_PAD14_TIE_OPT_V 0x1 +#define RTC_IO_TOUCH_PAD14_TIE_OPT_S 21 +/* RTC_IO_TOUCH_PAD14_XPD : R/W ;bitpos:[20] ;default: 1'd0 ; */ +/*description: TOUCH_XPD*/ +#define RTC_IO_TOUCH_PAD14_XPD (BIT(20)) +#define RTC_IO_TOUCH_PAD14_XPD_M (BIT(20)) +#define RTC_IO_TOUCH_PAD14_XPD_V 0x1 +#define RTC_IO_TOUCH_PAD14_XPD_S 20 +/* RTC_IO_TOUCH_PAD14_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_TOUCH_PAD14_MUX_SEL (BIT(19)) +#define RTC_IO_TOUCH_PAD14_MUX_SEL_M (BIT(19)) +#define RTC_IO_TOUCH_PAD14_MUX_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD14_MUX_SEL_S 19 +/* RTC_IO_TOUCH_PAD14_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_TOUCH_PAD14_FUN_SEL 0x00000003 +#define RTC_IO_TOUCH_PAD14_FUN_SEL_M ((RTC_IO_TOUCH_PAD14_FUN_SEL_V) << (RTC_IO_TOUCH_PAD14_FUN_SEL_S)) +#define RTC_IO_TOUCH_PAD14_FUN_SEL_V 0x3 +#define RTC_IO_TOUCH_PAD14_FUN_SEL_S 17 +/* RTC_IO_TOUCH_PAD14_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_TOUCH_PAD14_SLP_SEL (BIT(16)) +#define RTC_IO_TOUCH_PAD14_SLP_SEL_M (BIT(16)) +#define RTC_IO_TOUCH_PAD14_SLP_SEL_V 0x1 +#define RTC_IO_TOUCH_PAD14_SLP_SEL_S 16 +/* RTC_IO_TOUCH_PAD14_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD14_SLP_IE (BIT(15)) +#define RTC_IO_TOUCH_PAD14_SLP_IE_M (BIT(15)) +#define RTC_IO_TOUCH_PAD14_SLP_IE_V 0x1 +#define RTC_IO_TOUCH_PAD14_SLP_IE_S 15 +/* RTC_IO_TOUCH_PAD14_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_TOUCH_PAD14_SLP_OE (BIT(14)) +#define RTC_IO_TOUCH_PAD14_SLP_OE_M (BIT(14)) +#define RTC_IO_TOUCH_PAD14_SLP_OE_V 0x1 +#define RTC_IO_TOUCH_PAD14_SLP_OE_S 14 +/* RTC_IO_TOUCH_PAD14_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_TOUCH_PAD14_FUN_IE (BIT(13)) +#define RTC_IO_TOUCH_PAD14_FUN_IE_M (BIT(13)) +#define RTC_IO_TOUCH_PAD14_FUN_IE_V 0x1 +#define RTC_IO_TOUCH_PAD14_FUN_IE_S 13 + +#define RTC_IO_XTAL_32P_PAD_REG (DR_REG_RTCIO_BASE + 0xC0) +/* RTC_IO_X32P_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_X32P_DRV 0x00000003 +#define RTC_IO_X32P_DRV_M ((RTC_IO_X32P_DRV_V) << (RTC_IO_X32P_DRV_S)) +#define RTC_IO_X32P_DRV_V 0x3 +#define RTC_IO_X32P_DRV_S 29 +/* RTC_IO_X32P_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_X32P_RDE (BIT(28)) +#define RTC_IO_X32P_RDE_M (BIT(28)) +#define RTC_IO_X32P_RDE_V 0x1 +#define RTC_IO_X32P_RDE_S 28 +/* RTC_IO_X32P_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_X32P_RUE (BIT(27)) +#define RTC_IO_X32P_RUE_M (BIT(27)) +#define RTC_IO_X32P_RUE_V 0x1 +#define RTC_IO_X32P_RUE_S 27 +/* RTC_IO_X32P_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_X32P_MUX_SEL (BIT(19)) +#define RTC_IO_X32P_MUX_SEL_M (BIT(19)) +#define RTC_IO_X32P_MUX_SEL_V 0x1 +#define RTC_IO_X32P_MUX_SEL_S 19 +/* RTC_IO_X32P_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_X32P_FUN_SEL 0x00000003 +#define RTC_IO_X32P_FUN_SEL_M ((RTC_IO_X32P_FUN_SEL_V) << (RTC_IO_X32P_FUN_SEL_S)) +#define RTC_IO_X32P_FUN_SEL_V 0x3 +#define RTC_IO_X32P_FUN_SEL_S 17 +/* RTC_IO_X32P_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_X32P_SLP_SEL (BIT(16)) +#define RTC_IO_X32P_SLP_SEL_M (BIT(16)) +#define RTC_IO_X32P_SLP_SEL_V 0x1 +#define RTC_IO_X32P_SLP_SEL_S 16 +/* RTC_IO_X32P_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_X32P_SLP_IE (BIT(15)) +#define RTC_IO_X32P_SLP_IE_M (BIT(15)) +#define RTC_IO_X32P_SLP_IE_V 0x1 +#define RTC_IO_X32P_SLP_IE_S 15 +/* RTC_IO_X32P_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_X32P_SLP_OE (BIT(14)) +#define RTC_IO_X32P_SLP_OE_M (BIT(14)) +#define RTC_IO_X32P_SLP_OE_V 0x1 +#define RTC_IO_X32P_SLP_OE_S 14 +/* RTC_IO_X32P_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_X32P_FUN_IE (BIT(13)) +#define RTC_IO_X32P_FUN_IE_M (BIT(13)) +#define RTC_IO_X32P_FUN_IE_V 0x1 +#define RTC_IO_X32P_FUN_IE_S 13 + +#define RTC_IO_XTAL_32N_PAD_REG (DR_REG_RTCIO_BASE + 0xC4) +/* RTC_IO_X32N_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_X32N_DRV 0x00000003 +#define RTC_IO_X32N_DRV_M ((RTC_IO_X32N_DRV_V) << (RTC_IO_X32N_DRV_S)) +#define RTC_IO_X32N_DRV_V 0x3 +#define RTC_IO_X32N_DRV_S 29 +/* RTC_IO_X32N_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: RDE*/ +#define RTC_IO_X32N_RDE (BIT(28)) +#define RTC_IO_X32N_RDE_M (BIT(28)) +#define RTC_IO_X32N_RDE_V 0x1 +#define RTC_IO_X32N_RDE_S 28 +/* RTC_IO_X32N_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_X32N_RUE (BIT(27)) +#define RTC_IO_X32N_RUE_M (BIT(27)) +#define RTC_IO_X32N_RUE_V 0x1 +#define RTC_IO_X32N_RUE_S 27 +/* RTC_IO_X32N_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_X32N_MUX_SEL (BIT(19)) +#define RTC_IO_X32N_MUX_SEL_M (BIT(19)) +#define RTC_IO_X32N_MUX_SEL_V 0x1 +#define RTC_IO_X32N_MUX_SEL_S 19 +/* RTC_IO_X32N_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_X32N_FUN_SEL 0x00000003 +#define RTC_IO_X32N_FUN_SEL_M ((RTC_IO_X32N_FUN_SEL_V) << (RTC_IO_X32N_FUN_SEL_S)) +#define RTC_IO_X32N_FUN_SEL_V 0x3 +#define RTC_IO_X32N_FUN_SEL_S 17 +/* RTC_IO_X32N_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_X32N_SLP_SEL (BIT(16)) +#define RTC_IO_X32N_SLP_SEL_M (BIT(16)) +#define RTC_IO_X32N_SLP_SEL_V 0x1 +#define RTC_IO_X32N_SLP_SEL_S 16 +/* RTC_IO_X32N_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_X32N_SLP_IE (BIT(15)) +#define RTC_IO_X32N_SLP_IE_M (BIT(15)) +#define RTC_IO_X32N_SLP_IE_V 0x1 +#define RTC_IO_X32N_SLP_IE_S 15 +/* RTC_IO_X32N_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_X32N_SLP_OE (BIT(14)) +#define RTC_IO_X32N_SLP_OE_M (BIT(14)) +#define RTC_IO_X32N_SLP_OE_V 0x1 +#define RTC_IO_X32N_SLP_OE_S 14 +/* RTC_IO_X32N_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_X32N_FUN_IE (BIT(13)) +#define RTC_IO_X32N_FUN_IE_M (BIT(13)) +#define RTC_IO_X32N_FUN_IE_V 0x1 +#define RTC_IO_X32N_FUN_IE_S 13 + +#define RTC_IO_PAD_DAC1_REG (DR_REG_RTCIO_BASE + 0xC8) +/* RTC_IO_PDAC1_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: PDAC1_DRV*/ +#define RTC_IO_PDAC1_DRV 0x00000003 +#define RTC_IO_PDAC1_DRV_M ((RTC_IO_PDAC1_DRV_V) << (RTC_IO_PDAC1_DRV_S)) +#define RTC_IO_PDAC1_DRV_V 0x3 +#define RTC_IO_PDAC1_DRV_S 29 +/* RTC_IO_PDAC1_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: PDAC1_RDE*/ +#define RTC_IO_PDAC1_RDE (BIT(28)) +#define RTC_IO_PDAC1_RDE_M (BIT(28)) +#define RTC_IO_PDAC1_RDE_V 0x1 +#define RTC_IO_PDAC1_RDE_S 28 +/* RTC_IO_PDAC1_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: PDAC1_RUE*/ +#define RTC_IO_PDAC1_RUE (BIT(27)) +#define RTC_IO_PDAC1_RUE_M (BIT(27)) +#define RTC_IO_PDAC1_RUE_V 0x1 +#define RTC_IO_PDAC1_RUE_S 27 +/* RTC_IO_PDAC1_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_PDAC1_MUX_SEL (BIT(19)) +#define RTC_IO_PDAC1_MUX_SEL_M (BIT(19)) +#define RTC_IO_PDAC1_MUX_SEL_V 0x1 +#define RTC_IO_PDAC1_MUX_SEL_S 19 +/* RTC_IO_PDAC1_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: PDAC1 function sel*/ +#define RTC_IO_PDAC1_FUN_SEL 0x00000003 +#define RTC_IO_PDAC1_FUN_SEL_M ((RTC_IO_PDAC1_FUN_SEL_V) << (RTC_IO_PDAC1_FUN_SEL_S)) +#define RTC_IO_PDAC1_FUN_SEL_V 0x3 +#define RTC_IO_PDAC1_FUN_SEL_S 17 +/* RTC_IO_PDAC1_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_PDAC1_SLP_SEL (BIT(16)) +#define RTC_IO_PDAC1_SLP_SEL_M (BIT(16)) +#define RTC_IO_PDAC1_SLP_SEL_V 0x1 +#define RTC_IO_PDAC1_SLP_SEL_S 16 +/* RTC_IO_PDAC1_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_PDAC1_SLP_IE (BIT(15)) +#define RTC_IO_PDAC1_SLP_IE_M (BIT(15)) +#define RTC_IO_PDAC1_SLP_IE_V 0x1 +#define RTC_IO_PDAC1_SLP_IE_S 15 +/* RTC_IO_PDAC1_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_PDAC1_SLP_OE (BIT(14)) +#define RTC_IO_PDAC1_SLP_OE_M (BIT(14)) +#define RTC_IO_PDAC1_SLP_OE_V 0x1 +#define RTC_IO_PDAC1_SLP_OE_S 14 +/* RTC_IO_PDAC1_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_PDAC1_FUN_IE (BIT(13)) +#define RTC_IO_PDAC1_FUN_IE_M (BIT(13)) +#define RTC_IO_PDAC1_FUN_IE_V 0x1 +#define RTC_IO_PDAC1_FUN_IE_S 13 +/* RTC_IO_PDAC1_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: 1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR + ADC FSM to control PDAC1_XPD_DAC*/ +#define RTC_IO_PDAC1_DAC_XPD_FORCE (BIT(12)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_M (BIT(12)) +#define RTC_IO_PDAC1_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC1_DAC_XPD_FORCE_S 12 +/* RTC_IO_PDAC1_XPD_DAC : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: PDAC1_XPD_DAC*/ +#define RTC_IO_PDAC1_XPD_DAC (BIT(11)) +#define RTC_IO_PDAC1_XPD_DAC_M (BIT(11)) +#define RTC_IO_PDAC1_XPD_DAC_V 0x1 +#define RTC_IO_PDAC1_XPD_DAC_S 11 +/* RTC_IO_PDAC1_DAC : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: PDAC1_DAC*/ +#define RTC_IO_PDAC1_DAC 0x000000FF +#define RTC_IO_PDAC1_DAC_M ((RTC_IO_PDAC1_DAC_V) << (RTC_IO_PDAC1_DAC_S)) +#define RTC_IO_PDAC1_DAC_V 0xFF +#define RTC_IO_PDAC1_DAC_S 3 + +#define RTC_IO_PAD_DAC2_REG (DR_REG_RTCIO_BASE + 0xCC) +/* RTC_IO_PDAC2_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: PDAC2_DRV*/ +#define RTC_IO_PDAC2_DRV 0x00000003 +#define RTC_IO_PDAC2_DRV_M ((RTC_IO_PDAC2_DRV_V) << (RTC_IO_PDAC2_DRV_S)) +#define RTC_IO_PDAC2_DRV_V 0x3 +#define RTC_IO_PDAC2_DRV_S 29 +/* RTC_IO_PDAC2_RDE : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: PDAC2_RDE*/ +#define RTC_IO_PDAC2_RDE (BIT(28)) +#define RTC_IO_PDAC2_RDE_M (BIT(28)) +#define RTC_IO_PDAC2_RDE_V 0x1 +#define RTC_IO_PDAC2_RDE_S 28 +/* RTC_IO_PDAC2_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: PDAC2_RUE*/ +#define RTC_IO_PDAC2_RUE (BIT(27)) +#define RTC_IO_PDAC2_RUE_M (BIT(27)) +#define RTC_IO_PDAC2_RUE_V 0x1 +#define RTC_IO_PDAC2_RUE_S 27 +/* RTC_IO_PDAC2_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_PDAC2_MUX_SEL (BIT(19)) +#define RTC_IO_PDAC2_MUX_SEL_M (BIT(19)) +#define RTC_IO_PDAC2_MUX_SEL_V 0x1 +#define RTC_IO_PDAC2_MUX_SEL_S 19 +/* RTC_IO_PDAC2_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: PDAC1 function sel*/ +#define RTC_IO_PDAC2_FUN_SEL 0x00000003 +#define RTC_IO_PDAC2_FUN_SEL_M ((RTC_IO_PDAC2_FUN_SEL_V) << (RTC_IO_PDAC2_FUN_SEL_S)) +#define RTC_IO_PDAC2_FUN_SEL_V 0x3 +#define RTC_IO_PDAC2_FUN_SEL_S 17 +/* RTC_IO_PDAC2_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_PDAC2_SLP_SEL (BIT(16)) +#define RTC_IO_PDAC2_SLP_SEL_M (BIT(16)) +#define RTC_IO_PDAC2_SLP_SEL_V 0x1 +#define RTC_IO_PDAC2_SLP_SEL_S 16 +/* RTC_IO_PDAC2_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_PDAC2_SLP_IE (BIT(15)) +#define RTC_IO_PDAC2_SLP_IE_M (BIT(15)) +#define RTC_IO_PDAC2_SLP_IE_V 0x1 +#define RTC_IO_PDAC2_SLP_IE_S 15 +/* RTC_IO_PDAC2_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_PDAC2_SLP_OE (BIT(14)) +#define RTC_IO_PDAC2_SLP_OE_M (BIT(14)) +#define RTC_IO_PDAC2_SLP_OE_V 0x1 +#define RTC_IO_PDAC2_SLP_OE_S 14 +/* RTC_IO_PDAC2_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_PDAC2_FUN_IE (BIT(13)) +#define RTC_IO_PDAC2_FUN_IE_M (BIT(13)) +#define RTC_IO_PDAC2_FUN_IE_V 0x1 +#define RTC_IO_PDAC2_FUN_IE_S 13 +/* RTC_IO_PDAC2_DAC_XPD_FORCE : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: 1: use reg_pdac2_xpd_dac to control PDAC2_XPD_DAC 0: use SAR + ADC FSM to control PDAC2_XPD_DAC*/ +#define RTC_IO_PDAC2_DAC_XPD_FORCE (BIT(12)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_M (BIT(12)) +#define RTC_IO_PDAC2_DAC_XPD_FORCE_V 0x1 +#define RTC_IO_PDAC2_DAC_XPD_FORCE_S 12 +/* RTC_IO_PDAC2_XPD_DAC : R/W ;bitpos:[11] ;default: 1'd0 ; */ +/*description: PDAC2_XPD_DAC*/ +#define RTC_IO_PDAC2_XPD_DAC (BIT(11)) +#define RTC_IO_PDAC2_XPD_DAC_M (BIT(11)) +#define RTC_IO_PDAC2_XPD_DAC_V 0x1 +#define RTC_IO_PDAC2_XPD_DAC_S 11 +/* RTC_IO_PDAC2_DAC : R/W ;bitpos:[10:3] ;default: 8'd0 ; */ +/*description: PDAC2_DAC*/ +#define RTC_IO_PDAC2_DAC 0x000000FF +#define RTC_IO_PDAC2_DAC_M ((RTC_IO_PDAC2_DAC_V) << (RTC_IO_PDAC2_DAC_S)) +#define RTC_IO_PDAC2_DAC_V 0xFF +#define RTC_IO_PDAC2_DAC_S 3 + +#define RTC_IO_RTC_PAD19_REG (DR_REG_RTCIO_BASE + 0xD0) +/* RTC_IO_PAD19_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_PAD19_DRV 0x00000003 +#define RTC_IO_PAD19_DRV_M ((RTC_IO_PAD19_DRV_V) << (RTC_IO_PAD19_DRV_S)) +#define RTC_IO_PAD19_DRV_V 0x3 +#define RTC_IO_PAD19_DRV_S 29 +/* RTC_IO_PAD19_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: RDE*/ +#define RTC_IO_PAD19_RDE (BIT(28)) +#define RTC_IO_PAD19_RDE_M (BIT(28)) +#define RTC_IO_PAD19_RDE_V 0x1 +#define RTC_IO_PAD19_RDE_S 28 +/* RTC_IO_PAD19_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_PAD19_RUE (BIT(27)) +#define RTC_IO_PAD19_RUE_M (BIT(27)) +#define RTC_IO_PAD19_RUE_V 0x1 +#define RTC_IO_PAD19_RUE_S 27 +/* RTC_IO_PAD19_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_PAD19_MUX_SEL (BIT(19)) +#define RTC_IO_PAD19_MUX_SEL_M (BIT(19)) +#define RTC_IO_PAD19_MUX_SEL_V 0x1 +#define RTC_IO_PAD19_MUX_SEL_S 19 +/* RTC_IO_PAD19_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_PAD19_FUN_SEL 0x00000003 +#define RTC_IO_PAD19_FUN_SEL_M ((RTC_IO_PAD19_FUN_SEL_V) << (RTC_IO_PAD19_FUN_SEL_S)) +#define RTC_IO_PAD19_FUN_SEL_V 0x3 +#define RTC_IO_PAD19_FUN_SEL_S 17 +/* RTC_IO_PAD19_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_PAD19_SLP_SEL (BIT(16)) +#define RTC_IO_PAD19_SLP_SEL_M (BIT(16)) +#define RTC_IO_PAD19_SLP_SEL_V 0x1 +#define RTC_IO_PAD19_SLP_SEL_S 16 +/* RTC_IO_PAD19_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_PAD19_SLP_IE (BIT(15)) +#define RTC_IO_PAD19_SLP_IE_M (BIT(15)) +#define RTC_IO_PAD19_SLP_IE_V 0x1 +#define RTC_IO_PAD19_SLP_IE_S 15 +/* RTC_IO_PAD19_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_PAD19_SLP_OE (BIT(14)) +#define RTC_IO_PAD19_SLP_OE_M (BIT(14)) +#define RTC_IO_PAD19_SLP_OE_V 0x1 +#define RTC_IO_PAD19_SLP_OE_S 14 +/* RTC_IO_PAD19_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_PAD19_FUN_IE (BIT(13)) +#define RTC_IO_PAD19_FUN_IE_M (BIT(13)) +#define RTC_IO_PAD19_FUN_IE_V 0x1 +#define RTC_IO_PAD19_FUN_IE_S 13 + +#define RTC_IO_RTC_PAD20_REG (DR_REG_RTCIO_BASE + 0xD4) +/* RTC_IO_PAD20_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_PAD20_DRV 0x00000003 +#define RTC_IO_PAD20_DRV_M ((RTC_IO_PAD20_DRV_V) << (RTC_IO_PAD20_DRV_S)) +#define RTC_IO_PAD20_DRV_V 0x3 +#define RTC_IO_PAD20_DRV_S 29 +/* RTC_IO_PAD20_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: RDE*/ +#define RTC_IO_PAD20_RDE (BIT(28)) +#define RTC_IO_PAD20_RDE_M (BIT(28)) +#define RTC_IO_PAD20_RDE_V 0x1 +#define RTC_IO_PAD20_RDE_S 28 +/* RTC_IO_PAD20_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_PAD20_RUE (BIT(27)) +#define RTC_IO_PAD20_RUE_M (BIT(27)) +#define RTC_IO_PAD20_RUE_V 0x1 +#define RTC_IO_PAD20_RUE_S 27 +/* RTC_IO_PAD20_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_PAD20_MUX_SEL (BIT(19)) +#define RTC_IO_PAD20_MUX_SEL_M (BIT(19)) +#define RTC_IO_PAD20_MUX_SEL_V 0x1 +#define RTC_IO_PAD20_MUX_SEL_S 19 +/* RTC_IO_PAD20_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_PAD20_FUN_SEL 0x00000003 +#define RTC_IO_PAD20_FUN_SEL_M ((RTC_IO_PAD20_FUN_SEL_V) << (RTC_IO_PAD20_FUN_SEL_S)) +#define RTC_IO_PAD20_FUN_SEL_V 0x3 +#define RTC_IO_PAD20_FUN_SEL_S 17 +/* RTC_IO_PAD20_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_PAD20_SLP_SEL (BIT(16)) +#define RTC_IO_PAD20_SLP_SEL_M (BIT(16)) +#define RTC_IO_PAD20_SLP_SEL_V 0x1 +#define RTC_IO_PAD20_SLP_SEL_S 16 +/* RTC_IO_PAD20_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_PAD20_SLP_IE (BIT(15)) +#define RTC_IO_PAD20_SLP_IE_M (BIT(15)) +#define RTC_IO_PAD20_SLP_IE_V 0x1 +#define RTC_IO_PAD20_SLP_IE_S 15 +/* RTC_IO_PAD20_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_PAD20_SLP_OE (BIT(14)) +#define RTC_IO_PAD20_SLP_OE_M (BIT(14)) +#define RTC_IO_PAD20_SLP_OE_V 0x1 +#define RTC_IO_PAD20_SLP_OE_S 14 +/* RTC_IO_PAD20_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_PAD20_FUN_IE (BIT(13)) +#define RTC_IO_PAD20_FUN_IE_M (BIT(13)) +#define RTC_IO_PAD20_FUN_IE_V 0x1 +#define RTC_IO_PAD20_FUN_IE_S 13 + +#define RTC_IO_RTC_PAD21_REG (DR_REG_RTCIO_BASE + 0xD8) +/* RTC_IO_PAD21_DRV : R/W ;bitpos:[30:29] ;default: 2'd2 ; */ +/*description: DRV*/ +#define RTC_IO_PAD21_DRV 0x00000003 +#define RTC_IO_PAD21_DRV_M ((RTC_IO_PAD21_DRV_V) << (RTC_IO_PAD21_DRV_S)) +#define RTC_IO_PAD21_DRV_V 0x3 +#define RTC_IO_PAD21_DRV_S 29 +/* RTC_IO_PAD21_RDE : R/W ;bitpos:[28] ;default: 1'd1 ; */ +/*description: RDE*/ +#define RTC_IO_PAD21_RDE (BIT(28)) +#define RTC_IO_PAD21_RDE_M (BIT(28)) +#define RTC_IO_PAD21_RDE_V 0x1 +#define RTC_IO_PAD21_RDE_S 28 +/* RTC_IO_PAD21_RUE : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: RUE*/ +#define RTC_IO_PAD21_RUE (BIT(27)) +#define RTC_IO_PAD21_RUE_M (BIT(27)) +#define RTC_IO_PAD21_RUE_V 0x1 +#define RTC_IO_PAD21_RUE_S 27 +/* RTC_IO_PAD21_MUX_SEL : R/W ;bitpos:[19] ;default: 1'd0 ; */ +/*description: 1: use RTC GPIO 0: use digital GPIO*/ +#define RTC_IO_PAD21_MUX_SEL (BIT(19)) +#define RTC_IO_PAD21_MUX_SEL_M (BIT(19)) +#define RTC_IO_PAD21_MUX_SEL_V 0x1 +#define RTC_IO_PAD21_MUX_SEL_S 19 +/* RTC_IO_PAD21_FUN_SEL : R/W ;bitpos:[18:17] ;default: 2'd0 ; */ +/*description: function sel*/ +#define RTC_IO_PAD21_FUN_SEL 0x00000003 +#define RTC_IO_PAD21_FUN_SEL_M ((RTC_IO_PAD21_FUN_SEL_V) << (RTC_IO_PAD21_FUN_SEL_S)) +#define RTC_IO_PAD21_FUN_SEL_V 0x3 +#define RTC_IO_PAD21_FUN_SEL_S 17 +/* RTC_IO_PAD21_SLP_SEL : R/W ;bitpos:[16] ;default: 1'd0 ; */ +/*description: 1: enable sleep mode during sleep 0: no sleep mode*/ +#define RTC_IO_PAD21_SLP_SEL (BIT(16)) +#define RTC_IO_PAD21_SLP_SEL_M (BIT(16)) +#define RTC_IO_PAD21_SLP_SEL_V 0x1 +#define RTC_IO_PAD21_SLP_SEL_S 16 +/* RTC_IO_PAD21_SLP_IE : R/W ;bitpos:[15] ;default: 1'd0 ; */ +/*description: input enable in sleep mode*/ +#define RTC_IO_PAD21_SLP_IE (BIT(15)) +#define RTC_IO_PAD21_SLP_IE_M (BIT(15)) +#define RTC_IO_PAD21_SLP_IE_V 0x1 +#define RTC_IO_PAD21_SLP_IE_S 15 +/* RTC_IO_PAD21_SLP_OE : R/W ;bitpos:[14] ;default: 1'd0 ; */ +/*description: output enable in sleep mode*/ +#define RTC_IO_PAD21_SLP_OE (BIT(14)) +#define RTC_IO_PAD21_SLP_OE_M (BIT(14)) +#define RTC_IO_PAD21_SLP_OE_V 0x1 +#define RTC_IO_PAD21_SLP_OE_S 14 +/* RTC_IO_PAD21_FUN_IE : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: input enable in work mode*/ +#define RTC_IO_PAD21_FUN_IE (BIT(13)) +#define RTC_IO_PAD21_FUN_IE_M (BIT(13)) +#define RTC_IO_PAD21_FUN_IE_V 0x1 +#define RTC_IO_PAD21_FUN_IE_S 13 + +#define RTC_IO_EXT_WAKEUP0_REG (DR_REG_RTCIO_BASE + 0xDC) +/* RTC_IO_EXT_WAKEUP0_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: */ +#define RTC_IO_EXT_WAKEUP0_SEL 0x0000001F +#define RTC_IO_EXT_WAKEUP0_SEL_M ((RTC_IO_EXT_WAKEUP0_SEL_V) << (RTC_IO_EXT_WAKEUP0_SEL_S)) +#define RTC_IO_EXT_WAKEUP0_SEL_V 0x1F +#define RTC_IO_EXT_WAKEUP0_SEL_S 27 + +#define RTC_IO_XTL_EXT_CTR_REG (DR_REG_RTCIO_BASE + 0xE0) +/* RTC_IO_XTL_EXT_CTR_SEL : R/W ;bitpos:[31:27] ;default: 5'd0 ; */ +/*description: select RTC GPIO 0 ~ 17 to control XTAL*/ +#define RTC_IO_XTL_EXT_CTR_SEL 0x0000001F +#define RTC_IO_XTL_EXT_CTR_SEL_M ((RTC_IO_XTL_EXT_CTR_SEL_V) << (RTC_IO_XTL_EXT_CTR_SEL_S)) +#define RTC_IO_XTL_EXT_CTR_SEL_V 0x1F +#define RTC_IO_XTL_EXT_CTR_SEL_S 27 + +#define RTC_IO_SAR_I2C_IO_REG (DR_REG_RTCIO_BASE + 0xE4) +/* RTC_IO_SAR_I2C_SDA_SEL : R/W ;bitpos:[31:30] ;default: 2'd0 ; */ +/*description: */ +#define RTC_IO_SAR_I2C_SDA_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SDA_SEL_M ((RTC_IO_SAR_I2C_SDA_SEL_V) << (RTC_IO_SAR_I2C_SDA_SEL_S)) +#define RTC_IO_SAR_I2C_SDA_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SDA_SEL_S 30 +/* RTC_IO_SAR_I2C_SCL_SEL : R/W ;bitpos:[29:28] ;default: 2'd0 ; */ +/*description: */ +#define RTC_IO_SAR_I2C_SCL_SEL 0x00000003 +#define RTC_IO_SAR_I2C_SCL_SEL_M ((RTC_IO_SAR_I2C_SCL_SEL_V) << (RTC_IO_SAR_I2C_SCL_SEL_S)) +#define RTC_IO_SAR_I2C_SCL_SEL_V 0x3 +#define RTC_IO_SAR_I2C_SCL_SEL_S 28 +/* RTC_IO_SAR_DEBUG_BIT_SEL : R/W ;bitpos:[27:23] ;default: 5'h0 ; */ +/*description: */ +#define RTC_IO_SAR_DEBUG_BIT_SEL 0x0000001F +#define RTC_IO_SAR_DEBUG_BIT_SEL_M ((RTC_IO_SAR_DEBUG_BIT_SEL_V) << (RTC_IO_SAR_DEBUG_BIT_SEL_S)) +#define RTC_IO_SAR_DEBUG_BIT_SEL_V 0x1F +#define RTC_IO_SAR_DEBUG_BIT_SEL_S 23 + +#define RTC_IO_TOUCH_CTRL_REG (DR_REG_RTCIO_BASE + 0xE8) +/* RTC_IO_IO_TOUCH_BUFMODE : R/W ;bitpos:[4] ;default: 1'd0 ; */ +/*description: BUF_MODE when touch work without fsm*/ +#define RTC_IO_IO_TOUCH_BUFMODE (BIT(4)) +#define RTC_IO_IO_TOUCH_BUFMODE_M (BIT(4)) +#define RTC_IO_IO_TOUCH_BUFMODE_V 0x1 +#define RTC_IO_IO_TOUCH_BUFMODE_S 4 +/* RTC_IO_IO_TOUCH_BUFSEL : R/W ;bitpos:[3:0] ;default: 4'd0 ; */ +/*description: BUF_SEL when touch work without fsm*/ +#define RTC_IO_IO_TOUCH_BUFSEL 0x0000000F +#define RTC_IO_IO_TOUCH_BUFSEL_M ((RTC_IO_IO_TOUCH_BUFSEL_V) << (RTC_IO_IO_TOUCH_BUFSEL_S)) +#define RTC_IO_IO_TOUCH_BUFSEL_V 0xF +#define RTC_IO_IO_TOUCH_BUFSEL_S 0 + +#define RTC_IO_DATE_REG (DR_REG_RTCIO_BASE + 0x1FC) +/* RTC_IO_IO_DATE : R/W ;bitpos:[27:0] ;default: 28'h1903170 ; */ +/*description: */ +#define RTC_IO_IO_DATE 0x0FFFFFFF +#define RTC_IO_IO_DATE_M ((RTC_IO_IO_DATE_V) << (RTC_IO_IO_DATE_S)) +#define RTC_IO_IO_DATE_V 0xFFFFFFF +#define RTC_IO_IO_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/rtc_io_struct.h b/components/soc/soc/esp32s3/include/soc/rtc_io_struct.h new file mode 100644 index 000000000..70d2e24c0 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/rtc_io_struct.h @@ -0,0 +1,354 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t reserved0: 10; + uint32_t data: 22; /*RTC GPIO 0 ~ 21 output data*/ + }; + uint32_t val; + } out; + union { + struct { + uint32_t reserved0: 10; + uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 output data write 1 to set*/ + }; + uint32_t val; + } out_w1ts; + union { + struct { + uint32_t reserved0: 10; + uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 output data write 1 to clear*/ + }; + uint32_t val; + } out_w1tc; + union { + struct { + uint32_t reserved0: 10; + uint32_t enable: 22; /*RTC GPIO 0 ~ 21 enable*/ + }; + uint32_t val; + } enable; + union { + struct { + uint32_t reserved0: 10; + uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 enable write 1 to set*/ + }; + uint32_t val; + } enable_w1ts; + union { + struct { + uint32_t reserved0: 10; + uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 enable write 1 to clear*/ + }; + uint32_t val; + } enable_w1tc; + union { + struct { + uint32_t reserved0: 10; + uint32_t status: 22; /*RTC GPIO 0 ~ 21 interrupt status*/ + }; + uint32_t val; + } status; + union { + struct { + uint32_t reserved0: 10; + uint32_t w1ts: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to set*/ + }; + uint32_t val; + } status_w1ts; + union { + struct { + uint32_t reserved0: 10; + uint32_t w1tc: 22; /*RTC GPIO 0 ~ 21 interrupt status write 1 to clear*/ + }; + uint32_t val; + } status_w1tc; + union { + struct { + uint32_t reserved0: 10; + uint32_t in: 22; /*RTC GPIO input data*/ + }; + uint32_t val; + } in_val; + union { + struct { + uint32_t reserved0: 2; + uint32_t pad_driver: 1; /*if set to 0: normal output if set to 1: open drain*/ + uint32_t reserved3: 4; + uint32_t int_type: 3; /*if set to 0: GPIO interrupt disable if set to 1: rising edge trigger if set to 2: falling edge trigger if set to 3: any edge trigger if set to 4: low level trigger if set to 5: high level trigger*/ + uint32_t wakeup_enable: 1; /*RTC GPIO wakeup enable bit*/ + uint32_t reserved11: 21; + }; + uint32_t val; + } pin[22]; + union { + struct { + uint32_t sel0: 5; + uint32_t sel1: 5; + uint32_t sel2: 5; + uint32_t sel3: 5; + uint32_t sel4: 5; + uint32_t no_gating_12m: 1; + uint32_t reserved26: 6; + }; + uint32_t val; + } debug_sel; + union { + struct { + uint32_t reserved0: 13; + uint32_t fun_ie: 1; /*input enable in work mode*/ + uint32_t slp_oe: 1; /*output enable in sleep mode*/ + uint32_t slp_ie: 1; /*input enable in sleep mode*/ + uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ + uint32_t fun_sel: 2; /*function sel*/ + uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ + uint32_t xpd: 1; /*TOUCH_XPD*/ + uint32_t tie_opt: 1; /*TOUCH_TIE_OPT*/ + uint32_t start: 1; /*TOUCH_START*/ + uint32_t dac: 3; /*TOUCH_DAC*/ + uint32_t reserved26: 1; + uint32_t rue: 1; /*RUE*/ + uint32_t rde: 1; /*RDE*/ + uint32_t drv: 2; /*DRV*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } touch_pad[15]; + union { + struct { + uint32_t reserved0: 13; + uint32_t x32p_fun_ie: 1; /*input enable in work mode*/ + uint32_t x32p_slp_oe: 1; /*output enable in sleep mode*/ + uint32_t x32p_slp_ie: 1; /*input enable in sleep mode*/ + uint32_t x32p_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ + uint32_t x32p_fun_sel: 2; /*function sel*/ + uint32_t x32p_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ + uint32_t reserved20: 7; + uint32_t x32p_rue: 1; /*RUE*/ + uint32_t x32p_rde: 1; /*RDE*/ + uint32_t x32p_drv: 2; /*DRV*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } xtal_32p_pad; + union { + struct { + uint32_t reserved0: 13; + uint32_t x32n_fun_ie: 1; /*input enable in work mode*/ + uint32_t x32n_slp_oe: 1; /*output enable in sleep mode*/ + uint32_t x32n_slp_ie: 1; /*input enable in sleep mode*/ + uint32_t x32n_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ + uint32_t x32n_fun_sel: 2; /*function sel*/ + uint32_t x32n_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ + uint32_t reserved20: 7; + uint32_t x32n_rue: 1; /*RUE*/ + uint32_t x32n_rde: 1; /*RDE*/ + uint32_t x32n_drv: 2; /*DRV*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } xtal_32n_pad; + union { + struct { + uint32_t reserved0: 3; + uint32_t dac: 8; /*PDAC1_DAC*/ + uint32_t xpd_dac: 1; /*PDAC1_XPD_DAC*/ + uint32_t dac_xpd_force: 1; /*1: use reg_pdac1_xpd_dac to control PDAC1_XPD_DAC 0: use SAR ADC FSM to control PDAC1_XPD_DAC*/ + uint32_t fun_ie: 1; /*input enable in work mode*/ + uint32_t slp_oe: 1; /*output enable in sleep mode*/ + uint32_t slp_ie: 1; /*input enable in sleep mode*/ + uint32_t slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ + uint32_t fun_sel: 2; /*PDAC1 function sel*/ + uint32_t mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ + uint32_t reserved20: 7; + uint32_t rue: 1; /*PDAC1_RUE*/ + uint32_t rde: 1; /*PDAC1_RDE*/ + uint32_t drv: 2; /*PDAC1_DRV*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } pad_dac[2]; + union { + struct { + uint32_t reserved0: 13; + uint32_t rtc_pad19_fun_ie: 1; /*input enable in work mode*/ + uint32_t rtc_pad19_slp_oe: 1; /*output enable in sleep mode*/ + uint32_t rtc_pad19_slp_ie: 1; /*input enable in sleep mode*/ + uint32_t rtc_pad19_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ + uint32_t rtc_pad19_fun_sel: 2; /*function sel*/ + uint32_t rtc_pad19_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ + uint32_t reserved20: 7; + uint32_t rtc_pad19_rue: 1; /*RUE*/ + uint32_t rtc_pad19_rde: 1; /*RDE*/ + uint32_t rtc_pad19_drv: 2; /*DRV*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } rtc_pad19; + union { + struct { + uint32_t reserved0: 13; + uint32_t rtc_pad20_fun_ie: 1; /*input enable in work mode*/ + uint32_t rtc_pad20_slp_oe: 1; /*output enable in sleep mode*/ + uint32_t rtc_pad20_slp_ie: 1; /*input enable in sleep mode*/ + uint32_t rtc_pad20_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ + uint32_t rtc_pad20_fun_sel: 2; /*function sel*/ + uint32_t rtc_pad20_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ + uint32_t reserved20: 7; + uint32_t rtc_pad20_rue: 1; /*RUE*/ + uint32_t rtc_pad20_rde: 1; /*RDE*/ + uint32_t rtc_pad20_drv: 2; /*DRV*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } rtc_pad20; + union { + struct { + uint32_t reserved0: 13; + uint32_t rtc_pad21_fun_ie: 1; /*input enable in work mode*/ + uint32_t rtc_pad21_slp_oe: 1; /*output enable in sleep mode*/ + uint32_t rtc_pad21_slp_ie: 1; /*input enable in sleep mode*/ + uint32_t rtc_pad21_slp_sel: 1; /*1: enable sleep mode during sleep 0: no sleep mode*/ + uint32_t rtc_pad21_fun_sel: 2; /*function sel*/ + uint32_t rtc_pad21_mux_sel: 1; /*1: use RTC GPIO 0: use digital GPIO*/ + uint32_t reserved20: 7; + uint32_t rtc_pad21_rue: 1; /*RUE*/ + uint32_t rtc_pad21_rde: 1; /*RDE*/ + uint32_t rtc_pad21_drv: 2; /*DRV*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } rtc_pad21; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; + }; + uint32_t val; + } ext_wakeup0; + union { + struct { + uint32_t reserved0: 27; + uint32_t sel: 5; /*select RTC GPIO 0 ~ 17 to control XTAL*/ + }; + uint32_t val; + } xtl_ext_ctr; + union { + struct { + uint32_t reserved0: 23; + uint32_t debug_bit_sel: 5; + uint32_t scl_sel: 2; + uint32_t sda_sel: 2; + }; + uint32_t val; + } sar_i2c_io; + union { + struct { + uint32_t io_touch_bufsel: 4; /*BUF_SEL when touch work without fsm*/ + uint32_t io_touch_bufmode: 1; /*BUF_MODE when touch work without fsm*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } touch_ctrl; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} rtc_io_dev_t; + +extern rtc_io_dev_t RTCIO; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sdmmc_reg.h b/components/soc/soc/esp32s3/include/soc/sdmmc_reg.h new file mode 100644 index 000000000..41c191eb6 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sdmmc_reg.h @@ -0,0 +1,94 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include "soc.h" + +#define SDMMC_CTRL_REG (DR_REG_SDMMC_BASE + 0x00) +#define SDMMC_PWREN_REG (DR_REG_SDMMC_BASE + 0x04) +#define SDMMC_CLKDIV_REG (DR_REG_SDMMC_BASE + 0x08) +#define SDMMC_CLKSRC_REG (DR_REG_SDMMC_BASE + 0x0c) +#define SDMMC_CLKENA_REG (DR_REG_SDMMC_BASE + 0x10) +#define SDMMC_TMOUT_REG (DR_REG_SDMMC_BASE + 0x14) +#define SDMMC_CTYPE_REG (DR_REG_SDMMC_BASE + 0x18) +#define SDMMC_BLKSIZ_REG (DR_REG_SDMMC_BASE + 0x1c) +#define SDMMC_BYTCNT_REG (DR_REG_SDMMC_BASE + 0x20) +#define SDMMC_INTMASK_REG (DR_REG_SDMMC_BASE + 0x24) +#define SDMMC_CMDARG_REG (DR_REG_SDMMC_BASE + 0x28) +#define SDMMC_CMD_REG (DR_REG_SDMMC_BASE + 0x2c) +#define SDMMC_RESP0_REG (DR_REG_SDMMC_BASE + 0x30) +#define SDMMC_RESP1_REG (DR_REG_SDMMC_BASE + 0x34) +#define SDMMC_RESP2_REG (DR_REG_SDMMC_BASE + 0x38) +#define SDMMC_RESP3_REG (DR_REG_SDMMC_BASE + 0x3c) + +#define SDMMC_MINTSTS_REG (DR_REG_SDMMC_BASE + 0x40) +#define SDMMC_RINTSTS_REG (DR_REG_SDMMC_BASE + 0x44) +#define SDMMC_STATUS_REG (DR_REG_SDMMC_BASE + 0x48) +#define SDMMC_FIFOTH_REG (DR_REG_SDMMC_BASE + 0x4c) +#define SDMMC_CDETECT_REG (DR_REG_SDMMC_BASE + 0x50) +#define SDMMC_WRTPRT_REG (DR_REG_SDMMC_BASE + 0x54) +#define SDMMC_GPIO_REG (DR_REG_SDMMC_BASE + 0x58) +#define SDMMC_TCBCNT_REG (DR_REG_SDMMC_BASE + 0x5c) +#define SDMMC_TBBCNT_REG (DR_REG_SDMMC_BASE + 0x60) +#define SDMMC_DEBNCE_REG (DR_REG_SDMMC_BASE + 0x64) +#define SDMMC_USRID_REG (DR_REG_SDMMC_BASE + 0x68) +#define SDMMC_VERID_REG (DR_REG_SDMMC_BASE + 0x6c) +#define SDMMC_HCON_REG (DR_REG_SDMMC_BASE + 0x70) +#define SDMMC_UHS_REG_REG (DR_REG_SDMMC_BASE + 0x74) +#define SDMMC_RST_N_REG (DR_REG_SDMMC_BASE + 0x78) +#define SDMMC_BMOD_REG (DR_REG_SDMMC_BASE + 0x80) +#define SDMMC_PLDMND_REG (DR_REG_SDMMC_BASE + 0x84) +#define SDMMC_DBADDR_REG (DR_REG_SDMMC_BASE + 0x88) +#define SDMMC_DBADDRU_REG (DR_REG_SDMMC_BASE + 0x8c) +#define SDMMC_IDSTS_REG (DR_REG_SDMMC_BASE + 0x8c) +#define SDMMC_IDINTEN_REG (DR_REG_SDMMC_BASE + 0x90) +#define SDMMC_DSCADDR_REG (DR_REG_SDMMC_BASE + 0x94) +#define SDMMC_DSCADDRL_REG (DR_REG_SDMMC_BASE + 0x98) +#define SDMMC_DSCADDRU_REG (DR_REG_SDMMC_BASE + 0x9c) +#define SDMMC_BUFADDRL_REG (DR_REG_SDMMC_BASE + 0xa0) +#define SDMMC_BUFADDRU_REG (DR_REG_SDMMC_BASE + 0xa4) +#define SDMMC_CARDTHRCTL_REG (DR_REG_SDMMC_BASE + 0x100) +#define SDMMC_BACK_END_POWER_REG (DR_REG_SDMMC_BASE + 0x104) +#define SDMMC_UHS_REG_EXT_REG (DR_REG_SDMMC_BASE + 0x108) +#define SDMMC_EMMC_DDR_REG_REG (DR_REG_SDMMC_BASE + 0x10c) +#define SDMMC_ENABLE_SHIFT_REG (DR_REG_SDMMC_BASE + 0x110) + +#define SDMMC_CLOCK_REG (DR_REG_SDMMC_BASE + 0x800) + +#define SDMMC_INTMASK_IO_SLOT1 BIT(17) +#define SDMMC_INTMASK_IO_SLOT0 BIT(16) +#define SDMMC_INTMASK_EBE BIT(15) +#define SDMMC_INTMASK_ACD BIT(14) +#define SDMMC_INTMASK_SBE BIT(13) +#define SDMMC_INTMASK_HLE BIT(12) +#define SDMMC_INTMASK_FRUN BIT(11) +#define SDMMC_INTMASK_HTO BIT(10) +#define SDMMC_INTMASK_DTO BIT(9) +#define SDMMC_INTMASK_RTO BIT(8) +#define SDMMC_INTMASK_DCRC BIT(7) +#define SDMMC_INTMASK_RCRC BIT(6) +#define SDMMC_INTMASK_RXDR BIT(5) +#define SDMMC_INTMASK_TXDR BIT(4) +#define SDMMC_INTMASK_DATA_OVER BIT(3) +#define SDMMC_INTMASK_CMD_DONE BIT(2) +#define SDMMC_INTMASK_RESP_ERR BIT(1) +#define SDMMC_INTMASK_CD BIT(0) + +#define SDMMC_IDMAC_INTMASK_AI BIT(9) +#define SDMMC_IDMAC_INTMASK_NI BIT(8) +#define SDMMC_IDMAC_INTMASK_CES BIT(5) +#define SDMMC_IDMAC_INTMASK_DU BIT(4) +#define SDMMC_IDMAC_INTMASK_FBE BIT(2) +#define SDMMC_IDMAC_INTMASK_RI BIT(1) +#define SDMMC_IDMAC_INTMASK_TI BIT(0) diff --git a/components/soc/soc/esp32s3/include/soc/sdmmc_struct.h b/components/soc/soc/esp32s3/include/soc/sdmmc_struct.h new file mode 100644 index 000000000..dc4e65df0 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sdmmc_struct.h @@ -0,0 +1,374 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#include + +#ifdef __cplusplus +extern "C" { +#endif + +typedef struct { + uint32_t reserved1: 1; + uint32_t disable_int_on_completion: 1; + uint32_t last_descriptor: 1; + uint32_t first_descriptor: 1; + uint32_t second_address_chained: 1; + uint32_t end_of_ring: 1; + uint32_t reserved2: 24; + uint32_t card_error_summary: 1; + uint32_t owned_by_idmac: 1; + uint32_t buffer1_size: 13; + uint32_t buffer2_size: 13; + uint32_t reserved3: 6; + void *buffer1_ptr; + union { + void *buffer2_ptr; + void *next_desc_ptr; + }; +} sdmmc_desc_t; + +#define SDMMC_DMA_MAX_BUF_LEN 4096 + +_Static_assert(sizeof(sdmmc_desc_t) == 16, "invalid size of sdmmc_desc_t structure"); + + +typedef struct { + uint32_t cmd_index: 6; ///< Command index + uint32_t response_expect: 1; ///< set if response is expected + uint32_t response_long: 1; ///< 0: short response expected, 1: long response expected + uint32_t check_response_crc: 1; ///< set if controller should check response CRC + uint32_t data_expected: 1; ///< 0: no data expected, 1: data expected + uint32_t rw: 1; ///< 0: read from card, 1: write to card (don't care if no data expected) + uint32_t stream_mode: 1; ///< 0: block transfer, 1: stream transfer (don't care if no data expected) + uint32_t send_auto_stop: 1; ///< set to send stop at the end of the transfer + uint32_t wait_complete: 1; ///< 0: send command at once, 1: wait for previous command to complete + uint32_t stop_abort_cmd: 1; ///< set if this is a stop or abort command intended to stop current transfer + uint32_t send_init: 1; ///< set to send init sequence (80 clocks of 1) + uint32_t card_num: 5; ///< card number + uint32_t update_clk_reg: 1; ///< 0: normal command, 1: don't send command, just update clock registers + uint32_t read_ceata: 1; ///< set if performing read from CE-ATA device + uint32_t ccs_expected: 1; ///< set if CCS is expected from CE-ATA device + uint32_t enable_boot: 1; ///< set for mandatory boot mode + uint32_t expect_boot_ack: 1; ///< when set along with enable_boot, controller expects boot ack pattern + uint32_t disable_boot: 1; ///< set to terminate boot operation (don't set along with enable_boot) + uint32_t boot_mode: 1; ///< 0: mandatory boot operation, 1: alternate boot operation + uint32_t volt_switch: 1; ///< set to enable voltage switching (for CMD11 only) + uint32_t use_hold_reg: 1; ///< clear to bypass HOLD register + uint32_t reserved: 1; + uint32_t start_command: 1; ///< Start command; once command is sent to the card, bit is cleared. +} sdmmc_hw_cmd_t; ///< command format used in cmd register; this structure is defined to make it easier to build command values + +_Static_assert(sizeof(sdmmc_hw_cmd_t) == 4, "invalid size of sdmmc_cmd_t structure"); + + +typedef volatile struct { + union { + struct { + uint32_t controller_reset: 1; + uint32_t fifo_reset: 1; + uint32_t dma_reset: 1; + uint32_t reserved1: 1; + uint32_t int_enable: 1; + uint32_t dma_enable: 1; + uint32_t read_wait: 1; + uint32_t send_irq_response: 1; + uint32_t abort_read_data: 1; + uint32_t send_ccsd: 1; + uint32_t send_auto_stop_ccsd: 1; + uint32_t ceata_device_interrupt_status: 1; + uint32_t reserved2: 4; + uint32_t card_voltage_a: 4; + uint32_t card_voltage_b: 4; + uint32_t enable_od_pullup: 1; + uint32_t use_internal_dma: 1; + uint32_t reserved3: 6; + }; + uint32_t val; + } ctrl; + + uint32_t pwren; ///< 1: enable power to card, 0: disable power to card + + union { + struct { + uint32_t div0: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + uint32_t div1: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + uint32_t div2: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + uint32_t div3: 8; ///< 0: bypass, 1-255: divide clock by (2*div0). + }; + uint32_t val; + } clkdiv; + + union { + struct { + uint32_t card0: 2; ///< 0-3: select clock divider for card 0 among div0-div3 + uint32_t card1: 2; ///< 0-3: select clock divider for card 1 among div0-div3 + uint32_t reserved: 28; + }; + uint32_t val; + } clksrc; + + union { + struct { + uint32_t cclk_enable: 16; ///< 1: enable clock to card, 0: disable clock + uint32_t cclk_low_power: 16; ///< 1: enable clock gating when card is idle, 0: disable clock gating + }; + uint32_t val; + } clkena; + + union { + struct { + uint32_t response: 8; ///< response timeout, in card output clock cycles + uint32_t data: 24; ///< data read timeout, in card output clock cycles + }; + uint32_t val; + } tmout; + + union { + struct { + uint32_t card_width: 16; ///< one bit for each card: 0: 1-bit mode, 1: 4-bit mode + uint32_t card_width_8: 16; ///< one bit for each card: 0: not 8-bit mode (corresponding card_width bit is used), 1: 8-bit mode (card_width bit is ignored) + }; + uint32_t val; + } ctype; + + uint32_t blksiz: 16; ///< block size, default 0x200 + uint32_t : 16; + + uint32_t bytcnt; ///< number of bytes to be transferred + + union { + struct { + uint32_t cd: 1; ///< Card detect interrupt enable + uint32_t re: 1; ///< Response error interrupt enable + uint32_t cmd_done: 1; ///< Command done interrupt enable + uint32_t dto: 1; ///< Data transfer over interrupt enable + uint32_t txdr: 1; ///< Transmit FIFO data request interrupt enable + uint32_t rxdr: 1; ///< Receive FIFO data request interrupt enable + uint32_t rcrc: 1; ///< Response CRC error interrupt enable + uint32_t dcrc: 1; ///< Data CRC error interrupt enable + uint32_t rto: 1; ///< Response timeout interrupt enable + uint32_t drto: 1; ///< Data read timeout interrupt enable + uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt enable + uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt enable + uint32_t hle: 1; ///< Hardware locked write error interrupt enable + uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt enable + uint32_t acd: 1; ///< Auto command done interrupt enable + uint32_t ebe: 1; ///< End bit error / write no CRC interrupt enable + uint32_t sdio: 16; ///< SDIO interrupt enable + }; + uint32_t val; + } intmask; + + uint32_t cmdarg; ///< Command argument to be passed to card + + sdmmc_hw_cmd_t cmd; + + uint32_t resp[4]; ///< Response from card + + union { + struct { + uint32_t cd: 1; ///< Card detect interrupt masked status + uint32_t re: 1; ///< Response error interrupt masked status + uint32_t cmd_done: 1; ///< Command done interrupt masked status + uint32_t dto: 1; ///< Data transfer over interrupt masked status + uint32_t txdr: 1; ///< Transmit FIFO data request interrupt masked status + uint32_t rxdr: 1; ///< Receive FIFO data request interrupt masked status + uint32_t rcrc: 1; ///< Response CRC error interrupt masked status + uint32_t dcrc: 1; ///< Data CRC error interrupt masked status + uint32_t rto: 1; ///< Response timeout interrupt masked status + uint32_t drto: 1; ///< Data read timeout interrupt masked status + uint32_t hto: 1; ///< Data starvation-by-host timeout interrupt masked status + uint32_t frun: 1; ///< FIFO underrun/overrun error interrupt masked status + uint32_t hle: 1; ///< Hardware locked write error interrupt masked status + uint32_t sbi_bci: 1; ///< Start bit error / busy clear interrupt masked status + uint32_t acd: 1; ///< Auto command done interrupt masked status + uint32_t ebe: 1; ///< End bit error / write no CRC interrupt masked status + uint32_t sdio: 16; ///< SDIO interrupt masked status + }; + uint32_t val; + } mintsts; + + union { + struct { + uint32_t cd: 1; ///< Card detect raw interrupt status + uint32_t re: 1; ///< Response error raw interrupt status + uint32_t cmd_done: 1; ///< Command done raw interrupt status + uint32_t dto: 1; ///< Data transfer over raw interrupt status + uint32_t txdr: 1; ///< Transmit FIFO data request raw interrupt status + uint32_t rxdr: 1; ///< Receive FIFO data request raw interrupt status + uint32_t rcrc: 1; ///< Response CRC error raw interrupt status + uint32_t dcrc: 1; ///< Data CRC error raw interrupt status + uint32_t rto: 1; ///< Response timeout raw interrupt status + uint32_t drto: 1; ///< Data read timeout raw interrupt status + uint32_t hto: 1; ///< Data starvation-by-host timeout raw interrupt status + uint32_t frun: 1; ///< FIFO underrun/overrun error raw interrupt status + uint32_t hle: 1; ///< Hardware locked write error raw interrupt status + uint32_t sbi_bci: 1; ///< Start bit error / busy clear raw interrupt status + uint32_t acd: 1; ///< Auto command done raw interrupt status + uint32_t ebe: 1; ///< End bit error / write no CRC raw interrupt status + uint32_t sdio: 16; ///< SDIO raw interrupt status + }; + uint32_t val; + } rintsts; ///< interrupts can be cleared by writing this register + + union { + struct { + uint32_t fifo_rx_watermark: 1; ///< FIFO reached receive watermark level + uint32_t fifo_tx_watermark: 1; ///< FIFO reached transmit watermark level + uint32_t fifo_empty: 1; ///< FIFO is empty + uint32_t fifo_full: 1; ///< FIFO is full + uint32_t cmd_fsm_state: 4; ///< command FSM state + uint32_t data3_status: 1; ///< this bit reads 1 if card is present + uint32_t data_busy: 1; ///< this bit reads 1 if card is busy + uint32_t data_fsm_busy: 1; ///< this bit reads 1 if transmit/receive FSM is busy + uint32_t response_index: 6; ///< index of the previous response + uint32_t fifo_count: 13; ///< number of filled locations in the FIFO + uint32_t dma_ack: 1; ///< DMA acknowledge signal + uint32_t dma_req: 1; ///< DMA request signal + }; + uint32_t val; + } status; + + union { + struct { + uint32_t tx_watermark: 12; ///< FIFO TX watermark level + uint32_t reserved1: 4; + uint32_t rx_watermark: 12; ///< FIFO RX watermark level + uint32_t dw_dma_mts: 3; + uint32_t reserved2: 1; + }; + uint32_t val; + } fifoth; + + union { + struct { + uint32_t cards: 2; ///< bit N reads 0 if card N is present + uint32_t reserved: 30; + }; + uint32_t val; + } cdetect; + + union { + struct { + uint32_t cards: 2; ///< bit N reads 1 if card N is write protected + uint32_t reserved: 30; + }; + uint32_t val; + } wrtprt; + + uint32_t gpio; ///< unused + uint32_t tcbcnt; ///< transferred (to card) byte count + uint32_t tbbcnt; ///< transferred from host to FIFO byte count + + union { + struct { + uint32_t debounce_count: 24; ///< number of host cycles used by debounce filter, typical time should be 5-25ms + uint32_t reserved: 8; + }; + } debnce; + + uint32_t usrid; ///< user ID + uint32_t verid; ///< IP block version + uint32_t hcon; ///< compile-time IP configuration + uint32_t uhs; ///< TBD + + union { + struct { + uint32_t cards: 2; ///< bit N resets card N, active low + uint32_t reserved: 30; + }; + } rst_n; + + uint32_t reserved_7c; + + union { + struct { + uint32_t sw_reset: 1; ///< set to reset DMA controller + uint32_t fb: 1; ///< set if AHB master performs fixed burst transfers + uint32_t dsl: 5; ///< descriptor skip length: number of words to skip between two unchained descriptors + uint32_t enable: 1; ///< set to enable IDMAC + uint32_t pbl: 3; ///< programmable burst length + uint32_t reserved: 21; + }; + uint32_t val; + } bmod; + + uint32_t pldmnd; ///< set any bit to resume IDMAC FSM from suspended state + sdmmc_desc_t *dbaddr; ///< descriptor list base + + union { + struct { + uint32_t ti: 1; ///< transmit interrupt status + uint32_t ri: 1; ///< receive interrupt status + uint32_t fbe: 1; ///< fatal bus error + uint32_t reserved1: 1; + uint32_t du: 1; ///< descriptor unavailable + uint32_t ces: 1; ///< card error summary + uint32_t reserved2: 2; + uint32_t nis: 1; ///< normal interrupt summary + uint32_t fbe_code: 3; ///< code of fatal bus error + uint32_t fsm: 4; ///< DMAC FSM state + uint32_t reserved3: 15; + }; + uint32_t val; + } idsts; + + union { + struct { + uint32_t ti: 1; ///< transmit interrupt enable + uint32_t ri: 1; ///< receive interrupt enable + uint32_t fbe: 1; ///< fatal bus error interrupt enable + uint32_t reserved1: 1; + uint32_t du: 1; ///< descriptor unavailable interrupt enable + uint32_t ces: 1; ///< card error interrupt enable + uint32_t reserved2: 2; + uint32_t ni: 1; ///< normal interrupt interrupt enable + uint32_t ai: 1; ///< abnormal interrupt enable + uint32_t reserved3: 22; + }; + uint32_t val; + } idinten; + + uint32_t dscaddr; ///< current host descriptor address + uint32_t dscaddrl; ///< unused + uint32_t dscaddru; ///< unused + uint32_t bufaddrl; ///< unused + uint32_t bufaddru; ///< unused + uint32_t reserved_a8[22]; + uint32_t cardthrctl; + uint32_t back_end_power; + uint32_t uhs_reg_ext; + uint32_t emmc_ddr_reg; + uint32_t enable_shift; + uint32_t reserved_114[443]; + union { + struct { + uint32_t phase_dout: 3; ///< phase of data output clock (0x0: 0, 0x1: 90, 0x4: 180, 0x6: 270) + uint32_t phase_din: 3; ///< phase of data input clock + uint32_t phase_core: 3; ///< phase of the clock to SDMMC peripheral + uint32_t div_factor_p: 4; ///< controls clock period; it will be (div_factor_p + 1) / 160MHz + uint32_t div_factor_h: 4; ///< controls length of high pulse; it will be (div_factor_h + 1) / 160MHz + uint32_t div_factor_m: 4; ///< should be equal to div_factor_p + }; + uint32_t val; + } clock; +} sdmmc_dev_t; +extern sdmmc_dev_t SDMMC; + +_Static_assert(sizeof(sdmmc_dev_t) == 0x804, "invalid size of sdmmc_dev_t structure"); + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sens_reg.h b/components/soc/soc/esp32s3/include/soc/sens_reg.h new file mode 100644 index 000000000..5be2afd38 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sens_reg.h @@ -0,0 +1,1722 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SENS_SAR_READER1_CTRL_REG (DR_REG_SENS_BASE + 0x0000) +/* SENS_SAR1_INT_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: enable saradc1 to send out interrupt*/ +#define SENS_SAR1_INT_EN (BIT(29)) +#define SENS_SAR1_INT_EN_M (BIT(29)) +#define SENS_SAR1_INT_EN_V 0x1 +#define SENS_SAR1_INT_EN_S 29 +/* SENS_SAR1_DATA_INV : R/W ;bitpos:[28] ;default: 1'd0 ; */ +/*description: Invert SAR ADC1 data*/ +#define SENS_SAR1_DATA_INV (BIT(28)) +#define SENS_SAR1_DATA_INV_M (BIT(28)) +#define SENS_SAR1_DATA_INV_V 0x1 +#define SENS_SAR1_DATA_INV_S 28 +/* SENS_SAR1_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: */ +#define SENS_SAR1_SAMPLE_NUM 0x000000FF +#define SENS_SAR1_SAMPLE_NUM_M ((SENS_SAR1_SAMPLE_NUM_V) << (SENS_SAR1_SAMPLE_NUM_S)) +#define SENS_SAR1_SAMPLE_NUM_V 0xFF +#define SENS_SAR1_SAMPLE_NUM_S 19 +/* SENS_SAR1_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SENS_SAR1_CLK_GATED (BIT(18)) +#define SENS_SAR1_CLK_GATED_M (BIT(18)) +#define SENS_SAR1_CLK_GATED_V 0x1 +#define SENS_SAR1_CLK_GATED_S 18 +/* SENS_SAR1_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: clock divider*/ +#define SENS_SAR1_CLK_DIV 0x000000FF +#define SENS_SAR1_CLK_DIV_M ((SENS_SAR1_CLK_DIV_V) << (SENS_SAR1_CLK_DIV_S)) +#define SENS_SAR1_CLK_DIV_V 0xFF +#define SENS_SAR1_CLK_DIV_S 0 + +#define SENS_SAR_READER1_STATUS_REG (DR_REG_SENS_BASE + 0x0004) +/* SENS_SAR1_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SENS_SAR1_READER_STATUS 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_M ((SENS_SAR1_READER_STATUS_V) << (SENS_SAR1_READER_STATUS_S)) +#define SENS_SAR1_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR1_READER_STATUS_S 0 + +#define SENS_SAR_MEAS1_CTRL1_REG (DR_REG_SENS_BASE + 0x0008) +/* SENS_AMP_SHORT_REF_GND_FORCE : R/W ;bitpos:[31:30] ;default: 2'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_GND_FORCE_M ((SENS_AMP_SHORT_REF_GND_FORCE_V) << (SENS_AMP_SHORT_REF_GND_FORCE_S)) +#define SENS_AMP_SHORT_REF_GND_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_GND_FORCE_S 30 +/* SENS_AMP_SHORT_REF_FORCE : R/W ;bitpos:[29:28] ;default: 2'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FORCE 0x00000003 +#define SENS_AMP_SHORT_REF_FORCE_M ((SENS_AMP_SHORT_REF_FORCE_V) << (SENS_AMP_SHORT_REF_FORCE_S)) +#define SENS_AMP_SHORT_REF_FORCE_V 0x3 +#define SENS_AMP_SHORT_REF_FORCE_S 28 +/* SENS_AMP_RST_FB_FORCE : R/W ;bitpos:[27:26] ;default: 2'b0 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FORCE 0x00000003 +#define SENS_AMP_RST_FB_FORCE_M ((SENS_AMP_RST_FB_FORCE_V) << (SENS_AMP_RST_FB_FORCE_S)) +#define SENS_AMP_RST_FB_FORCE_V 0x3 +#define SENS_AMP_RST_FB_FORCE_S 26 +/* SENS_FORCE_XPD_AMP : R/W ;bitpos:[25:24] ;default: 2'd0 ; */ +/*description: */ +#define SENS_FORCE_XPD_AMP 0x00000003 +#define SENS_FORCE_XPD_AMP_M ((SENS_FORCE_XPD_AMP_V) << (SENS_FORCE_XPD_AMP_S)) +#define SENS_FORCE_XPD_AMP_V 0x3 +#define SENS_FORCE_XPD_AMP_S 24 + +#define SENS_SAR_MEAS1_CTRL2_REG (DR_REG_SENS_BASE + 0x000c) +/* SENS_SAR1_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: SAR ADC1 pad enable bitmap is controlled by SW*/ +#define SENS_SAR1_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR1_EN_PAD_FORCE_V 0x1 +#define SENS_SAR1_EN_PAD_FORCE_S 31 +/* SENS_SAR1_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ +/*description: SAR ADC1 pad enable bitmap*/ +#define SENS_SAR1_EN_PAD 0x00000FFF +#define SENS_SAR1_EN_PAD_M ((SENS_SAR1_EN_PAD_V) << (SENS_SAR1_EN_PAD_S)) +#define SENS_SAR1_EN_PAD_V 0xFFF +#define SENS_SAR1_EN_PAD_S 19 +/* SENS_MEAS1_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: 1: SAR ADC1 controller (in RTC) is started by SW*/ +#define SENS_MEAS1_START_FORCE (BIT(18)) +#define SENS_MEAS1_START_FORCE_M (BIT(18)) +#define SENS_MEAS1_START_FORCE_V 0x1 +#define SENS_MEAS1_START_FORCE_S 18 +/* SENS_MEAS1_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: SAR ADC1 controller (in RTC) starts conversion*/ +#define SENS_MEAS1_START_SAR (BIT(17)) +#define SENS_MEAS1_START_SAR_M (BIT(17)) +#define SENS_MEAS1_START_SAR_V 0x1 +#define SENS_MEAS1_START_SAR_S 17 +/* SENS_MEAS1_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: SAR ADC1 conversion done indication*/ +#define SENS_MEAS1_DONE_SAR (BIT(16)) +#define SENS_MEAS1_DONE_SAR_M (BIT(16)) +#define SENS_MEAS1_DONE_SAR_V 0x1 +#define SENS_MEAS1_DONE_SAR_S 16 +/* SENS_MEAS1_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: SAR ADC1 data*/ +#define SENS_MEAS1_DATA_SAR 0x0000FFFF +#define SENS_MEAS1_DATA_SAR_M ((SENS_MEAS1_DATA_SAR_V) << (SENS_MEAS1_DATA_SAR_S)) +#define SENS_MEAS1_DATA_SAR_V 0xFFFF +#define SENS_MEAS1_DATA_SAR_S 0 + +#define SENS_SAR_MEAS1_MUX_REG (DR_REG_SENS_BASE + 0x0010) +/* SENS_SAR1_DIG_FORCE : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: 1: SAR ADC1 controlled by DIG ADC1 CTRL*/ +#define SENS_SAR1_DIG_FORCE (BIT(31)) +#define SENS_SAR1_DIG_FORCE_M (BIT(31)) +#define SENS_SAR1_DIG_FORCE_V 0x1 +#define SENS_SAR1_DIG_FORCE_S 31 + +#define SENS_SAR_ATTEN1_REG (DR_REG_SENS_BASE + 0x0014) +/* SENS_SAR1_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad*/ +#define SENS_SAR1_ATTEN 0xFFFFFFFF +#define SENS_SAR1_ATTEN_M ((SENS_SAR1_ATTEN_V) << (SENS_SAR1_ATTEN_S)) +#define SENS_SAR1_ATTEN_V 0xFFFFFFFF +#define SENS_SAR1_ATTEN_S 0 + +#define SENS_SAR_AMP_CTRL1_REG (DR_REG_SENS_BASE + 0x0018) +/* SENS_SAR_AMP_WAIT2 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT2 0x0000FFFF +#define SENS_SAR_AMP_WAIT2_M ((SENS_SAR_AMP_WAIT2_V) << (SENS_SAR_AMP_WAIT2_S)) +#define SENS_SAR_AMP_WAIT2_V 0xFFFF +#define SENS_SAR_AMP_WAIT2_S 16 +/* SENS_SAR_AMP_WAIT1 : R/W ;bitpos:[15:0] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT1 0x0000FFFF +#define SENS_SAR_AMP_WAIT1_M ((SENS_SAR_AMP_WAIT1_V) << (SENS_SAR_AMP_WAIT1_S)) +#define SENS_SAR_AMP_WAIT1_V 0xFFFF +#define SENS_SAR_AMP_WAIT1_S 0 + +#define SENS_SAR_AMP_CTRL2_REG (DR_REG_SENS_BASE + 0x001c) +/* SENS_SAR_AMP_WAIT3 : R/W ;bitpos:[31:16] ;default: 16'd10 ; */ +/*description: */ +#define SENS_SAR_AMP_WAIT3 0x0000FFFF +#define SENS_SAR_AMP_WAIT3_M ((SENS_SAR_AMP_WAIT3_V) << (SENS_SAR_AMP_WAIT3_S)) +#define SENS_SAR_AMP_WAIT3_V 0xFFFF +#define SENS_SAR_AMP_WAIT3_S 16 +/* SENS_SAR_RSTB_FSM_IDLE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SAR_RSTB_FSM_IDLE (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_M (BIT(6)) +#define SENS_SAR_RSTB_FSM_IDLE_V 0x1 +#define SENS_SAR_RSTB_FSM_IDLE_S 6 +/* SENS_XPD_SAR_FSM_IDLE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_XPD_SAR_FSM_IDLE (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_M (BIT(5)) +#define SENS_XPD_SAR_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_FSM_IDLE_S 5 +/* SENS_AMP_SHORT_REF_GND_FSM_IDLE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_M (BIT(4)) +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_GND_FSM_IDLE_S 4 +/* SENS_AMP_SHORT_REF_FSM_IDLE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FSM_IDLE (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_M (BIT(3)) +#define SENS_AMP_SHORT_REF_FSM_IDLE_V 0x1 +#define SENS_AMP_SHORT_REF_FSM_IDLE_S 3 +/* SENS_AMP_RST_FB_FSM_IDLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FSM_IDLE (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_M (BIT(2)) +#define SENS_AMP_RST_FB_FSM_IDLE_V 0x1 +#define SENS_AMP_RST_FB_FSM_IDLE_S 2 +/* SENS_XPD_SAR_AMP_FSM_IDLE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_XPD_SAR_AMP_FSM_IDLE (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_M (BIT(1)) +#define SENS_XPD_SAR_AMP_FSM_IDLE_V 0x1 +#define SENS_XPD_SAR_AMP_FSM_IDLE_S 1 +/* SENS_SAR1_DAC_XPD_FSM_IDLE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SAR1_DAC_XPD_FSM_IDLE (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_M (BIT(0)) +#define SENS_SAR1_DAC_XPD_FSM_IDLE_V 0x1 +#define SENS_SAR1_DAC_XPD_FSM_IDLE_S 0 + +#define SENS_SAR_AMP_CTRL3_REG (DR_REG_SENS_BASE + 0x0020) +/* SENS_SAR_RSTB_FSM : R/W ;bitpos:[27:24] ;default: 4'b0000 ; */ +/*description: */ +#define SENS_SAR_RSTB_FSM 0x0000000F +#define SENS_SAR_RSTB_FSM_M ((SENS_SAR_RSTB_FSM_V) << (SENS_SAR_RSTB_FSM_S)) +#define SENS_SAR_RSTB_FSM_V 0xF +#define SENS_SAR_RSTB_FSM_S 24 +/* SENS_XPD_SAR_FSM : R/W ;bitpos:[23:20] ;default: 4'b0111 ; */ +/*description: */ +#define SENS_XPD_SAR_FSM 0x0000000F +#define SENS_XPD_SAR_FSM_M ((SENS_XPD_SAR_FSM_V) << (SENS_XPD_SAR_FSM_S)) +#define SENS_XPD_SAR_FSM_V 0xF +#define SENS_XPD_SAR_FSM_S 20 +/* SENS_AMP_SHORT_REF_GND_FSM : R/W ;bitpos:[19:16] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_GND_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_GND_FSM_M ((SENS_AMP_SHORT_REF_GND_FSM_V) << (SENS_AMP_SHORT_REF_GND_FSM_S)) +#define SENS_AMP_SHORT_REF_GND_FSM_V 0xF +#define SENS_AMP_SHORT_REF_GND_FSM_S 16 +/* SENS_AMP_SHORT_REF_FSM : R/W ;bitpos:[15:12] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_AMP_SHORT_REF_FSM 0x0000000F +#define SENS_AMP_SHORT_REF_FSM_M ((SENS_AMP_SHORT_REF_FSM_V) << (SENS_AMP_SHORT_REF_FSM_S)) +#define SENS_AMP_SHORT_REF_FSM_V 0xF +#define SENS_AMP_SHORT_REF_FSM_S 12 +/* SENS_AMP_RST_FB_FSM : R/W ;bitpos:[11:8] ;default: 4'b1000 ; */ +/*description: */ +#define SENS_AMP_RST_FB_FSM 0x0000000F +#define SENS_AMP_RST_FB_FSM_M ((SENS_AMP_RST_FB_FSM_V) << (SENS_AMP_RST_FB_FSM_S)) +#define SENS_AMP_RST_FB_FSM_V 0xF +#define SENS_AMP_RST_FB_FSM_S 8 +/* SENS_XPD_SAR_AMP_FSM : R/W ;bitpos:[7:4] ;default: 4'b1111 ; */ +/*description: */ +#define SENS_XPD_SAR_AMP_FSM 0x0000000F +#define SENS_XPD_SAR_AMP_FSM_M ((SENS_XPD_SAR_AMP_FSM_V) << (SENS_XPD_SAR_AMP_FSM_S)) +#define SENS_XPD_SAR_AMP_FSM_V 0xF +#define SENS_XPD_SAR_AMP_FSM_S 4 +/* SENS_SAR1_DAC_XPD_FSM : R/W ;bitpos:[3:0] ;default: 4'b0011 ; */ +/*description: */ +#define SENS_SAR1_DAC_XPD_FSM 0x0000000F +#define SENS_SAR1_DAC_XPD_FSM_M ((SENS_SAR1_DAC_XPD_FSM_V) << (SENS_SAR1_DAC_XPD_FSM_S)) +#define SENS_SAR1_DAC_XPD_FSM_V 0xF +#define SENS_SAR1_DAC_XPD_FSM_S 0 + +#define SENS_SAR_READER2_CTRL_REG (DR_REG_SENS_BASE + 0x0024) +/* SENS_SAR2_INT_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: enable saradc2 to send out interrupt*/ +#define SENS_SAR2_INT_EN (BIT(30)) +#define SENS_SAR2_INT_EN_M (BIT(30)) +#define SENS_SAR2_INT_EN_V 0x1 +#define SENS_SAR2_INT_EN_S 30 +/* SENS_SAR2_DATA_INV : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Invert SAR ADC2 data*/ +#define SENS_SAR2_DATA_INV (BIT(29)) +#define SENS_SAR2_DATA_INV_M (BIT(29)) +#define SENS_SAR2_DATA_INV_V 0x1 +#define SENS_SAR2_DATA_INV_S 29 +/* SENS_SAR2_SAMPLE_NUM : R/W ;bitpos:[26:19] ;default: 8'd0 ; */ +/*description: */ +#define SENS_SAR2_SAMPLE_NUM 0x000000FF +#define SENS_SAR2_SAMPLE_NUM_M ((SENS_SAR2_SAMPLE_NUM_V) << (SENS_SAR2_SAMPLE_NUM_S)) +#define SENS_SAR2_SAMPLE_NUM_V 0xFF +#define SENS_SAR2_SAMPLE_NUM_S 19 +/* SENS_SAR2_CLK_GATED : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SENS_SAR2_CLK_GATED (BIT(18)) +#define SENS_SAR2_CLK_GATED_M (BIT(18)) +#define SENS_SAR2_CLK_GATED_V 0x1 +#define SENS_SAR2_CLK_GATED_S 18 +/* SENS_SAR2_WAIT_ARB_CYCLE : R/W ;bitpos:[17:16] ;default: 2'b1 ; */ +/*description: wait arbit stable after sar_done*/ +#define SENS_SAR2_WAIT_ARB_CYCLE 0x00000003 +#define SENS_SAR2_WAIT_ARB_CYCLE_M ((SENS_SAR2_WAIT_ARB_CYCLE_V) << (SENS_SAR2_WAIT_ARB_CYCLE_S)) +#define SENS_SAR2_WAIT_ARB_CYCLE_V 0x3 +#define SENS_SAR2_WAIT_ARB_CYCLE_S 16 +/* SENS_SAR2_CLK_DIV : R/W ;bitpos:[7:0] ;default: 8'd2 ; */ +/*description: clock divider*/ +#define SENS_SAR2_CLK_DIV 0x000000FF +#define SENS_SAR2_CLK_DIV_M ((SENS_SAR2_CLK_DIV_V) << (SENS_SAR2_CLK_DIV_S)) +#define SENS_SAR2_CLK_DIV_V 0xFF +#define SENS_SAR2_CLK_DIV_S 0 + +#define SENS_SAR_READER2_STATUS_REG (DR_REG_SENS_BASE + 0x0028) +/* SENS_SAR2_READER_STATUS : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SENS_SAR2_READER_STATUS 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_M ((SENS_SAR2_READER_STATUS_V) << (SENS_SAR2_READER_STATUS_S)) +#define SENS_SAR2_READER_STATUS_V 0xFFFFFFFF +#define SENS_SAR2_READER_STATUS_S 0 + +#define SENS_SAR_MEAS2_CTRL1_REG (DR_REG_SENS_BASE + 0x002c) +/* SENS_SAR2_XPD_WAIT : R/W ;bitpos:[31:24] ;default: 8'h7 ; */ +/*description: */ +#define SENS_SAR2_XPD_WAIT 0x000000FF +#define SENS_SAR2_XPD_WAIT_M ((SENS_SAR2_XPD_WAIT_V) << (SENS_SAR2_XPD_WAIT_S)) +#define SENS_SAR2_XPD_WAIT_V 0xFF +#define SENS_SAR2_XPD_WAIT_S 24 +/* SENS_SAR2_RSTB_WAIT : R/W ;bitpos:[23:16] ;default: 8'd2 ; */ +/*description: */ +#define SENS_SAR2_RSTB_WAIT 0x000000FF +#define SENS_SAR2_RSTB_WAIT_M ((SENS_SAR2_RSTB_WAIT_V) << (SENS_SAR2_RSTB_WAIT_S)) +#define SENS_SAR2_RSTB_WAIT_V 0xFF +#define SENS_SAR2_RSTB_WAIT_S 16 +/* SENS_SAR2_STANDBY_WAIT : R/W ;bitpos:[15:8] ;default: 8'd2 ; */ +/*description: */ +#define SENS_SAR2_STANDBY_WAIT 0x000000FF +#define SENS_SAR2_STANDBY_WAIT_M ((SENS_SAR2_STANDBY_WAIT_V) << (SENS_SAR2_STANDBY_WAIT_S)) +#define SENS_SAR2_STANDBY_WAIT_V 0xFF +#define SENS_SAR2_STANDBY_WAIT_S 8 +/* SENS_SAR2_RSTB_FORCE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENS_SAR2_RSTB_FORCE 0x00000003 +#define SENS_SAR2_RSTB_FORCE_M ((SENS_SAR2_RSTB_FORCE_V) << (SENS_SAR2_RSTB_FORCE_S)) +#define SENS_SAR2_RSTB_FORCE_V 0x3 +#define SENS_SAR2_RSTB_FORCE_S 6 +/* SENS_SAR2_EN_TEST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: SAR2_EN_TEST*/ +#define SENS_SAR2_EN_TEST (BIT(5)) +#define SENS_SAR2_EN_TEST_M (BIT(5)) +#define SENS_SAR2_EN_TEST_V 0x1 +#define SENS_SAR2_EN_TEST_S 5 +/* SENS_SAR2_PKDET_CAL_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: rtc control pkdet enable*/ +#define SENS_SAR2_PKDET_CAL_EN (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_M (BIT(4)) +#define SENS_SAR2_PKDET_CAL_EN_V 0x1 +#define SENS_SAR2_PKDET_CAL_EN_S 4 +/* SENS_SAR2_PWDET_CAL_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: rtc control pwdet enable*/ +#define SENS_SAR2_PWDET_CAL_EN (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_M (BIT(3)) +#define SENS_SAR2_PWDET_CAL_EN_V 0x1 +#define SENS_SAR2_PWDET_CAL_EN_S 3 +/* SENS_SAR2_CNTL_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: saradc2_cntl_fsm*/ +#define SENS_SAR2_CNTL_STATE 0x00000007 +#define SENS_SAR2_CNTL_STATE_M ((SENS_SAR2_CNTL_STATE_V) << (SENS_SAR2_CNTL_STATE_S)) +#define SENS_SAR2_CNTL_STATE_V 0x7 +#define SENS_SAR2_CNTL_STATE_S 0 + +#define SENS_SAR_MEAS2_CTRL2_REG (DR_REG_SENS_BASE + 0x0030) +/* SENS_SAR2_EN_PAD_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 pad enable bitmap is controlled by SW*/ +#define SENS_SAR2_EN_PAD_FORCE (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_M (BIT(31)) +#define SENS_SAR2_EN_PAD_FORCE_V 0x1 +#define SENS_SAR2_EN_PAD_FORCE_S 31 +/* SENS_SAR2_EN_PAD : R/W ;bitpos:[30:19] ;default: 12'b0 ; */ +/*description: SAR ADC2 pad enable bitmap*/ +#define SENS_SAR2_EN_PAD 0x00000FFF +#define SENS_SAR2_EN_PAD_M ((SENS_SAR2_EN_PAD_V) << (SENS_SAR2_EN_PAD_S)) +#define SENS_SAR2_EN_PAD_V 0xFFF +#define SENS_SAR2_EN_PAD_S 19 +/* SENS_MEAS2_START_FORCE : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: 1: SAR ADC2 controller (in RTC) is started by SW*/ +#define SENS_MEAS2_START_FORCE (BIT(18)) +#define SENS_MEAS2_START_FORCE_M (BIT(18)) +#define SENS_MEAS2_START_FORCE_V 0x1 +#define SENS_MEAS2_START_FORCE_S 18 +/* SENS_MEAS2_START_SAR : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: SAR ADC2 controller (in RTC) starts conversion*/ +#define SENS_MEAS2_START_SAR (BIT(17)) +#define SENS_MEAS2_START_SAR_M (BIT(17)) +#define SENS_MEAS2_START_SAR_V 0x1 +#define SENS_MEAS2_START_SAR_S 17 +/* SENS_MEAS2_DONE_SAR : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: SAR ADC2 conversion done indication*/ +#define SENS_MEAS2_DONE_SAR (BIT(16)) +#define SENS_MEAS2_DONE_SAR_M (BIT(16)) +#define SENS_MEAS2_DONE_SAR_V 0x1 +#define SENS_MEAS2_DONE_SAR_S 16 +/* SENS_MEAS2_DATA_SAR : RO ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: SAR ADC2 data*/ +#define SENS_MEAS2_DATA_SAR 0x0000FFFF +#define SENS_MEAS2_DATA_SAR_M ((SENS_MEAS2_DATA_SAR_V) << (SENS_MEAS2_DATA_SAR_S)) +#define SENS_MEAS2_DATA_SAR_V 0xFFFF +#define SENS_MEAS2_DATA_SAR_S 0 + +#define SENS_SAR_MEAS2_MUX_REG (DR_REG_SENS_BASE + 0x0034) +/* SENS_SAR2_RTC_FORCE : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: in sleep force to use rtc to control ADC*/ +#define SENS_SAR2_RTC_FORCE (BIT(31)) +#define SENS_SAR2_RTC_FORCE_M (BIT(31)) +#define SENS_SAR2_RTC_FORCE_V 0x1 +#define SENS_SAR2_RTC_FORCE_S 31 +/* SENS_SAR2_PWDET_CCT : R/W ;bitpos:[30:28] ;default: 3'b0 ; */ +/*description: SAR2_PWDET_CCT*/ +#define SENS_SAR2_PWDET_CCT 0x00000007 +#define SENS_SAR2_PWDET_CCT_M ((SENS_SAR2_PWDET_CCT_V) << (SENS_SAR2_PWDET_CCT_S)) +#define SENS_SAR2_PWDET_CCT_V 0x7 +#define SENS_SAR2_PWDET_CCT_S 28 + +#define SENS_SAR_ATTEN2_REG (DR_REG_SENS_BASE + 0x0038) +/* SENS_SAR2_ATTEN : R/W ;bitpos:[31:0] ;default: 32'hffffffff ; */ +/*description: 2-bit attenuation for each pad*/ +#define SENS_SAR2_ATTEN 0xFFFFFFFF +#define SENS_SAR2_ATTEN_M ((SENS_SAR2_ATTEN_V) << (SENS_SAR2_ATTEN_S)) +#define SENS_SAR2_ATTEN_V 0xFFFFFFFF +#define SENS_SAR2_ATTEN_S 0 + +#define SENS_SAR_POWER_XPD_SAR_REG (DR_REG_SENS_BASE + 0x003c) +/* SENS_SARCLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SENS_SARCLK_EN (BIT(31)) +#define SENS_SARCLK_EN_M (BIT(31)) +#define SENS_SARCLK_EN_V 0x1 +#define SENS_SARCLK_EN_S 31 +/* SENS_FORCE_XPD_SAR : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ +/*description: */ +#define SENS_FORCE_XPD_SAR 0x00000003 +#define SENS_FORCE_XPD_SAR_M ((SENS_FORCE_XPD_SAR_V) << (SENS_FORCE_XPD_SAR_S)) +#define SENS_FORCE_XPD_SAR_V 0x3 +#define SENS_FORCE_XPD_SAR_S 29 + +#define SENS_SAR_SLAVE_ADDR1_REG (DR_REG_SENS_BASE + 0x0040) +/* SENS_MEAS_STATUS : RO ;bitpos:[29:22] ;default: 8'h0 ; */ +/*description: */ +#define SENS_MEAS_STATUS 0x000000FF +#define SENS_MEAS_STATUS_M ((SENS_MEAS_STATUS_V) << (SENS_MEAS_STATUS_S)) +#define SENS_MEAS_STATUS_V 0xFF +#define SENS_MEAS_STATUS_S 22 +/* SENS_I2C_SLAVE_ADDR0 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR0 0x000007FF +#define SENS_I2C_SLAVE_ADDR0_M ((SENS_I2C_SLAVE_ADDR0_V) << (SENS_I2C_SLAVE_ADDR0_S)) +#define SENS_I2C_SLAVE_ADDR0_V 0x7FF +#define SENS_I2C_SLAVE_ADDR0_S 11 +/* SENS_I2C_SLAVE_ADDR1 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR1 0x000007FF +#define SENS_I2C_SLAVE_ADDR1_M ((SENS_I2C_SLAVE_ADDR1_V) << (SENS_I2C_SLAVE_ADDR1_S)) +#define SENS_I2C_SLAVE_ADDR1_V 0x7FF +#define SENS_I2C_SLAVE_ADDR1_S 0 + +#define SENS_SAR_SLAVE_ADDR2_REG (DR_REG_SENS_BASE + 0x0044) +/* SENS_I2C_SLAVE_ADDR2 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR2 0x000007FF +#define SENS_I2C_SLAVE_ADDR2_M ((SENS_I2C_SLAVE_ADDR2_V) << (SENS_I2C_SLAVE_ADDR2_S)) +#define SENS_I2C_SLAVE_ADDR2_V 0x7FF +#define SENS_I2C_SLAVE_ADDR2_S 11 +/* SENS_I2C_SLAVE_ADDR3 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR3 0x000007FF +#define SENS_I2C_SLAVE_ADDR3_M ((SENS_I2C_SLAVE_ADDR3_V) << (SENS_I2C_SLAVE_ADDR3_S)) +#define SENS_I2C_SLAVE_ADDR3_V 0x7FF +#define SENS_I2C_SLAVE_ADDR3_S 0 + +#define SENS_SAR_SLAVE_ADDR3_REG (DR_REG_SENS_BASE + 0x0048) +/* SENS_I2C_SLAVE_ADDR4 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR4 0x000007FF +#define SENS_I2C_SLAVE_ADDR4_M ((SENS_I2C_SLAVE_ADDR4_V) << (SENS_I2C_SLAVE_ADDR4_S)) +#define SENS_I2C_SLAVE_ADDR4_V 0x7FF +#define SENS_I2C_SLAVE_ADDR4_S 11 +/* SENS_I2C_SLAVE_ADDR5 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR5 0x000007FF +#define SENS_I2C_SLAVE_ADDR5_M ((SENS_I2C_SLAVE_ADDR5_V) << (SENS_I2C_SLAVE_ADDR5_S)) +#define SENS_I2C_SLAVE_ADDR5_V 0x7FF +#define SENS_I2C_SLAVE_ADDR5_S 0 + +#define SENS_SAR_SLAVE_ADDR4_REG (DR_REG_SENS_BASE + 0x004c) +/* SENS_I2C_SLAVE_ADDR6 : R/W ;bitpos:[21:11] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR6 0x000007FF +#define SENS_I2C_SLAVE_ADDR6_M ((SENS_I2C_SLAVE_ADDR6_V) << (SENS_I2C_SLAVE_ADDR6_S)) +#define SENS_I2C_SLAVE_ADDR6_V 0x7FF +#define SENS_I2C_SLAVE_ADDR6_S 11 +/* SENS_I2C_SLAVE_ADDR7 : R/W ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SENS_I2C_SLAVE_ADDR7 0x000007FF +#define SENS_I2C_SLAVE_ADDR7_M ((SENS_I2C_SLAVE_ADDR7_V) << (SENS_I2C_SLAVE_ADDR7_S)) +#define SENS_I2C_SLAVE_ADDR7_V 0x7FF +#define SENS_I2C_SLAVE_ADDR7_S 0 + +#define SENS_SAR_TSENS_CTRL_REG (DR_REG_SENS_BASE + 0x0050) +/* SENS_TSENS_DUMP_OUT : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: temperature sensor dump out*/ +#define SENS_TSENS_DUMP_OUT (BIT(24)) +#define SENS_TSENS_DUMP_OUT_M (BIT(24)) +#define SENS_TSENS_DUMP_OUT_V 0x1 +#define SENS_TSENS_DUMP_OUT_S 24 +/* SENS_TSENS_POWER_UP_FORCE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: dump out & power up controlled by SW*/ +#define SENS_TSENS_POWER_UP_FORCE (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_M (BIT(23)) +#define SENS_TSENS_POWER_UP_FORCE_V 0x1 +#define SENS_TSENS_POWER_UP_FORCE_S 23 +/* SENS_TSENS_POWER_UP : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: temperature sensor power up*/ +#define SENS_TSENS_POWER_UP (BIT(22)) +#define SENS_TSENS_POWER_UP_M (BIT(22)) +#define SENS_TSENS_POWER_UP_V 0x1 +#define SENS_TSENS_POWER_UP_S 22 +/* SENS_TSENS_CLK_DIV : R/W ;bitpos:[21:14] ;default: 8'd6 ; */ +/*description: temperature sensor clock divider*/ +#define SENS_TSENS_CLK_DIV 0x000000FF +#define SENS_TSENS_CLK_DIV_M ((SENS_TSENS_CLK_DIV_V) << (SENS_TSENS_CLK_DIV_S)) +#define SENS_TSENS_CLK_DIV_V 0xFF +#define SENS_TSENS_CLK_DIV_S 14 +/* SENS_TSENS_IN_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: invert temperature sensor data*/ +#define SENS_TSENS_IN_INV (BIT(13)) +#define SENS_TSENS_IN_INV_M (BIT(13)) +#define SENS_TSENS_IN_INV_V 0x1 +#define SENS_TSENS_IN_INV_S 13 +/* SENS_TSENS_INT_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: enable temperature sensor to send out interrupt*/ +#define SENS_TSENS_INT_EN (BIT(12)) +#define SENS_TSENS_INT_EN_M (BIT(12)) +#define SENS_TSENS_INT_EN_V 0x1 +#define SENS_TSENS_INT_EN_S 12 +/* SENS_TSENS_READY : RO ;bitpos:[8] ;default: 1'h0 ; */ +/*description: indicate temperature sensor out ready*/ +#define SENS_TSENS_READY (BIT(8)) +#define SENS_TSENS_READY_M (BIT(8)) +#define SENS_TSENS_READY_V 0x1 +#define SENS_TSENS_READY_S 8 +/* SENS_TSENS_OUT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: temperature sensor data out*/ +#define SENS_TSENS_OUT 0x000000FF +#define SENS_TSENS_OUT_M ((SENS_TSENS_OUT_V) << (SENS_TSENS_OUT_S)) +#define SENS_TSENS_OUT_V 0xFF +#define SENS_TSENS_OUT_S 0 + +#define SENS_SAR_TSENS_CTRL2_REG (DR_REG_SENS_BASE + 0x0054) +/* SENS_TSENS_CLK_INV : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SENS_TSENS_CLK_INV (BIT(14)) +#define SENS_TSENS_CLK_INV_M (BIT(14)) +#define SENS_TSENS_CLK_INV_V 0x1 +#define SENS_TSENS_CLK_INV_S 14 +/* SENS_TSENS_XPD_FORCE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define SENS_TSENS_XPD_FORCE 0x00000003 +#define SENS_TSENS_XPD_FORCE_M ((SENS_TSENS_XPD_FORCE_V) << (SENS_TSENS_XPD_FORCE_S)) +#define SENS_TSENS_XPD_FORCE_V 0x3 +#define SENS_TSENS_XPD_FORCE_S 12 +/* SENS_TSENS_XPD_WAIT : R/W ;bitpos:[11:0] ;default: 12'h2 ; */ +/*description: */ +#define SENS_TSENS_XPD_WAIT 0x00000FFF +#define SENS_TSENS_XPD_WAIT_M ((SENS_TSENS_XPD_WAIT_V) << (SENS_TSENS_XPD_WAIT_S)) +#define SENS_TSENS_XPD_WAIT_V 0xFFF +#define SENS_TSENS_XPD_WAIT_S 0 + +#define SENS_SAR_I2C_CTRL_REG (DR_REG_SENS_BASE + 0x0058) +/* SENS_SAR_I2C_START_FORCE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: I2C started by SW*/ +#define SENS_SAR_I2C_START_FORCE (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_M (BIT(29)) +#define SENS_SAR_I2C_START_FORCE_V 0x1 +#define SENS_SAR_I2C_START_FORCE_S 29 +/* SENS_SAR_I2C_START : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: start I2C*/ +#define SENS_SAR_I2C_START (BIT(28)) +#define SENS_SAR_I2C_START_M (BIT(28)) +#define SENS_SAR_I2C_START_V 0x1 +#define SENS_SAR_I2C_START_S 28 +/* SENS_SAR_I2C_CTRL : R/W ;bitpos:[27:0] ;default: 28'b0 ; */ +/*description: I2C control data*/ +#define SENS_SAR_I2C_CTRL 0x0FFFFFFF +#define SENS_SAR_I2C_CTRL_M ((SENS_SAR_I2C_CTRL_V) << (SENS_SAR_I2C_CTRL_S)) +#define SENS_SAR_I2C_CTRL_V 0xFFFFFFF +#define SENS_SAR_I2C_CTRL_S 0 + +#define SENS_SAR_TOUCH_CONF_REG (DR_REG_SENS_BASE + 0x005c) +/* SENS_TOUCH_APPROACH_PAD0 : R/W ;bitpos:[31:28] ;default: 4'hF ; */ +/*description: indicate which pad is approach pad0*/ +#define SENS_TOUCH_APPROACH_PAD0 0x0000000F +#define SENS_TOUCH_APPROACH_PAD0_M ((SENS_TOUCH_APPROACH_PAD0_V) << (SENS_TOUCH_APPROACH_PAD0_S)) +#define SENS_TOUCH_APPROACH_PAD0_V 0xF +#define SENS_TOUCH_APPROACH_PAD0_S 28 +/* SENS_TOUCH_APPROACH_PAD1 : R/W ;bitpos:[27:24] ;default: 4'hF ; */ +/*description: indicate which pad is approach pad1*/ +#define SENS_TOUCH_APPROACH_PAD1 0x0000000F +#define SENS_TOUCH_APPROACH_PAD1_M ((SENS_TOUCH_APPROACH_PAD1_V) << (SENS_TOUCH_APPROACH_PAD1_S)) +#define SENS_TOUCH_APPROACH_PAD1_V 0xF +#define SENS_TOUCH_APPROACH_PAD1_S 24 +/* SENS_TOUCH_APPROACH_PAD2 : R/W ;bitpos:[23:20] ;default: 4'hF ; */ +/*description: indicate which pad is approach pad2*/ +#define SENS_TOUCH_APPROACH_PAD2 0x0000000F +#define SENS_TOUCH_APPROACH_PAD2_M ((SENS_TOUCH_APPROACH_PAD2_V) << (SENS_TOUCH_APPROACH_PAD2_S)) +#define SENS_TOUCH_APPROACH_PAD2_V 0xF +#define SENS_TOUCH_APPROACH_PAD2_S 20 +/* SENS_TOUCH_UNIT_END : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: touch_unit_done*/ +#define SENS_TOUCH_UNIT_END (BIT(19)) +#define SENS_TOUCH_UNIT_END_M (BIT(19)) +#define SENS_TOUCH_UNIT_END_V 0x1 +#define SENS_TOUCH_UNIT_END_S 19 +/* SENS_TOUCH_DENOISE_END : RO ;bitpos:[18] ;default: 1'd0 ; */ +/*description: touch_denoise_done*/ +#define SENS_TOUCH_DENOISE_END (BIT(18)) +#define SENS_TOUCH_DENOISE_END_M (BIT(18)) +#define SENS_TOUCH_DENOISE_END_V 0x1 +#define SENS_TOUCH_DENOISE_END_S 18 +/* SENS_TOUCH_DATA_SEL : R/W ;bitpos:[17:16] ;default: 2'd0 ; */ +/*description: 3: smooth data 2: baseline 1 0: raw_data*/ +#define SENS_TOUCH_DATA_SEL 0x00000003 +#define SENS_TOUCH_DATA_SEL_M ((SENS_TOUCH_DATA_SEL_V) << (SENS_TOUCH_DATA_SEL_S)) +#define SENS_TOUCH_DATA_SEL_V 0x3 +#define SENS_TOUCH_DATA_SEL_S 16 +/* SENS_TOUCH_STATUS_CLR : WO ;bitpos:[15] ;default: 1'd0 ; */ +/*description: clear all touch active status*/ +#define SENS_TOUCH_STATUS_CLR (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_M (BIT(15)) +#define SENS_TOUCH_STATUS_CLR_V 0x1 +#define SENS_TOUCH_STATUS_CLR_S 15 +/* SENS_TOUCH_OUTEN : R/W ;bitpos:[14:0] ;default: 15'h7FFF ; */ +/*description: touch controller output enable*/ +#define SENS_TOUCH_OUTEN 0x00007FFF +#define SENS_TOUCH_OUTEN_M ((SENS_TOUCH_OUTEN_V) << (SENS_TOUCH_OUTEN_S)) +#define SENS_TOUCH_OUTEN_V 0x7FFF +#define SENS_TOUCH_OUTEN_S 0 + +#define SENS_SAR_TOUCH_THRES1_REG (DR_REG_SENS_BASE + 0x0060) +/* SENS_TOUCH_OUT_TH1 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 1*/ +#define SENS_TOUCH_OUT_TH1 0x003FFFFF +#define SENS_TOUCH_OUT_TH1_M ((SENS_TOUCH_OUT_TH1_V) << (SENS_TOUCH_OUT_TH1_S)) +#define SENS_TOUCH_OUT_TH1_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH1_S 0 + +#define SENS_SAR_TOUCH_THRES2_REG (DR_REG_SENS_BASE + 0x0064) +/* SENS_TOUCH_OUT_TH2 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 2*/ +#define SENS_TOUCH_OUT_TH2 0x003FFFFF +#define SENS_TOUCH_OUT_TH2_M ((SENS_TOUCH_OUT_TH2_V) << (SENS_TOUCH_OUT_TH2_S)) +#define SENS_TOUCH_OUT_TH2_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH2_S 0 + +#define SENS_SAR_TOUCH_THRES3_REG (DR_REG_SENS_BASE + 0x0068) +/* SENS_TOUCH_OUT_TH3 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 3*/ +#define SENS_TOUCH_OUT_TH3 0x003FFFFF +#define SENS_TOUCH_OUT_TH3_M ((SENS_TOUCH_OUT_TH3_V) << (SENS_TOUCH_OUT_TH3_S)) +#define SENS_TOUCH_OUT_TH3_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH3_S 0 + +#define SENS_SAR_TOUCH_THRES4_REG (DR_REG_SENS_BASE + 0x006c) +/* SENS_TOUCH_OUT_TH4 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 4*/ +#define SENS_TOUCH_OUT_TH4 0x003FFFFF +#define SENS_TOUCH_OUT_TH4_M ((SENS_TOUCH_OUT_TH4_V) << (SENS_TOUCH_OUT_TH4_S)) +#define SENS_TOUCH_OUT_TH4_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH4_S 0 + +#define SENS_SAR_TOUCH_THRES5_REG (DR_REG_SENS_BASE + 0x0070) +/* SENS_TOUCH_OUT_TH5 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 5*/ +#define SENS_TOUCH_OUT_TH5 0x003FFFFF +#define SENS_TOUCH_OUT_TH5_M ((SENS_TOUCH_OUT_TH5_V) << (SENS_TOUCH_OUT_TH5_S)) +#define SENS_TOUCH_OUT_TH5_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH5_S 0 + +#define SENS_SAR_TOUCH_THRES6_REG (DR_REG_SENS_BASE + 0x0074) +/* SENS_TOUCH_OUT_TH6 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 6*/ +#define SENS_TOUCH_OUT_TH6 0x003FFFFF +#define SENS_TOUCH_OUT_TH6_M ((SENS_TOUCH_OUT_TH6_V) << (SENS_TOUCH_OUT_TH6_S)) +#define SENS_TOUCH_OUT_TH6_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH6_S 0 + +#define SENS_SAR_TOUCH_THRES7_REG (DR_REG_SENS_BASE + 0x0078) +/* SENS_TOUCH_OUT_TH7 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 7*/ +#define SENS_TOUCH_OUT_TH7 0x003FFFFF +#define SENS_TOUCH_OUT_TH7_M ((SENS_TOUCH_OUT_TH7_V) << (SENS_TOUCH_OUT_TH7_S)) +#define SENS_TOUCH_OUT_TH7_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH7_S 0 + +#define SENS_SAR_TOUCH_THRES8_REG (DR_REG_SENS_BASE + 0x007c) +/* SENS_TOUCH_OUT_TH8 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 8*/ +#define SENS_TOUCH_OUT_TH8 0x003FFFFF +#define SENS_TOUCH_OUT_TH8_M ((SENS_TOUCH_OUT_TH8_V) << (SENS_TOUCH_OUT_TH8_S)) +#define SENS_TOUCH_OUT_TH8_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH8_S 0 + +#define SENS_SAR_TOUCH_THRES9_REG (DR_REG_SENS_BASE + 0x0080) +/* SENS_TOUCH_OUT_TH9 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 9*/ +#define SENS_TOUCH_OUT_TH9 0x003FFFFF +#define SENS_TOUCH_OUT_TH9_M ((SENS_TOUCH_OUT_TH9_V) << (SENS_TOUCH_OUT_TH9_S)) +#define SENS_TOUCH_OUT_TH9_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH9_S 0 + +#define SENS_SAR_TOUCH_THRES10_REG (DR_REG_SENS_BASE + 0x0084) +/* SENS_TOUCH_OUT_TH10 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 10*/ +#define SENS_TOUCH_OUT_TH10 0x003FFFFF +#define SENS_TOUCH_OUT_TH10_M ((SENS_TOUCH_OUT_TH10_V) << (SENS_TOUCH_OUT_TH10_S)) +#define SENS_TOUCH_OUT_TH10_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH10_S 0 + +#define SENS_SAR_TOUCH_THRES11_REG (DR_REG_SENS_BASE + 0x0088) +/* SENS_TOUCH_OUT_TH11 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 11*/ +#define SENS_TOUCH_OUT_TH11 0x003FFFFF +#define SENS_TOUCH_OUT_TH11_M ((SENS_TOUCH_OUT_TH11_V) << (SENS_TOUCH_OUT_TH11_S)) +#define SENS_TOUCH_OUT_TH11_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH11_S 0 + +#define SENS_SAR_TOUCH_THRES12_REG (DR_REG_SENS_BASE + 0x008c) +/* SENS_TOUCH_OUT_TH12 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 12*/ +#define SENS_TOUCH_OUT_TH12 0x003FFFFF +#define SENS_TOUCH_OUT_TH12_M ((SENS_TOUCH_OUT_TH12_V) << (SENS_TOUCH_OUT_TH12_S)) +#define SENS_TOUCH_OUT_TH12_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH12_S 0 + +#define SENS_SAR_TOUCH_THRES13_REG (DR_REG_SENS_BASE + 0x0090) +/* SENS_TOUCH_OUT_TH13 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 13*/ +#define SENS_TOUCH_OUT_TH13 0x003FFFFF +#define SENS_TOUCH_OUT_TH13_M ((SENS_TOUCH_OUT_TH13_V) << (SENS_TOUCH_OUT_TH13_S)) +#define SENS_TOUCH_OUT_TH13_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH13_S 0 + +#define SENS_SAR_TOUCH_THRES14_REG (DR_REG_SENS_BASE + 0x0094) +/* SENS_TOUCH_OUT_TH14 : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: Finger threshold for touch pad 14*/ +#define SENS_TOUCH_OUT_TH14 0x003FFFFF +#define SENS_TOUCH_OUT_TH14_M ((SENS_TOUCH_OUT_TH14_V) << (SENS_TOUCH_OUT_TH14_S)) +#define SENS_TOUCH_OUT_TH14_V 0x3FFFFF +#define SENS_TOUCH_OUT_TH14_S 0 + +#define SENS_SAR_TOUCH_CHN_ST_REG (DR_REG_SENS_BASE + 0x00d4) +/* SENS_TOUCH_MEAS_DONE : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SENS_TOUCH_MEAS_DONE (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_M (BIT(31)) +#define SENS_TOUCH_MEAS_DONE_V 0x1 +#define SENS_TOUCH_MEAS_DONE_S 31 +/* SENS_TOUCH_CHANNEL_CLR : WO ;bitpos:[29:15] ;default: 15'd0 ; */ +/*description: Clear touch channel*/ +#define SENS_TOUCH_CHANNEL_CLR 0x00007FFF +#define SENS_TOUCH_CHANNEL_CLR_M ((SENS_TOUCH_CHANNEL_CLR_V) << (SENS_TOUCH_CHANNEL_CLR_S)) +#define SENS_TOUCH_CHANNEL_CLR_V 0x7FFF +#define SENS_TOUCH_CHANNEL_CLR_S 15 +/* SENS_TOUCH_PAD_ACTIVE : RO ;bitpos:[14:0] ;default: 15'd0 ; */ +/*description: touch active status*/ +#define SENS_TOUCH_PAD_ACTIVE 0x00007FFF +#define SENS_TOUCH_PAD_ACTIVE_M ((SENS_TOUCH_PAD_ACTIVE_V) << (SENS_TOUCH_PAD_ACTIVE_S)) +#define SENS_TOUCH_PAD_ACTIVE_V 0x7FFF +#define SENS_TOUCH_PAD_ACTIVE_S 0 + +#define SENS_SAR_TOUCH_STATUS0_REG (DR_REG_SENS_BASE + 0x00d8) +/* SENS_TOUCH_SCAN_CURR : RO ;bitpos:[25:22] ;default: 4'd0 ; */ +/*description: */ +#define SENS_TOUCH_SCAN_CURR 0x0000000F +#define SENS_TOUCH_SCAN_CURR_M ((SENS_TOUCH_SCAN_CURR_V) << (SENS_TOUCH_SCAN_CURR_S)) +#define SENS_TOUCH_SCAN_CURR_V 0xF +#define SENS_TOUCH_SCAN_CURR_S 22 +/* SENS_TOUCH_DENOISE_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: the counter for touch pad 0*/ +#define SENS_TOUCH_DENOISE_DATA 0x003FFFFF +#define SENS_TOUCH_DENOISE_DATA_M ((SENS_TOUCH_DENOISE_DATA_V) << (SENS_TOUCH_DENOISE_DATA_S)) +#define SENS_TOUCH_DENOISE_DATA_V 0x3FFFFF +#define SENS_TOUCH_DENOISE_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS1_REG (DR_REG_SENS_BASE + 0x00dc) +/* SENS_TOUCH_PAD1_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD1_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD1_DEBOUNCE_M ((SENS_TOUCH_PAD1_DEBOUNCE_V) << (SENS_TOUCH_PAD1_DEBOUNCE_S)) +#define SENS_TOUCH_PAD1_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD1_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD1_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD1_DATA 0x003FFFFF +#define SENS_TOUCH_PAD1_DATA_M ((SENS_TOUCH_PAD1_DATA_V) << (SENS_TOUCH_PAD1_DATA_S)) +#define SENS_TOUCH_PAD1_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD1_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS2_REG (DR_REG_SENS_BASE + 0x00e0) +/* SENS_TOUCH_PAD2_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD2_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD2_DEBOUNCE_M ((SENS_TOUCH_PAD2_DEBOUNCE_V) << (SENS_TOUCH_PAD2_DEBOUNCE_S)) +#define SENS_TOUCH_PAD2_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD2_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD2_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD2_DATA 0x003FFFFF +#define SENS_TOUCH_PAD2_DATA_M ((SENS_TOUCH_PAD2_DATA_V) << (SENS_TOUCH_PAD2_DATA_S)) +#define SENS_TOUCH_PAD2_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD2_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS3_REG (DR_REG_SENS_BASE + 0x00e4) +/* SENS_TOUCH_PAD3_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD3_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD3_DEBOUNCE_M ((SENS_TOUCH_PAD3_DEBOUNCE_V) << (SENS_TOUCH_PAD3_DEBOUNCE_S)) +#define SENS_TOUCH_PAD3_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD3_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD3_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD3_DATA 0x003FFFFF +#define SENS_TOUCH_PAD3_DATA_M ((SENS_TOUCH_PAD3_DATA_V) << (SENS_TOUCH_PAD3_DATA_S)) +#define SENS_TOUCH_PAD3_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD3_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS4_REG (DR_REG_SENS_BASE + 0x00e8) +/* SENS_TOUCH_PAD4_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD4_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD4_DEBOUNCE_M ((SENS_TOUCH_PAD4_DEBOUNCE_V) << (SENS_TOUCH_PAD4_DEBOUNCE_S)) +#define SENS_TOUCH_PAD4_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD4_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD4_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD4_DATA 0x003FFFFF +#define SENS_TOUCH_PAD4_DATA_M ((SENS_TOUCH_PAD4_DATA_V) << (SENS_TOUCH_PAD4_DATA_S)) +#define SENS_TOUCH_PAD4_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD4_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS5_REG (DR_REG_SENS_BASE + 0x00ec) +/* SENS_TOUCH_PAD5_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD5_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD5_DEBOUNCE_M ((SENS_TOUCH_PAD5_DEBOUNCE_V) << (SENS_TOUCH_PAD5_DEBOUNCE_S)) +#define SENS_TOUCH_PAD5_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD5_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD5_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD5_DATA 0x003FFFFF +#define SENS_TOUCH_PAD5_DATA_M ((SENS_TOUCH_PAD5_DATA_V) << (SENS_TOUCH_PAD5_DATA_S)) +#define SENS_TOUCH_PAD5_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD5_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS6_REG (DR_REG_SENS_BASE + 0x00f0) +/* SENS_TOUCH_PAD6_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD6_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD6_DEBOUNCE_M ((SENS_TOUCH_PAD6_DEBOUNCE_V) << (SENS_TOUCH_PAD6_DEBOUNCE_S)) +#define SENS_TOUCH_PAD6_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD6_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD6_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD6_DATA 0x003FFFFF +#define SENS_TOUCH_PAD6_DATA_M ((SENS_TOUCH_PAD6_DATA_V) << (SENS_TOUCH_PAD6_DATA_S)) +#define SENS_TOUCH_PAD6_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD6_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS7_REG (DR_REG_SENS_BASE + 0x00f4) +/* SENS_TOUCH_PAD7_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD7_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD7_DEBOUNCE_M ((SENS_TOUCH_PAD7_DEBOUNCE_V) << (SENS_TOUCH_PAD7_DEBOUNCE_S)) +#define SENS_TOUCH_PAD7_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD7_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD7_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD7_DATA 0x003FFFFF +#define SENS_TOUCH_PAD7_DATA_M ((SENS_TOUCH_PAD7_DATA_V) << (SENS_TOUCH_PAD7_DATA_S)) +#define SENS_TOUCH_PAD7_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD7_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS8_REG (DR_REG_SENS_BASE + 0x00f8) +/* SENS_TOUCH_PAD8_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD8_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD8_DEBOUNCE_M ((SENS_TOUCH_PAD8_DEBOUNCE_V) << (SENS_TOUCH_PAD8_DEBOUNCE_S)) +#define SENS_TOUCH_PAD8_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD8_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD8_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD8_DATA 0x003FFFFF +#define SENS_TOUCH_PAD8_DATA_M ((SENS_TOUCH_PAD8_DATA_V) << (SENS_TOUCH_PAD8_DATA_S)) +#define SENS_TOUCH_PAD8_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD8_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS9_REG (DR_REG_SENS_BASE + 0x00fc) +/* SENS_TOUCH_PAD9_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD9_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD9_DEBOUNCE_M ((SENS_TOUCH_PAD9_DEBOUNCE_V) << (SENS_TOUCH_PAD9_DEBOUNCE_S)) +#define SENS_TOUCH_PAD9_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD9_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD9_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD9_DATA 0x003FFFFF +#define SENS_TOUCH_PAD9_DATA_M ((SENS_TOUCH_PAD9_DATA_V) << (SENS_TOUCH_PAD9_DATA_S)) +#define SENS_TOUCH_PAD9_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD9_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS10_REG (DR_REG_SENS_BASE + 0x0100) +/* SENS_TOUCH_PAD10_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD10_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD10_DEBOUNCE_M ((SENS_TOUCH_PAD10_DEBOUNCE_V) << (SENS_TOUCH_PAD10_DEBOUNCE_S)) +#define SENS_TOUCH_PAD10_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD10_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD10_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD10_DATA 0x003FFFFF +#define SENS_TOUCH_PAD10_DATA_M ((SENS_TOUCH_PAD10_DATA_V) << (SENS_TOUCH_PAD10_DATA_S)) +#define SENS_TOUCH_PAD10_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD10_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS11_REG (DR_REG_SENS_BASE + 0x0104) +/* SENS_TOUCH_PAD11_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD11_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD11_DEBOUNCE_M ((SENS_TOUCH_PAD11_DEBOUNCE_V) << (SENS_TOUCH_PAD11_DEBOUNCE_S)) +#define SENS_TOUCH_PAD11_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD11_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD11_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD11_DATA 0x003FFFFF +#define SENS_TOUCH_PAD11_DATA_M ((SENS_TOUCH_PAD11_DATA_V) << (SENS_TOUCH_PAD11_DATA_S)) +#define SENS_TOUCH_PAD11_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD11_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS12_REG (DR_REG_SENS_BASE + 0x0108) +/* SENS_TOUCH_PAD12_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD12_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD12_DEBOUNCE_M ((SENS_TOUCH_PAD12_DEBOUNCE_V) << (SENS_TOUCH_PAD12_DEBOUNCE_S)) +#define SENS_TOUCH_PAD12_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD12_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD12_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD12_DATA 0x003FFFFF +#define SENS_TOUCH_PAD12_DATA_M ((SENS_TOUCH_PAD12_DATA_V) << (SENS_TOUCH_PAD12_DATA_S)) +#define SENS_TOUCH_PAD12_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD12_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS13_REG (DR_REG_SENS_BASE + 0x010c) +/* SENS_TOUCH_PAD13_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD13_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD13_DEBOUNCE_M ((SENS_TOUCH_PAD13_DEBOUNCE_V) << (SENS_TOUCH_PAD13_DEBOUNCE_S)) +#define SENS_TOUCH_PAD13_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD13_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD13_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD13_DATA 0x003FFFFF +#define SENS_TOUCH_PAD13_DATA_M ((SENS_TOUCH_PAD13_DATA_V) << (SENS_TOUCH_PAD13_DATA_S)) +#define SENS_TOUCH_PAD13_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD13_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS14_REG (DR_REG_SENS_BASE + 0x0110) +/* SENS_TOUCH_PAD14_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_PAD14_DEBOUNCE 0x00000007 +#define SENS_TOUCH_PAD14_DEBOUNCE_M ((SENS_TOUCH_PAD14_DEBOUNCE_V) << (SENS_TOUCH_PAD14_DEBOUNCE_S)) +#define SENS_TOUCH_PAD14_DEBOUNCE_V 0x7 +#define SENS_TOUCH_PAD14_DEBOUNCE_S 29 +/* SENS_TOUCH_PAD14_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_PAD14_DATA 0x003FFFFF +#define SENS_TOUCH_PAD14_DATA_M ((SENS_TOUCH_PAD14_DATA_V) << (SENS_TOUCH_PAD14_DATA_S)) +#define SENS_TOUCH_PAD14_DATA_V 0x3FFFFF +#define SENS_TOUCH_PAD14_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS15_REG (DR_REG_SENS_BASE + 0x0114) +/* SENS_TOUCH_SLP_DEBOUNCE : RO ;bitpos:[31:29] ;default: 3'd0 ; */ +/*description: */ +#define SENS_TOUCH_SLP_DEBOUNCE 0x00000007 +#define SENS_TOUCH_SLP_DEBOUNCE_M ((SENS_TOUCH_SLP_DEBOUNCE_V) << (SENS_TOUCH_SLP_DEBOUNCE_S)) +#define SENS_TOUCH_SLP_DEBOUNCE_V 0x7 +#define SENS_TOUCH_SLP_DEBOUNCE_S 29 +/* SENS_TOUCH_SLP_DATA : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define SENS_TOUCH_SLP_DATA 0x003FFFFF +#define SENS_TOUCH_SLP_DATA_M ((SENS_TOUCH_SLP_DATA_V) << (SENS_TOUCH_SLP_DATA_S)) +#define SENS_TOUCH_SLP_DATA_V 0x3FFFFF +#define SENS_TOUCH_SLP_DATA_S 0 + +#define SENS_SAR_TOUCH_STATUS16_REG (DR_REG_SENS_BASE + 0x0118) +/* SENS_TOUCH_SLP_APPROACH_CNT : RO ;bitpos:[31:24] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_SLP_APPROACH_CNT 0x000000FF +#define SENS_TOUCH_SLP_APPROACH_CNT_M ((SENS_TOUCH_SLP_APPROACH_CNT_V) << (SENS_TOUCH_SLP_APPROACH_CNT_S)) +#define SENS_TOUCH_SLP_APPROACH_CNT_V 0xFF +#define SENS_TOUCH_SLP_APPROACH_CNT_S 24 +/* SENS_TOUCH_APPROACH_PAD0_CNT : RO ;bitpos:[23:16] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_APPROACH_PAD0_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD0_CNT_M ((SENS_TOUCH_APPROACH_PAD0_CNT_V) << (SENS_TOUCH_APPROACH_PAD0_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD0_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD0_CNT_S 16 +/* SENS_TOUCH_APPROACH_PAD1_CNT : RO ;bitpos:[15:8] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_APPROACH_PAD1_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD1_CNT_M ((SENS_TOUCH_APPROACH_PAD1_CNT_V) << (SENS_TOUCH_APPROACH_PAD1_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD1_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD1_CNT_S 8 +/* SENS_TOUCH_APPROACH_PAD2_CNT : RO ;bitpos:[7:0] ;default: 8'd0 ; */ +/*description: */ +#define SENS_TOUCH_APPROACH_PAD2_CNT 0x000000FF +#define SENS_TOUCH_APPROACH_PAD2_CNT_M ((SENS_TOUCH_APPROACH_PAD2_CNT_V) << (SENS_TOUCH_APPROACH_PAD2_CNT_S)) +#define SENS_TOUCH_APPROACH_PAD2_CNT_V 0xFF +#define SENS_TOUCH_APPROACH_PAD2_CNT_S 0 + +#define SENS_SAR_DAC_CTRL1_REG (DR_REG_SENS_BASE + 0x011c) +/* SENS_DAC_CLK_INV : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: 1: invert PDAC_CLK*/ +#define SENS_DAC_CLK_INV (BIT(25)) +#define SENS_DAC_CLK_INV_M (BIT(25)) +#define SENS_DAC_CLK_INV_V 0x1 +#define SENS_DAC_CLK_INV_S 25 +/* SENS_DAC_CLK_FORCE_HIGH : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: 1: force PDAC_CLK to high*/ +#define SENS_DAC_CLK_FORCE_HIGH (BIT(24)) +#define SENS_DAC_CLK_FORCE_HIGH_M (BIT(24)) +#define SENS_DAC_CLK_FORCE_HIGH_V 0x1 +#define SENS_DAC_CLK_FORCE_HIGH_S 24 +/* SENS_DAC_CLK_FORCE_LOW : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: 1: force PDAC_CLK to low*/ +#define SENS_DAC_CLK_FORCE_LOW (BIT(23)) +#define SENS_DAC_CLK_FORCE_LOW_M (BIT(23)) +#define SENS_DAC_CLK_FORCE_LOW_V 0x1 +#define SENS_DAC_CLK_FORCE_LOW_S 23 +/* SENS_DAC_DIG_FORCE : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: 1: DAC1 & DAC2 use DMA*/ +#define SENS_DAC_DIG_FORCE (BIT(22)) +#define SENS_DAC_DIG_FORCE_M (BIT(22)) +#define SENS_DAC_DIG_FORCE_V 0x1 +#define SENS_DAC_DIG_FORCE_S 22 +/* SENS_DEBUG_BIT_SEL : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ +/*description: */ +#define SENS_DEBUG_BIT_SEL 0x0000001F +#define SENS_DEBUG_BIT_SEL_M ((SENS_DEBUG_BIT_SEL_V) << (SENS_DEBUG_BIT_SEL_S)) +#define SENS_DEBUG_BIT_SEL_V 0x1F +#define SENS_DEBUG_BIT_SEL_S 17 +/* SENS_SW_TONE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1: enable CW generator*/ +#define SENS_SW_TONE_EN (BIT(16)) +#define SENS_SW_TONE_EN_M (BIT(16)) +#define SENS_SW_TONE_EN_V 0x1 +#define SENS_SW_TONE_EN_S 16 +/* SENS_SW_FSTEP : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: frequency step for CW generator*/ +#define SENS_SW_FSTEP 0x0000FFFF +#define SENS_SW_FSTEP_M ((SENS_SW_FSTEP_V) << (SENS_SW_FSTEP_S)) +#define SENS_SW_FSTEP_V 0xFFFF +#define SENS_SW_FSTEP_S 0 + +#define SENS_SAR_DAC_CTRL2_REG (DR_REG_SENS_BASE + 0x0120) +/* SENS_DAC_CW_EN2 : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: 1: to select CW generator as source to PDAC2_DAC[7:0]*/ +#define SENS_DAC_CW_EN2 (BIT(25)) +#define SENS_DAC_CW_EN2_M (BIT(25)) +#define SENS_DAC_CW_EN2_V 0x1 +#define SENS_DAC_CW_EN2_S 25 +/* SENS_DAC_CW_EN1 : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: 1: to select CW generator as source to PDAC1_DAC[7:0]*/ +#define SENS_DAC_CW_EN1 (BIT(24)) +#define SENS_DAC_CW_EN1_M (BIT(24)) +#define SENS_DAC_CW_EN1_V 0x1 +#define SENS_DAC_CW_EN1_S 24 +/* SENS_DAC_INV2 : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: 00: do not invert any bits*/ +#define SENS_DAC_INV2 0x00000003 +#define SENS_DAC_INV2_M ((SENS_DAC_INV2_V) << (SENS_DAC_INV2_S)) +#define SENS_DAC_INV2_V 0x3 +#define SENS_DAC_INV2_S 22 +/* SENS_DAC_INV1 : R/W ;bitpos:[21:20] ;default: 2'b0 ; */ +/*description: 00: do not invert any bits*/ +#define SENS_DAC_INV1 0x00000003 +#define SENS_DAC_INV1_M ((SENS_DAC_INV1_V) << (SENS_DAC_INV1_S)) +#define SENS_DAC_INV1_V 0x3 +#define SENS_DAC_INV1_S 20 +/* SENS_DAC_SCALE2 : R/W ;bitpos:[19:18] ;default: 2'b0 ; */ +/*description: 00: no scale*/ +#define SENS_DAC_SCALE2 0x00000003 +#define SENS_DAC_SCALE2_M ((SENS_DAC_SCALE2_V) << (SENS_DAC_SCALE2_S)) +#define SENS_DAC_SCALE2_V 0x3 +#define SENS_DAC_SCALE2_S 18 +/* SENS_DAC_SCALE1 : R/W ;bitpos:[17:16] ;default: 2'b0 ; */ +/*description: 00: no scale*/ +#define SENS_DAC_SCALE1 0x00000003 +#define SENS_DAC_SCALE1_M ((SENS_DAC_SCALE1_V) << (SENS_DAC_SCALE1_S)) +#define SENS_DAC_SCALE1_V 0x3 +#define SENS_DAC_SCALE1_S 16 +/* SENS_DAC_DC2 : R/W ;bitpos:[15:8] ;default: 8'b0 ; */ +/*description: DC offset for DAC2 CW generator*/ +#define SENS_DAC_DC2 0x000000FF +#define SENS_DAC_DC2_M ((SENS_DAC_DC2_V) << (SENS_DAC_DC2_S)) +#define SENS_DAC_DC2_V 0xFF +#define SENS_DAC_DC2_S 8 +/* SENS_DAC_DC1 : R/W ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: DC offset for DAC1 CW generator*/ +#define SENS_DAC_DC1 0x000000FF +#define SENS_DAC_DC1_M ((SENS_DAC_DC1_V) << (SENS_DAC_DC1_S)) +#define SENS_DAC_DC1_V 0xFF +#define SENS_DAC_DC1_S 0 + +#define SENS_SAR_COCPU_STATE_REG (DR_REG_SENS_BASE + 0x0124) +/* SENS_COCPU_EBREAK : RO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: check cocpu whether in ebreak*/ +#define SENS_COCPU_EBREAK (BIT(30)) +#define SENS_COCPU_EBREAK_M (BIT(30)) +#define SENS_COCPU_EBREAK_V 0x1 +#define SENS_COCPU_EBREAK_S 30 +/* SENS_COCPU_TRAP : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: check cocpu whether in trap state*/ +#define SENS_COCPU_TRAP (BIT(29)) +#define SENS_COCPU_TRAP_M (BIT(29)) +#define SENS_COCPU_TRAP_V 0x1 +#define SENS_COCPU_TRAP_S 29 +/* SENS_COCPU_EOI : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: check cocpu whether in interrupt state*/ +#define SENS_COCPU_EOI (BIT(28)) +#define SENS_COCPU_EOI_M (BIT(28)) +#define SENS_COCPU_EOI_V 0x1 +#define SENS_COCPU_EOI_S 28 +/* SENS_COCPU_RESET_N : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: check cocpu whether in reset state*/ +#define SENS_COCPU_RESET_N (BIT(27)) +#define SENS_COCPU_RESET_N_M (BIT(27)) +#define SENS_COCPU_RESET_N_V 0x1 +#define SENS_COCPU_RESET_N_S 27 +/* SENS_COCPU_CLK_EN_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: check cocpu whether clk on*/ +#define SENS_COCPU_CLK_EN_ST (BIT(26)) +#define SENS_COCPU_CLK_EN_ST_M (BIT(26)) +#define SENS_COCPU_CLK_EN_ST_V 0x1 +#define SENS_COCPU_CLK_EN_ST_S 26 +/* SENS_COCPU_DBG_TRIGGER : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: trigger cocpu debug registers*/ +#define SENS_COCPU_DBG_TRIGGER (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_M (BIT(25)) +#define SENS_COCPU_DBG_TRIGGER_V 0x1 +#define SENS_COCPU_DBG_TRIGGER_S 25 + +#define SENS_SAR_COCPU_INT_RAW_REG (DR_REG_SENS_BASE + 0x0128) +/* SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_RAW_S 11 +/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_RAW_S 10 +/* SENS_COCPU_TOUCH_TIMEOUT_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_RAW_S 9 +/* SENS_COCPU_SWD_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: int from super watch dog*/ +#define SENS_COCPU_SWD_INT_RAW (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_M (BIT(8)) +#define SENS_COCPU_SWD_INT_RAW_V 0x1 +#define SENS_COCPU_SWD_INT_RAW_S 8 +/* SENS_COCPU_SW_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: int from software*/ +#define SENS_COCPU_SW_INT_RAW (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_M (BIT(7)) +#define SENS_COCPU_SW_INT_RAW_V 0x1 +#define SENS_COCPU_SW_INT_RAW_S 7 +/* SENS_COCPU_START_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: int from start*/ +#define SENS_COCPU_START_INT_RAW (BIT(6)) +#define SENS_COCPU_START_INT_RAW_M (BIT(6)) +#define SENS_COCPU_START_INT_RAW_V 0x1 +#define SENS_COCPU_START_INT_RAW_S 6 +/* SENS_COCPU_TSENS_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: int from tsens*/ +#define SENS_COCPU_TSENS_INT_RAW (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_RAW_V 0x1 +#define SENS_COCPU_TSENS_INT_RAW_S 5 +/* SENS_COCPU_SENS2_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: int from saradc2*/ +#define SENS_COCPU_SENS2_INT_RAW (BIT(4)) +#define SENS_COCPU_SENS2_INT_RAW_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_RAW_V 0x1 +#define SENS_COCPU_SENS2_INT_RAW_S 4 +/* SENS_COCPU_SENS1_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: int from saradc1*/ +#define SENS_COCPU_SENS1_INT_RAW (BIT(3)) +#define SENS_COCPU_SENS1_INT_RAW_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_RAW_V 0x1 +#define SENS_COCPU_SENS1_INT_RAW_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: int from touch active*/ +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_RAW_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: int from touch inactive*/ +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_RAW_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: int from touch done*/ +#define SENS_COCPU_TOUCH_DONE_INT_RAW (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_RAW_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_RAW_S 0 + +#define SENS_SAR_COCPU_INT_ENA_REG (DR_REG_SENS_BASE + 0x012c) +/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_S 11 +/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_S 10 +/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_S 9 +/* SENS_COCPU_SWD_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_ENA (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_S 8 +/* SENS_COCPU_SW_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: cocpu int enable*/ +#define SENS_COCPU_SW_INT_ENA (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_V 0x1 +#define SENS_COCPU_SW_INT_ENA_S 7 +/* SENS_COCPU_START_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_ENA (BIT(6)) +#define SENS_COCPU_START_INT_ENA_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_V 0x1 +#define SENS_COCPU_START_INT_ENA_S 6 +/* SENS_COCPU_TSENS_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_ENA (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_S 5 +/* SENS_COCPU_SENS2_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_ENA (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_V 0x1 +#define SENS_COCPU_SENS2_INT_ENA_S 4 +/* SENS_COCPU_SENS1_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_ENA (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_V 0x1 +#define SENS_COCPU_SENS1_INT_ENA_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_ENA (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_S 0 + +#define SENS_SAR_COCPU_INT_ST_REG (DR_REG_SENS_BASE + 0x0130) +/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ST_S 11 +/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ST_S 10 +/* SENS_COCPU_TOUCH_TIMEOUT_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ST_S 9 +/* SENS_COCPU_SWD_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_ST (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ST_V 0x1 +#define SENS_COCPU_SWD_INT_ST_S 8 +/* SENS_COCPU_SW_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: cocpu int status*/ +#define SENS_COCPU_SW_INT_ST (BIT(7)) +#define SENS_COCPU_SW_INT_ST_M (BIT(7)) +#define SENS_COCPU_SW_INT_ST_V 0x1 +#define SENS_COCPU_SW_INT_ST_S 7 +/* SENS_COCPU_START_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_ST (BIT(6)) +#define SENS_COCPU_START_INT_ST_M (BIT(6)) +#define SENS_COCPU_START_INT_ST_V 0x1 +#define SENS_COCPU_START_INT_ST_S 6 +/* SENS_COCPU_TSENS_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_ST (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ST_V 0x1 +#define SENS_COCPU_TSENS_INT_ST_S 5 +/* SENS_COCPU_SENS2_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_ST (BIT(4)) +#define SENS_COCPU_SENS2_INT_ST_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ST_V 0x1 +#define SENS_COCPU_SENS2_INT_ST_S 4 +/* SENS_COCPU_SENS1_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_ST (BIT(3)) +#define SENS_COCPU_SENS1_INT_ST_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ST_V 0x1 +#define SENS_COCPU_SENS1_INT_ST_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ST_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ST_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_ST (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ST_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ST_S 0 + +#define SENS_SAR_COCPU_INT_CLR_REG (DR_REG_SENS_BASE + 0x0134) +/* SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_CLR_S 11 +/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_CLR_S 10 +/* SENS_COCPU_TOUCH_TIMEOUT_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_CLR_S 9 +/* SENS_COCPU_SWD_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_CLR (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_M (BIT(8)) +#define SENS_COCPU_SWD_INT_CLR_V 0x1 +#define SENS_COCPU_SWD_INT_CLR_S 8 +/* SENS_COCPU_SW_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: cocpu int clear*/ +#define SENS_COCPU_SW_INT_CLR (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_M (BIT(7)) +#define SENS_COCPU_SW_INT_CLR_V 0x1 +#define SENS_COCPU_SW_INT_CLR_S 7 +/* SENS_COCPU_START_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_CLR (BIT(6)) +#define SENS_COCPU_START_INT_CLR_M (BIT(6)) +#define SENS_COCPU_START_INT_CLR_V 0x1 +#define SENS_COCPU_START_INT_CLR_S 6 +/* SENS_COCPU_TSENS_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_CLR (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_CLR_V 0x1 +#define SENS_COCPU_TSENS_INT_CLR_S 5 +/* SENS_COCPU_SENS2_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_CLR (BIT(4)) +#define SENS_COCPU_SENS2_INT_CLR_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_CLR_V 0x1 +#define SENS_COCPU_SENS2_INT_CLR_S 4 +/* SENS_COCPU_SENS1_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_CLR (BIT(3)) +#define SENS_COCPU_SENS1_INT_CLR_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_CLR_V 0x1 +#define SENS_COCPU_SENS1_INT_CLR_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_CLR_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_CLR_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_CLR (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_CLR_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_CLR_S 0 + +#define SENS_SAR_COCPU_DEBUG_REG (DR_REG_SENS_BASE + 0x0138) +/* SENS_COCPU_MEM_ADDR : RO ;bitpos:[31:19] ;default: 13'd0 ; */ +/*description: cocpu mem address output*/ +#define SENS_COCPU_MEM_ADDR 0x00001FFF +#define SENS_COCPU_MEM_ADDR_M ((SENS_COCPU_MEM_ADDR_V) << (SENS_COCPU_MEM_ADDR_S)) +#define SENS_COCPU_MEM_ADDR_V 0x1FFF +#define SENS_COCPU_MEM_ADDR_S 19 +/* SENS_COCPU_MEM_WEN : RO ;bitpos:[18:15] ;default: 4'd0 ; */ +/*description: cocpu mem write enable output*/ +#define SENS_COCPU_MEM_WEN 0x0000000F +#define SENS_COCPU_MEM_WEN_M ((SENS_COCPU_MEM_WEN_V) << (SENS_COCPU_MEM_WEN_S)) +#define SENS_COCPU_MEM_WEN_V 0xF +#define SENS_COCPU_MEM_WEN_S 15 +/* SENS_COCPU_MEM_RDY : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: cocpu mem ready input*/ +#define SENS_COCPU_MEM_RDY (BIT(14)) +#define SENS_COCPU_MEM_RDY_M (BIT(14)) +#define SENS_COCPU_MEM_RDY_V 0x1 +#define SENS_COCPU_MEM_RDY_S 14 +/* SENS_COCPU_MEM_VLD : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: cocpu mem valid output*/ +#define SENS_COCPU_MEM_VLD (BIT(13)) +#define SENS_COCPU_MEM_VLD_M (BIT(13)) +#define SENS_COCPU_MEM_VLD_V 0x1 +#define SENS_COCPU_MEM_VLD_S 13 +/* SENS_COCPU_PC : RO ;bitpos:[12:0] ;default: 13'd0 ; */ +/*description: cocpu Program counter*/ +#define SENS_COCPU_PC 0x00001FFF +#define SENS_COCPU_PC_M ((SENS_COCPU_PC_V) << (SENS_COCPU_PC_S)) +#define SENS_COCPU_PC_V 0x1FFF +#define SENS_COCPU_PC_S 0 + +#define SENS_SAR_HALL_CTRL_REG (DR_REG_SENS_BASE + 0x013c) +/* SENS_HALL_PHASE_FORCE : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: 1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled + by FSM in ULP-coprocessor*/ +#define SENS_HALL_PHASE_FORCE (BIT(31)) +#define SENS_HALL_PHASE_FORCE_M (BIT(31)) +#define SENS_HALL_PHASE_FORCE_V 0x1 +#define SENS_HALL_PHASE_FORCE_S 31 +/* SENS_HALL_PHASE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Reverse phase of hall sensor*/ +#define SENS_HALL_PHASE (BIT(30)) +#define SENS_HALL_PHASE_M (BIT(30)) +#define SENS_HALL_PHASE_V 0x1 +#define SENS_HALL_PHASE_S 30 +/* SENS_XPD_HALL_FORCE : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: 1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by + FSM in ULP-coprocessor*/ +#define SENS_XPD_HALL_FORCE (BIT(29)) +#define SENS_XPD_HALL_FORCE_M (BIT(29)) +#define SENS_XPD_HALL_FORCE_V 0x1 +#define SENS_XPD_HALL_FORCE_S 29 +/* SENS_XPD_HALL : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Power on hall sensor and connect to VP and VN*/ +#define SENS_XPD_HALL (BIT(28)) +#define SENS_XPD_HALL_M (BIT(28)) +#define SENS_XPD_HALL_V 0x1 +#define SENS_XPD_HALL_S 28 + +#define SENS_SAR_NOUSE_REG (DR_REG_SENS_BASE + 0x0140) +/* SENS_SAR_NOUSE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SENS_SAR_NOUSE 0xFFFFFFFF +#define SENS_SAR_NOUSE_M ((SENS_SAR_NOUSE_V) << (SENS_SAR_NOUSE_S)) +#define SENS_SAR_NOUSE_V 0xFFFFFFFF +#define SENS_SAR_NOUSE_S 0 + +#define SENS_SAR_PERI_CLK_GATE_CONF_REG (DR_REG_SENS_BASE + 0x0144) +/* SENS_IOMUX_CLK_EN : R/W ;bitpos:[31] ;default: 1'd0 ; */ +/*description: */ +#define SENS_IOMUX_CLK_EN (BIT(31)) +#define SENS_IOMUX_CLK_EN_M (BIT(31)) +#define SENS_IOMUX_CLK_EN_V 0x1 +#define SENS_IOMUX_CLK_EN_S 31 +/* SENS_CLK_EN : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SENS_CLK_EN (BIT(30)) +#define SENS_CLK_EN_M (BIT(30)) +#define SENS_CLK_EN_V 0x1 +#define SENS_CLK_EN_S 30 +/* SENS_TSENS_CLK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SENS_TSENS_CLK_EN (BIT(29)) +#define SENS_TSENS_CLK_EN_M (BIT(29)) +#define SENS_TSENS_CLK_EN_V 0x1 +#define SENS_TSENS_CLK_EN_S 29 +/* SENS_RTC_I2C_CLK_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SENS_RTC_I2C_CLK_EN (BIT(27)) +#define SENS_RTC_I2C_CLK_EN_M (BIT(27)) +#define SENS_RTC_I2C_CLK_EN_V 0x1 +#define SENS_RTC_I2C_CLK_EN_S 27 +/* SENS_DAC_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SENS_DAC_CLK_EN (BIT(26)) +#define SENS_DAC_CLK_EN_M (BIT(26)) +#define SENS_DAC_CLK_EN_V 0x1 +#define SENS_DAC_CLK_EN_S 26 + +#define SENS_SAR_PERI_RESET_CONF_REG (DR_REG_SENS_BASE + 0x0148) +/* SENS_RESET : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SENS_RESET (BIT(30)) +#define SENS_RESET_M (BIT(30)) +#define SENS_RESET_V 0x1 +#define SENS_RESET_S 30 +/* SENS_TSENS_RESET : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SENS_TSENS_RESET (BIT(29)) +#define SENS_TSENS_RESET_M (BIT(29)) +#define SENS_TSENS_RESET_V 0x1 +#define SENS_TSENS_RESET_S 29 +/* SENS_RTC_I2C_RESET : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SENS_RTC_I2C_RESET (BIT(27)) +#define SENS_RTC_I2C_RESET_M (BIT(27)) +#define SENS_RTC_I2C_RESET_V 0x1 +#define SENS_RTC_I2C_RESET_S 27 +/* SENS_DAC_RESET : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SENS_DAC_RESET (BIT(26)) +#define SENS_DAC_RESET_M (BIT(26)) +#define SENS_DAC_RESET_V 0x1 +#define SENS_DAC_RESET_S 26 +/* SENS_COCPU_RESET : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_RESET (BIT(25)) +#define SENS_COCPU_RESET_M (BIT(25)) +#define SENS_COCPU_RESET_V 0x1 +#define SENS_COCPU_RESET_S 25 + +#define SENS_SAR_COCPU_INT_ENA_W1TS_REG (DR_REG_SENS_BASE + 0x014c) +/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TS_S 11 +/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TS_S 10 +/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TS_S 9 +/* SENS_COCPU_SWD_INT_ENA_W1TS : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_ENA_W1TS (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TS_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_W1TS_S 8 +/* SENS_COCPU_SW_INT_ENA_W1TS : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SW_INT_ENA_W1TS (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TS_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SW_INT_ENA_W1TS_S 7 +/* SENS_COCPU_START_INT_ENA_W1TS : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_ENA_W1TS (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TS_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_START_INT_ENA_W1TS_S 6 +/* SENS_COCPU_TSENS_INT_ENA_W1TS : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_ENA_W1TS (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TS_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_W1TS_S 5 +/* SENS_COCPU_SENS2_INT_ENA_W1TS : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_ENA_W1TS (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_W1TS_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SENS2_INT_ENA_W1TS_S 4 +/* SENS_COCPU_SENS1_INT_ENA_W1TS : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_ENA_W1TS (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_W1TS_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_SENS1_INT_ENA_W1TS_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TS_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TS_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TS_S 0 + +#define SENS_SAR_COCPU_INT_ENA_W1TC_REG (DR_REG_SENS_BASE + 0x0150) +/* SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_M (BIT(11)) +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_SCAN_DONE_INT_ENA_W1TC_S 11 +/* SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_M (BIT(10)) +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_APPROACH_LOOP_DONE_INT_ENA_W1TC_S 10 +/* SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_M (BIT(9)) +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_TIMEOUT_INT_ENA_W1TC_S 9 +/* SENS_COCPU_SWD_INT_ENA_W1TC : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SWD_INT_ENA_W1TC (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TC_M (BIT(8)) +#define SENS_COCPU_SWD_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SWD_INT_ENA_W1TC_S 8 +/* SENS_COCPU_SW_INT_ENA_W1TC : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SW_INT_ENA_W1TC (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TC_M (BIT(7)) +#define SENS_COCPU_SW_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SW_INT_ENA_W1TC_S 7 +/* SENS_COCPU_START_INT_ENA_W1TC : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_START_INT_ENA_W1TC (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TC_M (BIT(6)) +#define SENS_COCPU_START_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_START_INT_ENA_W1TC_S 6 +/* SENS_COCPU_TSENS_INT_ENA_W1TC : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TSENS_INT_ENA_W1TC (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TC_M (BIT(5)) +#define SENS_COCPU_TSENS_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TSENS_INT_ENA_W1TC_S 5 +/* SENS_COCPU_SENS2_INT_ENA_W1TC : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS2_INT_ENA_W1TC (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_W1TC_M (BIT(4)) +#define SENS_COCPU_SENS2_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SENS2_INT_ENA_W1TC_S 4 +/* SENS_COCPU_SENS1_INT_ENA_W1TC : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_SENS1_INT_ENA_W1TC (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_W1TC_M (BIT(3)) +#define SENS_COCPU_SENS1_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_SENS1_INT_ENA_W1TC_S 3 +/* SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_M (BIT(2)) +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_ACTIVE_INT_ENA_W1TC_S 2 +/* SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_M (BIT(1)) +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_INACTIVE_INT_ENA_W1TC_S 1 +/* SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_M (BIT(0)) +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_V 0x1 +#define SENS_COCPU_TOUCH_DONE_INT_ENA_W1TC_S 0 + +#define SENS_SARDATE_REG (DR_REG_SENS_BASE + 0x0154) +/* SENS_SAR_DATE : R/W ;bitpos:[27:0] ;default: 28'h1909160 ; */ +/*description: */ +#define SENS_SAR_DATE 0x0FFFFFFF +#define SENS_SAR_DATE_M ((SENS_SAR_DATE_V) << (SENS_SAR_DATE_S)) +#define SENS_SAR_DATE_V 0xFFFFFFF +#define SENS_SAR_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sens_struct.h b/components/soc/soc/esp32s3/include/soc/sens_struct.h new file mode 100644 index 000000000..98f3680c2 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sens_struct.h @@ -0,0 +1,506 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t sar1_clk_div: 8; /*clock divider*/ + uint32_t reserved8: 10; + uint32_t sar1_clk_gated: 1; + uint32_t sar1_sample_num: 8; + uint32_t reserved27: 1; + uint32_t sar1_data_inv: 1; /*Invert SAR ADC1 data*/ + uint32_t sar1_int_en: 1; /*enable saradc1 to send out interrupt*/ + uint32_t reserved30: 2; + }; + uint32_t val; + } sar_reader1_ctrl; + uint32_t sar_reader1_status; /**/ + union { + struct { + uint32_t reserved0: 24; + uint32_t force_xpd_amp: 2; + uint32_t amp_rst_fb_force: 2; + uint32_t amp_short_ref_force: 2; + uint32_t amp_short_ref_gnd_force: 2; + }; + uint32_t val; + } sar_meas1_ctrl1; + union { + struct { + uint32_t meas1_data_sar: 16; /*SAR ADC1 data*/ + uint32_t meas1_done_sar: 1; /*SAR ADC1 conversion done indication*/ + uint32_t meas1_start_sar: 1; /*SAR ADC1 controller (in RTC) starts conversion*/ + uint32_t meas1_start_force: 1; /*1: SAR ADC1 controller (in RTC) is started by SW*/ + uint32_t sar1_en_pad: 12; /*SAR ADC1 pad enable bitmap*/ + uint32_t sar1_en_pad_force: 1; /*1: SAR ADC1 pad enable bitmap is controlled by SW*/ + }; + uint32_t val; + } sar_meas1_ctrl2; + union { + struct { + uint32_t reserved0: 31; + uint32_t sar1_dig_force: 1; /*1: SAR ADC1 controlled by DIG ADC1 CTRL*/ + }; + uint32_t val; + } sar_meas1_mux; + uint32_t sar_atten1; /*2-bit attenuation for each pad*/ + union { + struct { + uint32_t sar_amp_wait1: 16; + uint32_t sar_amp_wait2: 16; + }; + uint32_t val; + } sar_amp_ctrl1; + union { + struct { + uint32_t sar1_dac_xpd_fsm_idle: 1; + uint32_t xpd_sar_amp_fsm_idle: 1; + uint32_t amp_rst_fb_fsm_idle: 1; + uint32_t amp_short_ref_fsm_idle: 1; + uint32_t amp_short_ref_gnd_fsm_idle: 1; + uint32_t xpd_sar_fsm_idle: 1; + uint32_t sar_rstb_fsm_idle: 1; + uint32_t reserved7: 9; + uint32_t sar_amp_wait3: 16; + }; + uint32_t val; + } sar_amp_ctrl2; + union { + struct { + uint32_t sar1_dac_xpd_fsm: 4; + uint32_t xpd_sar_amp_fsm: 4; + uint32_t amp_rst_fb_fsm: 4; + uint32_t amp_short_ref_fsm: 4; + uint32_t amp_short_ref_gnd_fsm: 4; + uint32_t xpd_sar_fsm: 4; + uint32_t sar_rstb_fsm: 4; + uint32_t reserved28: 4; + }; + uint32_t val; + } sar_amp_ctrl3; + union { + struct { + uint32_t sar2_clk_div: 8; /*clock divider*/ + uint32_t reserved8: 8; + uint32_t sar2_wait_arb_cycle: 2; /*wait arbit stable after sar_done*/ + uint32_t sar2_clk_gated: 1; + uint32_t sar2_sample_num: 8; + uint32_t reserved27: 2; + uint32_t sar2_data_inv: 1; /*Invert SAR ADC2 data*/ + uint32_t sar2_int_en: 1; /*enable saradc2 to send out interrupt*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } sar_reader2_ctrl; + uint32_t sar_reader2_status; /**/ + union { + struct { + uint32_t sar2_cntl_state: 3; /*saradc2_cntl_fsm*/ + uint32_t sar2_pwdet_cal_en: 1; /*rtc control pwdet enable*/ + uint32_t sar2_pkdet_cal_en: 1; /*rtc control pkdet enable*/ + uint32_t sar2_en_test: 1; /*SAR2_EN_TEST*/ + uint32_t sar2_rstb_force: 2; + uint32_t sar2_standby_wait: 8; + uint32_t sar2_rstb_wait: 8; + uint32_t sar2_xpd_wait: 8; + }; + uint32_t val; + } sar_meas2_ctrl1; + union { + struct { + uint32_t meas2_data_sar: 16; /*SAR ADC2 data*/ + uint32_t meas2_done_sar: 1; /*SAR ADC2 conversion done indication*/ + uint32_t meas2_start_sar: 1; /*SAR ADC2 controller (in RTC) starts conversion*/ + uint32_t meas2_start_force: 1; /*1: SAR ADC2 controller (in RTC) is started by SW*/ + uint32_t sar2_en_pad: 12; /*SAR ADC2 pad enable bitmap*/ + uint32_t sar2_en_pad_force: 1; /*1: SAR ADC2 pad enable bitmap is controlled by SW*/ + }; + uint32_t val; + } sar_meas2_ctrl2; + union { + struct { + uint32_t reserved0: 28; + uint32_t sar2_pwdet_cct: 3; /*SAR2_PWDET_CCT*/ + uint32_t sar2_rtc_force: 1; /*in sleep force to use rtc to control ADC*/ + }; + uint32_t val; + } sar_meas2_mux; + uint32_t sar_atten2; /*2-bit attenuation for each pad*/ + union { + struct { + uint32_t reserved0: 29; + uint32_t force_xpd_sar: 2; + uint32_t sarclk_en: 1; + }; + uint32_t val; + } sar_power_xpd_sar; + union { + struct { + uint32_t i2c_slave_addr1: 11; + uint32_t i2c_slave_addr0: 11; + uint32_t meas_status: 8; + uint32_t reserved30: 2; + }; + uint32_t val; + } sar_slave_addr1; + union { + struct { + uint32_t i2c_slave_addr3: 11; + uint32_t i2c_slave_addr2: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } sar_slave_addr2; + union { + struct { + uint32_t i2c_slave_addr5: 11; + uint32_t i2c_slave_addr4: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } sar_slave_addr3; + union { + struct { + uint32_t i2c_slave_addr7: 11; + uint32_t i2c_slave_addr6: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } sar_slave_addr4; + union { + struct { + uint32_t tsens_out: 8; /*temperature sensor data out*/ + uint32_t tsens_ready: 1; /*indicate temperature sensor out ready*/ + uint32_t reserved9: 3; + uint32_t tsens_int_en: 1; /*enable temperature sensor to send out interrupt*/ + uint32_t tsens_in_inv: 1; /*invert temperature sensor data*/ + uint32_t tsens_clk_div: 8; /*temperature sensor clock divider*/ + uint32_t tsens_power_up: 1; /*temperature sensor power up*/ + uint32_t tsens_power_up_force: 1; /*1: dump out & power up controlled by SW*/ + uint32_t tsens_dump_out: 1; /*temperature sensor dump out*/ + uint32_t reserved25: 7; + }; + uint32_t val; + } sar_tctrl; + union { + struct { + uint32_t tsens_xpd_wait: 12; + uint32_t tsens_xpd_force: 2; + uint32_t tsens_clk_inv: 1; + uint32_t reserved15: 17; + }; + uint32_t val; + } sar_tctrl2; + union { + struct { + uint32_t sar_i2c_ctrl: 28; /*I2C control data*/ + uint32_t sar_i2c_start: 1; /*start I2C*/ + uint32_t sar_i2c_start_force: 1; /*1: I2C started by SW*/ + uint32_t reserved30: 2; + }; + uint32_t val; + } sar_i2c_ctrl; + union { + struct { + uint32_t touch_outen: 15; /*touch controller output enable*/ + uint32_t touch_status_clr: 1; /*clear all touch active status*/ + uint32_t touch_data_sel: 2; /*3: smooth data 2: baseline 1 0: raw_data*/ + uint32_t touch_denoise_end: 1; /*touch_denoise_done*/ + uint32_t touch_unit_end: 1; /*touch_unit_done*/ + uint32_t touch_approach_pad2: 4; /*indicate which pad is approach pad2*/ + uint32_t touch_approach_pad1: 4; /*indicate which pad is approach pad1*/ + uint32_t touch_approach_pad0: 4; /*indicate which pad is approach pad0*/ + }; + uint32_t val; + } sar_touch_conf; + union { + struct { + uint32_t thresh: 22; /*Finger threshold for touch pad 1*/ + uint32_t reserved22: 10; + }; + uint32_t val; + } touch_thresh[14]; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + union { + struct { + uint32_t touch_pad_active: 15; /*touch active status*/ + uint32_t touch_channel_clr: 15; /*Clear touch channel*/ + uint32_t reserved30: 1; + uint32_t touch_meas_done: 1; + }; + uint32_t val; + } sar_touch_chn_st; + union { + struct { + uint32_t touch_denoise_data: 22; /*the counter for touch pad 0*/ + uint32_t touch_scan_curr: 4; + uint32_t reserved26: 6; + }; + uint32_t val; + } sar_touch_status0; + union { + struct { + uint32_t touch_pad1_data: 22; + uint32_t reserved22: 7; + uint32_t touch_pad_debounce: 3; + }; + uint32_t val; + } sar_touch_status[14]; + union { + struct { + uint32_t touch_slp_data: 22; + uint32_t reserved22: 7; + uint32_t touch_slp_debounce: 3; + }; + uint32_t val; + } sar_touch_status15; + union { + struct { + uint32_t touch_approach_pad2_cnt: 8; + uint32_t touch_approach_pad1_cnt: 8; + uint32_t touch_approach_pad0_cnt: 8; + uint32_t touch_slp_approach_cnt: 8; + }; + uint32_t val; + } sar_touch_status16; + union { + struct { + uint32_t sw_fstep: 16; /*frequency step for CW generator*/ + uint32_t sw_tone_en: 1; /*1: enable CW generator*/ + uint32_t debug_bit_sel: 5; + uint32_t dac_dig_force: 1; /*1: DAC1 & DAC2 use DMA*/ + uint32_t dac_clk_force_low: 1; /*1: force PDAC_CLK to low*/ + uint32_t dac_clk_force_high: 1; /*1: force PDAC_CLK to high*/ + uint32_t dac_clk_inv: 1; /*1: invert PDAC_CLK*/ + uint32_t reserved26: 6; + }; + uint32_t val; + } sar_dac_ctrl1; + union { + struct { + uint32_t dac_dc1: 8; /*DC offset for DAC1 CW generator*/ + uint32_t dac_dc2: 8; /*DC offset for DAC2 CW generator*/ + uint32_t dac_scale1: 2; /*00: no scale*/ + uint32_t dac_scale2: 2; /*00: no scale*/ + uint32_t dac_inv1: 2; /*00: do not invert any bits*/ + uint32_t dac_inv2: 2; /*00: do not invert any bits*/ + uint32_t dac_cw_en1: 1; /*1: to select CW generator as source to PDAC1_DAC[7:0]*/ + uint32_t dac_cw_en2: 1; /*1: to select CW generator as source to PDAC2_DAC[7:0]*/ + uint32_t reserved26: 6; + }; + uint32_t val; + } sar_dac_ctrl2; + union { + struct { + uint32_t reserved0: 25; + uint32_t dbg_trigger: 1; /*trigger cocpu debug registers*/ + uint32_t clk_en_st: 1; /*check cocpu whether clk on*/ + uint32_t reset_n: 1; /*check cocpu whether in reset state*/ + uint32_t eoi: 1; /*check cocpu whether in interrupt state*/ + uint32_t trap: 1; /*check cocpu whether in trap state*/ + uint32_t ebreak: 1; /*check cocpu whether in ebreak*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } sar_cocpu_state; + union { + struct { + uint32_t touch_done: 1; /*int from touch done*/ + uint32_t touch_inactive: 1; /*int from touch inactive*/ + uint32_t touch_active: 1; /*int from touch active*/ + uint32_t saradc1: 1; /*int from saradc1*/ + uint32_t saradc2: 1; /*int from saradc2*/ + uint32_t tsens: 1; /*int from tsens*/ + uint32_t start: 1; /*int from start*/ + uint32_t sw: 1; /*int from software*/ + uint32_t swd: 1; /*int from super watch dog*/ + uint32_t touch_timeout: 1; + uint32_t touch_approach_loop_done: 1; + uint32_t touch_scan_done: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } sar_cocpu_int_raw; + union { + struct { + uint32_t touch_done: 1; + uint32_t touch_inactive: 1; + uint32_t touch_active: 1; + uint32_t saradc1: 1; + uint32_t saradc2: 1; + uint32_t tsens: 1; + uint32_t start: 1; + uint32_t sw: 1; /*cocpu int enable*/ + uint32_t swd: 1; + uint32_t touch_timeout: 1; + uint32_t touch_approach_loop_done: 1; + uint32_t touch_scan_done: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } sar_cocpu_int_ena; + union { + struct { + uint32_t touch_done: 1; + uint32_t touch_inactive: 1; + uint32_t touch_active: 1; + uint32_t saradc1: 1; + uint32_t saradc2: 1; + uint32_t tsens: 1; + uint32_t start: 1; + uint32_t sw: 1; /*cocpu int status*/ + uint32_t swd: 1; + uint32_t touch_timeout: 1; + uint32_t touch_approach_loop_done: 1; + uint32_t touch_scan_done: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } sar_cocpu_int_st; + union { + struct { + uint32_t touch_done: 1; + uint32_t touch_inactive: 1; + uint32_t touch_active: 1; + uint32_t saradc1: 1; + uint32_t saradc2: 1; + uint32_t tsens: 1; + uint32_t start: 1; + uint32_t sw: 1; /*cocpu int clear*/ + uint32_t swd: 1; + uint32_t touch_timeout: 1; + uint32_t touch_approach_loop_done: 1; + uint32_t touch_scan_done: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } sar_cocpu_int_clr; + union { + struct { + uint32_t pc: 13; /*cocpu Program counter*/ + uint32_t mem_vld: 1; /*cocpu mem valid output*/ + uint32_t mem_rdy: 1; /*cocpu mem ready input*/ + uint32_t mem_wen: 4; /*cocpu mem write enable output*/ + uint32_t mem_addr: 13; /*cocpu mem address output*/ + }; + uint32_t val; + } sar_cocpu_debug; + union { + struct { + uint32_t reserved0: 28; + uint32_t xpd_hall: 1; /*Power on hall sensor and connect to VP and VN*/ + uint32_t xpd_hall_force: 1; /*1: XPD HALL is controlled by SW. 0: XPD HALL is controlled by FSM in ULP-coprocessor*/ + uint32_t hall_phase: 1; /*Reverse phase of hall sensor*/ + uint32_t hall_phase_force: 1; /*1: HALL PHASE is controlled by SW 0: HALL PHASE is controlled by FSM in ULP-coprocessor*/ + }; + uint32_t val; + } sar_hall_ctrl; + uint32_t sar_nouse; /**/ + union { + struct { + uint32_t reserved0: 26; + uint32_t dac_clk_en: 1; + uint32_t rtc_i2c_clk_en: 1; + uint32_t reserved28: 1; + uint32_t tsens_clk_en: 1; + uint32_t saradc_clk_en: 1; + uint32_t iomux_clk_en: 1; + }; + uint32_t val; + } sar_peri_clk_gate_conf; + union { + struct { + uint32_t reserved0: 25; + uint32_t reset: 1; + uint32_t dac_reset: 1; + uint32_t rtc_i2c_reset: 1; + uint32_t reserved28: 1; + uint32_t tsens_reset: 1; + uint32_t saradc_reset: 1; + uint32_t reserved31: 1; + }; + uint32_t val; + } sar_peri_reset_conf; + union { + struct { + uint32_t touch_done_w1ts: 1; + uint32_t touch_inactive_w1ts: 1; + uint32_t touch_active_w1ts: 1; + uint32_t saradc1_w1ts: 1; + uint32_t saradc2_w1ts: 1; + uint32_t tsens_w1ts: 1; + uint32_t start_w1ts: 1; + uint32_t sw_w1ts: 1; + uint32_t swd_w1ts: 1; + uint32_t touch_timeout_w1ts: 1; + uint32_t touch_approach_loop_done_w1ts: 1; + uint32_t touch_scan_done_w1ts: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } sar_cocpu_int_ena_w1ts; + union { + struct { + uint32_t touch_done_w1tc: 1; + uint32_t touch_inactive_w1tc: 1; + uint32_t touch_active_w1tc: 1; + uint32_t saradc1_w1tc: 1; + uint32_t saradc2_w1tc: 1; + uint32_t tsens_w1tc: 1; + uint32_t start_w1tc: 1; + uint32_t sw_w1tc: 1; + uint32_t swd_w1tc: 1; + uint32_t touch_timeout_w1tc: 1; + uint32_t touch_approach_loop_done_w1tc: 1; + uint32_t touch_scan_done_w1tc: 1; + uint32_t reserved12: 20; + }; + uint32_t val; + } sar_cocpu_int_ena_w1tc; + union { + struct { + uint32_t sar_date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } sardate; +} sens_dev_t; + +extern sens_dev_t SENS; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sensitive_reg.h b/components/soc/soc/esp32s3/include/soc/sensitive_reg.h new file mode 100644 index 000000000..0c3ed1496 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sensitive_reg.h @@ -0,0 +1,4136 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_0_REG (DR_REG_SENSITIVE_BASE + 0x000) +/* SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK (BIT(0)) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_V 0x1 +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_LOCK_S 0 + +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_1_REG (DR_REG_SENSITIVE_BASE + 0x004) +/* SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN : R/W ;bitpos:[7:0] ;default: ~8'b0 ; */ +/*description: */ +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN 0x000000FF +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_M ((SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V) << (SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S)) +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_V 0xFF +#define SENSITIVE_CACHE_DATAARRAY_CONNECT_FLATTEN_S 0 + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x008) +/* SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_LOCK_S 0 + +#define SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x00C) +/* SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_M (BIT(0)) +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_V 0x1 +#define SENSITIVE_APB_PERIPHERAL_ACCESS_SPLIT_BURST_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_0_REG (DR_REG_SENSITIVE_BASE + 0x010) +/* SENSITIVE_INTERNAL_SRAM_USAGE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_M (BIT(0)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_V 0x1 +#define SENSITIVE_INTERNAL_SRAM_USAGE_LOCK_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_1_REG (DR_REG_SENSITIVE_BASE + 0x014) +/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0 : R/W ;bitpos:[10:0] ;default: ~11'h0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0 0x000007FF +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_V 0x7FF +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_0_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_2_REG (DR_REG_SENSITIVE_BASE + 0x018) +/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1 : R/W ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1 0x0003FFFF +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_V 0x3FFFF +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_1_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_3_REG (DR_REG_SENSITIVE_BASE + 0x01C) +/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2 : R/W ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2 0x0000000F +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_V 0xF +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_2_S 0 + +#define SENSITIVE_INTERNAL_SRAM_USAGE_4_REG (DR_REG_SENSITIVE_BASE + 0x020) +/* SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3 : R/W ;bitpos:[6:0] ;default: 7'b0 ; */ +/*description: */ +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3 0x0000007F +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_M ((SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_V) << (SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_S)) +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_V 0x7F +#define SENSITIVE_INTERNAL_SRAM_USAGE_FLATTEN_3_S 0 + +#define SENSITIVE_CACHE_TAG_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x024) +/* SENSITIVE_CACHE_TAG_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_TAG_ACCESS_LOCK_S 0 + +#define SENSITIVE_CACHE_TAG_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x028) +/* SENSITIVE_PRO_D_TAG_WR_ACS : R/W ;bitpos:[3] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_D_TAG_WR_ACS (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_M (BIT(3)) +#define SENSITIVE_PRO_D_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_WR_ACS_S 3 +/* SENSITIVE_PRO_D_TAG_RD_ACS : R/W ;bitpos:[2] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_D_TAG_RD_ACS (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_M (BIT(2)) +#define SENSITIVE_PRO_D_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_D_TAG_RD_ACS_S 2 +/* SENSITIVE_PRO_I_TAG_WR_ACS : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_I_TAG_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_I_TAG_WR_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_WR_ACS_S 1 +/* SENSITIVE_PRO_I_TAG_RD_ACS : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_PRO_I_TAG_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_I_TAG_RD_ACS_V 0x1 +#define SENSITIVE_PRO_I_TAG_RD_ACS_S 0 + +#define SENSITIVE_CACHE_MMU_ACCESS_0_REG (DR_REG_SENSITIVE_BASE + 0x02C) +/* SENSITIVE_CACHE_MMU_ACCESS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_M (BIT(0)) +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_V 0x1 +#define SENSITIVE_CACHE_MMU_ACCESS_LOCK_S 0 + +#define SENSITIVE_CACHE_MMU_ACCESS_1_REG (DR_REG_SENSITIVE_BASE + 0x030) +/* SENSITIVE_PRO_MMU_WR_ACS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_PRO_MMU_WR_ACS (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_M (BIT(1)) +#define SENSITIVE_PRO_MMU_WR_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_WR_ACS_S 1 +/* SENSITIVE_PRO_MMU_RD_ACS : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_PRO_MMU_RD_ACS (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_M (BIT(0)) +#define SENSITIVE_PRO_MMU_RD_ACS_V 0x1 +#define SENSITIVE_PRO_MMU_RD_ACS_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x034) +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x038) +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x03C) +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x040) +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SPI3_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x044) +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x048) +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x04C) +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x050) +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x054) +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x058) +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_I2S1_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x05C) +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x060) +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x064) +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x068) +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SLC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x06C) +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x070) +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x074) +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x078) +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x07C) +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x080) +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x084) +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x088) +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LCD_CAM_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x08C) +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x090) +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_USB_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x094) +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x098) +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x09C) +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0A0) +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_DMA_APBPERI_SDIO_HOST_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0A4) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0A8) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0AC) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[24:3] ;default: 22'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 3 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x0B0) +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V) << (SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/* SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0B4) +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0B8) +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR 0x0000007F +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_V 0x7F +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_6_S 12 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_5_S 10 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_4_S 8 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_3_S 6 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V) << (SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0BC) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR 0x0000007F +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_V 0x7F +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_6_S 12 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_5_S 10 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_4_S 8 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_3_S 6 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x0C0) +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR 0x0000007F +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_V 0x7F +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_6_S 12 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_5_S 10 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_4_S 8 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_3_S 6 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V) << (SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x0C4) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR 0x0000007F +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_V 0x7F +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_6_S 12 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_5_S 10 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_4_S 8 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_3_S 6 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x0C8) +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR 0x0000007F +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_V 0x7F +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR_S 14 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_6_S 12 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_5_S 10 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_4_S 8 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_3_S 6 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_M ((SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V) << (SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S)) +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0CC) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0D0) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 18 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 15 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 12 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 9 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 6 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 3 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 0 + +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x0D4) +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[20:18] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 18 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[17:15] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 15 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[14:12] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 12 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 9 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 6 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 3 +/* SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000007 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x7 +#define SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0D8) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0DC) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0E0) +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 +/* SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0E4) +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0E8) +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x0EC) +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[28:5] ;default: 24'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x00FFFFFF +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0xFFFFFF +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 5 +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 3 +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE (BIT(2)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_M (BIT(2)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE_S 2 +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(1)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 1 +/* SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_IRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x0F0) +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x0F4) +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS_S 26 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS_S 24 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_1_S 22 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0_S 20 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3_S 18 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2_S 16 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1_S 14 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0_S 12 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_1_S 10 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0_S 8 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3_S 6 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2_S 4 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1_S 2 +/* SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0 0x00000003 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_M ((SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V) << (SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S)) +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_V 0x3 +#define SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x0F8) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x0FC) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x100) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x104) +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V) << (SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/* SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x108) +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x10C) +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x110) +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR : RO ;bitpos:[25:4] ;default: 22'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR 0x003FFFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V) << (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_V 0x3FFFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR_S 4 +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD : RO ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD 0x00000003 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V) << (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_V 0x3 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD_S 2 +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_M (BIT(1)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK_S 1 +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x114) +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN : RO ;bitpos:[16:1] ;default: 16'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN 0x0000FFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_M ((SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V) << (SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_V 0xFFFF +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN_S 1 +/* SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_M (BIT(0)) +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_V 0x1 +#define SENSITIVE_CORE_1_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x118) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x11C) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x120) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x124) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x128) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x12C) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x130) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x134) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S 30 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x138) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 28 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 26 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 24 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 22 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 20 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 18 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 16 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 14 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 12 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x13C) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x140) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x144) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x148) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x14C) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x150) +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M ((SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V) << (SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S)) +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x154) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x158) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x15C) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x160) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x164) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x168) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x16C) +/* SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x170) +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_LOCK_S 0 + +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x174) +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL 0x00000003 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_M ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V) << (SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_V 0x3 +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_SEL_S 22 +/* SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE 0x003FFFFF +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_M ((SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_V) << (SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_S)) +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_V 0x3FFFFF +#define SENSITIVE_CORE_0_VECBASE_OVERRIDE_VALUE_S 0 + +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x178) +/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 + +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x17C) +/* SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_M (BIT(0)) +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x1 +#define SENSITIVE_CORE_0_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_0_REG (DR_REG_SENSITIVE_BASE + 0x180) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_LOCK_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_1_REG (DR_REG_SENSITIVE_BASE + 0x184) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART1_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S0_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_MISC_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI1_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_HINF_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WDG_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RTC_CONFIG_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMER_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_FE2_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_GPIO_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_2_REG (DR_REG_SENSITIVE_BASE + 0x188) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM0_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BB_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_ENCRYPT_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_EFUSE_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LEDC_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLC_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PCNT_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RMT_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SLCHOST_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_BUFFER_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BT_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_3_REG (DR_REG_SENSITIVE_BASE + 0x18C) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_0_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWR_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_BTMAC_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_RWBT_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM3_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM2_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_UART2_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2S1_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_PWM1_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_TWAI_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SDIO_HOST_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT1_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_3_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_4_REG (DR_REG_SENSITIVE_BASE + 0x190) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DIO_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_AD_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_LCD_CAM_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_0_G1SPI_ENCRYPT_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_5_REG (DR_REG_SENSITIVE_BASE + 0x194) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART1_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S0_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_MISC_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI1_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_HINF_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WDG_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RTC_CONFIG_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMER_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_FE2_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_GPIO_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_6_REG (DR_REG_SENSITIVE_BASE + 0x198) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM0_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BB_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_ENCRYPT_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_EFUSE_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LEDC_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLC_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PCNT_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RMT_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SLCHOST_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_BUFFER_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BT_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_7_REG (DR_REG_SENSITIVE_BASE + 0x19C) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 : R/W ;bitpos:[31:30] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_0_S 30 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWR_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_BTMAC_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_RWBT_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM3_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM2_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_UART2_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2S1_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_PWM1_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_TWAI_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SDIO_HOST_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT1_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_3_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_8_REG (DR_REG_SENSITIVE_BASE + 0x1A0) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER : R/W ;bitpos:[29:28] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER_S 28 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO : R/W ;bitpos:[27:26] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DIO_S 26 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD : R/W ;bitpos:[25:24] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_AD_S 24 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG : R/W ;bitpos:[23:22] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG_S 22 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY : R/W ;bitpos:[21:20] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY_S 20 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT : R/W ;bitpos:[19:18] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT_S 18 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE : R/W ;bitpos:[17:16] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE_S 16 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM : R/W ;bitpos:[15:14] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM_S 14 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB : R/W ;bitpos:[13:12] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_S 12 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM : R/W ;bitpos:[11:10] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_LCD_CAM_S 10 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC : R/W ;bitpos:[9:8] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC_S 8 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA : R/W ;bitpos:[7:6] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI : R/W ;bitpos:[5:4] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI_S 4 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP : R/W ;bitpos:[3:2] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_WORLD_1_G1SPI_ENCRYPT_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_9_REG (DR_REG_SENSITIVE_BASE + 0x1A4) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_10_REG (DR_REG_SENSITIVE_BASE + 0x1A8) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H_S 9 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H_S 3 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_11_REG (DR_REG_SENSITIVE_BASE + 0x1AC) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_12_REG (DR_REG_SENSITIVE_BASE + 0x1B0) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_H_S 9 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_1_L_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_H_S 3 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_0_WORLD_0_L_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_13_REG (DR_REG_SENSITIVE_BASE + 0x1B4) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 : R/W ;bitpos:[21:11] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_1_S 11 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0 0x000007FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_V 0x7FF +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_SPLTADDR_WORLD_0_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_14_REG (DR_REG_SENSITIVE_BASE + 0x1B8) +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H : R/W ;bitpos:[11:9] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_H_S 9 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L : R/W ;bitpos:[8:6] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_1_L_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H : R/W ;bitpos:[5:3] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_H_S 3 +/* SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L : R/W ;bitpos:[2:0] ;default: ~3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_M ((SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V) << (SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S)) +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_CONSTRAIN_RTCSLOW_1_WORLD_0_L_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_0_REG (DR_REG_SENSITIVE_BASE + 0x1BC) +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_LOCK_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_1_REG (DR_REG_SENSITIVE_BASE + 0x1C0) +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_2_REG (DR_REG_SENSITIVE_BASE + 0x1C4) +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD : RO ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD_S 6 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE (BIT(5)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_M (BIT(5)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE_S 5 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE : RO ;bitpos:[4:2] ;default: 3'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE 0x00000007 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_V 0x7 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE_S 2 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0 (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_M (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0_S 1 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_3_REG (DR_REG_SENSITIVE_BASE + 0x1C8) +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_4_REG (DR_REG_SENSITIVE_BASE + 0x1CC) +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN : R/W ;bitpos:[1] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_M (BIT(1)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN_S 1 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR : R/W ;bitpos:[0] ;default: ~1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_5_REG (DR_REG_SENSITIVE_BASE + 0x1D0) +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD : RO ;bitpos:[4:3] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD_S 3 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE : RO ;bitpos:[2:1] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE 0x00000003 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_V 0x3 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE_S 1 +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_M (BIT(0)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_V 0x1 +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR_S 0 + +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_6_REG (DR_REG_SENSITIVE_BASE + 0x1D4) +/* SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_M ((SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V) << (SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S)) +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_V 0xFFFFFFFF +#define SENSITIVE_CORE_1_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR_S 0 + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1D8) +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_LOCK_S 0 + +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1DC) +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL 0x00000003 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V) << (SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_V 0x3 +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_SEL_S 22 +/* SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE : R/W ;bitpos:[21:0] ;default: 22'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE 0x003FFFFF +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_M ((SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_V) << (SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_S)) +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_V 0x3FFFFF +#define SENSITIVE_CORE_1_VECBASE_OVERRIDE_VALUE_S 0 + +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_0_REG (DR_REG_SENSITIVE_BASE + 0x1E0) +/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_M (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_V 0x1 +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_LOCK_S 0 + +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_1_REG (DR_REG_SENSITIVE_BASE + 0x1E4) +/* SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_M (BIT(0)) +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_V 0x1 +#define SENSITIVE_CORE_1_TOOMANYEXCEPTIONS_M_OVERRIDE_S 0 + +#define SENSITIVE_CLOCK_GATE_REG (DR_REG_SENSITIVE_BASE + 0x1E8) +/* SENSITIVE_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SENSITIVE_CLK_EN (BIT(0)) +#define SENSITIVE_CLK_EN_M (BIT(0)) +#define SENSITIVE_CLK_EN_V 0x1 +#define SENSITIVE_CLK_EN_S 0 + +#define SENSITIVE_DATE_REG (DR_REG_SENSITIVE_BASE + 0xFFC) +/* SENSITIVE_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003240 ; */ +/*description: */ +#define SENSITIVE_DATE 0x0FFFFFFF +#define SENSITIVE_DATE_M ((SENSITIVE_DATE_V) << (SENSITIVE_DATE_S)) +#define SENSITIVE_DATE_V 0xFFFFFFF +#define SENSITIVE_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sensitive_struct.h b/components/soc/soc/esp32s3/include/soc/sensitive_struct.h new file mode 100644 index 000000000..db2d3e1be --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sensitive_struct.h @@ -0,0 +1,2281 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t cache_dataarray_connect_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } cache_dataarray_connect_0; + union { + struct { + uint32_t cache_dataarray_connect_flatten: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } cache_dataarray_connect_1; + union { + struct { + uint32_t apb_peripheral_access_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } apb_peripheral_access_0; + union { + struct { + uint32_t apb_peripheral_access_split_burst: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } apb_peripheral_access_1; + union { + struct { + uint32_t internal_sram_usage_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } internal_sram_usage_0; + union { + struct { + uint32_t internal_sram_usage_flatten_0: 11; + uint32_t reserved11: 21; + }; + uint32_t val; + } internal_sram_usage_1; + union { + struct { + uint32_t internal_sram_usage_flatten_1: 18; + uint32_t reserved18: 14; + }; + uint32_t val; + } internal_sram_usage_2; + union { + struct { + uint32_t internal_sram_usage_flatten_2: 4; + uint32_t reserved4: 28; + }; + uint32_t val; + } internal_sram_usage_3; + union { + struct { + uint32_t internal_sram_usage_flatten_3: 7; + uint32_t reserved7: 25; + }; + uint32_t val; + } internal_sram_usage_4; + union { + struct { + uint32_t cache_tag_access_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } cache_tag_access_0; + union { + struct { + uint32_t pro_i_tag_rd_acs: 1; + uint32_t pro_i_tag_wr_acs: 1; + uint32_t pro_d_tag_rd_acs: 1; + uint32_t pro_d_tag_wr_acs: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } cache_tag_access_1; + union { + struct { + uint32_t cache_mmu_access_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } cache_mmu_access_0; + union { + struct { + uint32_t pro_mmu_rd_acs: 1; + uint32_t pro_mmu_wr_acs: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } cache_mmu_access_1; + union { + struct { + uint32_t dma_apbperi_spi2_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_spi2_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_spi2_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_spi2_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_spi3_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_spi3_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_spi3_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_spi3_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_uchi0_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_uchi0_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_uchi0_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_uchi0_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_i2s0_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_i2s0_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_i2s0_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_i2s0_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_i2s1_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_i2s1_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_i2s1_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_i2s1_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_mac_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_mac_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_mac_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_mac_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_slc_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_slc_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_slc_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_slc_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_aes_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_aes_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_aes_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_aes_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_sha_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_sha_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_sha_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_sha_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_adc_dac_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_adc_dac_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_adc_dac_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_adc_dac_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_lcd_cam_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_lcd_cam_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_lcd_cam_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_lcd_cam_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_usb_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_usb_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_usb_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_usb_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_lc_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_lc_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_lc_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_lc_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_sdio_host_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_sdio_host_pms_constrain_0; + union { + struct { + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_0: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_1: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_2: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_pms_3: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_0: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_1: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_2: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_pms_3: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t dma_apbperi_sdio_host_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } dma_apbperi_sdio_host_pms_constrain_1; + union { + struct { + uint32_t dma_apbperi_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } dma_apbperi_pms_monitor_0; + union { + struct { + uint32_t dma_apbperi_pms_monitor_violate_clr: 1; + uint32_t dma_apbperi_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } dma_apbperi_pms_monitor_1; + union { + struct { + uint32_t dma_apbperi_pms_monitor_violate_intr: 1; + uint32_t dma_apbperi_pms_monitor_violate_status_world: 2; + uint32_t dma_apbperi_pms_monitor_violate_status_addr: 22; + uint32_t reserved25: 7; + }; + uint32_t val; + } dma_apbperi_pms_monitor_2; + union { + struct { + uint32_t dma_apbperi_pms_monitor_violate_status_wr: 1; + uint32_t dma_apbperi_pms_monitor_violate_status_byteen: 16; + uint32_t reserved17: 15; + }; + uint32_t val; + } dma_apbperi_pms_monitor_3; + union { + struct { + uint32_t core_x_iram0_dram0_dma_split_line_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_0; + union { + struct { + uint32_t core_x_iram0_dram0_dma_sram_category_0: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_1: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_2: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_3: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_4: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_5: 2; + uint32_t core_x_iram0_dram0_dma_sram_category_6: 2; + uint32_t core_x_iram0_dram0_dma_sram_splitaddr: 7; + uint32_t reserved21: 11; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_1; + union { + struct { + uint32_t core_x_iram0_sram_line_0_category_0: 2; + uint32_t core_x_iram0_sram_line_0_category_1: 2; + uint32_t core_x_iram0_sram_line_0_category_2: 2; + uint32_t core_x_iram0_sram_line_0_category_3: 2; + uint32_t core_x_iram0_sram_line_0_category_4: 2; + uint32_t core_x_iram0_sram_line_0_category_5: 2; + uint32_t core_x_iram0_sram_line_0_category_6: 2; + uint32_t core_x_iram0_sram_line_0_splitaddr: 7; + uint32_t reserved21: 11; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_2; + union { + struct { + uint32_t core_x_iram0_sram_line_1_category_0: 2; + uint32_t core_x_iram0_sram_line_1_category_1: 2; + uint32_t core_x_iram0_sram_line_1_category_2: 2; + uint32_t core_x_iram0_sram_line_1_category_3: 2; + uint32_t core_x_iram0_sram_line_1_category_4: 2; + uint32_t core_x_iram0_sram_line_1_category_5: 2; + uint32_t core_x_iram0_sram_line_1_category_6: 2; + uint32_t core_x_iram0_sram_line_1_splitaddr: 7; + uint32_t reserved21: 11; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_3; + union { + struct { + uint32_t core_x_dram0_dma_sram_line_0_category_0: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_1: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_2: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_3: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_4: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_5: 2; + uint32_t core_x_dram0_dma_sram_line_0_category_6: 2; + uint32_t core_x_dram0_dma_sram_line_0_splitaddr: 7; + uint32_t reserved21: 11; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_4; + union { + struct { + uint32_t core_x_dram0_dma_sram_line_1_category_0: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_1: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_2: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_3: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_4: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_5: 2; + uint32_t core_x_dram0_dma_sram_line_1_category_6: 2; + uint32_t core_x_dram0_dma_sram_line_1_splitaddr: 7; + uint32_t reserved21: 11; + }; + uint32_t val; + } core_x_iram0_dram0_dma_split_line_constrain_5; + union { + struct { + uint32_t core_x_iram0_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_x_iram0_pms_constrain_0; + union { + struct { + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_2: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_pms_3: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_rom_world_1_pms: 3; + uint32_t reserved21: 11; + }; + uint32_t val; + } core_x_iram0_pms_constrain_1; + union { + struct { + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_2: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_pms_3: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 3; + uint32_t core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_1: 3; + uint32_t core_x_iram0_pms_constrain_rom_world_0_pms: 3; + uint32_t reserved21: 11; + }; + uint32_t val; + } core_x_iram0_pms_constrain_2; + union { + struct { + uint32_t core_0_iram0_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_iram0_pms_monitor_0; + union { + struct { + uint32_t core_0_iram0_pms_monitor_violate_clr: 1; + uint32_t core_0_iram0_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_0_iram0_pms_monitor_1; + union { + struct { + uint32_t core_0_iram0_pms_monitor_violate_intr: 1; + uint32_t core_0_iram0_pms_monitor_violate_status_wr: 1; + uint32_t core_0_iram0_pms_monitor_violate_status_loadstore: 1; + uint32_t core_0_iram0_pms_monitor_violate_status_world: 2; + uint32_t core_0_iram0_pms_monitor_violate_status_addr: 24; + uint32_t reserved29: 3; + }; + uint32_t val; + } core_0_iram0_pms_monitor_2; + union { + struct { + uint32_t core_1_iram0_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_iram0_pms_monitor_0; + union { + struct { + uint32_t core_1_iram0_pms_monitor_violate_clr: 1; + uint32_t core_1_iram0_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_1_iram0_pms_monitor_1; + union { + struct { + uint32_t core_1_iram0_pms_monitor_violate_intr: 1; + uint32_t core_1_iram0_pms_monitor_violate_status_wr: 1; + uint32_t core_1_iram0_pms_monitor_violate_status_loadstore: 1; + uint32_t core_1_iram0_pms_monitor_violate_status_world: 2; + uint32_t core_1_iram0_pms_monitor_violate_status_addr: 24; + uint32_t reserved29: 3; + }; + uint32_t val; + } core_1_iram0_pms_monitor_2; + union { + struct { + uint32_t core_x_dram0_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_x_dram0_pms_constrain_0; + union { + struct { + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_2: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_pms_3: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_0_cachedataarray_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_2: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_pms_3: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_0: 2; + uint32_t core_x_dram0_pms_constrain_sram_world_1_cachedataarray_pms_1: 2; + uint32_t core_x_dram0_pms_constrain_rom_world_0_pms: 2; + uint32_t core_x_dram0_pms_constrain_rom_world_1_pms: 2; + uint32_t reserved28: 4; + }; + uint32_t val; + } core_x_dram0_pms_constrain_1; + union { + struct { + uint32_t core_0_dram0_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_dram0_pms_monitor_0; + union { + struct { + uint32_t core_0_dram0_pms_monitor_violate_clr: 1; + uint32_t core_0_dram0_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_0_dram0_pms_monitor_1; + union { + struct { + uint32_t core_0_dram0_pms_monitor_violate_intr: 1; + uint32_t core_0_dram0_pms_monitor_violate_status_lock: 1; + uint32_t core_0_dram0_pms_monitor_violate_status_world: 2; + uint32_t core_0_dram0_pms_monitor_violate_status_addr: 22; + uint32_t reserved26: 6; + }; + uint32_t val; + } core_0_dram0_pms_monitor_2; + union { + struct { + uint32_t core_0_dram0_pms_monitor_violate_status_wr: 1; + uint32_t core_0_dram0_pms_monitor_violate_status_byteen: 16; + uint32_t reserved17: 15; + }; + uint32_t val; + } core_0_dram0_pms_monitor_3; + union { + struct { + uint32_t core_1_dram0_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_dram0_pms_monitor_0; + union { + struct { + uint32_t core_1_dram0_pms_monitor_violate_clr: 1; + uint32_t core_1_dram0_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_1_dram0_pms_monitor_1; + union { + struct { + uint32_t core_1_dram0_pms_monitor_violate_intr: 1; + uint32_t core_1_dram0_pms_monitor_violate_status_lock: 1; + uint32_t core_1_dram0_pms_monitor_violate_status_world: 2; + uint32_t core_1_dram0_pms_monitor_violate_status_addr: 22; + uint32_t reserved26: 6; + }; + uint32_t val; + } core_1_dram0_pms_monitor_2; + union { + struct { + uint32_t core_1_dram0_pms_monitor_violate_status_wr: 1; + uint32_t core_1_dram0_pms_monitor_violate_status_byteen: 16; + uint32_t reserved17: 15; + }; + uint32_t val; + } core_1_dram0_pms_monitor_3; + union { + struct { + uint32_t core_0_pif_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_pif_pms_constrain_0; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_0_uart: 2; + uint32_t core_0_pif_pms_constrain_world_0_g0spi_1: 2; + uint32_t core_0_pif_pms_constrain_world_0_g0spi_0: 2; + uint32_t core_0_pif_pms_constrain_world_0_gpio: 2; + uint32_t core_0_pif_pms_constrain_world_0_fe2: 2; + uint32_t core_0_pif_pms_constrain_world_0_fe: 2; + uint32_t core_0_pif_pms_constrain_world_0_timer: 2; + uint32_t core_0_pif_pms_constrain_world_0_rtc_config: 2; + uint32_t core_0_pif_pms_constrain_world_0_io_mux: 2; + uint32_t core_0_pif_pms_constrain_world_0_wdg: 2; + uint32_t core_0_pif_pms_constrain_world_0_hinf: 2; + uint32_t core_0_pif_pms_constrain_world_0_uhci1: 2; + uint32_t core_0_pif_pms_constrain_world_0_misc: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2c: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2s0: 2; + uint32_t core_0_pif_pms_constrain_world_0_uart1: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_1; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_0_bt: 2; + uint32_t core_0_pif_pms_constrain_world_0_bt_buffer: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2c_ext0: 2; + uint32_t core_0_pif_pms_constrain_world_0_uhci0: 2; + uint32_t core_0_pif_pms_constrain_world_0_slchost: 2; + uint32_t core_0_pif_pms_constrain_world_0_rmt: 2; + uint32_t core_0_pif_pms_constrain_world_0_pcnt: 2; + uint32_t core_0_pif_pms_constrain_world_0_slc: 2; + uint32_t core_0_pif_pms_constrain_world_0_ledc: 2; + uint32_t core_0_pif_pms_constrain_world_0_efuse: 2; + uint32_t core_0_pif_pms_constrain_world_0_g0spi_encrypt: 2; + uint32_t core_0_pif_pms_constrain_world_0_bb: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwm0: 2; + uint32_t core_0_pif_pms_constrain_world_0_timergroup: 2; + uint32_t core_0_pif_pms_constrain_world_0_timergroup1: 2; + uint32_t core_0_pif_pms_constrain_world_0_systimer: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_2; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_0_spi_2: 2; + uint32_t core_0_pif_pms_constrain_world_0_spi_3: 2; + uint32_t core_0_pif_pms_constrain_world_0_apb_ctrl: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2c_ext1: 2; + uint32_t core_0_pif_pms_constrain_world_0_sdio_host: 2; + uint32_t core_0_pif_pms_constrain_world_0_can: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwm1: 2; + uint32_t core_0_pif_pms_constrain_world_0_i2s1: 2; + uint32_t core_0_pif_pms_constrain_world_0_uart2: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwm2: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwm3: 2; + uint32_t core_0_pif_pms_constrain_world_0_rwbt: 2; + uint32_t core_0_pif_pms_constrain_world_0_btmac: 2; + uint32_t core_0_pif_pms_constrain_world_0_wifimac: 2; + uint32_t core_0_pif_pms_constrain_world_0_pwr: 2; + uint32_t core_0_pif_pms_constrain_world_0_g1spi_0: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_3; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_0_g1spi_encrypt: 2; + uint32_t core_0_pif_pms_constrain_world_0_usb_wrap: 2; + uint32_t core_0_pif_pms_constrain_world_0_crypto_peri: 2; + uint32_t core_0_pif_pms_constrain_world_0_crypto_dma: 2; + uint32_t core_0_pif_pms_constrain_world_0_apb_adc: 2; + uint32_t core_0_pif_pms_constrain_world_0_lcd_cam: 2; + uint32_t core_0_pif_pms_constrain_world_0_usb: 2; + uint32_t core_0_pif_pms_constrain_world_0_system: 2; + uint32_t core_0_pif_pms_constrain_world_0_sensitive: 2; + uint32_t core_0_pif_pms_constrain_world_0_interrupt: 2; + uint32_t core_0_pif_pms_constrain_world_0_dma_copy: 2; + uint32_t core_0_pif_pms_constrain_world_0_cache_config: 2; + uint32_t core_0_pif_pms_constrain_world_0_ad: 2; + uint32_t core_0_pif_pms_constrain_world_0_dio: 2; + uint32_t core_0_pif_pms_constrain_world_0_world_controller: 2; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_4; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_1_uart: 2; + uint32_t core_0_pif_pms_constrain_world_1_g0spi_1: 2; + uint32_t core_0_pif_pms_constrain_world_1_g0spi_0: 2; + uint32_t core_0_pif_pms_constrain_world_1_gpio: 2; + uint32_t core_0_pif_pms_constrain_world_1_fe2: 2; + uint32_t core_0_pif_pms_constrain_world_1_fe: 2; + uint32_t core_0_pif_pms_constrain_world_1_timer: 2; + uint32_t core_0_pif_pms_constrain_world_1_rtc_config: 2; + uint32_t core_0_pif_pms_constrain_world_1_io_mux: 2; + uint32_t core_0_pif_pms_constrain_world_1_wdg: 2; + uint32_t core_0_pif_pms_constrain_world_1_hinf: 2; + uint32_t core_0_pif_pms_constrain_world_1_uhci1: 2; + uint32_t core_0_pif_pms_constrain_world_1_misc: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2c: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2s0: 2; + uint32_t core_0_pif_pms_constrain_world_1_uart1: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_5; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_1_bt: 2; + uint32_t core_0_pif_pms_constrain_world_1_bt_buffer: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2c_ext0: 2; + uint32_t core_0_pif_pms_constrain_world_1_uhci0: 2; + uint32_t core_0_pif_pms_constrain_world_1_slchost: 2; + uint32_t core_0_pif_pms_constrain_world_1_rmt: 2; + uint32_t core_0_pif_pms_constrain_world_1_pcnt: 2; + uint32_t core_0_pif_pms_constrain_world_1_slc: 2; + uint32_t core_0_pif_pms_constrain_world_1_ledc: 2; + uint32_t core_0_pif_pms_constrain_world_1_efuse: 2; + uint32_t core_0_pif_pms_constrain_world_1_g0spi_encrypt: 2; + uint32_t core_0_pif_pms_constrain_world_1_bb: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwm0: 2; + uint32_t core_0_pif_pms_constrain_world_1_timergroup: 2; + uint32_t core_0_pif_pms_constrain_world_1_timergroup1: 2; + uint32_t core_0_pif_pms_constrain_world_1_systimer: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_6; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_1_spi_2: 2; + uint32_t core_0_pif_pms_constrain_world_1_spi_3: 2; + uint32_t core_0_pif_pms_constrain_world_1_apb_ctrl: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2c_ext1: 2; + uint32_t core_0_pif_pms_constrain_world_1_sdio_host: 2; + uint32_t core_0_pif_pms_constrain_world_1_can: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwm1: 2; + uint32_t core_0_pif_pms_constrain_world_1_i2s1: 2; + uint32_t core_0_pif_pms_constrain_world_1_uart2: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwm2: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwm3: 2; + uint32_t core_0_pif_pms_constrain_world_1_rwbt: 2; + uint32_t core_0_pif_pms_constrain_world_1_btmac: 2; + uint32_t core_0_pif_pms_constrain_world_1_wifimac: 2; + uint32_t core_0_pif_pms_constrain_world_1_pwr: 2; + uint32_t core_0_pif_pms_constrain_world_1_g1spi_0: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_7; + union { + struct { + uint32_t core_0_pif_pms_constrain_world_1_g1spi_encrypt: 2; + uint32_t core_0_pif_pms_constrain_world_1_usb_wrap: 2; + uint32_t core_0_pif_pms_constrain_world_1_crypto_peri: 2; + uint32_t core_0_pif_pms_constrain_world_1_crypto_dma: 2; + uint32_t core_0_pif_pms_constrain_world_1_apb_adc: 2; + uint32_t core_0_pif_pms_constrain_world_1_lcd_cam: 2; + uint32_t core_0_pif_pms_constrain_world_1_usb: 2; + uint32_t core_0_pif_pms_constrain_world_1_system: 2; + uint32_t core_0_pif_pms_constrain_world_1_sensitive: 2; + uint32_t core_0_pif_pms_constrain_world_1_interrupt: 2; + uint32_t core_0_pif_pms_constrain_world_1_dma_copy: 2; + uint32_t core_0_pif_pms_constrain_world_1_cache_config: 2; + uint32_t core_0_pif_pms_constrain_world_1_ad: 2; + uint32_t core_0_pif_pms_constrain_world_1_dio: 2; + uint32_t core_0_pif_pms_constrain_world_1_world_controller: 2; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_0_pif_pms_constrain_8; + union { + struct { + uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; + uint32_t core_0_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_0_pif_pms_constrain_9; + union { + struct { + uint32_t core_0_pif_pms_constrain_rtcfast_world_0_l: 3; + uint32_t core_0_pif_pms_constrain_rtcfast_world_0_h: 3; + uint32_t core_0_pif_pms_constrain_rtcfast_world_1_l: 3; + uint32_t core_0_pif_pms_constrain_rtcfast_world_1_h: 3; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_pif_pms_constrain_10; + union { + struct { + uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_0: 11; + uint32_t core_0_pif_pms_constrain_rtcslow_0_spltaddr_world_1: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_0_pif_pms_constrain_11; + union { + struct { + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_0_h: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_0_world_1_h: 3; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_pif_pms_constrain_12; + union { + struct { + uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_0: 11; + uint32_t core_0_pif_pms_constrain_rtcslow_1_spltaddr_world_1: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_0_pif_pms_constrain_13; + union { + struct { + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_0_h: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_l: 3; + uint32_t core_0_pif_pms_constrain_rtcslow_1_world_1_h: 3; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_0_pif_pms_constrain_14; + union { + struct { + uint32_t core_0_pif_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_pif_pms_monitor_0; + union { + struct { + uint32_t core_0_pif_pms_monitor_violate_clr: 1; + uint32_t core_0_pif_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_0_pif_pms_monitor_1; + union { + struct { + uint32_t core_0_pif_pms_monitor_violate_intr: 1; + uint32_t core_0_pif_pms_monitor_violate_status_hport_0: 1; + uint32_t core_0_pif_pms_monitor_violate_status_hsize: 3; + uint32_t core_0_pif_pms_monitor_violate_status_hwrite: 1; + uint32_t core_0_pif_pms_monitor_violate_status_hworld: 2; + uint32_t reserved8: 24; + }; + uint32_t val; + } core_0_pif_pms_monitor_2; + uint32_t core_0_pif_pms_monitor_3; /**/ + union { + struct { + uint32_t core_0_pif_pms_monitor_nonword_violate_clr: 1; + uint32_t core_0_pif_pms_monitor_nonword_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_0_pif_pms_monitor_4; + union { + struct { + uint32_t core_0_pif_pms_monitor_nonword_violate_intr: 1; + uint32_t core_0_pif_pms_monitor_nonword_violate_status_hsize: 2; + uint32_t core_0_pif_pms_monitor_nonword_violate_status_hworld: 2; + uint32_t reserved5: 27; + }; + uint32_t val; + } core_0_pif_pms_monitor_5; + uint32_t core_0_pif_pms_monitor_6; /**/ + union { + struct { + uint32_t core_0_vecbase_override_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_vecbase_override_0; + union { + struct { + uint32_t core_0_vecbase_override_value: 22; + uint32_t core_0_vecbase_override_sel: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } core_0_vecbase_override_1; + union { + struct { + uint32_t core_0_toomanyexceptions_m_override_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_toomanyexceptions_m_override_0; + union { + struct { + uint32_t core_0_toomanyexceptions_m_override: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_0_toomanyexceptions_m_override_1; + union { + struct { + uint32_t core_1_pif_pms_constrain_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_pif_pms_constrain_0; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_0_uart: 2; + uint32_t core_1_pif_pms_constrain_world_0_g0spi_1: 2; + uint32_t core_1_pif_pms_constrain_world_0_g0spi_0: 2; + uint32_t core_1_pif_pms_constrain_world_0_gpio: 2; + uint32_t core_1_pif_pms_constrain_world_0_fe2: 2; + uint32_t core_1_pif_pms_constrain_world_0_fe: 2; + uint32_t core_1_pif_pms_constrain_world_0_timer: 2; + uint32_t core_1_pif_pms_constrain_world_0_rtc_config: 2; + uint32_t core_1_pif_pms_constrain_world_0_io_mux: 2; + uint32_t core_1_pif_pms_constrain_world_0_wdg: 2; + uint32_t core_1_pif_pms_constrain_world_0_hinf: 2; + uint32_t core_1_pif_pms_constrain_world_0_uhci1: 2; + uint32_t core_1_pif_pms_constrain_world_0_misc: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2c: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2s0: 2; + uint32_t core_1_pif_pms_constrain_world_0_uart1: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_1; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_0_bt: 2; + uint32_t core_1_pif_pms_constrain_world_0_bt_buffer: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2c_ext0: 2; + uint32_t core_1_pif_pms_constrain_world_0_uhci0: 2; + uint32_t core_1_pif_pms_constrain_world_0_slchost: 2; + uint32_t core_1_pif_pms_constrain_world_0_rmt: 2; + uint32_t core_1_pif_pms_constrain_world_0_pcnt: 2; + uint32_t core_1_pif_pms_constrain_world_0_slc: 2; + uint32_t core_1_pif_pms_constrain_world_0_ledc: 2; + uint32_t core_1_pif_pms_constrain_world_0_efuse: 2; + uint32_t core_1_pif_pms_constrain_world_0_g0spi_encrypt: 2; + uint32_t core_1_pif_pms_constrain_world_0_bb: 2; + uint32_t core_1_pif_pms_constrain_world_0_pwm0: 2; + uint32_t core_1_pif_pms_constrain_world_0_timergroup: 2; + uint32_t core_1_pif_pms_constrain_world_0_timergroup1: 2; + uint32_t core_1_pif_pms_constrain_world_0_systimer: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_2; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_0_spi_2: 2; + uint32_t core_1_pif_pms_constrain_world_0_spi_3: 2; + uint32_t core_1_pif_pms_constrain_world_0_apb_ctrl: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2c_ext1: 2; + uint32_t core_1_pif_pms_constrain_world_0_sdio_host: 2; + uint32_t core_1_pif_pms_constrain_world_0_can: 2; + uint32_t core_1_pif_pms_constrain_world_0_pwm1: 2; + uint32_t core_1_pif_pms_constrain_world_0_i2s1: 2; + uint32_t core_1_pif_pms_constrain_world_0_uart2: 2; + uint32_t core_1_pif_pms_constrain_world_0_pwm2: 2; + uint32_t core_1_pif_pms_constrain_world_0_pwm3: 2; + uint32_t core_1_pif_pms_constrain_world_0_rwbt: 2; + uint32_t core_1_pif_pms_constrain_world_0_btmac: 2; + uint32_t core_1_pif_pms_constrain_world_0_wifimac: 2; + uint32_t core_1_pif_pms_constrain_world_0_pwr: 2; + uint32_t core_1_pif_pms_constrain_world_0_g1spi_0: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_3; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_0_g1spi_encrypt: 2; + uint32_t core_1_pif_pms_constrain_world_0_usb_wrap: 2; + uint32_t core_1_pif_pms_constrain_world_0_crypto_peri: 2; + uint32_t core_1_pif_pms_constrain_world_0_crypto_dma: 2; + uint32_t core_1_pif_pms_constrain_world_0_apb_adc: 2; + uint32_t core_1_pif_pms_constrain_world_0_lcd_cam: 2; + uint32_t core_1_pif_pms_constrain_world_0_usb: 2; + uint32_t core_1_pif_pms_constrain_world_0_system: 2; + uint32_t core_1_pif_pms_constrain_world_0_sensitive: 2; + uint32_t core_1_pif_pms_constrain_world_0_interrupt: 2; + uint32_t core_1_pif_pms_constrain_world_0_dma_copy: 2; + uint32_t core_1_pif_pms_constrain_world_0_cache_config: 2; + uint32_t core_1_pif_pms_constrain_world_0_ad: 2; + uint32_t core_1_pif_pms_constrain_world_0_dio: 2; + uint32_t core_1_pif_pms_constrain_world_0_world_controller: 2; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_4; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_1_uart: 2; + uint32_t core_1_pif_pms_constrain_world_1_g0spi_1: 2; + uint32_t core_1_pif_pms_constrain_world_1_g0spi_0: 2; + uint32_t core_1_pif_pms_constrain_world_1_gpio: 2; + uint32_t core_1_pif_pms_constrain_world_1_fe2: 2; + uint32_t core_1_pif_pms_constrain_world_1_fe: 2; + uint32_t core_1_pif_pms_constrain_world_1_timer: 2; + uint32_t core_1_pif_pms_constrain_world_1_rtc_config: 2; + uint32_t core_1_pif_pms_constrain_world_1_io_mux: 2; + uint32_t core_1_pif_pms_constrain_world_1_wdg: 2; + uint32_t core_1_pif_pms_constrain_world_1_hinf: 2; + uint32_t core_1_pif_pms_constrain_world_1_uhci1: 2; + uint32_t core_1_pif_pms_constrain_world_1_misc: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2c: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2s0: 2; + uint32_t core_1_pif_pms_constrain_world_1_uart1: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_5; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_1_bt: 2; + uint32_t core_1_pif_pms_constrain_world_1_bt_buffer: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2c_ext0: 2; + uint32_t core_1_pif_pms_constrain_world_1_uhci0: 2; + uint32_t core_1_pif_pms_constrain_world_1_slchost: 2; + uint32_t core_1_pif_pms_constrain_world_1_rmt: 2; + uint32_t core_1_pif_pms_constrain_world_1_pcnt: 2; + uint32_t core_1_pif_pms_constrain_world_1_slc: 2; + uint32_t core_1_pif_pms_constrain_world_1_ledc: 2; + uint32_t core_1_pif_pms_constrain_world_1_efuse: 2; + uint32_t core_1_pif_pms_constrain_world_1_g0spi_encrypt: 2; + uint32_t core_1_pif_pms_constrain_world_1_bb: 2; + uint32_t core_1_pif_pms_constrain_world_1_pwm0: 2; + uint32_t core_1_pif_pms_constrain_world_1_timergroup: 2; + uint32_t core_1_pif_pms_constrain_world_1_timergroup1: 2; + uint32_t core_1_pif_pms_constrain_world_1_systimer: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_6; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_1_spi_2: 2; + uint32_t core_1_pif_pms_constrain_world_1_spi_3: 2; + uint32_t core_1_pif_pms_constrain_world_1_apb_ctrl: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2c_ext1: 2; + uint32_t core_1_pif_pms_constrain_world_1_sdio_host: 2; + uint32_t core_1_pif_pms_constrain_world_1_can: 2; + uint32_t core_1_pif_pms_constrain_world_1_pwm1: 2; + uint32_t core_1_pif_pms_constrain_world_1_i2s1: 2; + uint32_t core_1_pif_pms_constrain_world_1_uart2: 2; + uint32_t core_1_pif_pms_constrain_world_1_pwm2: 2; + uint32_t core_1_pif_pms_constrain_world_1_pwm3: 2; + uint32_t core_1_pif_pms_constrain_world_1_rwbt: 2; + uint32_t core_1_pif_pms_constrain_world_1_btmac: 2; + uint32_t core_1_pif_pms_constrain_world_1_wifimac: 2; + uint32_t core_1_pif_pms_constrain_world_1_pwr: 2; + uint32_t core_1_pif_pms_constrain_world_1_g1spi_0: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_7; + union { + struct { + uint32_t core_1_pif_pms_constrain_world_1_g1spi_encrypt: 2; + uint32_t core_1_pif_pms_constrain_world_1_usb_wrap: 2; + uint32_t core_1_pif_pms_constrain_world_1_crypto_peri: 2; + uint32_t core_1_pif_pms_constrain_world_1_crypto_dma: 2; + uint32_t core_1_pif_pms_constrain_world_1_apb_adc: 2; + uint32_t core_1_pif_pms_constrain_world_1_lcd_cam: 2; + uint32_t core_1_pif_pms_constrain_world_1_usb: 2; + uint32_t core_1_pif_pms_constrain_world_1_system: 2; + uint32_t core_1_pif_pms_constrain_world_1_sensitive: 2; + uint32_t core_1_pif_pms_constrain_world_1_interrupt: 2; + uint32_t core_1_pif_pms_constrain_world_1_dma_copy: 2; + uint32_t core_1_pif_pms_constrain_world_1_cache_config: 2; + uint32_t core_1_pif_pms_constrain_world_1_ad: 2; + uint32_t core_1_pif_pms_constrain_world_1_dio: 2; + uint32_t core_1_pif_pms_constrain_world_1_world_controller: 2; + uint32_t reserved30: 2; + }; + uint32_t val; + } core_1_pif_pms_constrain_8; + union { + struct { + uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_0: 11; + uint32_t core_1_pif_pms_constrain_rtcfast_spltaddr_world_1: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_1_pif_pms_constrain_9; + union { + struct { + uint32_t core_1_pif_pms_constrain_rtcfast_world_0_l: 3; + uint32_t core_1_pif_pms_constrain_rtcfast_world_0_h: 3; + uint32_t core_1_pif_pms_constrain_rtcfast_world_1_l: 3; + uint32_t core_1_pif_pms_constrain_rtcfast_world_1_h: 3; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_1_pif_pms_constrain_10; + union { + struct { + uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_0: 11; + uint32_t core_1_pif_pms_constrain_rtcslow_0_spltaddr_world_1: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_1_pif_pms_constrain_11; + union { + struct { + uint32_t core_1_pif_pms_constrain_rtcslow_0_world_0_l: 3; + uint32_t core_1_pif_pms_constrain_rtcslow_0_world_0_h: 3; + uint32_t core_1_pif_pms_constrain_rtcslow_0_world_1_l: 3; + uint32_t core_1_pif_pms_constrain_rtcslow_0_world_1_h: 3; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_1_pif_pms_constrain_12; + union { + struct { + uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_0: 11; + uint32_t core_1_pif_pms_constrain_rtcslow_1_spltaddr_world_1: 11; + uint32_t reserved22: 10; + }; + uint32_t val; + } core_1_pif_pms_constrain_13; + union { + struct { + uint32_t core_1_pif_pms_constrain_rtcslow_1_world_0_l: 3; + uint32_t core_1_pif_pms_constrain_rtcslow_1_world_0_h: 3; + uint32_t core_1_pif_pms_constrain_rtcslow_1_world_1_l: 3; + uint32_t core_1_pif_pms_constrain_rtcslow_1_world_1_h: 3; + uint32_t reserved12: 20; + }; + uint32_t val; + } core_1_pif_pms_constrain_14; + union { + struct { + uint32_t core_1_pif_pms_monitor_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_pif_pms_monitor_0; + union { + struct { + uint32_t core_1_pif_pms_monitor_violate_clr: 1; + uint32_t core_1_pif_pms_monitor_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_1_pif_pms_monitor_1; + union { + struct { + uint32_t core_1_pif_pms_monitor_violate_intr: 1; + uint32_t core_1_pif_pms_monitor_violate_status_hport_0: 1; + uint32_t core_1_pif_pms_monitor_violate_status_hsize: 3; + uint32_t core_1_pif_pms_monitor_violate_status_hwrite: 1; + uint32_t core_1_pif_pms_monitor_violate_status_hworld: 2; + uint32_t reserved8: 24; + }; + uint32_t val; + } core_1_pif_pms_monitor_2; + uint32_t core_1_pif_pms_monitor_3; /**/ + union { + struct { + uint32_t core_1_pif_pms_monitor_nonword_violate_clr: 1; + uint32_t core_1_pif_pms_monitor_nonword_violate_en: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } core_1_pif_pms_monitor_4; + union { + struct { + uint32_t core_1_pif_pms_monitor_nonword_violate_intr: 1; + uint32_t core_1_pif_pms_monitor_nonword_violate_status_hsize: 2; + uint32_t core_1_pif_pms_monitor_nonword_violate_status_hworld: 2; + uint32_t reserved5: 27; + }; + uint32_t val; + } core_1_pif_pms_monitor_5; + uint32_t core_1_pif_pms_monitor_6; /**/ + union { + struct { + uint32_t core_1_vecbase_override_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_vecbase_override_0; + union { + struct { + uint32_t core_1_vecbase_override_value: 22; + uint32_t core_1_vecbase_override_sel: 2; + uint32_t reserved24: 8; + }; + uint32_t val; + } core_1_vecbase_override_1; + union { + struct { + uint32_t core_1_toomanyexceptions_m_override_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_toomanyexceptions_m_override_0; + union { + struct { + uint32_t core_1_toomanyexceptions_m_override: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } core_1_toomanyexceptions_m_override_1; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } clock_gate; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t reserved_3fc; + uint32_t reserved_400; + uint32_t reserved_404; + uint32_t reserved_408; + uint32_t reserved_40c; + uint32_t reserved_410; + uint32_t reserved_414; + uint32_t reserved_418; + uint32_t reserved_41c; + uint32_t reserved_420; + uint32_t reserved_424; + uint32_t reserved_428; + uint32_t reserved_42c; + uint32_t reserved_430; + uint32_t reserved_434; + uint32_t reserved_438; + uint32_t reserved_43c; + uint32_t reserved_440; + uint32_t reserved_444; + uint32_t reserved_448; + uint32_t reserved_44c; + uint32_t reserved_450; + uint32_t reserved_454; + uint32_t reserved_458; + uint32_t reserved_45c; + uint32_t reserved_460; + uint32_t reserved_464; + uint32_t reserved_468; + uint32_t reserved_46c; + uint32_t reserved_470; + uint32_t reserved_474; + uint32_t reserved_478; + uint32_t reserved_47c; + uint32_t reserved_480; + uint32_t reserved_484; + uint32_t reserved_488; + uint32_t reserved_48c; + uint32_t reserved_490; + uint32_t reserved_494; + uint32_t reserved_498; + uint32_t reserved_49c; + uint32_t reserved_4a0; + uint32_t reserved_4a4; + uint32_t reserved_4a8; + uint32_t reserved_4ac; + uint32_t reserved_4b0; + uint32_t reserved_4b4; + uint32_t reserved_4b8; + uint32_t reserved_4bc; + uint32_t reserved_4c0; + uint32_t reserved_4c4; + uint32_t reserved_4c8; + uint32_t reserved_4cc; + uint32_t reserved_4d0; + uint32_t reserved_4d4; + uint32_t reserved_4d8; + uint32_t reserved_4dc; + uint32_t reserved_4e0; + uint32_t reserved_4e4; + uint32_t reserved_4e8; + uint32_t reserved_4ec; + uint32_t reserved_4f0; + uint32_t reserved_4f4; + uint32_t reserved_4f8; + uint32_t reserved_4fc; + uint32_t reserved_500; + uint32_t reserved_504; + uint32_t reserved_508; + uint32_t reserved_50c; + uint32_t reserved_510; + uint32_t reserved_514; + uint32_t reserved_518; + uint32_t reserved_51c; + uint32_t reserved_520; + uint32_t reserved_524; + uint32_t reserved_528; + uint32_t reserved_52c; + uint32_t reserved_530; + uint32_t reserved_534; + uint32_t reserved_538; + uint32_t reserved_53c; + uint32_t reserved_540; + uint32_t reserved_544; + uint32_t reserved_548; + uint32_t reserved_54c; + uint32_t reserved_550; + uint32_t reserved_554; + uint32_t reserved_558; + uint32_t reserved_55c; + uint32_t reserved_560; + uint32_t reserved_564; + uint32_t reserved_568; + uint32_t reserved_56c; + uint32_t reserved_570; + uint32_t reserved_574; + uint32_t reserved_578; + uint32_t reserved_57c; + uint32_t reserved_580; + uint32_t reserved_584; + uint32_t reserved_588; + uint32_t reserved_58c; + uint32_t reserved_590; + uint32_t reserved_594; + uint32_t reserved_598; + uint32_t reserved_59c; + uint32_t reserved_5a0; + uint32_t reserved_5a4; + uint32_t reserved_5a8; + uint32_t reserved_5ac; + uint32_t reserved_5b0; + uint32_t reserved_5b4; + uint32_t reserved_5b8; + uint32_t reserved_5bc; + uint32_t reserved_5c0; + uint32_t reserved_5c4; + uint32_t reserved_5c8; + uint32_t reserved_5cc; + uint32_t reserved_5d0; + uint32_t reserved_5d4; + uint32_t reserved_5d8; + uint32_t reserved_5dc; + uint32_t reserved_5e0; + uint32_t reserved_5e4; + uint32_t reserved_5e8; + uint32_t reserved_5ec; + uint32_t reserved_5f0; + uint32_t reserved_5f4; + uint32_t reserved_5f8; + uint32_t reserved_5fc; + uint32_t reserved_600; + uint32_t reserved_604; + uint32_t reserved_608; + uint32_t reserved_60c; + uint32_t reserved_610; + uint32_t reserved_614; + uint32_t reserved_618; + uint32_t reserved_61c; + uint32_t reserved_620; + uint32_t reserved_624; + uint32_t reserved_628; + uint32_t reserved_62c; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + uint32_t reserved_6fc; + uint32_t reserved_700; + uint32_t reserved_704; + uint32_t reserved_708; + uint32_t reserved_70c; + uint32_t reserved_710; + uint32_t reserved_714; + uint32_t reserved_718; + uint32_t reserved_71c; + uint32_t reserved_720; + uint32_t reserved_724; + uint32_t reserved_728; + uint32_t reserved_72c; + uint32_t reserved_730; + uint32_t reserved_734; + uint32_t reserved_738; + uint32_t reserved_73c; + uint32_t reserved_740; + uint32_t reserved_744; + uint32_t reserved_748; + uint32_t reserved_74c; + uint32_t reserved_750; + uint32_t reserved_754; + uint32_t reserved_758; + uint32_t reserved_75c; + uint32_t reserved_760; + uint32_t reserved_764; + uint32_t reserved_768; + uint32_t reserved_76c; + uint32_t reserved_770; + uint32_t reserved_774; + uint32_t reserved_778; + uint32_t reserved_77c; + uint32_t reserved_780; + uint32_t reserved_784; + uint32_t reserved_788; + uint32_t reserved_78c; + uint32_t reserved_790; + uint32_t reserved_794; + uint32_t reserved_798; + uint32_t reserved_79c; + uint32_t reserved_7a0; + uint32_t reserved_7a4; + uint32_t reserved_7a8; + uint32_t reserved_7ac; + uint32_t reserved_7b0; + uint32_t reserved_7b4; + uint32_t reserved_7b8; + uint32_t reserved_7bc; + uint32_t reserved_7c0; + uint32_t reserved_7c4; + uint32_t reserved_7c8; + uint32_t reserved_7cc; + uint32_t reserved_7d0; + uint32_t reserved_7d4; + uint32_t reserved_7d8; + uint32_t reserved_7dc; + uint32_t reserved_7e0; + uint32_t reserved_7e4; + uint32_t reserved_7e8; + uint32_t reserved_7ec; + uint32_t reserved_7f0; + uint32_t reserved_7f4; + uint32_t reserved_7f8; + uint32_t reserved_7fc; + uint32_t reserved_800; + uint32_t reserved_804; + uint32_t reserved_808; + uint32_t reserved_80c; + uint32_t reserved_810; + uint32_t reserved_814; + uint32_t reserved_818; + uint32_t reserved_81c; + uint32_t reserved_820; + uint32_t reserved_824; + uint32_t reserved_828; + uint32_t reserved_82c; + uint32_t reserved_830; + uint32_t reserved_834; + uint32_t reserved_838; + uint32_t reserved_83c; + uint32_t reserved_840; + uint32_t reserved_844; + uint32_t reserved_848; + uint32_t reserved_84c; + uint32_t reserved_850; + uint32_t reserved_854; + uint32_t reserved_858; + uint32_t reserved_85c; + uint32_t reserved_860; + uint32_t reserved_864; + uint32_t reserved_868; + uint32_t reserved_86c; + uint32_t reserved_870; + uint32_t reserved_874; + uint32_t reserved_878; + uint32_t reserved_87c; + uint32_t reserved_880; + uint32_t reserved_884; + uint32_t reserved_888; + uint32_t reserved_88c; + uint32_t reserved_890; + uint32_t reserved_894; + uint32_t reserved_898; + uint32_t reserved_89c; + uint32_t reserved_8a0; + uint32_t reserved_8a4; + uint32_t reserved_8a8; + uint32_t reserved_8ac; + uint32_t reserved_8b0; + uint32_t reserved_8b4; + uint32_t reserved_8b8; + uint32_t reserved_8bc; + uint32_t reserved_8c0; + uint32_t reserved_8c4; + uint32_t reserved_8c8; + uint32_t reserved_8cc; + uint32_t reserved_8d0; + uint32_t reserved_8d4; + uint32_t reserved_8d8; + uint32_t reserved_8dc; + uint32_t reserved_8e0; + uint32_t reserved_8e4; + uint32_t reserved_8e8; + uint32_t reserved_8ec; + uint32_t reserved_8f0; + uint32_t reserved_8f4; + uint32_t reserved_8f8; + uint32_t reserved_8fc; + uint32_t reserved_900; + uint32_t reserved_904; + uint32_t reserved_908; + uint32_t reserved_90c; + uint32_t reserved_910; + uint32_t reserved_914; + uint32_t reserved_918; + uint32_t reserved_91c; + uint32_t reserved_920; + uint32_t reserved_924; + uint32_t reserved_928; + uint32_t reserved_92c; + uint32_t reserved_930; + uint32_t reserved_934; + uint32_t reserved_938; + uint32_t reserved_93c; + uint32_t reserved_940; + uint32_t reserved_944; + uint32_t reserved_948; + uint32_t reserved_94c; + uint32_t reserved_950; + uint32_t reserved_954; + uint32_t reserved_958; + uint32_t reserved_95c; + uint32_t reserved_960; + uint32_t reserved_964; + uint32_t reserved_968; + uint32_t reserved_96c; + uint32_t reserved_970; + uint32_t reserved_974; + uint32_t reserved_978; + uint32_t reserved_97c; + uint32_t reserved_980; + uint32_t reserved_984; + uint32_t reserved_988; + uint32_t reserved_98c; + uint32_t reserved_990; + uint32_t reserved_994; + uint32_t reserved_998; + uint32_t reserved_99c; + uint32_t reserved_9a0; + uint32_t reserved_9a4; + uint32_t reserved_9a8; + uint32_t reserved_9ac; + uint32_t reserved_9b0; + uint32_t reserved_9b4; + uint32_t reserved_9b8; + uint32_t reserved_9bc; + uint32_t reserved_9c0; + uint32_t reserved_9c4; + uint32_t reserved_9c8; + uint32_t reserved_9cc; + uint32_t reserved_9d0; + uint32_t reserved_9d4; + uint32_t reserved_9d8; + uint32_t reserved_9dc; + uint32_t reserved_9e0; + uint32_t reserved_9e4; + uint32_t reserved_9e8; + uint32_t reserved_9ec; + uint32_t reserved_9f0; + uint32_t reserved_9f4; + uint32_t reserved_9f8; + uint32_t reserved_9fc; + uint32_t reserved_a00; + uint32_t reserved_a04; + uint32_t reserved_a08; + uint32_t reserved_a0c; + uint32_t reserved_a10; + uint32_t reserved_a14; + uint32_t reserved_a18; + uint32_t reserved_a1c; + uint32_t reserved_a20; + uint32_t reserved_a24; + uint32_t reserved_a28; + uint32_t reserved_a2c; + uint32_t reserved_a30; + uint32_t reserved_a34; + uint32_t reserved_a38; + uint32_t reserved_a3c; + uint32_t reserved_a40; + uint32_t reserved_a44; + uint32_t reserved_a48; + uint32_t reserved_a4c; + uint32_t reserved_a50; + uint32_t reserved_a54; + uint32_t reserved_a58; + uint32_t reserved_a5c; + uint32_t reserved_a60; + uint32_t reserved_a64; + uint32_t reserved_a68; + uint32_t reserved_a6c; + uint32_t reserved_a70; + uint32_t reserved_a74; + uint32_t reserved_a78; + uint32_t reserved_a7c; + uint32_t reserved_a80; + uint32_t reserved_a84; + uint32_t reserved_a88; + uint32_t reserved_a8c; + uint32_t reserved_a90; + uint32_t reserved_a94; + uint32_t reserved_a98; + uint32_t reserved_a9c; + uint32_t reserved_aa0; + uint32_t reserved_aa4; + uint32_t reserved_aa8; + uint32_t reserved_aac; + uint32_t reserved_ab0; + uint32_t reserved_ab4; + uint32_t reserved_ab8; + uint32_t reserved_abc; + uint32_t reserved_ac0; + uint32_t reserved_ac4; + uint32_t reserved_ac8; + uint32_t reserved_acc; + uint32_t reserved_ad0; + uint32_t reserved_ad4; + uint32_t reserved_ad8; + uint32_t reserved_adc; + uint32_t reserved_ae0; + uint32_t reserved_ae4; + uint32_t reserved_ae8; + uint32_t reserved_aec; + uint32_t reserved_af0; + uint32_t reserved_af4; + uint32_t reserved_af8; + uint32_t reserved_afc; + uint32_t reserved_b00; + uint32_t reserved_b04; + uint32_t reserved_b08; + uint32_t reserved_b0c; + uint32_t reserved_b10; + uint32_t reserved_b14; + uint32_t reserved_b18; + uint32_t reserved_b1c; + uint32_t reserved_b20; + uint32_t reserved_b24; + uint32_t reserved_b28; + uint32_t reserved_b2c; + uint32_t reserved_b30; + uint32_t reserved_b34; + uint32_t reserved_b38; + uint32_t reserved_b3c; + uint32_t reserved_b40; + uint32_t reserved_b44; + uint32_t reserved_b48; + uint32_t reserved_b4c; + uint32_t reserved_b50; + uint32_t reserved_b54; + uint32_t reserved_b58; + uint32_t reserved_b5c; + uint32_t reserved_b60; + uint32_t reserved_b64; + uint32_t reserved_b68; + uint32_t reserved_b6c; + uint32_t reserved_b70; + uint32_t reserved_b74; + uint32_t reserved_b78; + uint32_t reserved_b7c; + uint32_t reserved_b80; + uint32_t reserved_b84; + uint32_t reserved_b88; + uint32_t reserved_b8c; + uint32_t reserved_b90; + uint32_t reserved_b94; + uint32_t reserved_b98; + uint32_t reserved_b9c; + uint32_t reserved_ba0; + uint32_t reserved_ba4; + uint32_t reserved_ba8; + uint32_t reserved_bac; + uint32_t reserved_bb0; + uint32_t reserved_bb4; + uint32_t reserved_bb8; + uint32_t reserved_bbc; + uint32_t reserved_bc0; + uint32_t reserved_bc4; + uint32_t reserved_bc8; + uint32_t reserved_bcc; + uint32_t reserved_bd0; + uint32_t reserved_bd4; + uint32_t reserved_bd8; + uint32_t reserved_bdc; + uint32_t reserved_be0; + uint32_t reserved_be4; + uint32_t reserved_be8; + uint32_t reserved_bec; + uint32_t reserved_bf0; + uint32_t reserved_bf4; + uint32_t reserved_bf8; + uint32_t reserved_bfc; + uint32_t reserved_c00; + uint32_t reserved_c04; + uint32_t reserved_c08; + uint32_t reserved_c0c; + uint32_t reserved_c10; + uint32_t reserved_c14; + uint32_t reserved_c18; + uint32_t reserved_c1c; + uint32_t reserved_c20; + uint32_t reserved_c24; + uint32_t reserved_c28; + uint32_t reserved_c2c; + uint32_t reserved_c30; + uint32_t reserved_c34; + uint32_t reserved_c38; + uint32_t reserved_c3c; + uint32_t reserved_c40; + uint32_t reserved_c44; + uint32_t reserved_c48; + uint32_t reserved_c4c; + uint32_t reserved_c50; + uint32_t reserved_c54; + uint32_t reserved_c58; + uint32_t reserved_c5c; + uint32_t reserved_c60; + uint32_t reserved_c64; + uint32_t reserved_c68; + uint32_t reserved_c6c; + uint32_t reserved_c70; + uint32_t reserved_c74; + uint32_t reserved_c78; + uint32_t reserved_c7c; + uint32_t reserved_c80; + uint32_t reserved_c84; + uint32_t reserved_c88; + uint32_t reserved_c8c; + uint32_t reserved_c90; + uint32_t reserved_c94; + uint32_t reserved_c98; + uint32_t reserved_c9c; + uint32_t reserved_ca0; + uint32_t reserved_ca4; + uint32_t reserved_ca8; + uint32_t reserved_cac; + uint32_t reserved_cb0; + uint32_t reserved_cb4; + uint32_t reserved_cb8; + uint32_t reserved_cbc; + uint32_t reserved_cc0; + uint32_t reserved_cc4; + uint32_t reserved_cc8; + uint32_t reserved_ccc; + uint32_t reserved_cd0; + uint32_t reserved_cd4; + uint32_t reserved_cd8; + uint32_t reserved_cdc; + uint32_t reserved_ce0; + uint32_t reserved_ce4; + uint32_t reserved_ce8; + uint32_t reserved_cec; + uint32_t reserved_cf0; + uint32_t reserved_cf4; + uint32_t reserved_cf8; + uint32_t reserved_cfc; + uint32_t reserved_d00; + uint32_t reserved_d04; + uint32_t reserved_d08; + uint32_t reserved_d0c; + uint32_t reserved_d10; + uint32_t reserved_d14; + uint32_t reserved_d18; + uint32_t reserved_d1c; + uint32_t reserved_d20; + uint32_t reserved_d24; + uint32_t reserved_d28; + uint32_t reserved_d2c; + uint32_t reserved_d30; + uint32_t reserved_d34; + uint32_t reserved_d38; + uint32_t reserved_d3c; + uint32_t reserved_d40; + uint32_t reserved_d44; + uint32_t reserved_d48; + uint32_t reserved_d4c; + uint32_t reserved_d50; + uint32_t reserved_d54; + uint32_t reserved_d58; + uint32_t reserved_d5c; + uint32_t reserved_d60; + uint32_t reserved_d64; + uint32_t reserved_d68; + uint32_t reserved_d6c; + uint32_t reserved_d70; + uint32_t reserved_d74; + uint32_t reserved_d78; + uint32_t reserved_d7c; + uint32_t reserved_d80; + uint32_t reserved_d84; + uint32_t reserved_d88; + uint32_t reserved_d8c; + uint32_t reserved_d90; + uint32_t reserved_d94; + uint32_t reserved_d98; + uint32_t reserved_d9c; + uint32_t reserved_da0; + uint32_t reserved_da4; + uint32_t reserved_da8; + uint32_t reserved_dac; + uint32_t reserved_db0; + uint32_t reserved_db4; + uint32_t reserved_db8; + uint32_t reserved_dbc; + uint32_t reserved_dc0; + uint32_t reserved_dc4; + uint32_t reserved_dc8; + uint32_t reserved_dcc; + uint32_t reserved_dd0; + uint32_t reserved_dd4; + uint32_t reserved_dd8; + uint32_t reserved_ddc; + uint32_t reserved_de0; + uint32_t reserved_de4; + uint32_t reserved_de8; + uint32_t reserved_dec; + uint32_t reserved_df0; + uint32_t reserved_df4; + uint32_t reserved_df8; + uint32_t reserved_dfc; + uint32_t reserved_e00; + uint32_t reserved_e04; + uint32_t reserved_e08; + uint32_t reserved_e0c; + uint32_t reserved_e10; + uint32_t reserved_e14; + uint32_t reserved_e18; + uint32_t reserved_e1c; + uint32_t reserved_e20; + uint32_t reserved_e24; + uint32_t reserved_e28; + uint32_t reserved_e2c; + uint32_t reserved_e30; + uint32_t reserved_e34; + uint32_t reserved_e38; + uint32_t reserved_e3c; + uint32_t reserved_e40; + uint32_t reserved_e44; + uint32_t reserved_e48; + uint32_t reserved_e4c; + uint32_t reserved_e50; + uint32_t reserved_e54; + uint32_t reserved_e58; + uint32_t reserved_e5c; + uint32_t reserved_e60; + uint32_t reserved_e64; + uint32_t reserved_e68; + uint32_t reserved_e6c; + uint32_t reserved_e70; + uint32_t reserved_e74; + uint32_t reserved_e78; + uint32_t reserved_e7c; + uint32_t reserved_e80; + uint32_t reserved_e84; + uint32_t reserved_e88; + uint32_t reserved_e8c; + uint32_t reserved_e90; + uint32_t reserved_e94; + uint32_t reserved_e98; + uint32_t reserved_e9c; + uint32_t reserved_ea0; + uint32_t reserved_ea4; + uint32_t reserved_ea8; + uint32_t reserved_eac; + uint32_t reserved_eb0; + uint32_t reserved_eb4; + uint32_t reserved_eb8; + uint32_t reserved_ebc; + uint32_t reserved_ec0; + uint32_t reserved_ec4; + uint32_t reserved_ec8; + uint32_t reserved_ecc; + uint32_t reserved_ed0; + uint32_t reserved_ed4; + uint32_t reserved_ed8; + uint32_t reserved_edc; + uint32_t reserved_ee0; + uint32_t reserved_ee4; + uint32_t reserved_ee8; + uint32_t reserved_eec; + uint32_t reserved_ef0; + uint32_t reserved_ef4; + uint32_t reserved_ef8; + uint32_t reserved_efc; + uint32_t reserved_f00; + uint32_t reserved_f04; + uint32_t reserved_f08; + uint32_t reserved_f0c; + uint32_t reserved_f10; + uint32_t reserved_f14; + uint32_t reserved_f18; + uint32_t reserved_f1c; + uint32_t reserved_f20; + uint32_t reserved_f24; + uint32_t reserved_f28; + uint32_t reserved_f2c; + uint32_t reserved_f30; + uint32_t reserved_f34; + uint32_t reserved_f38; + uint32_t reserved_f3c; + uint32_t reserved_f40; + uint32_t reserved_f44; + uint32_t reserved_f48; + uint32_t reserved_f4c; + uint32_t reserved_f50; + uint32_t reserved_f54; + uint32_t reserved_f58; + uint32_t reserved_f5c; + uint32_t reserved_f60; + uint32_t reserved_f64; + uint32_t reserved_f68; + uint32_t reserved_f6c; + uint32_t reserved_f70; + uint32_t reserved_f74; + uint32_t reserved_f78; + uint32_t reserved_f7c; + uint32_t reserved_f80; + uint32_t reserved_f84; + uint32_t reserved_f88; + uint32_t reserved_f8c; + uint32_t reserved_f90; + uint32_t reserved_f94; + uint32_t reserved_f98; + uint32_t reserved_f9c; + uint32_t reserved_fa0; + uint32_t reserved_fa4; + uint32_t reserved_fa8; + uint32_t reserved_fac; + uint32_t reserved_fb0; + uint32_t reserved_fb4; + uint32_t reserved_fb8; + uint32_t reserved_fbc; + uint32_t reserved_fc0; + uint32_t reserved_fc4; + uint32_t reserved_fc8; + uint32_t reserved_fcc; + uint32_t reserved_fd0; + uint32_t reserved_fd4; + uint32_t reserved_fd8; + uint32_t reserved_fdc; + uint32_t reserved_fe0; + uint32_t reserved_fe4; + uint32_t reserved_fe8; + uint32_t reserved_fec; + uint32_t reserved_ff0; + uint32_t reserved_ff4; + uint32_t reserved_ff8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} sensitive_dev_t; + +extern sensitive_dev_t SENSITIVE; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h b/components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h new file mode 100644 index 000000000..0a3d99c2b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sigmadelta_caps.h @@ -0,0 +1,37 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +// ESP32-S3 have 1 SIGMADELTA peripheral. +#define SIGMADELTA_PORT_0 (0) /*!< SIGMADELTA port 0 */ +#define SIGMADELTA_PORT_MAX (1) /*!< SIGMADELTA port max */ +#define SOC_SIGMADELTA_NUM (SIGMADELTA_PORT_MAX) + +#define SIGMADELTA_CHANNEL_0 (0) /*!< Sigma-delta channel 0 */ +#define SIGMADELTA_CHANNEL_1 (1) /*!< Sigma-delta channel 1 */ +#define SIGMADELTA_CHANNEL_2 (2) /*!< Sigma-delta channel 2 */ +#define SIGMADELTA_CHANNEL_3 (3) /*!< Sigma-delta channel 3 */ +#define SIGMADELTA_CHANNEL_4 (4) /*!< Sigma-delta channel 4 */ +#define SIGMADELTA_CHANNEL_5 (5) /*!< Sigma-delta channel 5 */ +#define SIGMADELTA_CHANNEL_6 (6) /*!< Sigma-delta channel 6 */ +#define SIGMADELTA_CHANNEL_7 (7) /*!< Sigma-delta channel 7 */ +#define SIGMADELTA_CHANNEL_MAX (8) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/slc_reg.h b/components/soc/soc/esp32s3/include/soc/slc_reg.h new file mode 100644 index 000000000..e2da76397 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/slc_reg.h @@ -0,0 +1,1906 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SLC_CONF0_REG (DR_REG_SLC_BASE + 0x0) +/* SLC_SLC0_WR_RETRY_MASK_EN : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_MASK_EN (BIT(18)) +#define SLC_SLC0_WR_RETRY_MASK_EN_M (BIT(18)) +#define SLC_SLC0_WR_RETRY_MASK_EN_V 0x1 +#define SLC_SLC0_WR_RETRY_MASK_EN_S 18 +/* SLC_SLC0_TOKEN_SEL : R/W ;bitpos:[15] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TOKEN_SEL (BIT(15)) +#define SLC_SLC0_TOKEN_SEL_M (BIT(15)) +#define SLC_SLC0_TOKEN_SEL_V 0x1 +#define SLC_SLC0_TOKEN_SEL_S 15 +/* SLC_SLC0_TOKEN_AUTO_CLR : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TOKEN_AUTO_CLR (BIT(14)) +#define SLC_SLC0_TOKEN_AUTO_CLR_M (BIT(14)) +#define SLC_SLC0_TOKEN_AUTO_CLR_V 0x1 +#define SLC_SLC0_TOKEN_AUTO_CLR_S 14 +/* SLC_SLC0_TXDATA_BURST_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TXDATA_BURST_EN (BIT(13)) +#define SLC_SLC0_TXDATA_BURST_EN_M (BIT(13)) +#define SLC_SLC0_TXDATA_BURST_EN_V 0x1 +#define SLC_SLC0_TXDATA_BURST_EN_S 13 +/* SLC_SLC0_TXDSCR_BURST_EN : R/W ;bitpos:[12] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TXDSCR_BURST_EN (BIT(12)) +#define SLC_SLC0_TXDSCR_BURST_EN_M (BIT(12)) +#define SLC_SLC0_TXDSCR_BURST_EN_V 0x1 +#define SLC_SLC0_TXDSCR_BURST_EN_S 12 +/* SLC_SLC0_TXLINK_AUTO_RET : R/W ;bitpos:[11] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_AUTO_RET (BIT(11)) +#define SLC_SLC0_TXLINK_AUTO_RET_M (BIT(11)) +#define SLC_SLC0_TXLINK_AUTO_RET_V 0x1 +#define SLC_SLC0_TXLINK_AUTO_RET_S 11 +/* SLC_SLC0_RXLINK_AUTO_RET : R/W ;bitpos:[10] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_AUTO_RET (BIT(10)) +#define SLC_SLC0_RXLINK_AUTO_RET_M (BIT(10)) +#define SLC_SLC0_RXLINK_AUTO_RET_V 0x1 +#define SLC_SLC0_RXLINK_AUTO_RET_S 10 +/* SLC_SLC0_RXDATA_BURST_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RXDATA_BURST_EN (BIT(9)) +#define SLC_SLC0_RXDATA_BURST_EN_M (BIT(9)) +#define SLC_SLC0_RXDATA_BURST_EN_V 0x1 +#define SLC_SLC0_RXDATA_BURST_EN_S 9 +/* SLC_SLC0_RXDSCR_BURST_EN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RXDSCR_BURST_EN (BIT(8)) +#define SLC_SLC0_RXDSCR_BURST_EN_M (BIT(8)) +#define SLC_SLC0_RXDSCR_BURST_EN_V 0x1 +#define SLC_SLC0_RXDSCR_BURST_EN_S 8 +/* SLC_SLC0_RX_NO_RESTART_CLR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_NO_RESTART_CLR (BIT(7)) +#define SLC_SLC0_RX_NO_RESTART_CLR_M (BIT(7)) +#define SLC_SLC0_RX_NO_RESTART_CLR_V 0x1 +#define SLC_SLC0_RX_NO_RESTART_CLR_S 7 +/* SLC_SLC0_RX_AUTO_WRBACK : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_AUTO_WRBACK (BIT(6)) +#define SLC_SLC0_RX_AUTO_WRBACK_M (BIT(6)) +#define SLC_SLC0_RX_AUTO_WRBACK_V 0x1 +#define SLC_SLC0_RX_AUTO_WRBACK_S 6 +/* SLC_SLC0_RX_LOOP_TEST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_LOOP_TEST (BIT(5)) +#define SLC_SLC0_RX_LOOP_TEST_M (BIT(5)) +#define SLC_SLC0_RX_LOOP_TEST_V 0x1 +#define SLC_SLC0_RX_LOOP_TEST_S 5 +/* SLC_SLC0_TX_LOOP_TEST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TX_LOOP_TEST (BIT(4)) +#define SLC_SLC0_TX_LOOP_TEST_M (BIT(4)) +#define SLC_SLC0_TX_LOOP_TEST_V 0x1 +#define SLC_SLC0_TX_LOOP_TEST_S 4 +/* SLC_AHBM_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_AHBM_RST (BIT(3)) +#define SLC_AHBM_RST_M (BIT(3)) +#define SLC_AHBM_RST_V 0x1 +#define SLC_AHBM_RST_S 3 +/* SLC_AHBM_FIFO_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_AHBM_FIFO_RST (BIT(2)) +#define SLC_AHBM_FIFO_RST_M (BIT(2)) +#define SLC_AHBM_FIFO_RST_V 0x1 +#define SLC_AHBM_FIFO_RST_S 2 +/* SLC_SLC0_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_RST (BIT(1)) +#define SLC_SLC0_RX_RST_M (BIT(1)) +#define SLC_SLC0_RX_RST_V 0x1 +#define SLC_SLC0_RX_RST_S 1 +/* SLC_SLC0_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_RST (BIT(0)) +#define SLC_SLC0_TX_RST_M (BIT(0)) +#define SLC_SLC0_TX_RST_V 0x1 +#define SLC_SLC0_TX_RST_S 0 + +#define SLC_0INT_RAW_REG (DR_REG_SLC_BASE + 0x4) +/* SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_M (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_V 0x1 +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_RAW_S 27 +/* SLC_SLC0_RX_QUICK_EOF_INT_RAW : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_RAW_S 26 +/* SLC_CMD_DTC_INT_RAW : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_RAW (BIT(25)) +#define SLC_CMD_DTC_INT_RAW_M (BIT(25)) +#define SLC_CMD_DTC_INT_RAW_V 0x1 +#define SLC_CMD_DTC_INT_RAW_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_RAW : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_RAW (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_RAW_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_RAW_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_RAW : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_RAW_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_RAW : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_RAW (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_RAW_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_RAW_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_RAW_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_RAW : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_RAW_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_RAW : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_RAW_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_RAW_S 19 +/* SLC_SLC0_TOHOST_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_RAW (BIT(18)) +#define SLC_SLC0_TOHOST_INT_RAW_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_RAW_V 0x1 +#define SLC_SLC0_TOHOST_INT_RAW_S 18 +/* SLC_SLC0_RX_EOF_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_RAW (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_RAW_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_RX_EOF_INT_RAW_S 17 +/* SLC_SLC0_RX_DONE_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_RAW (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_RAW_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_RAW_V 0x1 +#define SLC_SLC0_RX_DONE_INT_RAW_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_RAW (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_RAW_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_RAW_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_RAW_S 15 +/* SLC_SLC0_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_RAW (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_RAW_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_RAW_V 0x1 +#define SLC_SLC0_TX_DONE_INT_RAW_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_RAW_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_RAW_S 12 +/* SLC_SLC0_TX_OVF_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_RAW (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_RAW_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_RAW_V 0x1 +#define SLC_SLC0_TX_OVF_INT_RAW_S 11 +/* SLC_SLC0_RX_UDF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_RAW (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_RAW_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_RAW_V 0x1 +#define SLC_SLC0_RX_UDF_INT_RAW_S 10 +/* SLC_SLC0_TX_START_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_RAW (BIT(9)) +#define SLC_SLC0_TX_START_INT_RAW_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_RAW_V 0x1 +#define SLC_SLC0_TX_START_INT_RAW_S 9 +/* SLC_SLC0_RX_START_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_RAW (BIT(8)) +#define SLC_SLC0_RX_START_INT_RAW_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_RAW_V 0x1 +#define SLC_SLC0_RX_START_INT_RAW_S 8 +/* SLC_FRHOST_BIT7_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_RAW (BIT(7)) +#define SLC_FRHOST_BIT7_INT_RAW_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT7_INT_RAW_S 7 +/* SLC_FRHOST_BIT6_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_RAW (BIT(6)) +#define SLC_FRHOST_BIT6_INT_RAW_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT6_INT_RAW_S 6 +/* SLC_FRHOST_BIT5_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_RAW (BIT(5)) +#define SLC_FRHOST_BIT5_INT_RAW_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT5_INT_RAW_S 5 +/* SLC_FRHOST_BIT4_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_RAW (BIT(4)) +#define SLC_FRHOST_BIT4_INT_RAW_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT4_INT_RAW_S 4 +/* SLC_FRHOST_BIT3_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_RAW (BIT(3)) +#define SLC_FRHOST_BIT3_INT_RAW_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT3_INT_RAW_S 3 +/* SLC_FRHOST_BIT2_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_RAW (BIT(2)) +#define SLC_FRHOST_BIT2_INT_RAW_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT2_INT_RAW_S 2 +/* SLC_FRHOST_BIT1_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_RAW (BIT(1)) +#define SLC_FRHOST_BIT1_INT_RAW_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT1_INT_RAW_S 1 +/* SLC_FRHOST_BIT0_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_RAW (BIT(0)) +#define SLC_FRHOST_BIT0_INT_RAW_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_RAW_V 0x1 +#define SLC_FRHOST_BIT0_INT_RAW_S 0 + +#define SLC_0INT_ST_REG (DR_REG_SLC_BASE + 0x8) +/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_M (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_V 0x1 +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST_S 27 +/* SLC_SLC0_RX_QUICK_EOF_INT_ST : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ST (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ST_S 26 +/* SLC_CMD_DTC_INT_ST : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ST (BIT(25)) +#define SLC_CMD_DTC_INT_ST_M (BIT(25)) +#define SLC_CMD_DTC_INT_ST_V 0x1 +#define SLC_CMD_DTC_INT_ST_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ST : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ST (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ST_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ST : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ST (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ST_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ST : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ST (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ST_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ST (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ST_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ST (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ST_S 19 +/* SLC_SLC0_TOHOST_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ST (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST_V 0x1 +#define SLC_SLC0_TOHOST_INT_ST_S 18 +/* SLC_SLC0_RX_EOF_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ST (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ST_S 17 +/* SLC_SLC0_RX_DONE_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ST (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ST_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ST (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ST_S 15 +/* SLC_SLC0_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ST (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ST_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ST (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ST_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ST (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ST_S 12 +/* SLC_SLC0_TX_OVF_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ST (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ST_S 11 +/* SLC_SLC0_RX_UDF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ST (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ST_S 10 +/* SLC_SLC0_TX_START_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ST (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST_V 0x1 +#define SLC_SLC0_TX_START_INT_ST_S 9 +/* SLC_SLC0_RX_START_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ST (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST_V 0x1 +#define SLC_SLC0_RX_START_INT_ST_S 8 +/* SLC_FRHOST_BIT7_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ST (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST_V 0x1 +#define SLC_FRHOST_BIT7_INT_ST_S 7 +/* SLC_FRHOST_BIT6_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ST (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST_V 0x1 +#define SLC_FRHOST_BIT6_INT_ST_S 6 +/* SLC_FRHOST_BIT5_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ST (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST_V 0x1 +#define SLC_FRHOST_BIT5_INT_ST_S 5 +/* SLC_FRHOST_BIT4_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ST (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST_V 0x1 +#define SLC_FRHOST_BIT4_INT_ST_S 4 +/* SLC_FRHOST_BIT3_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ST (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST_V 0x1 +#define SLC_FRHOST_BIT3_INT_ST_S 3 +/* SLC_FRHOST_BIT2_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ST (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST_V 0x1 +#define SLC_FRHOST_BIT2_INT_ST_S 2 +/* SLC_FRHOST_BIT1_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ST (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST_V 0x1 +#define SLC_FRHOST_BIT1_INT_ST_S 1 +/* SLC_FRHOST_BIT0_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ST (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST_V 0x1 +#define SLC_FRHOST_BIT0_INT_ST_S 0 + +#define SLC_0INT_ENA_REG (DR_REG_SLC_BASE + 0xC) +/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_M (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_V 0x1 +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA_S 27 +/* SLC_SLC0_RX_QUICK_EOF_INT_ENA : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA_S 26 +/* SLC_CMD_DTC_INT_ENA : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ENA (BIT(25)) +#define SLC_CMD_DTC_INT_ENA_M (BIT(25)) +#define SLC_CMD_DTC_INT_ENA_V 0x1 +#define SLC_CMD_DTC_INT_ENA_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ENA : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ENA (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ENA_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ENA : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ENA : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ENA (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ENA_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA_S 19 +/* SLC_SLC0_TOHOST_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ENA (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA_V 0x1 +#define SLC_SLC0_TOHOST_INT_ENA_S 18 +/* SLC_SLC0_RX_EOF_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ENA (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ENA_S 17 +/* SLC_SLC0_RX_DONE_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ENA (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ENA_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ENA (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ENA_S 15 +/* SLC_SLC0_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ENA (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ENA_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA_S 12 +/* SLC_SLC0_TX_OVF_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ENA (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ENA_S 11 +/* SLC_SLC0_RX_UDF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ENA (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ENA_S 10 +/* SLC_SLC0_TX_START_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ENA (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA_V 0x1 +#define SLC_SLC0_TX_START_INT_ENA_S 9 +/* SLC_SLC0_RX_START_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ENA (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA_V 0x1 +#define SLC_SLC0_RX_START_INT_ENA_S 8 +/* SLC_FRHOST_BIT7_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ENA (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT7_INT_ENA_S 7 +/* SLC_FRHOST_BIT6_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ENA (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT6_INT_ENA_S 6 +/* SLC_FRHOST_BIT5_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ENA (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT5_INT_ENA_S 5 +/* SLC_FRHOST_BIT4_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ENA (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT4_INT_ENA_S 4 +/* SLC_FRHOST_BIT3_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ENA (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT3_INT_ENA_S 3 +/* SLC_FRHOST_BIT2_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ENA (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT2_INT_ENA_S 2 +/* SLC_FRHOST_BIT1_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ENA (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT1_INT_ENA_S 1 +/* SLC_FRHOST_BIT0_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ENA (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA_V 0x1 +#define SLC_FRHOST_BIT0_INT_ENA_S 0 + +#define SLC_0INT_CLR_REG (DR_REG_SLC_BASE + 0x10) +/* SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_M (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_V 0x1 +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_CLR_S 27 +/* SLC_SLC0_RX_QUICK_EOF_INT_CLR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_CLR_S 26 +/* SLC_CMD_DTC_INT_CLR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_CLR (BIT(25)) +#define SLC_CMD_DTC_INT_CLR_M (BIT(25)) +#define SLC_CMD_DTC_INT_CLR_V 0x1 +#define SLC_CMD_DTC_INT_CLR_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_CLR : WO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_CLR (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_CLR_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_CLR_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_CLR : WO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_CLR_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_CLR : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_CLR (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_CLR_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_CLR_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_CLR_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_CLR_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_CLR_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_CLR_S 19 +/* SLC_SLC0_TOHOST_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_CLR (BIT(18)) +#define SLC_SLC0_TOHOST_INT_CLR_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_CLR_V 0x1 +#define SLC_SLC0_TOHOST_INT_CLR_S 18 +/* SLC_SLC0_RX_EOF_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_CLR (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_CLR_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_RX_EOF_INT_CLR_S 17 +/* SLC_SLC0_RX_DONE_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_CLR (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_CLR_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_CLR_V 0x1 +#define SLC_SLC0_RX_DONE_INT_CLR_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_CLR (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_CLR_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_CLR_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_CLR_S 15 +/* SLC_SLC0_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_CLR (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_CLR_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_CLR_V 0x1 +#define SLC_SLC0_TX_DONE_INT_CLR_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_CLR_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_CLR_S 12 +/* SLC_SLC0_TX_OVF_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_CLR (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_CLR_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_CLR_V 0x1 +#define SLC_SLC0_TX_OVF_INT_CLR_S 11 +/* SLC_SLC0_RX_UDF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_CLR (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_CLR_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_CLR_V 0x1 +#define SLC_SLC0_RX_UDF_INT_CLR_S 10 +/* SLC_SLC0_TX_START_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_CLR (BIT(9)) +#define SLC_SLC0_TX_START_INT_CLR_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_CLR_V 0x1 +#define SLC_SLC0_TX_START_INT_CLR_S 9 +/* SLC_SLC0_RX_START_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_CLR (BIT(8)) +#define SLC_SLC0_RX_START_INT_CLR_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_CLR_V 0x1 +#define SLC_SLC0_RX_START_INT_CLR_S 8 +/* SLC_FRHOST_BIT7_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_CLR (BIT(7)) +#define SLC_FRHOST_BIT7_INT_CLR_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT7_INT_CLR_S 7 +/* SLC_FRHOST_BIT6_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_CLR (BIT(6)) +#define SLC_FRHOST_BIT6_INT_CLR_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT6_INT_CLR_S 6 +/* SLC_FRHOST_BIT5_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_CLR (BIT(5)) +#define SLC_FRHOST_BIT5_INT_CLR_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT5_INT_CLR_S 5 +/* SLC_FRHOST_BIT4_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_CLR (BIT(4)) +#define SLC_FRHOST_BIT4_INT_CLR_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT4_INT_CLR_S 4 +/* SLC_FRHOST_BIT3_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_CLR (BIT(3)) +#define SLC_FRHOST_BIT3_INT_CLR_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT3_INT_CLR_S 3 +/* SLC_FRHOST_BIT2_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_CLR (BIT(2)) +#define SLC_FRHOST_BIT2_INT_CLR_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT2_INT_CLR_S 2 +/* SLC_FRHOST_BIT1_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_CLR (BIT(1)) +#define SLC_FRHOST_BIT1_INT_CLR_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT1_INT_CLR_S 1 +/* SLC_FRHOST_BIT0_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_CLR (BIT(0)) +#define SLC_FRHOST_BIT0_INT_CLR_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_CLR_V 0x1 +#define SLC_FRHOST_BIT0_INT_CLR_S 0 + +#define SLC_RX_STATUS_REG (DR_REG_SLC_BASE + 0x24) +/* SLC_SLC0_RX_BUF_LEN : RO ;bitpos:[13:2] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_BUF_LEN 0x00000FFF +#define SLC_SLC0_RX_BUF_LEN_M ((SLC_SLC0_RX_BUF_LEN_V) << (SLC_SLC0_RX_BUF_LEN_S)) +#define SLC_SLC0_RX_BUF_LEN_V 0xFFF +#define SLC_SLC0_RX_BUF_LEN_S 2 +/* SLC_SLC0_RX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_EMPTY (BIT(1)) +#define SLC_SLC0_RX_EMPTY_M (BIT(1)) +#define SLC_SLC0_RX_EMPTY_V 0x1 +#define SLC_SLC0_RX_EMPTY_S 1 +/* SLC_SLC0_RX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_FULL (BIT(0)) +#define SLC_SLC0_RX_FULL_M (BIT(0)) +#define SLC_SLC0_RX_FULL_V 0x1 +#define SLC_SLC0_RX_FULL_S 0 + +#define SLC_0RXFIFO_PUSH_REG (DR_REG_SLC_BASE + 0x28) +/* SLC_SLC0_RXFIFO_PUSH : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_RXFIFO_PUSH (BIT(16)) +#define SLC_SLC0_RXFIFO_PUSH_M (BIT(16)) +#define SLC_SLC0_RXFIFO_PUSH_V 0x1 +#define SLC_SLC0_RXFIFO_PUSH_S 16 +/* SLC_SLC0_RXFIFO_WDATA : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define SLC_SLC0_RXFIFO_WDATA 0x000001FF +#define SLC_SLC0_RXFIFO_WDATA_M ((SLC_SLC0_RXFIFO_WDATA_V) << (SLC_SLC0_RXFIFO_WDATA_S)) +#define SLC_SLC0_RXFIFO_WDATA_V 0x1FF +#define SLC_SLC0_RXFIFO_WDATA_S 0 + +#define SLC_TX_STATUS_REG (DR_REG_SLC_BASE + 0x30) +/* SLC_SLC0_TX_EMPTY : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TX_EMPTY (BIT(1)) +#define SLC_SLC0_TX_EMPTY_M (BIT(1)) +#define SLC_SLC0_TX_EMPTY_V 0x1 +#define SLC_SLC0_TX_EMPTY_S 1 +/* SLC_SLC0_TX_FULL : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_FULL (BIT(0)) +#define SLC_SLC0_TX_FULL_M (BIT(0)) +#define SLC_SLC0_TX_FULL_V 0x1 +#define SLC_SLC0_TX_FULL_S 0 + +#define SLC_0TXFIFO_POP_REG (DR_REG_SLC_BASE + 0x34) +/* SLC_SLC0_TXFIFO_POP : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TXFIFO_POP (BIT(16)) +#define SLC_SLC0_TXFIFO_POP_M (BIT(16)) +#define SLC_SLC0_TXFIFO_POP_V 0x1 +#define SLC_SLC0_TXFIFO_POP_S 16 +/* SLC_SLC0_TXFIFO_RDATA : RO ;bitpos:[10:0] ;default: 11'h0 ; */ +/*description: */ +#define SLC_SLC0_TXFIFO_RDATA 0x000007FF +#define SLC_SLC0_TXFIFO_RDATA_M ((SLC_SLC0_TXFIFO_RDATA_V) << (SLC_SLC0_TXFIFO_RDATA_S)) +#define SLC_SLC0_TXFIFO_RDATA_V 0x7FF +#define SLC_SLC0_TXFIFO_RDATA_S 0 + +#define SLC_0RX_LINK_REG (DR_REG_SLC_BASE + 0x3C) +/* SLC_SLC0_RXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_PARK (BIT(31)) +#define SLC_SLC0_RXLINK_PARK_M (BIT(31)) +#define SLC_SLC0_RXLINK_PARK_V 0x1 +#define SLC_SLC0_RXLINK_PARK_S 31 +/* SLC_SLC0_RXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_RESTART (BIT(30)) +#define SLC_SLC0_RXLINK_RESTART_M (BIT(30)) +#define SLC_SLC0_RXLINK_RESTART_V 0x1 +#define SLC_SLC0_RXLINK_RESTART_S 30 +/* SLC_SLC0_RXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_START (BIT(29)) +#define SLC_SLC0_RXLINK_START_M (BIT(29)) +#define SLC_SLC0_RXLINK_START_V 0x1 +#define SLC_SLC0_RXLINK_START_S 29 +/* SLC_SLC0_RXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_STOP (BIT(28)) +#define SLC_SLC0_RXLINK_STOP_M (BIT(28)) +#define SLC_SLC0_RXLINK_STOP_V 0x1 +#define SLC_SLC0_RXLINK_STOP_S 28 +/* SLC_SLC0_RXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_ADDR 0x000FFFFF +#define SLC_SLC0_RXLINK_ADDR_M ((SLC_SLC0_RXLINK_ADDR_V) << (SLC_SLC0_RXLINK_ADDR_S)) +#define SLC_SLC0_RXLINK_ADDR_V 0xFFFFF +#define SLC_SLC0_RXLINK_ADDR_S 0 + +#define SLC_0TX_LINK_REG (DR_REG_SLC_BASE + 0x40) +/* SLC_SLC0_TXLINK_PARK : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_PARK (BIT(31)) +#define SLC_SLC0_TXLINK_PARK_M (BIT(31)) +#define SLC_SLC0_TXLINK_PARK_V 0x1 +#define SLC_SLC0_TXLINK_PARK_S 31 +/* SLC_SLC0_TXLINK_RESTART : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_RESTART (BIT(30)) +#define SLC_SLC0_TXLINK_RESTART_M (BIT(30)) +#define SLC_SLC0_TXLINK_RESTART_V 0x1 +#define SLC_SLC0_TXLINK_RESTART_S 30 +/* SLC_SLC0_TXLINK_START : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_START (BIT(29)) +#define SLC_SLC0_TXLINK_START_M (BIT(29)) +#define SLC_SLC0_TXLINK_START_V 0x1 +#define SLC_SLC0_TXLINK_START_S 29 +/* SLC_SLC0_TXLINK_STOP : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_STOP (BIT(28)) +#define SLC_SLC0_TXLINK_STOP_M (BIT(28)) +#define SLC_SLC0_TXLINK_STOP_V 0x1 +#define SLC_SLC0_TXLINK_STOP_S 28 +/* SLC_SLC0_TXLINK_ADDR : R/W ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_ADDR 0x000FFFFF +#define SLC_SLC0_TXLINK_ADDR_M ((SLC_SLC0_TXLINK_ADDR_V) << (SLC_SLC0_TXLINK_ADDR_S)) +#define SLC_SLC0_TXLINK_ADDR_V 0xFFFFF +#define SLC_SLC0_TXLINK_ADDR_S 0 + +#define SLC_INTVEC_TOHOST_REG (DR_REG_SLC_BASE + 0x4C) +/* SLC_SLC0_TOHOST_INTVEC : WO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INTVEC 0x000000FF +#define SLC_SLC0_TOHOST_INTVEC_M ((SLC_SLC0_TOHOST_INTVEC_V) << (SLC_SLC0_TOHOST_INTVEC_S)) +#define SLC_SLC0_TOHOST_INTVEC_V 0xFF +#define SLC_SLC0_TOHOST_INTVEC_S 0 + +#define SLC_0TOKEN0_REG (DR_REG_SLC_BASE + 0x50) +/* SLC_SLC0_TOKEN0 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0 0x00000FFF +#define SLC_SLC0_TOKEN0_M ((SLC_SLC0_TOKEN0_V) << (SLC_SLC0_TOKEN0_S)) +#define SLC_SLC0_TOKEN0_V 0xFFF +#define SLC_SLC0_TOKEN0_S 16 +/* SLC_SLC0_TOKEN0_INC_MORE : WO ;bitpos:[14] ;default: 1'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_INC_MORE (BIT(14)) +#define SLC_SLC0_TOKEN0_INC_MORE_M (BIT(14)) +#define SLC_SLC0_TOKEN0_INC_MORE_V 0x1 +#define SLC_SLC0_TOKEN0_INC_MORE_S 14 +/* SLC_SLC0_TOKEN0_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_INC (BIT(13)) +#define SLC_SLC0_TOKEN0_INC_M (BIT(13)) +#define SLC_SLC0_TOKEN0_INC_V 0x1 +#define SLC_SLC0_TOKEN0_INC_S 13 +/* SLC_SLC0_TOKEN0_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_WR (BIT(12)) +#define SLC_SLC0_TOKEN0_WR_M (BIT(12)) +#define SLC_SLC0_TOKEN0_WR_V 0x1 +#define SLC_SLC0_TOKEN0_WR_S 12 +/* SLC_SLC0_TOKEN0_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_WDATA 0x00000FFF +#define SLC_SLC0_TOKEN0_WDATA_M ((SLC_SLC0_TOKEN0_WDATA_V) << (SLC_SLC0_TOKEN0_WDATA_S)) +#define SLC_SLC0_TOKEN0_WDATA_V 0xFFF +#define SLC_SLC0_TOKEN0_WDATA_S 0 + +#define SLC_0TOKEN1_REG (DR_REG_SLC_BASE + 0x54) +/* SLC_SLC0_TOKEN1 : RO ;bitpos:[27:16] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1 0x00000FFF +#define SLC_SLC0_TOKEN1_M ((SLC_SLC0_TOKEN1_V) << (SLC_SLC0_TOKEN1_S)) +#define SLC_SLC0_TOKEN1_V 0xFFF +#define SLC_SLC0_TOKEN1_S 16 +/* SLC_SLC0_TOKEN1_INC_MORE : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_INC_MORE (BIT(14)) +#define SLC_SLC0_TOKEN1_INC_MORE_M (BIT(14)) +#define SLC_SLC0_TOKEN1_INC_MORE_V 0x1 +#define SLC_SLC0_TOKEN1_INC_MORE_S 14 +/* SLC_SLC0_TOKEN1_INC : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_INC (BIT(13)) +#define SLC_SLC0_TOKEN1_INC_M (BIT(13)) +#define SLC_SLC0_TOKEN1_INC_V 0x1 +#define SLC_SLC0_TOKEN1_INC_S 13 +/* SLC_SLC0_TOKEN1_WR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_WR (BIT(12)) +#define SLC_SLC0_TOKEN1_WR_M (BIT(12)) +#define SLC_SLC0_TOKEN1_WR_V 0x1 +#define SLC_SLC0_TOKEN1_WR_S 12 +/* SLC_SLC0_TOKEN1_WDATA : WO ;bitpos:[11:0] ;default: 12'h0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_WDATA 0x00000FFF +#define SLC_SLC0_TOKEN1_WDATA_M ((SLC_SLC0_TOKEN1_WDATA_V) << (SLC_SLC0_TOKEN1_WDATA_S)) +#define SLC_SLC0_TOKEN1_WDATA_V 0xFFF +#define SLC_SLC0_TOKEN1_WDATA_S 0 + +#define SLC_CONF1_REG (DR_REG_SLC_BASE + 0x60) +/* SLC_CLK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CLK_EN (BIT(22)) +#define SLC_CLK_EN_M (BIT(22)) +#define SLC_CLK_EN_V 0x1 +#define SLC_CLK_EN_S 22 +/* SLC_HOST_INT_LEVEL_SEL : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_HOST_INT_LEVEL_SEL (BIT(19)) +#define SLC_HOST_INT_LEVEL_SEL_M (BIT(19)) +#define SLC_HOST_INT_LEVEL_SEL_V 0x1 +#define SLC_HOST_INT_LEVEL_SEL_S 19 +/* SLC_SLC0_RX_STITCH_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_STITCH_EN (BIT(6)) +#define SLC_SLC0_RX_STITCH_EN_M (BIT(6)) +#define SLC_SLC0_RX_STITCH_EN_V 0x1 +#define SLC_SLC0_RX_STITCH_EN_S 6 +/* SLC_SLC0_TX_STITCH_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_TX_STITCH_EN (BIT(5)) +#define SLC_SLC0_TX_STITCH_EN_M (BIT(5)) +#define SLC_SLC0_TX_STITCH_EN_V 0x1 +#define SLC_SLC0_TX_STITCH_EN_S 5 +/* SLC_SLC0_LEN_AUTO_CLR : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_LEN_AUTO_CLR (BIT(4)) +#define SLC_SLC0_LEN_AUTO_CLR_M (BIT(4)) +#define SLC_SLC0_LEN_AUTO_CLR_V 0x1 +#define SLC_SLC0_LEN_AUTO_CLR_S 4 +/* SLC_CMD_HOLD_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SLC_CMD_HOLD_EN (BIT(3)) +#define SLC_CMD_HOLD_EN_M (BIT(3)) +#define SLC_CMD_HOLD_EN_V 0x1 +#define SLC_CMD_HOLD_EN_S 3 +/* SLC_SLC0_RX_CHECK_SUM_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_CHECK_SUM_EN (BIT(2)) +#define SLC_SLC0_RX_CHECK_SUM_EN_M (BIT(2)) +#define SLC_SLC0_RX_CHECK_SUM_EN_V 0x1 +#define SLC_SLC0_RX_CHECK_SUM_EN_S 2 +/* SLC_SLC0_TX_CHECK_SUM_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_CHECK_SUM_EN (BIT(1)) +#define SLC_SLC0_TX_CHECK_SUM_EN_M (BIT(1)) +#define SLC_SLC0_TX_CHECK_SUM_EN_V 0x1 +#define SLC_SLC0_TX_CHECK_SUM_EN_S 1 +/* SLC_SLC0_CHECK_OWNER : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_CHECK_OWNER (BIT(0)) +#define SLC_SLC0_CHECK_OWNER_M (BIT(0)) +#define SLC_SLC0_CHECK_OWNER_V 0x1 +#define SLC_SLC0_CHECK_OWNER_S 0 + +#define SLC_0_STATE0_REG (DR_REG_SLC_BASE + 0x64) +/* SLC_SLC0_STATE0 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_STATE0 0xFFFFFFFF +#define SLC_SLC0_STATE0_M ((SLC_SLC0_STATE0_V) << (SLC_SLC0_STATE0_S)) +#define SLC_SLC0_STATE0_V 0xFFFFFFFF +#define SLC_SLC0_STATE0_S 0 + +#define SLC_0_STATE1_REG (DR_REG_SLC_BASE + 0x68) +/* SLC_SLC0_STATE1 : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_STATE1 0xFFFFFFFF +#define SLC_SLC0_STATE1_M ((SLC_SLC0_STATE1_V) << (SLC_SLC0_STATE1_S)) +#define SLC_SLC0_STATE1_V 0xFFFFFFFF +#define SLC_SLC0_STATE1_S 0 + +#define SLC_BRIDGE_CONF_REG (DR_REG_SLC_BASE + 0x74) +/* SLC_TX_PUSH_IDLE_NUM : R/W ;bitpos:[31:16] ;default: 16'ha ; */ +/*description: */ +#define SLC_TX_PUSH_IDLE_NUM 0x0000FFFF +#define SLC_TX_PUSH_IDLE_NUM_M ((SLC_TX_PUSH_IDLE_NUM_V) << (SLC_TX_PUSH_IDLE_NUM_S)) +#define SLC_TX_PUSH_IDLE_NUM_V 0xFFFF +#define SLC_TX_PUSH_IDLE_NUM_S 16 +/* SLC_HDA_MAP_128K : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: */ +#define SLC_HDA_MAP_128K (BIT(13)) +#define SLC_HDA_MAP_128K_M (BIT(13)) +#define SLC_HDA_MAP_128K_V 0x1 +#define SLC_HDA_MAP_128K_S 13 +/* SLC_SLC0_TX_DUMMY_MODE : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: */ +#define SLC_SLC0_TX_DUMMY_MODE (BIT(12)) +#define SLC_SLC0_TX_DUMMY_MODE_M (BIT(12)) +#define SLC_SLC0_TX_DUMMY_MODE_V 0x1 +#define SLC_SLC0_TX_DUMMY_MODE_S 12 +/* SLC_FIFO_MAP_ENA : R/W ;bitpos:[11:8] ;default: 4'h7 ; */ +/*description: */ +#define SLC_FIFO_MAP_ENA 0x0000000F +#define SLC_FIFO_MAP_ENA_M ((SLC_FIFO_MAP_ENA_V) << (SLC_FIFO_MAP_ENA_S)) +#define SLC_FIFO_MAP_ENA_V 0xF +#define SLC_FIFO_MAP_ENA_S 8 +/* SLC_TXEOF_ENA : R/W ;bitpos:[5:0] ;default: 6'h20 ; */ +/*description: */ +#define SLC_TXEOF_ENA 0x0000003F +#define SLC_TXEOF_ENA_M ((SLC_TXEOF_ENA_V) << (SLC_TXEOF_ENA_S)) +#define SLC_TXEOF_ENA_V 0x3F +#define SLC_TXEOF_ENA_S 0 + +#define SLC_0_TO_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x78) +/* SLC_SLC0_TO_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TO_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_DES_ADDR_M ((SLC_SLC0_TO_EOF_DES_ADDR_V) << (SLC_SLC0_TO_EOF_DES_ADDR_S)) +#define SLC_SLC0_TO_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_DES_ADDR_S 0 + +#define SLC_0_TX_EOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0x7C) +/* SLC_SLC0_TX_SUC_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_M ((SLC_SLC0_TX_SUC_EOF_DES_ADDR_V) << (SLC_SLC0_TX_SUC_EOF_DES_ADDR_S)) +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_SUC_EOF_DES_ADDR_S 0 + +#define SLC_0_TO_EOF_BFR_DES_ADDR_REG (DR_REG_SLC_BASE + 0x80) +/* SLC_SLC0_TO_EOF_BFR_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_M ((SLC_SLC0_TO_EOF_BFR_DES_ADDR_V) << (SLC_SLC0_TO_EOF_BFR_DES_ADDR_S)) +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TO_EOF_BFR_DES_ADDR_S 0 + +#define SLC_AHB_TEST_REG (DR_REG_SLC_BASE + 0x90) +/* SLC_AHB_TESTADDR : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: */ +#define SLC_AHB_TESTADDR 0x00000003 +#define SLC_AHB_TESTADDR_M ((SLC_AHB_TESTADDR_V) << (SLC_AHB_TESTADDR_S)) +#define SLC_AHB_TESTADDR_V 0x3 +#define SLC_AHB_TESTADDR_S 4 +/* SLC_AHB_TESTMODE : R/W ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define SLC_AHB_TESTMODE 0x00000007 +#define SLC_AHB_TESTMODE_M ((SLC_AHB_TESTMODE_V) << (SLC_AHB_TESTMODE_S)) +#define SLC_AHB_TESTMODE_V 0x7 +#define SLC_AHB_TESTMODE_S 0 + +#define SLC_SDIO_ST_REG (DR_REG_SLC_BASE + 0x94) +/* SLC_FUNC1_ACC_STATE : RO ;bitpos:[20:16] ;default: 5'b0 ; */ +/*description: */ +#define SLC_FUNC1_ACC_STATE 0x0000001F +#define SLC_FUNC1_ACC_STATE_M ((SLC_FUNC1_ACC_STATE_V) << (SLC_FUNC1_ACC_STATE_S)) +#define SLC_FUNC1_ACC_STATE_V 0x1F +#define SLC_FUNC1_ACC_STATE_S 16 +/* SLC_BUS_ST : RO ;bitpos:[14:12] ;default: 3'b0 ; */ +/*description: */ +#define SLC_BUS_ST 0x00000007 +#define SLC_BUS_ST_M ((SLC_BUS_ST_V) << (SLC_BUS_ST_S)) +#define SLC_BUS_ST_V 0x7 +#define SLC_BUS_ST_S 12 +/* SLC_SDIO_WAKEUP : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SDIO_WAKEUP (BIT(8)) +#define SLC_SDIO_WAKEUP_M (BIT(8)) +#define SLC_SDIO_WAKEUP_V 0x1 +#define SLC_SDIO_WAKEUP_S 8 +/* SLC_FUNC_ST : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: */ +#define SLC_FUNC_ST 0x0000000F +#define SLC_FUNC_ST_M ((SLC_FUNC_ST_V) << (SLC_FUNC_ST_S)) +#define SLC_FUNC_ST_V 0xF +#define SLC_FUNC_ST_S 4 +/* SLC_CMD_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define SLC_CMD_ST 0x00000007 +#define SLC_CMD_ST_M ((SLC_CMD_ST_V) << (SLC_CMD_ST_S)) +#define SLC_CMD_ST_V 0x7 +#define SLC_CMD_ST_S 0 + +#define SLC_RX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0x98) +/* SLC_SLC0_RD_RETRY_THRESHOLD : R/W ;bitpos:[15:5] ;default: 11'h80 ; */ +/*description: */ +#define SLC_SLC0_RD_RETRY_THRESHOLD 0x000007FF +#define SLC_SLC0_RD_RETRY_THRESHOLD_M ((SLC_SLC0_RD_RETRY_THRESHOLD_V) << (SLC_SLC0_RD_RETRY_THRESHOLD_S)) +#define SLC_SLC0_RD_RETRY_THRESHOLD_V 0x7FF +#define SLC_SLC0_RD_RETRY_THRESHOLD_S 5 +/* SLC_SLC0_RX_FILL_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_FILL_EN (BIT(4)) +#define SLC_SLC0_RX_FILL_EN_M (BIT(4)) +#define SLC_SLC0_RX_FILL_EN_V 0x1 +#define SLC_SLC0_RX_FILL_EN_S 4 +/* SLC_SLC0_RX_EOF_MODE : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_MODE (BIT(3)) +#define SLC_SLC0_RX_EOF_MODE_M (BIT(3)) +#define SLC_SLC0_RX_EOF_MODE_V 0x1 +#define SLC_SLC0_RX_EOF_MODE_S 3 +/* SLC_SLC0_RX_FILL_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_FILL_MODE (BIT(2)) +#define SLC_SLC0_RX_FILL_MODE_M (BIT(2)) +#define SLC_SLC0_RX_FILL_MODE_V 0x1 +#define SLC_SLC0_RX_FILL_MODE_S 2 +/* SLC_SLC0_INFOR_NO_REPLACE : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SLC_SLC0_INFOR_NO_REPLACE (BIT(1)) +#define SLC_SLC0_INFOR_NO_REPLACE_M (BIT(1)) +#define SLC_SLC0_INFOR_NO_REPLACE_V 0x1 +#define SLC_SLC0_INFOR_NO_REPLACE_S 1 +/* SLC_SLC0_TOKEN_NO_REPLACE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN_NO_REPLACE (BIT(0)) +#define SLC_SLC0_TOKEN_NO_REPLACE_M (BIT(0)) +#define SLC_SLC0_TOKEN_NO_REPLACE_V 0x1 +#define SLC_SLC0_TOKEN_NO_REPLACE_S 0 + +#define SLC_0_TXLINK_DSCR_REG (DR_REG_SLC_BASE + 0x9C) +/* SLC_SLC0_TXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_DSCR 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_M ((SLC_SLC0_TXLINK_DSCR_V) << (SLC_SLC0_TXLINK_DSCR_S)) +#define SLC_SLC0_TXLINK_DSCR_V 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_S 0 + +#define SLC_0_TXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xA0) +/* SLC_SLC0_TXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_DSCR_BF0 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF0_M ((SLC_SLC0_TXLINK_DSCR_BF0_V) << (SLC_SLC0_TXLINK_DSCR_BF0_S)) +#define SLC_SLC0_TXLINK_DSCR_BF0_V 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF0_S 0 + +#define SLC_0_TXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xA4) +/* SLC_SLC0_TXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_TXLINK_DSCR_BF1 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF1_M ((SLC_SLC0_TXLINK_DSCR_BF1_V) << (SLC_SLC0_TXLINK_DSCR_BF1_S)) +#define SLC_SLC0_TXLINK_DSCR_BF1_V 0xFFFFFFFF +#define SLC_SLC0_TXLINK_DSCR_BF1_S 0 + +#define SLC_0_RXLINK_DSCR_REG (DR_REG_SLC_BASE + 0xA8) +/* SLC_SLC0_RXLINK_DSCR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_DSCR 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_M ((SLC_SLC0_RXLINK_DSCR_V) << (SLC_SLC0_RXLINK_DSCR_S)) +#define SLC_SLC0_RXLINK_DSCR_V 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_S 0 + +#define SLC_0_RXLINK_DSCR_BF0_REG (DR_REG_SLC_BASE + 0xAC) +/* SLC_SLC0_RXLINK_DSCR_BF0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_DSCR_BF0 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF0_M ((SLC_SLC0_RXLINK_DSCR_BF0_V) << (SLC_SLC0_RXLINK_DSCR_BF0_S)) +#define SLC_SLC0_RXLINK_DSCR_BF0_V 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF0_S 0 + +#define SLC_0_RXLINK_DSCR_BF1_REG (DR_REG_SLC_BASE + 0xB0) +/* SLC_SLC0_RXLINK_DSCR_BF1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RXLINK_DSCR_BF1 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF1_M ((SLC_SLC0_RXLINK_DSCR_BF1_V) << (SLC_SLC0_RXLINK_DSCR_BF1_S)) +#define SLC_SLC0_RXLINK_DSCR_BF1_V 0xFFFFFFFF +#define SLC_SLC0_RXLINK_DSCR_BF1_S 0 + +#define SLC_0_TX_ERREOF_DES_ADDR_REG (DR_REG_SLC_BASE + 0xCC) +/* SLC_SLC0_TX_ERR_EOF_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_M ((SLC_SLC0_TX_ERR_EOF_DES_ADDR_V) << (SLC_SLC0_TX_ERR_EOF_DES_ADDR_S)) +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_ERR_EOF_DES_ADDR_S 0 + +#define SLC_TOKEN_LAT_REG (DR_REG_SLC_BASE + 0xD4) +/* SLC_SLC0_TOKEN : RO ;bitpos:[11:0] ;default: 12'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN 0x00000FFF +#define SLC_SLC0_TOKEN_M ((SLC_SLC0_TOKEN_V) << (SLC_SLC0_TOKEN_S)) +#define SLC_SLC0_TOKEN_V 0xFFF +#define SLC_SLC0_TOKEN_S 0 + +#define SLC_TX_DSCR_CONF_REG (DR_REG_SLC_BASE + 0xD8) +/* SLC_WR_RETRY_THRESHOLD : R/W ;bitpos:[10:0] ;default: 11'h80 ; */ +/*description: */ +#define SLC_WR_RETRY_THRESHOLD 0x000007FF +#define SLC_WR_RETRY_THRESHOLD_M ((SLC_WR_RETRY_THRESHOLD_V) << (SLC_WR_RETRY_THRESHOLD_S)) +#define SLC_WR_RETRY_THRESHOLD_V 0x7FF +#define SLC_WR_RETRY_THRESHOLD_S 0 + +#define SLC_CMD_INFOR0_REG (DR_REG_SLC_BASE + 0xDC) +/* SLC_CMD_CONTENT0 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_CMD_CONTENT0 0xFFFFFFFF +#define SLC_CMD_CONTENT0_M ((SLC_CMD_CONTENT0_V) << (SLC_CMD_CONTENT0_S)) +#define SLC_CMD_CONTENT0_V 0xFFFFFFFF +#define SLC_CMD_CONTENT0_S 0 + +#define SLC_CMD_INFOR1_REG (DR_REG_SLC_BASE + 0xE0) +/* SLC_CMD_CONTENT1 : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_CMD_CONTENT1 0xFFFFFFFF +#define SLC_CMD_CONTENT1_M ((SLC_CMD_CONTENT1_V) << (SLC_CMD_CONTENT1_S)) +#define SLC_CMD_CONTENT1_V 0xFFFFFFFF +#define SLC_CMD_CONTENT1_S 0 + +#define SLC_0_LEN_CONF_REG (DR_REG_SLC_BASE + 0xE4) +/* SLC_SLC0_TX_NEW_PKT_IND : RO ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_NEW_PKT_IND (BIT(28)) +#define SLC_SLC0_TX_NEW_PKT_IND_M (BIT(28)) +#define SLC_SLC0_TX_NEW_PKT_IND_V 0x1 +#define SLC_SLC0_TX_NEW_PKT_IND_S 28 +/* SLC_SLC0_RX_NEW_PKT_IND : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_NEW_PKT_IND (BIT(27)) +#define SLC_SLC0_RX_NEW_PKT_IND_M (BIT(27)) +#define SLC_SLC0_RX_NEW_PKT_IND_V 0x1 +#define SLC_SLC0_RX_NEW_PKT_IND_S 27 +/* SLC_SLC0_TX_GET_USED_DSCR : WO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_GET_USED_DSCR (BIT(26)) +#define SLC_SLC0_TX_GET_USED_DSCR_M (BIT(26)) +#define SLC_SLC0_TX_GET_USED_DSCR_V 0x1 +#define SLC_SLC0_TX_GET_USED_DSCR_S 26 +/* SLC_SLC0_RX_GET_USED_DSCR : WO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_GET_USED_DSCR (BIT(25)) +#define SLC_SLC0_RX_GET_USED_DSCR_M (BIT(25)) +#define SLC_SLC0_RX_GET_USED_DSCR_V 0x1 +#define SLC_SLC0_RX_GET_USED_DSCR_S 25 +/* SLC_SLC0_TX_PACKET_LOAD_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_PACKET_LOAD_EN (BIT(24)) +#define SLC_SLC0_TX_PACKET_LOAD_EN_M (BIT(24)) +#define SLC_SLC0_TX_PACKET_LOAD_EN_V 0x1 +#define SLC_SLC0_TX_PACKET_LOAD_EN_S 24 +/* SLC_SLC0_RX_PACKET_LOAD_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_PACKET_LOAD_EN (BIT(23)) +#define SLC_SLC0_RX_PACKET_LOAD_EN_M (BIT(23)) +#define SLC_SLC0_RX_PACKET_LOAD_EN_V 0x1 +#define SLC_SLC0_RX_PACKET_LOAD_EN_S 23 +/* SLC_SLC0_LEN_INC_MORE : WO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_LEN_INC_MORE (BIT(22)) +#define SLC_SLC0_LEN_INC_MORE_M (BIT(22)) +#define SLC_SLC0_LEN_INC_MORE_V 0x1 +#define SLC_SLC0_LEN_INC_MORE_S 22 +/* SLC_SLC0_LEN_INC : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_LEN_INC (BIT(21)) +#define SLC_SLC0_LEN_INC_M (BIT(21)) +#define SLC_SLC0_LEN_INC_V 0x1 +#define SLC_SLC0_LEN_INC_S 21 +/* SLC_SLC0_LEN_WR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_LEN_WR (BIT(20)) +#define SLC_SLC0_LEN_WR_M (BIT(20)) +#define SLC_SLC0_LEN_WR_V 0x1 +#define SLC_SLC0_LEN_WR_S 20 +/* SLC_SLC0_LEN_WDATA : WO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_LEN_WDATA 0x000FFFFF +#define SLC_SLC0_LEN_WDATA_M ((SLC_SLC0_LEN_WDATA_V) << (SLC_SLC0_LEN_WDATA_S)) +#define SLC_SLC0_LEN_WDATA_V 0xFFFFF +#define SLC_SLC0_LEN_WDATA_S 0 + +#define SLC_0_LENGTH_REG (DR_REG_SLC_BASE + 0xE8) +/* SLC_SLC0_LEN : RO ;bitpos:[19:0] ;default: 20'h0 ; */ +/*description: */ +#define SLC_SLC0_LEN 0x000FFFFF +#define SLC_SLC0_LEN_M ((SLC_SLC0_LEN_V) << (SLC_SLC0_LEN_S)) +#define SLC_SLC0_LEN_V 0xFFFFF +#define SLC_SLC0_LEN_S 0 + +#define SLC_0_TXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xEC) +/* SLC_SLC0_TX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_H_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_H_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_H_DSCR_ADDR_S 0 + +#define SLC_0_TXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF0) +/* SLC_SLC0_TX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_E_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_E_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_E_DSCR_ADDR_S 0 + +#define SLC_0_RXPKT_H_DSCR_REG (DR_REG_SLC_BASE + 0xF4) +/* SLC_SLC0_RX_PKT_H_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_H_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_H_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_H_DSCR_ADDR_S 0 + +#define SLC_0_RXPKT_E_DSCR_REG (DR_REG_SLC_BASE + 0xF8) +/* SLC_SLC0_RX_PKT_E_DSCR_ADDR : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_E_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_E_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_E_DSCR_ADDR_S 0 + +#define SLC_0_TXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0xFC) +/* SLC_SLC0_TX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_START_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_START_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_START_DSCR_ADDR_S 0 + +#define SLC_0_TXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x100) +/* SLC_SLC0_TX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_TX_PKT_END_DSCR_ADDR_V) << (SLC_SLC0_TX_PKT_END_DSCR_ADDR_S)) +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_TX_PKT_END_DSCR_ADDR_S 0 + +#define SLC_0_RXPKTU_H_DSCR_REG (DR_REG_SLC_BASE + 0x104) +/* SLC_SLC0_RX_PKT_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_START_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_START_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_START_DSCR_ADDR_S 0 + +#define SLC_0_RXPKTU_E_DSCR_REG (DR_REG_SLC_BASE + 0x108) +/* SLC_SLC0_RX_PKT_END_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_M ((SLC_SLC0_RX_PKT_END_DSCR_ADDR_V) << (SLC_SLC0_RX_PKT_END_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PKT_END_DSCR_ADDR_S 0 + +#define SLC_SEQ_POSITION_REG (DR_REG_SLC_BASE + 0x114) +/* SLC_SLC0_SEQ_POSITION : R/W ;bitpos:[7:0] ;default: 8'h9 ; */ +/*description: */ +#define SLC_SLC0_SEQ_POSITION 0x000000FF +#define SLC_SLC0_SEQ_POSITION_M ((SLC_SLC0_SEQ_POSITION_V) << (SLC_SLC0_SEQ_POSITION_S)) +#define SLC_SLC0_SEQ_POSITION_V 0xFF +#define SLC_SLC0_SEQ_POSITION_S 0 + +#define SLC_0_DSCR_REC_CONF_REG (DR_REG_SLC_BASE + 0x118) +/* SLC_SLC0_RX_DSCR_REC_LIM : R/W ;bitpos:[9:0] ;default: 10'h3ff ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_REC_LIM 0x000003FF +#define SLC_SLC0_RX_DSCR_REC_LIM_M ((SLC_SLC0_RX_DSCR_REC_LIM_V) << (SLC_SLC0_RX_DSCR_REC_LIM_S)) +#define SLC_SLC0_RX_DSCR_REC_LIM_V 0x3FF +#define SLC_SLC0_RX_DSCR_REC_LIM_S 0 + +#define SLC_SDIO_CRC_ST0_REG (DR_REG_SLC_BASE + 0x11C) +/* SLC_DAT3_CRC_ERR_CNT : RO ;bitpos:[31:24] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT3_CRC_ERR_CNT 0x000000FF +#define SLC_DAT3_CRC_ERR_CNT_M ((SLC_DAT3_CRC_ERR_CNT_V) << (SLC_DAT3_CRC_ERR_CNT_S)) +#define SLC_DAT3_CRC_ERR_CNT_V 0xFF +#define SLC_DAT3_CRC_ERR_CNT_S 24 +/* SLC_DAT2_CRC_ERR_CNT : RO ;bitpos:[23:16] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT2_CRC_ERR_CNT 0x000000FF +#define SLC_DAT2_CRC_ERR_CNT_M ((SLC_DAT2_CRC_ERR_CNT_V) << (SLC_DAT2_CRC_ERR_CNT_S)) +#define SLC_DAT2_CRC_ERR_CNT_V 0xFF +#define SLC_DAT2_CRC_ERR_CNT_S 16 +/* SLC_DAT1_CRC_ERR_CNT : RO ;bitpos:[15:8] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT1_CRC_ERR_CNT 0x000000FF +#define SLC_DAT1_CRC_ERR_CNT_M ((SLC_DAT1_CRC_ERR_CNT_V) << (SLC_DAT1_CRC_ERR_CNT_S)) +#define SLC_DAT1_CRC_ERR_CNT_V 0xFF +#define SLC_DAT1_CRC_ERR_CNT_S 8 +/* SLC_DAT0_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SLC_DAT0_CRC_ERR_CNT 0x000000FF +#define SLC_DAT0_CRC_ERR_CNT_M ((SLC_DAT0_CRC_ERR_CNT_V) << (SLC_DAT0_CRC_ERR_CNT_S)) +#define SLC_DAT0_CRC_ERR_CNT_V 0xFF +#define SLC_DAT0_CRC_ERR_CNT_S 0 + +#define SLC_SDIO_CRC_ST1_REG (DR_REG_SLC_BASE + 0x120) +/* SLC_ERR_CNT_CLR : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SLC_ERR_CNT_CLR (BIT(31)) +#define SLC_ERR_CNT_CLR_M (BIT(31)) +#define SLC_ERR_CNT_CLR_V 0x1 +#define SLC_ERR_CNT_CLR_S 31 +/* SLC_CMD_CRC_ERR_CNT : RO ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SLC_CMD_CRC_ERR_CNT 0x000000FF +#define SLC_CMD_CRC_ERR_CNT_M ((SLC_CMD_CRC_ERR_CNT_V) << (SLC_CMD_CRC_ERR_CNT_S)) +#define SLC_CMD_CRC_ERR_CNT_V 0xFF +#define SLC_CMD_CRC_ERR_CNT_S 0 + +#define SLC_0_EOF_START_DES_REG (DR_REG_SLC_BASE + 0x124) +/* SLC_SLC0_EOF_START_DES_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_EOF_START_DES_ADDR 0xFFFFFFFF +#define SLC_SLC0_EOF_START_DES_ADDR_M ((SLC_SLC0_EOF_START_DES_ADDR_V) << (SLC_SLC0_EOF_START_DES_ADDR_S)) +#define SLC_SLC0_EOF_START_DES_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_EOF_START_DES_ADDR_S 0 + +#define SLC_0_PUSH_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x128) +/* SLC_SLC0_RX_PUSH_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_PUSH_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_PUSH_DSCR_ADDR_M ((SLC_SLC0_RX_PUSH_DSCR_ADDR_V) << (SLC_SLC0_RX_PUSH_DSCR_ADDR_S)) +#define SLC_SLC0_RX_PUSH_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_PUSH_DSCR_ADDR_S 0 + +#define SLC_0_DONE_DSCR_ADDR_REG (DR_REG_SLC_BASE + 0x12C) +/* SLC_SLC0_RX_DONE_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_RX_DONE_DSCR_ADDR_M ((SLC_SLC0_RX_DONE_DSCR_ADDR_V) << (SLC_SLC0_RX_DONE_DSCR_ADDR_S)) +#define SLC_SLC0_RX_DONE_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_RX_DONE_DSCR_ADDR_S 0 + +#define SLC_0_SUB_START_DES_REG (DR_REG_SLC_BASE + 0x130) +/* SLC_SLC0_SUB_PAC_START_DSCR_ADDR : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR 0xFFFFFFFF +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_M ((SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V) << (SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S)) +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_V 0xFFFFFFFF +#define SLC_SLC0_SUB_PAC_START_DSCR_ADDR_S 0 + +#define SLC_0_DSCR_CNT_REG (DR_REG_SLC_BASE + 0x134) +/* SLC_SLC0_RX_GET_EOF_OCC : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_GET_EOF_OCC (BIT(16)) +#define SLC_SLC0_RX_GET_EOF_OCC_M (BIT(16)) +#define SLC_SLC0_RX_GET_EOF_OCC_V 0x1 +#define SLC_SLC0_RX_GET_EOF_OCC_S 16 +/* SLC_SLC0_RX_DSCR_CNT_LAT : RO ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_CNT_LAT 0x000003FF +#define SLC_SLC0_RX_DSCR_CNT_LAT_M ((SLC_SLC0_RX_DSCR_CNT_LAT_V) << (SLC_SLC0_RX_DSCR_CNT_LAT_S)) +#define SLC_SLC0_RX_DSCR_CNT_LAT_V 0x3FF +#define SLC_SLC0_RX_DSCR_CNT_LAT_S 0 + +#define SLC_0_LEN_LIM_CONF_REG (DR_REG_SLC_BASE + 0x138) +/* SLC_SLC0_LEN_LIM : R/W ;bitpos:[19:0] ;default: 20'h5400 ; */ +/*description: */ +#define SLC_SLC0_LEN_LIM 0x000FFFFF +#define SLC_SLC0_LEN_LIM_M ((SLC_SLC0_LEN_LIM_V) << (SLC_SLC0_LEN_LIM_S)) +#define SLC_SLC0_LEN_LIM_V 0xFFFFF +#define SLC_SLC0_LEN_LIM_S 0 + +#define SLC_0INT_ST1_REG (DR_REG_SLC_BASE + 0x13C) +/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 : RO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1 (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_M (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_V 0x1 +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ST1_S 27 +/* SLC_SLC0_RX_QUICK_EOF_INT_ST1 : RO ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1 (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ST1_S 26 +/* SLC_CMD_DTC_INT_ST1 : RO ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ST1 (BIT(25)) +#define SLC_CMD_DTC_INT_ST1_M (BIT(25)) +#define SLC_CMD_DTC_INT_ST1_V 0x1 +#define SLC_CMD_DTC_INT_ST1_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ST1 : RO ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ST1 (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST1_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ST1_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ST1 : RO ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1 (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ST1_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ST1 : RO ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ST1 (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST1_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ST1_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ST1_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1 (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ST1_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ST1 : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1 (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ST1_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ST1 : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1 (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ST1_S 19 +/* SLC_SLC0_TOHOST_INT_ST1 : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ST1 (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST1_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ST1_V 0x1 +#define SLC_SLC0_TOHOST_INT_ST1_S 18 +/* SLC_SLC0_RX_EOF_INT_ST1 : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ST1 (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST1_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ST1_S 17 +/* SLC_SLC0_RX_DONE_INT_ST1 : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ST1 (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST1_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ST1_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ST1_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ST1 : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ST1 (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST1_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ST1_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ST1_S 15 +/* SLC_SLC0_TX_DONE_INT_ST1 : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ST1 (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST1_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ST1_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ST1_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ST1 : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1 (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ST1_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ST1 : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1 (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ST1_S 12 +/* SLC_SLC0_TX_OVF_INT_ST1 : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ST1 (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST1_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ST1_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ST1_S 11 +/* SLC_SLC0_RX_UDF_INT_ST1 : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ST1 (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST1_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ST1_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ST1_S 10 +/* SLC_SLC0_TX_START_INT_ST1 : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ST1 (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST1_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ST1_V 0x1 +#define SLC_SLC0_TX_START_INT_ST1_S 9 +/* SLC_SLC0_RX_START_INT_ST1 : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ST1 (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST1_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ST1_V 0x1 +#define SLC_SLC0_RX_START_INT_ST1_S 8 +/* SLC_FRHOST_BIT7_INT_ST1 : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ST1 (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST1_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT7_INT_ST1_S 7 +/* SLC_FRHOST_BIT6_INT_ST1 : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ST1 (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST1_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT6_INT_ST1_S 6 +/* SLC_FRHOST_BIT5_INT_ST1 : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ST1 (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST1_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT5_INT_ST1_S 5 +/* SLC_FRHOST_BIT4_INT_ST1 : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ST1 (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST1_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT4_INT_ST1_S 4 +/* SLC_FRHOST_BIT3_INT_ST1 : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ST1 (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST1_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT3_INT_ST1_S 3 +/* SLC_FRHOST_BIT2_INT_ST1 : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ST1 (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST1_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT2_INT_ST1_S 2 +/* SLC_FRHOST_BIT1_INT_ST1 : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ST1 (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST1_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT1_INT_ST1_S 1 +/* SLC_FRHOST_BIT0_INT_ST1 : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ST1 (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST1_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ST1_V 0x1 +#define SLC_FRHOST_BIT0_INT_ST1_S 0 + +#define SLC_0INT_ENA1_REG (DR_REG_SLC_BASE + 0x140) +/* SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1 (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_M (BIT(27)) +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_V 0x1 +#define SLC_SLC0_HOST_POP_EOF_ERR_INT_ENA1_S 27 +/* SLC_SLC0_RX_QUICK_EOF_INT_ENA1 : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1 (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_M (BIT(26)) +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_QUICK_EOF_INT_ENA1_S 26 +/* SLC_CMD_DTC_INT_ENA1 : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SLC_CMD_DTC_INT_ENA1 (BIT(25)) +#define SLC_CMD_DTC_INT_ENA1_M (BIT(25)) +#define SLC_CMD_DTC_INT_ENA1_V 0x1 +#define SLC_CMD_DTC_INT_ENA1_S 25 +/* SLC_SLC0_TX_ERR_EOF_INT_ENA1 : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1 (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_M (BIT(24)) +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_ERR_EOF_INT_ENA1_S 24 +/* SLC_SLC0_WR_RETRY_DONE_INT_ENA1 : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1 (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_M (BIT(23)) +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_V 0x1 +#define SLC_SLC0_WR_RETRY_DONE_INT_ENA1_S 23 +/* SLC_SLC0_HOST_RD_ACK_INT_ENA1 : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1 (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_M (BIT(22)) +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_V 0x1 +#define SLC_SLC0_HOST_RD_ACK_INT_ENA1_S 22 +/* SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1 (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_M (BIT(21)) +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_DSCR_EMPTY_INT_ENA1_S 21 +/* SLC_SLC0_RX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1 (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_M (BIT(20)) +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_DSCR_ERR_INT_ENA1_S 20 +/* SLC_SLC0_TX_DSCR_ERR_INT_ENA1 : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1 (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_M (BIT(19)) +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_DSCR_ERR_INT_ENA1_S 19 +/* SLC_SLC0_TOHOST_INT_ENA1 : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOHOST_INT_ENA1 (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA1_M (BIT(18)) +#define SLC_SLC0_TOHOST_INT_ENA1_V 0x1 +#define SLC_SLC0_TOHOST_INT_ENA1_S 18 +/* SLC_SLC0_RX_EOF_INT_ENA1 : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_EOF_INT_ENA1 (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA1_M (BIT(17)) +#define SLC_SLC0_RX_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_EOF_INT_ENA1_S 17 +/* SLC_SLC0_RX_DONE_INT_ENA1 : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_DONE_INT_ENA1 (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA1_M (BIT(16)) +#define SLC_SLC0_RX_DONE_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_DONE_INT_ENA1_S 16 +/* SLC_SLC0_TX_SUC_EOF_INT_ENA1 : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1 (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_M (BIT(15)) +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_SUC_EOF_INT_ENA1_S 15 +/* SLC_SLC0_TX_DONE_INT_ENA1 : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_DONE_INT_ENA1 (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA1_M (BIT(14)) +#define SLC_SLC0_TX_DONE_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_DONE_INT_ENA1_S 14 +/* SLC_SLC0_TOKEN1_1TO0_INT_ENA1 : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1 (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_M (BIT(13)) +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_V 0x1 +#define SLC_SLC0_TOKEN1_1TO0_INT_ENA1_S 13 +/* SLC_SLC0_TOKEN0_1TO0_INT_ENA1 : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1 (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_M (BIT(12)) +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_V 0x1 +#define SLC_SLC0_TOKEN0_1TO0_INT_ENA1_S 12 +/* SLC_SLC0_TX_OVF_INT_ENA1 : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_OVF_INT_ENA1 (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA1_M (BIT(11)) +#define SLC_SLC0_TX_OVF_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_OVF_INT_ENA1_S 11 +/* SLC_SLC0_RX_UDF_INT_ENA1 : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_UDF_INT_ENA1 (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA1_M (BIT(10)) +#define SLC_SLC0_RX_UDF_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_UDF_INT_ENA1_S 10 +/* SLC_SLC0_TX_START_INT_ENA1 : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_TX_START_INT_ENA1 (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA1_M (BIT(9)) +#define SLC_SLC0_TX_START_INT_ENA1_V 0x1 +#define SLC_SLC0_TX_START_INT_ENA1_S 9 +/* SLC_SLC0_RX_START_INT_ENA1 : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SLC_SLC0_RX_START_INT_ENA1 (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA1_M (BIT(8)) +#define SLC_SLC0_RX_START_INT_ENA1_V 0x1 +#define SLC_SLC0_RX_START_INT_ENA1_S 8 +/* SLC_FRHOST_BIT7_INT_ENA1 : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT7_INT_ENA1 (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA1_M (BIT(7)) +#define SLC_FRHOST_BIT7_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT7_INT_ENA1_S 7 +/* SLC_FRHOST_BIT6_INT_ENA1 : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT6_INT_ENA1 (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA1_M (BIT(6)) +#define SLC_FRHOST_BIT6_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT6_INT_ENA1_S 6 +/* SLC_FRHOST_BIT5_INT_ENA1 : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT5_INT_ENA1 (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA1_M (BIT(5)) +#define SLC_FRHOST_BIT5_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT5_INT_ENA1_S 5 +/* SLC_FRHOST_BIT4_INT_ENA1 : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT4_INT_ENA1 (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA1_M (BIT(4)) +#define SLC_FRHOST_BIT4_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT4_INT_ENA1_S 4 +/* SLC_FRHOST_BIT3_INT_ENA1 : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT3_INT_ENA1 (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA1_M (BIT(3)) +#define SLC_FRHOST_BIT3_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT3_INT_ENA1_S 3 +/* SLC_FRHOST_BIT2_INT_ENA1 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT2_INT_ENA1 (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA1_M (BIT(2)) +#define SLC_FRHOST_BIT2_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT2_INT_ENA1_S 2 +/* SLC_FRHOST_BIT1_INT_ENA1 : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT1_INT_ENA1 (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA1_M (BIT(1)) +#define SLC_FRHOST_BIT1_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT1_INT_ENA1_S 1 +/* SLC_FRHOST_BIT0_INT_ENA1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SLC_FRHOST_BIT0_INT_ENA1 (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA1_M (BIT(0)) +#define SLC_FRHOST_BIT0_INT_ENA1_V 0x1 +#define SLC_FRHOST_BIT0_INT_ENA1_S 0 + +#define SLC_DATE_REG (DR_REG_SLC_BASE + 0x1F8) +/* SLC_DATE : R/W ;bitpos:[31:0] ;default: 32'h18080700 ; */ +/*description: */ +#define SLC_DATE 0xFFFFFFFF +#define SLC_DATE_M ((SLC_DATE_V) << (SLC_DATE_S)) +#define SLC_DATE_V 0xFFFFFFFF +#define SLC_DATE_S 0 + +#define SLC_ID_REG (DR_REG_SLC_BASE + 0x1FC) +/* SLC_ID : R/W ;bitpos:[31:0] ;default: 32'h0100 ; */ +/*description: */ +#define SLC_ID 0xFFFFFFFF +#define SLC_ID_M ((SLC_ID_V) << (SLC_ID_S)) +#define SLC_ID_V 0xFFFFFFFF +#define SLC_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/slc_struct.h b/components/soc/soc/esp32s3/include/soc/slc_struct.h new file mode 100644 index 000000000..cc1526530 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/slc_struct.h @@ -0,0 +1,590 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t slc0_tx_rst: 1; + uint32_t slc0_rx_rst: 1; + uint32_t ahbm_fifo_rst: 1; + uint32_t ahbm_rst: 1; + uint32_t slc0_tx_loop_test: 1; + uint32_t slc0_rx_loop_test: 1; + uint32_t slc0_rx_auto_wrback: 1; + uint32_t slc0_rx_no_restart_clr: 1; + uint32_t slc0_rxdscr_burst_en: 1; + uint32_t slc0_rxdata_burst_en: 1; + uint32_t slc0_rxlink_auto_ret: 1; + uint32_t slc0_txlink_auto_ret: 1; + uint32_t slc0_txdscr_burst_en: 1; + uint32_t slc0_txdata_burst_en: 1; + uint32_t slc0_token_auto_clr: 1; + uint32_t slc0_token_sel: 1; + uint32_t reserved16: 2; + uint32_t slc0_wr_retry_mask_en: 1; + uint32_t reserved19: 13; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t host_pop_eof_err: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_int_raw; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t host_pop_eof_err: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_int_st; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t host_pop_eof_err: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_int_ena; + union { + struct { + uint32_t frhost_bit0: 1; + uint32_t frhost_bit1: 1; + uint32_t frhost_bit2: 1; + uint32_t frhost_bit3: 1; + uint32_t frhost_bit4: 1; + uint32_t frhost_bit5: 1; + uint32_t frhost_bit6: 1; + uint32_t frhost_bit7: 1; + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_udf: 1; + uint32_t tx_ovf: 1; + uint32_t token0_1to0: 1; + uint32_t token1_1to0: 1; + uint32_t tx_done: 1; + uint32_t tx_suc_eof: 1; + uint32_t rx_done: 1; + uint32_t rx_eof: 1; + uint32_t tohost: 1; + uint32_t tx_dscr_err: 1; + uint32_t rx_dscr_err: 1; + uint32_t tx_dscr_empty: 1; + uint32_t host_rd_ack: 1; + uint32_t wr_retry_done: 1; + uint32_t tx_err_eof: 1; + uint32_t cmd_dtc: 1; + uint32_t rx_quick_eof: 1; + uint32_t host_pop_eof_err: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_int_clr; + uint32_t reserved_14; + uint32_t reserved_18; + uint32_t reserved_1c; + uint32_t reserved_20; + union { + struct { + uint32_t slc0_rx_full: 1; + uint32_t slc0_rx_empty: 1; + uint32_t slc0_rx_buf_len: 12; + uint32_t reserved14: 18; + }; + uint32_t val; + } rx_status; + union { + struct { + uint32_t rxfifo_wdata: 9; + uint32_t reserved9: 7; + uint32_t rxfifo_push: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc0_rxfifo_push; + uint32_t reserved_2c; + union { + struct { + uint32_t slc0_tx_full: 1; + uint32_t slc0_tx_empty: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } tx_status; + union { + struct { + uint32_t txfifo_rdata: 11; + uint32_t reserved11: 5; + uint32_t txfifo_pop: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc0_txfifo_pop; + uint32_t reserved_38; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } slc0_rx_link; + union { + struct { + uint32_t addr: 20; + uint32_t reserved20: 8; + uint32_t stop: 1; + uint32_t start: 1; + uint32_t restart: 1; + uint32_t park: 1; + }; + uint32_t val; + } slc0_tx_link; + uint32_t reserved_44; + uint32_t reserved_48; + union { + struct { + uint32_t slc0_intvec: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } intvec_tohost; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token0: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_token0; + union { + struct { + uint32_t wdata: 12; + uint32_t wr: 1; + uint32_t inc: 1; + uint32_t inc_more: 1; + uint32_t reserved15: 1; + uint32_t token1: 12; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_token1; + uint32_t reserved_58; + uint32_t reserved_5c; + union { + struct { + uint32_t slc0_check_owner: 1; + uint32_t slc0_tx_check_sum_en: 1; + uint32_t slc0_rx_check_sum_en: 1; + uint32_t cmd_hold_en: 1; + uint32_t slc0_len_auto_clr: 1; + uint32_t slc0_tx_stitch_en: 1; + uint32_t slc0_rx_stitch_en: 1; + uint32_t reserved7: 12; + uint32_t host_int_level_sel: 1; + uint32_t reserved20: 2; + uint32_t clk_en: 1; + uint32_t reserved23: 9; + }; + uint32_t val; + } conf1; + uint32_t slc0_state0; /**/ + uint32_t slc0_state1; /**/ + uint32_t reserved_6c; + uint32_t reserved_70; + union { + struct { + uint32_t txeof_ena: 6; + uint32_t reserved6: 2; + uint32_t fifo_map_ena: 4; + uint32_t slc0_tx_dummy_mode: 1; + uint32_t hda_map_128k: 1; + uint32_t reserved14: 2; + uint32_t tx_push_idle_num: 16; + }; + uint32_t val; + } bridge_conf; + uint32_t slc0_to_eof_des_addr; /**/ + uint32_t slc0_tx_eof_des_addr; /**/ + uint32_t slc0_to_eof_bfr_des_addr; /**/ + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + union { + struct { + uint32_t mode: 3; + uint32_t reserved3: 1; + uint32_t addr: 2; + uint32_t reserved6: 26; + }; + uint32_t val; + } ahb_test; + union { + struct { + uint32_t cmd_st: 3; + uint32_t reserved3: 1; + uint32_t func_st: 4; + uint32_t sdio_wakeup: 1; + uint32_t reserved9: 3; + uint32_t bus_st: 3; + uint32_t reserved15: 1; + uint32_t func1_acc_state: 5; + uint32_t reserved21: 11; + }; + uint32_t val; + } sdio_st; + union { + struct { + uint32_t slc0_token_no_replace: 1; + uint32_t slc0_infor_no_replace: 1; + uint32_t slc0_rx_fill_mode: 1; + uint32_t slc0_rx_eof_mode: 1; + uint32_t slc0_rx_fill_en: 1; + uint32_t slc0_rd_retry_threshold: 11; + uint32_t reserved16: 16; + }; + uint32_t val; + } rx_dscr_conf; + uint32_t slc0_txlink_dscr; /**/ + uint32_t slc0_txlink_dscr_bf0; /**/ + uint32_t slc0_txlink_dscr_bf1; /**/ + uint32_t slc0_rxlink_dscr; /**/ + uint32_t slc0_rxlink_dscr_bf0; /**/ + uint32_t slc0_rxlink_dscr_bf1; /**/ + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t slc0_tx_erreof_des_addr; /**/ + uint32_t reserved_d0; + union { + struct { + uint32_t slc0_token: 12; + uint32_t reserved12: 20; + }; + uint32_t val; + } token_lat; + union { + struct { + uint32_t wr_retry_threshold: 11; + uint32_t reserved11: 21; + }; + uint32_t val; + } tx_dscr_conf; + uint32_t cmd_infor0; /**/ + uint32_t cmd_infor1; /**/ + union { + struct { + uint32_t len_wdata: 20; + uint32_t len_wr: 1; + uint32_t len_inc: 1; + uint32_t len_inc_more: 1; + uint32_t rx_packet_load_en: 1; + uint32_t tx_packet_load_en: 1; + uint32_t rx_get_used_dscr: 1; + uint32_t tx_get_used_dscr: 1; + uint32_t rx_new_pkt_ind: 1; + uint32_t tx_new_pkt_ind: 1; + uint32_t reserved29: 3; + }; + uint32_t val; + } slc0_len_conf; + union { + struct { + uint32_t len: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } slc0_length; + uint32_t slc0_txpkt_h_dscr; /**/ + uint32_t slc0_txpkt_e_dscr; /**/ + uint32_t slc0_rxpkt_h_dscr; /**/ + uint32_t slc0_rxpkt_e_dscr; /**/ + uint32_t slc0_txpktu_h_dscr; /**/ + uint32_t slc0_txpktu_e_dscr; /**/ + uint32_t slc0_rxpktu_h_dscr; /**/ + uint32_t slc0_rxpktu_e_dscr; /**/ + uint32_t reserved_10c; + uint32_t reserved_110; + union { + struct { + uint32_t slc0_position: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } seq_position; + union { + struct { + uint32_t rx_dscr_rec_lim: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } slc0_dscr_rec_conf; + union { + struct { + uint32_t dat0_crc_err_cnt: 8; + uint32_t dat1_crc_err_cnt: 8; + uint32_t dat2_crc_err_cnt: 8; + uint32_t dat3_crc_err_cnt: 8; + }; + uint32_t val; + } sdio_crc_st0; + union { + struct { + uint32_t cmd_crc_err_cnt: 8; + uint32_t reserved8: 23; + uint32_t err_cnt_clr: 1; + }; + uint32_t val; + } sdio_crc_st1; + uint32_t slc0_eof_start_des; /**/ + uint32_t slc0_push_dscr_addr; /**/ + uint32_t slc0_done_dscr_addr; /**/ + uint32_t slc0_sub_start_des; /**/ + union { + struct { + uint32_t rx_dscr_cnt_lat: 10; + uint32_t reserved10: 6; + uint32_t rx_get_eof_occ: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } slc0_dscr_cnt; + union { + struct { + uint32_t len_lim: 20; + uint32_t reserved20: 12; + }; + uint32_t val; + } slc0_len_lim_conf; + union { + struct { + uint32_t frhost_bit01: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit21: 1; + uint32_t frhost_bit31: 1; + uint32_t frhost_bit41: 1; + uint32_t frhost_bit51: 1; + uint32_t frhost_bit61: 1; + uint32_t frhost_bit71: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t tx_done1: 1; + uint32_t tx_suc_eof1: 1; + uint32_t rx_done1: 1; + uint32_t rx_eof1: 1; + uint32_t tohost1: 1; + uint32_t tx_dscr_err1: 1; + uint32_t rx_dscr_err1: 1; + uint32_t tx_dscr_empty1: 1; + uint32_t host_rd_ack1: 1; + uint32_t wr_retry_done1: 1; + uint32_t tx_err_eof1: 1; + uint32_t cmd_dtc1: 1; + uint32_t rx_quick_eof1: 1; + uint32_t host_pop_eof_err1: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_int_st1; + union { + struct { + uint32_t frhost_bit01: 1; + uint32_t frhost_bit11: 1; + uint32_t frhost_bit21: 1; + uint32_t frhost_bit31: 1; + uint32_t frhost_bit41: 1; + uint32_t frhost_bit51: 1; + uint32_t frhost_bit61: 1; + uint32_t frhost_bit71: 1; + uint32_t rx_start1: 1; + uint32_t tx_start1: 1; + uint32_t rx_udf1: 1; + uint32_t tx_ovf1: 1; + uint32_t token0_1to01: 1; + uint32_t token1_1to01: 1; + uint32_t tx_done1: 1; + uint32_t tx_suc_eof1: 1; + uint32_t rx_done1: 1; + uint32_t rx_eof1: 1; + uint32_t tohost1: 1; + uint32_t tx_dscr_err1: 1; + uint32_t rx_dscr_err1: 1; + uint32_t tx_dscr_empty1: 1; + uint32_t host_rd_ack1: 1; + uint32_t wr_retry_done1: 1; + uint32_t tx_err_eof1: 1; + uint32_t cmd_dtc1: 1; + uint32_t rx_quick_eof1: 1; + uint32_t host_pop_eof_err1: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } slc0_int_ena1; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t date; /**/ + uint32_t id; /**/ +} slc_dev_t; + +extern slc_dev_t SLC; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/soc.h b/components/soc/soc/esp32s3/include/soc/soc.h new file mode 100644 index 000000000..427bccf90 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/soc.h @@ -0,0 +1,331 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifndef __ASSEMBLER__ +#include +#include "esp_assert.h" +#include "esp_bit_defs.h" +#endif + +#define PRO_CPU_NUM (0) +#define APP_CPU_NUM (1) + +#define PRO_CPUID (0xcdcd) +#define APP_CPUID (0xabab) + +#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space + +#define DR_REG_SYSTEM_BASE 0x600c0000 +#define DR_REG_SENSITIVE_BASE 0x600c1000 +#define DR_REG_INTERRUPT_BASE 0x600c2000 +#define DR_REG_DMA_COPY_BASE 0x600c3000 +#define DR_REG_EXTMEM_BASE 0x600c4000 +#define DR_REG_MMU_TABLE 0x600c5000 +#define DR_REG_ITAG_TABLE 0x600c6000 +#define DR_REG_DTAG_TABLE 0x600c8000 +#define DR_REG_AES_BASE 0x6003a000 +#define DR_REG_SHA_BASE 0x6003b000 +#define DR_REG_RSA_BASE 0x6003c000 +#define DR_REG_HMAC_BASE 0x6003e000 +#define DR_REG_DIGITAL_SIGNATURE_BASE 0x6003d000 +#define DR_REG_CRYPTO_DMA_BASE 0x6003f000 +#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000 +#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000 +#define DR_REG_WORLD_CNTL_BASE 0x600d0000 +#define DR_REG_DPORT_END 0x600d3FFC +#define DR_REG_UART_BASE 0x60000000 +#define DR_REG_SPI1_BASE 0x60002000 +#define DR_REG_SPI0_BASE 0x60003000 +#define DR_REG_GPIO_BASE 0x60004000 +#define DR_REG_GPIO_SD_BASE 0x60004f00 +#define DR_REG_FE2_BASE 0x60005000 +#define DR_REG_FE_BASE 0x60006000 +#define DR_REG_FRC_TIMER_BASE 0x60007000 +#define DR_REG_RTCCNTL_BASE 0x60008000 +#define DR_REG_RTCIO_BASE 0x60008400 +#define DR_REG_SENS_BASE 0x60008800 +#define DR_REG_RTC_I2C_BASE 0x60008C00 +#define DR_REG_IO_MUX_BASE 0x60009000 +#define DR_REG_HINF_BASE 0x6000B000 +#define DR_REG_UHCI1_BASE 0x6000C000 +#define DR_REG_I2S_BASE 0x6000F000 +#define DR_REG_UART1_BASE 0x60010000 +#define DR_REG_BT_BASE 0x60011000 +#define DR_REG_I2C_EXT_BASE 0x60013000 +#define DR_REG_UHCI0_BASE 0x60014000 +#define DR_REG_SLCHOST_BASE 0x60015000 +#define DR_REG_RMT_BASE 0x60016000 +#define DR_REG_PCNT_BASE 0x60017000 +#define DR_REG_SLC_BASE 0x60018000 +#define DR_REG_LEDC_BASE 0x60019000 +#define DR_REG_EFUSE_BASE 0x6001A000 +#define DR_REG_NRX_BASE 0x6001CC00 +#define DR_REG_BB_BASE 0x6001D000 +#define DR_REG_PWM_BASE 0x6001E000 +#define DR_REG_TIMERGROUP0_BASE 0x6001F000 +#define DR_REG_TIMERGROUP1_BASE 0x60020000 +#define DR_REG_RTC_SLOWMEM_BASE 0x60021000 +#define DR_REG_SYS_TIMER_BASE 0x60023000 +#define DR_REG_SPI2_BASE 0x60024000 +#define DR_REG_SPI3_BASE 0x60025000 +#define DR_REG_SYSCON_BASE 0x60026000 +#define DR_REG_APB_CTRL_BASE 0x60026000 /* Old name for SYSCON, to be removed */ +#define DR_REG_I2C1_EXT_BASE 0x60027000 +#define DR_REG_SDMMC_BASE 0x60028000 +#define DR_REG_TWAI_BASE 0x6002B000 +#define DR_REG_PWM1_BASE 0x6002C000 +#define DR_REG_I2S1_BASE 0x6002D000 +#define DR_REG_UART2_BASE 0x6002E000 +#define DR_REG_PWM2_BASE 0x6002F000 +#define DR_REG_PWM3_BASE 0x60030000 +#define DR_REG_SPI4_BASE 0x60037000 +#define DR_REG_USB_WRAP_BASE 0x60039000 +#define DR_REG_APB_SARADC_BASE 0x60040000 +#define DR_REG_LCD_CAM_BASE 0x60041000 + +#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) +#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) +#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) +#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) +#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) +#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) +#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) + +//Registers Operation {{ +#define ETS_UNCACHED_ADDR(addr) (addr) +#define ETS_CACHED_ADDR(addr) (addr) + +#ifndef __ASSEMBLER__ + +//write value to register +#define REG_WRITE(_r, _v) ({ \ + (*(volatile uint32_t *)(_r)) = (_v); \ + }) + +//read value from register +#define REG_READ(_r) ({ \ + (*(volatile uint32_t *)(_r)); \ + }) + +//get bit or get bits from register +#define REG_GET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) & (_b)); \ + }) + +//set bit or set bits to register +#define REG_SET_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) |= (_b)); \ + }) + +//clear bit or clear bits of register +#define REG_CLR_BIT(_r, _b) ({ \ + (*(volatile uint32_t*)(_r) &= ~(_b)); \ + }) + +//set bits of register controlled by mask +#define REG_SET_BITS(_r, _b, _m) ({ \ + (*(volatile uint32_t*)(_r) = (*(volatile uint32_t*)(_r) & ~(_m)) | ((_b) & (_m))); \ + }) + +//get field from register, uses field _S & _V to determine mask +#define REG_GET_FIELD(_r, _f) ({ \ + ((REG_READ(_r) >> (_f##_S)) & (_f##_V)); \ + }) + +//set field of a register from variable, uses field _S & _V to determine mask +#define REG_SET_FIELD(_r, _f, _v) ({ \ + (REG_WRITE((_r),((REG_READ(_r) & ~((_f##_V) << (_f##_S)))|(((_v) & (_f##_V))<<(_f##_S))))); \ + }) + +//get field value from a variable, used when _f is not left shifted by _f##_S +#define VALUE_GET_FIELD(_r, _f) (((_r) >> (_f##_S)) & (_f)) + +//get field value from a variable, used when _f is left shifted by _f##_S +#define VALUE_GET_FIELD2(_r, _f) (((_r) & (_f))>> (_f##_S)) + +//set field value to a variable, used when _f is not left shifted by _f##_S +#define VALUE_SET_FIELD(_r, _f, _v) ((_r)=(((_r) & ~((_f) << (_f##_S)))|((_v)<<(_f##_S)))) + +//set field value to a variable, used when _f is left shifted by _f##_S +#define VALUE_SET_FIELD2(_r, _f, _v) ((_r)=(((_r) & ~(_f))|((_v)<<(_f##_S)))) + +//generate a value from a field value, used when _f is not left shifted by _f##_S +#define FIELD_TO_VALUE(_f, _v) (((_v)&(_f))<<_f##_S) + +//generate a value from a field value, used when _f is left shifted by _f##_S +#define FIELD_TO_VALUE2(_f, _v) (((_v)<<_f##_S) & (_f)) + +//read value from register +#define READ_PERI_REG(addr) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))); \ + }) + +//write value to register +#define WRITE_PERI_REG(addr, val) ({ \ + (*((volatile uint32_t *)ETS_UNCACHED_ADDR(addr))) = (uint32_t)(val); \ + }) + +//clear bits of register controlled by mask +#define CLEAR_PERI_REG_MASK(reg, mask) ({ \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)&(~(mask)))); \ + }) + +//set bits of register controlled by mask +#define SET_PERI_REG_MASK(reg, mask) ({ \ + WRITE_PERI_REG((reg), (READ_PERI_REG(reg)|(mask))); \ + }) + +//get bits of register controlled by mask +#define GET_PERI_REG_MASK(reg, mask) ({ \ + (READ_PERI_REG(reg) & (mask)); \ + }) + +//get bits of register controlled by highest bit and lowest bit +#define GET_PERI_REG_BITS(reg, hipos,lowpos) ({ \ + ((READ_PERI_REG(reg)>>(lowpos))&((1<<((hipos)-(lowpos)+1))-1)); \ + }) + +//set bits of register controlled by mask and shift +#define SET_PERI_REG_BITS(reg,bit_map,value,shift) ({ \ + (WRITE_PERI_REG((reg),(READ_PERI_REG(reg)&(~((bit_map)<<(shift))))|(((value) & bit_map)<<(shift)) )); \ + }) + +//get field of register +#define GET_PERI_REG_BITS2(reg, mask,shift) ({ \ + ((READ_PERI_REG(reg)>>(shift))&(mask)); \ + }) + +#endif /* !__ASSEMBLER__ */ +//}} + +//Periheral Clock {{ +#define APB_CLK_FREQ_ROM (40*1000000) +#define CPU_CLK_FREQ_ROM (40*1000000) +#define UART_CLK_FREQ_ROM (40*1000000) +#define EFUSE_CLK_FREQ_ROM (20*1000000) +#define CPU_CLK_FREQ APB_CLK_FREQ +#define APB_CLK_FREQ (80*1000000) +#define REF_CLK_FREQ (1000000) +#define UART_CLK_FREQ APB_CLK_FREQ +#define WDT_CLK_FREQ APB_CLK_FREQ +#define TIMER_CLK_FREQ (80000000>>4) +#define SPI_CLK_DIV 4 +#define TICKS_PER_US_ROM 40 +#define GPIO_MATRIX_DELAY_NS 0 +//}} + +/* Overall memory map */ +#define SOC_DROM_LOW 0x3C000000 +#define SOC_DROM_HIGH 0x3D000000 +#define SOC_IROM_LOW 0x42000000 +#define SOC_IROM_HIGH 0x42800000 +#define SOC_IRAM_LOW 0x40370000 +#define SOC_IRAM_HIGH 0x403E0000 +#define SOC_DRAM_LOW 0x3FC88000 +#define SOC_DRAM_HIGH 0x3FD00000 +#define SOC_RTC_IRAM_LOW 0x600FE000 +#define SOC_RTC_IRAM_HIGH 0x60100000 +#define SOC_RTC_DRAM_LOW 0x600FE000 +#define SOC_RTC_DRAM_HIGH 0x60100000 +#define SOC_RTC_DATA_LOW 0x50000000 +#define SOC_RTC_DATA_HIGH 0x50002000 +#define SOC_EXTRAM_DATA_LOW 0x3D000000 +#define SOC_EXTRAM_DATA_HIGH 0x3E000000 + +//First and last words of the D/IRAM region, for both the DRAM address as well as the IRAM alias. +#define SOC_DIRAM_IRAM_LOW 0x40378000 +#define SOC_DIRAM_IRAM_HIGH 0x403E0000 +#define SOC_DIRAM_DRAM_LOW 0x3FC88000 +#define SOC_DIRAM_DRAM_HIGH 0x3FCF0000 + +// Region of memory accessible via DMA. See esp_ptr_dma_capable(). +#define SOC_DMA_LOW 0x3FC88000 +#define SOC_DMA_HIGH 0x3FD00000 + +// Region of memory that is byte-accessible. See esp_ptr_byte_accessible(). +#define SOC_BYTE_ACCESSIBLE_LOW 0x3FC88000 +#define SOC_BYTE_ACCESSIBLE_HIGH 0x3FD00000 + +//Region of memory that is internal, as in on the same silicon die as the ESP32 CPUs +//(excluding RTC data region, that's checked separately.) See esp_ptr_internal(). +#define SOC_MEM_INTERNAL_LOW 0x3FC88000 +#define SOC_MEM_INTERNAL_HIGH 0x403E2000 + +// Start (highest address) of ROM boot stack, only relevant during early boot +#define SOC_ROM_STACK_START 0x3fcebf10 + +//interrupt cpu using table, Please see the core-isa.h +/************************************************************************************************************* + * Intr num Level Type PRO CPU usage APP CPU uasge + * 0 1 extern level WMAC Reserved + * 1 1 extern level BT/BLE Host HCI DMA BT/BLE Host HCI DMA + * 2 1 extern level + * 3 1 extern level + * 4 1 extern level WBB + * 5 1 extern level BT/BLE Controller BT/BLE Controller + * 6 1 timer FreeRTOS Tick(L1) FreeRTOS Tick(L1) + * 7 1 software BT/BLE VHCI BT/BLE VHCI + * 8 1 extern level BT/BLE BB(RX/TX) BT/BLE BB(RX/TX) + * 9 1 extern level + * 10 1 extern edge + * 11 3 profiling + * 12 1 extern level + * 13 1 extern level + * 14 7 nmi Reserved Reserved + * 15 3 timer FreeRTOS Tick(L3) FreeRTOS Tick(L3) + * 16 5 timer + * 17 1 extern level + * 18 1 extern level + * 19 2 extern level + * 20 2 extern level + * 21 2 extern level + * 22 3 extern edge + * 23 3 extern level + * 24 4 extern level TG1_WDT + * 25 4 extern level CACHEERR + * 26 5 extern level + * 27 3 extern level Reserved Reserved + * 28 4 extern edge DPORT ACCESS DPORT ACCESS + * 29 3 software Reserved Reserved + * 30 4 extern edge Reserved Reserved + * 31 5 extern level + ************************************************************************************************************* + */ + +//CPU0 Interrupt number reserved, not touch this. +#define ETS_WMAC_INUM 0 +#define ETS_BT_HOST_INUM 1 +#define ETS_WBB_INUM 4 +#define ETS_TG0_T1_INUM 10 /**< use edge interrupt*/ +#define ETS_FRC1_INUM 22 +#define ETS_T1_WDT_INUM 24 +#define ETS_CACHEERR_INUM 25 +#define ETS_DPORT_INUM 28 + +//CPU0 Interrupt number used in ROM, should be cancelled in SDK +#define ETS_SLC_INUM 1 +#define ETS_UART0_INUM 5 +#define ETS_UART1_INUM 5 +#define ETS_SPI2_INUM 1 +//CPU0 Interrupt number used in ROM code only when module init function called, should pay attention here. +#define ETS_FRC_TIMER2_INUM 10 /* use edge*/ +#define ETS_GPIO_INUM 4 + +//Other interrupt number should be managed by the user + +//Invalid interrupt for number interrupt matrix +#define ETS_INVALID_INUM 6 diff --git a/components/soc/soc/esp32s3/include/soc/soc_caps.h b/components/soc/soc/esp32s3/include/soc/soc_caps.h new file mode 100644 index 000000000..127b7e1e4 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/soc_caps.h @@ -0,0 +1,8 @@ +// The long term plan is to have a single soc_caps.h for each peripheral. +// During the refactoring and multichip support development process, we +// seperate these information into periph_caps.h for each peripheral and +// include them here. + +#pragma once + +#define SOC_CPU_CORES_NUM 2 \ No newline at end of file diff --git a/components/soc/soc/esp32s3/include/soc/soc_ulp.h b/components/soc/soc/esp32s3/include/soc/soc_ulp.h new file mode 100644 index 000000000..b9359c94a --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/soc_ulp.h @@ -0,0 +1,45 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +// This file contains various convenience macros to be used in ULP programs. + +// Helper macros to calculate bit field width from mask, using the preprocessor. +// Used later in READ_RTC_FIELD and WRITE_RTC_FIELD. +#define IS_BIT_SET(m, i) (((m) >> (i)) & 1) +#define MASK_TO_WIDTH_HELPER1(m, i) IS_BIT_SET(m, i) +#define MASK_TO_WIDTH_HELPER2(m, i) (MASK_TO_WIDTH_HELPER1(m, i) + MASK_TO_WIDTH_HELPER1(m, i + 1)) +#define MASK_TO_WIDTH_HELPER4(m, i) (MASK_TO_WIDTH_HELPER2(m, i) + MASK_TO_WIDTH_HELPER2(m, i + 2)) +#define MASK_TO_WIDTH_HELPER8(m, i) (MASK_TO_WIDTH_HELPER4(m, i) + MASK_TO_WIDTH_HELPER4(m, i + 4)) +#define MASK_TO_WIDTH_HELPER16(m, i) (MASK_TO_WIDTH_HELPER8(m, i) + MASK_TO_WIDTH_HELPER8(m, i + 8)) +#define MASK_TO_WIDTH_HELPER32(m, i) (MASK_TO_WIDTH_HELPER16(m, i) + MASK_TO_WIDTH_HELPER16(m, i + 16)) + +// Peripheral register access macros, build around REG_RD and REG_WR instructions. +// Registers defined in rtc_cntl_reg.h, rtc_io_reg.h, sens_reg.h, and rtc_i2c_reg.h are usable with these macros. + +// Read from rtc_reg[low_bit + bit_width - 1 : low_bit] into R0, bit_width <= 16 +#define READ_RTC_REG(rtc_reg, low_bit, bit_width) \ + REG_RD (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit) + +// Write immediate value into rtc_reg[low_bit + bit_width - 1 : low_bit], bit_width <= 8 +#define WRITE_RTC_REG(rtc_reg, low_bit, bit_width, value) \ + REG_WR (((rtc_reg) - DR_REG_RTCCNTL_BASE) / 4), ((low_bit) + (bit_width) - 1), (low_bit), ((value) & 0xff) + +// Read from a field in rtc_reg into R0, up to 16 bits +#define READ_RTC_FIELD(rtc_reg, field) \ + READ_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER16(field ## _V, 0)) + +// Write immediate value into a field in rtc_reg, up to 8 bits +#define WRITE_RTC_FIELD(rtc_reg, field, value) \ + WRITE_RTC_REG(rtc_reg, field ## _S, MASK_TO_WIDTH_HELPER8(field ## _V, 0), ((value) & field ## _V)) diff --git a/components/soc/soc/esp32s3/include/soc/spi_caps.h b/components/soc/soc/esp32s3/include/soc/spi_caps.h new file mode 100644 index 000000000..30efbbbcb --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/spi_caps.h @@ -0,0 +1,53 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_SPI_PERIPH_NUM 4 +#define SOC_SPI_DMA_CHAN_NUM 3 +#define SOC_SPI_PERIPH_CS_NUM(i) 3 + +#define SPI_FUNC_NUM 0 +#define SPI_IOMUX_PIN_NUM_HD 27 +#define SPI_IOMUX_PIN_NUM_CS 29 +#define SPI_IOMUX_PIN_NUM_MOSI 32 +#define SPI_IOMUX_PIN_NUM_CLK 30 +#define SPI_IOMUX_PIN_NUM_MISO 31 +#define SPI_IOMUX_PIN_NUM_WP 28 +//TODO: add the next slot + +#define FSPI_FUNC_NUM 4 +#define FSPI_IOMUX_PIN_NUM_HD 9 +#define FSPI_IOMUX_PIN_NUM_CS 10 +#define FSPI_IOMUX_PIN_NUM_MOSI 11 +#define FSPI_IOMUX_PIN_NUM_CLK 12 +#define FSPI_IOMUX_PIN_NUM_MISO 13 +#define FSPI_IOMUX_PIN_NUM_WP 14 +//TODO: add the next slot + +//HSPI and VSPI have no iomux pins + +#define SOC_SPI_MAXIMUM_BUFFER_SIZE 72 + +//#define SOC_SPI_SUPPORT_AS_CS //don't support to toggle the CS while the clock toggles +#define SOC_SPI_SUPPORT_DDRCLK 1 +#define SOC_SPI_SLAVE_SUPPORT_SEG_TRANS 1 +#define SOC_SPI_SUPPORT_CD_SIG 1 +#define SOC_SPI_SUPPORT_CONTINUOUS_TRANS 1 + +// Peripheral supports DIO, DOUT, QIO, or QOUT +#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(spi_dev) (!((void*)spi_dev == (void*)&GPSPI3)) + +// Peripheral supports output given level during its "dummy phase" +#define SOC_SPI_PERIPH_SUPPORT_CONTROL_DUMMY_OUTPUT(spi_dev) ((void*)spi_dev == (void*)&SPIMEM1) diff --git a/components/soc/soc/esp32s3/include/soc/spi_mem_reg.h b/components/soc/soc/esp32s3/include/soc/spi_mem_reg.h new file mode 100644 index 000000000..4f820c7fb --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/spi_mem_reg.h @@ -0,0 +1,1407 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SPI_MEM_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x004) +/* SPI_MEM_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: In user mode it is the memory address. other then the bit0-bit23 + is the memory address the bit24-bit31 are the byte length of a transfer.*/ +#define SPI_MEM_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_M ((SPI_MEM_USR_ADDR_VALUE_V) << (SPI_MEM_USR_ADDR_VALUE_S)) +#define SPI_MEM_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_MEM_USR_ADDR_VALUE_S 0 + +#define SPI_MEM_CTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x008) +/* SPI_MEM_FREAD_QIO : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 4 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_QIO (BIT(24)) +#define SPI_MEM_FREAD_QIO_M (BIT(24)) +#define SPI_MEM_FREAD_QIO_V 0x1 +#define SPI_MEM_FREAD_QIO_S 24 +/* SPI_MEM_FREAD_DIO : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: In the read operations address phase and read-data phase apply + 2 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_DIO (BIT(23)) +#define SPI_MEM_FREAD_DIO_M (BIT(23)) +#define SPI_MEM_FREAD_DIO_V 0x1 +#define SPI_MEM_FREAD_DIO_S 23 +/* SPI_MEM_WP_REG : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high 0: output low.*/ +#define SPI_MEM_WP_REG (BIT(21)) +#define SPI_MEM_WP_REG_M (BIT(21)) +#define SPI_MEM_WP_REG_V 0x1 +#define SPI_MEM_WP_REG_S 21 +/* SPI_MEM_FREAD_QUAD : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_QUAD (BIT(20)) +#define SPI_MEM_FREAD_QUAD_M (BIT(20)) +#define SPI_MEM_FREAD_QUAD_V 0x1 +#define SPI_MEM_FREAD_QUAD_S 20 +/* SPI_MEM_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity 1: high 0 low*/ +#define SPI_MEM_D_POL (BIT(19)) +#define SPI_MEM_D_POL_M (BIT(19)) +#define SPI_MEM_D_POL_V 0x1 +#define SPI_MEM_D_POL_S 19 +/* SPI_MEM_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity 1: high 0 low*/ +#define SPI_MEM_Q_POL (BIT(18)) +#define SPI_MEM_Q_POL_M (BIT(18)) +#define SPI_MEM_Q_POL_V 0x1 +#define SPI_MEM_Q_POL_S 18 +/* SPI_MEM_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ +#define SPI_MEM_FREAD_DUAL (BIT(14)) +#define SPI_MEM_FREAD_DUAL_M (BIT(14)) +#define SPI_MEM_FREAD_DUAL_V 0x1 +#define SPI_MEM_FREAD_DUAL_S 14 +/* SPI_MEM_FASTRD_MODE : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio + spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ +#define SPI_MEM_FASTRD_MODE (BIT(13)) +#define SPI_MEM_FASTRD_MODE_M (BIT(13)) +#define SPI_MEM_FASTRD_MODE_V 0x1 +#define SPI_MEM_FASTRD_MODE_S 13 +/* SPI_MEM_TX_CRC_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI1 enable crc32 when writing encrypted data to flash. + 1: enable 0:disable*/ +#define SPI_MEM_TX_CRC_EN (BIT(11)) +#define SPI_MEM_TX_CRC_EN_M (BIT(11)) +#define SPI_MEM_TX_CRC_EN_V 0x1 +#define SPI_MEM_TX_CRC_EN_S 11 +/* SPI_MEM_FCS_CRC_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI1 initialize crc32 module before writing encrypted data + to flash. Active low.*/ +#define SPI_MEM_FCS_CRC_EN (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_M (BIT(10)) +#define SPI_MEM_FCS_CRC_EN_V 0x1 +#define SPI_MEM_FCS_CRC_EN_S 10 +/* SPI_MEM_FCMD_OCT : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable*/ +#define SPI_MEM_FCMD_OCT (BIT(9)) +#define SPI_MEM_FCMD_OCT_M (BIT(9)) +#define SPI_MEM_FCMD_OCT_V 0x1 +#define SPI_MEM_FCMD_OCT_S 9 +/* SPI_MEM_FCMD_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable*/ +#define SPI_MEM_FCMD_QUAD (BIT(8)) +#define SPI_MEM_FCMD_QUAD_M (BIT(8)) +#define SPI_MEM_FCMD_QUAD_V 0x1 +#define SPI_MEM_FCMD_QUAD_S 8 +/* SPI_MEM_FCMD_DUAL : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Apply 2 signals during command phase 1:enable 0: disable*/ +#define SPI_MEM_FCMD_DUAL (BIT(7)) +#define SPI_MEM_FCMD_DUAL_M (BIT(7)) +#define SPI_MEM_FCMD_DUAL_V 0x1 +#define SPI_MEM_FCMD_DUAL_S 7 +/* SPI_MEM_FADDR_OCT : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 8 signals during address phase 1:enable 0: disable*/ +#define SPI_MEM_FADDR_OCT (BIT(6)) +#define SPI_MEM_FADDR_OCT_M (BIT(6)) +#define SPI_MEM_FADDR_OCT_V 0x1 +#define SPI_MEM_FADDR_OCT_S 6 +/* SPI_MEM_FDIN_OCT : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 8 signals during read-data phase 1:enable 0: disable*/ +#define SPI_MEM_FDIN_OCT (BIT(5)) +#define SPI_MEM_FDIN_OCT_M (BIT(5)) +#define SPI_MEM_FDIN_OCT_V 0x1 +#define SPI_MEM_FDIN_OCT_S 5 +/* SPI_MEM_FDOUT_OCT : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Apply 8 signals during write-data phase 1:enable 0: disable*/ +#define SPI_MEM_FDOUT_OCT (BIT(4)) +#define SPI_MEM_FDOUT_OCT_M (BIT(4)) +#define SPI_MEM_FDOUT_OCT_V 0x1 +#define SPI_MEM_FDOUT_OCT_S 4 +/* SPI_MEM_FDUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the dummy phase the signal level of spi is output by the spi controller.*/ +#define SPI_MEM_FDUMMY_OUT (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_M (BIT(3)) +#define SPI_MEM_FDUMMY_OUT_V 0x1 +#define SPI_MEM_FDUMMY_OUT_S 3 + +#define SPI_MEM_CTRL1_REG(i) (REG_SPI_MEM_BASE(i) + 0x00C) +/* SPI_MEM_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ +#define SPI_MEM_CLK_MODE 0x00000003 +#define SPI_MEM_CLK_MODE_M ((SPI_MEM_CLK_MODE_V) << (SPI_MEM_CLK_MODE_S)) +#define SPI_MEM_CLK_MODE_V 0x3 +#define SPI_MEM_CLK_MODE_S 0 + +#define SPI_MEM_CTRL2_REG(i) (REG_SPI_MEM_BASE(i) + 0x010) +/* SPI_MEM_SYNC_RESET : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: The FSM will be reset.*/ +#define SPI_MEM_SYNC_RESET (BIT(31)) +#define SPI_MEM_SYNC_RESET_M (BIT(31)) +#define SPI_MEM_SYNC_RESET_V 0x1 +#define SPI_MEM_SYNC_RESET_S 31 +/* SPI_MEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between + SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ +#define SPI_MEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_CS_HOLD_DELAY_M ((SPI_MEM_CS_HOLD_DELAY_V) << (SPI_MEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes + mode when accesses flash.*/ +#define SPI_MEM_ECC_16TO18_BYTE_EN (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_M (BIT(14)) +#define SPI_MEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_ECC_16TO18_BYTE_EN_S 14 +/* SPI_MEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: 1: MSPI skips page corner when accesses flash. 0: Not skip page + corner when accesses flash.*/ +#define SPI_MEM_ECC_SKIP_PAGE_CORNER (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_M (BIT(13)) +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_ECC_SKIP_PAGE_CORNER_S 13 +/* SPI_MEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[12:10] ;default: 3'd3 ; */ +/*description: SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS + hold cycle in ECC mode when accessed flash.*/ +#define SPI_MEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_ECC_CS_HOLD_TIME_V) << (SPI_MEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_ECC_CS_HOLD_TIME_S 10 +/* SPI_MEM_CS_HOLD_TIME : R/W ;bitpos:[9:5] ;default: 5'h1 ; */ +/*description: Spi cs signal is delayed to inactive by spi clock this bits are + combined with spi_mem_cs_hold bit.*/ +#define SPI_MEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_CS_HOLD_TIME_M ((SPI_MEM_CS_HOLD_TIME_V) << (SPI_MEM_CS_HOLD_TIME_S)) +#define SPI_MEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_CS_HOLD_TIME_S 5 +/* SPI_MEM_CS_SETUP_TIME : R/W ;bitpos:[4:0] ;default: 5'h1 ; */ +/*description: (cycles-1) of prepare phase by spi clock this bits are combined + with spi_mem_cs_setup bit.*/ +#define SPI_MEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_CS_SETUP_TIME_M ((SPI_MEM_CS_SETUP_TIME_V) << (SPI_MEM_CS_SETUP_TIME_S)) +#define SPI_MEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_CS_SETUP_TIME_S 0 + +#define SPI_MEM_CLOCK_REG(i) (REG_SPI_MEM_BASE(i) + 0x014) +/* SPI_MEM_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit in 1-division mode.*/ +#define SPI_MEM_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_CLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_CLK_EQU_SYSCLK_S 31 +/* SPI_MEM_CLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: In the master mode it is the divider of spi_mem_clk. So spi_mem_clk + frequency is system/(spi_mem_clkcnt_N+1)*/ +#define SPI_MEM_CLKCNT_N 0x000000FF +#define SPI_MEM_CLKCNT_N_M ((SPI_MEM_CLKCNT_N_V) << (SPI_MEM_CLKCNT_N_S)) +#define SPI_MEM_CLKCNT_N_V 0xFF +#define SPI_MEM_CLKCNT_N_S 16 +/* SPI_MEM_CLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ +#define SPI_MEM_CLKCNT_H 0x000000FF +#define SPI_MEM_CLKCNT_H_M ((SPI_MEM_CLKCNT_H_V) << (SPI_MEM_CLKCNT_H_S)) +#define SPI_MEM_CLKCNT_H_V 0xFF +#define SPI_MEM_CLKCNT_H_S 8 +/* SPI_MEM_CLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: In the master mode it must be equal to spi_mem_clkcnt_N.*/ +#define SPI_MEM_CLKCNT_L 0x000000FF +#define SPI_MEM_CLKCNT_L_M ((SPI_MEM_CLKCNT_L_V) << (SPI_MEM_CLKCNT_L_S)) +#define SPI_MEM_CLKCNT_L_V 0xFF +#define SPI_MEM_CLKCNT_L_S 0 + +#define SPI_MEM_USER_REG(i) (REG_SPI_MEM_BASE(i) + 0x018) +/* SPI_MEM_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation.*/ +#define SPI_MEM_USR_DUMMY (BIT(29)) +#define SPI_MEM_USR_DUMMY_M (BIT(29)) +#define SPI_MEM_USR_DUMMY_V 0x1 +#define SPI_MEM_USR_DUMMY_S 29 +/* SPI_MEM_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable.*/ +#define SPI_MEM_USR_DUMMY_IDLE (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_MEM_USR_DUMMY_IDLE_V 0x1 +#define SPI_MEM_USR_DUMMY_IDLE_S 26 +/* SPI_MEM_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mem_mosi_delay_mode bits to set mosi + signal delay mode.*/ +#define SPI_MEM_CK_OUT_EDGE (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_M (BIT(9)) +#define SPI_MEM_CK_OUT_EDGE_V 0x1 +#define SPI_MEM_CK_OUT_EDGE_S 9 +/* SPI_MEM_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ +#define SPI_MEM_CS_SETUP (BIT(7)) +#define SPI_MEM_CS_SETUP_M (BIT(7)) +#define SPI_MEM_CS_SETUP_V 0x1 +#define SPI_MEM_CS_SETUP_S 7 +/* SPI_MEM_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ +#define SPI_MEM_CS_HOLD (BIT(6)) +#define SPI_MEM_CS_HOLD_M (BIT(6)) +#define SPI_MEM_CS_HOLD_V 0x1 +#define SPI_MEM_CS_HOLD_S 6 + +#define SPI_MEM_USER1_REG(i) (REG_SPI_MEM_BASE(i) + 0x01C) +/* SPI_MEM_USR_ADDR_BITLEN : R/W ;bitpos:[31:26] ;default: 6'd23 ; */ +/*description: The length in bits of address phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_USR_ADDR_BITLEN 0x0000003F +#define SPI_MEM_USR_ADDR_BITLEN_M ((SPI_MEM_USR_ADDR_BITLEN_V) << (SPI_MEM_USR_ADDR_BITLEN_S)) +#define SPI_MEM_USR_ADDR_BITLEN_V 0x3F +#define SPI_MEM_USR_ADDR_BITLEN_S 26 +/* SPI_MEM_USR_DUMMY_CYCLELEN : R/W ;bitpos:[5:0] ;default: 6'd7 ; */ +/*description: The length in spi_mem_clk cycles of dummy phase. The register + value shall be (cycle_num-1).*/ +#define SPI_MEM_USR_DUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_USR_DUMMY_CYCLELEN_M ((SPI_MEM_USR_DUMMY_CYCLELEN_V) << (SPI_MEM_USR_DUMMY_CYCLELEN_S)) +#define SPI_MEM_USR_DUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_MEM_USER2_REG(i) (REG_SPI_MEM_BASE(i) + 0x020) +/* SPI_MEM_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall be (bit_num-1)*/ +#define SPI_MEM_USR_COMMAND_BITLEN 0x0000000F +#define SPI_MEM_USR_COMMAND_BITLEN_M ((SPI_MEM_USR_COMMAND_BITLEN_V) << (SPI_MEM_USR_COMMAND_BITLEN_S)) +#define SPI_MEM_USR_COMMAND_BITLEN_V 0xF +#define SPI_MEM_USR_COMMAND_BITLEN_S 28 +/* SPI_MEM_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command.*/ +#define SPI_MEM_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_MEM_USR_COMMAND_VALUE_M ((SPI_MEM_USR_COMMAND_VALUE_V) << (SPI_MEM_USR_COMMAND_VALUE_S)) +#define SPI_MEM_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_MEM_USR_COMMAND_VALUE_S 0 + +#define SPI_MEM_RD_STATUS_REG(i) (REG_SPI_MEM_BASE(i) + 0x02C) +/* SPI_MEM_WB_MODE : R/W ;bitpos:[23:16] ;default: 8'h00 ; */ +/*description: Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode + bit.*/ +#define SPI_MEM_WB_MODE 0x000000FF +#define SPI_MEM_WB_MODE_M ((SPI_MEM_WB_MODE_V) << (SPI_MEM_WB_MODE_S)) +#define SPI_MEM_WB_MODE_V 0xFF +#define SPI_MEM_WB_MODE_S 16 + +#define SPI_MEM_EXT_ADDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x030) +/* SPI_MEM_EXT_ADDR : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: The register are the higher 32bits in the 64 bits address mode.*/ +#define SPI_MEM_EXT_ADDR 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_M ((SPI_MEM_EXT_ADDR_V) << (SPI_MEM_EXT_ADDR_S)) +#define SPI_MEM_EXT_ADDR_V 0xFFFFFFFF +#define SPI_MEM_EXT_ADDR_S 0 + +#define SPI_MEM_MISC_REG(i) (REG_SPI_MEM_BASE(i) + 0x034) +/* SPI_MEM_CS_KEEP_ACTIVE : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set.*/ +#define SPI_MEM_CS_KEEP_ACTIVE (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_M (BIT(10)) +#define SPI_MEM_CS_KEEP_ACTIVE_V 0x1 +#define SPI_MEM_CS_KEEP_ACTIVE_S 10 +/* SPI_MEM_CK_IDLE_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low when idle*/ +#define SPI_MEM_CK_IDLE_EDGE (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_M (BIT(9)) +#define SPI_MEM_CK_IDLE_EDGE_V 0x1 +#define SPI_MEM_CK_IDLE_EDGE_S 9 +/* SPI_MEM_SSUB_PIN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0 sram is connected to SUBPINs.*/ +#define SPI_MEM_SSUB_PIN (BIT(8)) +#define SPI_MEM_SSUB_PIN_M (BIT(8)) +#define SPI_MEM_SSUB_PIN_V 0x1 +#define SPI_MEM_SSUB_PIN_S 8 +/* SPI_MEM_FSUB_PIN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0 flash is connected to SUBPINs.*/ +#define SPI_MEM_FSUB_PIN (BIT(7)) +#define SPI_MEM_FSUB_PIN_M (BIT(7)) +#define SPI_MEM_FSUB_PIN_V 0x1 +#define SPI_MEM_FSUB_PIN_S 7 +/* SPI_MEM_TRANS_END_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The bit is used to enable the intterrupt of SPI transmitting done.*/ +#define SPI_MEM_TRANS_END_INT_ENA (BIT(4)) +#define SPI_MEM_TRANS_END_INT_ENA_M (BIT(4)) +#define SPI_MEM_TRANS_END_INT_ENA_V 0x1 +#define SPI_MEM_TRANS_END_INT_ENA_S 4 +/* SPI_MEM_TRANS_END : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The bit is used to indicate the transimitting is done.*/ +#define SPI_MEM_TRANS_END (BIT(3)) +#define SPI_MEM_TRANS_END_M (BIT(3)) +#define SPI_MEM_TRANS_END_V 0x1 +#define SPI_MEM_TRANS_END_S 3 + +#define SPI_MEM_TX_CRC_REG(i) (REG_SPI_MEM_BASE(i) + 0x038) +/* SPI_MEM_TX_CRC_DATA : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: For SPI1 the value of crc32.*/ +#define SPI_MEM_TX_CRC_DATA 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_M ((SPI_MEM_TX_CRC_DATA_V) << (SPI_MEM_TX_CRC_DATA_S)) +#define SPI_MEM_TX_CRC_DATA_V 0xFFFFFFFF +#define SPI_MEM_TX_CRC_DATA_S 0 + +#define SPI_MEM_CACHE_FCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x03C) +/* SPI_MEM_FADDR_QUAD : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio.*/ +#define SPI_MEM_FADDR_QUAD (BIT(8)) +#define SPI_MEM_FADDR_QUAD_M (BIT(8)) +#define SPI_MEM_FADDR_QUAD_V 0x1 +#define SPI_MEM_FADDR_QUAD_S 8 +/* SPI_MEM_FDOUT_QUAD : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio.*/ +#define SPI_MEM_FDOUT_QUAD (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_M (BIT(7)) +#define SPI_MEM_FDOUT_QUAD_V 0x1 +#define SPI_MEM_FDOUT_QUAD_S 7 +/* SPI_MEM_FDIN_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_qio.*/ +#define SPI_MEM_FDIN_QUAD (BIT(6)) +#define SPI_MEM_FDIN_QUAD_M (BIT(6)) +#define SPI_MEM_FDIN_QUAD_V 0x1 +#define SPI_MEM_FDIN_QUAD_S 6 +/* SPI_MEM_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio.*/ +#define SPI_MEM_FADDR_DUAL (BIT(5)) +#define SPI_MEM_FADDR_DUAL_M (BIT(5)) +#define SPI_MEM_FADDR_DUAL_V 0x1 +#define SPI_MEM_FADDR_DUAL_S 5 +/* SPI_MEM_FDOUT_DUAL : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio.*/ +#define SPI_MEM_FDOUT_DUAL (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_M (BIT(4)) +#define SPI_MEM_FDOUT_DUAL_V 0x1 +#define SPI_MEM_FDOUT_DUAL_S 4 +/* SPI_MEM_FDIN_DUAL : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_fread_dio.*/ +#define SPI_MEM_FDIN_DUAL (BIT(3)) +#define SPI_MEM_FDIN_DUAL_M (BIT(3)) +#define SPI_MEM_FDIN_DUAL_V 0x1 +#define SPI_MEM_FDIN_DUAL_S 3 +/* SPI_MEM_CACHE_FLASH_USR_CMD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash for user define command 1: enable 0:disable.*/ +#define SPI_MEM_CACHE_FLASH_USR_CMD (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_M (BIT(2)) +#define SPI_MEM_CACHE_FLASH_USR_CMD_V 0x1 +#define SPI_MEM_CACHE_FLASH_USR_CMD_S 2 +/* SPI_MEM_CACHE_USR_CMD_4BYTE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ +#define SPI_MEM_CACHE_USR_CMD_4BYTE (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_M (BIT(1)) +#define SPI_MEM_CACHE_USR_CMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_CMD_4BYTE_S 1 +/* SPI_MEM_CACHE_REQ_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 Cache access enable 1: enable 0:disable.*/ +#define SPI_MEM_CACHE_REQ_EN (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_M (BIT(0)) +#define SPI_MEM_CACHE_REQ_EN_V 0x1 +#define SPI_MEM_CACHE_REQ_EN_S 0 + +#define SPI_MEM_CACHE_SCTRL_REG(i) (REG_SPI_MEM_BASE(i) + 0x040) +/* SPI_MEM_SRAM_WDUMMY_CYCLELEN : R/W ;bitpos:[27:22] ;default: 6'b1 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of write + dummy phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_WDUMMY_CYCLELEN_V) << (SPI_MEM_SRAM_WDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_WDUMMY_CYCLELEN_S 22 +/* SPI_MEM_SRAM_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: reserved*/ +#define SPI_MEM_SRAM_OCT (BIT(21)) +#define SPI_MEM_SRAM_OCT_M (BIT(21)) +#define SPI_MEM_SRAM_OCT_V 0x1 +#define SPI_MEM_SRAM_OCT_S 21 +/* SPI_MEM_CACHE_SRAM_USR_WCMD : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache write sram for user define command*/ +#define SPI_MEM_CACHE_SRAM_USR_WCMD (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_M (BIT(20)) +#define SPI_MEM_CACHE_SRAM_USR_WCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_WCMD_S 20 +/* SPI_MEM_SRAM_ADDR_BITLEN : R/W ;bitpos:[19:14] ;default: 6'd23 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of address + phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_SRAM_ADDR_BITLEN 0x0000003F +#define SPI_MEM_SRAM_ADDR_BITLEN_M ((SPI_MEM_SRAM_ADDR_BITLEN_V) << (SPI_MEM_SRAM_ADDR_BITLEN_S)) +#define SPI_MEM_SRAM_ADDR_BITLEN_V 0x3F +#define SPI_MEM_SRAM_ADDR_BITLEN_S 14 +/* SPI_MEM_SRAM_RDUMMY_CYCLELEN : R/W ;bitpos:[11:6] ;default: 6'b1 ; */ +/*description: For SPI0 In the sram mode it is the length in bits of read + dummy phase. The register value shall be (bit_num-1).*/ +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN 0x0000003F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_M ((SPI_MEM_SRAM_RDUMMY_CYCLELEN_V) << (SPI_MEM_SRAM_RDUMMY_CYCLELEN_S)) +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_V 0x3F +#define SPI_MEM_SRAM_RDUMMY_CYCLELEN_S 6 +/* SPI_MEM_CACHE_SRAM_USR_RCMD : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode cache read sram for user define command.*/ +#define SPI_MEM_CACHE_SRAM_USR_RCMD (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_M (BIT(5)) +#define SPI_MEM_CACHE_SRAM_USR_RCMD_V 0x1 +#define SPI_MEM_CACHE_SRAM_USR_RCMD_S 5 +/* SPI_MEM_USR_RD_SRAM_DUMMY : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for read operations.*/ +#define SPI_MEM_USR_RD_SRAM_DUMMY (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_M (BIT(4)) +#define SPI_MEM_USR_RD_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_RD_SRAM_DUMMY_S 4 +/* SPI_MEM_USR_WR_SRAM_DUMMY : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode it is the enable bit of dummy + phase for write operations.*/ +#define SPI_MEM_USR_WR_SRAM_DUMMY (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_M (BIT(3)) +#define SPI_MEM_USR_WR_SRAM_DUMMY_V 0x1 +#define SPI_MEM_USR_WR_SRAM_DUMMY_S 3 +/* SPI_MEM_USR_SRAM_QIO : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ +#define SPI_MEM_USR_SRAM_QIO (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_M (BIT(2)) +#define SPI_MEM_USR_SRAM_QIO_V 0x1 +#define SPI_MEM_USR_SRAM_QIO_S 2 +/* SPI_MEM_USR_SRAM_DIO : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ +#define SPI_MEM_USR_SRAM_DIO (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_M (BIT(1)) +#define SPI_MEM_USR_SRAM_DIO_V 0x1 +#define SPI_MEM_USR_SRAM_DIO_S 1 +/* SPI_MEM_CACHE_USR_SCMD_4BYTE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For SPI0 In the spi sram mode cache read flash with 4 bytes + command 1: enable 0:disable.*/ +#define SPI_MEM_CACHE_USR_SCMD_4BYTE (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_M (BIT(0)) +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_V 0x1 +#define SPI_MEM_CACHE_USR_SCMD_4BYTE_S 0 + +#define SPI_MEM_SRAM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x044) +/* SPI_MEM_SDUMMY_OUT : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: In the dummy phase the signal level of spi is output by the spi controller.*/ +#define SPI_MEM_SDUMMY_OUT (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_M (BIT(22)) +#define SPI_MEM_SDUMMY_OUT_V 0x1 +#define SPI_MEM_SDUMMY_OUT_S 22 +/* SPI_MEM_SCMD_OCT : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SCMD_OCT (BIT(21)) +#define SPI_MEM_SCMD_OCT_M (BIT(21)) +#define SPI_MEM_SCMD_OCT_V 0x1 +#define SPI_MEM_SCMD_OCT_S 21 +/* SPI_MEM_SADDR_OCT : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SADDR_OCT (BIT(20)) +#define SPI_MEM_SADDR_OCT_M (BIT(20)) +#define SPI_MEM_SADDR_OCT_V 0x1 +#define SPI_MEM_SADDR_OCT_S 20 +/* SPI_MEM_SDOUT_OCT : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SDOUT_OCT (BIT(19)) +#define SPI_MEM_SDOUT_OCT_M (BIT(19)) +#define SPI_MEM_SDOUT_OCT_V 0x1 +#define SPI_MEM_SDOUT_OCT_S 19 +/* SPI_MEM_SDIN_OCT : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/ +#define SPI_MEM_SDIN_OCT (BIT(18)) +#define SPI_MEM_SDIN_OCT_M (BIT(18)) +#define SPI_MEM_SDIN_OCT_V 0x1 +#define SPI_MEM_SDIN_OCT_S 18 +/* SPI_MEM_SCMD_QUAD : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_qio.*/ +#define SPI_MEM_SCMD_QUAD (BIT(17)) +#define SPI_MEM_SCMD_QUAD_M (BIT(17)) +#define SPI_MEM_SCMD_QUAD_V 0x1 +#define SPI_MEM_SCMD_QUAD_S 17 +/* SPI_MEM_SADDR_QUAD : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_qio.*/ +#define SPI_MEM_SADDR_QUAD (BIT(16)) +#define SPI_MEM_SADDR_QUAD_M (BIT(16)) +#define SPI_MEM_SADDR_QUAD_V 0x1 +#define SPI_MEM_SADDR_QUAD_S 16 +/* SPI_MEM_SDOUT_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_qio.*/ +#define SPI_MEM_SDOUT_QUAD (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_M (BIT(15)) +#define SPI_MEM_SDOUT_QUAD_V 0x1 +#define SPI_MEM_SDOUT_QUAD_S 15 +/* SPI_MEM_SDIN_QUAD : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_qio.*/ +#define SPI_MEM_SDIN_QUAD (BIT(14)) +#define SPI_MEM_SDIN_QUAD_M (BIT(14)) +#define SPI_MEM_SDIN_QUAD_V 0x1 +#define SPI_MEM_SDIN_QUAD_S 14 +/* SPI_MEM_SCMD_DUAL : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_dio.*/ +#define SPI_MEM_SCMD_DUAL (BIT(13)) +#define SPI_MEM_SCMD_DUAL_M (BIT(13)) +#define SPI_MEM_SCMD_DUAL_V 0x1 +#define SPI_MEM_SCMD_DUAL_S 13 +/* SPI_MEM_SADDR_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_dio.*/ +#define SPI_MEM_SADDR_DUAL (BIT(12)) +#define SPI_MEM_SADDR_DUAL_M (BIT(12)) +#define SPI_MEM_SADDR_DUAL_V 0x1 +#define SPI_MEM_SADDR_DUAL_S 12 +/* SPI_MEM_SDOUT_DUAL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_dio.*/ +#define SPI_MEM_SDOUT_DUAL (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_M (BIT(11)) +#define SPI_MEM_SDOUT_DUAL_V 0x1 +#define SPI_MEM_SDOUT_DUAL_S 11 +/* SPI_MEM_SDIN_DUAL : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. + The bit is the same with spi_mem_usr_sram_dio.*/ +#define SPI_MEM_SDIN_DUAL (BIT(10)) +#define SPI_MEM_SDIN_DUAL_M (BIT(10)) +#define SPI_MEM_SDIN_DUAL_V 0x1 +#define SPI_MEM_SDIN_DUAL_S 10 +/* SPI_MEM_SWB_MODE : R/W ;bitpos:[9:2] ;default: 8'b0 ; */ +/*description: Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode + bit.*/ +#define SPI_MEM_SWB_MODE 0x000000FF +#define SPI_MEM_SWB_MODE_M ((SPI_MEM_SWB_MODE_V) << (SPI_MEM_SWB_MODE_S)) +#define SPI_MEM_SWB_MODE_V 0xFF +#define SPI_MEM_SWB_MODE_S 2 +/* SPI_MEM_SCLK_MODE : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ +#define SPI_MEM_SCLK_MODE 0x00000003 +#define SPI_MEM_SCLK_MODE_M ((SPI_MEM_SCLK_MODE_V) << (SPI_MEM_SCLK_MODE_S)) +#define SPI_MEM_SCLK_MODE_V 0x3 +#define SPI_MEM_SCLK_MODE_S 0 + +#define SPI_MEM_SRAM_DRD_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x048) +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the length in bits of + command phase for sram. The register value shall be (bit_num-1).*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V) << (SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the read command value + of command phase for sram.*/ +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V) << (SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_RD_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_DWR_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x04C) +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN : R/W ;bitpos:[31:28] ;default: 4'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the in bits of command + phase for sram. The register value shall be (bit_num-1).*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN 0x0000000F +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V) << (SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_V 0xF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_BITLEN_S 28 +/* SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE : R/W ;bitpos:[15:0] ;default: 16'h0 ; */ +/*description: For SPI0 When cache mode is enable it is the write command value + of command phase for sram.*/ +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE 0x0000FFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_M ((SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V) << (SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S)) +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_V 0xFFFF +#define SPI_MEM_CACHE_SRAM_USR_WR_CMD_VALUE_S 0 + +#define SPI_MEM_SRAM_CLK_REG(i) (REG_SPI_MEM_BASE(i) + 0x050) +/* SPI_MEM_SCLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: + spi_mem_clk is divided from system clock.*/ +#define SPI_MEM_SCLK_EQU_SYSCLK (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_MEM_SCLK_EQU_SYSCLK_V 0x1 +#define SPI_MEM_SCLK_EQU_SYSCLK_S 31 +/* SPI_MEM_SCLKCNT_N : R/W ;bitpos:[23:16] ;default: 8'h3 ; */ +/*description: For SPI0 sram interface it is the divider of spi_mem_clk. So + spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ +#define SPI_MEM_SCLKCNT_N 0x000000FF +#define SPI_MEM_SCLKCNT_N_M ((SPI_MEM_SCLKCNT_N_V) << (SPI_MEM_SCLKCNT_N_S)) +#define SPI_MEM_SCLKCNT_N_V 0xFF +#define SPI_MEM_SCLKCNT_N_S 16 +/* SPI_MEM_SCLKCNT_H : R/W ;bitpos:[15:8] ;default: 8'h1 ; */ +/*description: For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ +#define SPI_MEM_SCLKCNT_H 0x000000FF +#define SPI_MEM_SCLKCNT_H_M ((SPI_MEM_SCLKCNT_H_V) << (SPI_MEM_SCLKCNT_H_S)) +#define SPI_MEM_SCLKCNT_H_V 0xFF +#define SPI_MEM_SCLKCNT_H_S 8 +/* SPI_MEM_SCLKCNT_L : R/W ;bitpos:[7:0] ;default: 8'h3 ; */ +/*description: For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/ +#define SPI_MEM_SCLKCNT_L 0x000000FF +#define SPI_MEM_SCLKCNT_L_M ((SPI_MEM_SCLKCNT_L_V) << (SPI_MEM_SCLKCNT_L_S)) +#define SPI_MEM_SCLKCNT_L_V 0xFF +#define SPI_MEM_SCLKCNT_L_S 0 + +#define SPI_MEM_FSM_REG(i) (REG_SPI_MEM_BASE(i) + 0x054) +/* SPI_MEM_ST : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: The status of spi state machine. 0: idle state 1: preparation + state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ +#define SPI_MEM_ST 0x00000007 +#define SPI_MEM_ST_M ((SPI_MEM_ST_V) << (SPI_MEM_ST_S)) +#define SPI_MEM_ST_V 0x7 +#define SPI_MEM_ST_S 0 + +#define SPI_MEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0A8) +/* SPI_MEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: add extra dummy spi clock cycle length for spi clock calibration.*/ +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_EXTRA_DUMMY_CYCLELEN_V) << (SPI_MEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The bit is used to enable timing auto-calibration for all reading operations.*/ +#define SPI_MEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_TIMING_CALI_V 0x1 +#define SPI_MEM_TIMING_CALI_S 1 +/* SPI_MEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: The bit is used to enable timing adjust clock for all reading operations.*/ +#define SPI_MEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0AC) +/* SPI_MEM_DINS_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DINS_MODE 0x00000003 +#define SPI_MEM_DINS_MODE_M ((SPI_MEM_DINS_MODE_V) << (SPI_MEM_DINS_MODE_S)) +#define SPI_MEM_DINS_MODE_V 0x3 +#define SPI_MEM_DINS_MODE_S 16 +/* SPI_MEM_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN7_MODE 0x00000003 +#define SPI_MEM_DIN7_MODE_M ((SPI_MEM_DIN7_MODE_V) << (SPI_MEM_DIN7_MODE_S)) +#define SPI_MEM_DIN7_MODE_V 0x3 +#define SPI_MEM_DIN7_MODE_S 14 +/* SPI_MEM_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN6_MODE 0x00000003 +#define SPI_MEM_DIN6_MODE_M ((SPI_MEM_DIN6_MODE_V) << (SPI_MEM_DIN6_MODE_S)) +#define SPI_MEM_DIN6_MODE_V 0x3 +#define SPI_MEM_DIN6_MODE_S 12 +/* SPI_MEM_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN5_MODE 0x00000003 +#define SPI_MEM_DIN5_MODE_M ((SPI_MEM_DIN5_MODE_V) << (SPI_MEM_DIN5_MODE_S)) +#define SPI_MEM_DIN5_MODE_V 0x3 +#define SPI_MEM_DIN5_MODE_S 10 +/* SPI_MEM_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ +#define SPI_MEM_DIN4_MODE 0x00000003 +#define SPI_MEM_DIN4_MODE_M ((SPI_MEM_DIN4_MODE_V) << (SPI_MEM_DIN4_MODE_S)) +#define SPI_MEM_DIN4_MODE_V 0x3 +#define SPI_MEM_DIN4_MODE_S 8 +/* SPI_MEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN3_MODE 0x00000003 +#define SPI_MEM_DIN3_MODE_M ((SPI_MEM_DIN3_MODE_V) << (SPI_MEM_DIN3_MODE_S)) +#define SPI_MEM_DIN3_MODE_V 0x3 +#define SPI_MEM_DIN3_MODE_S 6 +/* SPI_MEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN2_MODE 0x00000003 +#define SPI_MEM_DIN2_MODE_M ((SPI_MEM_DIN2_MODE_V) << (SPI_MEM_DIN2_MODE_S)) +#define SPI_MEM_DIN2_MODE_V 0x3 +#define SPI_MEM_DIN2_MODE_S 4 +/* SPI_MEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN1_MODE 0x00000003 +#define SPI_MEM_DIN1_MODE_M ((SPI_MEM_DIN1_MODE_V) << (SPI_MEM_DIN1_MODE_S)) +#define SPI_MEM_DIN1_MODE_V 0x3 +#define SPI_MEM_DIN1_MODE_S 2 +/* SPI_MEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_DIN0_MODE 0x00000003 +#define SPI_MEM_DIN0_MODE_M ((SPI_MEM_DIN0_MODE_V) << (SPI_MEM_DIN0_MODE_S)) +#define SPI_MEM_DIN0_MODE_V 0x3 +#define SPI_MEM_DIN0_MODE_S 0 + +#define SPI_MEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B0) +/* SPI_MEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DINS_NUM 0x00000003 +#define SPI_MEM_DINS_NUM_M ((SPI_MEM_DINS_NUM_V) << (SPI_MEM_DINS_NUM_S)) +#define SPI_MEM_DINS_NUM_V 0x3 +#define SPI_MEM_DINS_NUM_S 16 +/* SPI_MEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN7_NUM 0x00000003 +#define SPI_MEM_DIN7_NUM_M ((SPI_MEM_DIN7_NUM_V) << (SPI_MEM_DIN7_NUM_S)) +#define SPI_MEM_DIN7_NUM_V 0x3 +#define SPI_MEM_DIN7_NUM_S 14 +/* SPI_MEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN6_NUM 0x00000003 +#define SPI_MEM_DIN6_NUM_M ((SPI_MEM_DIN6_NUM_V) << (SPI_MEM_DIN6_NUM_S)) +#define SPI_MEM_DIN6_NUM_V 0x3 +#define SPI_MEM_DIN6_NUM_S 12 +/* SPI_MEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN5_NUM 0x00000003 +#define SPI_MEM_DIN5_NUM_M ((SPI_MEM_DIN5_NUM_V) << (SPI_MEM_DIN5_NUM_S)) +#define SPI_MEM_DIN5_NUM_V 0x3 +#define SPI_MEM_DIN5_NUM_S 10 +/* SPI_MEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN4_NUM 0x00000003 +#define SPI_MEM_DIN4_NUM_M ((SPI_MEM_DIN4_NUM_V) << (SPI_MEM_DIN4_NUM_S)) +#define SPI_MEM_DIN4_NUM_V 0x3 +#define SPI_MEM_DIN4_NUM_S 8 +/* SPI_MEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN3_NUM 0x00000003 +#define SPI_MEM_DIN3_NUM_M ((SPI_MEM_DIN3_NUM_V) << (SPI_MEM_DIN3_NUM_S)) +#define SPI_MEM_DIN3_NUM_V 0x3 +#define SPI_MEM_DIN3_NUM_S 6 +/* SPI_MEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN2_NUM 0x00000003 +#define SPI_MEM_DIN2_NUM_M ((SPI_MEM_DIN2_NUM_V) << (SPI_MEM_DIN2_NUM_S)) +#define SPI_MEM_DIN2_NUM_V 0x3 +#define SPI_MEM_DIN2_NUM_S 4 +/* SPI_MEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN1_NUM 0x00000003 +#define SPI_MEM_DIN1_NUM_M ((SPI_MEM_DIN1_NUM_V) << (SPI_MEM_DIN1_NUM_S)) +#define SPI_MEM_DIN1_NUM_V 0x3 +#define SPI_MEM_DIN1_NUM_S 2 +/* SPI_MEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_DIN0_NUM 0x00000003 +#define SPI_MEM_DIN0_NUM_M ((SPI_MEM_DIN0_NUM_V) << (SPI_MEM_DIN0_NUM_S)) +#define SPI_MEM_DIN0_NUM_V 0x3 +#define SPI_MEM_DIN0_NUM_S 0 + +#define SPI_MEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0B4) +/* SPI_MEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_DOUTS_MODE_S 8 +/* SPI_MEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_DOUT7_MODE_S 7 +/* SPI_MEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_DOUT6_MODE_S 6 +/* SPI_MEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_DOUT5_MODE_S 5 +/* SPI_MEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ +#define SPI_MEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_DOUT4_MODE_S 4 +/* SPI_MEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_DOUT3_MODE_S 3 +/* SPI_MEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_DOUT2_MODE_S 2 +/* SPI_MEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_DOUT1_MODE_S 1 +/* SPI_MEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_TIMING_CALI_REG(i) (REG_SPI_MEM_BASE(i) + 0x0BC) +/* SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN : R/W ;bitpos:[4:2] ;default: 3'd0 ; */ +/*description: For sram add extra dummy spi clock cycle length for spi clock calibration.*/ +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN 0x00000007 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_M ((SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V) << (SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S)) +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_V 0x7 +#define SPI_MEM_SPI_SMEM_EXTRA_DUMMY_CYCLELEN_S 2 +/* SPI_MEM_SPI_SMEM_TIMING_CALI : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For sram the bit is used to enable timing auto-calibration for + all reading operations.*/ +#define SPI_MEM_SPI_SMEM_TIMING_CALI (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_TIMING_CALI_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CALI_S 1 +/* SPI_MEM_SPI_SMEM_TIMING_CLK_ENA : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: For sram the bit is used to enable timing adjust clock for all + reading operations.*/ +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_V 0x1 +#define SPI_MEM_SPI_SMEM_TIMING_CLK_ENA_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C0) +/* SPI_MEM_SPI_SMEM_DINS_MODE : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DINS_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_MODE_M ((SPI_MEM_SPI_SMEM_DINS_MODE_V) << (SPI_MEM_SPI_SMEM_DINS_MODE_S)) +#define SPI_MEM_SPI_SMEM_DINS_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_MODE_S 16 +/* SPI_MEM_SPI_SMEM_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN7_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_M ((SPI_MEM_SPI_SMEM_DIN7_MODE_V) << (SPI_MEM_SPI_SMEM_DIN7_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN7_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN7_MODE_S 14 +/* SPI_MEM_SPI_SMEM_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN6_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_M ((SPI_MEM_SPI_SMEM_DIN6_MODE_V) << (SPI_MEM_SPI_SMEM_DIN6_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN6_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN6_MODE_S 12 +/* SPI_MEM_SPI_SMEM_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN5_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_M ((SPI_MEM_SPI_SMEM_DIN5_MODE_V) << (SPI_MEM_SPI_SMEM_DIN5_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN5_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN5_MODE_S 10 +/* SPI_MEM_SPI_SMEM_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN4_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_M ((SPI_MEM_SPI_SMEM_DIN4_MODE_V) << (SPI_MEM_SPI_SMEM_DIN4_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN4_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN4_MODE_S 8 +/* SPI_MEM_SPI_SMEM_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN3_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_M ((SPI_MEM_SPI_SMEM_DIN3_MODE_V) << (SPI_MEM_SPI_SMEM_DIN3_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN3_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN3_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN2_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_M ((SPI_MEM_SPI_SMEM_DIN2_MODE_V) << (SPI_MEM_SPI_SMEM_DIN2_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN2_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN2_MODE_S 4 +/* SPI_MEM_SPI_SMEM_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN1_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_M ((SPI_MEM_SPI_SMEM_DIN1_MODE_V) << (SPI_MEM_SPI_SMEM_DIN1_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN1_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN1_MODE_S 2 +/* SPI_MEM_SPI_SMEM_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DIN0_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_M ((SPI_MEM_SPI_SMEM_DIN0_MODE_V) << (SPI_MEM_SPI_SMEM_DIN0_MODE_S)) +#define SPI_MEM_SPI_SMEM_DIN0_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_DIN_NUM_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C4) +/* SPI_MEM_SPI_SMEM_DINS_NUM : R/W ;bitpos:[17:16] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: input + without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DINS_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DINS_NUM_M ((SPI_MEM_SPI_SMEM_DINS_NUM_V) << (SPI_MEM_SPI_SMEM_DINS_NUM_S)) +#define SPI_MEM_SPI_SMEM_DINS_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DINS_NUM_S 16 +/* SPI_MEM_SPI_SMEM_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN7_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_M ((SPI_MEM_SPI_SMEM_DIN7_NUM_V) << (SPI_MEM_SPI_SMEM_DIN7_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN7_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN7_NUM_S 14 +/* SPI_MEM_SPI_SMEM_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN6_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_M ((SPI_MEM_SPI_SMEM_DIN6_NUM_V) << (SPI_MEM_SPI_SMEM_DIN6_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN6_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN6_NUM_S 12 +/* SPI_MEM_SPI_SMEM_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN5_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_M ((SPI_MEM_SPI_SMEM_DIN5_NUM_V) << (SPI_MEM_SPI_SMEM_DIN5_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN5_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN5_NUM_S 10 +/* SPI_MEM_SPI_SMEM_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN4_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_M ((SPI_MEM_SPI_SMEM_DIN4_NUM_V) << (SPI_MEM_SPI_SMEM_DIN4_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN4_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN4_NUM_S 8 +/* SPI_MEM_SPI_SMEM_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN3_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_M ((SPI_MEM_SPI_SMEM_DIN3_NUM_V) << (SPI_MEM_SPI_SMEM_DIN3_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN3_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN3_NUM_S 6 +/* SPI_MEM_SPI_SMEM_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN2_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_M ((SPI_MEM_SPI_SMEM_DIN2_NUM_V) << (SPI_MEM_SPI_SMEM_DIN2_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN2_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN2_NUM_S 4 +/* SPI_MEM_SPI_SMEM_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN1_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_M ((SPI_MEM_SPI_SMEM_DIN1_NUM_V) << (SPI_MEM_SPI_SMEM_DIN1_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN1_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN1_NUM_S 2 +/* SPI_MEM_SPI_SMEM_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'h0 ; */ +/*description: the input signals are delayed by system clock cycles 0: delayed + by 1 cycle 1: delayed by 2 cycles ...*/ +#define SPI_MEM_SPI_SMEM_DIN0_NUM 0x00000003 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_M ((SPI_MEM_SPI_SMEM_DIN0_NUM_V) << (SPI_MEM_SPI_SMEM_DIN0_NUM_S)) +#define SPI_MEM_SPI_SMEM_DIN0_NUM_V 0x3 +#define SPI_MEM_SPI_SMEM_DIN0_NUM_S 0 + +#define SPI_MEM_SPI_SMEM_DOUT_MODE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0C8) +/* SPI_MEM_SPI_SMEM_DOUTS_MODE : R/W ;bitpos:[8] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUTS_MODE (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_M (BIT(8)) +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUTS_MODE_S 8 +/* SPI_MEM_SPI_SMEM_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT7_MODE (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_M (BIT(7)) +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT7_MODE_S 7 +/* SPI_MEM_SPI_SMEM_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT6_MODE (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_M (BIT(6)) +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT6_MODE_S 6 +/* SPI_MEM_SPI_SMEM_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT5_MODE (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_M (BIT(5)) +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT5_MODE_S 5 +/* SPI_MEM_SPI_SMEM_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT4_MODE (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT4_MODE_S 4 +/* SPI_MEM_SPI_SMEM_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT3_MODE (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT3_MODE_S 3 +/* SPI_MEM_SPI_SMEM_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT2_MODE (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT2_MODE_S 2 +/* SPI_MEM_SPI_SMEM_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT1_MODE (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT1_MODE_S 1 +/* SPI_MEM_SPI_SMEM_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: the output signals are delayed by system clock cycles 0: output + without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ +#define SPI_MEM_SPI_SMEM_DOUT0_MODE (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_DOUT0_MODE_S 0 + +#define SPI_MEM_SPI_SMEM_AC_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D0) +/* SPI_MEM_SPI_SMEM_CS_HOLD_DELAY : R/W ;bitpos:[30:25] ;default: 6'd0 ; */ +/*description: These bits are used to set the minimum CS high time tSHSL between + SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY 0x0000003F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_M ((SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V) << (SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_V 0x3F +#define SPI_MEM_SPI_SMEM_CS_HOLD_DELAY_S 25 +/* SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes + mode when accesses external RAM.*/ +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_M (BIT(16)) +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_16TO18_BYTE_EN_S 16 +/* SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: 1: MSPI skips page corner when accesses external RAM. 0: Not + skip page corner when accesses external RAM.*/ +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_M (BIT(15)) +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_V 0x1 +#define SPI_MEM_SPI_SMEM_ECC_SKIP_PAGE_CORNER_S 15 +/* SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME : R/W ;bitpos:[14:12] ;default: 3'd3 ; */ +/*description: SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI + CS hold cycles in ECC mode when accessed external RAM.*/ +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME 0x00000007 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V) << (SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_V 0x7 +#define SPI_MEM_SPI_SMEM_ECC_CS_HOLD_TIME_S 12 +/* SPI_MEM_SPI_SMEM_CS_HOLD_TIME : R/W ;bitpos:[11:7] ;default: 5'h1 ; */ +/*description: For spi0 spi cs signal is delayed to inactive by spi clock this + bits are combined with spi_mem_cs_hold bit.*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_M ((SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V) << (SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_HOLD_TIME_S 7 +/* SPI_MEM_SPI_SMEM_CS_SETUP_TIME : R/W ;bitpos:[6:2] ;default: 5'h1 ; */ +/*description: For spi0 (cycles-1) of prepare phase by spi clock this bits + are combined with spi_mem_cs_setup bit.*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME 0x0000001F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_M ((SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V) << (SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_V 0x1F +#define SPI_MEM_SPI_SMEM_CS_SETUP_TIME_S 2 +/* SPI_MEM_SPI_SMEM_CS_HOLD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ +#define SPI_MEM_SPI_SMEM_CS_HOLD (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_CS_HOLD_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_HOLD_S 1 +/* SPI_MEM_SPI_SMEM_CS_SETUP : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ +#define SPI_MEM_SPI_SMEM_CS_SETUP (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_CS_SETUP_V 0x1 +#define SPI_MEM_SPI_SMEM_CS_SETUP_S 0 + +#define SPI_MEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D4) +/* SPI_MEM_SPI_FMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to + flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to + flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_FMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_SPI_FMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to flash. .*/ +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus + mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_SPI_FMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases + of CMD and ADDR.*/ +#define SPI_MEM_SPI_FMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_FMEM_DQS_CA_IN_S 26 +/* SPI_MEM_SPI_FMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable the SPI HyperBus mode.*/ +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE (BIT(25)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_M (BIT(25)) +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_V 0x1 +#define SPI_MEM_SPI_FMEM_HYPERBUS_MODE_S 25 +/* SPI_MEM_SPI_FMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#.*/ +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: the bits are combined with the bit spi_fmem_ddr_fdqs_loop which + used to select data strobe generating mode in ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE 0x00000003 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V) << (SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_V 0x3 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_MODE_S 22 +/* SPI_MEM_SPI_FMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: the data strobe is generated by SPI.*/ +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock.*/ +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V) << (SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_FMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR + read mode when accesses to flash.*/ +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR + write mode when accesses to flash.*/ +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_SPI_FMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the panda device.*/ +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V) << (SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_FMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SPI_FMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SPI_FMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SPI_FMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SPI_FMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi ddr mode.*/ +#define SPI_MEM_SPI_FMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_FMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SPI_FMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in ddr mode 0 in sdr mode*/ +#define SPI_MEM_SPI_FMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_FMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_FMEM_DDR_EN_S 0 + +#define SPI_MEM_SPI_SMEM_DDR_REG(i) (REG_SPI_MEM_BASE(i) + 0x0D8) +/* SPI_MEM_SPI_SMEM_HYPERBUS_CA : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to enable HyperRAM address out when accesses to + external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_M (BIT(30)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_CA_S 30 +/* SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to enable octa_ram address out when accesses to + external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_M (BIT(29)) +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_V 0x1 +#define SPI_MEM_SPI_SMEM_OCTA_RAM_ADDR_S 29 +/* SPI_MEM_SPI_SMEM_CLK_DIFF_INV : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_M (BIT(28)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_INV_S 28 +/* SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Set this bit to enable the vary dummy function in SPI HyperBus + mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_M (BIT(27)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_DUMMY_2X_S 27 +/* SPI_MEM_SPI_SMEM_DQS_CA_IN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set this bit to enable the input of SPI_DQS signal in SPI phases + of CMD and ADDR.*/ +#define SPI_MEM_SPI_SMEM_DQS_CA_IN (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_M (BIT(26)) +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_V 0x1 +#define SPI_MEM_SPI_SMEM_DQS_CA_IN_S 26 +/* SPI_MEM_SPI_SMEM_HYPERBUS_MODE : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: Set this bit to enable the SPI HyperBus mode.*/ +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE (BIT(25)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_M (BIT(25)) +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_V 0x1 +#define SPI_MEM_SPI_SMEM_HYPERBUS_MODE_S 25 +/* SPI_MEM_SPI_SMEM_CLK_DIFF_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: Set this bit to enable the differential SPI_CLK#.*/ +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_M (BIT(24)) +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_CLK_DIFF_EN_S 24 +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE : R/W ;bitpos:[23:22] ;default: 2'b0 ; */ +/*description: the bits are combined with the bit spi_smem_ddr_fdqs_loop which + used to select data strobe generating mode in ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE 0x00000003 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_M ((SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V) << (SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_V 0x3 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_MODE_S 22 +/* SPI_MEM_SPI_SMEM_DDR_DQS_LOOP : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: the data strobe is generated by SPI.*/ +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_M (BIT(21)) +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_DQS_LOOP_S 21 +/* SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD : R/W ;bitpos:[20:14] ;default: 7'b0 ; */ +/*description: The delay number of data strobe which from memory based on SPI clock.*/ +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD 0x0000007F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_M ((SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V) << (SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S)) +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_V 0x7F +#define SPI_MEM_SPI_SMEM_USR_DDR_DQS_THD_S 14 +/* SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN : R/W ;bitpos:[13] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR + read mode when accesses to external RAM.*/ +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_M (BIT(13)) +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_RX_DDR_MSK_EN_S 13 +/* SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN : R/W ;bitpos:[12] ;default: 1'h1 ; */ +/*description: Set this bit to mask the first or the last byte in MSPI ECC DDR + write mode when accesses to external RAM.*/ +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_M (BIT(12)) +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_TX_DDR_MSK_EN_S 12 +/* SPI_MEM_SPI_SMEM_OUTMINBYTELEN : R/W ;bitpos:[11:5] ;default: 7'b1 ; */ +/*description: It is the minimum output data length in the ddr psram.*/ +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN 0x0000007F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_M ((SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V) << (SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S)) +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_V 0x7F +#define SPI_MEM_SPI_SMEM_OUTMINBYTELEN_S 5 +/* SPI_MEM_SPI_SMEM_DDR_CMD_DIS : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: the bit is used to disable dual edge in command phase when ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_M (BIT(4)) +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_CMD_DIS_S 4 +/* SPI_MEM_SPI_SMEM_DDR_WDAT_SWP : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Set the bit to reorder tx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_M (BIT(3)) +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_WDAT_SWP_S 3 +/* SPI_MEM_SPI_SMEM_DDR_RDAT_SWP : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: Set the bit to reorder rx data of the word in spi ddr mode.*/ +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_M (BIT(2)) +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_RDAT_SWP_S 2 +/* SPI_MEM_SPI_SMEM_VAR_DUMMY : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set the bit to enable variable dummy cycle in spi ddr mode.*/ +#define SPI_MEM_SPI_SMEM_VAR_DUMMY (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_M (BIT(1)) +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_V 0x1 +#define SPI_MEM_SPI_SMEM_VAR_DUMMY_S 1 +/* SPI_MEM_SPI_SMEM_DDR_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: in ddr mode 0 in sdr mode*/ +#define SPI_MEM_SPI_SMEM_DDR_EN (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_M (BIT(0)) +#define SPI_MEM_SPI_SMEM_DDR_EN_V 0x1 +#define SPI_MEM_SPI_SMEM_DDR_EN_S 0 + +#define SPI_MEM_CLOCK_GATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x0DC) +/* SPI_MEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: Register clock gate enable signal. 1: Enable. 0: Disable.*/ +#define SPI_MEM_CLK_EN (BIT(0)) +#define SPI_MEM_CLK_EN_M (BIT(0)) +#define SPI_MEM_CLK_EN_V 0x1 +#define SPI_MEM_CLK_EN_S 0 + +#define SPI_MEM_CORE_CLK_SEL_REG(i) (REG_SPI_MEM_BASE(i) + 0x0E0) +/* SPI_MEM_SPI01_CLK_SEL : R/W ;bitpos:[1:0] ;default: 2'd0 ; */ +/*description: When the digital system clock selects PLL clock and the frequency + of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ +#define SPI_MEM_SPI01_CLK_SEL 0x00000003 +#define SPI_MEM_SPI01_CLK_SEL_M ((SPI_MEM_SPI01_CLK_SEL_V) << (SPI_MEM_SPI01_CLK_SEL_S)) +#define SPI_MEM_SPI01_CLK_SEL_V 0x3 +#define SPI_MEM_SPI01_CLK_SEL_S 0 + +#define SPI_MEM_DATE_REG(i) (REG_SPI_MEM_BASE(i) + 0x3FC) +/* SPI_MEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2004010 ; */ +/*description: SPI register version.*/ +#define SPI_MEM_DATE 0x0FFFFFFF +#define SPI_MEM_DATE_M ((SPI_MEM_DATE_V) << (SPI_MEM_DATE_S)) +#define SPI_MEM_DATE_V 0xFFFFFFF +#define SPI_MEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/spi_mem_struct.h b/components/soc/soc/esp32s3/include/soc/spi_mem_struct.h new file mode 100644 index 000000000..d8f665cb1 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/spi_mem_struct.h @@ -0,0 +1,646 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + uint32_t addr; /*In user mode it is the memory address. other then the bit0-bit23 is the memory address the bit24-bit31 are the byte length of a transfer.*/ + union { + struct { + uint32_t reserved0: 3; /*reserved*/ + uint32_t fdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ + uint32_t fdout_oct: 1; /*Apply 8 signals during write-data phase 1:enable 0: disable*/ + uint32_t fdin_oct: 1; /*Apply 8 signals during read-data phase 1:enable 0: disable*/ + uint32_t faddr_oct: 1; /*Apply 8 signals during address phase 1:enable 0: disable*/ + uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable*/ + uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable*/ + uint32_t fcs_crc_en: 1; /*For SPI1 initialize crc32 module before writing encrypted data to flash. Active low.*/ + uint32_t tx_crc_en: 1; /*For SPI1 enable crc32 when writing encrypted data to flash. 1: enable 0:disable*/ + uint32_t reserved12: 1; /*reserved*/ + uint32_t fastrd_mode: 1; /*This bit enable the bits: spi_mem_fread_qio spi_mem_fread_dio spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t reserved15: 3; /*reserved*/ + uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low*/ + uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t wp: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low.*/ + uint32_t reserved22: 1; /*reserved*/ + uint32_t fread_dio: 1; /*In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.*/ + uint32_t fread_qio: 1; /*In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t reserved25: 7; /*reserved*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t reserved2: 30; /*reserved*/ + }; + uint32_t val; + } ctrl1; + union { + struct { + uint32_t cs_setup_time: 5; /*(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t cs_hold_time: 5; /*Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t ecc_cs_hold_time: 3; /*SPI_MEM_CS_HOLD_TIME + SPI_MEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycle in ECC mode when accessed flash.*/ + uint32_t ecc_skip_page_corner: 1; /*1: MSPI skips page corner when accesses flash. 0: Not skip page corner when accesses flash.*/ + uint32_t ecc_16to18_byte_en: 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses flash.*/ + uint32_t reserved15: 10; /*reserved*/ + uint32_t cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t sync_reset: 1; /*The FSM will be reset.*/ + }; + uint32_t val; + } ctrl2; + union { + struct { + uint32_t clkcnt_l: 8; /*In the master mode it must be equal to spi_mem_clkcnt_N.*/ + uint32_t clkcnt_h: 8; /*In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t clkcnt_n: 8; /*In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24: 7; /*reserved*/ + uint32_t clk_equ_sysclk: 1; /*Set this bit in 1-division mode.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t reserved0: 6; /*reserved*/ + uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ + uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ + uint32_t reserved8: 1; /*reserved*/ + uint32_t ck_out_edge: 1; /*the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.*/ + uint32_t reserved10: 16; /*reserved*/ + uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable.*/ + uint32_t reserved27: 1; /*reserved*/ + uint32_t reserved28: 1; /*reserved*/ + uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation.*/ + uint32_t reserved30: 1; /*reserved*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen: 6; /*The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).*/ + uint32_t reserved6: 20; /*reserved*/ + uint32_t usr_addr_bitlen: 6; /*The length in bits of address phase. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value: 16; /*The value of command.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1)*/ + }; + uint32_t val; + } user2; + uint32_t reserved_24; + uint32_t reserved_28; + union { + struct { + uint32_t reserved0: 16; /*reserved*/ + uint32_t wb_mode: 8; /*Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t reserved24: 8; /*reserved*/ + }; + uint32_t val; + } rd_status; + uint32_t ext_addr; /*The register are the higher 32bits in the 64 bits address mode.*/ + union { + struct { + uint32_t reserved0: 3; /*reserved*/ + uint32_t trans_end: 1; /*The bit is used to indicate the transimitting is done.*/ + uint32_t trans_end_en: 1; /*The bit is used to enable the intterrupt of SPI transmitting done.*/ + uint32_t reserved5: 2; /*reserved*/ + uint32_t fsub_pin: 1; /*For SPI0 flash is connected to SUBPINs.*/ + uint32_t ssub_pin: 1; /*For SPI0 sram is connected to SUBPINs.*/ + uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle*/ + uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set.*/ + uint32_t reserved11: 21; /*reserved*/ + }; + uint32_t val; + } misc; + uint32_t tx_crc; /*For SPI1 the value of crc32.*/ + union { + struct { + uint32_t req_en: 1; /*For SPI0 Cache access enable 1: enable 0:disable.*/ + uint32_t usr_cmd_4byte: 1; /*For SPI0 cache read flash with 4 bytes command 1: enable 0:disable.*/ + uint32_t flash_usr_cmd: 1; /*For SPI0 cache read flash for user define command 1: enable 0:disable.*/ + uint32_t fdin_dual: 1; /*For SPI0 flash din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdout_dual: 1; /*For SPI0 flash dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t faddr_dual: 1; /*For SPI0 flash address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.*/ + uint32_t fdin_quad: 1; /*For SPI0 flash din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t fdout_quad: 1; /*For SPI0 flash dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t faddr_quad: 1; /*For SPI0 flash address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } cache_fctrl; + union { + struct { + uint32_t usr_scmd_4byte: 1; /*For SPI0 In the spi sram mode cache read flash with 4 bytes command 1: enable 0:disable.*/ + uint32_t usr_sram_dio: 1; /*For SPI0 In the spi sram mode spi dual I/O mode enable 1: enable 0:disable*/ + uint32_t usr_sram_qio: 1; /*For SPI0 In the spi sram mode spi quad I/O mode enable 1: enable 0:disable*/ + uint32_t usr_wr_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for write operations.*/ + uint32_t usr_rd_sram_dummy: 1; /*For SPI0 In the spi sram mode it is the enable bit of dummy phase for read operations.*/ + uint32_t cache_sram_usr_rcmd: 1; /*For SPI0 In the spi sram mode cache read sram for user define command.*/ + uint32_t sram_rdummy_cyclelen: 6; /*For SPI0 In the sram mode it is the length in bits of read dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved12: 2; /*reserved*/ + uint32_t sram_addr_bitlen: 6; /*For SPI0 In the sram mode it is the length in bits of address phase. The register value shall be (bit_num-1).*/ + uint32_t cache_sram_usr_wcmd: 1; /*For SPI0 In the spi sram mode cache write sram for user define command*/ + uint32_t sram_oct: 1; /*reserved*/ + uint32_t sram_wdummy_cyclelen: 6; /*For SPI0 In the sram mode it is the length in bits of write dummy phase. The register value shall be (bit_num-1).*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } cache_sctrl; + union { + struct { + uint32_t sclk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.*/ + uint32_t swb_mode: 8; /*Mode bits in the psram fast read mode it is combined with spi_mem_fastrd_mode bit.*/ + uint32_t sdin_dual: 1; /*For SPI0 sram din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t sdout_dual: 1; /*For SPI0 sram dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t saddr_dual: 1; /*For SPI0 sram address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t scmd_dual: 1; /*For SPI0 sram cmd phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_dio.*/ + uint32_t sdin_quad: 1; /*For SPI0 sram din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdout_quad: 1; /*For SPI0 sram dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t saddr_quad: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t scmd_quad: 1; /*For SPI0 sram cmd phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_usr_sram_qio.*/ + uint32_t sdin_oct: 1; /*For SPI0 sram din phase apply 8 signals. 1: enable 0: disable.*/ + uint32_t sdout_oct: 1; /*For SPI0 sram dout phase apply 8 signals. 1: enable 0: disable.*/ + uint32_t saddr_oct: 1; /*For SPI0 sram address phase apply 4 signals. 1: enable 0: disable.*/ + uint32_t scmd_oct: 1; /*For SPI0 sram cmd phase apply 8 signals. 1: enable 0: disable.*/ + uint32_t sdummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller.*/ + uint32_t reserved23: 9; /*reserved*/ + }; + uint32_t val; + } sram_cmd; + union { + struct { + uint32_t usr_rd_cmd_value: 16; /*For SPI0 When cache mode is enable it is the read command value of command phase for sram.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_rd_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the length in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_drd_cmd; + union { + struct { + uint32_t usr_wr_cmd_value: 16; /*For SPI0 When cache mode is enable it is the write command value of command phase for sram.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_wr_cmd_bitlen: 4; /*For SPI0 When cache mode is enable it is the in bits of command phase for sram. The register value shall be (bit_num-1).*/ + }; + uint32_t val; + } sram_dwr_cmd; + union { + struct { + uint32_t cnt_l: 8; /*For SPI0 sram interface it must be equal to spi_mem_clkcnt_N.*/ + uint32_t cnt_h: 8; /*For SPI0 sram interface it must be floor((spi_mem_clkcnt_N+1)/2-1).*/ + uint32_t cnt_n: 8; /*For SPI0 sram interface it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)*/ + uint32_t reserved24: 7; /*reserved*/ + uint32_t equ_sysclk: 1; /*For SPI0 sram interface 1: spi_mem_clk is eqaul to system 0: spi_mem_clk is divided from system clock.*/ + }; + uint32_t val; + } sram_clk; + union { + struct { + uint32_t st: 3; /*The status of spi state machine. 0: idle state 1: preparation state 2: send command state 3: send data state 4: red data state 5:write data state 6: wait state 7: done state.*/ + uint32_t reserved3: 29; /*reserved*/ + }; + uint32_t val; + } fsm; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + union { + struct { + uint32_t timing_clk_ena: 1; /*The bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t timing_cali: 1; /*The bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t extra_dummy_cyclelen: 3; /*add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } timing_cali; + union { + struct { + uint32_t din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t dins_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout1_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout2_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout3_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t dout4_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout5_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout6_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t dout7_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t douts_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the spi_clk*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dout_mode; + uint32_t reserved_b8; + union { + struct { + uint32_t spi_smem_timing_clk_ena: 1; /*For sram the bit is used to enable timing adjust clock for all reading operations.*/ + uint32_t spi_smem_timing_cali: 1; /*For sram the bit is used to enable timing auto-calibration for all reading operations.*/ + uint32_t spi_smem_extra_dummy_cyclelen: 3; /*For sram add extra dummy spi clock cycle length for spi clock calibration.*/ + uint32_t reserved5: 27; + }; + uint32_t val; + } spi_smem_timing_cali; + union { + struct { + uint32_t spi_smem_din0_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din1_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din2_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din3_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din4_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din5_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din6_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_din7_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t spi_smem_dins_mode: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_mode; + union { + struct { + uint32_t spi_smem_din0_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din1_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din2_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din3_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din4_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din5_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din6_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_din7_num: 2; /*the input signals are delayed by system clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ...*/ + uint32_t spi_smem_dins_num: 2; /*the input signals are delayed by system clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the posedge of clk_160 4 input with the negedge of clk_160 5: input with the spi_clk high edge 6: input with the spi_clk low edge*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } spi_smem_din_num; + union { + struct { + uint32_t spi_smem_dout0_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout1_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout2_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout3_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout4_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout5_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout6_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_dout7_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t spi_smem_douts_mode: 1; /*the output signals are delayed by system clock cycles 0: output without delayed 1: output with the posedge of clk_apb 2 output with the negedge of clk_apb 3: output with the posedge of clk_160 4 output with the negedge of clk_160 5: output with the spi_clk high edge 6: output with the spi_clk low edge*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } spi_smem_dout_mode; + uint32_t reserved_cc; + union { + struct { + uint32_t spi_smem_cs_setup: 1; /*For spi0 spi cs is enable when spi is in prepare phase. 1: enable 0: disable.*/ + uint32_t spi_smem_cs_hold: 1; /*For spi0 spi cs keep low when spi is in done phase. 1: enable 0: disable.*/ + uint32_t spi_smem_cs_setup_time: 5; /*For spi0 (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.*/ + uint32_t spi_smem_cs_hold_time: 5; /*For spi0 spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.*/ + uint32_t spi_smem_ecc_cs_hold_time: 3; /*SPI_SMEM_CS_HOLD_TIME + SPI_SMEM_ECC_CS_HOLD_TIME is the MSPI CS hold cycles in ECC mode when accessed external RAM.*/ + uint32_t spi_smem_ecc_skip_page_corner: 1; /*1: MSPI skips page corner when accesses external RAM. 0: Not skip page corner when accesses external RAM.*/ + uint32_t spi_smem_ecc_16to18_byte_en: 1; /*Set this bit to enable MSPI ECC 16 bytes data with 2 ECC bytes mode when accesses external RAM.*/ + uint32_t reserved17: 8; /*reserved*/ + uint32_t spi_smem_cs_hold_delay: 6; /*These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to external RAM. tSHSL is (SPI_SMEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } spi_smem_ac; + union { + struct { + uint32_t spi_fmem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/ + uint32_t spi_fmem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/ + uint32_t spi_fmem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/ + uint32_t spi_fmem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/ + uint32_t spi_fmem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/ + uint32_t spi_fmem_outminbytelen: 7; /*It is the minimum output data length in the panda device.*/ + uint32_t spi_fmem_tx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to flash.*/ + uint32_t spi_fmem_rx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to flash.*/ + uint32_t spi_fmem_usr_ddr_dqs_thd: 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t spi_fmem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/ + uint32_t spi_fmem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_fmem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/ + uint32_t spi_fmem_clk_diff_en: 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t spi_fmem_hyperbus_mode: 1; /*Set this bit to enable the SPI HyperBus mode.*/ + uint32_t spi_fmem_dqs_ca_in: 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t spi_fmem_hyperbus_dummy_2x: 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t spi_fmem_clk_diff_inv: 1; /*Set this bit to invert SPI_DIFF when accesses to flash. .*/ + uint32_t spi_fmem_octa_ram_addr: 1; /*Set this bit to enable octa_ram address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ + uint32_t spi_fmem_hyperbus_ca: 1; /*Set this bit to enable HyperRAM address out when accesses to flash which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } ddr; + union { + struct { + uint32_t spi_smem_ddr_en: 1; /*1: in ddr mode 0 in sdr mode*/ + uint32_t spi_smem_var_dummy: 1; /*Set the bit to enable variable dummy cycle in spi ddr mode.*/ + uint32_t spi_smem_ddr_rdat_swp: 1; /*Set the bit to reorder rx data of the word in spi ddr mode.*/ + uint32_t spi_smem_ddr_wdat_swp: 1; /*Set the bit to reorder tx data of the word in spi ddr mode.*/ + uint32_t spi_smem_ddr_cmd_dis: 1; /*the bit is used to disable dual edge in command phase when ddr mode.*/ + uint32_t spi_smem_outminbytelen: 7; /*It is the minimum output data length in the ddr psram.*/ + uint32_t spi_smem_tx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR write mode when accesses to external RAM.*/ + uint32_t spi_smem_rx_ddr_msk_en: 1; /*Set this bit to mask the first or the last byte in MSPI ECC DDR read mode when accesses to external RAM.*/ + uint32_t spi_smem_usr_ddr_dqs_thd: 7; /*The delay number of data strobe which from memory based on SPI clock.*/ + uint32_t spi_smem_ddr_dqs_loop: 1; /*the data strobe is generated by SPI.*/ + uint32_t spi_smem_ddr_dqs_loop_mode: 2; /*the bits are combined with the bit spi_smem_ddr_fdqs_loop which used to select data strobe generating mode in ddr mode.*/ + uint32_t spi_smem_clk_diff_en: 1; /*Set this bit to enable the differential SPI_CLK#.*/ + uint32_t spi_smem_hyperbus_mode: 1; /*Set this bit to enable the SPI HyperBus mode.*/ + uint32_t spi_smem_dqs_ca_in: 1; /*Set this bit to enable the input of SPI_DQS signal in SPI phases of CMD and ADDR.*/ + uint32_t spi_smem_hyperbus_dummy_2x: 1; /*Set this bit to enable the vary dummy function in SPI HyperBus mode when SPI0 accesses flash or SPI1 accesses flash or sram.*/ + uint32_t spi_smem_clk_diff_inv: 1; /*Set this bit to invert SPI_DIFF when accesses to external RAM. .*/ + uint32_t spi_smem_octa_ram_addr: 1; /*Set this bit to enable octa_ram address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[25:4] 6'd0 spi_usr_addr_value[3:1] 1'b0}.*/ + uint32_t spi_smem_hyperbus_ca: 1; /*Set this bit to enable HyperRAM address out when accesses to external RAM which means ADDR_OUT[31:0] = {spi_usr_addr_value[19:4] 13'd0 spi_usr_addr_value[3:1]}.*/ + uint32_t reserved31: 1; /*reserved*/ + }; + uint32_t val; + } spi_smem_ddr; + union { + struct { + uint32_t clk_en: 1; /*Register clock gate enable signal. 1: Enable. 0: Disable.*/ + uint32_t reserved1: 31; /*reserved*/ + }; + uint32_t val; + } clock_gate; + union { + struct { + uint32_t spi01_clk_sel: 2; /*When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.*/ + uint32_t reserved2: 30; /*reserved*/ + }; + uint32_t val; + } core_clk_sel; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + union { + struct { + uint32_t date: 28; /*SPI register version.*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_mem_dev_t; + +extern spi_mem_dev_t SPIMEM0; +extern spi_mem_dev_t SPIMEM1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/spi_pins.h b/components/soc/soc/esp32s3/include/soc/spi_pins.h new file mode 100644 index 000000000..12f7aa639 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/spi_pins.h @@ -0,0 +1,35 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SPI_PERIPH_NUM 3 + +#define SPI_FUNC_NUM 2 +#define SPI_IOMUX_PIN_NUM_HD 27 +#define SPI_IOMUX_PIN_NUM_CS 29 +#define SPI_IOMUX_PIN_NUM_MOSI 32 +#define SPI_IOMUX_PIN_NUM_CLK 30 +#define SPI_IOMUX_PIN_NUM_MISO 31 +#define SPI_IOMUX_PIN_NUM_WP 28 +//TODO: add the next slot + +#define FSPI_FUNC_NUM 0 +#define FSPI_IOMUX_PIN_NUM_HD 9 +#define FSPI_IOMUX_PIN_NUM_CS 10 +#define FSPI_IOMUX_PIN_NUM_MOSI 11 +#define FSPI_IOMUX_PIN_NUM_CLK 12 +#define FSPI_IOMUX_PIN_NUM_MISO 13 +#define FSPI_IOMUX_PIN_NUM_WP 14 +//TODO: add the next slot diff --git a/components/soc/soc/esp32s3/include/soc/spi_reg.h b/components/soc/soc/esp32s3/include/soc/spi_reg.h new file mode 100644 index 000000000..89b4afeae --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/spi_reg.h @@ -0,0 +1,1588 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) +/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: User define command enable. An operation will be triggered when + the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ +#define SPI_USR (BIT(24)) +#define SPI_USR_M (BIT(24)) +#define SPI_USR_V 0x1 +#define SPI_USR_S 24 +/* SPI_UPDATE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: Set this bit to synchronize SPI registers from APB clock domain + into SPI module clock domain which is only used in SPI master mode.*/ +#define SPI_UPDATE (BIT(23)) +#define SPI_UPDATE_M (BIT(23)) +#define SPI_UPDATE_V 0x1 +#define SPI_UPDATE_S 23 +/* SPI_CONF_BITLEN : R/W ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ +#define SPI_CONF_BITLEN 0x0003FFFF +#define SPI_CONF_BITLEN_M ((SPI_CONF_BITLEN_V) << (SPI_CONF_BITLEN_S)) +#define SPI_CONF_BITLEN_V 0x3FFFF +#define SPI_CONF_BITLEN_S 0 + +#define SPI_ADDR_REG(i) (REG_SPI_BASE(i) + 0x004) +/* SPI_USR_ADDR_VALUE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: Address to slave. Can be configured in CONF state.*/ +#define SPI_USR_ADDR_VALUE 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_M ((SPI_USR_ADDR_VALUE_V) << (SPI_USR_ADDR_VALUE_S)) +#define SPI_USR_ADDR_VALUE_V 0xFFFFFFFF +#define SPI_USR_ADDR_VALUE_S 0 + +#define SPI_CTRL_REG(i) (REG_SPI_BASE(i) + 0x008) +/* SPI_WR_BIT_ORDER : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: In command address write-data (MOSI) phases 1: LSB firs 0: MSB + first. Can be configured in CONF state.*/ +#define SPI_WR_BIT_ORDER (BIT(26)) +#define SPI_WR_BIT_ORDER_M (BIT(26)) +#define SPI_WR_BIT_ORDER_V 0x1 +#define SPI_WR_BIT_ORDER_S 26 +/* SPI_RD_BIT_ORDER : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured + in CONF state.*/ +#define SPI_RD_BIT_ORDER (BIT(25)) +#define SPI_RD_BIT_ORDER_M (BIT(25)) +#define SPI_RD_BIT_ORDER_V 0x1 +#define SPI_RD_BIT_ORDER_S 25 +/* SPI_WP_POL : R/W ;bitpos:[21] ;default: 1'b1 ; */ +/*description: Write protect signal output when SPI is idle. 1: output high + 0: output low. Can be configured in CONF state.*/ +#define SPI_WP_POL (BIT(21)) +#define SPI_WP_POL_M (BIT(21)) +#define SPI_WP_POL_V 0x1 +#define SPI_WP_POL_S 21 +/* SPI_HOLD_POL : R/W ;bitpos:[20] ;default: 1'b1 ; */ +/*description: SPI_HOLD output value when SPI is idle. 1: output high 0: output + low. Can be configured in CONF state.*/ +#define SPI_HOLD_POL (BIT(20)) +#define SPI_HOLD_POL_M (BIT(20)) +#define SPI_HOLD_POL_V 0x1 +#define SPI_HOLD_POL_S 20 +/* SPI_D_POL : R/W ;bitpos:[19] ;default: 1'b1 ; */ +/*description: The bit is used to set MOSI line polarity 1: high 0 low. Can + be configured in CONF state.*/ +#define SPI_D_POL (BIT(19)) +#define SPI_D_POL_M (BIT(19)) +#define SPI_D_POL_V 0x1 +#define SPI_D_POL_S 19 +/* SPI_Q_POL : R/W ;bitpos:[18] ;default: 1'b1 ; */ +/*description: The bit is used to set MISO line polarity 1: high 0 low. Can + be configured in CONF state.*/ +#define SPI_Q_POL (BIT(18)) +#define SPI_Q_POL_M (BIT(18)) +#define SPI_Q_POL_V 0x1 +#define SPI_Q_POL_S 18 +/* SPI_FREAD_OCT : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 8 signals. 1: enable + 0: disable. Can be configured in CONF state.*/ +#define SPI_FREAD_OCT (BIT(16)) +#define SPI_FREAD_OCT_M (BIT(16)) +#define SPI_FREAD_OCT_V 0x1 +#define SPI_FREAD_OCT_S 16 +/* SPI_FREAD_QUAD : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 4 signals. 1: enable + 0: disable. Can be configured in CONF state.*/ +#define SPI_FREAD_QUAD (BIT(15)) +#define SPI_FREAD_QUAD_M (BIT(15)) +#define SPI_FREAD_QUAD_V 0x1 +#define SPI_FREAD_QUAD_S 15 +/* SPI_FREAD_DUAL : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the read operations read-data phase apply 2 signals. 1: enable + 0: disable. Can be configured in CONF state.*/ +#define SPI_FREAD_DUAL (BIT(14)) +#define SPI_FREAD_DUAL_M (BIT(14)) +#define SPI_FREAD_DUAL_V 0x1 +#define SPI_FREAD_DUAL_S 14 +/* SPI_FCMD_OCT : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: Apply 8 signals during command phase 1:enable 0: disable. Can + be configured in CONF state.*/ +#define SPI_FCMD_OCT (BIT(10)) +#define SPI_FCMD_OCT_M (BIT(10)) +#define SPI_FCMD_OCT_V 0x1 +#define SPI_FCMD_OCT_S 10 +/* SPI_FCMD_QUAD : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: Apply 4 signals during command phase 1:enable 0: disable. Can + be configured in CONF state.*/ +#define SPI_FCMD_QUAD (BIT(9)) +#define SPI_FCMD_QUAD_M (BIT(9)) +#define SPI_FCMD_QUAD_V 0x1 +#define SPI_FCMD_QUAD_S 9 +/* SPI_FCMD_DUAL : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: Apply 2 signals during command phase 1:enable 0: disable. Can + be configured in CONF state.*/ +#define SPI_FCMD_DUAL (BIT(8)) +#define SPI_FCMD_DUAL_M (BIT(8)) +#define SPI_FCMD_DUAL_V 0x1 +#define SPI_FCMD_DUAL_S 8 +/* SPI_FADDR_OCT : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: Apply 8 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state.*/ +#define SPI_FADDR_OCT (BIT(7)) +#define SPI_FADDR_OCT_M (BIT(7)) +#define SPI_FADDR_OCT_V 0x1 +#define SPI_FADDR_OCT_S 7 +/* SPI_FADDR_QUAD : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: Apply 4 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state.*/ +#define SPI_FADDR_QUAD (BIT(6)) +#define SPI_FADDR_QUAD_M (BIT(6)) +#define SPI_FADDR_QUAD_V 0x1 +#define SPI_FADDR_QUAD_S 6 +/* SPI_FADDR_DUAL : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: Apply 2 signals during addr phase 1:enable 0: disable. Can be + configured in CONF state.*/ +#define SPI_FADDR_DUAL (BIT(5)) +#define SPI_FADDR_DUAL_M (BIT(5)) +#define SPI_FADDR_DUAL_V 0x1 +#define SPI_FADDR_DUAL_S 5 +/* SPI_DUMMY_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: In the dummy phase the signal level of spi is output by the spi + controller. Can be configured in CONF state.*/ +#define SPI_DUMMY_OUT (BIT(3)) +#define SPI_DUMMY_OUT_M (BIT(3)) +#define SPI_DUMMY_OUT_V 0x1 +#define SPI_DUMMY_OUT_S 3 + +#define SPI_CLOCK_REG(i) (REG_SPI_BASE(i) + 0x00C) +/* SPI_CLK_EQU_SYSCLK : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: In the master mode 1: spi_clk is eqaul to system 0: spi_clk is + divided from system clock. Can be configured in CONF state.*/ +#define SPI_CLK_EQU_SYSCLK (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_M (BIT(31)) +#define SPI_CLK_EQU_SYSCLK_V 0x1 +#define SPI_CLK_EQU_SYSCLK_S 31 +/* SPI_CLKDIV_PRE : R/W ;bitpos:[30:18] ;default: 13'b0 ; */ +/*description: In the master mode it is pre-divider of spi_clk. Can be configured + in CONF state.*/ +#define SPI_CLKDIV_PRE 0x00001FFF +#define SPI_CLKDIV_PRE_M ((SPI_CLKDIV_PRE_V) << (SPI_CLKDIV_PRE_S)) +#define SPI_CLKDIV_PRE_V 0x1FFF +#define SPI_CLKDIV_PRE_S 18 +/* SPI_CLKCNT_N : R/W ;bitpos:[17:12] ;default: 6'h3 ; */ +/*description: In the master mode it is the divider of spi_clk. So spi_clk frequency + is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ +#define SPI_CLKCNT_N 0x0000003F +#define SPI_CLKCNT_N_M ((SPI_CLKCNT_N_V) << (SPI_CLKCNT_N_S)) +#define SPI_CLKCNT_N_V 0x3F +#define SPI_CLKCNT_N_S 12 +/* SPI_CLKCNT_H : R/W ;bitpos:[11:6] ;default: 6'h1 ; */ +/*description: In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In + the slave mode it must be 0. Can be configured in CONF state.*/ +#define SPI_CLKCNT_H 0x0000003F +#define SPI_CLKCNT_H_M ((SPI_CLKCNT_H_V) << (SPI_CLKCNT_H_S)) +#define SPI_CLKCNT_H_V 0x3F +#define SPI_CLKCNT_H_S 6 +/* SPI_CLKCNT_L : R/W ;bitpos:[5:0] ;default: 6'h3 ; */ +/*description: In the master mode it must be equal to spi_clkcnt_N. In the slave + mode it must be 0. Can be configured in CONF state.*/ +#define SPI_CLKCNT_L 0x0000003F +#define SPI_CLKCNT_L_M ((SPI_CLKCNT_L_V) << (SPI_CLKCNT_L_S)) +#define SPI_CLKCNT_L_V 0x3F +#define SPI_CLKCNT_L_S 0 + +#define SPI_USER_REG(i) (REG_SPI_BASE(i) + 0x010) +/* SPI_USR_COMMAND : R/W ;bitpos:[31] ;default: 1'b1 ; */ +/*description: This bit enable the command phase of an operation. Can be configured + in CONF state.*/ +#define SPI_USR_COMMAND (BIT(31)) +#define SPI_USR_COMMAND_M (BIT(31)) +#define SPI_USR_COMMAND_V 0x1 +#define SPI_USR_COMMAND_S 31 +/* SPI_USR_ADDR : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: This bit enable the address phase of an operation. Can be configured + in CONF state.*/ +#define SPI_USR_ADDR (BIT(30)) +#define SPI_USR_ADDR_M (BIT(30)) +#define SPI_USR_ADDR_V 0x1 +#define SPI_USR_ADDR_S 30 +/* SPI_USR_DUMMY : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: This bit enable the dummy phase of an operation. Can be configured + in CONF state.*/ +#define SPI_USR_DUMMY (BIT(29)) +#define SPI_USR_DUMMY_M (BIT(29)) +#define SPI_USR_DUMMY_V 0x1 +#define SPI_USR_DUMMY_S 29 +/* SPI_USR_MISO : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: This bit enable the read-data phase of an operation. Can be configured + in CONF state.*/ +#define SPI_USR_MISO (BIT(28)) +#define SPI_USR_MISO_M (BIT(28)) +#define SPI_USR_MISO_V 0x1 +#define SPI_USR_MISO_S 28 +/* SPI_USR_MOSI : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: This bit enable the write-data phase of an operation. Can be + configured in CONF state.*/ +#define SPI_USR_MOSI (BIT(27)) +#define SPI_USR_MOSI_M (BIT(27)) +#define SPI_USR_MOSI_V 0x1 +#define SPI_USR_MOSI_S 27 +/* SPI_USR_DUMMY_IDLE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: spi clock is disable in dummy phase when the bit is enable. Can + be configured in CONF state.*/ +#define SPI_USR_DUMMY_IDLE (BIT(26)) +#define SPI_USR_DUMMY_IDLE_M (BIT(26)) +#define SPI_USR_DUMMY_IDLE_V 0x1 +#define SPI_USR_DUMMY_IDLE_S 26 +/* SPI_USR_MOSI_HIGHPART : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: write-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable. Can be configured in CONF state.*/ +#define SPI_USR_MOSI_HIGHPART (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_M (BIT(25)) +#define SPI_USR_MOSI_HIGHPART_V 0x1 +#define SPI_USR_MOSI_HIGHPART_S 25 +/* SPI_USR_MISO_HIGHPART : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: read-data phase only access to high-part of the buffer spi_w8~spi_w15. + 1: enable 0: disable. Can be configured in CONF state.*/ +#define SPI_USR_MISO_HIGHPART (BIT(24)) +#define SPI_USR_MISO_HIGHPART_M (BIT(24)) +#define SPI_USR_MISO_HIGHPART_V 0x1 +#define SPI_USR_MISO_HIGHPART_S 24 +/* SPI_SIO : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: Set the bit to enable 3-line half duplex communication mosi and + miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ +#define SPI_SIO (BIT(17)) +#define SPI_SIO_M (BIT(17)) +#define SPI_SIO_V 0x1 +#define SPI_SIO_S 17 +/* SPI_USR_CONF_NXT : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: 1: Enable the DMA CONF phase of next seg-trans operation which + means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ +#define SPI_USR_CONF_NXT (BIT(15)) +#define SPI_USR_CONF_NXT_M (BIT(15)) +#define SPI_USR_CONF_NXT_V 0x1 +#define SPI_USR_CONF_NXT_S 15 +/* SPI_FWRITE_OCT : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 8 signals. Can + be configured in CONF state.*/ +#define SPI_FWRITE_OCT (BIT(14)) +#define SPI_FWRITE_OCT_M (BIT(14)) +#define SPI_FWRITE_OCT_V 0x1 +#define SPI_FWRITE_OCT_S 14 +/* SPI_FWRITE_QUAD : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 4 signals. Can + be configured in CONF state.*/ +#define SPI_FWRITE_QUAD (BIT(13)) +#define SPI_FWRITE_QUAD_M (BIT(13)) +#define SPI_FWRITE_QUAD_V 0x1 +#define SPI_FWRITE_QUAD_S 13 +/* SPI_FWRITE_DUAL : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: In the write operations read-data phase apply 2 signals. Can + be configured in CONF state.*/ +#define SPI_FWRITE_DUAL (BIT(12)) +#define SPI_FWRITE_DUAL_M (BIT(12)) +#define SPI_FWRITE_DUAL_V 0x1 +#define SPI_FWRITE_DUAL_S 12 +/* SPI_CK_OUT_EDGE : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: the bit combined with spi_mosi_delay_mode bits to set mosi signal + delay mode. Can be configured in CONF state.*/ +#define SPI_CK_OUT_EDGE (BIT(9)) +#define SPI_CK_OUT_EDGE_M (BIT(9)) +#define SPI_CK_OUT_EDGE_V 0x1 +#define SPI_CK_OUT_EDGE_S 9 +/* SPI_RSCK_I_EDGE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: In the slave mode this bit can be used to change the polarity + of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ +#define SPI_RSCK_I_EDGE (BIT(8)) +#define SPI_RSCK_I_EDGE_M (BIT(8)) +#define SPI_RSCK_I_EDGE_V 0x1 +#define SPI_RSCK_I_EDGE_S 8 +/* SPI_CS_SETUP : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: spi cs is enable when spi is in prepare phase. 1: enable 0: + disable. Can be configured in CONF state.*/ +#define SPI_CS_SETUP (BIT(7)) +#define SPI_CS_SETUP_M (BIT(7)) +#define SPI_CS_SETUP_V 0x1 +#define SPI_CS_SETUP_S 7 +/* SPI_CS_HOLD : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: spi cs keep low when spi is in done phase. 1: enable 0: disable. + Can be configured in CONF state.*/ +#define SPI_CS_HOLD (BIT(6)) +#define SPI_CS_HOLD_M (BIT(6)) +#define SPI_CS_HOLD_V 0x1 +#define SPI_CS_HOLD_S 6 +/* SPI_TSCK_I_EDGE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: In the slave mode this bit can be used to change the polarity + of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ +#define SPI_TSCK_I_EDGE (BIT(5)) +#define SPI_TSCK_I_EDGE_M (BIT(5)) +#define SPI_TSCK_I_EDGE_V 0x1 +#define SPI_TSCK_I_EDGE_S 5 +/* SPI_OPI_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: Just for master mode. 1: spi controller is in OPI mode (all in + 8-b-m). 0: others. Can be configured in CONF state.*/ +#define SPI_OPI_MODE (BIT(4)) +#define SPI_OPI_MODE_M (BIT(4)) +#define SPI_OPI_MODE_V 0x1 +#define SPI_OPI_MODE_S 4 +/* SPI_QPI_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: Both for master mode and slave mode. 1: spi controller is in + QPI mode. 0: others. Can be configured in CONF state.*/ +#define SPI_QPI_MODE (BIT(3)) +#define SPI_QPI_MODE_M (BIT(3)) +#define SPI_QPI_MODE_V 0x1 +#define SPI_QPI_MODE_S 3 +/* SPI_DOUTDIN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set the bit to enable full duplex communication. 1: enable 0: + disable. Can be configured in CONF state.*/ +#define SPI_DOUTDIN (BIT(0)) +#define SPI_DOUTDIN_M (BIT(0)) +#define SPI_DOUTDIN_V 0x1 +#define SPI_DOUTDIN_S 0 + +#define SPI_USER1_REG(i) (REG_SPI_BASE(i) + 0x014) +/* SPI_USR_ADDR_BITLEN : R/W ;bitpos:[31:27] ;default: 5'd23 ; */ +/*description: The length in bits of address phase. The register value shall + be (bit_num-1). Can be configured in CONF state.*/ +#define SPI_USR_ADDR_BITLEN 0x0000001F +#define SPI_USR_ADDR_BITLEN_M ((SPI_USR_ADDR_BITLEN_V) << (SPI_USR_ADDR_BITLEN_S)) +#define SPI_USR_ADDR_BITLEN_V 0x1F +#define SPI_USR_ADDR_BITLEN_S 27 +/* SPI_CS_HOLD_TIME : R/W ;bitpos:[26:22] ;default: 5'h1 ; */ +/*description: delay cycles of cs pin by spi clock this bits are combined with + spi_cs_hold bit. Can be configured in CONF state.*/ +#define SPI_CS_HOLD_TIME 0x0000001F +#define SPI_CS_HOLD_TIME_M ((SPI_CS_HOLD_TIME_V) << (SPI_CS_HOLD_TIME_S)) +#define SPI_CS_HOLD_TIME_V 0x1F +#define SPI_CS_HOLD_TIME_S 22 +/* SPI_CS_SETUP_TIME : R/W ;bitpos:[21:17] ;default: 5'b0 ; */ +/*description: (cycles+1) of prepare phase by spi clock this bits are combined + with spi_cs_setup bit. Can be configured in CONF state.*/ +#define SPI_CS_SETUP_TIME 0x0000001F +#define SPI_CS_SETUP_TIME_M ((SPI_CS_SETUP_TIME_V) << (SPI_CS_SETUP_TIME_S)) +#define SPI_CS_SETUP_TIME_V 0x1F +#define SPI_CS_SETUP_TIME_S 17 +/* SPI_USR_DUMMY_CYCLELEN : R/W ;bitpos:[7:0] ;default: 8'd7 ; */ +/*description: The length in spi_clk cycles of dummy phase. The register value + shall be (cycle_num-1). Can be configured in CONF state.*/ +#define SPI_USR_DUMMY_CYCLELEN 0x000000FF +#define SPI_USR_DUMMY_CYCLELEN_M ((SPI_USR_DUMMY_CYCLELEN_V) << (SPI_USR_DUMMY_CYCLELEN_S)) +#define SPI_USR_DUMMY_CYCLELEN_V 0xFF +#define SPI_USR_DUMMY_CYCLELEN_S 0 + +#define SPI_USER2_REG(i) (REG_SPI_BASE(i) + 0x018) +/* SPI_USR_COMMAND_BITLEN : R/W ;bitpos:[31:28] ;default: 4'd7 ; */ +/*description: The length in bits of command phase. The register value shall + be (bit_num-1). Can be configured in CONF state.*/ +#define SPI_USR_COMMAND_BITLEN 0x0000000F +#define SPI_USR_COMMAND_BITLEN_M ((SPI_USR_COMMAND_BITLEN_V) << (SPI_USR_COMMAND_BITLEN_S)) +#define SPI_USR_COMMAND_BITLEN_V 0xF +#define SPI_USR_COMMAND_BITLEN_S 28 +/* SPI_USR_COMMAND_VALUE : R/W ;bitpos:[15:0] ;default: 16'b0 ; */ +/*description: The value of command. Can be configured in CONF state.*/ +#define SPI_USR_COMMAND_VALUE 0x0000FFFF +#define SPI_USR_COMMAND_VALUE_M ((SPI_USR_COMMAND_VALUE_V) << (SPI_USR_COMMAND_VALUE_S)) +#define SPI_USR_COMMAND_VALUE_V 0xFFFF +#define SPI_USR_COMMAND_VALUE_S 0 + +#define SPI_MS_DLEN_REG(i) (REG_SPI_BASE(i) + 0x01C) +/* SPI_MS_DATA_BITLEN : R/W ;bitpos:[17:0] ;default: 18'b0 ; */ +/*description: The value of these bits is the configured SPI transmission data + bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ +#define SPI_MS_DATA_BITLEN 0x0003FFFF +#define SPI_MS_DATA_BITLEN_M ((SPI_MS_DATA_BITLEN_V) << (SPI_MS_DATA_BITLEN_S)) +#define SPI_MS_DATA_BITLEN_V 0x3FFFF +#define SPI_MS_DATA_BITLEN_S 0 + +#define SPI_MISC_REG(i) (REG_SPI_BASE(i) + 0x020) +/* SPI_QUAD_DIN_PIN_SWAP : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: 1: spi quad input swap enable 0: spi quad input swap disable. + Can be configured in CONF state.*/ +#define SPI_QUAD_DIN_PIN_SWAP (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_M (BIT(31)) +#define SPI_QUAD_DIN_PIN_SWAP_V 0x1 +#define SPI_QUAD_DIN_PIN_SWAP_S 31 +/* SPI_CS_KEEP_ACTIVE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: spi cs line keep low when the bit is set. Can be configured in CONF state.*/ +#define SPI_CS_KEEP_ACTIVE (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_M (BIT(30)) +#define SPI_CS_KEEP_ACTIVE_V 0x1 +#define SPI_CS_KEEP_ACTIVE_S 30 +/* SPI_CK_IDLE_EDGE : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: 1: spi clk line is high when idle 0: spi clk line is low + when idle. Can be configured in CONF state.*/ +#define SPI_CK_IDLE_EDGE (BIT(29)) +#define SPI_CK_IDLE_EDGE_M (BIT(29)) +#define SPI_CK_IDLE_EDGE_V 0x1 +#define SPI_CK_IDLE_EDGE_S 29 +/* SPI_DQS_IDLE_EDGE : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: The default value of spi_dqs. Can be configured in CONF state.*/ +#define SPI_DQS_IDLE_EDGE (BIT(24)) +#define SPI_DQS_IDLE_EDGE_M (BIT(24)) +#define SPI_DQS_IDLE_EDGE_V 0x1 +#define SPI_DQS_IDLE_EDGE_S 24 +/* SPI_SLAVE_CS_POL : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: spi slave input cs polarity select. 1: inv 0: not change. Can + be configured in CONF state.*/ +#define SPI_SLAVE_CS_POL (BIT(23)) +#define SPI_SLAVE_CS_POL_M (BIT(23)) +#define SPI_SLAVE_CS_POL_V 0x1 +#define SPI_SLAVE_CS_POL_S 23 +/* SPI_CMD_DTR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: 1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including + master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/ +#define SPI_CMD_DTR_EN (BIT(19)) +#define SPI_CMD_DTR_EN_M (BIT(19)) +#define SPI_CMD_DTR_EN_V 0x1 +#define SPI_CMD_DTR_EN_S 19 +/* SPI_ADDR_DTR_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: 1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including + master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/ +#define SPI_ADDR_DTR_EN (BIT(18)) +#define SPI_ADDR_DTR_EN_M (BIT(18)) +#define SPI_ADDR_DTR_EN_V 0x1 +#define SPI_ADDR_DTR_EN_S 18 +/* SPI_DATA_DTR_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: 1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR + mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/ +#define SPI_DATA_DTR_EN (BIT(17)) +#define SPI_DATA_DTR_EN_M (BIT(17)) +#define SPI_DATA_DTR_EN_V 0x1 +#define SPI_DATA_DTR_EN_S 17 +/* SPI_CLK_DATA_DTR_EN : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1: SPI master DTR mode is applied to SPI clk data and spi_dqs. + 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.*/ +#define SPI_CLK_DATA_DTR_EN (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_M (BIT(16)) +#define SPI_CLK_DATA_DTR_EN_V 0x1 +#define SPI_CLK_DATA_DTR_EN_S 16 +/* SPI_MASTER_CS_POL : R/W ;bitpos:[12:7] ;default: 6'b0 ; */ +/*description: In the master mode the bits are the polarity of spi cs line + the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ +#define SPI_MASTER_CS_POL 0x0000003F +#define SPI_MASTER_CS_POL_M ((SPI_MASTER_CS_POL_V) << (SPI_MASTER_CS_POL_S)) +#define SPI_MASTER_CS_POL_V 0x3F +#define SPI_MASTER_CS_POL_S 7 +/* SPI_CK_DIS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: 1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/ +#define SPI_CK_DIS (BIT(6)) +#define SPI_CK_DIS_M (BIT(6)) +#define SPI_CK_DIS_V 0x1 +#define SPI_CK_DIS_S 6 +/* SPI_CS5_DIS : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to + CS$n pin. Can be configured in CONF state.*/ +#define SPI_CS5_DIS (BIT(5)) +#define SPI_CS5_DIS_M (BIT(5)) +#define SPI_CS5_DIS_V 0x1 +#define SPI_CS5_DIS_S 5 +/* SPI_CS4_DIS : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to + CS$n pin. Can be configured in CONF state.*/ +#define SPI_CS4_DIS (BIT(4)) +#define SPI_CS4_DIS_M (BIT(4)) +#define SPI_CS4_DIS_V 0x1 +#define SPI_CS4_DIS_S 4 +/* SPI_CS3_DIS : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to + CS$n pin. Can be configured in CONF state.*/ +#define SPI_CS3_DIS (BIT(3)) +#define SPI_CS3_DIS_M (BIT(3)) +#define SPI_CS3_DIS_V 0x1 +#define SPI_CS3_DIS_S 3 +/* SPI_CS2_DIS : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to + CS$n pin. Can be configured in CONF state.*/ +#define SPI_CS2_DIS (BIT(2)) +#define SPI_CS2_DIS_M (BIT(2)) +#define SPI_CS2_DIS_V 0x1 +#define SPI_CS2_DIS_S 2 +/* SPI_CS1_DIS : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to + CS$n pin. Can be configured in CONF state.*/ +#define SPI_CS1_DIS (BIT(1)) +#define SPI_CS1_DIS_M (BIT(1)) +#define SPI_CS1_DIS_V 0x1 +#define SPI_CS1_DIS_S 1 +/* SPI_CS0_DIS : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to + CS$n pin. Can be configured in CONF state.*/ +#define SPI_CS0_DIS (BIT(0)) +#define SPI_CS0_DIS_M (BIT(0)) +#define SPI_CS0_DIS_V 0x1 +#define SPI_CS0_DIS_S 0 + +#define SPI_DIN_MODE_REG(i) (REG_SPI_BASE(i) + 0x024) +/* SPI_TIMING_HCLK_ACTIVE : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: 1:enable hclk in SPI input timing module. 0: disable it. Can + be configured in CONF state.*/ +#define SPI_TIMING_HCLK_ACTIVE (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_M (BIT(16)) +#define SPI_TIMING_HCLK_ACTIVE_V 0x1 +#define SPI_TIMING_HCLK_ACTIVE_S 16 +/* SPI_DIN7_MODE : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN7_MODE 0x00000003 +#define SPI_DIN7_MODE_M ((SPI_DIN7_MODE_V) << (SPI_DIN7_MODE_S)) +#define SPI_DIN7_MODE_V 0x3 +#define SPI_DIN7_MODE_S 14 +/* SPI_DIN6_MODE : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN6_MODE 0x00000003 +#define SPI_DIN6_MODE_M ((SPI_DIN6_MODE_V) << (SPI_DIN6_MODE_S)) +#define SPI_DIN6_MODE_V 0x3 +#define SPI_DIN6_MODE_S 12 +/* SPI_DIN5_MODE : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN5_MODE 0x00000003 +#define SPI_DIN5_MODE_M ((SPI_DIN5_MODE_V) << (SPI_DIN5_MODE_S)) +#define SPI_DIN5_MODE_V 0x3 +#define SPI_DIN5_MODE_S 10 +/* SPI_DIN4_MODE : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN4_MODE 0x00000003 +#define SPI_DIN4_MODE_M ((SPI_DIN4_MODE_V) << (SPI_DIN4_MODE_S)) +#define SPI_DIN4_MODE_V 0x3 +#define SPI_DIN4_MODE_S 8 +/* SPI_DIN3_MODE : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN3_MODE 0x00000003 +#define SPI_DIN3_MODE_M ((SPI_DIN3_MODE_V) << (SPI_DIN3_MODE_S)) +#define SPI_DIN3_MODE_V 0x3 +#define SPI_DIN3_MODE_S 6 +/* SPI_DIN2_MODE : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN2_MODE 0x00000003 +#define SPI_DIN2_MODE_M ((SPI_DIN2_MODE_V) << (SPI_DIN2_MODE_S)) +#define SPI_DIN2_MODE_V 0x3 +#define SPI_DIN2_MODE_S 4 +/* SPI_DIN1_MODE : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN1_MODE 0x00000003 +#define SPI_DIN1_MODE_M ((SPI_DIN1_MODE_V) << (SPI_DIN1_MODE_S)) +#define SPI_DIN1_MODE_V 0x3 +#define SPI_DIN1_MODE_S 2 +/* SPI_DIN0_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ +#define SPI_DIN0_MODE 0x00000003 +#define SPI_DIN0_MODE_M ((SPI_DIN0_MODE_V) << (SPI_DIN0_MODE_S)) +#define SPI_DIN0_MODE_V 0x3 +#define SPI_DIN0_MODE_S 0 + +#define SPI_DIN_NUM_REG(i) (REG_SPI_BASE(i) + 0x028) +/* SPI_DIN7_NUM : R/W ;bitpos:[15:14] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN7_NUM 0x00000003 +#define SPI_DIN7_NUM_M ((SPI_DIN7_NUM_V) << (SPI_DIN7_NUM_S)) +#define SPI_DIN7_NUM_V 0x3 +#define SPI_DIN7_NUM_S 14 +/* SPI_DIN6_NUM : R/W ;bitpos:[13:12] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN6_NUM 0x00000003 +#define SPI_DIN6_NUM_M ((SPI_DIN6_NUM_V) << (SPI_DIN6_NUM_S)) +#define SPI_DIN6_NUM_V 0x3 +#define SPI_DIN6_NUM_S 12 +/* SPI_DIN5_NUM : R/W ;bitpos:[11:10] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN5_NUM 0x00000003 +#define SPI_DIN5_NUM_M ((SPI_DIN5_NUM_V) << (SPI_DIN5_NUM_S)) +#define SPI_DIN5_NUM_V 0x3 +#define SPI_DIN5_NUM_S 10 +/* SPI_DIN4_NUM : R/W ;bitpos:[9:8] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN4_NUM 0x00000003 +#define SPI_DIN4_NUM_M ((SPI_DIN4_NUM_V) << (SPI_DIN4_NUM_S)) +#define SPI_DIN4_NUM_V 0x3 +#define SPI_DIN4_NUM_S 8 +/* SPI_DIN3_NUM : R/W ;bitpos:[7:6] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN3_NUM 0x00000003 +#define SPI_DIN3_NUM_M ((SPI_DIN3_NUM_V) << (SPI_DIN3_NUM_S)) +#define SPI_DIN3_NUM_V 0x3 +#define SPI_DIN3_NUM_S 6 +/* SPI_DIN2_NUM : R/W ;bitpos:[5:4] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN2_NUM 0x00000003 +#define SPI_DIN2_NUM_M ((SPI_DIN2_NUM_V) << (SPI_DIN2_NUM_S)) +#define SPI_DIN2_NUM_V 0x3 +#define SPI_DIN2_NUM_S 4 +/* SPI_DIN1_NUM : R/W ;bitpos:[3:2] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN1_NUM 0x00000003 +#define SPI_DIN1_NUM_M ((SPI_DIN1_NUM_V) << (SPI_DIN1_NUM_S)) +#define SPI_DIN1_NUM_V 0x3 +#define SPI_DIN1_NUM_S 2 +/* SPI_DIN0_NUM : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: the input signals are delayed by SPI module clock cycles 0: + delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ +#define SPI_DIN0_NUM 0x00000003 +#define SPI_DIN0_NUM_M ((SPI_DIN0_NUM_V) << (SPI_DIN0_NUM_S)) +#define SPI_DIN0_NUM_V 0x3 +#define SPI_DIN0_NUM_S 0 + +#define SPI_DOUT_MODE_REG(i) (REG_SPI_BASE(i) + 0x02C) +/* SPI_D_DQS_MODE : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The output signal SPI_DQS is delayed by the SPI module clock + 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_D_DQS_MODE (BIT(8)) +#define SPI_D_DQS_MODE_M (BIT(8)) +#define SPI_D_DQS_MODE_V 0x1 +#define SPI_D_DQS_MODE_S 8 +/* SPI_DOUT7_MODE : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT7_MODE (BIT(7)) +#define SPI_DOUT7_MODE_M (BIT(7)) +#define SPI_DOUT7_MODE_V 0x1 +#define SPI_DOUT7_MODE_S 7 +/* SPI_DOUT6_MODE : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT6_MODE (BIT(6)) +#define SPI_DOUT6_MODE_M (BIT(6)) +#define SPI_DOUT6_MODE_V 0x1 +#define SPI_DOUT6_MODE_S 6 +/* SPI_DOUT5_MODE : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT5_MODE (BIT(5)) +#define SPI_DOUT5_MODE_M (BIT(5)) +#define SPI_DOUT5_MODE_V 0x1 +#define SPI_DOUT5_MODE_S 5 +/* SPI_DOUT4_MODE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT4_MODE (BIT(4)) +#define SPI_DOUT4_MODE_M (BIT(4)) +#define SPI_DOUT4_MODE_V 0x1 +#define SPI_DOUT4_MODE_S 4 +/* SPI_DOUT3_MODE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT3_MODE (BIT(3)) +#define SPI_DOUT3_MODE_M (BIT(3)) +#define SPI_DOUT3_MODE_V 0x1 +#define SPI_DOUT3_MODE_S 3 +/* SPI_DOUT2_MODE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT2_MODE (BIT(2)) +#define SPI_DOUT2_MODE_M (BIT(2)) +#define SPI_DOUT2_MODE_V 0x1 +#define SPI_DOUT2_MODE_S 2 +/* SPI_DOUT1_MODE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT1_MODE (BIT(1)) +#define SPI_DOUT1_MODE_M (BIT(1)) +#define SPI_DOUT1_MODE_V 0x1 +#define SPI_DOUT1_MODE_S 1 +/* SPI_DOUT0_MODE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The output signal $n is delayed by the SPI module clock 0: output + without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ +#define SPI_DOUT0_MODE (BIT(0)) +#define SPI_DOUT0_MODE_M (BIT(0)) +#define SPI_DOUT0_MODE_V 0x1 +#define SPI_DOUT0_MODE_S 0 + +#define SPI_DMA_CONF_REG(i) (REG_SPI_BASE(i) + 0x030) +/* SPI_DMA_AFIFO_RST : WO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: Set this bit to reset DMA TX AFIFO which is used to send data + out in SPI slave DMA controlled mode transfer.*/ +#define SPI_DMA_AFIFO_RST (BIT(31)) +#define SPI_DMA_AFIFO_RST_M (BIT(31)) +#define SPI_DMA_AFIFO_RST_V 0x1 +#define SPI_DMA_AFIFO_RST_S 31 +/* SPI_BUF_AFIFO_RST : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set this bit to reset BUF TX AFIFO which is used send data out + in SPI slave CPU controlled mode transfer and master mode transfer.*/ +#define SPI_BUF_AFIFO_RST (BIT(30)) +#define SPI_BUF_AFIFO_RST_M (BIT(30)) +#define SPI_BUF_AFIFO_RST_V 0x1 +#define SPI_BUF_AFIFO_RST_S 30 +/* SPI_RX_AFIFO_RST : WO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: Set this bit to reset RX AFIFO which is used to receive data + in SPI master and slave mode transfer.*/ +#define SPI_RX_AFIFO_RST (BIT(29)) +#define SPI_RX_AFIFO_RST_M (BIT(29)) +#define SPI_RX_AFIFO_RST_V 0x1 +#define SPI_RX_AFIFO_RST_S 29 +/* SPI_DMA_TX_ENA : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: Set this bit to enable SPI DMA controlled send data mode.*/ +#define SPI_DMA_TX_ENA (BIT(28)) +#define SPI_DMA_TX_ENA_M (BIT(28)) +#define SPI_DMA_TX_ENA_V 0x1 +#define SPI_DMA_TX_ENA_S 28 +/* SPI_DMA_RX_ENA : R/W ;bitpos:[27] ;default: 1'd0 ; */ +/*description: Set this bit to enable SPI DMA controlled receive data mode.*/ +#define SPI_DMA_RX_ENA (BIT(27)) +#define SPI_DMA_RX_ENA_M (BIT(27)) +#define SPI_DMA_RX_ENA_V 0x1 +#define SPI_DMA_RX_ENA_S 27 +/* SPI_RX_EOF_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: 1: spi_dma_inlink_eof is set when the number of dma pushed data + bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ +#define SPI_RX_EOF_EN (BIT(21)) +#define SPI_RX_EOF_EN_M (BIT(21)) +#define SPI_RX_EOF_EN_V 0x1 +#define SPI_RX_EOF_EN_S 21 +/* SPI_SLV_TX_SEG_TRANS_CLR_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: + spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ +#define SPI_SLV_TX_SEG_TRANS_CLR_EN (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_M (BIT(20)) +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_TX_SEG_TRANS_CLR_EN_S 20 +/* SPI_SLV_RX_SEG_TRANS_CLR_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: + spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ +#define SPI_SLV_RX_SEG_TRANS_CLR_EN (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_M (BIT(19)) +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_V 0x1 +#define SPI_SLV_RX_SEG_TRANS_CLR_EN_S 19 +/* SPI_DMA_SLV_SEG_TRANS_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ +#define SPI_DMA_SLV_SEG_TRANS_EN (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_M (BIT(18)) +#define SPI_DMA_SLV_SEG_TRANS_EN_V 0x1 +#define SPI_DMA_SLV_SEG_TRANS_EN_S 18 + +#define SPI_DMA_INT_ENA_REG(i) (REG_SPI_BASE(i) + 0x034) +/* SPI_MST_TX_AFIFO_RERR_INT_ENA : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_MST_TX_AFIFO_RERR_INT_ENA (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_ENA_M (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_ENA_V 0x1 +#define SPI_MST_TX_AFIFO_RERR_INT_ENA_S 21 +/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA_M (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA_V 0x1 +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ENA_S 20 +/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA_M (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA_V 0x1 +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ENA_S 19 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_M (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ENA_S 18 +/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA_M (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA_V 0x1 +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ENA_S 17 +/* SPI_SLV_CMD_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ +#define SPI_SLV_CMD_ERR_INT_ENA (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ENA_V 0x1 +#define SPI_SLV_CMD_ERR_INT_ENA_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_ENA_S 15 +/* SPI_SEG_MAGIC_ERR_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ +#define SPI_SEG_MAGIC_ERR_INT_ENA (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ENA_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_ENA_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_ENA_S 13 +/* SPI_TRANS_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_TRANS_DONE_INT interrupt.*/ +#define SPI_TRANS_DONE_INT_ENA (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_M (BIT(12)) +#define SPI_TRANS_DONE_INT_ENA_V 0x1 +#define SPI_TRANS_DONE_INT_ENA_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_WR_BUF_DONE_INT_ENA (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ENA_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_ENA_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_RD_BUF_DONE_INT_ENA (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ENA_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_ENA_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_WR_DMA_DONE_INT_ENA (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ENA_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_ENA_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_RD_DMA_DONE_INT_ENA (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ENA_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_ENA_S 8 +/* SPI_SLV_CMDA_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMDA interrupt.*/ +#define SPI_SLV_CMDA_INT_ENA (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_M (BIT(7)) +#define SPI_SLV_CMDA_INT_ENA_V 0x1 +#define SPI_SLV_CMDA_INT_ENA_S 7 +/* SPI_SLV_CMD9_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMD9 interrupt.*/ +#define SPI_SLV_CMD9_INT_ENA (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_M (BIT(6)) +#define SPI_SLV_CMD9_INT_ENA_V 0x1 +#define SPI_SLV_CMD9_INT_ENA_S 6 +/* SPI_SLV_CMD8_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMD8 interrupt.*/ +#define SPI_SLV_CMD8_INT_ENA (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_M (BIT(5)) +#define SPI_SLV_CMD8_INT_ENA_V 0x1 +#define SPI_SLV_CMD8_INT_ENA_S 5 +/* SPI_SLV_CMD7_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave CMD7 interrupt.*/ +#define SPI_SLV_CMD7_INT_ENA (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_M (BIT(4)) +#define SPI_SLV_CMD7_INT_ENA_V 0x1 +#define SPI_SLV_CMD7_INT_ENA_S 4 +/* SPI_SLV_EN_QPI_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave En_QPI interrupt.*/ +#define SPI_SLV_EN_QPI_INT_ENA (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ENA_V 0x1 +#define SPI_SLV_EN_QPI_INT_ENA_S 3 +/* SPI_SLV_EX_QPI_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The enable bit for SPI slave Ex_QPI interrupt.*/ +#define SPI_SLV_EX_QPI_INT_ENA (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ENA_V 0x1 +#define SPI_SLV_EX_QPI_INT_ENA_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ENA_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ENA_S 0 + +#define SPI_DMA_INT_CLR_REG(i) (REG_SPI_BASE(i) + 0x038) +/* SPI_MST_TX_AFIFO_RERR_INT_CLR : WO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_MST_TX_AFIFO_RERR_INT_CLR (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_CLR_M (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_CLR_V 0x1 +#define SPI_MST_TX_AFIFO_RERR_INT_CLR_S 21 +/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR : WO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR_M (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR_V 0x1 +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_CLR_S 20 +/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR_M (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR_V 0x1 +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_CLR_S 19 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_CLR_S 18 +/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR_M (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR_V 0x1 +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_CLR_S 17 +/* SPI_SLV_CMD_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ +#define SPI_SLV_CMD_ERR_INT_CLR (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_CLR_V 0x1 +#define SPI_SLV_CMD_ERR_INT_CLR_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_CLR_S 15 +/* SPI_SEG_MAGIC_ERR_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ +#define SPI_SEG_MAGIC_ERR_INT_CLR (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_CLR_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_CLR_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_CLR_S 13 +/* SPI_TRANS_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_TRANS_DONE_INT interrupt.*/ +#define SPI_TRANS_DONE_INT_CLR (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_M (BIT(12)) +#define SPI_TRANS_DONE_INT_CLR_V 0x1 +#define SPI_TRANS_DONE_INT_CLR_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_WR_BUF_DONE_INT_CLR (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_CLR_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_CLR_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_RD_BUF_DONE_INT_CLR (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_CLR_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_CLR_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_WR_DMA_DONE_INT_CLR (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_CLR_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_CLR_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_RD_DMA_DONE_INT_CLR (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_CLR_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_CLR_S 8 +/* SPI_SLV_CMDA_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMDA interrupt.*/ +#define SPI_SLV_CMDA_INT_CLR (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_M (BIT(7)) +#define SPI_SLV_CMDA_INT_CLR_V 0x1 +#define SPI_SLV_CMDA_INT_CLR_S 7 +/* SPI_SLV_CMD9_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD9 interrupt.*/ +#define SPI_SLV_CMD9_INT_CLR (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_M (BIT(6)) +#define SPI_SLV_CMD9_INT_CLR_V 0x1 +#define SPI_SLV_CMD9_INT_CLR_S 6 +/* SPI_SLV_CMD8_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD8 interrupt.*/ +#define SPI_SLV_CMD8_INT_CLR (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_M (BIT(5)) +#define SPI_SLV_CMD8_INT_CLR_V 0x1 +#define SPI_SLV_CMD8_INT_CLR_S 5 +/* SPI_SLV_CMD7_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave CMD7 interrupt.*/ +#define SPI_SLV_CMD7_INT_CLR (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_M (BIT(4)) +#define SPI_SLV_CMD7_INT_CLR_V 0x1 +#define SPI_SLV_CMD7_INT_CLR_S 4 +/* SPI_SLV_EN_QPI_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave En_QPI interrupt.*/ +#define SPI_SLV_EN_QPI_INT_CLR (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_CLR_V 0x1 +#define SPI_SLV_EN_QPI_INT_CLR_S 3 +/* SPI_SLV_EX_QPI_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The clear bit for SPI slave Ex_QPI interrupt.*/ +#define SPI_SLV_EX_QPI_INT_CLR (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_CLR_V 0x1 +#define SPI_SLV_EX_QPI_INT_CLR_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_CLR_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_CLR_S 0 + +#define SPI_DMA_INT_RAW_REG(i) (REG_SPI_BASE(i) + 0x03C) +/* SPI_MST_TX_AFIFO_RERR_INT_RAW : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MST_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO + underflow when SPI master sends data out in CPU/DMA controlled mode. 0: Others.*/ +#define SPI_MST_TX_AFIFO_RERR_INT_RAW (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_RAW_M (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_RAW_V 0x1 +#define SPI_MST_TX_AFIFO_RERR_INT_RAW_S 21 +/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt. 1: SPI + AFIFO underflow when SPI slave sent data out in DMA controlled mode 0: Others.*/ +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW_M (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW_V 0x1 +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_RAW_S 20 +/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt. 1: SPI + AFIFO underflow when SPI slave sent data out in CPU controlled mode 0: Others.*/ +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW_M (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW_V 0x1 +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_RAW_S 19 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: + SPI AFIFO overflow when SPI master reads data in CPU/DMA controlled mode. 0: Others.*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_M (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_RAW_S 18 +/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt. 1: + SPI AFIFO overflow when SPI slave reads data in CPU/DMA controlled mode. 0: Others.*/ +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW_M (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW_V 0x1 +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_RAW_S 17 +/* SPI_SLV_CMD_ERR_INT_RAW : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command + value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ +#define SPI_SLV_CMD_ERR_INT_RAW (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_RAW_V 0x1 +#define SPI_SLV_CMD_ERR_INT_RAW_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_RAW : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing + data address of the current SPI slave mode CPU controlled FD Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_RAW_S 15 +/* SPI_SEG_MAGIC_ERR_INT_RAW : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic + value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ +#define SPI_SEG_MAGIC_ERR_INT_RAW (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_RAW_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_RAW_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_RAW : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi + master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_RAW_S 13 +/* SPI_TRANS_DONE_INT_RAW : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode + transmission is ended. 0: others.*/ +#define SPI_TRANS_DONE_INT_RAW (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_M (BIT(12)) +#define SPI_TRANS_DONE_INT_RAW_V 0x1 +#define SPI_TRANS_DONE_INT_RAW_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_RAW : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave + mode Wr_BUF transmission is ended. 0: Others.*/ +#define SPI_SLV_WR_BUF_DONE_INT_RAW (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_RAW_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_RAW_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_RAW : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave + mode Rd_BUF transmission is ended. 0: Others.*/ +#define SPI_SLV_RD_BUF_DONE_INT_RAW (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_RAW_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_RAW_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_RAW : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave + mode Wr_DMA transmission is ended. 0: Others.*/ +#define SPI_SLV_WR_DMA_DONE_INT_RAW (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_RAW_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_RAW_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_RAW : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave + mode Rd_DMA transmission is ended. 0: Others.*/ +#define SPI_SLV_RD_DMA_DONE_INT_RAW (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_RAW_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_RAW_S 8 +/* SPI_SLV_CMDA_INT_RAW : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA + transmission is ended. 0: Others.*/ +#define SPI_SLV_CMDA_INT_RAW (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_M (BIT(7)) +#define SPI_SLV_CMDA_INT_RAW_V 0x1 +#define SPI_SLV_CMDA_INT_RAW_S 7 +/* SPI_SLV_CMD9_INT_RAW : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 + transmission is ended. 0: Others.*/ +#define SPI_SLV_CMD9_INT_RAW (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_M (BIT(6)) +#define SPI_SLV_CMD9_INT_RAW_V 0x1 +#define SPI_SLV_CMD9_INT_RAW_S 6 +/* SPI_SLV_CMD8_INT_RAW : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 + transmission is ended. 0: Others.*/ +#define SPI_SLV_CMD8_INT_RAW (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_M (BIT(5)) +#define SPI_SLV_CMD8_INT_RAW_V 0x1 +#define SPI_SLV_CMD8_INT_RAW_S 5 +/* SPI_SLV_CMD7_INT_RAW : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 + transmission is ended. 0: Others.*/ +#define SPI_SLV_CMD7_INT_RAW (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_M (BIT(4)) +#define SPI_SLV_CMD7_INT_RAW_V 0x1 +#define SPI_SLV_CMD7_INT_RAW_S 4 +/* SPI_SLV_EN_QPI_INT_RAW : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode + En_QPI transmission is ended. 0: Others.*/ +#define SPI_SLV_EN_QPI_INT_RAW (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_RAW_V 0x1 +#define SPI_SLV_EN_QPI_INT_RAW_S 3 +/* SPI_SLV_EX_QPI_INT_RAW : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode + Ex_QPI transmission is ended. 0: Others.*/ +#define SPI_SLV_EX_QPI_INT_RAW (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_RAW_V 0x1 +#define SPI_SLV_EX_QPI_INT_RAW_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: 1: The current data rate of DMA TX is smaller than that of SPI. + SPI will stop in master mode and send out all 0 in slave mode. 0: Others.*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_RAW_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_RAW : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: 1: The current data rate of DMA Rx is smaller than that of SPI + which will lose the receive data. 0: Others.*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_RAW_S 0 + +#define SPI_DMA_INT_ST_REG(i) (REG_SPI_BASE(i) + 0x040) +/* SPI_MST_TX_AFIFO_RERR_INT_ST : RO ;bitpos:[21] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_MST_TX_AFIFO_RERR_INT_ST (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_ST_M (BIT(21)) +#define SPI_MST_TX_AFIFO_RERR_INT_ST_V 0x1 +#define SPI_MST_TX_AFIFO_RERR_INT_ST_S 21 +/* SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST : RO ;bitpos:[20] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST_M (BIT(20)) +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST_V 0x1 +#define SPI_SLV_DMA_TX_AFIFO_RERR_INT_ST_S 20 +/* SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST_M (BIT(19)) +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST_V 0x1 +#define SPI_SLV_BUF_TX_AFIFO_RERR_INT_ST_S 19 +/* SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_M (BIT(18)) +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_V 0x1 +#define SPI_MST_RX_AFIFO_WFULL_ERR_INT_ST_S 18 +/* SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST_M (BIT(17)) +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST_V 0x1 +#define SPI_SLV_RX_AFIFO_WFULL_ERR_INT_ST_S 17 +/* SPI_SLV_CMD_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ +#define SPI_SLV_CMD_ERR_INT_ST (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_M (BIT(16)) +#define SPI_SLV_CMD_ERR_INT_ST_V 0x1 +#define SPI_SLV_CMD_ERR_INT_ST_S 16 +/* SPI_SLV_BUF_ADDR_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ +#define SPI_SLV_BUF_ADDR_ERR_INT_ST (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_M (BIT(15)) +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_V 0x1 +#define SPI_SLV_BUF_ADDR_ERR_INT_ST_S 15 +/* SPI_SEG_MAGIC_ERR_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ +#define SPI_SEG_MAGIC_ERR_INT_ST (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_M (BIT(14)) +#define SPI_SEG_MAGIC_ERR_INT_ST_V 0x1 +#define SPI_SEG_MAGIC_ERR_INT_ST_S 14 +/* SPI_DMA_SEG_TRANS_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ +#define SPI_DMA_SEG_TRANS_DONE_INT_ST (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_M (BIT(13)) +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_V 0x1 +#define SPI_DMA_SEG_TRANS_DONE_INT_ST_S 13 +/* SPI_TRANS_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: The status bit for SPI_TRANS_DONE_INT interrupt.*/ +#define SPI_TRANS_DONE_INT_ST (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_M (BIT(12)) +#define SPI_TRANS_DONE_INT_ST_V 0x1 +#define SPI_TRANS_DONE_INT_ST_S 12 +/* SPI_SLV_WR_BUF_DONE_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_WR_BUF_DONE_INT_ST (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_M (BIT(11)) +#define SPI_SLV_WR_BUF_DONE_INT_ST_V 0x1 +#define SPI_SLV_WR_BUF_DONE_INT_ST_S 11 +/* SPI_SLV_RD_BUF_DONE_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ +#define SPI_SLV_RD_BUF_DONE_INT_ST (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_M (BIT(10)) +#define SPI_SLV_RD_BUF_DONE_INT_ST_V 0x1 +#define SPI_SLV_RD_BUF_DONE_INT_ST_S 10 +/* SPI_SLV_WR_DMA_DONE_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_WR_DMA_DONE_INT_ST (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_M (BIT(9)) +#define SPI_SLV_WR_DMA_DONE_INT_ST_V 0x1 +#define SPI_SLV_WR_DMA_DONE_INT_ST_S 9 +/* SPI_SLV_RD_DMA_DONE_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ +#define SPI_SLV_RD_DMA_DONE_INT_ST (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_M (BIT(8)) +#define SPI_SLV_RD_DMA_DONE_INT_ST_V 0x1 +#define SPI_SLV_RD_DMA_DONE_INT_ST_S 8 +/* SPI_SLV_CMDA_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMDA interrupt.*/ +#define SPI_SLV_CMDA_INT_ST (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_M (BIT(7)) +#define SPI_SLV_CMDA_INT_ST_V 0x1 +#define SPI_SLV_CMDA_INT_ST_S 7 +/* SPI_SLV_CMD9_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMD9 interrupt.*/ +#define SPI_SLV_CMD9_INT_ST (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_M (BIT(6)) +#define SPI_SLV_CMD9_INT_ST_V 0x1 +#define SPI_SLV_CMD9_INT_ST_S 6 +/* SPI_SLV_CMD8_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMD8 interrupt.*/ +#define SPI_SLV_CMD8_INT_ST (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_M (BIT(5)) +#define SPI_SLV_CMD8_INT_ST_V 0x1 +#define SPI_SLV_CMD8_INT_ST_S 5 +/* SPI_SLV_CMD7_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave CMD7 interrupt.*/ +#define SPI_SLV_CMD7_INT_ST (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_M (BIT(4)) +#define SPI_SLV_CMD7_INT_ST_V 0x1 +#define SPI_SLV_CMD7_INT_ST_S 4 +/* SPI_SLV_EN_QPI_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave En_QPI interrupt.*/ +#define SPI_SLV_EN_QPI_INT_ST (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_M (BIT(3)) +#define SPI_SLV_EN_QPI_INT_ST_V 0x1 +#define SPI_SLV_EN_QPI_INT_ST_S 3 +/* SPI_SLV_EX_QPI_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: The status bit for SPI slave Ex_QPI interrupt.*/ +#define SPI_SLV_EX_QPI_INT_ST (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_M (BIT(2)) +#define SPI_SLV_EX_QPI_INT_ST_V 0x1 +#define SPI_SLV_EX_QPI_INT_ST_S 2 +/* SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_M (BIT(1)) +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_V 0x1 +#define SPI_DMA_OUTFIFO_EMPTY_ERR_INT_ST_S 1 +/* SPI_DMA_INFIFO_FULL_ERR_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_M (BIT(0)) +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_V 0x1 +#define SPI_DMA_INFIFO_FULL_ERR_INT_ST_S 0 + +#define SPI_W0_REG(i) (REG_SPI_BASE(i) + 0x098) +/* SPI_BUF0 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF0 0xFFFFFFFF +#define SPI_BUF0_M ((SPI_BUF0_V) << (SPI_BUF0_S)) +#define SPI_BUF0_V 0xFFFFFFFF +#define SPI_BUF0_S 0 + +#define SPI_W1_REG(i) (REG_SPI_BASE(i) + 0x09C) +/* SPI_BUF1 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF1 0xFFFFFFFF +#define SPI_BUF1_M ((SPI_BUF1_V) << (SPI_BUF1_S)) +#define SPI_BUF1_V 0xFFFFFFFF +#define SPI_BUF1_S 0 + +#define SPI_W2_REG(i) (REG_SPI_BASE(i) + 0x0A0) +/* SPI_BUF2 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF2 0xFFFFFFFF +#define SPI_BUF2_M ((SPI_BUF2_V) << (SPI_BUF2_S)) +#define SPI_BUF2_V 0xFFFFFFFF +#define SPI_BUF2_S 0 + +#define SPI_W3_REG(i) (REG_SPI_BASE(i) + 0x0A4) +/* SPI_BUF3 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF3 0xFFFFFFFF +#define SPI_BUF3_M ((SPI_BUF3_V) << (SPI_BUF3_S)) +#define SPI_BUF3_V 0xFFFFFFFF +#define SPI_BUF3_S 0 + +#define SPI_W4_REG(i) (REG_SPI_BASE(i) + 0x0A8) +/* SPI_BUF4 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF4 0xFFFFFFFF +#define SPI_BUF4_M ((SPI_BUF4_V) << (SPI_BUF4_S)) +#define SPI_BUF4_V 0xFFFFFFFF +#define SPI_BUF4_S 0 + +#define SPI_W5_REG(i) (REG_SPI_BASE(i) + 0x0AC) +/* SPI_BUF5 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF5 0xFFFFFFFF +#define SPI_BUF5_M ((SPI_BUF5_V) << (SPI_BUF5_S)) +#define SPI_BUF5_V 0xFFFFFFFF +#define SPI_BUF5_S 0 + +#define SPI_W6_REG(i) (REG_SPI_BASE(i) + 0x0B0) +/* SPI_BUF6 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF6 0xFFFFFFFF +#define SPI_BUF6_M ((SPI_BUF6_V) << (SPI_BUF6_S)) +#define SPI_BUF6_V 0xFFFFFFFF +#define SPI_BUF6_S 0 + +#define SPI_W7_REG(i) (REG_SPI_BASE(i) + 0x0B4) +/* SPI_BUF7 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF7 0xFFFFFFFF +#define SPI_BUF7_M ((SPI_BUF7_V) << (SPI_BUF7_S)) +#define SPI_BUF7_V 0xFFFFFFFF +#define SPI_BUF7_S 0 + +#define SPI_W8_REG(i) (REG_SPI_BASE(i) + 0x0B8) +/* SPI_BUF8 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF8 0xFFFFFFFF +#define SPI_BUF8_M ((SPI_BUF8_V) << (SPI_BUF8_S)) +#define SPI_BUF8_V 0xFFFFFFFF +#define SPI_BUF8_S 0 + +#define SPI_W9_REG(i) (REG_SPI_BASE(i) + 0x0BC) +/* SPI_BUF9 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF9 0xFFFFFFFF +#define SPI_BUF9_M ((SPI_BUF9_V) << (SPI_BUF9_S)) +#define SPI_BUF9_V 0xFFFFFFFF +#define SPI_BUF9_S 0 + +#define SPI_W10_REG(i) (REG_SPI_BASE(i) + 0x0C0) +/* SPI_BUF10 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF10 0xFFFFFFFF +#define SPI_BUF10_M ((SPI_BUF10_V) << (SPI_BUF10_S)) +#define SPI_BUF10_V 0xFFFFFFFF +#define SPI_BUF10_S 0 + +#define SPI_W11_REG(i) (REG_SPI_BASE(i) + 0x0C4) +/* SPI_BUF11 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF11 0xFFFFFFFF +#define SPI_BUF11_M ((SPI_BUF11_V) << (SPI_BUF11_S)) +#define SPI_BUF11_V 0xFFFFFFFF +#define SPI_BUF11_S 0 + +#define SPI_W12_REG(i) (REG_SPI_BASE(i) + 0x0C8) +/* SPI_BUF12 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF12 0xFFFFFFFF +#define SPI_BUF12_M ((SPI_BUF12_V) << (SPI_BUF12_S)) +#define SPI_BUF12_V 0xFFFFFFFF +#define SPI_BUF12_S 0 + +#define SPI_W13_REG(i) (REG_SPI_BASE(i) + 0x0CC) +/* SPI_BUF13 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF13 0xFFFFFFFF +#define SPI_BUF13_M ((SPI_BUF13_V) << (SPI_BUF13_S)) +#define SPI_BUF13_V 0xFFFFFFFF +#define SPI_BUF13_S 0 + +#define SPI_W14_REG(i) (REG_SPI_BASE(i) + 0x0D0) +/* SPI_BUF14 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF14 0xFFFFFFFF +#define SPI_BUF14_M ((SPI_BUF14_V) << (SPI_BUF14_S)) +#define SPI_BUF14_V 0xFFFFFFFF +#define SPI_BUF14_S 0 + +#define SPI_W15_REG(i) (REG_SPI_BASE(i) + 0x0D4) +/* SPI_BUF15 : SRW ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: data buffer*/ +#define SPI_BUF15 0xFFFFFFFF +#define SPI_BUF15_M ((SPI_BUF15_V) << (SPI_BUF15_S)) +#define SPI_BUF15_V 0xFFFFFFFF +#define SPI_BUF15_S 0 + +#define SPI_SLAVE_REG(i) (REG_SPI_BASE(i) + 0x0E0) +/* SPI_USR_CONF : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: 1: Enable the DMA CONF phase of current seg-trans operation + which means seg-trans will start. 0: This is not seg-trans mode.*/ +#define SPI_USR_CONF (BIT(28)) +#define SPI_USR_CONF_M (BIT(28)) +#define SPI_USR_CONF_V 0x1 +#define SPI_USR_CONF_S 28 +/* SPI_SOFT_RESET : WO ;bitpos:[27] ;default: 1'b0 ; */ +/*description: Software reset enable reset the spi clock line cs line and data + lines. Can be configured in CONF state.*/ +#define SPI_SOFT_RESET (BIT(27)) +#define SPI_SOFT_RESET_M (BIT(27)) +#define SPI_SOFT_RESET_V 0x1 +#define SPI_SOFT_RESET_S 27 +/* SPI_SLAVE_MODE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: Set SPI work mode. 1: slave mode 0: master mode.*/ +#define SPI_SLAVE_MODE (BIT(26)) +#define SPI_SLAVE_MODE_M (BIT(26)) +#define SPI_SLAVE_MODE_V 0x1 +#define SPI_SLAVE_MODE_S 26 +/* SPI_DMA_SEG_MAGIC_VALUE : R/W ;bitpos:[25:22] ;default: 4'd10 ; */ +/*description: The magic value of BM table in master DMA seg-trans.*/ +#define SPI_DMA_SEG_MAGIC_VALUE 0x0000000F +#define SPI_DMA_SEG_MAGIC_VALUE_M ((SPI_DMA_SEG_MAGIC_VALUE_V) << (SPI_DMA_SEG_MAGIC_VALUE_S)) +#define SPI_DMA_SEG_MAGIC_VALUE_V 0xF +#define SPI_DMA_SEG_MAGIC_VALUE_S 22 +/* SPI_SLV_WRBUF_BITLEN_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in CPU controlled mode(Wr_BUF). 0: others*/ +#define SPI_SLV_WRBUF_BITLEN_EN (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_M (BIT(11)) +#define SPI_SLV_WRBUF_BITLEN_EN_V 0x1 +#define SPI_SLV_WRBUF_BITLEN_EN_S 11 +/* SPI_SLV_RDBUF_BITLEN_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in CPU controlled mode(Rd_BUF). 0: others*/ +#define SPI_SLV_RDBUF_BITLEN_EN (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_M (BIT(10)) +#define SPI_SLV_RDBUF_BITLEN_EN_V 0x1 +#define SPI_SLV_RDBUF_BITLEN_EN_S 10 +/* SPI_SLV_WRDMA_BITLEN_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave + data length in DMA controlled mode(Wr_DMA). 0: others*/ +#define SPI_SLV_WRDMA_BITLEN_EN (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_M (BIT(9)) +#define SPI_SLV_WRDMA_BITLEN_EN_V 0x1 +#define SPI_SLV_WRDMA_BITLEN_EN_S 9 +/* SPI_SLV_RDDMA_BITLEN_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave + data length in DMA controlled mode(Rd_DMA). 0: others*/ +#define SPI_SLV_RDDMA_BITLEN_EN (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_M (BIT(8)) +#define SPI_SLV_RDDMA_BITLEN_EN_V 0x1 +#define SPI_SLV_RDDMA_BITLEN_EN_S 8 +/* SPI_RSCK_DATA_OUT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: It saves half a cycle when tsck is the same as rsck. 1: output + data at rsck posedge 0: output data at tsck posedge*/ +#define SPI_RSCK_DATA_OUT (BIT(3)) +#define SPI_RSCK_DATA_OUT_M (BIT(3)) +#define SPI_RSCK_DATA_OUT_V 0x1 +#define SPI_RSCK_DATA_OUT_S 3 +/* SPI_CLK_MODE_13 : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: {CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output + data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ +#define SPI_CLK_MODE_13 (BIT(2)) +#define SPI_CLK_MODE_13_M (BIT(2)) +#define SPI_CLK_MODE_13_V 0x1 +#define SPI_CLK_MODE_13_S 2 +/* SPI_CLK_MODE : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: SPI clock mode bits. 0: SPI clock is off when CS inactive 1: + SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ +#define SPI_CLK_MODE 0x00000003 +#define SPI_CLK_MODE_M ((SPI_CLK_MODE_V) << (SPI_CLK_MODE_S)) +#define SPI_CLK_MODE_V 0x3 +#define SPI_CLK_MODE_S 0 + +#define SPI_SLAVE1_REG(i) (REG_SPI_BASE(i) + 0x0E4) +/* SPI_SLV_LAST_ADDR : SRW ;bitpos:[31:26] ;default: 6'd0 ; */ +/*description: In the slave mode it is the value of address.*/ +#define SPI_SLV_LAST_ADDR 0x0000003F +#define SPI_SLV_LAST_ADDR_M ((SPI_SLV_LAST_ADDR_V) << (SPI_SLV_LAST_ADDR_S)) +#define SPI_SLV_LAST_ADDR_V 0x3F +#define SPI_SLV_LAST_ADDR_S 26 +/* SPI_SLV_LAST_COMMAND : SRW ;bitpos:[25:18] ;default: 8'b0 ; */ +/*description: In the slave mode it is the value of command.*/ +#define SPI_SLV_LAST_COMMAND 0x000000FF +#define SPI_SLV_LAST_COMMAND_M ((SPI_SLV_LAST_COMMAND_V) << (SPI_SLV_LAST_COMMAND_S)) +#define SPI_SLV_LAST_COMMAND_V 0xFF +#define SPI_SLV_LAST_COMMAND_S 18 +/* SPI_SLV_DATA_BITLEN : SRW ;bitpos:[17:0] ;default: 18'd0 ; */ +/*description: The transferred data bit length in SPI slave FD and HD mode.*/ +#define SPI_SLV_DATA_BITLEN 0x0003FFFF +#define SPI_SLV_DATA_BITLEN_M ((SPI_SLV_DATA_BITLEN_V) << (SPI_SLV_DATA_BITLEN_S)) +#define SPI_SLV_DATA_BITLEN_V 0x3FFFF +#define SPI_SLV_DATA_BITLEN_S 0 + +#define SPI_CLK_GATE_REG(i) (REG_SPI_BASE(i) + 0x0E8) +/* SPI_MST_CLK_SEL : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: This bit is used to select SPI module clock source in master + mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ +#define SPI_MST_CLK_SEL (BIT(2)) +#define SPI_MST_CLK_SEL_M (BIT(2)) +#define SPI_MST_CLK_SEL_V 0x1 +#define SPI_MST_CLK_SEL_S 2 +/* SPI_MST_CLK_ACTIVE : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: Set this bit to power on the SPI module clock.*/ +#define SPI_MST_CLK_ACTIVE (BIT(1)) +#define SPI_MST_CLK_ACTIVE_M (BIT(1)) +#define SPI_MST_CLK_ACTIVE_V 0x1 +#define SPI_MST_CLK_ACTIVE_S 1 +/* SPI_CLK_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: Set this bit to enable clk gate*/ +#define SPI_CLK_EN (BIT(0)) +#define SPI_CLK_EN_M (BIT(0)) +#define SPI_CLK_EN_V 0x1 +#define SPI_CLK_EN_S 0 + +#define SPI_DATE_REG(i) (REG_SPI_BASE(i) + 0x0F0) +/* SPI_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003110 ; */ +/*description: SPI register version.*/ +#define SPI_DATE 0x0FFFFFFF +#define SPI_DATE_M ((SPI_DATE_V) << (SPI_DATE_S)) +#define SPI_DATE_V 0xFFFFFFF +#define SPI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/spi_struct.h b/components/soc/soc/esp32s3/include/soc/spi_struct.h new file mode 100644 index 000000000..19731ff8f --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/spi_struct.h @@ -0,0 +1,398 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t conf_bitlen: 18; /*Define the APB cycles of SPI_CONF state. Can be configured in CONF state.*/ + uint32_t reserved18: 5; /*reserved*/ + uint32_t update: 1; /*Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain which is only used in SPI master mode.*/ + uint32_t usr: 1; /*User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.*/ + uint32_t reserved25: 7; /*reserved*/ + }; + uint32_t val; + } cmd; + uint32_t addr; /*Address to slave. Can be configured in CONF state.*/ + union { + struct { + uint32_t reserved0: 3; /*reserved*/ + uint32_t dummy_out: 1; /*In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.*/ + uint32_t reserved4: 1; /*reserved*/ + uint32_t faddr_dual: 1; /*Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t faddr_quad: 1; /*Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t faddr_oct: 1; /*Apply 8 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_dual: 1; /*Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_quad: 1; /*Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t fcmd_oct: 1; /*Apply 8 signals during command phase 1:enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved11: 3; /*reserved*/ + uint32_t fread_dual: 1; /*In the read operations read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t fread_quad: 1; /*In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t fread_oct: 1; /*In the read operations read-data phase apply 8 signals. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved17: 1; /*reserved*/ + uint32_t q_pol: 1; /*The bit is used to set MISO line polarity 1: high 0 low. Can be configured in CONF state.*/ + uint32_t d_pol: 1; /*The bit is used to set MOSI line polarity 1: high 0 low. Can be configured in CONF state.*/ + uint32_t hold_pol: 1; /*SPI_HOLD output value when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/ + uint32_t wp_pol: 1; /*Write protect signal output when SPI is idle. 1: output high 0: output low. Can be configured in CONF state.*/ + uint32_t reserved22: 3; /*reserved*/ + uint32_t rd_bit_order: 1; /*In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.*/ + uint32_t wr_bit_order: 1; /*In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.*/ + uint32_t reserved27: 5; /*reserved*/ + }; + uint32_t val; + } ctrl; + union { + struct { + uint32_t clkcnt_l: 6; /*In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.*/ + uint32_t clkcnt_h: 6; /*In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.*/ + uint32_t clkcnt_n: 6; /*In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.*/ + uint32_t clkdiv_pre: 13; /*In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.*/ + uint32_t clk_equ_sysclk: 1; /*In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.*/ + }; + uint32_t val; + } clock; + union { + struct { + uint32_t doutdin: 1; /*Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved1: 2; /*reserved*/ + uint32_t qpi_mode: 1; /*Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.*/ + uint32_t opi_mode: 1; /*Just for master mode. 1: spi controller is in OPI mode (all in 8-b-m). 0: others. Can be configured in CONF state.*/ + uint32_t tsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.*/ + uint32_t cs_hold: 1; /*spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t cs_setup: 1; /*spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t rsck_i_edge: 1; /*In the slave mode this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.*/ + uint32_t ck_out_edge: 1; /*the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.*/ + uint32_t reserved10: 2; /*reserved*/ + uint32_t fwrite_dual: 1; /*In the write operations read-data phase apply 2 signals. Can be configured in CONF state.*/ + uint32_t fwrite_quad: 1; /*In the write operations read-data phase apply 4 signals. Can be configured in CONF state.*/ + uint32_t fwrite_oct: 1; /*In the write operations read-data phase apply 8 signals. Can be configured in CONF state.*/ + uint32_t usr_conf_nxt: 1; /*1: Enable the DMA CONF phase of next seg-trans operation which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.*/ + uint32_t reserved16: 1; /*reserved*/ + uint32_t sio: 1; /*Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t reserved18: 6; /*reserved*/ + uint32_t usr_miso_highpart: 1; /*read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t usr_mosi_highpart: 1; /*write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.*/ + uint32_t usr_dummy_idle: 1; /*spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.*/ + uint32_t usr_mosi: 1; /*This bit enable the write-data phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_miso: 1; /*This bit enable the read-data phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_dummy: 1; /*This bit enable the dummy phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_addr: 1; /*This bit enable the address phase of an operation. Can be configured in CONF state.*/ + uint32_t usr_command: 1; /*This bit enable the command phase of an operation. Can be configured in CONF state.*/ + }; + uint32_t val; + } user; + union { + struct { + uint32_t usr_dummy_cyclelen: 8; /*The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.*/ + uint32_t reserved8: 9; /*reserved*/ + uint32_t cs_setup_time: 5; /*(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.*/ + uint32_t cs_hold_time: 5; /*delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.*/ + uint32_t usr_addr_bitlen: 5; /*The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + }; + uint32_t val; + } user1; + union { + struct { + uint32_t usr_command_value: 16; /*The value of command. Can be configured in CONF state.*/ + uint32_t reserved16: 12; /*reserved*/ + uint32_t usr_command_bitlen: 4; /*The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + }; + uint32_t val; + } user2; + union { + struct { + uint32_t ms_data_bitlen: 18; /*The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.*/ + uint32_t reserved18: 14; /*reserved*/ + }; + uint32_t val; + } ms_dlen; + union { + struct { + uint32_t cs0_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs1_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs2_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs3_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs4_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t cs5_dis: 1; /*SPI CS$n pin enable 1: disable CS$n 0: spi_cs$n signal is from/to CS$n pin. Can be configured in CONF state.*/ + uint32_t ck_dis: 1; /*1: spi clk out disable 0: spi clk out enable. Can be configured in CONF state.*/ + uint32_t master_cs_pol: 6; /*In the master mode the bits are the polarity of spi cs line the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.*/ + uint32_t reserved13: 3; /*reserved*/ + uint32_t clk_data_dtr_en: 1; /*1: SPI master DTR mode is applied to SPI clk data and spi_dqs. 0: SPI master DTR mode is only applied to spi_dqs. This bit should be used with bit 17/18/19.*/ + uint32_t data_dtr_en: 1; /*1: SPI clk and data of SPI_DOUT and SPI_DIN state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_DOUT and SPI_DIN state are in STR mode. Can be configured in CONF state.*/ + uint32_t addr_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_ADDR state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_ADDR state are in STR mode. Can be configured in CONF state.*/ + uint32_t cmd_dtr_en: 1; /*1: SPI clk and data of SPI_SEND_CMD state are in DTR mode including master 1/2/4/8-bm. 0: SPI clk and data of SPI_SEND_CMD state are in STR mode. Can be configured in CONF state.*/ + uint32_t reserved20: 3; /*reserved*/ + uint32_t slave_cs_pol: 1; /*spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.*/ + uint32_t dqs_idle_edge: 1; /*The default value of spi_dqs. Can be configured in CONF state.*/ + uint32_t reserved25: 4; /*reserved*/ + uint32_t ck_idle_edge: 1; /*1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.*/ + uint32_t cs_keep_active: 1; /*spi cs line keep low when the bit is set. Can be configured in CONF state.*/ + uint32_t quad_din_pin_swap: 1; /*1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.*/ + }; + uint32_t val; + } misc; + union { + struct { + uint32_t din0_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din1_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din2_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din3_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din4_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din5_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din6_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t din7_mode: 2; /*the input signals are delayed by SPI module clock cycles 0: input without delayed 1: input with the posedge of clk_apb 2 input with the negedge of clk_apb 3: input with the spi_clk. Can be configured in CONF state.*/ + uint32_t timing_hclk_active: 1; /*1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.*/ + uint32_t reserved17: 15; /*reserved*/ + }; + uint32_t val; + } din_mode; + union { + struct { + uint32_t din0_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t din1_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t din2_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t din3_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t din4_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t din5_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t din6_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t din7_num: 2; /*the input signals are delayed by SPI module clock cycles 0: delayed by 1 cycle 1: delayed by 2 cycles ... Can be configured in CONF state.*/ + uint32_t reserved16: 16; /*reserved*/ + }; + uint32_t val; + } din_num; + union { + struct { + uint32_t dout0_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout1_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout2_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout3_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout4_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout5_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout6_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t dout7_mode: 1; /*The output signal $n is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t d_dqs_mode: 1; /*The output signal SPI_DQS is delayed by the SPI module clock 0: output without delayed 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.*/ + uint32_t reserved9: 23; /*reserved*/ + }; + uint32_t val; + } dout_mode; + union { + struct { + uint32_t reserved0: 18; /*reserved*/ + uint32_t dma_seg_trans_en: 1; /*Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.*/ + uint32_t rx_seg_trans_clr_en: 1; /*1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.*/ + uint32_t tx_seg_trans_clr_en: 1; /*1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.*/ + uint32_t rx_eof_en: 1; /*1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.*/ + uint32_t reserved22: 5; /*reserved*/ + uint32_t dma_rx_ena: 1; /*Set this bit to enable SPI DMA controlled receive data mode.*/ + uint32_t dma_tx_ena: 1; /*Set this bit to enable SPI DMA controlled send data mode.*/ + uint32_t rx_afifo_rst: 1; /*Set this bit to reset RX AFIFO which is used to receive data in SPI master and slave mode transfer.*/ + uint32_t buf_afifo_rst: 1; /*Set this bit to reset BUF TX AFIFO which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.*/ + uint32_t dma_afifo_rst: 1; /*Set this bit to reset DMA TX AFIFO which is used to send data out in SPI slave DMA controlled mode transfer.*/ + }; + uint32_t val; + } dma_conf; + union { + struct { + uint32_t infifo_full_err: 1; /*The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err: 1; /*The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi: 1; /*The enable bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi: 1; /*The enable bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7: 1; /*The enable bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8: 1; /*The enable bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9: 1; /*The enable bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda: 1; /*The enable bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done: 1; /*The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done: 1; /*The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done: 1; /*The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done: 1; /*The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done: 1; /*The enable bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done: 1; /*The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err: 1; /*The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err: 1; /*The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err: 1; /*The enable bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t rx_afifo_wfull_err: 1; /*The enable bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ + uint32_t mst_rx_afifo_wfull_err: 1; /*The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ + uint32_t buf_tx_afifo_rerr: 1; /*The enable bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ + uint32_t dma_tx_afifo_rerr: 1; /*The enable bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ + uint32_t mst_tx_afifo_rerr: 1; /*The enable bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ + uint32_t reserved22: 10; /*reserved*/ + }; + uint32_t val; + } dma_int_ena; + union { + struct { + uint32_t infifo_full_err: 1; /*The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err: 1; /*The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi: 1; /*The clear bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi: 1; /*The clear bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7: 1; /*The clear bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8: 1; /*The clear bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9: 1; /*The clear bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda: 1; /*The clear bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done: 1; /*The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done: 1; /*The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done: 1; /*The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done: 1; /*The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done: 1; /*The clear bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done: 1; /*The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err: 1; /*The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err: 1; /*The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err: 1; /*The clear bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t rx_afifo_wfull_err: 1; /*The clear bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ + uint32_t mst_rx_afifo_wfull_err: 1; /*The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ + uint32_t buf_tx_afifo_rerr: 1; /*The clear bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ + uint32_t dma_tx_afifo_rerr: 1; /*The clear bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ + uint32_t mst_tx_afifo_rerr: 1; /*The clear bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ + uint32_t reserved22: 10; /*reserved*/ + }; + uint32_t val; + } dma_int_clr; + union { + struct { + uint32_t infifo_full_err: 1; /*1: The current data rate of DMA Rx is smaller than that of SPI which will lose the receive data. 0: Others.*/ + uint32_t outfifo_empty_err: 1; /*1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.*/ + uint32_t ex_qpi: 1; /*The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.*/ + uint32_t en_qpi: 1; /*The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.*/ + uint32_t cmd7: 1; /*The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.*/ + uint32_t cmd8: 1; /*The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.*/ + uint32_t cmd9: 1; /*The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.*/ + uint32_t cmda: 1; /*The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.*/ + uint32_t rd_dma_done: 1; /*The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.*/ + uint32_t wr_dma_done: 1; /*The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.*/ + uint32_t rd_buf_done: 1; /*The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.*/ + uint32_t wr_buf_done: 1; /*The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.*/ + uint32_t trans_done: 1; /*The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.*/ + uint32_t dma_seg_trans_done: 1; /*The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.*/ + uint32_t seg_magic_err: 1; /*The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.*/ + uint32_t buf_addr_err: 1; /*The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.*/ + uint32_t cmd_err: 1; /*The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.*/ + uint32_t rx_afifo_wfull_err: 1; /*The raw bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt. 1: SPI AFIFO overflow when SPI slave reads data in CPU/DMA controlled mode. 0: Others.*/ + uint32_t mst_rx_afifo_wfull_err: 1; /*The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: SPI AFIFO overflow when SPI master reads data in CPU/DMA controlled mode. 0: Others.*/ + uint32_t buf_tx_afifo_rerr: 1; /*The raw bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI slave sent data out in CPU controlled mode 0: Others.*/ + uint32_t dma_tx_afifo_rerr: 1; /*The raw bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI slave sent data out in DMA controlled mode 0: Others.*/ + uint32_t mst_tx_afifo_rerr: 1; /*The raw bit for SPI_MST_TX_AFIFO_RERR_INT interrupt. 1: SPI AFIFO underflow when SPI master sends data out in CPU/DMA controlled mode. 0: Others.*/ + uint32_t reserved22: 10; /*SPI interrupt raw register. Can be configured in CONF state.*/ + }; + uint32_t val; + } dma_int_raw; + union { + struct { + uint32_t infifo_full_err: 1; /*The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.*/ + uint32_t outfifo_empty_err: 1; /*The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.*/ + uint32_t ex_qpi: 1; /*The status bit for SPI slave Ex_QPI interrupt.*/ + uint32_t en_qpi: 1; /*The status bit for SPI slave En_QPI interrupt.*/ + uint32_t cmd7: 1; /*The status bit for SPI slave CMD7 interrupt.*/ + uint32_t cmd8: 1; /*The status bit for SPI slave CMD8 interrupt.*/ + uint32_t cmd9: 1; /*The status bit for SPI slave CMD9 interrupt.*/ + uint32_t cmda: 1; /*The status bit for SPI slave CMDA interrupt.*/ + uint32_t rd_dma_done: 1; /*The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.*/ + uint32_t wr_dma_done: 1; /*The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.*/ + uint32_t rd_buf_done: 1; /*The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.*/ + uint32_t wr_buf_done: 1; /*The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.*/ + uint32_t trans_done: 1; /*The status bit for SPI_TRANS_DONE_INT interrupt.*/ + uint32_t dma_seg_trans_done: 1; /*The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.*/ + uint32_t seg_magic_err: 1; /*The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.*/ + uint32_t buf_addr_err: 1; /*The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.*/ + uint32_t cmd_err: 1; /*The status bit for SPI_SLV_CMD_ERR_INT interrupt.*/ + uint32_t rx_afifo_wfull_err: 1; /*The status bit for SPI_SLV_RX_AFIFO_WFULL_ERR_INT interrupt*/ + uint32_t mst_rx_afifo_wfull_err: 1; /*The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt*/ + uint32_t buf_tx_afifo_rerr: 1; /*The status bit for SPI_SLV_BUF_TX_AFIFO_RERR_INT interrupt*/ + uint32_t dma_tx_afifo_rerr: 1; /*The status bit for SPI_SLV_DMA_TX_AFIFO_RERR_INT interrupt*/ + uint32_t mst_tx_afifo_rerr: 1; /*The status bit for SPI_MST_TX_AFIFO_RERR_INT interrupt*/ + uint32_t reserved22: 10; /*reserved*/ + }; + uint32_t val; + } dma_int_st; + uint32_t reserved_44; + uint32_t reserved_48; + uint32_t reserved_4c; + uint32_t reserved_50; + uint32_t reserved_54; + uint32_t reserved_58; + uint32_t reserved_5c; + uint32_t reserved_60; + uint32_t reserved_64; + uint32_t reserved_68; + uint32_t reserved_6c; + uint32_t reserved_70; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t data_buf[18]; /*data buffer*/ + uint32_t reserved_d8; + uint32_t reserved_dc; + union { + struct { + uint32_t clk_mode: 2; /*SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.*/ + uint32_t clk_mode_13: 1; /*{CPOL CPHA} 1: support spi clk mode 1 and 3 first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2 first edge output data B[1]/B[6].*/ + uint32_t rsck_data_out: 1; /*It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge*/ + uint32_t reserved4: 4; /*reserved*/ + uint32_t rddma_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others*/ + uint32_t wrdma_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others*/ + uint32_t rdbuf_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others*/ + uint32_t wrbuf_bitlen_en: 1; /*1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others*/ + uint32_t reserved12: 10; /*reserved*/ + uint32_t dma_seg_magic_value: 4; /*The magic value of BM table in master DMA seg-trans.*/ + uint32_t slave_mode: 1; /*Set SPI work mode. 1: slave mode 0: master mode.*/ + uint32_t soft_reset: 1; /*Software reset enable reset the spi clock line cs line and data lines. Can be configured in CONF state.*/ + uint32_t usr_conf: 1; /*1: Enable the DMA CONF phase of current seg-trans operation which means seg-trans will start. 0: This is not seg-trans mode.*/ + uint32_t reserved29: 3; /*reserved*/ + }; + uint32_t val; + } slave; + union { + struct { + uint32_t data_bitlen: 18; /*The transferred data bit length in SPI slave FD and HD mode.*/ + uint32_t last_command: 8; /*In the slave mode it is the value of command.*/ + uint32_t last_addr: 6; /*In the slave mode it is the value of address.*/ + }; + uint32_t val; + } slave1; + union { + struct { + uint32_t clk_en: 1; /*Set this bit to enable clk gate*/ + uint32_t mst_clk_active: 1; /*Set this bit to power on the SPI module clock.*/ + uint32_t mst_clk_sel: 1; /*This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.*/ + uint32_t reserved3: 29; /*reserved*/ + }; + uint32_t val; + } clk_gate; + uint32_t reserved_ec; + union { + struct { + uint32_t date: 28; /*SPI register version.*/ + uint32_t reserved28: 4; /*reserved*/ + }; + uint32_t val; + } date; +} spi_dev_t; + +extern spi_dev_t GPSPI2; +extern spi_dev_t GPSPI3; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sys_timer_reg.h b/components/soc/soc/esp32s3/include/soc/sys_timer_reg.h new file mode 100644 index 000000000..090663a2b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sys_timer_reg.h @@ -0,0 +1,420 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SYS_TIMER_SYSTIMER_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0000) +/* SYS_TIMER_CLK_EN : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: register file clk gating*/ +#define SYS_TIMER_CLK_EN (BIT(31)) +#define SYS_TIMER_CLK_EN_M (BIT(31)) +#define SYS_TIMER_CLK_EN_V 0x1 +#define SYS_TIMER_CLK_EN_S 31 +/* SYS_TIMER_TIMER_UNIT0_WORK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: timer unit0 work enable*/ +#define SYS_TIMER_TIMER_UNIT0_WORK_EN (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_WORK_EN_S 30 +/* SYS_TIMER_TIMER_UNIT1_WORK_EN : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: timer unit1 work enable*/ +#define SYS_TIMER_TIMER_UNIT1_WORK_EN (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_WORK_EN_S 29 +/* SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: If timer unit0 is stalled when core0 stalled*/ +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_M (BIT(28)) +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28 +/* SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: If timer unit0 is stalled when core1 stalled*/ +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_M (BIT(27)) +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27 +/* SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W ;bitpos:[26] ;default: 1'b1 ; */ +/*description: If timer unit1 is stalled when core0 stalled*/ +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_M (BIT(26)) +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26 +/* SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: If timer unit1 is stalled when core1 stalled*/ +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_M (BIT(25)) +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25 +/* SYS_TIMER_TARGET0_WORK_EN : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: target0 work enable*/ +#define SYS_TIMER_TARGET0_WORK_EN (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_M (BIT(24)) +#define SYS_TIMER_TARGET0_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET0_WORK_EN_S 24 +/* SYS_TIMER_TARGET1_WORK_EN : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: target1 work enable*/ +#define SYS_TIMER_TARGET1_WORK_EN (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_M (BIT(23)) +#define SYS_TIMER_TARGET1_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET1_WORK_EN_S 23 +/* SYS_TIMER_TARGET2_WORK_EN : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: target2 work enable*/ +#define SYS_TIMER_TARGET2_WORK_EN (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_M (BIT(22)) +#define SYS_TIMER_TARGET2_WORK_EN_V 0x1 +#define SYS_TIMER_TARGET2_WORK_EN_S 22 +/* SYS_TIMER_SYSTIMER_CLK_FO : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: systimer clock force on*/ +#define SYS_TIMER_SYSTIMER_CLK_FO (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_CLK_FO_V 0x1 +#define SYS_TIMER_SYSTIMER_CLK_FO_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0004) +/* SYS_TIMER_TIMER_UNIT0_UPDATE : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: update timer_unit0*/ +#define SYS_TIMER_TIMER_UNIT0_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT0_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_UPDATE_S 30 +/* SYS_TIMER_TIMER_UNIT0_VALUE_VALID : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_VALUE_VALID_S 29 + +#define SYS_TIMER_SYSTIMER_UNIT1_OP_REG (DR_REG_SYS_TIMER_BASE + 0x0008) +/* SYS_TIMER_TIMER_UNIT1_UPDATE : WO ;bitpos:[30] ;default: 1'b0 ; */ +/*description: update timer unit1*/ +#define SYS_TIMER_TIMER_UNIT1_UPDATE (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_M (BIT(30)) +#define SYS_TIMER_TIMER_UNIT1_UPDATE_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_UPDATE_S 30 +/* SYS_TIMER_TIMER_UNIT1_VALUE_VALID : RO ;bitpos:[29] ;default: 1'b0 ; */ +/*description: timer value is sync and valid*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_M (BIT(29)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_VALUE_VALID_S 29 + +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x000C) +/* SYS_TIMER_TIMER_UNIT0_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer unit0 load high 32 bit*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT0_LOAD_HI_V) << (SYS_TIMER_TIMER_UNIT0_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0010) +/* SYS_TIMER_TIMER_UNIT0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer unit0 load low 32 bit*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT0_LOAD_LO_V) << (SYS_TIMER_TIMER_UNIT0_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_LOAD_LO_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0014) +/* SYS_TIMER_TIMER_UNIT1_LOAD_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer unit1 load high 32 bit*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_M ((SYS_TIMER_TIMER_UNIT1_LOAD_HI_V) << (SYS_TIMER_TIMER_UNIT1_LOAD_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0018) +/* SYS_TIMER_TIMER_UNIT1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer unit1 load low 32 bit*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_M ((SYS_TIMER_TIMER_UNIT1_LOAD_LO_V) << (SYS_TIMER_TIMER_UNIT1_LOAD_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_LOAD_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET0_HI_REG (DR_REG_SYS_TIMER_BASE + 0x001C) +/* SYS_TIMER_TIMER_TARGET0_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer taget0 high 32 bit*/ +#define SYS_TIMER_TIMER_TARGET0_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET0_HI_M ((SYS_TIMER_TIMER_TARGET0_HI_V) << (SYS_TIMER_TIMER_TARGET0_HI_S)) +#define SYS_TIMER_TIMER_TARGET0_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET0_HI_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET0_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0020) +/* SYS_TIMER_TIMER_TARGET0_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer taget0 low 32 bit*/ +#define SYS_TIMER_TIMER_TARGET0_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET0_LO_M ((SYS_TIMER_TIMER_TARGET0_LO_V) << (SYS_TIMER_TIMER_TARGET0_LO_S)) +#define SYS_TIMER_TIMER_TARGET0_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET0_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET1_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0024) +/* SYS_TIMER_TIMER_TARGET1_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer taget1 high 32 bit*/ +#define SYS_TIMER_TIMER_TARGET1_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET1_HI_M ((SYS_TIMER_TIMER_TARGET1_HI_V) << (SYS_TIMER_TIMER_TARGET1_HI_S)) +#define SYS_TIMER_TIMER_TARGET1_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET1_HI_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET1_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0028) +/* SYS_TIMER_TIMER_TARGET1_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer taget1 low 32 bit*/ +#define SYS_TIMER_TIMER_TARGET1_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET1_LO_M ((SYS_TIMER_TIMER_TARGET1_LO_V) << (SYS_TIMER_TIMER_TARGET1_LO_S)) +#define SYS_TIMER_TIMER_TARGET1_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET1_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET2_HI_REG (DR_REG_SYS_TIMER_BASE + 0x002C) +/* SYS_TIMER_TIMER_TARGET2_HI : R/W ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer taget2 high 32 bit*/ +#define SYS_TIMER_TIMER_TARGET2_HI 0x000FFFFF +#define SYS_TIMER_TIMER_TARGET2_HI_M ((SYS_TIMER_TIMER_TARGET2_HI_V) << (SYS_TIMER_TIMER_TARGET2_HI_S)) +#define SYS_TIMER_TIMER_TARGET2_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_TARGET2_HI_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET2_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0030) +/* SYS_TIMER_TIMER_TARGET2_LO : R/W ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer taget2 low 32 bit*/ +#define SYS_TIMER_TIMER_TARGET2_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET2_LO_M ((SYS_TIMER_TIMER_TARGET2_LO_V) << (SYS_TIMER_TIMER_TARGET2_LO_S)) +#define SYS_TIMER_TIMER_TARGET2_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_TARGET2_LO_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET0_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0034) +/* SYS_TIMER_TARGET0_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: select which unit to compare*/ +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET0_TIMER_UNIT_SEL_S 31 +/* SYS_TIMER_TARGET0_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set target0 to period mode*/ +#define SYS_TIMER_TARGET0_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET0_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET0_PERIOD_MODE_S 30 +/* SYS_TIMER_TARGET0_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: target0 period*/ +#define SYS_TIMER_TARGET0_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET0_PERIOD_M ((SYS_TIMER_TARGET0_PERIOD_V) << (SYS_TIMER_TARGET0_PERIOD_S)) +#define SYS_TIMER_TARGET0_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET0_PERIOD_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET1_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x0038) +/* SYS_TIMER_TARGET1_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: select which unit to compare*/ +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET1_TIMER_UNIT_SEL_S 31 +/* SYS_TIMER_TARGET1_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set target1 to period mode*/ +#define SYS_TIMER_TARGET1_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET1_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET1_PERIOD_MODE_S 30 +/* SYS_TIMER_TARGET1_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: target1 period*/ +#define SYS_TIMER_TARGET1_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET1_PERIOD_M ((SYS_TIMER_TARGET1_PERIOD_V) << (SYS_TIMER_TARGET1_PERIOD_S)) +#define SYS_TIMER_TARGET1_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET1_PERIOD_S 0 + +#define SYS_TIMER_SYSTIMER_TARGET2_CONF_REG (DR_REG_SYS_TIMER_BASE + 0x003C) +/* SYS_TIMER_TARGET2_TIMER_UNIT_SEL : R/W ;bitpos:[31] ;default: 1'b0 ; */ +/*description: select which unit to compare*/ +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_M (BIT(31)) +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_V 0x1 +#define SYS_TIMER_TARGET2_TIMER_UNIT_SEL_S 31 +/* SYS_TIMER_TARGET2_PERIOD_MODE : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: Set target2 to period mode*/ +#define SYS_TIMER_TARGET2_PERIOD_MODE (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_M (BIT(30)) +#define SYS_TIMER_TARGET2_PERIOD_MODE_V 0x1 +#define SYS_TIMER_TARGET2_PERIOD_MODE_S 30 +/* SYS_TIMER_TARGET2_PERIOD : R/W ;bitpos:[25:0] ;default: 26'h0 ; */ +/*description: target2 period*/ +#define SYS_TIMER_TARGET2_PERIOD 0x03FFFFFF +#define SYS_TIMER_TARGET2_PERIOD_M ((SYS_TIMER_TARGET2_PERIOD_V) << (SYS_TIMER_TARGET2_PERIOD_S)) +#define SYS_TIMER_TARGET2_PERIOD_V 0x3FFFFFF +#define SYS_TIMER_TARGET2_PERIOD_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0040) +/* SYS_TIMER_TIMER_UNIT0_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer read value high 32bit*/ +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT0_VALUE_HI_V) << (SYS_TIMER_TIMER_UNIT0_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x0044) +/* SYS_TIMER_TIMER_UNIT0_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer read value low 32bit*/ +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT0_VALUE_LO_V) << (SYS_TIMER_TIMER_UNIT0_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT0_VALUE_LO_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYS_TIMER_BASE + 0x0048) +/* SYS_TIMER_TIMER_UNIT1_VALUE_HI : RO ;bitpos:[19:0] ;default: 20'd0 ; */ +/*description: timer read value high 32bit*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_M ((SYS_TIMER_TIMER_UNIT1_VALUE_HI_V) << (SYS_TIMER_TIMER_UNIT1_VALUE_HI_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_V 0xFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_HI_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYS_TIMER_BASE + 0x004C) +/* SYS_TIMER_TIMER_UNIT1_VALUE_LO : RO ;bitpos:[31:0] ;default: 32'd0 ; */ +/*description: timer read value low 32bit*/ +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_M ((SYS_TIMER_TIMER_UNIT1_VALUE_LO_V) << (SYS_TIMER_TIMER_UNIT1_VALUE_LO_S)) +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFF +#define SYS_TIMER_TIMER_UNIT1_VALUE_LO_S 0 + +#define SYS_TIMER_SYSTIMER_COMP0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0050) +/* SYS_TIMER_TIMER_COMP0_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp0 load value*/ +#define SYS_TIMER_TIMER_COMP0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP0_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_COMP1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0054) +/* SYS_TIMER_TIMER_COMP1_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp1 load value*/ +#define SYS_TIMER_TIMER_COMP1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP1_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_COMP2_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0058) +/* SYS_TIMER_TIMER_COMP2_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer comp2 load value*/ +#define SYS_TIMER_TIMER_COMP2_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_COMP2_LOAD_V 0x1 +#define SYS_TIMER_TIMER_COMP2_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x005C) +/* SYS_TIMER_TIMER_UNIT0_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer unit0 load value*/ +#define SYS_TIMER_TIMER_UNIT0_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT0_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT0_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYS_TIMER_BASE + 0x0060) +/* SYS_TIMER_TIMER_UNIT1_LOAD : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: timer unit1 load value*/ +#define SYS_TIMER_TIMER_UNIT1_LOAD (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_M (BIT(0)) +#define SYS_TIMER_TIMER_UNIT1_LOAD_V 0x1 +#define SYS_TIMER_TIMER_UNIT1_LOAD_S 0 + +#define SYS_TIMER_SYSTIMER_INT_ENA_REG (DR_REG_SYS_TIMER_BASE + 0x0064) +/* SYS_TIMER_SYSTIMER_INT2_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 enable*/ +#define SYS_TIMER_SYSTIMER_INT2_ENA (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_ENA_M (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_ENA_V 0x1 +#define SYS_TIMER_SYSTIMER_INT2_ENA_S 2 +/* SYS_TIMER_SYSTIMER_INT1_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 enable*/ +#define SYS_TIMER_SYSTIMER_INT1_ENA (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_ENA_M (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_ENA_V 0x1 +#define SYS_TIMER_SYSTIMER_INT1_ENA_S 1 +/* SYS_TIMER_SYSTIMER_INT0_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 enable*/ +#define SYS_TIMER_SYSTIMER_INT0_ENA (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_ENA_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_ENA_V 0x1 +#define SYS_TIMER_SYSTIMER_INT0_ENA_S 0 + +#define SYS_TIMER_SYSTIMER_INT_RAW_REG (DR_REG_SYS_TIMER_BASE + 0x0068) +/* SYS_TIMER_SYSTIMER_INT2_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 raw*/ +#define SYS_TIMER_SYSTIMER_INT2_RAW (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_RAW_M (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_RAW_V 0x1 +#define SYS_TIMER_SYSTIMER_INT2_RAW_S 2 +/* SYS_TIMER_SYSTIMER_INT1_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 raw*/ +#define SYS_TIMER_SYSTIMER_INT1_RAW (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_RAW_M (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_RAW_V 0x1 +#define SYS_TIMER_SYSTIMER_INT1_RAW_S 1 +/* SYS_TIMER_SYSTIMER_INT0_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 raw*/ +#define SYS_TIMER_SYSTIMER_INT0_RAW (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_RAW_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_RAW_V 0x1 +#define SYS_TIMER_SYSTIMER_INT0_RAW_S 0 + +#define SYS_TIMER_SYSTIMER_INT_CLR_REG (DR_REG_SYS_TIMER_BASE + 0x006c) +/* SYS_TIMER_SYSTIMER_INT2_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: interupt2 clear*/ +#define SYS_TIMER_SYSTIMER_INT2_CLR (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_CLR_M (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_CLR_V 0x1 +#define SYS_TIMER_SYSTIMER_INT2_CLR_S 2 +/* SYS_TIMER_SYSTIMER_INT1_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: interupt1 clear*/ +#define SYS_TIMER_SYSTIMER_INT1_CLR (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_CLR_M (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_CLR_V 0x1 +#define SYS_TIMER_SYSTIMER_INT1_CLR_S 1 +/* SYS_TIMER_SYSTIMER_INT0_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: interupt0 clear*/ +#define SYS_TIMER_SYSTIMER_INT0_CLR (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_CLR_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_CLR_V 0x1 +#define SYS_TIMER_SYSTIMER_INT0_CLR_S 0 + +#define SYS_TIMER_SYSTIMER_INT_ST_REG (DR_REG_SYS_TIMER_BASE + 0x0070) +/* SYS_TIMER_SYSTIMER_INT2_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_SYSTIMER_INT2_ST (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_ST_M (BIT(2)) +#define SYS_TIMER_SYSTIMER_INT2_ST_V 0x1 +#define SYS_TIMER_SYSTIMER_INT2_ST_S 2 +/* SYS_TIMER_SYSTIMER_INT1_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_SYSTIMER_INT1_ST (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_ST_M (BIT(1)) +#define SYS_TIMER_SYSTIMER_INT1_ST_V 0x1 +#define SYS_TIMER_SYSTIMER_INT1_ST_S 1 +/* SYS_TIMER_SYSTIMER_INT0_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYS_TIMER_SYSTIMER_INT0_ST (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_ST_M (BIT(0)) +#define SYS_TIMER_SYSTIMER_INT0_ST_V 0x1 +#define SYS_TIMER_SYSTIMER_INT0_ST_S 0 + +#define SYS_TIMER_SYSTIMER_DATE_REG (DR_REG_SYS_TIMER_BASE + 0x00fc) +/* SYS_TIMER_SYSTIMER_DATE : R/W ;bitpos:[31:0] ;default: 28'h2003071 ; */ +/*description: */ +#define SYS_TIMER_SYSTIMER_DATE 0xFFFFFFFF +#define SYS_TIMER_SYSTIMER_DATE_M ((SYS_TIMER_SYSTIMER_DATE_V) << (SYS_TIMER_SYSTIMER_DATE_S)) +#define SYS_TIMER_SYSTIMER_DATE_V 0xFFFFFFFF +#define SYS_TIMER_SYSTIMER_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/sys_timer_struct.h b/components/soc/soc/esp32s3/include/soc/sys_timer_struct.h new file mode 100644 index 000000000..e6689754d --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/sys_timer_struct.h @@ -0,0 +1,253 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t systimer_clk_fo: 1; /*systimer clock force on*/ + uint32_t reserved1: 21; + uint32_t target2_work_en: 1; /*target2 work enable*/ + uint32_t target1_work_en: 1; /*target1 work enable*/ + uint32_t target0_work_en: 1; /*target0 work enable*/ + uint32_t timer_unit1_core1_stall_en: 1; /*If timer unit1 is stalled when core1 stalled*/ + uint32_t timer_unit1_core0_stall_en: 1; /*If timer unit1 is stalled when core0 stalled*/ + uint32_t timer_unit0_core1_stall_en: 1; /*If timer unit0 is stalled when core1 stalled*/ + uint32_t timer_unit0_core0_stall_en: 1; /*If timer unit0 is stalled when core0 stalled*/ + uint32_t timer_unit1_work_en: 1; /*timer unit1 work enable*/ + uint32_t timer_unit0_work_en: 1; /*timer unit0 work enable*/ + uint32_t clk_en: 1; /*register file clk gating*/ + }; + uint32_t val; + } systimer_conf; + union { + struct { + uint32_t reserved0: 29; + uint32_t timer_unit0_value_valid: 1; + uint32_t timer_unit0_update: 1; /*update timer_unit0*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } systimer_unit0_op; + union { + struct { + uint32_t reserved0: 29; + uint32_t timer_unit1_value_valid: 1; /*timer value is sync and valid*/ + uint32_t timer_unit1_update: 1; /*update timer unit1*/ + uint32_t reserved31: 1; + }; + uint32_t val; + } systimer_unit1_op; + union { + struct { + uint32_t timer_unit0_load_hi: 20; /*timer unit0 load high 32 bit*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } systimer_unit0_load_hi; + uint32_t systimer_unit0_load_lo; /*timer unit0 load low 32 bit*/ + union { + struct { + uint32_t timer_unit1_load_hi: 20; /*timer unit1 load high 32 bit*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } systimer_unit1_load_hi; + uint32_t systimer_unit1_load_lo; /*timer unit1 load low 32 bit*/ + union { + struct { + uint32_t timer_target0_hi: 20; /*timer taget0 high 32 bit*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } systimer_target0_hi; + uint32_t systimer_target0_lo; /*timer taget0 low 32 bit*/ + union { + struct { + uint32_t timer_target1_hi: 20; /*timer taget1 high 32 bit*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } systimer_target1_hi; + uint32_t systimer_target1_lo; /*timer taget1 low 32 bit*/ + union { + struct { + uint32_t timer_target2_hi: 20; /*timer taget2 high 32 bit*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } systimer_target2_hi; + uint32_t systimer_target2_lo; /*timer taget2 low 32 bit*/ + union { + struct { + uint32_t target0_period: 26; /*target0 period*/ + uint32_t reserved26: 4; + uint32_t target0_period_mode: 1; /*Set target0 to period mode*/ + uint32_t target0_timer_unit_sel: 1; /*select which unit to compare*/ + }; + uint32_t val; + } systimer_target0_conf; + union { + struct { + uint32_t target1_period: 26; /*target1 period*/ + uint32_t reserved26: 4; + uint32_t target1_period_mode: 1; /*Set target1 to period mode*/ + uint32_t target1_timer_unit_sel: 1; /*select which unit to compare*/ + }; + uint32_t val; + } systimer_target1_conf; + union { + struct { + uint32_t target2_period: 26; /*target2 period*/ + uint32_t reserved26: 4; + uint32_t target2_period_mode: 1; /*Set target2 to period mode*/ + uint32_t target2_timer_unit_sel: 1; /*select which unit to compare*/ + }; + uint32_t val; + } systimer_target2_conf; + union { + struct { + uint32_t timer_unit0_value_hi: 20; /*timer read value high 32bit*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } systimer_unit0_value_hi; + uint32_t systimer_unit0_value_lo; /*timer read value low 32bit*/ + union { + struct { + uint32_t timer_unit1_value_hi: 20; /*timer read value high 32bit*/ + uint32_t reserved20: 12; + }; + uint32_t val; + } systimer_unit1_value_hi; + uint32_t systimer_unit1_value_lo; /*timer read value low 32bit*/ + union { + struct { + uint32_t timer_comp0_load: 1; /*timer comp0 load value*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } systimer_comp0_load; + union { + struct { + uint32_t timer_comp1_load: 1; /*timer comp1 load value*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } systimer_comp1_load; + union { + struct { + uint32_t timer_comp2_load: 1; /*timer comp2 load value*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } systimer_comp2_load; + union { + struct { + uint32_t timer_unit0_load: 1; /*timer unit0 load value*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } systimer_unit0_load; + union { + struct { + uint32_t timer_unit1_load: 1; /*timer unit1 load value*/ + uint32_t reserved1: 31; + }; + uint32_t val; + } systimer_unit1_load; + union { + struct { + uint32_t systimer_int0_ena: 1; /*interupt0 enable*/ + uint32_t systimer_int1_ena: 1; /*interupt1 enable*/ + uint32_t systimer_int2_ena: 1; /*interupt2 enable*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } systimer_int_ena; + union { + struct { + uint32_t systimer_int0_raw: 1; /*interupt0 raw*/ + uint32_t systimer_int1_raw: 1; /*interupt1 raw*/ + uint32_t systimer_int2_raw: 1; /*interupt2 raw*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } systimer_int_raw; + union { + struct { + uint32_t systimer_int0_clr: 1; /*interupt0 clear*/ + uint32_t systimer_int1_clr: 1; /*interupt1 clear*/ + uint32_t systimer_int2_clr: 1; /*interupt2 clear*/ + uint32_t reserved3: 29; + }; + uint32_t val; + } systimer_int_clr; + union { + struct { + uint32_t systimer_int0_st: 1; + uint32_t systimer_int1_st: 1; + uint32_t systimer_int2_st: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } systimer_int_st; + uint32_t reserved_74; + uint32_t reserved_78; + uint32_t reserved_7c; + uint32_t reserved_80; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t systimer_date; /**/ +} sys_timer_dev_t; + +extern sys_timer_dev_t SYS_TIMER; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/syscon_reg.h b/components/soc/soc/esp32s3/include/soc/syscon_reg.h new file mode 100644 index 000000000..718fbc180 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/syscon_reg.h @@ -0,0 +1,548 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SYSCON_SYSCLK_CONF_REG (DR_REG_SYSCON_BASE + 0x000) +/* SYSCON_SOC_CLK_SEL : R/W ;bitpos:[15:14] ;default: 2'd0 ; */ +/*description: */ +#define SYSCON_SOC_CLK_SEL 0x00000003 +#define SYSCON_SOC_CLK_SEL_M ((SYSCON_SOC_CLK_SEL_V) << (SYSCON_SOC_CLK_SEL_S)) +#define SYSCON_SOC_CLK_SEL_V 0x3 +#define SYSCON_SOC_CLK_SEL_S 14 +/* SYSCON_RST_TICK_CNT : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_RST_TICK_CNT (BIT(12)) +#define SYSCON_RST_TICK_CNT_M (BIT(12)) +#define SYSCON_RST_TICK_CNT_V 0x1 +#define SYSCON_RST_TICK_CNT_S 12 +/* SYSCON_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_CLK_EN (BIT(11)) +#define SYSCON_CLK_EN_M (BIT(11)) +#define SYSCON_CLK_EN_V 0x1 +#define SYSCON_CLK_EN_S 11 +/* SYSCON_CLK_320M_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_CLK_320M_EN (BIT(10)) +#define SYSCON_CLK_320M_EN_M (BIT(10)) +#define SYSCON_CLK_320M_EN_V 0x1 +#define SYSCON_CLK_320M_EN_S 10 +/* SYSCON_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define SYSCON_PRE_DIV_CNT 0x000003FF +#define SYSCON_PRE_DIV_CNT_M ((SYSCON_PRE_DIV_CNT_V) << (SYSCON_PRE_DIV_CNT_S)) +#define SYSCON_PRE_DIV_CNT_V 0x3FF +#define SYSCON_PRE_DIV_CNT_S 0 + +#define SYSCON_TICK_CONF_REG (DR_REG_SYSCON_BASE + 0x004) +/* SYSCON_TICK_ENABLE : R/W ;bitpos:[16] ;default: 1'd1 ; */ +/*description: */ +#define SYSCON_TICK_ENABLE (BIT(16)) +#define SYSCON_TICK_ENABLE_M (BIT(16)) +#define SYSCON_TICK_ENABLE_V 0x1 +#define SYSCON_TICK_ENABLE_S 16 +/* SYSCON_CK8M_TICK_NUM : R/W ;bitpos:[15:8] ;default: 8'd7 ; */ +/*description: */ +#define SYSCON_CK8M_TICK_NUM 0x000000FF +#define SYSCON_CK8M_TICK_NUM_M ((SYSCON_CK8M_TICK_NUM_V) << (SYSCON_CK8M_TICK_NUM_S)) +#define SYSCON_CK8M_TICK_NUM_V 0xFF +#define SYSCON_CK8M_TICK_NUM_S 8 +/* SYSCON_XTAL_TICK_NUM : R/W ;bitpos:[7:0] ;default: 8'd39 ; */ +/*description: */ +#define SYSCON_XTAL_TICK_NUM 0x000000FF +#define SYSCON_XTAL_TICK_NUM_M ((SYSCON_XTAL_TICK_NUM_V) << (SYSCON_XTAL_TICK_NUM_S)) +#define SYSCON_XTAL_TICK_NUM_V 0xFF +#define SYSCON_XTAL_TICK_NUM_S 0 + +#define SYSCON_CLK_OUT_EN_REG (DR_REG_SYSCON_BASE + 0x008) +/* SYSCON_CLK_XTAL_OEN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_XTAL_OEN (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_M (BIT(10)) +#define SYSCON_CLK_XTAL_OEN_V 0x1 +#define SYSCON_CLK_XTAL_OEN_S 10 +/* SYSCON_CLK40X_BB_OEN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK40X_BB_OEN (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_M (BIT(9)) +#define SYSCON_CLK40X_BB_OEN_V 0x1 +#define SYSCON_CLK40X_BB_OEN_S 9 +/* SYSCON_CLK_DAC_CPU_OEN : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_DAC_CPU_OEN (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_M (BIT(8)) +#define SYSCON_CLK_DAC_CPU_OEN_V 0x1 +#define SYSCON_CLK_DAC_CPU_OEN_S 8 +/* SYSCON_CLK_ADC_INF_OEN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_ADC_INF_OEN (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_M (BIT(7)) +#define SYSCON_CLK_ADC_INF_OEN_V 0x1 +#define SYSCON_CLK_ADC_INF_OEN_S 7 +/* SYSCON_CLK_320M_OEN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_320M_OEN (BIT(6)) +#define SYSCON_CLK_320M_OEN_M (BIT(6)) +#define SYSCON_CLK_320M_OEN_V 0x1 +#define SYSCON_CLK_320M_OEN_S 6 +/* SYSCON_CLK160_OEN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK160_OEN (BIT(5)) +#define SYSCON_CLK160_OEN_M (BIT(5)) +#define SYSCON_CLK160_OEN_V 0x1 +#define SYSCON_CLK160_OEN_S 5 +/* SYSCON_CLK80_OEN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK80_OEN (BIT(4)) +#define SYSCON_CLK80_OEN_M (BIT(4)) +#define SYSCON_CLK80_OEN_V 0x1 +#define SYSCON_CLK80_OEN_S 4 +/* SYSCON_CLK_BB_OEN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK_BB_OEN (BIT(3)) +#define SYSCON_CLK_BB_OEN_M (BIT(3)) +#define SYSCON_CLK_BB_OEN_V 0x1 +#define SYSCON_CLK_BB_OEN_S 3 +/* SYSCON_CLK44_OEN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK44_OEN (BIT(2)) +#define SYSCON_CLK44_OEN_M (BIT(2)) +#define SYSCON_CLK44_OEN_V 0x1 +#define SYSCON_CLK44_OEN_S 2 +/* SYSCON_CLK22_OEN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK22_OEN (BIT(1)) +#define SYSCON_CLK22_OEN_M (BIT(1)) +#define SYSCON_CLK22_OEN_V 0x1 +#define SYSCON_CLK22_OEN_S 1 +/* SYSCON_CLK20_OEN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_CLK20_OEN (BIT(0)) +#define SYSCON_CLK20_OEN_M (BIT(0)) +#define SYSCON_CLK20_OEN_V 0x1 +#define SYSCON_CLK20_OEN_S 0 + +#define SYSCON_WIFI_BB_CFG_REG (DR_REG_SYSCON_BASE + 0x00C) +/* SYSCON_WIFI_BB_CFG : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_WIFI_BB_CFG 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_M ((SYSCON_WIFI_BB_CFG_V) << (SYSCON_WIFI_BB_CFG_S)) +#define SYSCON_WIFI_BB_CFG_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_S 0 + +#define SYSCON_WIFI_BB_CFG_2_REG (DR_REG_SYSCON_BASE + 0x010) +/* SYSCON_WIFI_BB_CFG_2 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_WIFI_BB_CFG_2 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_M ((SYSCON_WIFI_BB_CFG_2_V) << (SYSCON_WIFI_BB_CFG_2_S)) +#define SYSCON_WIFI_BB_CFG_2_V 0xFFFFFFFF +#define SYSCON_WIFI_BB_CFG_2_S 0 + +#define SYSCON_WIFI_CLK_EN_REG (DR_REG_SYSCON_BASE + 0x014) +/* SYSCON_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define SYSCON_WIFI_CLK_EN 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_M ((SYSCON_WIFI_CLK_EN_V) << (SYSCON_WIFI_CLK_EN_S)) +#define SYSCON_WIFI_CLK_EN_V 0xFFFFFFFF +#define SYSCON_WIFI_CLK_EN_S 0 + +#define SYSCON_WIFI_RST_EN_REG (DR_REG_SYSCON_BASE + 0x018) +/* SYSCON_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_WIFI_RST 0xFFFFFFFF +#define SYSCON_WIFI_RST_M ((SYSCON_WIFI_RST_V) << (SYSCON_WIFI_RST_S)) +#define SYSCON_WIFI_RST_V 0xFFFFFFFF +#define SYSCON_WIFI_RST_S 0 + +#define SYSTEM_WIFI_CLK_EN_REG SYSCON_WIFI_CLK_EN_REG +/* SYSTEM_WIFI_CLK_EN : R/W ;bitpos:[31:0] ;default: 32'hfffce030 ; */ +/*description: */ +#define SYSTEM_WIFI_CLK_EN 0xFFFFFFFF +#define SYSTEM_WIFI_CLK_EN_M ((SYSTEM_WIFI_CLK_EN_V) << (SYSTEM_WIFI_CLK_EN_S)) +#define SYSTEM_WIFI_CLK_EN_V 0xFFFFFFFF +#define SYSTEM_WIFI_CLK_EN_S 0 + +/* Mask for all Wifi clock bits - 0, 1, 2, 3, 6, 7, 8, 9, 10, 15, 19, 20, 21 + Bit15 not included here because of the bit now can't be cleared */ +#define SYSTEM_WIFI_CLK_WIFI_EN 0x003807cf +#define SYSTEM_WIFI_CLK_WIFI_EN_M ((SYSTEM_WIFI_CLK_WIFI_EN_V) << (SYSTEM_WIFI_CLK_WIFI_EN_S)) +#define SYSTEM_WIFI_CLK_WIFI_EN_V 0x7cf +#define SYSTEM_WIFI_CLK_WIFI_EN_S 0 +/* Mask for all Bluetooth clock bits - 11, 16, 17 */ +#define SYSTEM_WIFI_CLK_BT_EN 0x61 +#define SYSTEM_WIFI_CLK_BT_EN_M ((SYSTEM_WIFI_CLK_BT_EN_V) << (SYSTEM_WIFI_CLK_BT_EN_S)) +#define SYSTEM_WIFI_CLK_BT_EN_V 0x61 +#define SYSTEM_WIFI_CLK_BT_EN_S 11 +/* Mask for clock bits used by both WIFI and Bluetooth, bit 0, 3, 6, 7, 8, 9 */ +#define SYSTEM_WIFI_CLK_WIFI_BT_COMMON_M 0x000003c9 + +/* Digital team to check */ +//bluetooth baseband bit11 +#define SYSTEM_BT_BASEBAND_EN BIT(11) +//bluetooth LC bit16 and bit17 +#define SYSTEM_BT_LC_EN (BIT(16) | BIT(17)) + +/* Remaining single bit clock masks */ +#define SYSTEM_WIFI_CLK_UNUSED_BIT5 BIT(5) +#define SYSTEM_WIFI_CLK_UNUSED_BIT12 BIT(12) +#define SYSTEM_WIFI_CLK_SDIO_HOST_EN BIT(13) +#define SYSTEM_WIFI_CLK_EMAC_EN BIT(14) +#define SYSTEM_WIFI_CLK_RNG_EN BIT(15) + +#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG +#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG +/* SYSTEM_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSTEM_WIFI_RST 0xFFFFFFFF +#define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S)) +#define SYSTEM_WIFI_RST_V 0xFFFFFFFF +#define SYSTEM_WIFI_RST_S 0 +#define SYSTEM_RW_BTLP_RST (BIT(10)) +#define SYSTEM_RW_BTMAC_RST (BIT(9)) +#define SYSTEM_MACPWR_RST (BIT(8)) +#define SYSTEM_EMAC_RST (BIT(7)) +#define SYSTEM_SDIO_RST (BIT(5)) +#define SYSTEM_BTMAC_RST (BIT(4)) +#define SYSTEM_BT_RST (BIT(3)) +#define SYSTEM_MAC_RST (BIT(2)) +#define SYSTEM_FE_RST (BIT(1)) +#define SYSTEM_BB_RST (BIT(0)) + +#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C) +/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */ +/*description: */ +#define SYSCON_PERI_IO_SWAP 0x000000FF +#define SYSCON_PERI_IO_SWAP_M ((SYSCON_PERI_IO_SWAP_V) << (SYSCON_PERI_IO_SWAP_S)) +#define SYSCON_PERI_IO_SWAP_V 0xFF +#define SYSCON_PERI_IO_SWAP_S 0 + +#define SYSCON_EXT_MEM_PMS_LOCK_REG (DR_REG_SYSCON_BASE + 0x020) +/* SYSCON_EXT_MEM_PMS_LOCK : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_EXT_MEM_PMS_LOCK (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_M (BIT(0)) +#define SYSCON_EXT_MEM_PMS_LOCK_V 0x1 +#define SYSCON_EXT_MEM_PMS_LOCK_S 0 + +#define SYSCON_FLASH_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x024) +/* SYSCON_FLASH_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_FLASH_ACE0_ATTR 0x000000FF +#define SYSCON_FLASH_ACE0_ATTR_M ((SYSCON_FLASH_ACE0_ATTR_V) << (SYSCON_FLASH_ACE0_ATTR_S)) +#define SYSCON_FLASH_ACE0_ATTR_V 0xFF +#define SYSCON_FLASH_ACE0_ATTR_S 0 + +#define SYSCON_FLASH_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x028) +/* SYSCON_FLASH_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_FLASH_ACE1_ATTR 0x000000FF +#define SYSCON_FLASH_ACE1_ATTR_M ((SYSCON_FLASH_ACE1_ATTR_V) << (SYSCON_FLASH_ACE1_ATTR_S)) +#define SYSCON_FLASH_ACE1_ATTR_V 0xFF +#define SYSCON_FLASH_ACE1_ATTR_S 0 + +#define SYSCON_FLASH_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x02C) +/* SYSCON_FLASH_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_FLASH_ACE2_ATTR 0x000000FF +#define SYSCON_FLASH_ACE2_ATTR_M ((SYSCON_FLASH_ACE2_ATTR_V) << (SYSCON_FLASH_ACE2_ATTR_S)) +#define SYSCON_FLASH_ACE2_ATTR_V 0xFF +#define SYSCON_FLASH_ACE2_ATTR_S 0 + +#define SYSCON_FLASH_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x030) +/* SYSCON_FLASH_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_FLASH_ACE3_ATTR 0x000000FF +#define SYSCON_FLASH_ACE3_ATTR_M ((SYSCON_FLASH_ACE3_ATTR_V) << (SYSCON_FLASH_ACE3_ATTR_S)) +#define SYSCON_FLASH_ACE3_ATTR_V 0xFF +#define SYSCON_FLASH_ACE3_ATTR_S 0 + +#define SYSCON_FLASH_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x034) +/* SYSCON_FLASH_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_FLASH_ACE0_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_M ((SYSCON_FLASH_ACE0_ADDR_S_V) << (SYSCON_FLASH_ACE0_ADDR_S_S)) +#define SYSCON_FLASH_ACE0_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE0_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x038) +/* SYSCON_FLASH_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE1_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_M ((SYSCON_FLASH_ACE1_ADDR_S_V) << (SYSCON_FLASH_ACE1_ADDR_S_S)) +#define SYSCON_FLASH_ACE1_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE1_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x03C) +/* SYSCON_FLASH_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE2_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_M ((SYSCON_FLASH_ACE2_ADDR_S_V) << (SYSCON_FLASH_ACE2_ADDR_S_S)) +#define SYSCON_FLASH_ACE2_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE2_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x040) +/* SYSCON_FLASH_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE3_ADDR_S 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_M ((SYSCON_FLASH_ACE3_ADDR_S_V) << (SYSCON_FLASH_ACE3_ADDR_S_S)) +#define SYSCON_FLASH_ACE3_ADDR_S_V 0xFFFFFFFF +#define SYSCON_FLASH_ACE3_ADDR_S_S 0 + +#define SYSCON_FLASH_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x044) +/* SYSCON_FLASH_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE0_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE0_SIZE_M ((SYSCON_FLASH_ACE0_SIZE_V) << (SYSCON_FLASH_ACE0_SIZE_S)) +#define SYSCON_FLASH_ACE0_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE0_SIZE_S 0 + +#define SYSCON_FLASH_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x048) +/* SYSCON_FLASH_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE1_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE1_SIZE_M ((SYSCON_FLASH_ACE1_SIZE_V) << (SYSCON_FLASH_ACE1_SIZE_S)) +#define SYSCON_FLASH_ACE1_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE1_SIZE_S 0 + +#define SYSCON_FLASH_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x04C) +/* SYSCON_FLASH_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE2_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE2_SIZE_M ((SYSCON_FLASH_ACE2_SIZE_V) << (SYSCON_FLASH_ACE2_SIZE_S)) +#define SYSCON_FLASH_ACE2_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE2_SIZE_S 0 + +#define SYSCON_FLASH_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x050) +/* SYSCON_FLASH_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_FLASH_ACE3_SIZE 0x0000FFFF +#define SYSCON_FLASH_ACE3_SIZE_M ((SYSCON_FLASH_ACE3_SIZE_V) << (SYSCON_FLASH_ACE3_SIZE_S)) +#define SYSCON_FLASH_ACE3_SIZE_V 0xFFFF +#define SYSCON_FLASH_ACE3_SIZE_S 0 + +#define SYSCON_SRAM_ACE0_ATTR_REG (DR_REG_SYSCON_BASE + 0x054) +/* SYSCON_SRAM_ACE0_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_SRAM_ACE0_ATTR 0x000000FF +#define SYSCON_SRAM_ACE0_ATTR_M ((SYSCON_SRAM_ACE0_ATTR_V) << (SYSCON_SRAM_ACE0_ATTR_S)) +#define SYSCON_SRAM_ACE0_ATTR_V 0xFF +#define SYSCON_SRAM_ACE0_ATTR_S 0 + +#define SYSCON_SRAM_ACE1_ATTR_REG (DR_REG_SYSCON_BASE + 0x058) +/* SYSCON_SRAM_ACE1_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_SRAM_ACE1_ATTR 0x000000FF +#define SYSCON_SRAM_ACE1_ATTR_M ((SYSCON_SRAM_ACE1_ATTR_V) << (SYSCON_SRAM_ACE1_ATTR_S)) +#define SYSCON_SRAM_ACE1_ATTR_V 0xFF +#define SYSCON_SRAM_ACE1_ATTR_S 0 + +#define SYSCON_SRAM_ACE2_ATTR_REG (DR_REG_SYSCON_BASE + 0x05C) +/* SYSCON_SRAM_ACE2_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_SRAM_ACE2_ATTR 0x000000FF +#define SYSCON_SRAM_ACE2_ATTR_M ((SYSCON_SRAM_ACE2_ATTR_V) << (SYSCON_SRAM_ACE2_ATTR_S)) +#define SYSCON_SRAM_ACE2_ATTR_V 0xFF +#define SYSCON_SRAM_ACE2_ATTR_S 0 + +#define SYSCON_SRAM_ACE3_ATTR_REG (DR_REG_SYSCON_BASE + 0x060) +/* SYSCON_SRAM_ACE3_ATTR : R/W ;bitpos:[7:0] ;default: 8'hff ; */ +/*description: */ +#define SYSCON_SRAM_ACE3_ATTR 0x000000FF +#define SYSCON_SRAM_ACE3_ATTR_M ((SYSCON_SRAM_ACE3_ATTR_V) << (SYSCON_SRAM_ACE3_ATTR_S)) +#define SYSCON_SRAM_ACE3_ATTR_V 0xFF +#define SYSCON_SRAM_ACE3_ATTR_S 0 + +#define SYSCON_SRAM_ACE0_ADDR_REG (DR_REG_SYSCON_BASE + 0x064) +/* SYSCON_SRAM_ACE0_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_SRAM_ACE0_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE0_ADDR_S_M ((SYSCON_SRAM_ACE0_ADDR_S_V) << (SYSCON_SRAM_ACE0_ADDR_S_S)) +#define SYSCON_SRAM_ACE0_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE0_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE1_ADDR_REG (DR_REG_SYSCON_BASE + 0x068) +/* SYSCON_SRAM_ACE1_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h10000000 ; */ +/*description: */ +#define SYSCON_SRAM_ACE1_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE1_ADDR_S_M ((SYSCON_SRAM_ACE1_ADDR_S_V) << (SYSCON_SRAM_ACE1_ADDR_S_S)) +#define SYSCON_SRAM_ACE1_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE1_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE2_ADDR_REG (DR_REG_SYSCON_BASE + 0x06C) +/* SYSCON_SRAM_ACE2_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h20000000 ; */ +/*description: */ +#define SYSCON_SRAM_ACE2_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE2_ADDR_S_M ((SYSCON_SRAM_ACE2_ADDR_S_V) << (SYSCON_SRAM_ACE2_ADDR_S_S)) +#define SYSCON_SRAM_ACE2_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE2_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE3_ADDR_REG (DR_REG_SYSCON_BASE + 0x070) +/* SYSCON_SRAM_ACE3_ADDR_S : R/W ;bitpos:[31:0] ;default: 32'h30000000 ; */ +/*description: */ +#define SYSCON_SRAM_ACE3_ADDR_S 0xFFFFFFFF +#define SYSCON_SRAM_ACE3_ADDR_S_M ((SYSCON_SRAM_ACE3_ADDR_S_V) << (SYSCON_SRAM_ACE3_ADDR_S_S)) +#define SYSCON_SRAM_ACE3_ADDR_S_V 0xFFFFFFFF +#define SYSCON_SRAM_ACE3_ADDR_S_S 0 + +#define SYSCON_SRAM_ACE0_SIZE_REG (DR_REG_SYSCON_BASE + 0x074) +/* SYSCON_SRAM_ACE0_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_SRAM_ACE0_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE0_SIZE_M ((SYSCON_SRAM_ACE0_SIZE_V) << (SYSCON_SRAM_ACE0_SIZE_S)) +#define SYSCON_SRAM_ACE0_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE0_SIZE_S 0 + +#define SYSCON_SRAM_ACE1_SIZE_REG (DR_REG_SYSCON_BASE + 0x078) +/* SYSCON_SRAM_ACE1_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_SRAM_ACE1_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE1_SIZE_M ((SYSCON_SRAM_ACE1_SIZE_V) << (SYSCON_SRAM_ACE1_SIZE_S)) +#define SYSCON_SRAM_ACE1_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE1_SIZE_S 0 + +#define SYSCON_SRAM_ACE2_SIZE_REG (DR_REG_SYSCON_BASE + 0x07C) +/* SYSCON_SRAM_ACE2_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_SRAM_ACE2_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE2_SIZE_M ((SYSCON_SRAM_ACE2_SIZE_V) << (SYSCON_SRAM_ACE2_SIZE_S)) +#define SYSCON_SRAM_ACE2_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE2_SIZE_S 0 + +#define SYSCON_SRAM_ACE3_SIZE_REG (DR_REG_SYSCON_BASE + 0x080) +/* SYSCON_SRAM_ACE3_SIZE : R/W ;bitpos:[15:0] ;default: 16'h1000 ; */ +/*description: */ +#define SYSCON_SRAM_ACE3_SIZE 0x0000FFFF +#define SYSCON_SRAM_ACE3_SIZE_M ((SYSCON_SRAM_ACE3_SIZE_V) << (SYSCON_SRAM_ACE3_SIZE_S)) +#define SYSCON_SRAM_ACE3_SIZE_V 0xFFFF +#define SYSCON_SRAM_ACE3_SIZE_S 0 + +#define SYSCON_SPI_MEM_PMS_CTRL_REG (DR_REG_SYSCON_BASE + 0x084) +/* SYSCON_SPI_MEM_REJECT_CDE : RO ;bitpos:[6:2] ;default: 5'h0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_CDE 0x0000001F +#define SYSCON_SPI_MEM_REJECT_CDE_M ((SYSCON_SPI_MEM_REJECT_CDE_V) << (SYSCON_SPI_MEM_REJECT_CDE_S)) +#define SYSCON_SPI_MEM_REJECT_CDE_V 0x1F +#define SYSCON_SPI_MEM_REJECT_CDE_S 2 +/* SYSCON_SPI_MEM_REJECT_CLR : WOD ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_CLR (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_M (BIT(1)) +#define SYSCON_SPI_MEM_REJECT_CLR_V 0x1 +#define SYSCON_SPI_MEM_REJECT_CLR_S 1 +/* SYSCON_SPI_MEM_REJECT_INT : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_INT (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_M (BIT(0)) +#define SYSCON_SPI_MEM_REJECT_INT_V 0x1 +#define SYSCON_SPI_MEM_REJECT_INT_S 0 + +#define SYSCON_SPI_MEM_REJECT_ADDR_REG (DR_REG_SYSCON_BASE + 0x088) +/* SYSCON_SPI_MEM_REJECT_ADDR : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define SYSCON_SPI_MEM_REJECT_ADDR 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_M ((SYSCON_SPI_MEM_REJECT_ADDR_V) << (SYSCON_SPI_MEM_REJECT_ADDR_S)) +#define SYSCON_SPI_MEM_REJECT_ADDR_V 0xFFFFFFFF +#define SYSCON_SPI_MEM_REJECT_ADDR_S 0 + +#define SYSCON_SDIO_CTRL_REG (DR_REG_SYSCON_BASE + 0x08C) +/* SYSCON_SDIO_WIN_ACCESS_EN : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define SYSCON_SDIO_WIN_ACCESS_EN (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_M (BIT(0)) +#define SYSCON_SDIO_WIN_ACCESS_EN_V 0x1 +#define SYSCON_SDIO_WIN_ACCESS_EN_S 0 + +#define SYSCON_REDCY_SIG0_REG (DR_REG_SYSCON_BASE + 0x090) +/* SYSCON_REDCY_ANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSCON_REDCY_ANDOR (BIT(31)) +#define SYSCON_REDCY_ANDOR_M (BIT(31)) +#define SYSCON_REDCY_ANDOR_V 0x1 +#define SYSCON_REDCY_ANDOR_S 31 +/* SYSCON_REDCY_SIG0 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define SYSCON_REDCY_SIG0 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_M ((SYSCON_REDCY_SIG0_V) << (SYSCON_REDCY_SIG0_S)) +#define SYSCON_REDCY_SIG0_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG0_S 0 + +#define SYSCON_REDCY_SIG1_REG (DR_REG_SYSCON_BASE + 0x094) +/* SYSCON_REDCY_NANDOR : RO ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSCON_REDCY_NANDOR (BIT(31)) +#define SYSCON_REDCY_NANDOR_M (BIT(31)) +#define SYSCON_REDCY_NANDOR_V 0x1 +#define SYSCON_REDCY_NANDOR_S 31 +/* SYSCON_REDCY_SIG1 : R/W ;bitpos:[30:0] ;default: 31'h0 ; */ +/*description: */ +#define SYSCON_REDCY_SIG1 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_M ((SYSCON_REDCY_SIG1_V) << (SYSCON_REDCY_SIG1_S)) +#define SYSCON_REDCY_SIG1_V 0x7FFFFFFF +#define SYSCON_REDCY_SIG1_S 0 + +#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098) +/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_DC_MEM_FORCE_PD (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_M (BIT(5)) +#define SYSCON_DC_MEM_FORCE_PD_V 0x1 +#define SYSCON_DC_MEM_FORCE_PD_S 5 +/* SYSCON_DC_MEM_FORCE_PU : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_DC_MEM_FORCE_PU (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_M (BIT(4)) +#define SYSCON_DC_MEM_FORCE_PU_V 0x1 +#define SYSCON_DC_MEM_FORCE_PU_S 4 +/* SYSCON_PBUS_MEM_FORCE_PD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_PBUS_MEM_FORCE_PD (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_M (BIT(3)) +#define SYSCON_PBUS_MEM_FORCE_PD_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PD_S 3 +/* SYSCON_PBUS_MEM_FORCE_PU : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_PBUS_MEM_FORCE_PU (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_M (BIT(2)) +#define SYSCON_PBUS_MEM_FORCE_PU_V 0x1 +#define SYSCON_PBUS_MEM_FORCE_PU_S 2 +/* SYSCON_AGC_MEM_FORCE_PD : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSCON_AGC_MEM_FORCE_PD (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_M (BIT(1)) +#define SYSCON_AGC_MEM_FORCE_PD_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PD_S 1 +/* SYSCON_AGC_MEM_FORCE_PU : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSCON_AGC_MEM_FORCE_PU (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_M (BIT(0)) +#define SYSCON_AGC_MEM_FORCE_PU_V 0x1 +#define SYSCON_AGC_MEM_FORCE_PU_S 0 + +#define SYSCON_DATE_REG (DR_REG_SYSCON_BASE + 0x3FC) +/* SYSCON_DATE : R/W ;bitpos:[31:0] ;default: 32'h1907100 ; */ +/*description: */ +#define SYSCON_DATE 0xFFFFFFFF +#define SYSCON_DATE_M ((SYSCON_DATE_V) << (SYSCON_DATE_S)) +#define SYSCON_DATE_V 0xFFFFFFFF +#define SYSCON_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/syscon_struct.h b/components/soc/soc/esp32s3/include/soc/syscon_struct.h new file mode 100644 index 000000000..3e1a560b9 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/syscon_struct.h @@ -0,0 +1,467 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t pre_div: 10; + uint32_t clk_320m_en: 1; + uint32_t clk_en: 1; + uint32_t rst_tick: 1; + uint32_t reserved13: 1; + uint32_t soc_clk_sel: 2; + uint32_t reserved16: 16; + }; + uint32_t val; + } apb_ctrl_sysclk_conf; + union { + struct { + uint32_t xtal_tick: 8; + uint32_t ck8m_tick: 8; + uint32_t tick_enable: 1; + uint32_t reserved17: 15; + }; + uint32_t val; + } apb_ctrl_tick_conf; + union { + struct { + uint32_t clk20_oen: 1; + uint32_t clk22_oen: 1; + uint32_t clk44_oen: 1; + uint32_t clk_bb_oen: 1; + uint32_t clk80_oen: 1; + uint32_t clk160_oen: 1; + uint32_t clk_320m_oen: 1; + uint32_t clk_adc_inf_oen: 1; + uint32_t clk_dac_cpu_oen: 1; + uint32_t clk40x_bb_oen: 1; + uint32_t clk_xtal_oen: 1; + uint32_t reserved11: 21; + }; + uint32_t val; + } apb_ctrl_clk_out_en; + union { + struct { + uint32_t peri_io_swap: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } host_inf_sel; + union { + struct { + uint32_t ext_mem_pms_lock: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } ext_mem_pms_lock; + union { + struct { + uint32_t flash_ace0_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } flash_ace0_attr; + union { + struct { + uint32_t flash_ace1_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } flash_ace1_attr; + union { + struct { + uint32_t flash_ace2_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } flash_ace2_attr; + union { + struct { + uint32_t flash_ace3_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } flash_ace3_attr; + uint32_t flash_ace0_addr; /**/ + uint32_t flash_ace1_addr; /**/ + uint32_t flash_ace2_addr; /**/ + uint32_t flash_ace3_addr; /**/ + union { + struct { + uint32_t flash_ace0_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace0_size; + union { + struct { + uint32_t flash_ace1_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace1_size; + union { + struct { + uint32_t flash_ace2_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace2_size; + union { + struct { + uint32_t flash_ace3_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } flash_ace3_size; + union { + struct { + uint32_t sram_ace0_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } sram_ace0_attr; + union { + struct { + uint32_t sram_ace1_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } sram_ace1_attr; + union { + struct { + uint32_t sram_ace2_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } sram_ace2_attr; + union { + struct { + uint32_t sram_ace3_attr: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } sram_ace3_attr; + uint32_t sram_ace0_addr; /**/ + uint32_t sram_ace1_addr; /**/ + uint32_t sram_ace2_addr; /**/ + uint32_t sram_ace3_addr; /**/ + union { + struct { + uint32_t sram_ace0_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace0_size; + union { + struct { + uint32_t sram_ace1_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace1_size; + union { + struct { + uint32_t sram_ace2_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace2_size; + union { + struct { + uint32_t sram_ace3_size: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } sram_ace3_size; + union { + struct { + uint32_t spi_mem_reject_int: 1; + uint32_t spi_mem_reject_clr: 1; + uint32_t spi_mem_reject_cde: 5; + uint32_t reserved7: 25; + }; + uint32_t val; + } spi_mem_pms_ctrl; + uint32_t spi_mem_reject_addr; /**/ + union { + struct { + uint32_t sdio_win_access_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } sdio_ctrl; + union { + struct { + uint32_t redcy_sig0: 31; + uint32_t redcy_andor: 1; + }; + uint32_t val; + } redcy_sig0; + union { + struct { + uint32_t redcy_sig1: 31; + uint32_t redcy_nandor: 1; + }; + uint32_t val; + } redcy_sig1; + uint32_t wifi_bb_cfg; /**/ + uint32_t wifi_bb_cfg_2; /**/ + uint32_t wifi_clk_en; /**/ + uint32_t wifi_rst_en; /**/ + union { + struct { + uint32_t agc_mem_force_pu: 1; + uint32_t agc_mem_force_pd: 1; + uint32_t pbus_mem_force_pu: 1; + uint32_t pbus_mem_force_pd: 1; + uint32_t dc_mem_force_pu: 1; + uint32_t dc_mem_force_pd: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } front_end_mem_pd; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + uint32_t reserved_100; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t date; /**/ +} syscon_dev_t; + +extern syscon_dev_t SYSCON; + +#ifdef __cplusplus +} +#endif + +#endif /* _SOC_SYSCON_STRUCT_H_ */ diff --git a/components/soc/soc/esp32s3/include/soc/system_reg.h b/components/soc/soc/esp32s3/include/soc/system_reg.h new file mode 100644 index 000000000..443fb8737 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/system_reg.h @@ -0,0 +1,1062 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define SYSTEM_ROM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x000) +/* SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON : R/W ;bitpos:[2] ;default: ~1'b0 ; */ +/*description: */ +#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON (BIT(2)) +#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON_M (BIT(2)) +#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON_V 0x1 +#define SYSTEM_ROM_IRAM0_DRAM0_CLKGATE_FORCE_ON_S 2 +/* SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON : R/W ;bitpos:[1:0] ;default: ~2'b0 ; */ +/*description: */ +#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON 0x00000003 +#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_M ((SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_V) << (SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_S)) +#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_V 0x3 +#define SYSTEM_ROM_IRAM0_CLKGATE_FORCE_ON_S 0 + +#define SYSTEM_ROM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x004) +/* SYSTEM_ROM_IRAM0_DRAM0_POWER_UP : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP (BIT(5)) +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP_M (BIT(5)) +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP_V 0x1 +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_UP_S 5 +/* SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN (BIT(4)) +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN_M (BIT(4)) +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN_V 0x1 +#define SYSTEM_ROM_IRAM0_DRAM0_POWER_DOWN_S 4 +/* SYSTEM_ROM_IRAM0_POWER_UP : R/W ;bitpos:[3:2] ;default: 2'b11 ; */ +/*description: */ +#define SYSTEM_ROM_IRAM0_POWER_UP 0x00000003 +#define SYSTEM_ROM_IRAM0_POWER_UP_M ((SYSTEM_ROM_IRAM0_POWER_UP_V) << (SYSTEM_ROM_IRAM0_POWER_UP_S)) +#define SYSTEM_ROM_IRAM0_POWER_UP_V 0x3 +#define SYSTEM_ROM_IRAM0_POWER_UP_S 2 +/* SYSTEM_ROM_IRAM0_POWER_DOWN : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SYSTEM_ROM_IRAM0_POWER_DOWN 0x00000003 +#define SYSTEM_ROM_IRAM0_POWER_DOWN_M ((SYSTEM_ROM_IRAM0_POWER_DOWN_V) << (SYSTEM_ROM_IRAM0_POWER_DOWN_S)) +#define SYSTEM_ROM_IRAM0_POWER_DOWN_V 0x3 +#define SYSTEM_ROM_IRAM0_POWER_DOWN_S 0 + +#define SYSTEM_SRAM_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x008) +/* SYSTEM_SRAM_CLKGATE_FORCE_ON : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SYSTEM_SRAM_CLKGATE_FORCE_ON 0x000007FF +#define SYSTEM_SRAM_CLKGATE_FORCE_ON_M ((SYSTEM_SRAM_CLKGATE_FORCE_ON_V) << (SYSTEM_SRAM_CLKGATE_FORCE_ON_S)) +#define SYSTEM_SRAM_CLKGATE_FORCE_ON_V 0x7FF +#define SYSTEM_SRAM_CLKGATE_FORCE_ON_S 0 + +#define SYSTEM_SRAM_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x00C) +/* SYSTEM_SRAM_POWER_DOWN : R/W ;bitpos:[10:0] ;default: 11'b0 ; */ +/*description: */ +#define SYSTEM_SRAM_POWER_DOWN 0x000007FF +#define SYSTEM_SRAM_POWER_DOWN_M ((SYSTEM_SRAM_POWER_DOWN_V) << (SYSTEM_SRAM_POWER_DOWN_S)) +#define SYSTEM_SRAM_POWER_DOWN_V 0x7FF +#define SYSTEM_SRAM_POWER_DOWN_S 0 + +#define SYSTEM_SRAM_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x010) +/* SYSTEM_SRAM_POWER_UP : R/W ;bitpos:[10:0] ;default: ~11'b0 ; */ +/*description: */ +#define SYSTEM_SRAM_POWER_UP 0x000007FF +#define SYSTEM_SRAM_POWER_UP_M ((SYSTEM_SRAM_POWER_UP_V) << (SYSTEM_SRAM_POWER_UP_S)) +#define SYSTEM_SRAM_POWER_UP_V 0x7FF +#define SYSTEM_SRAM_POWER_UP_S 0 + +#define SYSTEM_CORE_1_CONTROL_0_REG (DR_REG_SYSTEM_BASE + 0x014) +/* SYSTEM_CONTROL_CORE_1_RESETING : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CONTROL_CORE_1_RESETING (BIT(2)) +#define SYSTEM_CONTROL_CORE_1_RESETING_M (BIT(2)) +#define SYSTEM_CONTROL_CORE_1_RESETING_V 0x1 +#define SYSTEM_CONTROL_CORE_1_RESETING_S 2 +/* SYSTEM_CONTROL_CORE_1_CLKGATE_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN (BIT(1)) +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_M (BIT(1)) +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_V 0x1 +#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN_S 1 +/* SYSTEM_CONTROL_CORE_1_RUNSTALL : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CONTROL_CORE_1_RUNSTALL (BIT(0)) +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_M (BIT(0)) +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_V 0x1 +#define SYSTEM_CONTROL_CORE_1_RUNSTALL_S 0 + +#define SYSTEM_CORE_1_CONTROL_1_REG (DR_REG_SYSTEM_BASE + 0x018) +/* SYSTEM_CONTROL_CORE_1_MESSAGE : R/W ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CONTROL_CORE_1_MESSAGE 0xFFFFFFFF +#define SYSTEM_CONTROL_CORE_1_MESSAGE_M ((SYSTEM_CONTROL_CORE_1_MESSAGE_V) << (SYSTEM_CONTROL_CORE_1_MESSAGE_S)) +#define SYSTEM_CONTROL_CORE_1_MESSAGE_V 0xFFFFFFFF +#define SYSTEM_CONTROL_CORE_1_MESSAGE_S 0 + +#define SYSTEM_CPU_PERI_CLK_EN_REG (DR_REG_SYSTEM_BASE + 0x01C) +/* SYSTEM_CLK_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CLK_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_CLK_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_CLK_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_CLK_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CLK_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_CLK_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_CLK_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PERI_RST_EN_REG (DR_REG_SYSTEM_BASE + 0x020) +/* SYSTEM_RST_EN_DEDICATED_GPIO : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RST_EN_DEDICATED_GPIO (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_M (BIT(7)) +#define SYSTEM_RST_EN_DEDICATED_GPIO_V 0x1 +#define SYSTEM_RST_EN_DEDICATED_GPIO_S 7 +/* SYSTEM_RST_EN_ASSIST_DEBUG : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RST_EN_ASSIST_DEBUG (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_M (BIT(6)) +#define SYSTEM_RST_EN_ASSIST_DEBUG_V 0x1 +#define SYSTEM_RST_EN_ASSIST_DEBUG_S 6 + +#define SYSTEM_CPU_PER_CONF_REG (DR_REG_SYSTEM_BASE + 0x024) +/* SYSTEM_CPU_WAITI_DELAY_NUM : R/W ;bitpos:[7:4] ;default: 4'h0 ; */ +/*description: */ +#define SYSTEM_CPU_WAITI_DELAY_NUM 0x0000000F +#define SYSTEM_CPU_WAITI_DELAY_NUM_M ((SYSTEM_CPU_WAITI_DELAY_NUM_V) << (SYSTEM_CPU_WAITI_DELAY_NUM_S)) +#define SYSTEM_CPU_WAITI_DELAY_NUM_V 0xF +#define SYSTEM_CPU_WAITI_DELAY_NUM_S 4 +/* SYSTEM_CPU_WAIT_MODE_FORCE_ON : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_M (BIT(3)) +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_V 0x1 +#define SYSTEM_CPU_WAIT_MODE_FORCE_ON_S 3 +/* SYSTEM_PLL_FREQ_SEL : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_PLL_FREQ_SEL (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_M (BIT(2)) +#define SYSTEM_PLL_FREQ_SEL_V 0x1 +#define SYSTEM_PLL_FREQ_SEL_S 2 +/* SYSTEM_CPUPERIOD_SEL : R/W ;bitpos:[1:0] ;default: 2'b0 ; */ +/*description: */ +#define SYSTEM_CPUPERIOD_SEL 0x00000003 +#define SYSTEM_CPUPERIOD_SEL_M ((SYSTEM_CPUPERIOD_SEL_V) << (SYSTEM_CPUPERIOD_SEL_S)) +#define SYSTEM_CPUPERIOD_SEL_V 0x3 +#define SYSTEM_CPUPERIOD_SEL_S 0 + +#define SYSTEM_JTAG_CTRL_0_REG (DR_REG_SYSTEM_BASE + 0x028) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_0_S 0 + +#define SYSTEM_JTAG_CTRL_1_REG (DR_REG_SYSTEM_BASE + 0x02C) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_1_S 0 + +#define SYSTEM_JTAG_CTRL_2_REG (DR_REG_SYSTEM_BASE + 0x030) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_2_S 0 + +#define SYSTEM_JTAG_CTRL_3_REG (DR_REG_SYSTEM_BASE + 0x034) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_3_S 0 + +#define SYSTEM_JTAG_CTRL_4_REG (DR_REG_SYSTEM_BASE + 0x038) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_4_S 0 + +#define SYSTEM_JTAG_CTRL_5_REG (DR_REG_SYSTEM_BASE + 0x03C) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_5_S 0 + +#define SYSTEM_JTAG_CTRL_6_REG (DR_REG_SYSTEM_BASE + 0x040) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_6_S 0 + +#define SYSTEM_JTAG_CTRL_7_REG (DR_REG_SYSTEM_BASE + 0x044) +/* SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 : WOR ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_M ((SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V) << (SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S)) +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_V 0xFFFFFFFF +#define SYSTEM_CANCEL_EFUSE_DISABLE_JTAG_TEMPORARY_7_S 0 + +#define SYSTEM_MEM_PD_MASK_REG (DR_REG_SYSTEM_BASE + 0x048) +/* SYSTEM_LSLP_MEM_PD_MASK : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LSLP_MEM_PD_MASK (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_M (BIT(0)) +#define SYSTEM_LSLP_MEM_PD_MASK_V 0x1 +#define SYSTEM_LSLP_MEM_PD_MASK_S 0 + +#define SYSTEM_PERIP_CLK_EN0_REG (DR_REG_SYSTEM_BASE + 0x04C) +/* SYSTEM_SPI4_CLK_EN : R/W ;bitpos:[31] ;default: 1'h1 ; */ +/*description: */ +#define SYSTEM_SPI4_CLK_EN (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_M (BIT(31)) +#define SYSTEM_SPI4_CLK_EN_V 0x1 +#define SYSTEM_SPI4_CLK_EN_S 31 +/* SYSTEM_ADC2_ARB_CLK_EN : R/W ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_CLK_EN (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_M (BIT(30)) +#define SYSTEM_ADC2_ARB_CLK_EN_V 0x1 +#define SYSTEM_ADC2_ARB_CLK_EN_S 30 +/* SYSTEM_SYSTIMER_CLK_EN : R/W ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_CLK_EN (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_M (BIT(29)) +#define SYSTEM_SYSTIMER_CLK_EN_V 0x1 +#define SYSTEM_SYSTIMER_CLK_EN_S 29 +/* SYSTEM_APB_SARADC_CLK_EN : R/W ;bitpos:[28] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_CLK_EN (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_M (BIT(28)) +#define SYSTEM_APB_SARADC_CLK_EN_V 0x1 +#define SYSTEM_APB_SARADC_CLK_EN_S 28 +/* SYSTEM_SPI3_DMA_CLK_EN : R/W ;bitpos:[27] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_CLK_EN (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_M (BIT(27)) +#define SYSTEM_SPI3_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI3_DMA_CLK_EN_S 27 +/* SYSTEM_PWM3_CLK_EN : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_CLK_EN (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_M (BIT(26)) +#define SYSTEM_PWM3_CLK_EN_V 0x1 +#define SYSTEM_PWM3_CLK_EN_S 26 +/* SYSTEM_PWM2_CLK_EN : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_CLK_EN (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_M (BIT(25)) +#define SYSTEM_PWM2_CLK_EN_V 0x1 +#define SYSTEM_PWM2_CLK_EN_S 25 +/* SYSTEM_UART_MEM_CLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_MEM_CLK_EN (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_M (BIT(24)) +#define SYSTEM_UART_MEM_CLK_EN_V 0x1 +#define SYSTEM_UART_MEM_CLK_EN_S 24 +/* SYSTEM_USB_CLK_EN : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_USB_CLK_EN (BIT(23)) +#define SYSTEM_USB_CLK_EN_M (BIT(23)) +#define SYSTEM_USB_CLK_EN_V 0x1 +#define SYSTEM_USB_CLK_EN_S 23 +/* SYSTEM_SPI2_DMA_CLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_CLK_EN (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_M (BIT(22)) +#define SYSTEM_SPI2_DMA_CLK_EN_V 0x1 +#define SYSTEM_SPI2_DMA_CLK_EN_S 22 +/* SYSTEM_I2S1_CLK_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S1_CLK_EN (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_M (BIT(21)) +#define SYSTEM_I2S1_CLK_EN_V 0x1 +#define SYSTEM_I2S1_CLK_EN_S 21 +/* SYSTEM_PWM1_CLK_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_CLK_EN (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_M (BIT(20)) +#define SYSTEM_PWM1_CLK_EN_V 0x1 +#define SYSTEM_PWM1_CLK_EN_S 20 +/* SYSTEM_TWAI_CLK_EN : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_CLK_EN (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_M (BIT(19)) +#define SYSTEM_TWAI_CLK_EN_V 0x1 +#define SYSTEM_TWAI_CLK_EN_S 19 +/* SYSTEM_I2C_EXT1_CLK_EN : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_CLK_EN (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_M (BIT(18)) +#define SYSTEM_I2C_EXT1_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT1_CLK_EN_S 18 +/* SYSTEM_PWM0_CLK_EN : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_CLK_EN (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_M (BIT(17)) +#define SYSTEM_PWM0_CLK_EN_V 0x1 +#define SYSTEM_PWM0_CLK_EN_S 17 +/* SYSTEM_SPI3_CLK_EN : R/W ;bitpos:[16] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI3_CLK_EN (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_M (BIT(16)) +#define SYSTEM_SPI3_CLK_EN_V 0x1 +#define SYSTEM_SPI3_CLK_EN_S 16 +/* SYSTEM_TIMERGROUP1_CLK_EN : R/W ;bitpos:[15] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_CLK_EN (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP1_CLK_EN_S 15 +/* SYSTEM_EFUSE_CLK_EN : R/W ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EFUSE_CLK_EN (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_M (BIT(14)) +#define SYSTEM_EFUSE_CLK_EN_V 0x1 +#define SYSTEM_EFUSE_CLK_EN_S 14 +/* SYSTEM_TIMERGROUP_CLK_EN : R/W ;bitpos:[13] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_CLK_EN (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_M (BIT(13)) +#define SYSTEM_TIMERGROUP_CLK_EN_V 0x1 +#define SYSTEM_TIMERGROUP_CLK_EN_S 13 +/* SYSTEM_UHCI1_CLK_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_CLK_EN (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_M (BIT(12)) +#define SYSTEM_UHCI1_CLK_EN_V 0x1 +#define SYSTEM_UHCI1_CLK_EN_S 12 +/* SYSTEM_LEDC_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_CLK_EN (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_M (BIT(11)) +#define SYSTEM_LEDC_CLK_EN_V 0x1 +#define SYSTEM_LEDC_CLK_EN_S 11 +/* SYSTEM_PCNT_CLK_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_CLK_EN (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_M (BIT(10)) +#define SYSTEM_PCNT_CLK_EN_V 0x1 +#define SYSTEM_PCNT_CLK_EN_S 10 +/* SYSTEM_RMT_CLK_EN : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_CLK_EN (BIT(9)) +#define SYSTEM_RMT_CLK_EN_M (BIT(9)) +#define SYSTEM_RMT_CLK_EN_V 0x1 +#define SYSTEM_RMT_CLK_EN_S 9 +/* SYSTEM_UHCI0_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_CLK_EN (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_M (BIT(8)) +#define SYSTEM_UHCI0_CLK_EN_V 0x1 +#define SYSTEM_UHCI0_CLK_EN_S 8 +/* SYSTEM_I2C_EXT0_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_CLK_EN (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_M (BIT(7)) +#define SYSTEM_I2C_EXT0_CLK_EN_V 0x1 +#define SYSTEM_I2C_EXT0_CLK_EN_S 7 +/* SYSTEM_SPI2_CLK_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI2_CLK_EN (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_M (BIT(6)) +#define SYSTEM_SPI2_CLK_EN_V 0x1 +#define SYSTEM_SPI2_CLK_EN_S 6 +/* SYSTEM_UART1_CLK_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART1_CLK_EN (BIT(5)) +#define SYSTEM_UART1_CLK_EN_M (BIT(5)) +#define SYSTEM_UART1_CLK_EN_V 0x1 +#define SYSTEM_UART1_CLK_EN_S 5 +/* SYSTEM_I2S0_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_CLK_EN (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_M (BIT(4)) +#define SYSTEM_I2S0_CLK_EN_V 0x1 +#define SYSTEM_I2S0_CLK_EN_S 4 +/* SYSTEM_WDG_CLK_EN : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_WDG_CLK_EN (BIT(3)) +#define SYSTEM_WDG_CLK_EN_M (BIT(3)) +#define SYSTEM_WDG_CLK_EN_V 0x1 +#define SYSTEM_WDG_CLK_EN_S 3 +/* SYSTEM_UART_CLK_EN : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART_CLK_EN (BIT(2)) +#define SYSTEM_UART_CLK_EN_M (BIT(2)) +#define SYSTEM_UART_CLK_EN_V 0x1 +#define SYSTEM_UART_CLK_EN_S 2 +/* SYSTEM_SPI01_CLK_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SPI01_CLK_EN (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_M (BIT(1)) +#define SYSTEM_SPI01_CLK_EN_V 0x1 +#define SYSTEM_SPI01_CLK_EN_S 1 +/* SYSTEM_TIMERS_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_TIMERS_CLK_EN (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_M (BIT(0)) +#define SYSTEM_TIMERS_CLK_EN_V 0x1 +#define SYSTEM_TIMERS_CLK_EN_S 0 + +#define SYSTEM_PERIP_CLK_EN1_REG (DR_REG_SYSTEM_BASE + 0x050) +/* SYSTEM_UART2_CLK_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_UART2_CLK_EN (BIT(9)) +#define SYSTEM_UART2_CLK_EN_M (BIT(9)) +#define SYSTEM_UART2_CLK_EN_V 0x1 +#define SYSTEM_UART2_CLK_EN_S 9 +/* SYSTEM_LCD_CAM_CLK_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_CLK_EN (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_M (BIT(8)) +#define SYSTEM_LCD_CAM_CLK_EN_V 0x1 +#define SYSTEM_LCD_CAM_CLK_EN_S 8 +/* SYSTEM_SDIO_HOST_CLK_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_CLK_EN (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_M (BIT(7)) +#define SYSTEM_SDIO_HOST_CLK_EN_V 0x1 +#define SYSTEM_SDIO_HOST_CLK_EN_S 7 +/* SYSTEM_DMA_CLK_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DMA_CLK_EN (BIT(6)) +#define SYSTEM_DMA_CLK_EN_M (BIT(6)) +#define SYSTEM_DMA_CLK_EN_V 0x1 +#define SYSTEM_DMA_CLK_EN_S 6 +/* SYSTEM_CRYPTO_HMAC_CLK_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_CLK_EN (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_HMAC_CLK_EN_S 5 +/* SYSTEM_CRYPTO_DS_CLK_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_CLK_EN (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_DS_CLK_EN_S 4 +/* SYSTEM_CRYPTO_RSA_CLK_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_CLK_EN (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_RSA_CLK_EN_S 3 +/* SYSTEM_CRYPTO_SHA_CLK_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_CLK_EN (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_SHA_CLK_EN_S 2 +/* SYSTEM_CRYPTO_AES_CLK_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_CLK_EN (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_CLK_EN_V 0x1 +#define SYSTEM_CRYPTO_AES_CLK_EN_S 1 + +#define SYSTEM_PERIP_RST_EN0_REG (DR_REG_SYSTEM_BASE + 0x054) +/* SYSTEM_SPI4_RST : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define SYSTEM_SPI4_RST (BIT(31)) +#define SYSTEM_SPI4_RST_M (BIT(31)) +#define SYSTEM_SPI4_RST_V 0x1 +#define SYSTEM_SPI4_RST_S 31 +/* SYSTEM_ADC2_ARB_RST : R/W ;bitpos:[30] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ADC2_ARB_RST (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_M (BIT(30)) +#define SYSTEM_ADC2_ARB_RST_V 0x1 +#define SYSTEM_ADC2_ARB_RST_S 30 +/* SYSTEM_SYSTIMER_RST : R/W ;bitpos:[29] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SYSTIMER_RST (BIT(29)) +#define SYSTEM_SYSTIMER_RST_M (BIT(29)) +#define SYSTEM_SYSTIMER_RST_V 0x1 +#define SYSTEM_SYSTIMER_RST_S 29 +/* SYSTEM_APB_SARADC_RST : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_APB_SARADC_RST (BIT(28)) +#define SYSTEM_APB_SARADC_RST_M (BIT(28)) +#define SYSTEM_APB_SARADC_RST_V 0x1 +#define SYSTEM_APB_SARADC_RST_S 28 +/* SYSTEM_SPI3_DMA_RST : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_DMA_RST (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_M (BIT(27)) +#define SYSTEM_SPI3_DMA_RST_V 0x1 +#define SYSTEM_SPI3_DMA_RST_S 27 +/* SYSTEM_PWM3_RST : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM3_RST (BIT(26)) +#define SYSTEM_PWM3_RST_M (BIT(26)) +#define SYSTEM_PWM3_RST_V 0x1 +#define SYSTEM_PWM3_RST_S 26 +/* SYSTEM_PWM2_RST : R/W ;bitpos:[25] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM2_RST (BIT(25)) +#define SYSTEM_PWM2_RST_M (BIT(25)) +#define SYSTEM_PWM2_RST_V 0x1 +#define SYSTEM_PWM2_RST_S 25 +/* SYSTEM_UART_MEM_RST : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_MEM_RST (BIT(24)) +#define SYSTEM_UART_MEM_RST_M (BIT(24)) +#define SYSTEM_UART_MEM_RST_V 0x1 +#define SYSTEM_UART_MEM_RST_S 24 +/* SYSTEM_USB_RST : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_USB_RST (BIT(23)) +#define SYSTEM_USB_RST_M (BIT(23)) +#define SYSTEM_USB_RST_V 0x1 +#define SYSTEM_USB_RST_S 23 +/* SYSTEM_SPI2_DMA_RST : R/W ;bitpos:[22] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_DMA_RST (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_M (BIT(22)) +#define SYSTEM_SPI2_DMA_RST_V 0x1 +#define SYSTEM_SPI2_DMA_RST_S 22 +/* SYSTEM_I2S1_RST : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S1_RST (BIT(21)) +#define SYSTEM_I2S1_RST_M (BIT(21)) +#define SYSTEM_I2S1_RST_V 0x1 +#define SYSTEM_I2S1_RST_S 21 +/* SYSTEM_PWM1_RST : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM1_RST (BIT(20)) +#define SYSTEM_PWM1_RST_M (BIT(20)) +#define SYSTEM_PWM1_RST_V 0x1 +#define SYSTEM_PWM1_RST_S 20 +/* SYSTEM_TWAI_RST : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TWAI_RST (BIT(19)) +#define SYSTEM_TWAI_RST_M (BIT(19)) +#define SYSTEM_TWAI_RST_V 0x1 +#define SYSTEM_TWAI_RST_S 19 +/* SYSTEM_I2C_EXT1_RST : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT1_RST (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_M (BIT(18)) +#define SYSTEM_I2C_EXT1_RST_V 0x1 +#define SYSTEM_I2C_EXT1_RST_S 18 +/* SYSTEM_PWM0_RST : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PWM0_RST (BIT(17)) +#define SYSTEM_PWM0_RST_M (BIT(17)) +#define SYSTEM_PWM0_RST_V 0x1 +#define SYSTEM_PWM0_RST_S 17 +/* SYSTEM_SPI3_RST : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI3_RST (BIT(16)) +#define SYSTEM_SPI3_RST_M (BIT(16)) +#define SYSTEM_SPI3_RST_V 0x1 +#define SYSTEM_SPI3_RST_S 16 +/* SYSTEM_TIMERGROUP1_RST : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP1_RST (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_M (BIT(15)) +#define SYSTEM_TIMERGROUP1_RST_V 0x1 +#define SYSTEM_TIMERGROUP1_RST_S 15 +/* SYSTEM_EFUSE_RST : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EFUSE_RST (BIT(14)) +#define SYSTEM_EFUSE_RST_M (BIT(14)) +#define SYSTEM_EFUSE_RST_V 0x1 +#define SYSTEM_EFUSE_RST_S 14 +/* SYSTEM_TIMERGROUP_RST : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERGROUP_RST (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_M (BIT(13)) +#define SYSTEM_TIMERGROUP_RST_V 0x1 +#define SYSTEM_TIMERGROUP_RST_S 13 +/* SYSTEM_UHCI1_RST : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI1_RST (BIT(12)) +#define SYSTEM_UHCI1_RST_M (BIT(12)) +#define SYSTEM_UHCI1_RST_V 0x1 +#define SYSTEM_UHCI1_RST_S 12 +/* SYSTEM_LEDC_RST : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LEDC_RST (BIT(11)) +#define SYSTEM_LEDC_RST_M (BIT(11)) +#define SYSTEM_LEDC_RST_V 0x1 +#define SYSTEM_LEDC_RST_S 11 +/* SYSTEM_PCNT_RST : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_PCNT_RST (BIT(10)) +#define SYSTEM_PCNT_RST_M (BIT(10)) +#define SYSTEM_PCNT_RST_V 0x1 +#define SYSTEM_PCNT_RST_S 10 +/* SYSTEM_RMT_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RMT_RST (BIT(9)) +#define SYSTEM_RMT_RST_M (BIT(9)) +#define SYSTEM_RMT_RST_V 0x1 +#define SYSTEM_RMT_RST_S 9 +/* SYSTEM_UHCI0_RST : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UHCI0_RST (BIT(8)) +#define SYSTEM_UHCI0_RST_M (BIT(8)) +#define SYSTEM_UHCI0_RST_V 0x1 +#define SYSTEM_UHCI0_RST_S 8 +/* SYSTEM_I2C_EXT0_RST : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2C_EXT0_RST (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_M (BIT(7)) +#define SYSTEM_I2C_EXT0_RST_V 0x1 +#define SYSTEM_I2C_EXT0_RST_S 7 +/* SYSTEM_SPI2_RST : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI2_RST (BIT(6)) +#define SYSTEM_SPI2_RST_M (BIT(6)) +#define SYSTEM_SPI2_RST_V 0x1 +#define SYSTEM_SPI2_RST_S 6 +/* SYSTEM_UART1_RST : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART1_RST (BIT(5)) +#define SYSTEM_UART1_RST_M (BIT(5)) +#define SYSTEM_UART1_RST_V 0x1 +#define SYSTEM_UART1_RST_S 5 +/* SYSTEM_I2S0_RST : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_I2S0_RST (BIT(4)) +#define SYSTEM_I2S0_RST_M (BIT(4)) +#define SYSTEM_I2S0_RST_V 0x1 +#define SYSTEM_I2S0_RST_S 4 +/* SYSTEM_WDG_RST : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_WDG_RST (BIT(3)) +#define SYSTEM_WDG_RST_M (BIT(3)) +#define SYSTEM_WDG_RST_V 0x1 +#define SYSTEM_WDG_RST_S 3 +/* SYSTEM_UART_RST : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART_RST (BIT(2)) +#define SYSTEM_UART_RST_M (BIT(2)) +#define SYSTEM_UART_RST_V 0x1 +#define SYSTEM_UART_RST_S 2 +/* SYSTEM_SPI01_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_SPI01_RST (BIT(1)) +#define SYSTEM_SPI01_RST_M (BIT(1)) +#define SYSTEM_SPI01_RST_V 0x1 +#define SYSTEM_SPI01_RST_S 1 +/* SYSTEM_TIMERS_RST : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_TIMERS_RST (BIT(0)) +#define SYSTEM_TIMERS_RST_M (BIT(0)) +#define SYSTEM_TIMERS_RST_V 0x1 +#define SYSTEM_TIMERS_RST_S 0 + +#define SYSTEM_PERIP_RST_EN1_REG (DR_REG_SYSTEM_BASE + 0x058) +/* SYSTEM_UART2_RST : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_UART2_RST (BIT(9)) +#define SYSTEM_UART2_RST_M (BIT(9)) +#define SYSTEM_UART2_RST_V 0x1 +#define SYSTEM_UART2_RST_S 9 +/* SYSTEM_LCD_CAM_RST : R/W ;bitpos:[8] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LCD_CAM_RST (BIT(8)) +#define SYSTEM_LCD_CAM_RST_M (BIT(8)) +#define SYSTEM_LCD_CAM_RST_V 0x1 +#define SYSTEM_LCD_CAM_RST_S 8 +/* SYSTEM_SDIO_HOST_RST : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_SDIO_HOST_RST (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_M (BIT(7)) +#define SYSTEM_SDIO_HOST_RST_V 0x1 +#define SYSTEM_SDIO_HOST_RST_S 7 +/* SYSTEM_DMA_RST : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_DMA_RST (BIT(6)) +#define SYSTEM_DMA_RST_M (BIT(6)) +#define SYSTEM_DMA_RST_V 0x1 +#define SYSTEM_DMA_RST_S 6 +/* SYSTEM_CRYPTO_HMAC_RST : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_HMAC_RST (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_M (BIT(5)) +#define SYSTEM_CRYPTO_HMAC_RST_V 0x1 +#define SYSTEM_CRYPTO_HMAC_RST_S 5 +/* SYSTEM_CRYPTO_DS_RST : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_DS_RST (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_M (BIT(4)) +#define SYSTEM_CRYPTO_DS_RST_V 0x1 +#define SYSTEM_CRYPTO_DS_RST_S 4 +/* SYSTEM_CRYPTO_RSA_RST : R/W ;bitpos:[3] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_RSA_RST (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_M (BIT(3)) +#define SYSTEM_CRYPTO_RSA_RST_V 0x1 +#define SYSTEM_CRYPTO_RSA_RST_S 3 +/* SYSTEM_CRYPTO_SHA_RST : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_SHA_RST (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_M (BIT(2)) +#define SYSTEM_CRYPTO_SHA_RST_V 0x1 +#define SYSTEM_CRYPTO_SHA_RST_S 2 +/* SYSTEM_CRYPTO_AES_RST : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CRYPTO_AES_RST (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_M (BIT(1)) +#define SYSTEM_CRYPTO_AES_RST_V 0x1 +#define SYSTEM_CRYPTO_AES_RST_S 1 + +#define SYSTEM_BT_LPCK_DIV_INT_REG (DR_REG_SYSTEM_BASE + 0x05C) +/* SYSTEM_BT_LPCK_DIV_NUM : R/W ;bitpos:[11:0] ;default: 12'd255 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_NUM 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_NUM_M ((SYSTEM_BT_LPCK_DIV_NUM_V) << (SYSTEM_BT_LPCK_DIV_NUM_S)) +#define SYSTEM_BT_LPCK_DIV_NUM_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_NUM_S 0 + +#define SYSTEM_BT_LPCK_DIV_FRAC_REG (DR_REG_SYSTEM_BASE + 0x060) +/* SYSTEM_LPCLK_RTC_EN : R/W ;bitpos:[28] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_RTC_EN (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_M (BIT(28)) +#define SYSTEM_LPCLK_RTC_EN_V 0x1 +#define SYSTEM_LPCLK_RTC_EN_S 28 +/* SYSTEM_LPCLK_SEL_XTAL32K : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_XTAL32K (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_M (BIT(27)) +#define SYSTEM_LPCLK_SEL_XTAL32K_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL32K_S 27 +/* SYSTEM_LPCLK_SEL_XTAL : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_XTAL (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_M (BIT(26)) +#define SYSTEM_LPCLK_SEL_XTAL_V 0x1 +#define SYSTEM_LPCLK_SEL_XTAL_S 26 +/* SYSTEM_LPCLK_SEL_8M : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_8M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_M (BIT(25)) +#define SYSTEM_LPCLK_SEL_8M_V 0x1 +#define SYSTEM_LPCLK_SEL_8M_S 25 +/* SYSTEM_LPCLK_SEL_RTC_SLOW : R/W ;bitpos:[24] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_LPCLK_SEL_RTC_SLOW (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_M (BIT(24)) +#define SYSTEM_LPCLK_SEL_RTC_SLOW_V 0x1 +#define SYSTEM_LPCLK_SEL_RTC_SLOW_S 24 +/* SYSTEM_BT_LPCK_DIV_A : R/W ;bitpos:[23:12] ;default: 12'd1 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_A 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_A_M ((SYSTEM_BT_LPCK_DIV_A_V) << (SYSTEM_BT_LPCK_DIV_A_S)) +#define SYSTEM_BT_LPCK_DIV_A_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_A_S 12 +/* SYSTEM_BT_LPCK_DIV_B : R/W ;bitpos:[11:0] ;default: 12'd1 ; */ +/*description: */ +#define SYSTEM_BT_LPCK_DIV_B 0x00000FFF +#define SYSTEM_BT_LPCK_DIV_B_M ((SYSTEM_BT_LPCK_DIV_B_V) << (SYSTEM_BT_LPCK_DIV_B_S)) +#define SYSTEM_BT_LPCK_DIV_B_V 0xFFF +#define SYSTEM_BT_LPCK_DIV_B_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_0_REG (DR_REG_SYSTEM_BASE + 0x064) +/* SYSTEM_CPU_INTR_FROM_CPU_0 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_0 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_0_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_0_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_1_REG (DR_REG_SYSTEM_BASE + 0x068) +/* SYSTEM_CPU_INTR_FROM_CPU_1 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_1 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_1_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_1_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_2_REG (DR_REG_SYSTEM_BASE + 0x06C) +/* SYSTEM_CPU_INTR_FROM_CPU_2 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_2 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_2_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_2_S 0 + +#define SYSTEM_CPU_INTR_FROM_CPU_3_REG (DR_REG_SYSTEM_BASE + 0x070) +/* SYSTEM_CPU_INTR_FROM_CPU_3 : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_CPU_INTR_FROM_CPU_3 (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_M (BIT(0)) +#define SYSTEM_CPU_INTR_FROM_CPU_3_V 0x1 +#define SYSTEM_CPU_INTR_FROM_CPU_3_S 0 + +#define SYSTEM_RSA_PD_CTRL_REG (DR_REG_SYSTEM_BASE + 0x074) +/* SYSTEM_RSA_MEM_FORCE_PD : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_FORCE_PD (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_M (BIT(2)) +#define SYSTEM_RSA_MEM_FORCE_PD_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PD_S 2 +/* SYSTEM_RSA_MEM_FORCE_PU : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_FORCE_PU (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_M (BIT(1)) +#define SYSTEM_RSA_MEM_FORCE_PU_V 0x1 +#define SYSTEM_RSA_MEM_FORCE_PU_S 1 +/* SYSTEM_RSA_MEM_PD : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_RSA_MEM_PD (BIT(0)) +#define SYSTEM_RSA_MEM_PD_M (BIT(0)) +#define SYSTEM_RSA_MEM_PD_V 0x1 +#define SYSTEM_RSA_MEM_PD_S 0 + +#define SYSTEM_EDMA_CTRL_REG (DR_REG_SYSTEM_BASE + 0x078) +/* SYSTEM_EDMA_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_EDMA_RESET (BIT(1)) +#define SYSTEM_EDMA_RESET_M (BIT(1)) +#define SYSTEM_EDMA_RESET_V 0x1 +#define SYSTEM_EDMA_RESET_S 1 +/* SYSTEM_EDMA_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_EDMA_CLK_ON (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_M (BIT(0)) +#define SYSTEM_EDMA_CLK_ON_V 0x1 +#define SYSTEM_EDMA_CLK_ON_S 0 + +#define SYSTEM_CACHE_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x07C) +/* SYSTEM_DCACHE_RESET : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_DCACHE_RESET (BIT(3)) +#define SYSTEM_DCACHE_RESET_M (BIT(3)) +#define SYSTEM_DCACHE_RESET_V 0x1 +#define SYSTEM_DCACHE_RESET_S 3 +/* SYSTEM_DCACHE_CLK_ON : R/W ;bitpos:[2] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_DCACHE_CLK_ON (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_M (BIT(2)) +#define SYSTEM_DCACHE_CLK_ON_V 0x1 +#define SYSTEM_DCACHE_CLK_ON_S 2 +/* SYSTEM_ICACHE_RESET : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ICACHE_RESET (BIT(1)) +#define SYSTEM_ICACHE_RESET_M (BIT(1)) +#define SYSTEM_ICACHE_RESET_V 0x1 +#define SYSTEM_ICACHE_RESET_S 1 +/* SYSTEM_ICACHE_CLK_ON : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_ICACHE_CLK_ON (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_M (BIT(0)) +#define SYSTEM_ICACHE_CLK_ON_V 0x1 +#define SYSTEM_ICACHE_CLK_ON_S 0 + +#define SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG (DR_REG_SYSTEM_BASE + 0x080) +/* SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_M (BIT(3)) +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT_S 3 +/* SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_M (BIT(2)) +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_G0CB_DECRYPT_S 2 +/* SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_M (BIT(1)) +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_DOWNLOAD_DB_ENCRYPT_S 1 +/* SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_M (BIT(0)) +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_V 0x1 +#define SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT_S 0 + +#define SYSTEM_RTC_FASTMEM_CONFIG_REG (DR_REG_SYSTEM_BASE + 0x084) +/* SYSTEM_RTC_MEM_CRC_FINISH : RO ;bitpos:[31] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_FINISH (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_M (BIT(31)) +#define SYSTEM_RTC_MEM_CRC_FINISH_V 0x1 +#define SYSTEM_RTC_MEM_CRC_FINISH_S 31 +/* SYSTEM_RTC_MEM_CRC_LEN : R/W ;bitpos:[30:20] ;default: 11'h7ff ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_LEN 0x000007FF +#define SYSTEM_RTC_MEM_CRC_LEN_M ((SYSTEM_RTC_MEM_CRC_LEN_V) << (SYSTEM_RTC_MEM_CRC_LEN_S)) +#define SYSTEM_RTC_MEM_CRC_LEN_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_LEN_S 20 +/* SYSTEM_RTC_MEM_CRC_ADDR : R/W ;bitpos:[19:9] ;default: 11'h0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_ADDR 0x000007FF +#define SYSTEM_RTC_MEM_CRC_ADDR_M ((SYSTEM_RTC_MEM_CRC_ADDR_V) << (SYSTEM_RTC_MEM_CRC_ADDR_S)) +#define SYSTEM_RTC_MEM_CRC_ADDR_V 0x7FF +#define SYSTEM_RTC_MEM_CRC_ADDR_S 9 +/* SYSTEM_RTC_MEM_CRC_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_START (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_M (BIT(8)) +#define SYSTEM_RTC_MEM_CRC_START_V 0x1 +#define SYSTEM_RTC_MEM_CRC_START_S 8 + +#define SYSTEM_RTC_FASTMEM_CRC_REG (DR_REG_SYSTEM_BASE + 0x088) +/* SYSTEM_RTC_MEM_CRC_RES : RO ;bitpos:[31:0] ;default: 32'b0 ; */ +/*description: */ +#define SYSTEM_RTC_MEM_CRC_RES 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_M ((SYSTEM_RTC_MEM_CRC_RES_V) << (SYSTEM_RTC_MEM_CRC_RES_S)) +#define SYSTEM_RTC_MEM_CRC_RES_V 0xFFFFFFFF +#define SYSTEM_RTC_MEM_CRC_RES_S 0 + +#define SYSTEM_REDUNDANT_ECO_CTRL_REG (DR_REG_SYSTEM_BASE + 0x08C) +/* SYSTEM_REDUNDANT_ECO_RESULT : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REDUNDANT_ECO_RESULT (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_M (BIT(1)) +#define SYSTEM_REDUNDANT_ECO_RESULT_V 0x1 +#define SYSTEM_REDUNDANT_ECO_RESULT_S 1 +/* SYSTEM_REDUNDANT_ECO_DRIVE : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_REDUNDANT_ECO_DRIVE (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_M (BIT(0)) +#define SYSTEM_REDUNDANT_ECO_DRIVE_V 0x1 +#define SYSTEM_REDUNDANT_ECO_DRIVE_S 0 + +#define SYSTEM_CLOCK_GATE_REG (DR_REG_SYSTEM_BASE + 0x090) +/* SYSTEM_CLK_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define SYSTEM_CLK_EN (BIT(0)) +#define SYSTEM_CLK_EN_M (BIT(0)) +#define SYSTEM_CLK_EN_V 0x1 +#define SYSTEM_CLK_EN_S 0 + +#define SYSTEM_SYSCLK_CONF_REG (DR_REG_SYSTEM_BASE + 0x094) +/* SYSTEM_CLK_DIV_EN : RO ;bitpos:[19] ;default: 1'd0 ; */ +/*description: */ +#define SYSTEM_CLK_DIV_EN (BIT(19)) +#define SYSTEM_CLK_DIV_EN_M (BIT(19)) +#define SYSTEM_CLK_DIV_EN_V 0x1 +#define SYSTEM_CLK_DIV_EN_S 19 +/* SYSTEM_CLK_XTAL_FREQ : RO ;bitpos:[18:12] ;default: 7'd0 ; */ +/*description: */ +#define SYSTEM_CLK_XTAL_FREQ 0x0000007F +#define SYSTEM_CLK_XTAL_FREQ_M ((SYSTEM_CLK_XTAL_FREQ_V) << (SYSTEM_CLK_XTAL_FREQ_S)) +#define SYSTEM_CLK_XTAL_FREQ_V 0x7F +#define SYSTEM_CLK_XTAL_FREQ_S 12 +/* SYSTEM_SOC_CLK_SEL : R/W ;bitpos:[11:10] ;default: 2'd0 ; */ +/*description: */ +#define SYSTEM_SOC_CLK_SEL 0x00000003 +#define SYSTEM_SOC_CLK_SEL_M ((SYSTEM_SOC_CLK_SEL_V) << (SYSTEM_SOC_CLK_SEL_S)) +#define SYSTEM_SOC_CLK_SEL_V 0x3 +#define SYSTEM_SOC_CLK_SEL_S 10 +/* SYSTEM_PRE_DIV_CNT : R/W ;bitpos:[9:0] ;default: 10'h1 ; */ +/*description: */ +#define SYSTEM_PRE_DIV_CNT 0x000003FF +#define SYSTEM_PRE_DIV_CNT_M ((SYSTEM_PRE_DIV_CNT_V) << (SYSTEM_PRE_DIV_CNT_S)) +#define SYSTEM_PRE_DIV_CNT_V 0x3FF +#define SYSTEM_PRE_DIV_CNT_S 0 + +#define SYSTEM_MEM_PVT_REG (DR_REG_SYSTEM_BASE + 0x098) +/* SYSTEM_MEM_TIMING_ERR_CNT : RO ;bitpos:[21:6] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_MEM_TIMING_ERR_CNT 0x0000FFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_M ((SYSTEM_MEM_TIMING_ERR_CNT_V) << (SYSTEM_MEM_TIMING_ERR_CNT_S)) +#define SYSTEM_MEM_TIMING_ERR_CNT_V 0xFFFF +#define SYSTEM_MEM_TIMING_ERR_CNT_S 6 +/* SYSTEM_MEM_PVT_MONITOR_EN : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MEM_PVT_MONITOR_EN (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_M (BIT(5)) +#define SYSTEM_MEM_PVT_MONITOR_EN_V 0x1 +#define SYSTEM_MEM_PVT_MONITOR_EN_S 5 +/* SYSTEM_MEM_ERR_CNT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_MEM_ERR_CNT_CLR (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_M (BIT(4)) +#define SYSTEM_MEM_ERR_CNT_CLR_V 0x1 +#define SYSTEM_MEM_ERR_CNT_CLR_S 4 +/* SYSTEM_MEM_PATH_LEN : R/W ;bitpos:[3:0] ;default: 4'h3 ; */ +/*description: */ +#define SYSTEM_MEM_PATH_LEN 0x0000000F +#define SYSTEM_MEM_PATH_LEN_M ((SYSTEM_MEM_PATH_LEN_V) << (SYSTEM_MEM_PATH_LEN_S)) +#define SYSTEM_MEM_PATH_LEN_V 0xF +#define SYSTEM_MEM_PATH_LEN_S 0 + +#define SYSTEM_COMB_PVT_REG (DR_REG_SYSTEM_BASE + 0x09C) +/* SYSTEM_COMB_TIMING_ERR_CNT : RO ;bitpos:[22:7] ;default: 16'h0 ; */ +/*description: */ +#define SYSTEM_COMB_TIMING_ERR_CNT 0x0000FFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_M ((SYSTEM_COMB_TIMING_ERR_CNT_V) << (SYSTEM_COMB_TIMING_ERR_CNT_S)) +#define SYSTEM_COMB_TIMING_ERR_CNT_V 0xFFFF +#define SYSTEM_COMB_TIMING_ERR_CNT_S 7 +/* SYSTEM_COMB_PVT_MONITOR_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_PVT_MONITOR_EN (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_M (BIT(6)) +#define SYSTEM_COMB_PVT_MONITOR_EN_V 0x1 +#define SYSTEM_COMB_PVT_MONITOR_EN_S 6 +/* SYSTEM_COMB_ERR_CNT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define SYSTEM_COMB_ERR_CNT_CLR (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_M (BIT(5)) +#define SYSTEM_COMB_ERR_CNT_CLR_V 0x1 +#define SYSTEM_COMB_ERR_CNT_CLR_S 5 +/* SYSTEM_COMB_PATH_LEN : R/W ;bitpos:[4:0] ;default: 5'h3 ; */ +/*description: */ +#define SYSTEM_COMB_PATH_LEN 0x0000001F +#define SYSTEM_COMB_PATH_LEN_M ((SYSTEM_COMB_PATH_LEN_V) << (SYSTEM_COMB_PATH_LEN_S)) +#define SYSTEM_COMB_PATH_LEN_V 0x1F +#define SYSTEM_COMB_PATH_LEN_S 0 + +#define SYSTEM_RETENTION_BUS_CTRL_REG (DR_REG_SYSTEM_BASE + 0x100) +/* SYSTEM_RETENTION_LINK_ADDR : R/W ;bitpos:[26:0] ;default: 27'd0 ; */ +/*description: */ +#define SYSTEM_RETENTION_LINK_ADDR 0x07FFFFFF +#define SYSTEM_RETENTION_LINK_ADDR_M ((SYSTEM_RETENTION_LINK_ADDR_V) << (SYSTEM_RETENTION_LINK_ADDR_S)) +#define SYSTEM_RETENTION_LINK_ADDR_V 0x7FFFFFF +#define SYSTEM_RETENTION_LINK_ADDR_S 0 + +#define SYSTEM_DATE_REG (DR_REG_SYSTEM_BASE + 0xFFC) +/* SYSTEM_DATE : R/W ;bitpos:[27:0] ;default: 28'h2002281 ; */ +/*description: */ +#define SYSTEM_DATE 0x0FFFFFFF +#define SYSTEM_DATE_M ((SYSTEM_DATE_V) << (SYSTEM_DATE_S)) +#define SYSTEM_DATE_V 0xFFFFFFF +#define SYSTEM_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/system_struct.h b/components/soc/soc/esp32s3/include/soc/system_struct.h new file mode 100644 index 000000000..77383353c --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/system_struct.h @@ -0,0 +1,1364 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t rom_iram0_clkgate_force_on: 2; + uint32_t rom_iram0_dram0_clkgate_force_on: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } rom_ctrl_0; + union { + struct { + uint32_t rom_iram0_power_down: 2; + uint32_t rom_iram0_power_up: 2; + uint32_t rom_iram0_dram0_power_down: 1; + uint32_t rom_iram0_dram0_power_up: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } rom_ctrl_1; + union { + struct { + uint32_t sram_clkgate_force_on: 11; + uint32_t reserved11: 21; + }; + uint32_t val; + } sram_ctrl_0; + union { + struct { + uint32_t sram_power_down: 11; + uint32_t reserved11: 21; + }; + uint32_t val; + } sram_ctrl_1; + union { + struct { + uint32_t sram_power_up: 11; + uint32_t reserved11: 21; + }; + uint32_t val; + } sram_ctrl_2; + union { + struct { + uint32_t control_core_1_runstall: 1; + uint32_t control_core_1_clkgate_en: 1; + uint32_t control_core_1_reseting: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } core_1_control_0; + uint32_t core_1_control_1; /**/ + union { + struct { + uint32_t reserved0: 6; + uint32_t clk_en_assist_debug: 1; + uint32_t clk_en_dedicated_gpio: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } cpu_peri_clk_en; + union { + struct { + uint32_t reserved0: 6; + uint32_t rst_en_assist_debug: 1; + uint32_t rst_en_dedicated_gpio: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } cpu_peri_rst_en; + union { + struct { + uint32_t cpuperiod_sel: 2; + uint32_t pll_freq_sel: 1; + uint32_t cpu_wait_mode_force_on: 1; + uint32_t cpu_waiti_delay_num: 4; + uint32_t reserved8: 24; + }; + uint32_t val; + } cpu_per_conf; + uint32_t jtag_ctrl_0; /**/ + uint32_t jtag_ctrl_1; /**/ + uint32_t jtag_ctrl_2; /**/ + uint32_t jtag_ctrl_3; /**/ + uint32_t jtag_ctrl_4; /**/ + uint32_t jtag_ctrl_5; /**/ + uint32_t jtag_ctrl_6; /**/ + uint32_t jtag_ctrl_7; /**/ + union { + struct { + uint32_t lslp_mem_pd_mask: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } mem_pd_mask; + union { + struct { + uint32_t timers_clk_en: 1; + uint32_t spi01_clk_en: 1; + uint32_t uart_clk_en: 1; + uint32_t wdg_clk_en: 1; + uint32_t i2s0_clk_en: 1; + uint32_t uart1_clk_en: 1; + uint32_t spi2_clk_en: 1; + uint32_t i2c_ext0_clk_en: 1; + uint32_t uhci0_clk_en: 1; + uint32_t rmt_clk_en: 1; + uint32_t pcnt_clk_en: 1; + uint32_t ledc_clk_en: 1; + uint32_t uhci1_clk_en: 1; + uint32_t timergroup_clk_en: 1; + uint32_t efuse_clk_en: 1; + uint32_t timergroup1_clk_en: 1; + uint32_t spi3_clk_en: 1; + uint32_t pwm0_clk_en: 1; + uint32_t i2c_ext1_clk_en: 1; + uint32_t can_clk_en: 1; + uint32_t pwm1_clk_en: 1; + uint32_t i2s1_clk_en: 1; + uint32_t spi2_dma_clk_en: 1; + uint32_t usb_clk_en: 1; + uint32_t uart_mem_clk_en: 1; + uint32_t pwm2_clk_en: 1; + uint32_t pwm3_clk_en: 1; + uint32_t spi3_dma_clk_en: 1; + uint32_t apb_saradc_clk_en: 1; + uint32_t systimer_clk_en: 1; + uint32_t adc2_arb_clk_en: 1; + uint32_t spi4_clk_en: 1; + }; + uint32_t val; + } perip_clk_en0; + union { + struct { + uint32_t reserved0: 1; + uint32_t crypto_aes_clk_en: 1; + uint32_t crypto_sha_clk_en: 1; + uint32_t crypto_rsa_clk_en: 1; + uint32_t crypto_ds_clk_en: 1; + uint32_t crypto_hmac_clk_en: 1; + uint32_t dma_clk_en: 1; + uint32_t sdio_host_clk_en: 1; + uint32_t lcd_cam_clk_en: 1; + uint32_t uart2_clk_en: 1; + uint32_t reserved10: 22; + }; + uint32_t val; + } perip_clk_en1; + union { + struct { + uint32_t timers_rst: 1; + uint32_t spi01_rst: 1; + uint32_t uart_rst: 1; + uint32_t wdg_rst: 1; + uint32_t i2s0_rst: 1; + uint32_t uart1_rst: 1; + uint32_t spi2_rst: 1; + uint32_t i2c_ext0_rst: 1; + uint32_t uhci0_rst: 1; + uint32_t rmt_rst: 1; + uint32_t pcnt_rst: 1; + uint32_t ledc_rst: 1; + uint32_t uhci1_rst: 1; + uint32_t timergroup_rst: 1; + uint32_t efuse_rst: 1; + uint32_t timergroup1_rst: 1; + uint32_t spi3_rst: 1; + uint32_t pwm0_rst: 1; + uint32_t i2c_ext1_rst: 1; + uint32_t can_rst: 1; + uint32_t pwm1_rst: 1; + uint32_t i2s1_rst: 1; + uint32_t spi2_dma_rst: 1; + uint32_t usb_rst: 1; + uint32_t uart_mem_rst: 1; + uint32_t pwm2_rst: 1; + uint32_t pwm3_rst: 1; + uint32_t spi3_dma_rst: 1; + uint32_t apb_saradc_rst: 1; + uint32_t systimer_rst: 1; + uint32_t adc2_arb_rst: 1; + uint32_t spi4_rst: 1; + }; + uint32_t val; + } perip_rst_en0; + union { + struct { + uint32_t reserved0: 1; + uint32_t crypto_aes_rst: 1; + uint32_t crypto_sha_rst: 1; + uint32_t crypto_rsa_rst: 1; + uint32_t crypto_ds_rst: 1; + uint32_t crypto_hmac_rst: 1; + uint32_t dma_rst: 1; + uint32_t sdio_host_rst: 1; + uint32_t lcd_cam_rst: 1; + uint32_t uart2_rst: 1; + uint32_t reserved10: 22; + }; + uint32_t val; + } perip_rst_en1; + union { + struct { + uint32_t bt_lpck_div_num: 12; + uint32_t reserved12: 20; + }; + uint32_t val; + } bt_lpck_div_int; + union { + struct { + uint32_t bt_lpck_div_b: 12; + uint32_t bt_lpck_div_a: 12; + uint32_t lpclk_sel_rtc_slow: 1; + uint32_t lpclk_sel_8m: 1; + uint32_t lpclk_sel_xtal: 1; + uint32_t lpclk_sel_xtal32k: 1; + uint32_t lpclk_rtc_en: 1; + uint32_t reserved29: 3; + }; + uint32_t val; + } bt_lpck_div_frac; + union { + struct { + uint32_t cpu_intr_from_cpu_0: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } cpu_intr_from_cpu_0; + union { + struct { + uint32_t cpu_intr_from_cpu_1: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } cpu_intr_from_cpu_1; + union { + struct { + uint32_t cpu_intr_from_cpu_2: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } cpu_intr_from_cpu_2; + union { + struct { + uint32_t cpu_intr_from_cpu_3: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } cpu_intr_from_cpu_3; + union { + struct { + uint32_t rsa_mem_pd: 1; + uint32_t rsa_mem_force_pu: 1; + uint32_t rsa_mem_force_pd: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } rsa_pd_ctrl; + union { + struct { + uint32_t edma_clk_on: 1; + uint32_t edma_reset: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } edma_ctrl; + union { + struct { + uint32_t icache_clk_on: 1; + uint32_t icache_reset: 1; + uint32_t dcache_clk_on: 1; + uint32_t dcache_reset: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } cache_control; + union { + struct { + uint32_t enable_spi_manual_encrypt: 1; + uint32_t enable_download_db_encrypt: 1; + uint32_t enable_download_g0cb_decrypt: 1; + uint32_t enable_download_manual_encrypt: 1; + uint32_t reserved4: 28; + }; + uint32_t val; + } external_device_encrypt_decrypt_control; + union { + struct { + uint32_t reserved0: 8; + uint32_t rtc_mem_crc_start: 1; + uint32_t rtc_mem_crc_addr: 11; + uint32_t rtc_mem_crc_len: 11; + uint32_t rtc_mem_crc_finish: 1; + }; + uint32_t val; + } rtc_fastmem_config; + uint32_t rtc_fastmem_crc; /**/ + union { + struct { + uint32_t redundant_eco_drive: 1; + uint32_t redundant_eco_result: 1; + uint32_t reserved2: 30; + }; + uint32_t val; + } redundant_eco_ctrl; + union { + struct { + uint32_t clk_en: 1; + uint32_t reserved1: 31; + }; + uint32_t val; + } clock_gate; + union { + struct { + uint32_t pre_div_cnt: 10; + uint32_t soc_clk_sel: 2; + uint32_t clk_xtal_freq: 7; + uint32_t clk_div_en: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } sysclk_conf; + union { + struct { + uint32_t mem_path_len: 4; + uint32_t mem_err_cnt_clr: 1; + uint32_t mem_pvt_monitor_en: 1; + uint32_t mem_timing_err_cnt: 16; + uint32_t reserved22: 10; + }; + uint32_t val; + } mem_pvt; + union { + struct { + uint32_t comb_path_len: 5; + uint32_t comb_err_cnt_clr: 1; + uint32_t comb_pvt_monitor_en: 1; + uint32_t comb_timing_err_cnt: 16; + uint32_t reserved23: 9; + }; + uint32_t val; + } comb_pvt; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + uint32_t reserved_f8; + uint32_t reserved_fc; + union { + struct { + uint32_t retention_link_addr: 27; + uint32_t reserved27: 5; + }; + uint32_t val; + } retention_bus_ctrl; + uint32_t reserved_104; + uint32_t reserved_108; + uint32_t reserved_10c; + uint32_t reserved_110; + uint32_t reserved_114; + uint32_t reserved_118; + uint32_t reserved_11c; + uint32_t reserved_120; + uint32_t reserved_124; + uint32_t reserved_128; + uint32_t reserved_12c; + uint32_t reserved_130; + uint32_t reserved_134; + uint32_t reserved_138; + uint32_t reserved_13c; + uint32_t reserved_140; + uint32_t reserved_144; + uint32_t reserved_148; + uint32_t reserved_14c; + uint32_t reserved_150; + uint32_t reserved_154; + uint32_t reserved_158; + uint32_t reserved_15c; + uint32_t reserved_160; + uint32_t reserved_164; + uint32_t reserved_168; + uint32_t reserved_16c; + uint32_t reserved_170; + uint32_t reserved_174; + uint32_t reserved_178; + uint32_t reserved_17c; + uint32_t reserved_180; + uint32_t reserved_184; + uint32_t reserved_188; + uint32_t reserved_18c; + uint32_t reserved_190; + uint32_t reserved_194; + uint32_t reserved_198; + uint32_t reserved_19c; + uint32_t reserved_1a0; + uint32_t reserved_1a4; + uint32_t reserved_1a8; + uint32_t reserved_1ac; + uint32_t reserved_1b0; + uint32_t reserved_1b4; + uint32_t reserved_1b8; + uint32_t reserved_1bc; + uint32_t reserved_1c0; + uint32_t reserved_1c4; + uint32_t reserved_1c8; + uint32_t reserved_1cc; + uint32_t reserved_1d0; + uint32_t reserved_1d4; + uint32_t reserved_1d8; + uint32_t reserved_1dc; + uint32_t reserved_1e0; + uint32_t reserved_1e4; + uint32_t reserved_1e8; + uint32_t reserved_1ec; + uint32_t reserved_1f0; + uint32_t reserved_1f4; + uint32_t reserved_1f8; + uint32_t reserved_1fc; + uint32_t reserved_200; + uint32_t reserved_204; + uint32_t reserved_208; + uint32_t reserved_20c; + uint32_t reserved_210; + uint32_t reserved_214; + uint32_t reserved_218; + uint32_t reserved_21c; + uint32_t reserved_220; + uint32_t reserved_224; + uint32_t reserved_228; + uint32_t reserved_22c; + uint32_t reserved_230; + uint32_t reserved_234; + uint32_t reserved_238; + uint32_t reserved_23c; + uint32_t reserved_240; + uint32_t reserved_244; + uint32_t reserved_248; + uint32_t reserved_24c; + uint32_t reserved_250; + uint32_t reserved_254; + uint32_t reserved_258; + uint32_t reserved_25c; + uint32_t reserved_260; + uint32_t reserved_264; + uint32_t reserved_268; + uint32_t reserved_26c; + uint32_t reserved_270; + uint32_t reserved_274; + uint32_t reserved_278; + uint32_t reserved_27c; + uint32_t reserved_280; + uint32_t reserved_284; + uint32_t reserved_288; + uint32_t reserved_28c; + uint32_t reserved_290; + uint32_t reserved_294; + uint32_t reserved_298; + uint32_t reserved_29c; + uint32_t reserved_2a0; + uint32_t reserved_2a4; + uint32_t reserved_2a8; + uint32_t reserved_2ac; + uint32_t reserved_2b0; + uint32_t reserved_2b4; + uint32_t reserved_2b8; + uint32_t reserved_2bc; + uint32_t reserved_2c0; + uint32_t reserved_2c4; + uint32_t reserved_2c8; + uint32_t reserved_2cc; + uint32_t reserved_2d0; + uint32_t reserved_2d4; + uint32_t reserved_2d8; + uint32_t reserved_2dc; + uint32_t reserved_2e0; + uint32_t reserved_2e4; + uint32_t reserved_2e8; + uint32_t reserved_2ec; + uint32_t reserved_2f0; + uint32_t reserved_2f4; + uint32_t reserved_2f8; + uint32_t reserved_2fc; + uint32_t reserved_300; + uint32_t reserved_304; + uint32_t reserved_308; + uint32_t reserved_30c; + uint32_t reserved_310; + uint32_t reserved_314; + uint32_t reserved_318; + uint32_t reserved_31c; + uint32_t reserved_320; + uint32_t reserved_324; + uint32_t reserved_328; + uint32_t reserved_32c; + uint32_t reserved_330; + uint32_t reserved_334; + uint32_t reserved_338; + uint32_t reserved_33c; + uint32_t reserved_340; + uint32_t reserved_344; + uint32_t reserved_348; + uint32_t reserved_34c; + uint32_t reserved_350; + uint32_t reserved_354; + uint32_t reserved_358; + uint32_t reserved_35c; + uint32_t reserved_360; + uint32_t reserved_364; + uint32_t reserved_368; + uint32_t reserved_36c; + uint32_t reserved_370; + uint32_t reserved_374; + uint32_t reserved_378; + uint32_t reserved_37c; + uint32_t reserved_380; + uint32_t reserved_384; + uint32_t reserved_388; + uint32_t reserved_38c; + uint32_t reserved_390; + uint32_t reserved_394; + uint32_t reserved_398; + uint32_t reserved_39c; + uint32_t reserved_3a0; + uint32_t reserved_3a4; + uint32_t reserved_3a8; + uint32_t reserved_3ac; + uint32_t reserved_3b0; + uint32_t reserved_3b4; + uint32_t reserved_3b8; + uint32_t reserved_3bc; + uint32_t reserved_3c0; + uint32_t reserved_3c4; + uint32_t reserved_3c8; + uint32_t reserved_3cc; + uint32_t reserved_3d0; + uint32_t reserved_3d4; + uint32_t reserved_3d8; + uint32_t reserved_3dc; + uint32_t reserved_3e0; + uint32_t reserved_3e4; + uint32_t reserved_3e8; + uint32_t reserved_3ec; + uint32_t reserved_3f0; + uint32_t reserved_3f4; + uint32_t reserved_3f8; + uint32_t reserved_3fc; + uint32_t reserved_400; + uint32_t reserved_404; + uint32_t reserved_408; + uint32_t reserved_40c; + uint32_t reserved_410; + uint32_t reserved_414; + uint32_t reserved_418; + uint32_t reserved_41c; + uint32_t reserved_420; + uint32_t reserved_424; + uint32_t reserved_428; + uint32_t reserved_42c; + uint32_t reserved_430; + uint32_t reserved_434; + uint32_t reserved_438; + uint32_t reserved_43c; + uint32_t reserved_440; + uint32_t reserved_444; + uint32_t reserved_448; + uint32_t reserved_44c; + uint32_t reserved_450; + uint32_t reserved_454; + uint32_t reserved_458; + uint32_t reserved_45c; + uint32_t reserved_460; + uint32_t reserved_464; + uint32_t reserved_468; + uint32_t reserved_46c; + uint32_t reserved_470; + uint32_t reserved_474; + uint32_t reserved_478; + uint32_t reserved_47c; + uint32_t reserved_480; + uint32_t reserved_484; + uint32_t reserved_488; + uint32_t reserved_48c; + uint32_t reserved_490; + uint32_t reserved_494; + uint32_t reserved_498; + uint32_t reserved_49c; + uint32_t reserved_4a0; + uint32_t reserved_4a4; + uint32_t reserved_4a8; + uint32_t reserved_4ac; + uint32_t reserved_4b0; + uint32_t reserved_4b4; + uint32_t reserved_4b8; + uint32_t reserved_4bc; + uint32_t reserved_4c0; + uint32_t reserved_4c4; + uint32_t reserved_4c8; + uint32_t reserved_4cc; + uint32_t reserved_4d0; + uint32_t reserved_4d4; + uint32_t reserved_4d8; + uint32_t reserved_4dc; + uint32_t reserved_4e0; + uint32_t reserved_4e4; + uint32_t reserved_4e8; + uint32_t reserved_4ec; + uint32_t reserved_4f0; + uint32_t reserved_4f4; + uint32_t reserved_4f8; + uint32_t reserved_4fc; + uint32_t reserved_500; + uint32_t reserved_504; + uint32_t reserved_508; + uint32_t reserved_50c; + uint32_t reserved_510; + uint32_t reserved_514; + uint32_t reserved_518; + uint32_t reserved_51c; + uint32_t reserved_520; + uint32_t reserved_524; + uint32_t reserved_528; + uint32_t reserved_52c; + uint32_t reserved_530; + uint32_t reserved_534; + uint32_t reserved_538; + uint32_t reserved_53c; + uint32_t reserved_540; + uint32_t reserved_544; + uint32_t reserved_548; + uint32_t reserved_54c; + uint32_t reserved_550; + uint32_t reserved_554; + uint32_t reserved_558; + uint32_t reserved_55c; + uint32_t reserved_560; + uint32_t reserved_564; + uint32_t reserved_568; + uint32_t reserved_56c; + uint32_t reserved_570; + uint32_t reserved_574; + uint32_t reserved_578; + uint32_t reserved_57c; + uint32_t reserved_580; + uint32_t reserved_584; + uint32_t reserved_588; + uint32_t reserved_58c; + uint32_t reserved_590; + uint32_t reserved_594; + uint32_t reserved_598; + uint32_t reserved_59c; + uint32_t reserved_5a0; + uint32_t reserved_5a4; + uint32_t reserved_5a8; + uint32_t reserved_5ac; + uint32_t reserved_5b0; + uint32_t reserved_5b4; + uint32_t reserved_5b8; + uint32_t reserved_5bc; + uint32_t reserved_5c0; + uint32_t reserved_5c4; + uint32_t reserved_5c8; + uint32_t reserved_5cc; + uint32_t reserved_5d0; + uint32_t reserved_5d4; + uint32_t reserved_5d8; + uint32_t reserved_5dc; + uint32_t reserved_5e0; + uint32_t reserved_5e4; + uint32_t reserved_5e8; + uint32_t reserved_5ec; + uint32_t reserved_5f0; + uint32_t reserved_5f4; + uint32_t reserved_5f8; + uint32_t reserved_5fc; + uint32_t reserved_600; + uint32_t reserved_604; + uint32_t reserved_608; + uint32_t reserved_60c; + uint32_t reserved_610; + uint32_t reserved_614; + uint32_t reserved_618; + uint32_t reserved_61c; + uint32_t reserved_620; + uint32_t reserved_624; + uint32_t reserved_628; + uint32_t reserved_62c; + uint32_t reserved_630; + uint32_t reserved_634; + uint32_t reserved_638; + uint32_t reserved_63c; + uint32_t reserved_640; + uint32_t reserved_644; + uint32_t reserved_648; + uint32_t reserved_64c; + uint32_t reserved_650; + uint32_t reserved_654; + uint32_t reserved_658; + uint32_t reserved_65c; + uint32_t reserved_660; + uint32_t reserved_664; + uint32_t reserved_668; + uint32_t reserved_66c; + uint32_t reserved_670; + uint32_t reserved_674; + uint32_t reserved_678; + uint32_t reserved_67c; + uint32_t reserved_680; + uint32_t reserved_684; + uint32_t reserved_688; + uint32_t reserved_68c; + uint32_t reserved_690; + uint32_t reserved_694; + uint32_t reserved_698; + uint32_t reserved_69c; + uint32_t reserved_6a0; + uint32_t reserved_6a4; + uint32_t reserved_6a8; + uint32_t reserved_6ac; + uint32_t reserved_6b0; + uint32_t reserved_6b4; + uint32_t reserved_6b8; + uint32_t reserved_6bc; + uint32_t reserved_6c0; + uint32_t reserved_6c4; + uint32_t reserved_6c8; + uint32_t reserved_6cc; + uint32_t reserved_6d0; + uint32_t reserved_6d4; + uint32_t reserved_6d8; + uint32_t reserved_6dc; + uint32_t reserved_6e0; + uint32_t reserved_6e4; + uint32_t reserved_6e8; + uint32_t reserved_6ec; + uint32_t reserved_6f0; + uint32_t reserved_6f4; + uint32_t reserved_6f8; + uint32_t reserved_6fc; + uint32_t reserved_700; + uint32_t reserved_704; + uint32_t reserved_708; + uint32_t reserved_70c; + uint32_t reserved_710; + uint32_t reserved_714; + uint32_t reserved_718; + uint32_t reserved_71c; + uint32_t reserved_720; + uint32_t reserved_724; + uint32_t reserved_728; + uint32_t reserved_72c; + uint32_t reserved_730; + uint32_t reserved_734; + uint32_t reserved_738; + uint32_t reserved_73c; + uint32_t reserved_740; + uint32_t reserved_744; + uint32_t reserved_748; + uint32_t reserved_74c; + uint32_t reserved_750; + uint32_t reserved_754; + uint32_t reserved_758; + uint32_t reserved_75c; + uint32_t reserved_760; + uint32_t reserved_764; + uint32_t reserved_768; + uint32_t reserved_76c; + uint32_t reserved_770; + uint32_t reserved_774; + uint32_t reserved_778; + uint32_t reserved_77c; + uint32_t reserved_780; + uint32_t reserved_784; + uint32_t reserved_788; + uint32_t reserved_78c; + uint32_t reserved_790; + uint32_t reserved_794; + uint32_t reserved_798; + uint32_t reserved_79c; + uint32_t reserved_7a0; + uint32_t reserved_7a4; + uint32_t reserved_7a8; + uint32_t reserved_7ac; + uint32_t reserved_7b0; + uint32_t reserved_7b4; + uint32_t reserved_7b8; + uint32_t reserved_7bc; + uint32_t reserved_7c0; + uint32_t reserved_7c4; + uint32_t reserved_7c8; + uint32_t reserved_7cc; + uint32_t reserved_7d0; + uint32_t reserved_7d4; + uint32_t reserved_7d8; + uint32_t reserved_7dc; + uint32_t reserved_7e0; + uint32_t reserved_7e4; + uint32_t reserved_7e8; + uint32_t reserved_7ec; + uint32_t reserved_7f0; + uint32_t reserved_7f4; + uint32_t reserved_7f8; + uint32_t reserved_7fc; + uint32_t reserved_800; + uint32_t reserved_804; + uint32_t reserved_808; + uint32_t reserved_80c; + uint32_t reserved_810; + uint32_t reserved_814; + uint32_t reserved_818; + uint32_t reserved_81c; + uint32_t reserved_820; + uint32_t reserved_824; + uint32_t reserved_828; + uint32_t reserved_82c; + uint32_t reserved_830; + uint32_t reserved_834; + uint32_t reserved_838; + uint32_t reserved_83c; + uint32_t reserved_840; + uint32_t reserved_844; + uint32_t reserved_848; + uint32_t reserved_84c; + uint32_t reserved_850; + uint32_t reserved_854; + uint32_t reserved_858; + uint32_t reserved_85c; + uint32_t reserved_860; + uint32_t reserved_864; + uint32_t reserved_868; + uint32_t reserved_86c; + uint32_t reserved_870; + uint32_t reserved_874; + uint32_t reserved_878; + uint32_t reserved_87c; + uint32_t reserved_880; + uint32_t reserved_884; + uint32_t reserved_888; + uint32_t reserved_88c; + uint32_t reserved_890; + uint32_t reserved_894; + uint32_t reserved_898; + uint32_t reserved_89c; + uint32_t reserved_8a0; + uint32_t reserved_8a4; + uint32_t reserved_8a8; + uint32_t reserved_8ac; + uint32_t reserved_8b0; + uint32_t reserved_8b4; + uint32_t reserved_8b8; + uint32_t reserved_8bc; + uint32_t reserved_8c0; + uint32_t reserved_8c4; + uint32_t reserved_8c8; + uint32_t reserved_8cc; + uint32_t reserved_8d0; + uint32_t reserved_8d4; + uint32_t reserved_8d8; + uint32_t reserved_8dc; + uint32_t reserved_8e0; + uint32_t reserved_8e4; + uint32_t reserved_8e8; + uint32_t reserved_8ec; + uint32_t reserved_8f0; + uint32_t reserved_8f4; + uint32_t reserved_8f8; + uint32_t reserved_8fc; + uint32_t reserved_900; + uint32_t reserved_904; + uint32_t reserved_908; + uint32_t reserved_90c; + uint32_t reserved_910; + uint32_t reserved_914; + uint32_t reserved_918; + uint32_t reserved_91c; + uint32_t reserved_920; + uint32_t reserved_924; + uint32_t reserved_928; + uint32_t reserved_92c; + uint32_t reserved_930; + uint32_t reserved_934; + uint32_t reserved_938; + uint32_t reserved_93c; + uint32_t reserved_940; + uint32_t reserved_944; + uint32_t reserved_948; + uint32_t reserved_94c; + uint32_t reserved_950; + uint32_t reserved_954; + uint32_t reserved_958; + uint32_t reserved_95c; + uint32_t reserved_960; + uint32_t reserved_964; + uint32_t reserved_968; + uint32_t reserved_96c; + uint32_t reserved_970; + uint32_t reserved_974; + uint32_t reserved_978; + uint32_t reserved_97c; + uint32_t reserved_980; + uint32_t reserved_984; + uint32_t reserved_988; + uint32_t reserved_98c; + uint32_t reserved_990; + uint32_t reserved_994; + uint32_t reserved_998; + uint32_t reserved_99c; + uint32_t reserved_9a0; + uint32_t reserved_9a4; + uint32_t reserved_9a8; + uint32_t reserved_9ac; + uint32_t reserved_9b0; + uint32_t reserved_9b4; + uint32_t reserved_9b8; + uint32_t reserved_9bc; + uint32_t reserved_9c0; + uint32_t reserved_9c4; + uint32_t reserved_9c8; + uint32_t reserved_9cc; + uint32_t reserved_9d0; + uint32_t reserved_9d4; + uint32_t reserved_9d8; + uint32_t reserved_9dc; + uint32_t reserved_9e0; + uint32_t reserved_9e4; + uint32_t reserved_9e8; + uint32_t reserved_9ec; + uint32_t reserved_9f0; + uint32_t reserved_9f4; + uint32_t reserved_9f8; + uint32_t reserved_9fc; + uint32_t reserved_a00; + uint32_t reserved_a04; + uint32_t reserved_a08; + uint32_t reserved_a0c; + uint32_t reserved_a10; + uint32_t reserved_a14; + uint32_t reserved_a18; + uint32_t reserved_a1c; + uint32_t reserved_a20; + uint32_t reserved_a24; + uint32_t reserved_a28; + uint32_t reserved_a2c; + uint32_t reserved_a30; + uint32_t reserved_a34; + uint32_t reserved_a38; + uint32_t reserved_a3c; + uint32_t reserved_a40; + uint32_t reserved_a44; + uint32_t reserved_a48; + uint32_t reserved_a4c; + uint32_t reserved_a50; + uint32_t reserved_a54; + uint32_t reserved_a58; + uint32_t reserved_a5c; + uint32_t reserved_a60; + uint32_t reserved_a64; + uint32_t reserved_a68; + uint32_t reserved_a6c; + uint32_t reserved_a70; + uint32_t reserved_a74; + uint32_t reserved_a78; + uint32_t reserved_a7c; + uint32_t reserved_a80; + uint32_t reserved_a84; + uint32_t reserved_a88; + uint32_t reserved_a8c; + uint32_t reserved_a90; + uint32_t reserved_a94; + uint32_t reserved_a98; + uint32_t reserved_a9c; + uint32_t reserved_aa0; + uint32_t reserved_aa4; + uint32_t reserved_aa8; + uint32_t reserved_aac; + uint32_t reserved_ab0; + uint32_t reserved_ab4; + uint32_t reserved_ab8; + uint32_t reserved_abc; + uint32_t reserved_ac0; + uint32_t reserved_ac4; + uint32_t reserved_ac8; + uint32_t reserved_acc; + uint32_t reserved_ad0; + uint32_t reserved_ad4; + uint32_t reserved_ad8; + uint32_t reserved_adc; + uint32_t reserved_ae0; + uint32_t reserved_ae4; + uint32_t reserved_ae8; + uint32_t reserved_aec; + uint32_t reserved_af0; + uint32_t reserved_af4; + uint32_t reserved_af8; + uint32_t reserved_afc; + uint32_t reserved_b00; + uint32_t reserved_b04; + uint32_t reserved_b08; + uint32_t reserved_b0c; + uint32_t reserved_b10; + uint32_t reserved_b14; + uint32_t reserved_b18; + uint32_t reserved_b1c; + uint32_t reserved_b20; + uint32_t reserved_b24; + uint32_t reserved_b28; + uint32_t reserved_b2c; + uint32_t reserved_b30; + uint32_t reserved_b34; + uint32_t reserved_b38; + uint32_t reserved_b3c; + uint32_t reserved_b40; + uint32_t reserved_b44; + uint32_t reserved_b48; + uint32_t reserved_b4c; + uint32_t reserved_b50; + uint32_t reserved_b54; + uint32_t reserved_b58; + uint32_t reserved_b5c; + uint32_t reserved_b60; + uint32_t reserved_b64; + uint32_t reserved_b68; + uint32_t reserved_b6c; + uint32_t reserved_b70; + uint32_t reserved_b74; + uint32_t reserved_b78; + uint32_t reserved_b7c; + uint32_t reserved_b80; + uint32_t reserved_b84; + uint32_t reserved_b88; + uint32_t reserved_b8c; + uint32_t reserved_b90; + uint32_t reserved_b94; + uint32_t reserved_b98; + uint32_t reserved_b9c; + uint32_t reserved_ba0; + uint32_t reserved_ba4; + uint32_t reserved_ba8; + uint32_t reserved_bac; + uint32_t reserved_bb0; + uint32_t reserved_bb4; + uint32_t reserved_bb8; + uint32_t reserved_bbc; + uint32_t reserved_bc0; + uint32_t reserved_bc4; + uint32_t reserved_bc8; + uint32_t reserved_bcc; + uint32_t reserved_bd0; + uint32_t reserved_bd4; + uint32_t reserved_bd8; + uint32_t reserved_bdc; + uint32_t reserved_be0; + uint32_t reserved_be4; + uint32_t reserved_be8; + uint32_t reserved_bec; + uint32_t reserved_bf0; + uint32_t reserved_bf4; + uint32_t reserved_bf8; + uint32_t reserved_bfc; + uint32_t reserved_c00; + uint32_t reserved_c04; + uint32_t reserved_c08; + uint32_t reserved_c0c; + uint32_t reserved_c10; + uint32_t reserved_c14; + uint32_t reserved_c18; + uint32_t reserved_c1c; + uint32_t reserved_c20; + uint32_t reserved_c24; + uint32_t reserved_c28; + uint32_t reserved_c2c; + uint32_t reserved_c30; + uint32_t reserved_c34; + uint32_t reserved_c38; + uint32_t reserved_c3c; + uint32_t reserved_c40; + uint32_t reserved_c44; + uint32_t reserved_c48; + uint32_t reserved_c4c; + uint32_t reserved_c50; + uint32_t reserved_c54; + uint32_t reserved_c58; + uint32_t reserved_c5c; + uint32_t reserved_c60; + uint32_t reserved_c64; + uint32_t reserved_c68; + uint32_t reserved_c6c; + uint32_t reserved_c70; + uint32_t reserved_c74; + uint32_t reserved_c78; + uint32_t reserved_c7c; + uint32_t reserved_c80; + uint32_t reserved_c84; + uint32_t reserved_c88; + uint32_t reserved_c8c; + uint32_t reserved_c90; + uint32_t reserved_c94; + uint32_t reserved_c98; + uint32_t reserved_c9c; + uint32_t reserved_ca0; + uint32_t reserved_ca4; + uint32_t reserved_ca8; + uint32_t reserved_cac; + uint32_t reserved_cb0; + uint32_t reserved_cb4; + uint32_t reserved_cb8; + uint32_t reserved_cbc; + uint32_t reserved_cc0; + uint32_t reserved_cc4; + uint32_t reserved_cc8; + uint32_t reserved_ccc; + uint32_t reserved_cd0; + uint32_t reserved_cd4; + uint32_t reserved_cd8; + uint32_t reserved_cdc; + uint32_t reserved_ce0; + uint32_t reserved_ce4; + uint32_t reserved_ce8; + uint32_t reserved_cec; + uint32_t reserved_cf0; + uint32_t reserved_cf4; + uint32_t reserved_cf8; + uint32_t reserved_cfc; + uint32_t reserved_d00; + uint32_t reserved_d04; + uint32_t reserved_d08; + uint32_t reserved_d0c; + uint32_t reserved_d10; + uint32_t reserved_d14; + uint32_t reserved_d18; + uint32_t reserved_d1c; + uint32_t reserved_d20; + uint32_t reserved_d24; + uint32_t reserved_d28; + uint32_t reserved_d2c; + uint32_t reserved_d30; + uint32_t reserved_d34; + uint32_t reserved_d38; + uint32_t reserved_d3c; + uint32_t reserved_d40; + uint32_t reserved_d44; + uint32_t reserved_d48; + uint32_t reserved_d4c; + uint32_t reserved_d50; + uint32_t reserved_d54; + uint32_t reserved_d58; + uint32_t reserved_d5c; + uint32_t reserved_d60; + uint32_t reserved_d64; + uint32_t reserved_d68; + uint32_t reserved_d6c; + uint32_t reserved_d70; + uint32_t reserved_d74; + uint32_t reserved_d78; + uint32_t reserved_d7c; + uint32_t reserved_d80; + uint32_t reserved_d84; + uint32_t reserved_d88; + uint32_t reserved_d8c; + uint32_t reserved_d90; + uint32_t reserved_d94; + uint32_t reserved_d98; + uint32_t reserved_d9c; + uint32_t reserved_da0; + uint32_t reserved_da4; + uint32_t reserved_da8; + uint32_t reserved_dac; + uint32_t reserved_db0; + uint32_t reserved_db4; + uint32_t reserved_db8; + uint32_t reserved_dbc; + uint32_t reserved_dc0; + uint32_t reserved_dc4; + uint32_t reserved_dc8; + uint32_t reserved_dcc; + uint32_t reserved_dd0; + uint32_t reserved_dd4; + uint32_t reserved_dd8; + uint32_t reserved_ddc; + uint32_t reserved_de0; + uint32_t reserved_de4; + uint32_t reserved_de8; + uint32_t reserved_dec; + uint32_t reserved_df0; + uint32_t reserved_df4; + uint32_t reserved_df8; + uint32_t reserved_dfc; + uint32_t reserved_e00; + uint32_t reserved_e04; + uint32_t reserved_e08; + uint32_t reserved_e0c; + uint32_t reserved_e10; + uint32_t reserved_e14; + uint32_t reserved_e18; + uint32_t reserved_e1c; + uint32_t reserved_e20; + uint32_t reserved_e24; + uint32_t reserved_e28; + uint32_t reserved_e2c; + uint32_t reserved_e30; + uint32_t reserved_e34; + uint32_t reserved_e38; + uint32_t reserved_e3c; + uint32_t reserved_e40; + uint32_t reserved_e44; + uint32_t reserved_e48; + uint32_t reserved_e4c; + uint32_t reserved_e50; + uint32_t reserved_e54; + uint32_t reserved_e58; + uint32_t reserved_e5c; + uint32_t reserved_e60; + uint32_t reserved_e64; + uint32_t reserved_e68; + uint32_t reserved_e6c; + uint32_t reserved_e70; + uint32_t reserved_e74; + uint32_t reserved_e78; + uint32_t reserved_e7c; + uint32_t reserved_e80; + uint32_t reserved_e84; + uint32_t reserved_e88; + uint32_t reserved_e8c; + uint32_t reserved_e90; + uint32_t reserved_e94; + uint32_t reserved_e98; + uint32_t reserved_e9c; + uint32_t reserved_ea0; + uint32_t reserved_ea4; + uint32_t reserved_ea8; + uint32_t reserved_eac; + uint32_t reserved_eb0; + uint32_t reserved_eb4; + uint32_t reserved_eb8; + uint32_t reserved_ebc; + uint32_t reserved_ec0; + uint32_t reserved_ec4; + uint32_t reserved_ec8; + uint32_t reserved_ecc; + uint32_t reserved_ed0; + uint32_t reserved_ed4; + uint32_t reserved_ed8; + uint32_t reserved_edc; + uint32_t reserved_ee0; + uint32_t reserved_ee4; + uint32_t reserved_ee8; + uint32_t reserved_eec; + uint32_t reserved_ef0; + uint32_t reserved_ef4; + uint32_t reserved_ef8; + uint32_t reserved_efc; + uint32_t reserved_f00; + uint32_t reserved_f04; + uint32_t reserved_f08; + uint32_t reserved_f0c; + uint32_t reserved_f10; + uint32_t reserved_f14; + uint32_t reserved_f18; + uint32_t reserved_f1c; + uint32_t reserved_f20; + uint32_t reserved_f24; + uint32_t reserved_f28; + uint32_t reserved_f2c; + uint32_t reserved_f30; + uint32_t reserved_f34; + uint32_t reserved_f38; + uint32_t reserved_f3c; + uint32_t reserved_f40; + uint32_t reserved_f44; + uint32_t reserved_f48; + uint32_t reserved_f4c; + uint32_t reserved_f50; + uint32_t reserved_f54; + uint32_t reserved_f58; + uint32_t reserved_f5c; + uint32_t reserved_f60; + uint32_t reserved_f64; + uint32_t reserved_f68; + uint32_t reserved_f6c; + uint32_t reserved_f70; + uint32_t reserved_f74; + uint32_t reserved_f78; + uint32_t reserved_f7c; + uint32_t reserved_f80; + uint32_t reserved_f84; + uint32_t reserved_f88; + uint32_t reserved_f8c; + uint32_t reserved_f90; + uint32_t reserved_f94; + uint32_t reserved_f98; + uint32_t reserved_f9c; + uint32_t reserved_fa0; + uint32_t reserved_fa4; + uint32_t reserved_fa8; + uint32_t reserved_fac; + uint32_t reserved_fb0; + uint32_t reserved_fb4; + uint32_t reserved_fb8; + uint32_t reserved_fbc; + uint32_t reserved_fc0; + uint32_t reserved_fc4; + uint32_t reserved_fc8; + uint32_t reserved_fcc; + uint32_t reserved_fd0; + uint32_t reserved_fd4; + uint32_t reserved_fd8; + uint32_t reserved_fdc; + uint32_t reserved_fe0; + uint32_t reserved_fe4; + uint32_t reserved_fe8; + uint32_t reserved_fec; + uint32_t reserved_ff0; + uint32_t reserved_ff4; + uint32_t reserved_ff8; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } date; +} system_dev_t; + +extern system_dev_t SYSTEM; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/systimer_caps.h b/components/soc/soc/esp32s3/include/soc/systimer_caps.h new file mode 100644 index 000000000..f45618162 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/systimer_caps.h @@ -0,0 +1,21 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_SYSTIMER_COUNTER_NUM (2) // Number of counter units +#define SOC_SYSTIMER_ALARM_NUM (3) // Number of alarm units + +#define SOC_SYSTIMER_BIT_WIDTH_LO (26) // Bit width of systimer low part +#define SOC_SYSTIMER_BIT_WIDTH_HI (26) // Bit width of systimer high part diff --git a/components/soc/soc/esp32s3/include/soc/timer_group_caps.h b/components/soc/soc/esp32s3/include/soc/timer_group_caps.h new file mode 100644 index 000000000..67d138d9c --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/timer_group_caps.h @@ -0,0 +1,17 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#define SOC_TIMER_GROUP_SUPPORT_XTAL diff --git a/components/soc/soc/esp32s3/include/soc/timer_group_reg.h b/components/soc/soc/esp32s3/include/soc/timer_group_reg.h new file mode 100644 index 000000000..5d4fbbe8b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/timer_group_reg.h @@ -0,0 +1,508 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define TIMG_T0CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0000) +/* TIMG_T0_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_EN (BIT(31)) +#define TIMG_T0_EN_M (BIT(31)) +#define TIMG_T0_EN_V 0x1 +#define TIMG_T0_EN_S 31 +/* TIMG_T0_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_T0_INCREASE (BIT(30)) +#define TIMG_T0_INCREASE_M (BIT(30)) +#define TIMG_T0_INCREASE_V 0x1 +#define TIMG_T0_INCREASE_S 30 +/* TIMG_T0_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_T0_AUTORELOAD (BIT(29)) +#define TIMG_T0_AUTORELOAD_M (BIT(29)) +#define TIMG_T0_AUTORELOAD_V 0x1 +#define TIMG_T0_AUTORELOAD_S 29 +/* TIMG_T0_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: */ +#define TIMG_T0_DIVIDER 0x0000FFFF +#define TIMG_T0_DIVIDER_M ((TIMG_T0_DIVIDER_V) << (TIMG_T0_DIVIDER_S)) +#define TIMG_T0_DIVIDER_V 0xFFFF +#define TIMG_T0_DIVIDER_S 13 +/* TIMG_T0_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_ALARM_EN (BIT(10)) +#define TIMG_T0_ALARM_EN_M (BIT(10)) +#define TIMG_T0_ALARM_EN_V 0x1 +#define TIMG_T0_ALARM_EN_S 10 +/* TIMG_T0_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define TIMG_T0_USE_XTAL (BIT(9)) +#define TIMG_T0_USE_XTAL_M (BIT(9)) +#define TIMG_T0_USE_XTAL_V 0x1 +#define TIMG_T0_USE_XTAL_S 9 + +#define TIMG_T0LO_REG(i) (REG_TIMG_BASE(i) + 0x0004) +/* TIMG_T0_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_LO 0xFFFFFFFF +#define TIMG_T0_LO_M ((TIMG_T0_LO_V) << (TIMG_T0_LO_S)) +#define TIMG_T0_LO_V 0xFFFFFFFF +#define TIMG_T0_LO_S 0 + +#define TIMG_T0HI_REG(i) (REG_TIMG_BASE(i) + 0x0008) +/* TIMG_T0_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T0_HI 0x003FFFFF +#define TIMG_T0_HI_M ((TIMG_T0_HI_V) << (TIMG_T0_HI_S)) +#define TIMG_T0_HI_V 0x3FFFFF +#define TIMG_T0_HI_S 0 + +#define TIMG_T0UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x000c) +/* TIMG_T0_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_UPDATE (BIT(31)) +#define TIMG_T0_UPDATE_M (BIT(31)) +#define TIMG_T0_UPDATE_V 0x1 +#define TIMG_T0_UPDATE_S 31 + +#define TIMG_T0ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0010) +/* TIMG_T0_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_ALARM_LO 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_M ((TIMG_T0_ALARM_LO_V) << (TIMG_T0_ALARM_LO_S)) +#define TIMG_T0_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T0_ALARM_LO_S 0 + +#define TIMG_T0ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0014) +/* TIMG_T0_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T0_ALARM_HI 0x003FFFFF +#define TIMG_T0_ALARM_HI_M ((TIMG_T0_ALARM_HI_V) << (TIMG_T0_ALARM_HI_S)) +#define TIMG_T0_ALARM_HI_V 0x3FFFFF +#define TIMG_T0_ALARM_HI_S 0 + +#define TIMG_T0LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x0018) +/* TIMG_T0_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_LOAD_LO 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_M ((TIMG_T0_LOAD_LO_V) << (TIMG_T0_LOAD_LO_S)) +#define TIMG_T0_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T0_LOAD_LO_S 0 + +#define TIMG_T0LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x001c) +/* TIMG_T0_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T0_LOAD_HI 0x003FFFFF +#define TIMG_T0_LOAD_HI_M ((TIMG_T0_LOAD_HI_V) << (TIMG_T0_LOAD_HI_S)) +#define TIMG_T0_LOAD_HI_V 0x3FFFFF +#define TIMG_T0_LOAD_HI_S 0 + +#define TIMG_T0LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0020) +/* TIMG_T0_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T0_LOAD 0xFFFFFFFF +#define TIMG_T0_LOAD_M ((TIMG_T0_LOAD_V) << (TIMG_T0_LOAD_S)) +#define TIMG_T0_LOAD_V 0xFFFFFFFF +#define TIMG_T0_LOAD_S 0 + +#define TIMG_T1CONFIG_REG(i) (REG_TIMG_BASE(i) + 0x0024) +/* TIMG_T1_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T1_EN (BIT(31)) +#define TIMG_T1_EN_M (BIT(31)) +#define TIMG_T1_EN_V 0x1 +#define TIMG_T1_EN_S 31 +/* TIMG_T1_INCREASE : R/W ;bitpos:[30] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_T1_INCREASE (BIT(30)) +#define TIMG_T1_INCREASE_M (BIT(30)) +#define TIMG_T1_INCREASE_V 0x1 +#define TIMG_T1_INCREASE_S 30 +/* TIMG_T1_AUTORELOAD : R/W ;bitpos:[29] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_T1_AUTORELOAD (BIT(29)) +#define TIMG_T1_AUTORELOAD_M (BIT(29)) +#define TIMG_T1_AUTORELOAD_V 0x1 +#define TIMG_T1_AUTORELOAD_S 29 +/* TIMG_T1_DIVIDER : R/W ;bitpos:[28:13] ;default: 16'h1 ; */ +/*description: */ +#define TIMG_T1_DIVIDER 0x0000FFFF +#define TIMG_T1_DIVIDER_M ((TIMG_T1_DIVIDER_V) << (TIMG_T1_DIVIDER_S)) +#define TIMG_T1_DIVIDER_V 0xFFFF +#define TIMG_T1_DIVIDER_S 13 +/* TIMG_T1_ALARM_EN : R/W ;bitpos:[10] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T1_ALARM_EN (BIT(10)) +#define TIMG_T1_ALARM_EN_M (BIT(10)) +#define TIMG_T1_ALARM_EN_V 0x1 +#define TIMG_T1_ALARM_EN_S 10 +/* TIMG_T1_USE_XTAL : R/W ;bitpos:[9] ;default: 1'd0 ; */ +/*description: */ +#define TIMG_T1_USE_XTAL (BIT(9)) +#define TIMG_T1_USE_XTAL_M (BIT(9)) +#define TIMG_T1_USE_XTAL_V 0x1 +#define TIMG_T1_USE_XTAL_S 9 + +#define TIMG_T1LO_REG(i) (REG_TIMG_BASE(i) + 0x0028) +/* TIMG_T1_LO : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T1_LO 0xFFFFFFFF +#define TIMG_T1_LO_M ((TIMG_T1_LO_V) << (TIMG_T1_LO_S)) +#define TIMG_T1_LO_V 0xFFFFFFFF +#define TIMG_T1_LO_S 0 + +#define TIMG_T1HI_REG(i) (REG_TIMG_BASE(i) + 0x002c) +/* TIMG_T1_HI : RO ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T1_HI 0x003FFFFF +#define TIMG_T1_HI_M ((TIMG_T1_HI_V) << (TIMG_T1_HI_S)) +#define TIMG_T1_HI_V 0x3FFFFF +#define TIMG_T1_HI_S 0 + +#define TIMG_T1UPDATE_REG(i) (REG_TIMG_BASE(i) + 0x0030) +/* TIMG_T1_UPDATE : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T1_UPDATE (BIT(31)) +#define TIMG_T1_UPDATE_M (BIT(31)) +#define TIMG_T1_UPDATE_V 0x1 +#define TIMG_T1_UPDATE_S 31 + +#define TIMG_T1ALARMLO_REG(i) (REG_TIMG_BASE(i) + 0x0034) +/* TIMG_T1_ALARM_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T1_ALARM_LO 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_M ((TIMG_T1_ALARM_LO_V) << (TIMG_T1_ALARM_LO_S)) +#define TIMG_T1_ALARM_LO_V 0xFFFFFFFF +#define TIMG_T1_ALARM_LO_S 0 + +#define TIMG_T1ALARMHI_REG(i) (REG_TIMG_BASE(i) + 0x0038) +/* TIMG_T1_ALARM_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T1_ALARM_HI 0x003FFFFF +#define TIMG_T1_ALARM_HI_M ((TIMG_T1_ALARM_HI_V) << (TIMG_T1_ALARM_HI_S)) +#define TIMG_T1_ALARM_HI_V 0x3FFFFF +#define TIMG_T1_ALARM_HI_S 0 + +#define TIMG_T1LOADLO_REG(i) (REG_TIMG_BASE(i) + 0x003c) +/* TIMG_T1_LOAD_LO : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T1_LOAD_LO 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_M ((TIMG_T1_LOAD_LO_V) << (TIMG_T1_LOAD_LO_S)) +#define TIMG_T1_LOAD_LO_V 0xFFFFFFFF +#define TIMG_T1_LOAD_LO_S 0 + +#define TIMG_T1LOADHI_REG(i) (REG_TIMG_BASE(i) + 0x0040) +/* TIMG_T1_LOAD_HI : R/W ;bitpos:[21:0] ;default: 22'h0 ; */ +/*description: */ +#define TIMG_T1_LOAD_HI 0x003FFFFF +#define TIMG_T1_LOAD_HI_M ((TIMG_T1_LOAD_HI_V) << (TIMG_T1_LOAD_HI_S)) +#define TIMG_T1_LOAD_HI_V 0x3FFFFF +#define TIMG_T1_LOAD_HI_S 0 + +#define TIMG_T1LOAD_REG(i) (REG_TIMG_BASE(i) + 0x0044) +/* TIMG_T1_LOAD : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_T1_LOAD 0xFFFFFFFF +#define TIMG_T1_LOAD_M ((TIMG_T1_LOAD_V) << (TIMG_T1_LOAD_S)) +#define TIMG_T1_LOAD_V 0xFFFFFFFF +#define TIMG_T1_LOAD_S 0 + +#define TIMG_WDTCONFIG0_REG(i) (REG_TIMG_BASE(i) + 0x0048) +/* TIMG_WDT_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_EN (BIT(31)) +#define TIMG_WDT_EN_M (BIT(31)) +#define TIMG_WDT_EN_V 0x1 +#define TIMG_WDT_EN_S 31 +/* TIMG_WDT_STG0 : R/W ;bitpos:[30:29] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG0 0x00000003 +#define TIMG_WDT_STG0_M ((TIMG_WDT_STG0_V) << (TIMG_WDT_STG0_S)) +#define TIMG_WDT_STG0_V 0x3 +#define TIMG_WDT_STG0_S 29 +/* TIMG_WDT_STG1 : R/W ;bitpos:[28:27] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG1 0x00000003 +#define TIMG_WDT_STG1_M ((TIMG_WDT_STG1_V) << (TIMG_WDT_STG1_S)) +#define TIMG_WDT_STG1_V 0x3 +#define TIMG_WDT_STG1_S 27 +/* TIMG_WDT_STG2 : R/W ;bitpos:[26:25] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG2 0x00000003 +#define TIMG_WDT_STG2_M ((TIMG_WDT_STG2_V) << (TIMG_WDT_STG2_S)) +#define TIMG_WDT_STG2_V 0x3 +#define TIMG_WDT_STG2_S 25 +/* TIMG_WDT_STG3 : R/W ;bitpos:[24:23] ;default: 2'd0 ; */ +/*description: */ +#define TIMG_WDT_STG3 0x00000003 +#define TIMG_WDT_STG3_M ((TIMG_WDT_STG3_V) << (TIMG_WDT_STG3_S)) +#define TIMG_WDT_STG3_V 0x3 +#define TIMG_WDT_STG3_S 23 +/* TIMG_WDT_CPU_RESET_LENGTH : R/W ;bitpos:[20:18] ;default: 3'h1 ; */ +/*description: */ +#define TIMG_WDT_CPU_RESET_LENGTH 0x00000007 +#define TIMG_WDT_CPU_RESET_LENGTH_M ((TIMG_WDT_CPU_RESET_LENGTH_V) << (TIMG_WDT_CPU_RESET_LENGTH_S)) +#define TIMG_WDT_CPU_RESET_LENGTH_V 0x7 +#define TIMG_WDT_CPU_RESET_LENGTH_S 18 +/* TIMG_WDT_SYS_RESET_LENGTH : R/W ;bitpos:[17:15] ;default: 3'h1 ; */ +/*description: */ +#define TIMG_WDT_SYS_RESET_LENGTH 0x00000007 +#define TIMG_WDT_SYS_RESET_LENGTH_M ((TIMG_WDT_SYS_RESET_LENGTH_V) << (TIMG_WDT_SYS_RESET_LENGTH_S)) +#define TIMG_WDT_SYS_RESET_LENGTH_V 0x7 +#define TIMG_WDT_SYS_RESET_LENGTH_S 15 +/* TIMG_WDT_FLASHBOOT_MOD_EN : R/W ;bitpos:[14] ;default: 1'h1 ; */ +/*description: */ +#define TIMG_WDT_FLASHBOOT_MOD_EN (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_M (BIT(14)) +#define TIMG_WDT_FLASHBOOT_MOD_EN_V 0x1 +#define TIMG_WDT_FLASHBOOT_MOD_EN_S 14 +/* TIMG_WDT_PROCPU_RESET_EN : R/W ;bitpos:[13] ;default: 1'd0 ; */ +/*description: */ +#define TIMG_WDT_PROCPU_RESET_EN (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_M (BIT(13)) +#define TIMG_WDT_PROCPU_RESET_EN_V 0x1 +#define TIMG_WDT_PROCPU_RESET_EN_S 13 +/* TIMG_WDT_APPCPU_RESET_EN : R/W ;bitpos:[12] ;default: 1'd0 ; */ +/*description: */ +#define TIMG_WDT_APPCPU_RESET_EN (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_M (BIT(12)) +#define TIMG_WDT_APPCPU_RESET_EN_V 0x1 +#define TIMG_WDT_APPCPU_RESET_EN_S 12 + +#define TIMG_WDTCONFIG1_REG(i) (REG_TIMG_BASE(i) + 0x004c) +/* TIMG_WDT_CLK_PRESCALE : R/W ;bitpos:[31:16] ;default: 16'h1 ; */ +/*description: */ +#define TIMG_WDT_CLK_PRESCALE 0x0000FFFF +#define TIMG_WDT_CLK_PRESCALE_M ((TIMG_WDT_CLK_PRESCALE_V) << (TIMG_WDT_CLK_PRESCALE_S)) +#define TIMG_WDT_CLK_PRESCALE_V 0xFFFF +#define TIMG_WDT_CLK_PRESCALE_S 16 + +#define TIMG_WDTCONFIG2_REG(i) (REG_TIMG_BASE(i) + 0x0050) +/* TIMG_WDT_STG0_HOLD : R/W ;bitpos:[31:0] ;default: 32'd26000000 ; */ +/*description: */ +#define TIMG_WDT_STG0_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_M ((TIMG_WDT_STG0_HOLD_V) << (TIMG_WDT_STG0_HOLD_S)) +#define TIMG_WDT_STG0_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG0_HOLD_S 0 + +#define TIMG_WDTCONFIG3_REG(i) (REG_TIMG_BASE(i) + 0x0054) +/* TIMG_WDT_STG1_HOLD : R/W ;bitpos:[31:0] ;default: 32'h7ffffff ; */ +/*description: */ +#define TIMG_WDT_STG1_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_M ((TIMG_WDT_STG1_HOLD_V) << (TIMG_WDT_STG1_HOLD_S)) +#define TIMG_WDT_STG1_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG1_HOLD_S 0 + +#define TIMG_WDTCONFIG4_REG(i) (REG_TIMG_BASE(i) + 0x0058) +/* TIMG_WDT_STG2_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: */ +#define TIMG_WDT_STG2_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_M ((TIMG_WDT_STG2_HOLD_V) << (TIMG_WDT_STG2_HOLD_S)) +#define TIMG_WDT_STG2_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG2_HOLD_S 0 + +#define TIMG_WDTCONFIG5_REG(i) (REG_TIMG_BASE(i) + 0x005c) +/* TIMG_WDT_STG3_HOLD : R/W ;bitpos:[31:0] ;default: 32'hfffff ; */ +/*description: */ +#define TIMG_WDT_STG3_HOLD 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_M ((TIMG_WDT_STG3_HOLD_V) << (TIMG_WDT_STG3_HOLD_S)) +#define TIMG_WDT_STG3_HOLD_V 0xFFFFFFFF +#define TIMG_WDT_STG3_HOLD_S 0 + +#define TIMG_WDTFEED_REG(i) (REG_TIMG_BASE(i) + 0x0060) +/* TIMG_WDT_FEED : WO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define TIMG_WDT_FEED 0xFFFFFFFF +#define TIMG_WDT_FEED_M ((TIMG_WDT_FEED_V) << (TIMG_WDT_FEED_S)) +#define TIMG_WDT_FEED_V 0xFFFFFFFF +#define TIMG_WDT_FEED_S 0 + +#define TIMG_WDTWPROTECT_REG(i) (REG_TIMG_BASE(i) + 0x0064) +/* TIMG_WDT_WKEY : R/W ;bitpos:[31:0] ;default: 32'h50d83aa1 ; */ +/*description: */ +#define TIMG_WDT_WKEY 0xFFFFFFFF +#define TIMG_WDT_WKEY_M ((TIMG_WDT_WKEY_V) << (TIMG_WDT_WKEY_S)) +#define TIMG_WDT_WKEY_V 0xFFFFFFFF +#define TIMG_WDT_WKEY_S 0 + +#define TIMG_RTCCALICFG_REG(i) (REG_TIMG_BASE(i) + 0x0068) +/* TIMG_RTC_CALI_START : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_START (BIT(31)) +#define TIMG_RTC_CALI_START_M (BIT(31)) +#define TIMG_RTC_CALI_START_V 0x1 +#define TIMG_RTC_CALI_START_S 31 +/* TIMG_RTC_CALI_MAX : R/W ;bitpos:[30:16] ;default: 15'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_MAX 0x00007FFF +#define TIMG_RTC_CALI_MAX_M ((TIMG_RTC_CALI_MAX_V) << (TIMG_RTC_CALI_MAX_S)) +#define TIMG_RTC_CALI_MAX_V 0x7FFF +#define TIMG_RTC_CALI_MAX_S 16 +/* TIMG_RTC_CALI_RDY : RO ;bitpos:[15] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_RDY (BIT(15)) +#define TIMG_RTC_CALI_RDY_M (BIT(15)) +#define TIMG_RTC_CALI_RDY_V 0x1 +#define TIMG_RTC_CALI_RDY_S 15 +/* TIMG_RTC_CALI_CLK_SEL : R/W ;bitpos:[14:13] ;default: 2'h1 ; */ +/*description: */ +#define TIMG_RTC_CALI_CLK_SEL 0x00000003 +#define TIMG_RTC_CALI_CLK_SEL_M ((TIMG_RTC_CALI_CLK_SEL_V) << (TIMG_RTC_CALI_CLK_SEL_S)) +#define TIMG_RTC_CALI_CLK_SEL_V 0x3 +#define TIMG_RTC_CALI_CLK_SEL_S 13 +/* TIMG_RTC_CALI_START_CYCLING : R/W ;bitpos:[12] ;default: 1'd1 ; */ +/*description: */ +#define TIMG_RTC_CALI_START_CYCLING (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_M (BIT(12)) +#define TIMG_RTC_CALI_START_CYCLING_V 0x1 +#define TIMG_RTC_CALI_START_CYCLING_S 12 + +#define TIMG_RTCCALICFG1_REG(i) (REG_TIMG_BASE(i) + 0x006c) +/* TIMG_RTC_CALI_VALUE : RO ;bitpos:[31:7] ;default: 25'h0 ; */ +/*description: */ +#define TIMG_RTC_CALI_VALUE 0x01FFFFFF +#define TIMG_RTC_CALI_VALUE_M ((TIMG_RTC_CALI_VALUE_V) << (TIMG_RTC_CALI_VALUE_S)) +#define TIMG_RTC_CALI_VALUE_V 0x1FFFFFF +#define TIMG_RTC_CALI_VALUE_S 7 +/* TIMG_RTC_CALI_CYCLING_DATA_VLD : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define TIMG_RTC_CALI_CYCLING_DATA_VLD (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_M (BIT(0)) +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_V 0x1 +#define TIMG_RTC_CALI_CYCLING_DATA_VLD_S 0 + +#define TIMG_INT_ENA_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0070) +/* TIMG_WDT_INT_ENA : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_ENA (BIT(2)) +#define TIMG_WDT_INT_ENA_M (BIT(2)) +#define TIMG_WDT_INT_ENA_V 0x1 +#define TIMG_WDT_INT_ENA_S 2 +/* TIMG_T1_INT_ENA : R/W ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T1_INT_ENA (BIT(1)) +#define TIMG_T1_INT_ENA_M (BIT(1)) +#define TIMG_T1_INT_ENA_V 0x1 +#define TIMG_T1_INT_ENA_S 1 +/* TIMG_T0_INT_ENA : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_ENA (BIT(0)) +#define TIMG_T0_INT_ENA_M (BIT(0)) +#define TIMG_T0_INT_ENA_V 0x1 +#define TIMG_T0_INT_ENA_S 0 + +#define TIMG_INT_RAW_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0074) +/* TIMG_WDT_INT_RAW : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_RAW (BIT(2)) +#define TIMG_WDT_INT_RAW_M (BIT(2)) +#define TIMG_WDT_INT_RAW_V 0x1 +#define TIMG_WDT_INT_RAW_S 2 +/* TIMG_T1_INT_RAW : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T1_INT_RAW (BIT(1)) +#define TIMG_T1_INT_RAW_M (BIT(1)) +#define TIMG_T1_INT_RAW_V 0x1 +#define TIMG_T1_INT_RAW_S 1 +/* TIMG_T0_INT_RAW : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_RAW (BIT(0)) +#define TIMG_T0_INT_RAW_M (BIT(0)) +#define TIMG_T0_INT_RAW_V 0x1 +#define TIMG_T0_INT_RAW_S 0 + +#define TIMG_INT_ST_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x0078) +/* TIMG_WDT_INT_ST : RO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_ST (BIT(2)) +#define TIMG_WDT_INT_ST_M (BIT(2)) +#define TIMG_WDT_INT_ST_V 0x1 +#define TIMG_WDT_INT_ST_S 2 +/* TIMG_T1_INT_ST : RO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T1_INT_ST (BIT(1)) +#define TIMG_T1_INT_ST_M (BIT(1)) +#define TIMG_T1_INT_ST_V 0x1 +#define TIMG_T1_INT_ST_S 1 +/* TIMG_T0_INT_ST : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_ST (BIT(0)) +#define TIMG_T0_INT_ST_M (BIT(0)) +#define TIMG_T0_INT_ST_V 0x1 +#define TIMG_T0_INT_ST_S 0 + +#define TIMG_INT_CLR_TIMERS_REG(i) (REG_TIMG_BASE(i) + 0x007c) +/* TIMG_WDT_INT_CLR : WO ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_WDT_INT_CLR (BIT(2)) +#define TIMG_WDT_INT_CLR_M (BIT(2)) +#define TIMG_WDT_INT_CLR_V 0x1 +#define TIMG_WDT_INT_CLR_S 2 +/* TIMG_T1_INT_CLR : WO ;bitpos:[1] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T1_INT_CLR (BIT(1)) +#define TIMG_T1_INT_CLR_M (BIT(1)) +#define TIMG_T1_INT_CLR_V 0x1 +#define TIMG_T1_INT_CLR_S 1 +/* TIMG_T0_INT_CLR : WO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_T0_INT_CLR (BIT(0)) +#define TIMG_T0_INT_CLR_M (BIT(0)) +#define TIMG_T0_INT_CLR_V 0x1 +#define TIMG_T0_INT_CLR_S 0 + +#define TIMG_RTCCALICFG2_REG(i) (REG_TIMG_BASE(i) + 0x0080) +/* TIMG_RTC_CALI_TIMEOUT_THRES : R/W ;bitpos:[31:7] ;default: 25'h1ffffff ; */ +/*description: timeout if cali value counts over threshold*/ +#define TIMG_RTC_CALI_TIMEOUT_THRES 0x01FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_M ((TIMG_RTC_CALI_TIMEOUT_THRES_V) << (TIMG_RTC_CALI_TIMEOUT_THRES_S)) +#define TIMG_RTC_CALI_TIMEOUT_THRES_V 0x1FFFFFF +#define TIMG_RTC_CALI_TIMEOUT_THRES_S 7 +/* TIMG_RTC_CALI_TIMEOUT_RST_CNT : R/W ;bitpos:[6:3] ;default: 4'd3 ; */ +/*description: Cycles that release calibration timeout reset*/ +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT 0x0000000F +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_M ((TIMG_RTC_CALI_TIMEOUT_RST_CNT_V) << (TIMG_RTC_CALI_TIMEOUT_RST_CNT_S)) +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_V 0xF +#define TIMG_RTC_CALI_TIMEOUT_RST_CNT_S 3 +/* TIMG_RTC_CALI_TIMEOUT : RO ;bitpos:[0] ;default: 1'h0 ; */ +/*description: timeout indicator*/ +#define TIMG_RTC_CALI_TIMEOUT (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_M (BIT(0)) +#define TIMG_RTC_CALI_TIMEOUT_V 0x1 +#define TIMG_RTC_CALI_TIMEOUT_S 0 + +#define TIMG_NTIMERS_DATE_REG(i) (REG_TIMG_BASE(i) + 0x00f8) +/* TIMG_NTIMERS_DATE : R/W ;bitpos:[27:0] ;default: 28'h2003071 ; */ +/*description: */ +#define TIMG_NTIMERS_DATE 0x0FFFFFFF +#define TIMG_NTIMERS_DATE_M ((TIMG_NTIMERS_DATE_V) << (TIMG_NTIMERS_DATE_S)) +#define TIMG_NTIMERS_DATE_V 0xFFFFFFF +#define TIMG_NTIMERS_DATE_S 0 + +#define TIMG_CLK_REG(i) (REG_TIMG_BASE(i) + 0x00fc) +/* TIMG_CLK_EN : R/W ;bitpos:[31] ;default: 1'h0 ; */ +/*description: */ +#define TIMG_CLK_EN (BIT(31)) +#define TIMG_CLK_EN_M (BIT(31)) +#define TIMG_CLK_EN_V 0x1 +#define TIMG_CLK_EN_S 31 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/timer_group_struct.h b/components/soc/soc/esp32s3/include/soc/timer_group_struct.h new file mode 100644 index 000000000..351784193 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/timer_group_struct.h @@ -0,0 +1,216 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + struct { + union { + struct { + uint32_t reserved0: 9; + uint32_t use_xtal: 1; + uint32_t alarm_en: 1; + uint32_t reserved11: 1; + uint32_t reserved12: 1; + uint32_t divider: 16; + uint32_t autoreload: 1; + uint32_t increase: 1; + uint32_t enable: 1; + }; + uint32_t val; + } config; + uint32_t cnt_low; /**/ + union { + struct { + uint32_t hi: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } cnt_high; + union { + struct { + uint32_t reserved0: 31; + uint32_t update: 1; + }; + uint32_t val; + } update; + uint32_t alarm_low; /**/ + union { + struct { + uint32_t alarm_hi: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } alarm_high; + uint32_t load_low; /**/ + union { + struct { + uint32_t load_hi: 22; + uint32_t reserved22: 10; + }; + uint32_t val; + } load_high; + uint32_t reload; /**/ + } hw_timer[2]; + union { + struct { + uint32_t reserved0: 12; + uint32_t appcpu_reset_en: 1; + uint32_t procpu_reset_en: 1; + uint32_t flashboot_mod_en: 1; + uint32_t sys_reset_length: 3; + uint32_t cpu_reset_length: 3; + uint32_t reserved21: 1; + uint32_t reserved22: 1; + uint32_t stg3: 2; + uint32_t stg2: 2; + uint32_t stg1: 2; + uint32_t stg0: 2; + uint32_t en: 1; + }; + uint32_t val; + } wdt_config0; + union { + struct { + uint32_t reserved0: 16; + uint32_t clk_prescale: 16; + }; + uint32_t val; + } wdt_config1; + uint32_t wdt_config2; /**/ + uint32_t wdt_config3; /**/ + uint32_t wdt_config4; /**/ + uint32_t wdt_config5; /**/ + uint32_t wdt_feed; /**/ + uint32_t wdt_wprotect; /**/ + union { + struct { + uint32_t reserved0: 12; + uint32_t start_cycling: 1; + uint32_t clk_sel: 2; + uint32_t rdy: 1; + uint32_t max: 15; + uint32_t start: 1; + }; + uint32_t val; + } rtc_cali_cfg; + union { + struct { + uint32_t cycling_data_vld: 1; + uint32_t reserved1: 6; + uint32_t value: 25; + }; + uint32_t val; + } rtc_cali_cfg1; + union { + struct { + uint32_t t0: 1; + uint32_t t1: 1; + uint32_t wdt: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t t0: 1; + uint32_t t1: 1; + uint32_t wdt: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t t0: 1; + uint32_t t1: 1; + uint32_t wdt: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t t0: 1; + uint32_t t1: 1; + uint32_t wdt: 1; + uint32_t reserved3: 29; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t timeout: 1; /*timeout indicator*/ + uint32_t reserved1: 2; + uint32_t timeout_rst_cnt: 4; /*Cycles that release calibration timeout reset*/ + uint32_t timeout_thres: 25; /*timeout if cali value counts over threshold*/ + }; + uint32_t val; + } rtc_cali_cfg2; + uint32_t reserved_84; + uint32_t reserved_88; + uint32_t reserved_8c; + uint32_t reserved_90; + uint32_t reserved_94; + uint32_t reserved_98; + uint32_t reserved_9c; + uint32_t reserved_a0; + uint32_t reserved_a4; + uint32_t reserved_a8; + uint32_t reserved_ac; + uint32_t reserved_b0; + uint32_t reserved_b4; + uint32_t reserved_b8; + uint32_t reserved_bc; + uint32_t reserved_c0; + uint32_t reserved_c4; + uint32_t reserved_c8; + uint32_t reserved_cc; + uint32_t reserved_d0; + uint32_t reserved_d4; + uint32_t reserved_d8; + uint32_t reserved_dc; + uint32_t reserved_e0; + uint32_t reserved_e4; + uint32_t reserved_e8; + uint32_t reserved_ec; + uint32_t reserved_f0; + uint32_t reserved_f4; + union { + struct { + uint32_t date: 28; + uint32_t reserved28: 4; + }; + uint32_t val; + } timg_date; + union { + struct { + uint32_t reserved0: 31; + uint32_t en: 1; + }; + uint32_t val; + } clk; +} timg_dev_t; + +extern timg_dev_t TIMERG0; +extern timg_dev_t TIMERG1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/touch_channel.h b/components/soc/soc/esp32s3/include/soc/touch_channel.h new file mode 100644 index 000000000..d0921c59a --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/touch_channel.h @@ -0,0 +1,46 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +//Touch channels +#define TOUCH_PAD_GPIO4_CHANNEL TOUCH_PAD_NUM0 +#define TOUCH_PAD_NUM0_GPIO_NUM 4 + +#define TOUCH_PAD_GPIO0_CHANNEL TOUCH_PAD_NUM1 +#define TOUCH_PAD_NUM1_GPIO_NUM 0 + +#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2 +#define TOUCH_PAD_NUM2_GPIO_NUM 2 + +#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3 +#define TOUCH_PAD_NUM3_GPIO_NUM 15 + +#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4 +#define TOUCH_PAD_NUM4_GPIO_NUM 13 + +#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5 +#define TOUCH_PAD_NUM5_GPIO_NUM 12 + +#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6 +#define TOUCH_PAD_NUM6_GPIO_NUM 14 + +#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7 +#define TOUCH_PAD_NUM7_GPIO_NUM 27 + +#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8 +#define TOUCH_PAD_NUM8_GPIO_NUM 33 + +#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9 +#define TOUCH_PAD_NUM9_GPIO_NUM 32 diff --git a/components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h b/components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h new file mode 100644 index 000000000..0860bd838 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/touch_sensor_caps.h @@ -0,0 +1,33 @@ +// Copyright 2019-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define SOC_TOUCH_SENSOR_NUM (15) +#define SOC_TOUCH_SENSOR_BIT_MASK_MAX (0x7fff) + +#define SOC_TOUCH_PAD_MEASURE_WAIT (0xFF) +#define SOC_TOUCH_PAD_THRESHOLD_MAX (0x1FFFFF) + +#define SOC_TOUCH_SHIELD_CHANNEL (14) +#define SOC_TOUCH_DENOISE_CHANNEL (0) +#define SOC_TOUCH_PROXIMITY_CHANNEL_NUM (3) + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/touch_sensor_channel.h b/components/soc/soc/esp32s3/include/soc/touch_sensor_channel.h new file mode 100644 index 000000000..5979f149b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/touch_sensor_channel.h @@ -0,0 +1,44 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +/* Note: T0 is an internal channel that does not have a corresponding external GPIO. */ + +#define TOUCH_PAD_GPIO1_CHANNEL TOUCH_PAD_NUM1 +#define TOUCH_PAD_NUM1_GPIO_NUM 1 + +#define TOUCH_PAD_GPIO2_CHANNEL TOUCH_PAD_NUM2 +#define TOUCH_PAD_NUM2_GPIO_NUM 2 + +#define TOUCH_PAD_GPIO15_CHANNEL TOUCH_PAD_NUM3 +#define TOUCH_PAD_NUM3_GPIO_NUM 15 + +#define TOUCH_PAD_GPIO13_CHANNEL TOUCH_PAD_NUM4 +#define TOUCH_PAD_NUM4_GPIO_NUM 13 + +#define TOUCH_PAD_GPIO12_CHANNEL TOUCH_PAD_NUM5 +#define TOUCH_PAD_NUM5_GPIO_NUM 12 + +#define TOUCH_PAD_GPIO14_CHANNEL TOUCH_PAD_NUM6 +#define TOUCH_PAD_NUM6_GPIO_NUM 14 + +#define TOUCH_PAD_GPIO27_CHANNEL TOUCH_PAD_NUM7 +#define TOUCH_PAD_NUM7_GPIO_NUM 27 + +#define TOUCH_PAD_GPIO33_CHANNEL TOUCH_PAD_NUM8 +#define TOUCH_PAD_NUM8_GPIO_NUM 33 + +#define TOUCH_PAD_GPIO32_CHANNEL TOUCH_PAD_NUM9 +#define TOUCH_PAD_NUM9_GPIO_NUM 32 diff --git a/components/soc/soc/esp32s3/include/soc/uart_caps.h b/components/soc/soc/esp32s3/include/soc/uart_caps.h new file mode 100644 index 000000000..767c06765 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/uart_caps.h @@ -0,0 +1,32 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#define UART_FIFO_LEN (128) /*!< The UART hardware FIFO length */ +#define UART_BITRATE_MAX (5000000) /*!< Max bit rate supported by UART */ + +// ESP32-S3 have 2 UART +#define SOC_UART_NUM (2) +#define SOC_UART_MIN_WAKEUP_THRESH (2) +#define UART_INTR_MASK (0x7ffff) //All interrupt mask + +#ifdef __cplusplus +} +#endif + diff --git a/components/soc/soc/esp32s3/include/soc/uart_channel.h b/components/soc/soc/esp32s3/include/soc/uart_channel.h new file mode 100644 index 000000000..0475fd3b5 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/uart_channel.h @@ -0,0 +1,58 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at + +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +//UART channels +#define UART_GPIO1_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_TXD_DIRECT_GPIO_NUM 1 +#define UART_GPIO3_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RXD_DIRECT_GPIO_NUM 3 +#define UART_GPIO19_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_CTS_DIRECT_GPIO_NUM 19 +#define UART_GPIO22_DIRECT_CHANNEL UART_NUM_0 +#define UART_NUM_0_RTS_DIRECT_GPIO_NUM 22 + +#define UART_TXD_GPIO1_DIRECT_CHANNEL UART_GPIO1_DIRECT_CHANNEL +#define UART_RXD_GPIO3_DIRECT_CHANNEL UART_GPIO3_DIRECT_CHANNEL +#define UART_CTS_GPIO19_DIRECT_CHANNEL UART_GPIO19_DIRECT_CHANNEL +#define UART_RTS_GPIO22_DIRECT_CHANNEL UART_GPIO22_DIRECT_CHANNEL + +#define UART_GPIO10_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_TXD_DIRECT_GPIO_NUM 10 +#define UART_GPIO9_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_RXD_DIRECT_GPIO_NUM 9 +#define UART_GPIO6_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_CTS_DIRECT_GPIO_NUM 6 +#define UART_GPIO11_DIRECT_CHANNEL UART_NUM_1 +#define UART_NUM_1_RTS_DIRECT_GPIO_NUM 11 + +#define UART_TXD_GPIO10_DIRECT_CHANNEL UART_GPIO10_DIRECT_CHANNEL +#define UART_RXD_GPIO9_DIRECT_CHANNEL UART_GPIO9_DIRECT_CHANNEL +#define UART_CTS_GPIO6_DIRECT_CHANNEL UART_GPIO6_DIRECT_CHANNEL +#define UART_RTS_GPIO11_DIRECT_CHANNEL UART_GPIO11_DIRECT_CHANNEL + +#define UART_GPIO17_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_TXD_DIRECT_GPIO_NUM 17 +#define UART_GPIO16_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_RXD_DIRECT_GPIO_NUM 16 +#define UART_GPIO8_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_CTS_DIRECT_GPIO_NUM 8 +#define UART_GPIO7_DIRECT_CHANNEL UART_NUM_2 +#define UART_NUM_2_RTS_DIRECT_GPIO_NUM 7 + +#define UART_TXD_GPIO17_DIRECT_CHANNEL UART_GPIO17_DIRECT_CHANNEL +#define UART_RXD_GPIO16_DIRECT_CHANNEL UART_GPIO16_DIRECT_CHANNEL +#define UART_CTS_GPIO8_DIRECT_CHANNEL UART_GPIO8_DIRECT_CHANNEL +#define UART_RTS_GPIO7_DIRECT_CHANNEL UART_GPIO7_DIRECT_CHANNEL diff --git a/components/soc/soc/esp32s3/include/soc/uart_reg.h b/components/soc/soc/esp32s3/include/soc/uart_reg.h new file mode 100644 index 000000000..b992b43a0 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/uart_reg.h @@ -0,0 +1,1180 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define UART_FIFO_REG(i) (REG_UART_BASE(i) + 0x0) +/* UART_RXFIFO_RD_BYTE : RO ;bitpos:[7:0] ;default: 8'b0 ; */ +/*description: */ +#define UART_RXFIFO_RD_BYTE 0x000000FF +#define UART_RXFIFO_RD_BYTE_M ((UART_RXFIFO_RD_BYTE_V) << (UART_RXFIFO_RD_BYTE_S)) +#define UART_RXFIFO_RD_BYTE_V 0xFF +#define UART_RXFIFO_RD_BYTE_S 0 + +#define UART_INT_RAW_REG(i) (REG_UART_BASE(i) + 0x4) +/* UART_WAKEUP_INT_RAW : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define UART_WAKEUP_INT_RAW (BIT(19)) +#define UART_WAKEUP_INT_RAW_M (BIT(19)) +#define UART_WAKEUP_INT_RAW_V 0x1 +#define UART_WAKEUP_INT_RAW_S 19 +/* UART_AT_CMD_CHAR_DET_INT_RAW : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define UART_AT_CMD_CHAR_DET_INT_RAW (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_RAW_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_RAW_S 18 +/* UART_RS485_CLASH_INT_RAW : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_CLASH_INT_RAW (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_M (BIT(17)) +#define UART_RS485_CLASH_INT_RAW_V 0x1 +#define UART_RS485_CLASH_INT_RAW_S 17 +/* UART_RS485_FRM_ERR_INT_RAW : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_FRM_ERR_INT_RAW (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_RAW_V 0x1 +#define UART_RS485_FRM_ERR_INT_RAW_S 16 +/* UART_RS485_PARITY_ERR_INT_RAW : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_PARITY_ERR_INT_RAW (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_RAW_V 0x1 +#define UART_RS485_PARITY_ERR_INT_RAW_S 15 +/* UART_TX_DONE_INT_RAW : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_DONE_INT_RAW (BIT(14)) +#define UART_TX_DONE_INT_RAW_M (BIT(14)) +#define UART_TX_DONE_INT_RAW_V 0x1 +#define UART_TX_DONE_INT_RAW_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_RAW : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_IDLE_DONE_INT_RAW (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_RAW_S 13 +/* UART_TX_BRK_DONE_INT_RAW : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_DONE_INT_RAW (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_RAW_V 0x1 +#define UART_TX_BRK_DONE_INT_RAW_S 12 +/* UART_GLITCH_DET_INT_RAW : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UART_GLITCH_DET_INT_RAW (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_M (BIT(11)) +#define UART_GLITCH_DET_INT_RAW_V 0x1 +#define UART_GLITCH_DET_INT_RAW_S 11 +/* UART_SW_XOFF_INT_RAW : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XOFF_INT_RAW (BIT(10)) +#define UART_SW_XOFF_INT_RAW_M (BIT(10)) +#define UART_SW_XOFF_INT_RAW_V 0x1 +#define UART_SW_XOFF_INT_RAW_S 10 +/* UART_SW_XON_INT_RAW : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XON_INT_RAW (BIT(9)) +#define UART_SW_XON_INT_RAW_M (BIT(9)) +#define UART_SW_XON_INT_RAW_V 0x1 +#define UART_SW_XON_INT_RAW_S 9 +/* UART_RXFIFO_TOUT_INT_RAW : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_TOUT_INT_RAW (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_RAW_V 0x1 +#define UART_RXFIFO_TOUT_INT_RAW_S 8 +/* UART_BRK_DET_INT_RAW : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UART_BRK_DET_INT_RAW (BIT(7)) +#define UART_BRK_DET_INT_RAW_M (BIT(7)) +#define UART_BRK_DET_INT_RAW_V 0x1 +#define UART_BRK_DET_INT_RAW_S 7 +/* UART_CTS_CHG_INT_RAW : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UART_CTS_CHG_INT_RAW (BIT(6)) +#define UART_CTS_CHG_INT_RAW_M (BIT(6)) +#define UART_CTS_CHG_INT_RAW_V 0x1 +#define UART_CTS_CHG_INT_RAW_S 6 +/* UART_DSR_CHG_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UART_DSR_CHG_INT_RAW (BIT(5)) +#define UART_DSR_CHG_INT_RAW_M (BIT(5)) +#define UART_DSR_CHG_INT_RAW_V 0x1 +#define UART_DSR_CHG_INT_RAW_S 5 +/* UART_RXFIFO_OVF_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_OVF_INT_RAW (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_RAW_V 0x1 +#define UART_RXFIFO_OVF_INT_RAW_S 4 +/* UART_FRM_ERR_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UART_FRM_ERR_INT_RAW (BIT(3)) +#define UART_FRM_ERR_INT_RAW_M (BIT(3)) +#define UART_FRM_ERR_INT_RAW_V 0x1 +#define UART_FRM_ERR_INT_RAW_S 3 +/* UART_PARITY_ERR_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UART_PARITY_ERR_INT_RAW (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_M (BIT(2)) +#define UART_PARITY_ERR_INT_RAW_V 0x1 +#define UART_PARITY_ERR_INT_RAW_S 2 +/* UART_TXFIFO_EMPTY_INT_RAW : RO ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define UART_TXFIFO_EMPTY_INT_RAW (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_RAW_V 0x1 +#define UART_TXFIFO_EMPTY_INT_RAW_S 1 +/* UART_RXFIFO_FULL_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_FULL_INT_RAW (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_RAW_V 0x1 +#define UART_RXFIFO_FULL_INT_RAW_S 0 + +#define UART_INT_ST_REG(i) (REG_UART_BASE(i) + 0x8) +/* UART_WAKEUP_INT_ST : RO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define UART_WAKEUP_INT_ST (BIT(19)) +#define UART_WAKEUP_INT_ST_M (BIT(19)) +#define UART_WAKEUP_INT_ST_V 0x1 +#define UART_WAKEUP_INT_ST_S 19 +/* UART_AT_CMD_CHAR_DET_INT_ST : RO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define UART_AT_CMD_CHAR_DET_INT_ST (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ST_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ST_S 18 +/* UART_RS485_CLASH_INT_ST : RO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_CLASH_INT_ST (BIT(17)) +#define UART_RS485_CLASH_INT_ST_M (BIT(17)) +#define UART_RS485_CLASH_INT_ST_V 0x1 +#define UART_RS485_CLASH_INT_ST_S 17 +/* UART_RS485_FRM_ERR_INT_ST : RO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_FRM_ERR_INT_ST (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ST_V 0x1 +#define UART_RS485_FRM_ERR_INT_ST_S 16 +/* UART_RS485_PARITY_ERR_INT_ST : RO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_PARITY_ERR_INT_ST (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ST_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ST_S 15 +/* UART_TX_DONE_INT_ST : RO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_DONE_INT_ST (BIT(14)) +#define UART_TX_DONE_INT_ST_M (BIT(14)) +#define UART_TX_DONE_INT_ST_V 0x1 +#define UART_TX_DONE_INT_ST_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ST : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_IDLE_DONE_INT_ST (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ST_S 13 +/* UART_TX_BRK_DONE_INT_ST : RO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_DONE_INT_ST (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ST_V 0x1 +#define UART_TX_BRK_DONE_INT_ST_S 12 +/* UART_GLITCH_DET_INT_ST : RO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UART_GLITCH_DET_INT_ST (BIT(11)) +#define UART_GLITCH_DET_INT_ST_M (BIT(11)) +#define UART_GLITCH_DET_INT_ST_V 0x1 +#define UART_GLITCH_DET_INT_ST_S 11 +/* UART_SW_XOFF_INT_ST : RO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XOFF_INT_ST (BIT(10)) +#define UART_SW_XOFF_INT_ST_M (BIT(10)) +#define UART_SW_XOFF_INT_ST_V 0x1 +#define UART_SW_XOFF_INT_ST_S 10 +/* UART_SW_XON_INT_ST : RO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XON_INT_ST (BIT(9)) +#define UART_SW_XON_INT_ST_M (BIT(9)) +#define UART_SW_XON_INT_ST_V 0x1 +#define UART_SW_XON_INT_ST_S 9 +/* UART_RXFIFO_TOUT_INT_ST : RO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_TOUT_INT_ST (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ST_V 0x1 +#define UART_RXFIFO_TOUT_INT_ST_S 8 +/* UART_BRK_DET_INT_ST : RO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UART_BRK_DET_INT_ST (BIT(7)) +#define UART_BRK_DET_INT_ST_M (BIT(7)) +#define UART_BRK_DET_INT_ST_V 0x1 +#define UART_BRK_DET_INT_ST_S 7 +/* UART_CTS_CHG_INT_ST : RO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UART_CTS_CHG_INT_ST (BIT(6)) +#define UART_CTS_CHG_INT_ST_M (BIT(6)) +#define UART_CTS_CHG_INT_ST_V 0x1 +#define UART_CTS_CHG_INT_ST_S 6 +/* UART_DSR_CHG_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UART_DSR_CHG_INT_ST (BIT(5)) +#define UART_DSR_CHG_INT_ST_M (BIT(5)) +#define UART_DSR_CHG_INT_ST_V 0x1 +#define UART_DSR_CHG_INT_ST_S 5 +/* UART_RXFIFO_OVF_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_OVF_INT_ST (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ST_V 0x1 +#define UART_RXFIFO_OVF_INT_ST_S 4 +/* UART_FRM_ERR_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UART_FRM_ERR_INT_ST (BIT(3)) +#define UART_FRM_ERR_INT_ST_M (BIT(3)) +#define UART_FRM_ERR_INT_ST_V 0x1 +#define UART_FRM_ERR_INT_ST_S 3 +/* UART_PARITY_ERR_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UART_PARITY_ERR_INT_ST (BIT(2)) +#define UART_PARITY_ERR_INT_ST_M (BIT(2)) +#define UART_PARITY_ERR_INT_ST_V 0x1 +#define UART_PARITY_ERR_INT_ST_S 2 +/* UART_TXFIFO_EMPTY_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UART_TXFIFO_EMPTY_INT_ST (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ST_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ST_S 1 +/* UART_RXFIFO_FULL_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_FULL_INT_ST (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ST_V 0x1 +#define UART_RXFIFO_FULL_INT_ST_S 0 + +#define UART_INT_ENA_REG(i) (REG_UART_BASE(i) + 0xC) +/* UART_WAKEUP_INT_ENA : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define UART_WAKEUP_INT_ENA (BIT(19)) +#define UART_WAKEUP_INT_ENA_M (BIT(19)) +#define UART_WAKEUP_INT_ENA_V 0x1 +#define UART_WAKEUP_INT_ENA_S 19 +/* UART_AT_CMD_CHAR_DET_INT_ENA : R/W ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define UART_AT_CMD_CHAR_DET_INT_ENA (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_ENA_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_ENA_S 18 +/* UART_RS485_CLASH_INT_ENA : R/W ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_CLASH_INT_ENA (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_M (BIT(17)) +#define UART_RS485_CLASH_INT_ENA_V 0x1 +#define UART_RS485_CLASH_INT_ENA_S 17 +/* UART_RS485_FRM_ERR_INT_ENA : R/W ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_FRM_ERR_INT_ENA (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_ENA_V 0x1 +#define UART_RS485_FRM_ERR_INT_ENA_S 16 +/* UART_RS485_PARITY_ERR_INT_ENA : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_PARITY_ERR_INT_ENA (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_ENA_V 0x1 +#define UART_RS485_PARITY_ERR_INT_ENA_S 15 +/* UART_TX_DONE_INT_ENA : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_DONE_INT_ENA (BIT(14)) +#define UART_TX_DONE_INT_ENA_M (BIT(14)) +#define UART_TX_DONE_INT_ENA_V 0x1 +#define UART_TX_DONE_INT_ENA_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_ENA : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_IDLE_DONE_INT_ENA (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_ENA_S 13 +/* UART_TX_BRK_DONE_INT_ENA : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_DONE_INT_ENA (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_ENA_V 0x1 +#define UART_TX_BRK_DONE_INT_ENA_S 12 +/* UART_GLITCH_DET_INT_ENA : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UART_GLITCH_DET_INT_ENA (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_M (BIT(11)) +#define UART_GLITCH_DET_INT_ENA_V 0x1 +#define UART_GLITCH_DET_INT_ENA_S 11 +/* UART_SW_XOFF_INT_ENA : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XOFF_INT_ENA (BIT(10)) +#define UART_SW_XOFF_INT_ENA_M (BIT(10)) +#define UART_SW_XOFF_INT_ENA_V 0x1 +#define UART_SW_XOFF_INT_ENA_S 10 +/* UART_SW_XON_INT_ENA : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XON_INT_ENA (BIT(9)) +#define UART_SW_XON_INT_ENA_M (BIT(9)) +#define UART_SW_XON_INT_ENA_V 0x1 +#define UART_SW_XON_INT_ENA_S 9 +/* UART_RXFIFO_TOUT_INT_ENA : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_TOUT_INT_ENA (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_ENA_V 0x1 +#define UART_RXFIFO_TOUT_INT_ENA_S 8 +/* UART_BRK_DET_INT_ENA : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UART_BRK_DET_INT_ENA (BIT(7)) +#define UART_BRK_DET_INT_ENA_M (BIT(7)) +#define UART_BRK_DET_INT_ENA_V 0x1 +#define UART_BRK_DET_INT_ENA_S 7 +/* UART_CTS_CHG_INT_ENA : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UART_CTS_CHG_INT_ENA (BIT(6)) +#define UART_CTS_CHG_INT_ENA_M (BIT(6)) +#define UART_CTS_CHG_INT_ENA_V 0x1 +#define UART_CTS_CHG_INT_ENA_S 6 +/* UART_DSR_CHG_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UART_DSR_CHG_INT_ENA (BIT(5)) +#define UART_DSR_CHG_INT_ENA_M (BIT(5)) +#define UART_DSR_CHG_INT_ENA_V 0x1 +#define UART_DSR_CHG_INT_ENA_S 5 +/* UART_RXFIFO_OVF_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_OVF_INT_ENA (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_ENA_V 0x1 +#define UART_RXFIFO_OVF_INT_ENA_S 4 +/* UART_FRM_ERR_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UART_FRM_ERR_INT_ENA (BIT(3)) +#define UART_FRM_ERR_INT_ENA_M (BIT(3)) +#define UART_FRM_ERR_INT_ENA_V 0x1 +#define UART_FRM_ERR_INT_ENA_S 3 +/* UART_PARITY_ERR_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UART_PARITY_ERR_INT_ENA (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_M (BIT(2)) +#define UART_PARITY_ERR_INT_ENA_V 0x1 +#define UART_PARITY_ERR_INT_ENA_S 2 +/* UART_TXFIFO_EMPTY_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UART_TXFIFO_EMPTY_INT_ENA (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_ENA_V 0x1 +#define UART_TXFIFO_EMPTY_INT_ENA_S 1 +/* UART_RXFIFO_FULL_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_FULL_INT_ENA (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_ENA_V 0x1 +#define UART_RXFIFO_FULL_INT_ENA_S 0 + +#define UART_INT_CLR_REG(i) (REG_UART_BASE(i) + 0x10) +/* UART_WAKEUP_INT_CLR : WO ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define UART_WAKEUP_INT_CLR (BIT(19)) +#define UART_WAKEUP_INT_CLR_M (BIT(19)) +#define UART_WAKEUP_INT_CLR_V 0x1 +#define UART_WAKEUP_INT_CLR_S 19 +/* UART_AT_CMD_CHAR_DET_INT_CLR : WO ;bitpos:[18] ;default: 1'b0 ; */ +/*description: */ +#define UART_AT_CMD_CHAR_DET_INT_CLR (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_M (BIT(18)) +#define UART_AT_CMD_CHAR_DET_INT_CLR_V 0x1 +#define UART_AT_CMD_CHAR_DET_INT_CLR_S 18 +/* UART_RS485_CLASH_INT_CLR : WO ;bitpos:[17] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_CLASH_INT_CLR (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_M (BIT(17)) +#define UART_RS485_CLASH_INT_CLR_V 0x1 +#define UART_RS485_CLASH_INT_CLR_S 17 +/* UART_RS485_FRM_ERR_INT_CLR : WO ;bitpos:[16] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_FRM_ERR_INT_CLR (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_M (BIT(16)) +#define UART_RS485_FRM_ERR_INT_CLR_V 0x1 +#define UART_RS485_FRM_ERR_INT_CLR_S 16 +/* UART_RS485_PARITY_ERR_INT_CLR : WO ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_PARITY_ERR_INT_CLR (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_M (BIT(15)) +#define UART_RS485_PARITY_ERR_INT_CLR_V 0x1 +#define UART_RS485_PARITY_ERR_INT_CLR_S 15 +/* UART_TX_DONE_INT_CLR : WO ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_DONE_INT_CLR (BIT(14)) +#define UART_TX_DONE_INT_CLR_M (BIT(14)) +#define UART_TX_DONE_INT_CLR_V 0x1 +#define UART_TX_DONE_INT_CLR_S 14 +/* UART_TX_BRK_IDLE_DONE_INT_CLR : WO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_IDLE_DONE_INT_CLR (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_M (BIT(13)) +#define UART_TX_BRK_IDLE_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_IDLE_DONE_INT_CLR_S 13 +/* UART_TX_BRK_DONE_INT_CLR : WO ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_BRK_DONE_INT_CLR (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_M (BIT(12)) +#define UART_TX_BRK_DONE_INT_CLR_V 0x1 +#define UART_TX_BRK_DONE_INT_CLR_S 12 +/* UART_GLITCH_DET_INT_CLR : WO ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UART_GLITCH_DET_INT_CLR (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_M (BIT(11)) +#define UART_GLITCH_DET_INT_CLR_V 0x1 +#define UART_GLITCH_DET_INT_CLR_S 11 +/* UART_SW_XOFF_INT_CLR : WO ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XOFF_INT_CLR (BIT(10)) +#define UART_SW_XOFF_INT_CLR_M (BIT(10)) +#define UART_SW_XOFF_INT_CLR_V 0x1 +#define UART_SW_XOFF_INT_CLR_S 10 +/* UART_SW_XON_INT_CLR : WO ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_XON_INT_CLR (BIT(9)) +#define UART_SW_XON_INT_CLR_M (BIT(9)) +#define UART_SW_XON_INT_CLR_V 0x1 +#define UART_SW_XON_INT_CLR_S 9 +/* UART_RXFIFO_TOUT_INT_CLR : WO ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_TOUT_INT_CLR (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_M (BIT(8)) +#define UART_RXFIFO_TOUT_INT_CLR_V 0x1 +#define UART_RXFIFO_TOUT_INT_CLR_S 8 +/* UART_BRK_DET_INT_CLR : WO ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UART_BRK_DET_INT_CLR (BIT(7)) +#define UART_BRK_DET_INT_CLR_M (BIT(7)) +#define UART_BRK_DET_INT_CLR_V 0x1 +#define UART_BRK_DET_INT_CLR_S 7 +/* UART_CTS_CHG_INT_CLR : WO ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UART_CTS_CHG_INT_CLR (BIT(6)) +#define UART_CTS_CHG_INT_CLR_M (BIT(6)) +#define UART_CTS_CHG_INT_CLR_V 0x1 +#define UART_CTS_CHG_INT_CLR_S 6 +/* UART_DSR_CHG_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UART_DSR_CHG_INT_CLR (BIT(5)) +#define UART_DSR_CHG_INT_CLR_M (BIT(5)) +#define UART_DSR_CHG_INT_CLR_V 0x1 +#define UART_DSR_CHG_INT_CLR_S 5 +/* UART_RXFIFO_OVF_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_OVF_INT_CLR (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_M (BIT(4)) +#define UART_RXFIFO_OVF_INT_CLR_V 0x1 +#define UART_RXFIFO_OVF_INT_CLR_S 4 +/* UART_FRM_ERR_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UART_FRM_ERR_INT_CLR (BIT(3)) +#define UART_FRM_ERR_INT_CLR_M (BIT(3)) +#define UART_FRM_ERR_INT_CLR_V 0x1 +#define UART_FRM_ERR_INT_CLR_S 3 +/* UART_PARITY_ERR_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UART_PARITY_ERR_INT_CLR (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_M (BIT(2)) +#define UART_PARITY_ERR_INT_CLR_V 0x1 +#define UART_PARITY_ERR_INT_CLR_S 2 +/* UART_TXFIFO_EMPTY_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UART_TXFIFO_EMPTY_INT_CLR (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_M (BIT(1)) +#define UART_TXFIFO_EMPTY_INT_CLR_V 0x1 +#define UART_TXFIFO_EMPTY_INT_CLR_S 1 +/* UART_RXFIFO_FULL_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UART_RXFIFO_FULL_INT_CLR (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_M (BIT(0)) +#define UART_RXFIFO_FULL_INT_CLR_V 0x1 +#define UART_RXFIFO_FULL_INT_CLR_S 0 + +#define UART_CLKDIV_REG(i) (REG_UART_BASE(i) + 0x14) +/* UART_CLKDIV_FRAG : R/W ;bitpos:[23:20] ;default: 4'h0 ; */ +/*description: */ +#define UART_CLKDIV_FRAG 0x0000000F +#define UART_CLKDIV_FRAG_M ((UART_CLKDIV_FRAG_V) << (UART_CLKDIV_FRAG_S)) +#define UART_CLKDIV_FRAG_V 0xF +#define UART_CLKDIV_FRAG_S 20 +/* UART_CLKDIV : R/W ;bitpos:[11:0] ;default: 12'h2B6 ; */ +/*description: */ +#define UART_CLKDIV 0x00000FFF +#define UART_CLKDIV_M ((UART_CLKDIV_V) << (UART_CLKDIV_S)) +#define UART_CLKDIV_V 0xFFF +#define UART_CLKDIV_S 0 + +#define UART_RX_FILT_REG(i) (REG_UART_BASE(i) + 0x18) +/* UART_GLITCH_FILT_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UART_GLITCH_FILT_EN (BIT(8)) +#define UART_GLITCH_FILT_EN_M (BIT(8)) +#define UART_GLITCH_FILT_EN_V 0x1 +#define UART_GLITCH_FILT_EN_S 8 +/* UART_GLITCH_FILT : R/W ;bitpos:[7:0] ;default: 8'h8 ; */ +/*description: */ +#define UART_GLITCH_FILT 0x000000FF +#define UART_GLITCH_FILT_M ((UART_GLITCH_FILT_V) << (UART_GLITCH_FILT_S)) +#define UART_GLITCH_FILT_V 0xFF +#define UART_GLITCH_FILT_S 0 + +#define UART_STATUS_REG(i) (REG_UART_BASE(i) + 0x1C) +/* UART_TXD : RO ;bitpos:[31] ;default: 1'h1 ; */ +/*description: */ +#define UART_TXD (BIT(31)) +#define UART_TXD_M (BIT(31)) +#define UART_TXD_V 0x1 +#define UART_TXD_S 31 +/* UART_RTSN : RO ;bitpos:[30] ;default: 1'b1 ; */ +/*description: */ +#define UART_RTSN (BIT(30)) +#define UART_RTSN_M (BIT(30)) +#define UART_RTSN_V 0x1 +#define UART_RTSN_S 30 +/* UART_DTRN : RO ;bitpos:[29] ;default: 1'b1 ; */ +/*description: */ +#define UART_DTRN (BIT(29)) +#define UART_DTRN_M (BIT(29)) +#define UART_DTRN_V 0x1 +#define UART_DTRN_S 29 +/* UART_TXFIFO_CNT : RO ;bitpos:[25:16] ;default: 10'b0 ; */ +/*description: */ +#define UART_TXFIFO_CNT 0x000003FF +#define UART_TXFIFO_CNT_M ((UART_TXFIFO_CNT_V) << (UART_TXFIFO_CNT_S)) +#define UART_TXFIFO_CNT_V 0x3FF +#define UART_TXFIFO_CNT_S 16 +/* UART_RXD : RO ;bitpos:[15] ;default: 1'b1 ; */ +/*description: */ +#define UART_RXD (BIT(15)) +#define UART_RXD_M (BIT(15)) +#define UART_RXD_V 0x1 +#define UART_RXD_S 15 +/* UART_CTSN : RO ;bitpos:[14] ;default: 1'b1 ; */ +/*description: */ +#define UART_CTSN (BIT(14)) +#define UART_CTSN_M (BIT(14)) +#define UART_CTSN_V 0x1 +#define UART_CTSN_S 14 +/* UART_DSRN : RO ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UART_DSRN (BIT(13)) +#define UART_DSRN_M (BIT(13)) +#define UART_DSRN_V 0x1 +#define UART_DSRN_S 13 +/* UART_RXFIFO_CNT : RO ;bitpos:[9:0] ;default: 10'b0 ; */ +/*description: */ +#define UART_RXFIFO_CNT 0x000003FF +#define UART_RXFIFO_CNT_M ((UART_RXFIFO_CNT_V) << (UART_RXFIFO_CNT_S)) +#define UART_RXFIFO_CNT_V 0x3FF +#define UART_RXFIFO_CNT_S 0 + +#define UART_CONF0_REG(i) (REG_UART_BASE(i) + 0x20) +/* UART_MEM_CLK_EN : R/W ;bitpos:[28] ;default: 1'h1 ; */ +/*description: */ +#define UART_MEM_CLK_EN (BIT(28)) +#define UART_MEM_CLK_EN_M (BIT(28)) +#define UART_MEM_CLK_EN_V 0x1 +#define UART_MEM_CLK_EN_S 28 +/* UART_AUTOBAUD_EN : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define UART_AUTOBAUD_EN (BIT(27)) +#define UART_AUTOBAUD_EN_M (BIT(27)) +#define UART_AUTOBAUD_EN_V 0x1 +#define UART_AUTOBAUD_EN_S 27 +/* UART_ERR_WR_MASK : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define UART_ERR_WR_MASK (BIT(26)) +#define UART_ERR_WR_MASK_M (BIT(26)) +#define UART_ERR_WR_MASK_V 0x1 +#define UART_ERR_WR_MASK_S 26 +/* UART_CLK_EN : R/W ;bitpos:[25] ;default: 1'h0 ; */ +/*description: */ +#define UART_CLK_EN (BIT(25)) +#define UART_CLK_EN_M (BIT(25)) +#define UART_CLK_EN_V 0x1 +#define UART_CLK_EN_S 25 +/* UART_DTR_INV : R/W ;bitpos:[24] ;default: 1'h0 ; */ +/*description: */ +#define UART_DTR_INV (BIT(24)) +#define UART_DTR_INV_M (BIT(24)) +#define UART_DTR_INV_V 0x1 +#define UART_DTR_INV_S 24 +/* UART_RTS_INV : R/W ;bitpos:[23] ;default: 1'h0 ; */ +/*description: */ +#define UART_RTS_INV (BIT(23)) +#define UART_RTS_INV_M (BIT(23)) +#define UART_RTS_INV_V 0x1 +#define UART_RTS_INV_S 23 +/* UART_TXD_INV : R/W ;bitpos:[22] ;default: 1'h0 ; */ +/*description: */ +#define UART_TXD_INV (BIT(22)) +#define UART_TXD_INV_M (BIT(22)) +#define UART_TXD_INV_V 0x1 +#define UART_TXD_INV_S 22 +/* UART_DSR_INV : R/W ;bitpos:[21] ;default: 1'h0 ; */ +/*description: */ +#define UART_DSR_INV (BIT(21)) +#define UART_DSR_INV_M (BIT(21)) +#define UART_DSR_INV_V 0x1 +#define UART_DSR_INV_S 21 +/* UART_CTS_INV : R/W ;bitpos:[20] ;default: 1'h0 ; */ +/*description: */ +#define UART_CTS_INV (BIT(20)) +#define UART_CTS_INV_M (BIT(20)) +#define UART_CTS_INV_V 0x1 +#define UART_CTS_INV_S 20 +/* UART_RXD_INV : R/W ;bitpos:[19] ;default: 1'h0 ; */ +/*description: */ +#define UART_RXD_INV (BIT(19)) +#define UART_RXD_INV_M (BIT(19)) +#define UART_RXD_INV_V 0x1 +#define UART_RXD_INV_S 19 +/* UART_TXFIFO_RST : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: */ +#define UART_TXFIFO_RST (BIT(18)) +#define UART_TXFIFO_RST_M (BIT(18)) +#define UART_TXFIFO_RST_V 0x1 +#define UART_TXFIFO_RST_S 18 +/* UART_RXFIFO_RST : R/W ;bitpos:[17] ;default: 1'h0 ; */ +/*description: */ +#define UART_RXFIFO_RST (BIT(17)) +#define UART_RXFIFO_RST_M (BIT(17)) +#define UART_RXFIFO_RST_V 0x1 +#define UART_RXFIFO_RST_S 17 +/* UART_IRDA_EN : R/W ;bitpos:[16] ;default: 1'h0 ; */ +/*description: */ +#define UART_IRDA_EN (BIT(16)) +#define UART_IRDA_EN_M (BIT(16)) +#define UART_IRDA_EN_V 0x1 +#define UART_IRDA_EN_S 16 +/* UART_TX_FLOW_EN : R/W ;bitpos:[15] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_FLOW_EN (BIT(15)) +#define UART_TX_FLOW_EN_M (BIT(15)) +#define UART_TX_FLOW_EN_V 0x1 +#define UART_TX_FLOW_EN_S 15 +/* UART_LOOPBACK : R/W ;bitpos:[14] ;default: 1'b0 ; */ +/*description: */ +#define UART_LOOPBACK (BIT(14)) +#define UART_LOOPBACK_M (BIT(14)) +#define UART_LOOPBACK_V 0x1 +#define UART_LOOPBACK_S 14 +/* UART_IRDA_RX_INV : R/W ;bitpos:[13] ;default: 1'b0 ; */ +/*description: */ +#define UART_IRDA_RX_INV (BIT(13)) +#define UART_IRDA_RX_INV_M (BIT(13)) +#define UART_IRDA_RX_INV_V 0x1 +#define UART_IRDA_RX_INV_S 13 +/* UART_IRDA_TX_INV : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UART_IRDA_TX_INV (BIT(12)) +#define UART_IRDA_TX_INV_M (BIT(12)) +#define UART_IRDA_TX_INV_V 0x1 +#define UART_IRDA_TX_INV_S 12 +/* UART_IRDA_WCTL : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UART_IRDA_WCTL (BIT(11)) +#define UART_IRDA_WCTL_M (BIT(11)) +#define UART_IRDA_WCTL_V 0x1 +#define UART_IRDA_WCTL_S 11 +/* UART_IRDA_TX_EN : R/W ;bitpos:[10] ;default: 1'b0 ; */ +/*description: */ +#define UART_IRDA_TX_EN (BIT(10)) +#define UART_IRDA_TX_EN_M (BIT(10)) +#define UART_IRDA_TX_EN_V 0x1 +#define UART_IRDA_TX_EN_S 10 +/* UART_IRDA_DPLX : R/W ;bitpos:[9] ;default: 1'b0 ; */ +/*description: */ +#define UART_IRDA_DPLX (BIT(9)) +#define UART_IRDA_DPLX_M (BIT(9)) +#define UART_IRDA_DPLX_V 0x1 +#define UART_IRDA_DPLX_S 9 +/* UART_TXD_BRK : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UART_TXD_BRK (BIT(8)) +#define UART_TXD_BRK_M (BIT(8)) +#define UART_TXD_BRK_V 0x1 +#define UART_TXD_BRK_S 8 +/* UART_SW_DTR : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_DTR (BIT(7)) +#define UART_SW_DTR_M (BIT(7)) +#define UART_SW_DTR_V 0x1 +#define UART_SW_DTR_S 7 +/* UART_SW_RTS : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_RTS (BIT(6)) +#define UART_SW_RTS_M (BIT(6)) +#define UART_SW_RTS_V 0x1 +#define UART_SW_RTS_S 6 +/* UART_STOP_BIT_NUM : R/W ;bitpos:[5:4] ;default: 2'd1 ; */ +/*description: */ +#define UART_STOP_BIT_NUM 0x00000003 +#define UART_STOP_BIT_NUM_M ((UART_STOP_BIT_NUM_V) << (UART_STOP_BIT_NUM_S)) +#define UART_STOP_BIT_NUM_V 0x3 +#define UART_STOP_BIT_NUM_S 4 +/* UART_BIT_NUM : R/W ;bitpos:[3:2] ;default: 2'd3 ; */ +/*description: */ +#define UART_BIT_NUM 0x00000003 +#define UART_BIT_NUM_M ((UART_BIT_NUM_V) << (UART_BIT_NUM_S)) +#define UART_BIT_NUM_V 0x3 +#define UART_BIT_NUM_S 2 +/* UART_PARITY_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UART_PARITY_EN (BIT(1)) +#define UART_PARITY_EN_M (BIT(1)) +#define UART_PARITY_EN_V 0x1 +#define UART_PARITY_EN_S 1 +/* UART_PARITY : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UART_PARITY (BIT(0)) +#define UART_PARITY_M (BIT(0)) +#define UART_PARITY_V 0x1 +#define UART_PARITY_S 0 + +#define UART_CONF1_REG(i) (REG_UART_BASE(i) + 0x24) +/* UART_RX_TOUT_EN : R/W ;bitpos:[21] ;default: 1'b0 ; */ +/*description: */ +#define UART_RX_TOUT_EN (BIT(21)) +#define UART_RX_TOUT_EN_M (BIT(21)) +#define UART_RX_TOUT_EN_V 0x1 +#define UART_RX_TOUT_EN_S 21 +/* UART_RX_FLOW_EN : R/W ;bitpos:[20] ;default: 1'b0 ; */ +/*description: */ +#define UART_RX_FLOW_EN (BIT(20)) +#define UART_RX_FLOW_EN_M (BIT(20)) +#define UART_RX_FLOW_EN_V 0x1 +#define UART_RX_FLOW_EN_S 20 +/* UART_RX_TOUT_FLOW_DIS : R/W ;bitpos:[19] ;default: 1'b0 ; */ +/*description: */ +#define UART_RX_TOUT_FLOW_DIS (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS_M (BIT(19)) +#define UART_RX_TOUT_FLOW_DIS_V 0x1 +#define UART_RX_TOUT_FLOW_DIS_S 19 +/* UART_DIS_RX_DAT_OVF : R/W ;bitpos:[18] ;default: 1'h0 ; */ +/*description: */ +#define UART_DIS_RX_DAT_OVF (BIT(18)) +#define UART_DIS_RX_DAT_OVF_M (BIT(18)) +#define UART_DIS_RX_DAT_OVF_V 0x1 +#define UART_DIS_RX_DAT_OVF_S 18 +/* UART_TXFIFO_EMPTY_THRHD : R/W ;bitpos:[17:9] ;default: 9'h60 ; */ +/*description: */ +#define UART_TXFIFO_EMPTY_THRHD 0x000001FF +#define UART_TXFIFO_EMPTY_THRHD_M ((UART_TXFIFO_EMPTY_THRHD_V) << (UART_TXFIFO_EMPTY_THRHD_S)) +#define UART_TXFIFO_EMPTY_THRHD_V 0x1FF +#define UART_TXFIFO_EMPTY_THRHD_S 9 +/* UART_RXFIFO_FULL_THRHD : R/W ;bitpos:[8:0] ;default: 9'h60 ; */ +/*description: */ +#define UART_RXFIFO_FULL_THRHD 0x000001FF +#define UART_RXFIFO_FULL_THRHD_M ((UART_RXFIFO_FULL_THRHD_V) << (UART_RXFIFO_FULL_THRHD_S)) +#define UART_RXFIFO_FULL_THRHD_V 0x1FF +#define UART_RXFIFO_FULL_THRHD_S 0 + +#define UART_LOWPULSE_REG(i) (REG_UART_BASE(i) + 0x28) +/* UART_LOWPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: */ +#define UART_LOWPULSE_MIN_CNT 0x00000FFF +#define UART_LOWPULSE_MIN_CNT_M ((UART_LOWPULSE_MIN_CNT_V) << (UART_LOWPULSE_MIN_CNT_S)) +#define UART_LOWPULSE_MIN_CNT_V 0xFFF +#define UART_LOWPULSE_MIN_CNT_S 0 + +#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x2C) +/* UART_HIGHPULSE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: */ +#define UART_HIGHPULSE_MIN_CNT 0x00000FFF +#define UART_HIGHPULSE_MIN_CNT_M ((UART_HIGHPULSE_MIN_CNT_V) << (UART_HIGHPULSE_MIN_CNT_S)) +#define UART_HIGHPULSE_MIN_CNT_V 0xFFF +#define UART_HIGHPULSE_MIN_CNT_S 0 + +#define UART_RXD_CNT_REG(i) (REG_UART_BASE(i) + 0x30) +/* UART_RXD_EDGE_CNT : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: */ +#define UART_RXD_EDGE_CNT 0x000003FF +#define UART_RXD_EDGE_CNT_M ((UART_RXD_EDGE_CNT_V) << (UART_RXD_EDGE_CNT_S)) +#define UART_RXD_EDGE_CNT_V 0x3FF +#define UART_RXD_EDGE_CNT_S 0 + +#define UART_FLOW_CONF_REG(i) (REG_UART_BASE(i) + 0x34) +/* UART_SEND_XOFF : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UART_SEND_XOFF (BIT(5)) +#define UART_SEND_XOFF_M (BIT(5)) +#define UART_SEND_XOFF_V 0x1 +#define UART_SEND_XOFF_S 5 +/* UART_SEND_XON : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UART_SEND_XON (BIT(4)) +#define UART_SEND_XON_M (BIT(4)) +#define UART_SEND_XON_V 0x1 +#define UART_SEND_XON_S 4 +/* UART_FORCE_XOFF : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UART_FORCE_XOFF (BIT(3)) +#define UART_FORCE_XOFF_M (BIT(3)) +#define UART_FORCE_XOFF_V 0x1 +#define UART_FORCE_XOFF_S 3 +/* UART_FORCE_XON : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UART_FORCE_XON (BIT(2)) +#define UART_FORCE_XON_M (BIT(2)) +#define UART_FORCE_XON_V 0x1 +#define UART_FORCE_XON_S 2 +/* UART_XONOFF_DEL : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UART_XONOFF_DEL (BIT(1)) +#define UART_XONOFF_DEL_M (BIT(1)) +#define UART_XONOFF_DEL_V 0x1 +#define UART_XONOFF_DEL_S 1 +/* UART_SW_FLOW_CON_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UART_SW_FLOW_CON_EN (BIT(0)) +#define UART_SW_FLOW_CON_EN_M (BIT(0)) +#define UART_SW_FLOW_CON_EN_V 0x1 +#define UART_SW_FLOW_CON_EN_S 0 + +#define UART_SLEEP_CONF_REG(i) (REG_UART_BASE(i) + 0x38) +/* UART_ACTIVE_THRESHOLD : R/W ;bitpos:[9:0] ;default: 10'hf0 ; */ +/*description: */ +#define UART_ACTIVE_THRESHOLD 0x000003FF +#define UART_ACTIVE_THRESHOLD_M ((UART_ACTIVE_THRESHOLD_V) << (UART_ACTIVE_THRESHOLD_S)) +#define UART_ACTIVE_THRESHOLD_V 0x3FF +#define UART_ACTIVE_THRESHOLD_S 0 + +#define UART_SWFC_CONF0_REG(i) (REG_UART_BASE(i) + 0x3C) +/* UART_XOFF_CHAR : R/W ;bitpos:[16:9] ;default: 8'h13 ; */ +/*description: */ +#define UART_XOFF_CHAR 0x000000FF +#define UART_XOFF_CHAR_M ((UART_XOFF_CHAR_V) << (UART_XOFF_CHAR_S)) +#define UART_XOFF_CHAR_V 0xFF +#define UART_XOFF_CHAR_S 9 +/* UART_XOFF_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'he0 ; */ +/*description: */ +#define UART_XOFF_THRESHOLD 0x000001FF +#define UART_XOFF_THRESHOLD_M ((UART_XOFF_THRESHOLD_V) << (UART_XOFF_THRESHOLD_S)) +#define UART_XOFF_THRESHOLD_V 0x1FF +#define UART_XOFF_THRESHOLD_S 0 + +#define UART_SWFC_CONF1_REG(i) (REG_UART_BASE(i) + 0x40) +/* UART_XON_CHAR : R/W ;bitpos:[16:9] ;default: 8'h11 ; */ +/*description: */ +#define UART_XON_CHAR 0x000000FF +#define UART_XON_CHAR_M ((UART_XON_CHAR_V) << (UART_XON_CHAR_S)) +#define UART_XON_CHAR_V 0xFF +#define UART_XON_CHAR_S 9 +/* UART_XON_THRESHOLD : R/W ;bitpos:[8:0] ;default: 9'h0 ; */ +/*description: */ +#define UART_XON_THRESHOLD 0x000001FF +#define UART_XON_THRESHOLD_M ((UART_XON_THRESHOLD_V) << (UART_XON_THRESHOLD_S)) +#define UART_XON_THRESHOLD_V 0x1FF +#define UART_XON_THRESHOLD_S 0 + +#define UART_TXBRK_CONF_REG(i) (REG_UART_BASE(i) + 0x44) +/* UART_TX_BRK_NUM : R/W ;bitpos:[7:0] ;default: 8'ha ; */ +/*description: */ +#define UART_TX_BRK_NUM 0x000000FF +#define UART_TX_BRK_NUM_M ((UART_TX_BRK_NUM_V) << (UART_TX_BRK_NUM_S)) +#define UART_TX_BRK_NUM_V 0xFF +#define UART_TX_BRK_NUM_S 0 + +#define UART_IDLE_CONF_REG(i) (REG_UART_BASE(i) + 0x48) +/* UART_TX_IDLE_NUM : R/W ;bitpos:[19:10] ;default: 10'h100 ; */ +/*description: */ +#define UART_TX_IDLE_NUM 0x000003FF +#define UART_TX_IDLE_NUM_M ((UART_TX_IDLE_NUM_V) << (UART_TX_IDLE_NUM_S)) +#define UART_TX_IDLE_NUM_V 0x3FF +#define UART_TX_IDLE_NUM_S 10 +/* UART_RX_IDLE_THRHD : R/W ;bitpos:[9:0] ;default: 10'h100 ; */ +/*description: */ +#define UART_RX_IDLE_THRHD 0x000003FF +#define UART_RX_IDLE_THRHD_M ((UART_RX_IDLE_THRHD_V) << (UART_RX_IDLE_THRHD_S)) +#define UART_RX_IDLE_THRHD_V 0x3FF +#define UART_RX_IDLE_THRHD_S 0 + +#define UART_RS485_CONF_REG(i) (REG_UART_BASE(i) + 0x4c) +/* UART_RS485_TX_DLY_NUM : R/W ;bitpos:[9:6] ;default: 4'b0 ; */ +/*description: */ +#define UART_RS485_TX_DLY_NUM 0x0000000F +#define UART_RS485_TX_DLY_NUM_M ((UART_RS485_TX_DLY_NUM_V) << (UART_RS485_TX_DLY_NUM_S)) +#define UART_RS485_TX_DLY_NUM_V 0xF +#define UART_RS485_TX_DLY_NUM_S 6 +/* UART_RS485_RX_DLY_NUM : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_RX_DLY_NUM (BIT(5)) +#define UART_RS485_RX_DLY_NUM_M (BIT(5)) +#define UART_RS485_RX_DLY_NUM_V 0x1 +#define UART_RS485_RX_DLY_NUM_S 5 +/* UART_RS485RXBY_TX_EN : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485RXBY_TX_EN (BIT(4)) +#define UART_RS485RXBY_TX_EN_M (BIT(4)) +#define UART_RS485RXBY_TX_EN_V 0x1 +#define UART_RS485RXBY_TX_EN_S 4 +/* UART_RS485TX_RX_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485TX_RX_EN (BIT(3)) +#define UART_RS485TX_RX_EN_M (BIT(3)) +#define UART_RS485TX_RX_EN_V 0x1 +#define UART_RS485TX_RX_EN_S 3 +/* UART_DL1_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UART_DL1_EN (BIT(2)) +#define UART_DL1_EN_M (BIT(2)) +#define UART_DL1_EN_V 0x1 +#define UART_DL1_EN_S 2 +/* UART_DL0_EN : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UART_DL0_EN (BIT(1)) +#define UART_DL0_EN_M (BIT(1)) +#define UART_DL0_EN_V 0x1 +#define UART_DL0_EN_S 1 +/* UART_RS485_EN : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UART_RS485_EN (BIT(0)) +#define UART_RS485_EN_M (BIT(0)) +#define UART_RS485_EN_V 0x1 +#define UART_RS485_EN_S 0 + +#define UART_AT_CMD_PRECNT_REG(i) (REG_UART_BASE(i) + 0x50) +/* UART_PRE_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ +/*description: */ +#define UART_PRE_IDLE_NUM 0x0000FFFF +#define UART_PRE_IDLE_NUM_M ((UART_PRE_IDLE_NUM_V) << (UART_PRE_IDLE_NUM_S)) +#define UART_PRE_IDLE_NUM_V 0xFFFF +#define UART_PRE_IDLE_NUM_S 0 + +#define UART_AT_CMD_POSTCNT_REG(i) (REG_UART_BASE(i) + 0x54) +/* UART_POST_IDLE_NUM : R/W ;bitpos:[15:0] ;default: 16'h901 ; */ +/*description: */ +#define UART_POST_IDLE_NUM 0x0000FFFF +#define UART_POST_IDLE_NUM_M ((UART_POST_IDLE_NUM_V) << (UART_POST_IDLE_NUM_S)) +#define UART_POST_IDLE_NUM_V 0xFFFF +#define UART_POST_IDLE_NUM_S 0 + +#define UART_AT_CMD_GAPTOUT_REG(i) (REG_UART_BASE(i) + 0x58) +/* UART_RX_GAP_TOUT : R/W ;bitpos:[15:0] ;default: 16'd11 ; */ +/*description: */ +#define UART_RX_GAP_TOUT 0x0000FFFF +#define UART_RX_GAP_TOUT_M ((UART_RX_GAP_TOUT_V) << (UART_RX_GAP_TOUT_S)) +#define UART_RX_GAP_TOUT_V 0xFFFF +#define UART_RX_GAP_TOUT_S 0 + +#define UART_AT_CMD_CHAR_REG(i) (REG_UART_BASE(i) + 0x5c) +/* UART_CHAR_NUM : R/W ;bitpos:[15:8] ;default: 8'h3 ; */ +/*description: */ +#define UART_CHAR_NUM 0x000000FF +#define UART_CHAR_NUM_M ((UART_CHAR_NUM_V) << (UART_CHAR_NUM_S)) +#define UART_CHAR_NUM_V 0xFF +#define UART_CHAR_NUM_S 8 +/* UART_AT_CMD_CHAR : R/W ;bitpos:[7:0] ;default: 8'h2b ; */ +/*description: */ +#define UART_AT_CMD_CHAR 0x000000FF +#define UART_AT_CMD_CHAR_M ((UART_AT_CMD_CHAR_V) << (UART_AT_CMD_CHAR_S)) +#define UART_AT_CMD_CHAR_V 0xFF +#define UART_AT_CMD_CHAR_S 0 + +#define UART_MEM_CONF_REG(i) (REG_UART_BASE(i) + 0x60) +/* UART_MEM_FORCE_PU : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define UART_MEM_FORCE_PU (BIT(27)) +#define UART_MEM_FORCE_PU_M (BIT(27)) +#define UART_MEM_FORCE_PU_V 0x1 +#define UART_MEM_FORCE_PU_S 27 +/* UART_MEM_FORCE_PD : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define UART_MEM_FORCE_PD (BIT(26)) +#define UART_MEM_FORCE_PD_M (BIT(26)) +#define UART_MEM_FORCE_PD_V 0x1 +#define UART_MEM_FORCE_PD_S 26 +/* UART_RX_TOUT_THRHD : R/W ;bitpos:[25:16] ;default: 10'ha ; */ +/*description: */ +#define UART_RX_TOUT_THRHD 0x000003FF +#define UART_RX_TOUT_THRHD_M ((UART_RX_TOUT_THRHD_V) << (UART_RX_TOUT_THRHD_S)) +#define UART_RX_TOUT_THRHD_V 0x3FF +#define UART_RX_TOUT_THRHD_S 16 +/* UART_RX_FLOW_THRHD : R/W ;bitpos:[15:7] ;default: 9'h0 ; */ +/*description: */ +#define UART_RX_FLOW_THRHD 0x000001FF +#define UART_RX_FLOW_THRHD_M ((UART_RX_FLOW_THRHD_V) << (UART_RX_FLOW_THRHD_S)) +#define UART_RX_FLOW_THRHD_V 0x1FF +#define UART_RX_FLOW_THRHD_S 7 +/* UART_TX_SIZE : R/W ;bitpos:[6:4] ;default: 3'h1 ; */ +/*description: */ +#define UART_TX_SIZE 0x00000007 +#define UART_TX_SIZE_M ((UART_TX_SIZE_V) << (UART_TX_SIZE_S)) +#define UART_TX_SIZE_V 0x7 +#define UART_TX_SIZE_S 4 +/* UART_RX_SIZE : R/W ;bitpos:[3:1] ;default: 3'b1 ; */ +/*description: */ +#define UART_RX_SIZE 0x00000007 +#define UART_RX_SIZE_M ((UART_RX_SIZE_V) << (UART_RX_SIZE_S)) +#define UART_RX_SIZE_V 0x7 +#define UART_RX_SIZE_S 1 + +#define UART_MEM_TX_STATUS_REG(i) (REG_UART_BASE(i) + 0x64) +/* UART_TX_RADDR : RO ;bitpos:[20:11] ;default: 10'h0 ; */ +/*description: TXFIFO address for uart tx read data. Default value is 10'h0 + for uart0 10'h80 for uart1 10'h100 for uart2.*/ +#define UART_TX_RADDR 0x000003FF +#define UART_TX_RADDR_M ((UART_TX_RADDR_V) << (UART_TX_RADDR_S)) +#define UART_TX_RADDR_V 0x3FF +#define UART_TX_RADDR_S 11 +/* UART_APB_TX_WADDR : RO ;bitpos:[9:0] ;default: 10'h0 ; */ +/*description: TXFIFO address write by apb bus or hci. Default value is 10'h0 + for uart0 10'h80 for uart1 10'h100 for uart2.*/ +#define UART_APB_TX_WADDR 0x000003FF +#define UART_APB_TX_WADDR_M ((UART_APB_TX_WADDR_V) << (UART_APB_TX_WADDR_S)) +#define UART_APB_TX_WADDR_V 0x3FF +#define UART_APB_TX_WADDR_S 0 + +#define UART_MEM_RX_STATUS_REG(i) (REG_UART_BASE(i) + 0x68) +/* UART_RX_WADDR : RO ;bitpos:[20:11] ;default: 10'h200 ; */ +/*description: RXFIFO address for uart rx write data. Default value is 10'h200 + for uart0 10'h280 for uart1 10'h300 for uart2.*/ +#define UART_RX_WADDR 0x000003FF +#define UART_RX_WADDR_M ((UART_RX_WADDR_V) << (UART_RX_WADDR_S)) +#define UART_RX_WADDR_V 0x3FF +#define UART_RX_WADDR_S 11 +/* UART_APB_RX_RADDR : RO ;bitpos:[9:0] ;default: 10'h200 ; */ +/*description: RXFIFO address read by apb bus or hci. Default value is 10'h200 + for uart0 10'h280 for uart1 10'h300 for uart2.*/ +#define UART_APB_RX_RADDR 0x000003FF +#define UART_APB_RX_RADDR_M ((UART_APB_RX_RADDR_V) << (UART_APB_RX_RADDR_S)) +#define UART_APB_RX_RADDR_V 0x3FF +#define UART_APB_RX_RADDR_S 0 + +#define UART_FSM_STATUS_REG(i) (REG_UART_BASE(i) + 0x6c) +/* UART_ST_UTX_OUT : RO ;bitpos:[7:4] ;default: 4'b0 ; */ +/*description: */ +#define UART_ST_UTX_OUT 0x0000000F +#define UART_ST_UTX_OUT_M ((UART_ST_UTX_OUT_V) << (UART_ST_UTX_OUT_S)) +#define UART_ST_UTX_OUT_V 0xF +#define UART_ST_UTX_OUT_S 4 +/* UART_ST_URX_OUT : RO ;bitpos:[3:0] ;default: 4'b0 ; */ +/*description: */ +#define UART_ST_URX_OUT 0x0000000F +#define UART_ST_URX_OUT_M ((UART_ST_URX_OUT_V) << (UART_ST_URX_OUT_S)) +#define UART_ST_URX_OUT_V 0xF +#define UART_ST_URX_OUT_S 0 + +#define UART_POSPULSE_REG(i) (REG_UART_BASE(i) + 0x70) +/* UART_POSEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: */ +#define UART_POSEDGE_MIN_CNT 0x00000FFF +#define UART_POSEDGE_MIN_CNT_M ((UART_POSEDGE_MIN_CNT_V) << (UART_POSEDGE_MIN_CNT_S)) +#define UART_POSEDGE_MIN_CNT_V 0xFFF +#define UART_POSEDGE_MIN_CNT_S 0 + +#define UART_NEGPULSE_REG(i) (REG_UART_BASE(i) + 0x74) +/* UART_NEGEDGE_MIN_CNT : RO ;bitpos:[11:0] ;default: 12'hFFF ; */ +/*description: */ +#define UART_NEGEDGE_MIN_CNT 0x00000FFF +#define UART_NEGEDGE_MIN_CNT_M ((UART_NEGEDGE_MIN_CNT_V) << (UART_NEGEDGE_MIN_CNT_S)) +#define UART_NEGEDGE_MIN_CNT_V 0xFFF +#define UART_NEGEDGE_MIN_CNT_S 0 + +#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x78) +/* UART_RX_RST_CORE : R/W ;bitpos:[27] ;default: 1'b0 ; */ +/*description: */ +#define UART_RX_RST_CORE (BIT(27)) +#define UART_RX_RST_CORE_M (BIT(27)) +#define UART_RX_RST_CORE_V 0x1 +#define UART_RX_RST_CORE_S 27 +/* UART_TX_RST_CORE : R/W ;bitpos:[26] ;default: 1'b0 ; */ +/*description: */ +#define UART_TX_RST_CORE (BIT(26)) +#define UART_TX_RST_CORE_M (BIT(26)) +#define UART_TX_RST_CORE_V 0x1 +#define UART_TX_RST_CORE_S 26 +/* UART_RX_SCLK_EN : R/W ;bitpos:[25] ;default: 1'b1 ; */ +/*description: */ +#define UART_RX_SCLK_EN (BIT(25)) +#define UART_RX_SCLK_EN_M (BIT(25)) +#define UART_RX_SCLK_EN_V 0x1 +#define UART_RX_SCLK_EN_S 25 +/* UART_TX_SCLK_EN : R/W ;bitpos:[24] ;default: 1'b1 ; */ +/*description: */ +#define UART_TX_SCLK_EN (BIT(24)) +#define UART_TX_SCLK_EN_M (BIT(24)) +#define UART_TX_SCLK_EN_V 0x1 +#define UART_TX_SCLK_EN_S 24 +/* UART_RST_CORE : R/W ;bitpos:[23] ;default: 1'b0 ; */ +/*description: */ +#define UART_RST_CORE (BIT(23)) +#define UART_RST_CORE_M (BIT(23)) +#define UART_RST_CORE_V 0x1 +#define UART_RST_CORE_S 23 +/* UART_SCLK_EN : R/W ;bitpos:[22] ;default: 1'b1 ; */ +/*description: */ +#define UART_SCLK_EN (BIT(22)) +#define UART_SCLK_EN_M (BIT(22)) +#define UART_SCLK_EN_V 0x1 +#define UART_SCLK_EN_S 22 +/* UART_SCLK_SEL : R/W ;bitpos:[21:20] ;default: 2'd3 ; */ +/*description: */ +#define UART_SCLK_SEL 0x00000003 +#define UART_SCLK_SEL_M ((UART_SCLK_SEL_V) << (UART_SCLK_SEL_S)) +#define UART_SCLK_SEL_V 0x3 +#define UART_SCLK_SEL_S 20 +/* UART_SCLK_DIV_NUM : R/W ;bitpos:[19:12] ;default: 8'h1 ; */ +/*description: */ +#define UART_SCLK_DIV_NUM 0x000000FF +#define UART_SCLK_DIV_NUM_M ((UART_SCLK_DIV_NUM_V) << (UART_SCLK_DIV_NUM_S)) +#define UART_SCLK_DIV_NUM_V 0xFF +#define UART_SCLK_DIV_NUM_S 12 +/* UART_SCLK_DIV_A : R/W ;bitpos:[11:6] ;default: 6'h0 ; */ +/*description: */ +#define UART_SCLK_DIV_A 0x0000003F +#define UART_SCLK_DIV_A_M ((UART_SCLK_DIV_A_V) << (UART_SCLK_DIV_A_S)) +#define UART_SCLK_DIV_A_V 0x3F +#define UART_SCLK_DIV_A_S 6 +/* UART_SCLK_DIV_B : R/W ;bitpos:[5:0] ;default: 6'h0 ; */ +/*description: */ +#define UART_SCLK_DIV_B 0x0000003F +#define UART_SCLK_DIV_B_M ((UART_SCLK_DIV_B_V) << (UART_SCLK_DIV_B_S)) +#define UART_SCLK_DIV_B_V 0x3F +#define UART_SCLK_DIV_B_S 0 + +#define UART_DATE_REG(i) (REG_UART_BASE(i) + 0x7c) +/* UART_DATE : R/W ;bitpos:[31:0] ;default: 32'h2003040 ; */ +/*description: */ +#define UART_DATE 0xFFFFFFFF +#define UART_DATE_M ((UART_DATE_V) << (UART_DATE_S)) +#define UART_DATE_V 0xFFFFFFFF +#define UART_DATE_S 0 + +#define UART_ID_REG(i) (REG_UART_BASE(i) + 0x80) +/* UART_ID : R/W ;bitpos:[31:0] ;default: 32'h0500 ; */ +/*description: */ +#define UART_ID 0xFFFFFFFF +#define UART_ID_M ((UART_ID_V) << (UART_ID_S)) +#define UART_ID_V 0xFFFFFFFF +#define UART_ID_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/uart_struct.h b/components/soc/soc/esp32s3/include/soc/uart_struct.h new file mode 100644 index 000000000..d7034c140 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/uart_struct.h @@ -0,0 +1,402 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint8_t rw_byte; + uint8_t reserved[3]; + }; + uint32_t val; + } ahb_fifo; + union { + struct { + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rxfifo_full: 1; + uint32_t txfifo_empty: 1; + uint32_t parity_err: 1; + uint32_t frm_err: 1; + uint32_t rxfifo_ovf: 1; + uint32_t dsr_chg: 1; + uint32_t cts_chg: 1; + uint32_t brk_det: 1; + uint32_t rxfifo_tout: 1; + uint32_t sw_xon: 1; + uint32_t sw_xoff: 1; + uint32_t glitch_det: 1; + uint32_t tx_brk_done: 1; + uint32_t tx_brk_idle_done: 1; + uint32_t tx_done: 1; + uint32_t rs485_parity_err: 1; + uint32_t rs485_frm_err: 1; + uint32_t rs485_clash: 1; + uint32_t at_cmd_char_det: 1; + uint32_t wakeup: 1; + uint32_t reserved20: 12; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t div_int: 12; + uint32_t reserved12: 8; + uint32_t div_frag: 4; + uint32_t reserved24: 8; + }; + uint32_t val; + } clk_div; + union { + struct { + uint32_t glitch_filt: 8; + uint32_t glitch_filt_en: 1; + uint32_t reserved9: 23; + }; + uint32_t val; + } rx_filt; + union { + struct { + uint32_t rxfifo_cnt: 10; + uint32_t reserved10: 3; + uint32_t dsrn: 1; + uint32_t ctsn: 1; + uint32_t rxd: 1; + uint32_t txfifo_cnt: 10; + uint32_t reserved26: 3; + uint32_t dtrn: 1; + uint32_t rtsn: 1; + uint32_t txd: 1; + }; + uint32_t val; + } status; + union { + struct { + uint32_t parity: 1; + uint32_t parity_en: 1; + uint32_t bit_num: 2; + uint32_t stop_bit_num: 2; + uint32_t sw_rts: 1; + uint32_t sw_dtr: 1; + uint32_t txd_brk: 1; + uint32_t irda_dplx: 1; + uint32_t irda_tx_en: 1; + uint32_t irda_wctl: 1; + uint32_t irda_tx_inv: 1; + uint32_t irda_rx_inv: 1; + uint32_t loopback: 1; + uint32_t tx_flow_en: 1; + uint32_t irda_en: 1; + uint32_t rxfifo_rst: 1; + uint32_t txfifo_rst: 1; + uint32_t rxd_inv: 1; + uint32_t cts_inv: 1; + uint32_t dsr_inv: 1; + uint32_t txd_inv: 1; + uint32_t rts_inv: 1; + uint32_t dtr_inv: 1; + uint32_t clk_en: 1; + uint32_t err_wr_mask: 1; + uint32_t en: 1; + uint32_t mem_clk_en: 1; + uint32_t reserved29: 3; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rxfifo_full_thrhd: 9; + uint32_t txfifo_empty_thrhd: 9; + uint32_t dis_rx_dat_ovf: 1; + uint32_t rx_tout_flow_dis: 1; + uint32_t rx_flow_en: 1; + uint32_t rx_tout_en: 1; + uint32_t reserved22: 10; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t min_cnt: 12; + uint32_t reserved12: 20; + }; + uint32_t val; + } lowpulse; + union { + struct { + uint32_t min_cnt: 12; + uint32_t reserved12: 20; + }; + uint32_t val; + } highpulse; + union { + struct { + uint32_t edge_cnt: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } rxd_cnt; + union { + struct { + uint32_t sw_flow_con_en: 1; + uint32_t xonoff_del: 1; + uint32_t force_xon: 1; + uint32_t force_xoff: 1; + uint32_t send_xon: 1; + uint32_t send_xoff: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } flow_conf; + union { + struct { + uint32_t active_threshold: 10; + uint32_t reserved10: 22; + }; + uint32_t val; + } sleep_conf; + union { + struct { + uint32_t xoff_threshold: 9; + uint32_t xoff_char: 8; + uint32_t reserved17: 15; + }; + uint32_t val; + } swfc_conf0; + union { + struct { + uint32_t xon_threshold: 9; + uint32_t xon_char: 8; + uint32_t reserved17: 15; + }; + uint32_t val; + } swfc_conf1; + union { + struct { + uint32_t tx_brk_num: 8; + uint32_t reserved8: 24; + }; + uint32_t val; + } txbrk_conf; + union { + struct { + uint32_t rx_idle_thrhd: 10; + uint32_t tx_idle_num: 10; + uint32_t reserved20: 12; + }; + uint32_t val; + } idle_conf; + union { + struct { + uint32_t en: 1; + uint32_t dl0_en: 1; + uint32_t dl1_en: 1; + uint32_t tx_rx_en: 1; + uint32_t rx_busy_tx_en: 1; + uint32_t rx_dly_num: 1; + uint32_t tx_dly_num: 4; + uint32_t reserved10: 22; + }; + uint32_t val; + } rs485_conf; + union { + struct { + uint32_t pre_idle_num: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } at_cmd_precnt; + union { + struct { + uint32_t post_idle_num: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } at_cmd_postcnt; + union { + struct { + uint32_t rx_gap_tout: 16; + uint32_t reserved16: 16; + }; + uint32_t val; + } at_cmd_gaptout; + union { + struct { + uint32_t data: 8; + uint32_t char_num: 8; + uint32_t reserved16: 16; + }; + uint32_t val; + } at_cmd_char; + union { + struct { + uint32_t reserved0: 1; + uint32_t rx_size: 3; + uint32_t tx_size: 3; + uint32_t rx_flow_thrhd: 9; + uint32_t rx_tout_thrhd: 10; + uint32_t force_pd: 1; + uint32_t force_pu: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } mem_conf; + union { + struct { + uint32_t apb_tx_waddr: 10; /*TXFIFO address write by apb bus or hci. Default value is 10'h0 for uart0 10'h80 for uart1 10'h100 for uart2.*/ + uint32_t reserved10: 1; + uint32_t tx_raddr: 10; /*TXFIFO address for uart tx read data. Default value is 10'h0 for uart0 10'h80 for uart1 10'h100 for uart2.*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } mem_tx_status; + union { + struct { + uint32_t apb_rx_raddr: 10; /*RXFIFO address read by apb bus or hci. Default value is 10'h200 for uart0 10'h280 for uart1 10'h300 for uart2.*/ + uint32_t reserved10: 1; + uint32_t rx_waddr: 10; /*RXFIFO address for uart rx write data. Default value is 10'h200 for uart0 10'h280 for uart1 10'h300 for uart2.*/ + uint32_t reserved21: 11; + }; + uint32_t val; + } mem_rx_status; + union { + struct { + uint32_t st_urx_out: 4; + uint32_t st_utx_out: 4; + uint32_t reserved8: 24; + }; + uint32_t val; + } fsm_status; + union { + struct { + uint32_t min_cnt: 12; + uint32_t reserved12: 20; + }; + uint32_t val; + } pospulse; + union { + struct { + uint32_t min_cnt: 12; + uint32_t reserved12: 20; + }; + uint32_t val; + } negpulse; + union { + struct { + uint32_t sclk_div_b: 6; + uint32_t sclk_div_a: 6; + uint32_t sclk_div_num: 8; + uint32_t sclk_sel: 2; + uint32_t sclk_en: 1; + uint32_t rst_core: 1; + uint32_t tx_sclk_en: 1; + uint32_t rx_sclk_en: 1; + uint32_t tx_rst_core: 1; + uint32_t rx_rst_core: 1; + uint32_t reserved28: 4; + }; + uint32_t val; + } clk_conf; + uint32_t date; /**/ + uint32_t id; /**/ +} uart_dev_t; + +extern uart_dev_t UART0; +extern uart_dev_t UART1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/uhci_reg.h b/components/soc/soc/esp32s3/include/soc/uhci_reg.h new file mode 100644 index 000000000..440c85caf --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/uhci_reg.h @@ -0,0 +1,660 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include "soc.h" + +#define UHCI_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x0) +/* UHCI_UART_RX_BRK_EOF_EN : R/W ;bitpos:[12] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_UART_RX_BRK_EOF_EN (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_M (BIT(12)) +#define UHCI_UART_RX_BRK_EOF_EN_V 0x1 +#define UHCI_UART_RX_BRK_EOF_EN_S 12 +/* UHCI_CLK_EN : R/W ;bitpos:[11] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_CLK_EN (BIT(11)) +#define UHCI_CLK_EN_M (BIT(11)) +#define UHCI_CLK_EN_V 0x1 +#define UHCI_CLK_EN_S 11 +/* UHCI_ENCODE_CRC_EN : R/W ;bitpos:[10] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_ENCODE_CRC_EN (BIT(10)) +#define UHCI_ENCODE_CRC_EN_M (BIT(10)) +#define UHCI_ENCODE_CRC_EN_V 0x1 +#define UHCI_ENCODE_CRC_EN_S 10 +/* UHCI_LEN_EOF_EN : R/W ;bitpos:[9] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_LEN_EOF_EN (BIT(9)) +#define UHCI_LEN_EOF_EN_M (BIT(9)) +#define UHCI_LEN_EOF_EN_V 0x1 +#define UHCI_LEN_EOF_EN_S 9 +/* UHCI_UART_IDLE_EOF_EN : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_UART_IDLE_EOF_EN (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_M (BIT(8)) +#define UHCI_UART_IDLE_EOF_EN_V 0x1 +#define UHCI_UART_IDLE_EOF_EN_S 8 +/* UHCI_CRC_REC_EN : R/W ;bitpos:[7] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_CRC_REC_EN (BIT(7)) +#define UHCI_CRC_REC_EN_M (BIT(7)) +#define UHCI_CRC_REC_EN_V 0x1 +#define UHCI_CRC_REC_EN_S 7 +/* UHCI_HEAD_EN : R/W ;bitpos:[6] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_HEAD_EN (BIT(6)) +#define UHCI_HEAD_EN_M (BIT(6)) +#define UHCI_HEAD_EN_V 0x1 +#define UHCI_HEAD_EN_S 6 +/* UHCI_SEPER_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_SEPER_EN (BIT(5)) +#define UHCI_SEPER_EN_M (BIT(5)) +#define UHCI_SEPER_EN_V 0x1 +#define UHCI_SEPER_EN_S 5 +/* UHCI_UART2_CE : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_UART2_CE (BIT(4)) +#define UHCI_UART2_CE_M (BIT(4)) +#define UHCI_UART2_CE_V 0x1 +#define UHCI_UART2_CE_S 4 +/* UHCI_UART1_CE : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_UART1_CE (BIT(3)) +#define UHCI_UART1_CE_M (BIT(3)) +#define UHCI_UART1_CE_V 0x1 +#define UHCI_UART1_CE_S 3 +/* UHCI_UART0_CE : R/W ;bitpos:[2] ;default: 1'h0 ; */ +/*description: */ +#define UHCI_UART0_CE (BIT(2)) +#define UHCI_UART0_CE_M (BIT(2)) +#define UHCI_UART0_CE_V 0x1 +#define UHCI_UART0_CE_S 2 +/* UHCI_RX_RST : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_RST (BIT(1)) +#define UHCI_RX_RST_M (BIT(1)) +#define UHCI_RX_RST_V 0x1 +#define UHCI_RX_RST_S 1 +/* UHCI_TX_RST : R/W ;bitpos:[0] ;default: 1'h0 ; */ +/*description: */ +#define UHCI_TX_RST (BIT(0)) +#define UHCI_TX_RST_M (BIT(0)) +#define UHCI_TX_RST_V 0x1 +#define UHCI_TX_RST_S 0 + +#define UHCI_INT_RAW_REG(i) (REG_UHCI_BASE(i) + 0x4) +/* UHCI_SEND_A_Q_INT_RAW : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_RAW (BIT(5)) +#define UHCI_SEND_A_Q_INT_RAW_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_RAW_V 0x1 +#define UHCI_SEND_A_Q_INT_RAW_S 5 +/* UHCI_SEND_S_Q_INT_RAW : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_RAW (BIT(4)) +#define UHCI_SEND_S_Q_INT_RAW_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_RAW_V 0x1 +#define UHCI_SEND_S_Q_INT_RAW_S 4 +/* UHCI_TX_HUNG_INT_RAW : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_RAW (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_M (BIT(3)) +#define UHCI_TX_HUNG_INT_RAW_V 0x1 +#define UHCI_TX_HUNG_INT_RAW_S 3 +/* UHCI_RX_HUNG_INT_RAW : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_RAW (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_M (BIT(2)) +#define UHCI_RX_HUNG_INT_RAW_V 0x1 +#define UHCI_RX_HUNG_INT_RAW_S 2 +/* UHCI_TX_START_INT_RAW : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_RAW (BIT(1)) +#define UHCI_TX_START_INT_RAW_M (BIT(1)) +#define UHCI_TX_START_INT_RAW_V 0x1 +#define UHCI_TX_START_INT_RAW_S 1 +/* UHCI_RX_START_INT_RAW : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_RAW (BIT(0)) +#define UHCI_RX_START_INT_RAW_M (BIT(0)) +#define UHCI_RX_START_INT_RAW_V 0x1 +#define UHCI_RX_START_INT_RAW_S 0 + +#define UHCI_INT_ST_REG(i) (REG_UHCI_BASE(i) + 0x8) +/* UHCI_SEND_A_Q_INT_ST : RO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_ST (BIT(5)) +#define UHCI_SEND_A_Q_INT_ST_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_ST_V 0x1 +#define UHCI_SEND_A_Q_INT_ST_S 5 +/* UHCI_SEND_S_Q_INT_ST : RO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_ST (BIT(4)) +#define UHCI_SEND_S_Q_INT_ST_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_ST_V 0x1 +#define UHCI_SEND_S_Q_INT_ST_S 4 +/* UHCI_TX_HUNG_INT_ST : RO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_ST (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ST_V 0x1 +#define UHCI_TX_HUNG_INT_ST_S 3 +/* UHCI_RX_HUNG_INT_ST : RO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_ST (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ST_V 0x1 +#define UHCI_RX_HUNG_INT_ST_S 2 +/* UHCI_TX_START_INT_ST : RO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_ST (BIT(1)) +#define UHCI_TX_START_INT_ST_M (BIT(1)) +#define UHCI_TX_START_INT_ST_V 0x1 +#define UHCI_TX_START_INT_ST_S 1 +/* UHCI_RX_START_INT_ST : RO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_ST (BIT(0)) +#define UHCI_RX_START_INT_ST_M (BIT(0)) +#define UHCI_RX_START_INT_ST_V 0x1 +#define UHCI_RX_START_INT_ST_S 0 + +#define UHCI_INT_ENA_REG(i) (REG_UHCI_BASE(i) + 0xC) +/* UHCI_SEND_A_Q_INT_ENA : R/W ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_ENA (BIT(5)) +#define UHCI_SEND_A_Q_INT_ENA_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_ENA_V 0x1 +#define UHCI_SEND_A_Q_INT_ENA_S 5 +/* UHCI_SEND_S_Q_INT_ENA : R/W ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_ENA (BIT(4)) +#define UHCI_SEND_S_Q_INT_ENA_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_ENA_V 0x1 +#define UHCI_SEND_S_Q_INT_ENA_S 4 +/* UHCI_TX_HUNG_INT_ENA : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_ENA (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_M (BIT(3)) +#define UHCI_TX_HUNG_INT_ENA_V 0x1 +#define UHCI_TX_HUNG_INT_ENA_S 3 +/* UHCI_RX_HUNG_INT_ENA : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_ENA (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_M (BIT(2)) +#define UHCI_RX_HUNG_INT_ENA_V 0x1 +#define UHCI_RX_HUNG_INT_ENA_S 2 +/* UHCI_TX_START_INT_ENA : R/W ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_ENA (BIT(1)) +#define UHCI_TX_START_INT_ENA_M (BIT(1)) +#define UHCI_TX_START_INT_ENA_V 0x1 +#define UHCI_TX_START_INT_ENA_S 1 +/* UHCI_RX_START_INT_ENA : R/W ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_ENA (BIT(0)) +#define UHCI_RX_START_INT_ENA_M (BIT(0)) +#define UHCI_RX_START_INT_ENA_V 0x1 +#define UHCI_RX_START_INT_ENA_S 0 + +#define UHCI_INT_CLR_REG(i) (REG_UHCI_BASE(i) + 0x10) +/* UHCI_SEND_A_Q_INT_CLR : WO ;bitpos:[5] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_A_Q_INT_CLR (BIT(5)) +#define UHCI_SEND_A_Q_INT_CLR_M (BIT(5)) +#define UHCI_SEND_A_Q_INT_CLR_V 0x1 +#define UHCI_SEND_A_Q_INT_CLR_S 5 +/* UHCI_SEND_S_Q_INT_CLR : WO ;bitpos:[4] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SEND_S_Q_INT_CLR (BIT(4)) +#define UHCI_SEND_S_Q_INT_CLR_M (BIT(4)) +#define UHCI_SEND_S_Q_INT_CLR_V 0x1 +#define UHCI_SEND_S_Q_INT_CLR_S 4 +/* UHCI_TX_HUNG_INT_CLR : WO ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_HUNG_INT_CLR (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_M (BIT(3)) +#define UHCI_TX_HUNG_INT_CLR_V 0x1 +#define UHCI_TX_HUNG_INT_CLR_S 3 +/* UHCI_RX_HUNG_INT_CLR : WO ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_HUNG_INT_CLR (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_M (BIT(2)) +#define UHCI_RX_HUNG_INT_CLR_V 0x1 +#define UHCI_RX_HUNG_INT_CLR_S 2 +/* UHCI_TX_START_INT_CLR : WO ;bitpos:[1] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_START_INT_CLR (BIT(1)) +#define UHCI_TX_START_INT_CLR_M (BIT(1)) +#define UHCI_TX_START_INT_CLR_V 0x1 +#define UHCI_TX_START_INT_CLR_S 1 +/* UHCI_RX_START_INT_CLR : WO ;bitpos:[0] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_START_INT_CLR (BIT(0)) +#define UHCI_RX_START_INT_CLR_M (BIT(0)) +#define UHCI_RX_START_INT_CLR_V 0x1 +#define UHCI_RX_START_INT_CLR_S 0 + +#define UHCI_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x14) +/* UHCI_SW_START : R/W ;bitpos:[8] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SW_START (BIT(8)) +#define UHCI_SW_START_M (BIT(8)) +#define UHCI_SW_START_V 0x1 +#define UHCI_SW_START_S 8 +/* UHCI_WAIT_SW_START : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_WAIT_SW_START (BIT(7)) +#define UHCI_WAIT_SW_START_M (BIT(7)) +#define UHCI_WAIT_SW_START_V 0x1 +#define UHCI_WAIT_SW_START_S 7 +/* UHCI_TX_ACK_NUM_RE : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_TX_ACK_NUM_RE (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_M (BIT(5)) +#define UHCI_TX_ACK_NUM_RE_V 0x1 +#define UHCI_TX_ACK_NUM_RE_S 5 +/* UHCI_TX_CHECK_SUM_RE : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_TX_CHECK_SUM_RE (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_M (BIT(4)) +#define UHCI_TX_CHECK_SUM_RE_V 0x1 +#define UHCI_TX_CHECK_SUM_RE_S 4 +/* UHCI_SAVE_HEAD : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SAVE_HEAD (BIT(3)) +#define UHCI_SAVE_HEAD_M (BIT(3)) +#define UHCI_SAVE_HEAD_V 0x1 +#define UHCI_SAVE_HEAD_S 3 +/* UHCI_CRC_DISABLE : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_CRC_DISABLE (BIT(2)) +#define UHCI_CRC_DISABLE_M (BIT(2)) +#define UHCI_CRC_DISABLE_V 0x1 +#define UHCI_CRC_DISABLE_S 2 +/* UHCI_CHECK_SEQ_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_CHECK_SEQ_EN (BIT(1)) +#define UHCI_CHECK_SEQ_EN_M (BIT(1)) +#define UHCI_CHECK_SEQ_EN_V 0x1 +#define UHCI_CHECK_SEQ_EN_S 1 +/* UHCI_CHECK_SUM_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_CHECK_SUM_EN (BIT(0)) +#define UHCI_CHECK_SUM_EN_M (BIT(0)) +#define UHCI_CHECK_SUM_EN_V 0x1 +#define UHCI_CHECK_SUM_EN_S 0 + +#define UHCI_STATE0_REG(i) (REG_UHCI_BASE(i) + 0x18) +/* UHCI_DECODE_STATE : RO ;bitpos:[5:3] ;default: 3'b0 ; */ +/*description: */ +#define UHCI_DECODE_STATE 0x00000007 +#define UHCI_DECODE_STATE_M ((UHCI_DECODE_STATE_V) << (UHCI_DECODE_STATE_S)) +#define UHCI_DECODE_STATE_V 0x7 +#define UHCI_DECODE_STATE_S 3 +/* UHCI_RX_ERR_CAUSE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define UHCI_RX_ERR_CAUSE 0x00000007 +#define UHCI_RX_ERR_CAUSE_M ((UHCI_RX_ERR_CAUSE_V) << (UHCI_RX_ERR_CAUSE_S)) +#define UHCI_RX_ERR_CAUSE_V 0x7 +#define UHCI_RX_ERR_CAUSE_S 0 + +#define UHCI_STATE1_REG(i) (REG_UHCI_BASE(i) + 0x1C) +/* UHCI_ENCODE_STATE : RO ;bitpos:[2:0] ;default: 3'b0 ; */ +/*description: */ +#define UHCI_ENCODE_STATE 0x00000007 +#define UHCI_ENCODE_STATE_M ((UHCI_ENCODE_STATE_V) << (UHCI_ENCODE_STATE_S)) +#define UHCI_ENCODE_STATE_V 0x7 +#define UHCI_ENCODE_STATE_S 0 + +#define UHCI_ESCAPE_CONF_REG(i) (REG_UHCI_BASE(i) + 0x20) +/* UHCI_RX_13_ESC_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_13_ESC_EN (BIT(7)) +#define UHCI_RX_13_ESC_EN_M (BIT(7)) +#define UHCI_RX_13_ESC_EN_V 0x1 +#define UHCI_RX_13_ESC_EN_S 7 +/* UHCI_RX_11_ESC_EN : R/W ;bitpos:[6] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_RX_11_ESC_EN (BIT(6)) +#define UHCI_RX_11_ESC_EN_M (BIT(6)) +#define UHCI_RX_11_ESC_EN_V 0x1 +#define UHCI_RX_11_ESC_EN_S 6 +/* UHCI_RX_DB_ESC_EN : R/W ;bitpos:[5] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_RX_DB_ESC_EN (BIT(5)) +#define UHCI_RX_DB_ESC_EN_M (BIT(5)) +#define UHCI_RX_DB_ESC_EN_V 0x1 +#define UHCI_RX_DB_ESC_EN_S 5 +/* UHCI_RX_C0_ESC_EN : R/W ;bitpos:[4] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_RX_C0_ESC_EN (BIT(4)) +#define UHCI_RX_C0_ESC_EN_M (BIT(4)) +#define UHCI_RX_C0_ESC_EN_V 0x1 +#define UHCI_RX_C0_ESC_EN_S 4 +/* UHCI_TX_13_ESC_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_13_ESC_EN (BIT(3)) +#define UHCI_TX_13_ESC_EN_M (BIT(3)) +#define UHCI_TX_13_ESC_EN_V 0x1 +#define UHCI_TX_13_ESC_EN_S 3 +/* UHCI_TX_11_ESC_EN : R/W ;bitpos:[2] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_TX_11_ESC_EN (BIT(2)) +#define UHCI_TX_11_ESC_EN_M (BIT(2)) +#define UHCI_TX_11_ESC_EN_V 0x1 +#define UHCI_TX_11_ESC_EN_S 2 +/* UHCI_TX_DB_ESC_EN : R/W ;bitpos:[1] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_TX_DB_ESC_EN (BIT(1)) +#define UHCI_TX_DB_ESC_EN_M (BIT(1)) +#define UHCI_TX_DB_ESC_EN_V 0x1 +#define UHCI_TX_DB_ESC_EN_S 1 +/* UHCI_TX_C0_ESC_EN : R/W ;bitpos:[0] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_TX_C0_ESC_EN (BIT(0)) +#define UHCI_TX_C0_ESC_EN_M (BIT(0)) +#define UHCI_TX_C0_ESC_EN_V 0x1 +#define UHCI_TX_C0_ESC_EN_S 0 + +#define UHCI_HUNG_CONF_REG(i) (REG_UHCI_BASE(i) + 0x24) +/* UHCI_RXFIFO_TIMEOUT_ENA : R/W ;bitpos:[23] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_RXFIFO_TIMEOUT_ENA (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_M (BIT(23)) +#define UHCI_RXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_RXFIFO_TIMEOUT_ENA_S 23 +/* UHCI_RXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[22:20] ;default: 3'b0 ; */ +/*description: */ +#define UHCI_RXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_M ((UHCI_RXFIFO_TIMEOUT_SHIFT_V) << (UHCI_RXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_RXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_RXFIFO_TIMEOUT_SHIFT_S 20 +/* UHCI_RXFIFO_TIMEOUT : R/W ;bitpos:[19:12] ;default: 8'h10 ; */ +/*description: */ +#define UHCI_RXFIFO_TIMEOUT 0x000000FF +#define UHCI_RXFIFO_TIMEOUT_M ((UHCI_RXFIFO_TIMEOUT_V) << (UHCI_RXFIFO_TIMEOUT_S)) +#define UHCI_RXFIFO_TIMEOUT_V 0xFF +#define UHCI_RXFIFO_TIMEOUT_S 12 +/* UHCI_TXFIFO_TIMEOUT_ENA : R/W ;bitpos:[11] ;default: 1'b1 ; */ +/*description: */ +#define UHCI_TXFIFO_TIMEOUT_ENA (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_M (BIT(11)) +#define UHCI_TXFIFO_TIMEOUT_ENA_V 0x1 +#define UHCI_TXFIFO_TIMEOUT_ENA_S 11 +/* UHCI_TXFIFO_TIMEOUT_SHIFT : R/W ;bitpos:[10:8] ;default: 3'b0 ; */ +/*description: */ +#define UHCI_TXFIFO_TIMEOUT_SHIFT 0x00000007 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_M ((UHCI_TXFIFO_TIMEOUT_SHIFT_V) << (UHCI_TXFIFO_TIMEOUT_SHIFT_S)) +#define UHCI_TXFIFO_TIMEOUT_SHIFT_V 0x7 +#define UHCI_TXFIFO_TIMEOUT_SHIFT_S 8 +/* UHCI_TXFIFO_TIMEOUT : R/W ;bitpos:[7:0] ;default: 8'h10 ; */ +/*description: */ +#define UHCI_TXFIFO_TIMEOUT 0x000000FF +#define UHCI_TXFIFO_TIMEOUT_M ((UHCI_TXFIFO_TIMEOUT_V) << (UHCI_TXFIFO_TIMEOUT_S)) +#define UHCI_TXFIFO_TIMEOUT_V 0xFF +#define UHCI_TXFIFO_TIMEOUT_S 0 + +#define UHCI_ACK_NUM_REG(i) (REG_UHCI_BASE(i) + 0x28) + +#define UHCI_RX_HEAD_REG(i) (REG_UHCI_BASE(i) + 0x2C) +/* UHCI_RX_HEAD : RO ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_RX_HEAD 0xFFFFFFFF +#define UHCI_RX_HEAD_M ((UHCI_RX_HEAD_V) << (UHCI_RX_HEAD_S)) +#define UHCI_RX_HEAD_V 0xFFFFFFFF +#define UHCI_RX_HEAD_S 0 + +#define UHCI_QUICK_SENT_REG(i) (REG_UHCI_BASE(i) + 0x30) +/* UHCI_ALWAYS_SEND_EN : R/W ;bitpos:[7] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_ALWAYS_SEND_EN (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_M (BIT(7)) +#define UHCI_ALWAYS_SEND_EN_V 0x1 +#define UHCI_ALWAYS_SEND_EN_S 7 +/* UHCI_ALWAYS_SEND_NUM : R/W ;bitpos:[6:4] ;default: 3'h0 ; */ +/*description: */ +#define UHCI_ALWAYS_SEND_NUM 0x00000007 +#define UHCI_ALWAYS_SEND_NUM_M ((UHCI_ALWAYS_SEND_NUM_V) << (UHCI_ALWAYS_SEND_NUM_S)) +#define UHCI_ALWAYS_SEND_NUM_V 0x7 +#define UHCI_ALWAYS_SEND_NUM_S 4 +/* UHCI_SINGLE_SEND_EN : R/W ;bitpos:[3] ;default: 1'b0 ; */ +/*description: */ +#define UHCI_SINGLE_SEND_EN (BIT(3)) +#define UHCI_SINGLE_SEND_EN_M (BIT(3)) +#define UHCI_SINGLE_SEND_EN_V 0x1 +#define UHCI_SINGLE_SEND_EN_S 3 +/* UHCI_SINGLE_SEND_NUM : R/W ;bitpos:[2:0] ;default: 3'h0 ; */ +/*description: */ +#define UHCI_SINGLE_SEND_NUM 0x00000007 +#define UHCI_SINGLE_SEND_NUM_M ((UHCI_SINGLE_SEND_NUM_V) << (UHCI_SINGLE_SEND_NUM_S)) +#define UHCI_SINGLE_SEND_NUM_V 0x7 +#define UHCI_SINGLE_SEND_NUM_S 0 + +#define UHCI_Q0_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x34) +/* UHCI_SEND_Q0_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q0_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_M ((UHCI_SEND_Q0_WORD0_V) << (UHCI_SEND_Q0_WORD0_S)) +#define UHCI_SEND_Q0_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD0_S 0 + +#define UHCI_Q0_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x38) +/* UHCI_SEND_Q0_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q0_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_M ((UHCI_SEND_Q0_WORD1_V) << (UHCI_SEND_Q0_WORD1_S)) +#define UHCI_SEND_Q0_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q0_WORD1_S 0 + +#define UHCI_Q1_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x3C) +/* UHCI_SEND_Q1_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q1_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_M ((UHCI_SEND_Q1_WORD0_V) << (UHCI_SEND_Q1_WORD0_S)) +#define UHCI_SEND_Q1_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD0_S 0 + +#define UHCI_Q1_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x40) +/* UHCI_SEND_Q1_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q1_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_M ((UHCI_SEND_Q1_WORD1_V) << (UHCI_SEND_Q1_WORD1_S)) +#define UHCI_SEND_Q1_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q1_WORD1_S 0 + +#define UHCI_Q2_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x44) +/* UHCI_SEND_Q2_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q2_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_M ((UHCI_SEND_Q2_WORD0_V) << (UHCI_SEND_Q2_WORD0_S)) +#define UHCI_SEND_Q2_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD0_S 0 + +#define UHCI_Q2_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x48) +/* UHCI_SEND_Q2_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q2_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_M ((UHCI_SEND_Q2_WORD1_V) << (UHCI_SEND_Q2_WORD1_S)) +#define UHCI_SEND_Q2_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q2_WORD1_S 0 + +#define UHCI_Q3_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x4C) +/* UHCI_SEND_Q3_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q3_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_M ((UHCI_SEND_Q3_WORD0_V) << (UHCI_SEND_Q3_WORD0_S)) +#define UHCI_SEND_Q3_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD0_S 0 + +#define UHCI_Q3_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x50) +/* UHCI_SEND_Q3_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q3_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_M ((UHCI_SEND_Q3_WORD1_V) << (UHCI_SEND_Q3_WORD1_S)) +#define UHCI_SEND_Q3_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q3_WORD1_S 0 + +#define UHCI_Q4_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x54) +/* UHCI_SEND_Q4_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q4_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_M ((UHCI_SEND_Q4_WORD0_V) << (UHCI_SEND_Q4_WORD0_S)) +#define UHCI_SEND_Q4_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD0_S 0 + +#define UHCI_Q4_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x58) +/* UHCI_SEND_Q4_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q4_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_M ((UHCI_SEND_Q4_WORD1_V) << (UHCI_SEND_Q4_WORD1_S)) +#define UHCI_SEND_Q4_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q4_WORD1_S 0 + +#define UHCI_Q5_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x5C) +/* UHCI_SEND_Q5_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q5_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_M ((UHCI_SEND_Q5_WORD0_V) << (UHCI_SEND_Q5_WORD0_S)) +#define UHCI_SEND_Q5_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD0_S 0 + +#define UHCI_Q5_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x60) +/* UHCI_SEND_Q5_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q5_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_M ((UHCI_SEND_Q5_WORD1_V) << (UHCI_SEND_Q5_WORD1_S)) +#define UHCI_SEND_Q5_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q5_WORD1_S 0 + +#define UHCI_Q6_WORD0_REG(i) (REG_UHCI_BASE(i) + 0x64) +/* UHCI_SEND_Q6_WORD0 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q6_WORD0 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_M ((UHCI_SEND_Q6_WORD0_V) << (UHCI_SEND_Q6_WORD0_S)) +#define UHCI_SEND_Q6_WORD0_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD0_S 0 + +#define UHCI_Q6_WORD1_REG(i) (REG_UHCI_BASE(i) + 0x68) +/* UHCI_SEND_Q6_WORD1 : R/W ;bitpos:[31:0] ;default: 32'h0 ; */ +/*description: */ +#define UHCI_SEND_Q6_WORD1 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_M ((UHCI_SEND_Q6_WORD1_V) << (UHCI_SEND_Q6_WORD1_S)) +#define UHCI_SEND_Q6_WORD1_V 0xFFFFFFFF +#define UHCI_SEND_Q6_WORD1_S 0 + +#define UHCI_ESC_CONF0_REG(i) (REG_UHCI_BASE(i) + 0x6C) +/* UHCI_SEPER_ESC_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdc ; */ +/*description: */ +#define UHCI_SEPER_ESC_CHAR1 0x000000FF +#define UHCI_SEPER_ESC_CHAR1_M ((UHCI_SEPER_ESC_CHAR1_V) << (UHCI_SEPER_ESC_CHAR1_S)) +#define UHCI_SEPER_ESC_CHAR1_V 0xFF +#define UHCI_SEPER_ESC_CHAR1_S 16 +/* UHCI_SEPER_ESC_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: */ +#define UHCI_SEPER_ESC_CHAR0 0x000000FF +#define UHCI_SEPER_ESC_CHAR0_M ((UHCI_SEPER_ESC_CHAR0_V) << (UHCI_SEPER_ESC_CHAR0_S)) +#define UHCI_SEPER_ESC_CHAR0_V 0xFF +#define UHCI_SEPER_ESC_CHAR0_S 8 +/* UHCI_SEPER_CHAR : R/W ;bitpos:[7:0] ;default: 8'hc0 ; */ +/*description: */ +#define UHCI_SEPER_CHAR 0x000000FF +#define UHCI_SEPER_CHAR_M ((UHCI_SEPER_CHAR_V) << (UHCI_SEPER_CHAR_S)) +#define UHCI_SEPER_CHAR_V 0xFF +#define UHCI_SEPER_CHAR_S 0 + +#define UHCI_ESC_CONF1_REG(i) (REG_UHCI_BASE(i) + 0x70) +/* UHCI_ESC_SEQ0_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdd ; */ +/*description: */ +#define UHCI_ESC_SEQ0_CHAR1 0x000000FF +#define UHCI_ESC_SEQ0_CHAR1_M ((UHCI_ESC_SEQ0_CHAR1_V) << (UHCI_ESC_SEQ0_CHAR1_S)) +#define UHCI_ESC_SEQ0_CHAR1_V 0xFF +#define UHCI_ESC_SEQ0_CHAR1_S 16 +/* UHCI_ESC_SEQ0_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: */ +#define UHCI_ESC_SEQ0_CHAR0 0x000000FF +#define UHCI_ESC_SEQ0_CHAR0_M ((UHCI_ESC_SEQ0_CHAR0_V) << (UHCI_ESC_SEQ0_CHAR0_S)) +#define UHCI_ESC_SEQ0_CHAR0_V 0xFF +#define UHCI_ESC_SEQ0_CHAR0_S 8 +/* UHCI_ESC_SEQ0 : R/W ;bitpos:[7:0] ;default: 8'hdb ; */ +/*description: */ +#define UHCI_ESC_SEQ0 0x000000FF +#define UHCI_ESC_SEQ0_M ((UHCI_ESC_SEQ0_V) << (UHCI_ESC_SEQ0_S)) +#define UHCI_ESC_SEQ0_V 0xFF +#define UHCI_ESC_SEQ0_S 0 + +#define UHCI_ESC_CONF2_REG(i) (REG_UHCI_BASE(i) + 0x74) +/* UHCI_ESC_SEQ1_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hde ; */ +/*description: */ +#define UHCI_ESC_SEQ1_CHAR1 0x000000FF +#define UHCI_ESC_SEQ1_CHAR1_M ((UHCI_ESC_SEQ1_CHAR1_V) << (UHCI_ESC_SEQ1_CHAR1_S)) +#define UHCI_ESC_SEQ1_CHAR1_V 0xFF +#define UHCI_ESC_SEQ1_CHAR1_S 16 +/* UHCI_ESC_SEQ1_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: */ +#define UHCI_ESC_SEQ1_CHAR0 0x000000FF +#define UHCI_ESC_SEQ1_CHAR0_M ((UHCI_ESC_SEQ1_CHAR0_V) << (UHCI_ESC_SEQ1_CHAR0_S)) +#define UHCI_ESC_SEQ1_CHAR0_V 0xFF +#define UHCI_ESC_SEQ1_CHAR0_S 8 +/* UHCI_ESC_SEQ1 : R/W ;bitpos:[7:0] ;default: 8'h11 ; */ +/*description: */ +#define UHCI_ESC_SEQ1 0x000000FF +#define UHCI_ESC_SEQ1_M ((UHCI_ESC_SEQ1_V) << (UHCI_ESC_SEQ1_S)) +#define UHCI_ESC_SEQ1_V 0xFF +#define UHCI_ESC_SEQ1_S 0 + +#define UHCI_ESC_CONF3_REG(i) (REG_UHCI_BASE(i) + 0x78) +/* UHCI_ESC_SEQ2_CHAR1 : R/W ;bitpos:[23:16] ;default: 8'hdf ; */ +/*description: */ +#define UHCI_ESC_SEQ2_CHAR1 0x000000FF +#define UHCI_ESC_SEQ2_CHAR1_M ((UHCI_ESC_SEQ2_CHAR1_V) << (UHCI_ESC_SEQ2_CHAR1_S)) +#define UHCI_ESC_SEQ2_CHAR1_V 0xFF +#define UHCI_ESC_SEQ2_CHAR1_S 16 +/* UHCI_ESC_SEQ2_CHAR0 : R/W ;bitpos:[15:8] ;default: 8'hdb ; */ +/*description: */ +#define UHCI_ESC_SEQ2_CHAR0 0x000000FF +#define UHCI_ESC_SEQ2_CHAR0_M ((UHCI_ESC_SEQ2_CHAR0_V) << (UHCI_ESC_SEQ2_CHAR0_S)) +#define UHCI_ESC_SEQ2_CHAR0_V 0xFF +#define UHCI_ESC_SEQ2_CHAR0_S 8 +/* UHCI_ESC_SEQ2 : R/W ;bitpos:[7:0] ;default: 8'h13 ; */ +/*description: */ +#define UHCI_ESC_SEQ2 0x000000FF +#define UHCI_ESC_SEQ2_M ((UHCI_ESC_SEQ2_V) << (UHCI_ESC_SEQ2_S)) +#define UHCI_ESC_SEQ2_V 0xFF +#define UHCI_ESC_SEQ2_S 0 + +#define UHCI_PKT_THRES_REG(i) (REG_UHCI_BASE(i) + 0x7C) +/* UHCI_PKT_THRS : R/W ;bitpos:[12:0] ;default: 13'h80 ; */ +/*description: */ +#define UHCI_PKT_THRS 0x00001FFF +#define UHCI_PKT_THRS_M ((UHCI_PKT_THRS_V) << (UHCI_PKT_THRS_S)) +#define UHCI_PKT_THRS_V 0x1FFF +#define UHCI_PKT_THRS_S 0 + +#define UHCI_DATE_REG(i) (REG_UHCI_BASE(i) + 0x80) +/* UHCI_DATE : R/W ;bitpos:[31:0] ;default: 32'h2001182 ; */ +/*description: */ +#define UHCI_DATE 0xFFFFFFFF +#define UHCI_DATE_M ((UHCI_DATE_V) << (UHCI_DATE_S)) +#define UHCI_DATE_V 0xFFFFFFFF +#define UHCI_DATE_S 0 + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/uhci_struct.h b/components/soc/soc/esp32s3/include/soc/uhci_struct.h new file mode 100644 index 000000000..36fe3d78b --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/uhci_struct.h @@ -0,0 +1,213 @@ +// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +#pragma once + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +typedef volatile struct { + union { + struct { + uint32_t tx_rst: 1; + uint32_t rx_rst: 1; + uint32_t uart0_ce: 1; + uint32_t uart1_ce: 1; + uint32_t uart2_ce: 1; + uint32_t seper_en: 1; + uint32_t head_en: 1; + uint32_t crc_rec_en: 1; + uint32_t uart_idle_eof_en: 1; + uint32_t len_eof_en: 1; + uint32_t encode_crc_en: 1; + uint32_t clk_en: 1; + uint32_t uart_rx_brk_eof_en: 1; + uint32_t reserved13: 19; + }; + uint32_t val; + } conf0; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_raw; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_st; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_ena; + union { + struct { + uint32_t rx_start: 1; + uint32_t tx_start: 1; + uint32_t rx_hung: 1; + uint32_t tx_hung: 1; + uint32_t send_s_q: 1; + uint32_t send_a_q: 1; + uint32_t reserved6: 26; + }; + uint32_t val; + } int_clr; + union { + struct { + uint32_t check_sum_en: 1; + uint32_t check_seq_en: 1; + uint32_t crc_disable: 1; + uint32_t save_head: 1; + uint32_t tx_check_sum_re: 1; + uint32_t tx_ack_num_re: 1; + uint32_t reserved6: 1; + uint32_t wait_sw_start: 1; + uint32_t sw_start: 1; + uint32_t reserved9: 12; + uint32_t reserved21: 11; + }; + uint32_t val; + } conf1; + union { + struct { + uint32_t rx_err_cause: 3; + uint32_t decode_state: 3; + uint32_t reserved6: 26; + }; + uint32_t val; + } state0; + union { + struct { + uint32_t encode_state: 3; + uint32_t reserved3: 29; + }; + uint32_t val; + } state1; + union { + struct { + uint32_t tx_c0_esc_en: 1; + uint32_t tx_db_esc_en: 1; + uint32_t tx_11_esc_en: 1; + uint32_t tx_13_esc_en: 1; + uint32_t rx_c0_esc_en: 1; + uint32_t rx_db_esc_en: 1; + uint32_t rx_11_esc_en: 1; + uint32_t rx_13_esc_en: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } escape_conf; + union { + struct { + uint32_t txfifo_timeout: 8; + uint32_t txfifo_timeout_shift: 3; + uint32_t txfifo_timeout_ena: 1; + uint32_t rxfifo_timeout: 8; + uint32_t rxfifo_timeout_shift: 3; + uint32_t rxfifo_timeout_ena: 1; + uint32_t reserved24: 8; + }; + uint32_t val; + } hung_conf; + uint32_t ack_num; /**/ + uint32_t rx_head; /**/ + union { + struct { + uint32_t single_send_num: 3; + uint32_t single_send_en: 1; + uint32_t always_send_num: 3; + uint32_t always_send_en: 1; + uint32_t reserved8: 24; + }; + uint32_t val; + } quick_sent; + struct { + uint32_t w_data[2]; /**/ + } q_data[7]; + union { + struct { + uint32_t seper_char: 8; + uint32_t seper_esc_char0: 8; + uint32_t seper_esc_char1: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf0; + union { + struct { + uint32_t seq0: 8; + uint32_t seq0_char0: 8; + uint32_t seq0_char1: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf1; + union { + struct { + uint32_t seq1: 8; + uint32_t seq1_char0: 8; + uint32_t seq1_char1: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf2; + union { + struct { + uint32_t seq2: 8; + uint32_t seq2_char0: 8; + uint32_t seq2_char1: 8; + uint32_t reserved24: 8; + }; + uint32_t val; + } esc_conf3; + union { + struct { + uint32_t thrs: 13; + uint32_t reserved13: 19; + }; + uint32_t val; + } pkt_thres; + uint32_t date; /**/ +} uhci_dev_t; + +extern uhci_dev_t UHCI0; +extern uhci_dev_t UHCI1; + +#ifdef __cplusplus +} +#endif diff --git a/components/soc/soc/esp32s3/include/soc/wdev_reg.h b/components/soc/soc/esp32s3/include/soc/wdev_reg.h new file mode 100644 index 000000000..3427eb107 --- /dev/null +++ b/components/soc/soc/esp32s3/include/soc/wdev_reg.h @@ -0,0 +1,20 @@ +// Copyright 2010-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#pragma once + +#include "soc.h" + +/* Hardware random number generator register */ +#define WDEV_RND_REG 0x60035110 diff --git a/components/soc/soc/esp32s3/interrupts.c b/components/soc/soc/esp32s3/interrupts.c new file mode 100644 index 000000000..1de9d9057 --- /dev/null +++ b/components/soc/soc/esp32s3/interrupts.c @@ -0,0 +1,87 @@ +// Copyright 2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/interrupts.h" + +const char *const esp_isr_names[ETS_MAX_INTR_SOURCE] = { + [0] = "WIFI_MAC", + [1] = "WIFI_NMI", + [2] = "WIFI_BB", + [3] = "BT_MAC", + [4] = "BT_BB", + [5] = "BT_BB_NMI", + [6] = "RWBT", + [7] = "RWBLE", + [8] = "RWBT_NMI", + [9] = "RWBLE_NMI", + [10] = "SLC0", + [11] = "SLC1", + [12] = "UHCI0", + [13] = "UHCI1", + [14] = "TG0_T0_LEVEL", + [15] = "TG0_T1_LEVEL", + [16] = "TG0_WDT_LEVEL", + [17] = "TG0_LACT_LEVEL", + [18] = "TG1_T0_LEVEL", + [19] = "TG1_T1_LEVEL", + [20] = "TG1_WDT_LEVEL", + [21] = "TG1_LACT_LEVEL", + [22] = "GPIO", + [23] = "GPIO_NMI", + [24] = "FROM_CPU0", + [25] = "FROM_CPU1", + [26] = "FROM_CPU2", + [27] = "FROM_CPU3", + [28] = "SPI0", + [29] = "SPI1", + [30] = "SPI2", + [31] = "SPI3", + [32] = "I2S0", + [33] = "I2S1", + [34] = "UART0", + [35] = "UART1", + [36] = "UART2", + [37] = "SDIO_HOST", + [38] = "ETH_MAC", + [39] = "PWM0", + [40] = "PWM1", + [41] = "PWM2", + [42] = "PWM3", + [43] = "LEDC", + [44] = "EFUSE", + [45] = "TWAI", + [46] = "RTC_CORE", + [47] = "RMT", + [48] = "PCNT", + [49] = "I2C_EXT0", + [50] = "I2C_EXT1", + [51] = "RSA", + [52] = "SPI1_DMA", + [53] = "SPI2_DMA", + [54] = "SPI3_DMA", + [55] = "WDT", + [56] = "TIMER1", + [57] = "TIMER2", + [58] = "TG0_T0_EDGE", + [59] = "TG0_T1_EDGE", + [60] = "TG0_WDT_EDGE", + [61] = "TG0_LACT_EDGE", + [62] = "TG1_T0_EDGE", + [63] = "TG1_T1_EDGE", + [64] = "TG1_WDT_EDGE", + [65] = "TG1_LACT_EDGE", + [66] = "MMU_IA", + [67] = "MPU_IA", + [68] = "CACHE_IA", +}; diff --git a/components/soc/soc/esp32s3/ledc_periph.c b/components/soc/soc/esp32s3/ledc_periph.c new file mode 100644 index 000000000..077a8cc6c --- /dev/null +++ b/components/soc/soc/esp32s3/ledc_periph.c @@ -0,0 +1,25 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/ledc_periph.h" +#include "soc/gpio_sig_map.h" + +/* + Bunch of constants for every LEDC peripheral: GPIO signals +*/ +const ledc_signal_conn_t ledc_periph_signal[1] = { + { + .sig_out0_idx = LEDC_LS_SIG_OUT0_IDX, + } +}; \ No newline at end of file diff --git a/components/soc/soc/esp32s3/rtc_io_periph.c b/components/soc/soc/esp32s3/rtc_io_periph.c new file mode 100644 index 000000000..b7c9eae3b --- /dev/null +++ b/components/soc/soc/esp32s3/rtc_io_periph.c @@ -0,0 +1,93 @@ +// Copyright 2018-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/rtc_io_periph.h" + +const int rtc_io_num_map[GPIO_PIN_COUNT] = { + RTCIO_GPIO0_CHANNEL, //GPIO0 + RTCIO_GPIO1_CHANNEL, //GPIO1 + RTCIO_GPIO2_CHANNEL, //GPIO2 + RTCIO_GPIO3_CHANNEL, //GPIO3 + RTCIO_GPIO4_CHANNEL, //GPIO4 + RTCIO_GPIO5_CHANNEL, //GPIO5 + RTCIO_GPIO6_CHANNEL, //GPIO6 + RTCIO_GPIO7_CHANNEL, //GPIO7 + RTCIO_GPIO8_CHANNEL, //GPIO8 + RTCIO_GPIO9_CHANNEL, //GPIO9 + RTCIO_GPIO10_CHANNEL, //GPIO10 + RTCIO_GPIO11_CHANNEL, //GPIO11 + RTCIO_GPIO12_CHANNEL, //GPIO12 + RTCIO_GPIO13_CHANNEL, //GPIO13 + RTCIO_GPIO14_CHANNEL, //GPIO14 + RTCIO_GPIO15_CHANNEL, //GPIO15 + RTCIO_GPIO16_CHANNEL, //GPIO16 + RTCIO_GPIO17_CHANNEL, //GPIO17 + RTCIO_GPIO18_CHANNEL, //GPIO18 + RTCIO_GPIO19_CHANNEL, //GPIO19 + RTCIO_GPIO20_CHANNEL, //GPIO20 + RTCIO_GPIO21_CHANNEL, //GPIO21 + -1,//GPIO22 + -1,//GPIO23 + -1,//GPIO24 + -1,//GPIO25 + -1,//GPIO26 + -1,//GPIO27 + -1,//GPIO28 + -1,//GPIO29 + -1,//GPIO30 + -1,//GPIO31 + -1,//GPIO32 + -1,//GPIO33 + -1,//GPIO34 + -1,//GPIO35 + -1,//GPIO36 + -1,//GPIO37 + -1,//GPIO38 + -1,//GPIO39 + -1,//GPIO40 + -1,//GPIO41 + -1,//GPIO42 + -1,//GPIO43 + -1,//GPIO44 + -1,//GPIO45 + -1,//GPIO46 + -1,//GPIO47 +}; + +//Reg,Mux,Fun,IE,Up,Down,Rtc_number +const rtc_io_desc_t rtc_io_desc[SOC_RTC_IO_PIN_COUNT] = { + /*REG MUX select function select Input enable Pullup Pulldown Sleep select Sleep input enable Sleep output enable PAD hold Pad force hold Mask of drive capability Offset gpio number */ + {RTC_IO_TOUCH_PAD0_REG, RTC_IO_TOUCH_PAD0_MUX_SEL_M, RTC_IO_TOUCH_PAD0_FUN_SEL_S, RTC_IO_TOUCH_PAD0_FUN_IE_M, RTC_IO_TOUCH_PAD0_RUE_M, RTC_IO_TOUCH_PAD0_RDE_M, RTC_IO_TOUCH_PAD0_SLP_SEL_M, RTC_IO_TOUCH_PAD0_SLP_IE_M, RTC_IO_TOUCH_PAD0_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD0_HOLD_M, RTC_IO_TOUCH_PAD0_DRV_V, RTC_IO_TOUCH_PAD0_DRV_S, RTCIO_CHANNEL_0_GPIO_NUM}, //0 + {RTC_IO_TOUCH_PAD1_REG, RTC_IO_TOUCH_PAD1_MUX_SEL_M, RTC_IO_TOUCH_PAD1_FUN_SEL_S, RTC_IO_TOUCH_PAD1_FUN_IE_M, RTC_IO_TOUCH_PAD1_RUE_M, RTC_IO_TOUCH_PAD1_RDE_M, RTC_IO_TOUCH_PAD1_SLP_SEL_M, RTC_IO_TOUCH_PAD1_SLP_IE_M, RTC_IO_TOUCH_PAD1_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD1_HOLD_M, RTC_IO_TOUCH_PAD1_DRV_V, RTC_IO_TOUCH_PAD1_DRV_S, RTCIO_CHANNEL_1_GPIO_NUM}, //1 + {RTC_IO_TOUCH_PAD2_REG, RTC_IO_TOUCH_PAD2_MUX_SEL_M, RTC_IO_TOUCH_PAD2_FUN_SEL_S, RTC_IO_TOUCH_PAD2_FUN_IE_M, RTC_IO_TOUCH_PAD2_RUE_M, RTC_IO_TOUCH_PAD2_RDE_M, RTC_IO_TOUCH_PAD2_SLP_SEL_M, RTC_IO_TOUCH_PAD2_SLP_IE_M, RTC_IO_TOUCH_PAD2_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD2_HOLD_M, RTC_IO_TOUCH_PAD2_DRV_V, RTC_IO_TOUCH_PAD2_DRV_S, RTCIO_CHANNEL_2_GPIO_NUM}, //2 + {RTC_IO_TOUCH_PAD3_REG, RTC_IO_TOUCH_PAD3_MUX_SEL_M, RTC_IO_TOUCH_PAD3_FUN_SEL_S, RTC_IO_TOUCH_PAD3_FUN_IE_M, RTC_IO_TOUCH_PAD3_RUE_M, RTC_IO_TOUCH_PAD3_RDE_M, RTC_IO_TOUCH_PAD3_SLP_SEL_M, RTC_IO_TOUCH_PAD3_SLP_IE_M, RTC_IO_TOUCH_PAD3_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD3_HOLD_M, RTC_IO_TOUCH_PAD3_DRV_V, RTC_IO_TOUCH_PAD3_DRV_S, RTCIO_CHANNEL_3_GPIO_NUM}, //3 + {RTC_IO_TOUCH_PAD4_REG, RTC_IO_TOUCH_PAD4_MUX_SEL_M, RTC_IO_TOUCH_PAD4_FUN_SEL_S, RTC_IO_TOUCH_PAD4_FUN_IE_M, RTC_IO_TOUCH_PAD4_RUE_M, RTC_IO_TOUCH_PAD4_RDE_M, RTC_IO_TOUCH_PAD4_SLP_SEL_M, RTC_IO_TOUCH_PAD4_SLP_IE_M, RTC_IO_TOUCH_PAD4_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD4_HOLD_M, RTC_IO_TOUCH_PAD4_DRV_V, RTC_IO_TOUCH_PAD4_DRV_S, RTCIO_CHANNEL_4_GPIO_NUM}, //4 + {RTC_IO_TOUCH_PAD5_REG, RTC_IO_TOUCH_PAD5_MUX_SEL_M, RTC_IO_TOUCH_PAD5_FUN_SEL_S, RTC_IO_TOUCH_PAD5_FUN_IE_M, RTC_IO_TOUCH_PAD5_RUE_M, RTC_IO_TOUCH_PAD5_RDE_M, RTC_IO_TOUCH_PAD5_SLP_SEL_M, RTC_IO_TOUCH_PAD5_SLP_IE_M, RTC_IO_TOUCH_PAD5_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD5_HOLD_M, RTC_IO_TOUCH_PAD5_DRV_V, RTC_IO_TOUCH_PAD5_DRV_S, RTCIO_CHANNEL_5_GPIO_NUM}, //5 + {RTC_IO_TOUCH_PAD6_REG, RTC_IO_TOUCH_PAD6_MUX_SEL_M, RTC_IO_TOUCH_PAD6_FUN_SEL_S, RTC_IO_TOUCH_PAD6_FUN_IE_M, RTC_IO_TOUCH_PAD6_RUE_M, RTC_IO_TOUCH_PAD6_RDE_M, RTC_IO_TOUCH_PAD6_SLP_SEL_M, RTC_IO_TOUCH_PAD6_SLP_IE_M, RTC_IO_TOUCH_PAD6_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD6_HOLD_M, RTC_IO_TOUCH_PAD6_DRV_V, RTC_IO_TOUCH_PAD6_DRV_S, RTCIO_CHANNEL_6_GPIO_NUM}, //6 + {RTC_IO_TOUCH_PAD7_REG, RTC_IO_TOUCH_PAD7_MUX_SEL_M, RTC_IO_TOUCH_PAD7_FUN_SEL_S, RTC_IO_TOUCH_PAD7_FUN_IE_M, RTC_IO_TOUCH_PAD7_RUE_M, RTC_IO_TOUCH_PAD7_RDE_M, RTC_IO_TOUCH_PAD7_SLP_SEL_M, RTC_IO_TOUCH_PAD7_SLP_IE_M, RTC_IO_TOUCH_PAD7_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD7_HOLD_M, RTC_IO_TOUCH_PAD7_DRV_V, RTC_IO_TOUCH_PAD7_DRV_S, RTCIO_CHANNEL_7_GPIO_NUM}, //7 + {RTC_IO_TOUCH_PAD8_REG, RTC_IO_TOUCH_PAD8_MUX_SEL_M, RTC_IO_TOUCH_PAD8_FUN_SEL_S, RTC_IO_TOUCH_PAD8_FUN_IE_M, RTC_IO_TOUCH_PAD8_RUE_M, RTC_IO_TOUCH_PAD8_RDE_M, RTC_IO_TOUCH_PAD8_SLP_SEL_M, RTC_IO_TOUCH_PAD8_SLP_IE_M, RTC_IO_TOUCH_PAD8_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD8_HOLD_M, RTC_IO_TOUCH_PAD8_DRV_V, RTC_IO_TOUCH_PAD8_DRV_S, RTCIO_CHANNEL_8_GPIO_NUM}, //8 + {RTC_IO_TOUCH_PAD9_REG, RTC_IO_TOUCH_PAD9_MUX_SEL_M, RTC_IO_TOUCH_PAD9_FUN_SEL_S, RTC_IO_TOUCH_PAD9_FUN_IE_M, RTC_IO_TOUCH_PAD9_RUE_M, RTC_IO_TOUCH_PAD9_RDE_M, RTC_IO_TOUCH_PAD9_SLP_SEL_M, RTC_IO_TOUCH_PAD9_SLP_IE_M, RTC_IO_TOUCH_PAD9_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD9_HOLD_M, RTC_IO_TOUCH_PAD9_DRV_V, RTC_IO_TOUCH_PAD9_DRV_S, RTCIO_CHANNEL_9_GPIO_NUM}, //9 + {RTC_IO_TOUCH_PAD10_REG, RTC_IO_TOUCH_PAD10_MUX_SEL_M, RTC_IO_TOUCH_PAD10_FUN_SEL_S, RTC_IO_TOUCH_PAD10_FUN_IE_M, RTC_IO_TOUCH_PAD10_RUE_M, RTC_IO_TOUCH_PAD10_RDE_M, RTC_IO_TOUCH_PAD10_SLP_SEL_M, RTC_IO_TOUCH_PAD10_SLP_IE_M, RTC_IO_TOUCH_PAD10_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD10_HOLD_M, RTC_IO_TOUCH_PAD10_DRV_V, RTC_IO_TOUCH_PAD10_DRV_S, RTCIO_CHANNEL_10_GPIO_NUM}, //10 + {RTC_IO_TOUCH_PAD11_REG, RTC_IO_TOUCH_PAD11_MUX_SEL_M, RTC_IO_TOUCH_PAD11_FUN_SEL_S, RTC_IO_TOUCH_PAD11_FUN_IE_M, RTC_IO_TOUCH_PAD11_RUE_M, RTC_IO_TOUCH_PAD11_RDE_M, RTC_IO_TOUCH_PAD11_SLP_SEL_M, RTC_IO_TOUCH_PAD11_SLP_IE_M, RTC_IO_TOUCH_PAD11_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD11_HOLD_M, RTC_IO_TOUCH_PAD11_DRV_V, RTC_IO_TOUCH_PAD11_DRV_S, RTCIO_CHANNEL_11_GPIO_NUM}, //11 + {RTC_IO_TOUCH_PAD12_REG, RTC_IO_TOUCH_PAD12_MUX_SEL_M, RTC_IO_TOUCH_PAD12_FUN_SEL_S, RTC_IO_TOUCH_PAD12_FUN_IE_M, RTC_IO_TOUCH_PAD12_RUE_M, RTC_IO_TOUCH_PAD12_RDE_M, RTC_IO_TOUCH_PAD12_SLP_SEL_M, RTC_IO_TOUCH_PAD12_SLP_IE_M, RTC_IO_TOUCH_PAD12_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD12_HOLD_M, RTC_IO_TOUCH_PAD12_DRV_V, RTC_IO_TOUCH_PAD12_DRV_S, RTCIO_CHANNEL_12_GPIO_NUM}, //12 + {RTC_IO_TOUCH_PAD13_REG, RTC_IO_TOUCH_PAD13_MUX_SEL_M, RTC_IO_TOUCH_PAD13_FUN_SEL_S, RTC_IO_TOUCH_PAD13_FUN_IE_M, RTC_IO_TOUCH_PAD13_RUE_M, RTC_IO_TOUCH_PAD13_RDE_M, RTC_IO_TOUCH_PAD13_SLP_SEL_M, RTC_IO_TOUCH_PAD13_SLP_IE_M, RTC_IO_TOUCH_PAD13_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD13_HOLD_M, RTC_IO_TOUCH_PAD13_DRV_V, RTC_IO_TOUCH_PAD13_DRV_S, RTCIO_CHANNEL_13_GPIO_NUM}, //13 + {RTC_IO_TOUCH_PAD14_REG, RTC_IO_TOUCH_PAD14_MUX_SEL_M, RTC_IO_TOUCH_PAD14_FUN_SEL_S, RTC_IO_TOUCH_PAD14_FUN_IE_M, RTC_IO_TOUCH_PAD14_RUE_M, RTC_IO_TOUCH_PAD14_RDE_M, RTC_IO_TOUCH_PAD14_SLP_SEL_M, RTC_IO_TOUCH_PAD14_SLP_IE_M, RTC_IO_TOUCH_PAD14_SLP_OE_M, 0, RTC_CNTL_TOUCH_PAD14_HOLD_M, RTC_IO_TOUCH_PAD14_DRV_V, RTC_IO_TOUCH_PAD14_DRV_S, RTCIO_CHANNEL_14_GPIO_NUM}, //14 + {RTC_IO_XTAL_32P_PAD_REG, RTC_IO_X32P_MUX_SEL_M, RTC_IO_X32P_FUN_SEL_S, RTC_IO_X32P_FUN_IE_M, RTC_IO_X32P_RUE_M, RTC_IO_X32P_RDE_M, RTC_IO_X32P_SLP_SEL_M, RTC_IO_X32P_SLP_IE_M, RTC_IO_X32P_SLP_OE_M, 0, RTC_CNTL_X32P_HOLD_M, RTC_IO_X32P_DRV_V, RTC_IO_X32P_DRV_S, RTCIO_CHANNEL_15_GPIO_NUM}, //15 + {RTC_IO_XTAL_32N_PAD_REG, RTC_IO_X32N_MUX_SEL_M, RTC_IO_X32N_FUN_SEL_S, RTC_IO_X32N_FUN_IE_M, RTC_IO_X32N_RUE_M, RTC_IO_X32N_RDE_M, RTC_IO_X32N_SLP_SEL_M, RTC_IO_X32N_SLP_IE_M, RTC_IO_X32N_SLP_OE_M, 0, RTC_CNTL_X32N_HOLD_M, RTC_IO_X32N_DRV_V, RTC_IO_X32N_DRV_S, RTCIO_CHANNEL_16_GPIO_NUM}, //16 + {RTC_IO_PAD_DAC1_REG, RTC_IO_PDAC1_MUX_SEL_M, RTC_IO_PDAC1_FUN_SEL_S, RTC_IO_PDAC1_FUN_IE_M, RTC_IO_PDAC1_RUE_M, RTC_IO_PDAC1_RDE_M, RTC_IO_PDAC1_SLP_SEL_M, RTC_IO_PDAC1_SLP_IE_M, RTC_IO_PDAC1_SLP_OE_M, 0, RTC_CNTL_PDAC1_HOLD_M, RTC_IO_PDAC1_DRV_V, RTC_IO_PDAC1_DRV_S, RTCIO_CHANNEL_17_GPIO_NUM}, //17 + {RTC_IO_PAD_DAC2_REG, RTC_IO_PDAC2_MUX_SEL_M, RTC_IO_PDAC2_FUN_SEL_S, RTC_IO_PDAC2_FUN_IE_M, RTC_IO_PDAC2_RUE_M, RTC_IO_PDAC2_RDE_M, RTC_IO_PDAC2_SLP_SEL_M, RTC_IO_PDAC2_SLP_IE_M, RTC_IO_PDAC2_SLP_OE_M, 0, RTC_CNTL_PDAC2_HOLD_M, RTC_IO_PDAC2_DRV_V, RTC_IO_PDAC2_DRV_S, RTCIO_CHANNEL_18_GPIO_NUM}, //18 + {RTC_IO_RTC_PAD19_REG, RTC_IO_PAD19_MUX_SEL_M, RTC_IO_PAD19_FUN_SEL_S, RTC_IO_PAD19_FUN_IE_M, RTC_IO_PAD19_RUE_M, RTC_IO_PAD19_RDE_M, RTC_IO_PAD19_SLP_SEL_M, RTC_IO_PAD19_SLP_IE_M, RTC_IO_PAD19_SLP_OE_M, 0, RTC_CNTL_PAD19_HOLD_M, RTC_IO_PAD19_DRV_V, RTC_IO_PAD19_DRV_S, RTCIO_CHANNEL_19_GPIO_NUM}, //19 + {RTC_IO_RTC_PAD20_REG, RTC_IO_PAD20_MUX_SEL_M, RTC_IO_PAD20_FUN_SEL_S, RTC_IO_PAD20_FUN_IE_M, RTC_IO_PAD20_RUE_M, RTC_IO_PAD20_RDE_M, RTC_IO_PAD20_SLP_SEL_M, RTC_IO_PAD20_SLP_IE_M, RTC_IO_PAD20_SLP_OE_M, 0, RTC_CNTL_PAD20_HOLD_M, RTC_IO_PAD20_DRV_V, RTC_IO_PAD20_DRV_S, RTCIO_CHANNEL_20_GPIO_NUM}, //20 + {RTC_IO_RTC_PAD21_REG, RTC_IO_PAD21_MUX_SEL_M, RTC_IO_PAD21_FUN_SEL_S, RTC_IO_PAD21_FUN_IE_M, RTC_IO_PAD21_RUE_M, RTC_IO_PAD21_RDE_M, RTC_IO_PAD21_SLP_SEL_M, RTC_IO_PAD21_SLP_IE_M, RTC_IO_PAD21_SLP_OE_M, 0, RTC_CNTL_PAD21_HOLD_M, RTC_IO_PAD21_DRV_V, RTC_IO_PAD21_DRV_S, RTCIO_CHANNEL_21_GPIO_NUM}, //21 +}; diff --git a/components/soc/soc/esp32s3/rtc_periph.c b/components/soc/soc/esp32s3/rtc_periph.c new file mode 100644 index 000000000..e69de29bb diff --git a/components/soc/soc/esp32s3/sdio_slave_periph.c b/components/soc/soc/esp32s3/sdio_slave_periph.c new file mode 100644 index 000000000..e23a74dfc --- /dev/null +++ b/components/soc/soc/esp32s3/sdio_slave_periph.c @@ -0,0 +1,42 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include +#include "soc/sdio_slave_periph.h" +#include "soc/gpio_periph.h" + +// I/O slot of sdio slave: +// 0: GPIO 6, 11, 7, 8, 9, 10, +// 1: GPIO 14, 15, 2, 4, 12, 13 for CLK, CMD, D0, D1, D2, D3 respectively. +// only one peripheral for SDIO and only one slot can work at the same time. +// currently slot 0 is occupied by SPI for flash +const sdio_slave_slot_info_t sdio_slave_slot_info[2] = { + { + .clk_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CLK, + .cmd_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_CMD, + .d0_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D0, + .d1_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D1, + .d2_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D2, + .d3_gpio = SDIO_SLAVE_SLOT0_IOMUX_PIN_NUM_D3, + .func = SDIO_SLAVE_SLOT0_FUNC, + }, { + .clk_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CLK, + .cmd_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_CMD, + .d0_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D0, + .d1_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D1, + .d2_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D2, + .d3_gpio = SDIO_SLAVE_SLOT1_IOMUX_PIN_NUM_D3, + .func = SDIO_SLAVE_SLOT1_FUNC, + }, +}; diff --git a/components/soc/soc/esp32s3/sdmmc_periph.c b/components/soc/soc/esp32s3/sdmmc_periph.c new file mode 100644 index 000000000..982426573 --- /dev/null +++ b/components/soc/soc/esp32s3/sdmmc_periph.c @@ -0,0 +1,50 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/sdmmc_periph.h" + +const sdmmc_slot_info_t sdmmc_slot_info[2] = { + { + .clk_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_CLK, + .cmd_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_CMD, + .d0_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D0, + .d1_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D1, + .d2_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D2, + .d3_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D3, + .d4_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D4, + .d5_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D5, + .d6_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D6, + .d7_gpio = SDMMC_SLOT0_IOMUX_PIN_NUM_D7, + .card_detect = HOST_CARD_DETECT_N_1_IDX, + .write_protect = HOST_CARD_WRITE_PRT_1_IDX, + .card_int = HOST_CARD_INT_N_1_IDX, + .width = 8 + }, + { + .clk_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_CLK, + .cmd_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_CMD, + .d0_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D0, + .d1_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D1, + .d2_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D2, + .d3_gpio = SDMMC_SLOT1_IOMUX_PIN_NUM_D3, + .d4_gpio = -1, //slot1 has no D4-7 + .d5_gpio = -1, + .d6_gpio = -1, + .d7_gpio = -1, + .card_detect = HOST_CARD_DETECT_N_2_IDX, + .write_protect = HOST_CARD_WRITE_PRT_2_IDX, + .card_int = HOST_CARD_INT_N_2_IDX, + .width = 4 + } +}; \ No newline at end of file diff --git a/components/soc/soc/esp32s3/spi_periph.c b/components/soc/soc/esp32s3/spi_periph.c new file mode 100644 index 000000000..3af7e9f15 --- /dev/null +++ b/components/soc/soc/esp32s3/spi_periph.c @@ -0,0 +1,97 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/spi_periph.h" +#include "stddef.h" + +/* + Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const spi_signal_conn_t spi_periph_signal[SOC_SPI_PERIPH_NUM] = { + { + .spiclk_out = SPICLK_OUT_MUX_IDX, + .spiclk_in = 0,/* SPI clock is not an input signal*/ + .spid_out = SPID_OUT_IDX, + .spiq_out = SPIQ_OUT_IDX, + .spiwp_out = SPIWP_OUT_IDX, + .spihd_out = SPIHD_OUT_IDX, + .spid_in = SPID_IN_IDX, + .spiq_in = SPIQ_IN_IDX, + .spiwp_in = SPIWP_IN_IDX, + .spihd_in = SPIHD_IN_IDX, + .spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX},/* SPI0/1 do not have CS2 now */ + .spics_in = 0,/* SPI cs is not an input signal*/ + .spiclk_iomux_pin = SPI_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = SPI_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = SPI_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = SPI_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = SPI_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = SPI_IOMUX_PIN_NUM_CS, + .irq = ETS_SPI1_INTR_SOURCE, + .irq_dma = -1, + .module = PERIPH_SPI_MODULE, + .hw = (spi_dev_t *) &SPIMEM1, + .func = SPI_FUNC_NUM, + }, { + .spiclk_out = FSPICLK_OUT_MUX_IDX, + .spiclk_in = FSPICLK_IN_IDX, + .spid_out = FSPID_OUT_IDX, + .spiq_out = FSPIQ_OUT_IDX, + .spiwp_out = FSPIWP_OUT_IDX, + .spihd_out = FSPIHD_OUT_IDX, + .spid_in = FSPID_IN_IDX, + .spiq_in = FSPIQ_IN_IDX, + .spiwp_in = FSPIWP_IN_IDX, + .spihd_in = FSPIHD_IN_IDX, + .spics_out = {FSPICS0_OUT_IDX, FSPICS1_OUT_IDX, FSPICS2_OUT_IDX}, + .spics_in = FSPICS0_IN_IDX, + .spiclk_iomux_pin = FSPI_IOMUX_PIN_NUM_CLK, + .spid_iomux_pin = FSPI_IOMUX_PIN_NUM_MOSI, + .spiq_iomux_pin = FSPI_IOMUX_PIN_NUM_MISO, + .spiwp_iomux_pin = FSPI_IOMUX_PIN_NUM_WP, + .spihd_iomux_pin = FSPI_IOMUX_PIN_NUM_HD, + .spics0_iomux_pin = FSPI_IOMUX_PIN_NUM_CS, + .irq = ETS_SPI2_INTR_SOURCE, + .irq_dma = ETS_SPI2_DMA_INTR_SOURCE, + .module = PERIPH_FSPI_MODULE, + .hw = &GPSPI2, + .func = FSPI_FUNC_NUM, + }, { + .spiclk_out = SPI3_CLK_OUT_MUX_IDX, + .spiclk_in = SPI3_CLK_IN_IDX, + .spid_out = SPI3_D_OUT_IDX, + .spiq_out = SPI3_Q_OUT_IDX, + //SPI3 doesn't have wp and hd signals + .spiwp_out = -1, + .spihd_out = -1, + .spid_in = SPI3_D_IN_IDX, + .spiq_in = SPI3_Q_IN_IDX, + .spiwp_in = -1, + .spihd_in = -1, + .spics_out = {SPI3_CS0_OUT_IDX, SPI3_CS1_OUT_IDX, SPI3_CS2_OUT_IDX}, + .spics_in = SPI3_CS0_IN_IDX, + //SPI3 doesn't have iomux pins + .spiclk_iomux_pin = -1, + .spid_iomux_pin = -1, + .spiq_iomux_pin = -1, + .spiwp_iomux_pin = -1, + .spihd_iomux_pin = -1, + .spics0_iomux_pin = -1, + .irq = ETS_SPI3_INTR_SOURCE, + .irq_dma = ETS_SPI3_DMA_INTR_SOURCE, + .module = PERIPH_HSPI_MODULE, + .hw = &GPSPI3, + .func = -1, + } +}; diff --git a/components/soc/soc/esp32s3/touch_sensor_periph.c b/components/soc/soc/esp32s3/touch_sensor_periph.c new file mode 100644 index 000000000..6f1e26a20 --- /dev/null +++ b/components/soc/soc/esp32s3/touch_sensor_periph.c @@ -0,0 +1,29 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/touch_sensor_periph.h" + +/* Store IO number corresponding to the Touch Sensor channel number. */ +const int touch_sensor_channel_io_map[SOC_TOUCH_SENSOR_NUM] = { + -1, + TOUCH_PAD_NUM1_GPIO_NUM, + TOUCH_PAD_NUM2_GPIO_NUM, + TOUCH_PAD_NUM3_GPIO_NUM, + TOUCH_PAD_NUM4_GPIO_NUM, + TOUCH_PAD_NUM5_GPIO_NUM, + TOUCH_PAD_NUM6_GPIO_NUM, + TOUCH_PAD_NUM7_GPIO_NUM, + TOUCH_PAD_NUM8_GPIO_NUM, + TOUCH_PAD_NUM9_GPIO_NUM, +}; \ No newline at end of file diff --git a/components/soc/soc/esp32s3/uart_periph.c b/components/soc/soc/esp32s3/uart_periph.c new file mode 100644 index 000000000..4e0ae39a5 --- /dev/null +++ b/components/soc/soc/esp32s3/uart_periph.c @@ -0,0 +1,37 @@ +// Copyright 2015-2020 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +#include "soc/uart_periph.h" + +/* + Bunch of constants for every UART peripheral: GPIO signals, irqs, hw addr of registers etc +*/ +const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = { + { + .tx_sig = U0TXD_OUT_IDX, + .rx_sig = U0RXD_IN_IDX, + .rts_sig = U0RTS_OUT_IDX, + .cts_sig = U0CTS_IN_IDX, + .irq = ETS_UART0_INTR_SOURCE, + .module = PERIPH_UART0_MODULE, + }, + { + .tx_sig = U1TXD_OUT_IDX, + .rx_sig = U1RXD_IN_IDX, + .rts_sig = U1RTS_OUT_IDX, + .cts_sig = U1CTS_IN_IDX, + .irq = ETS_UART1_INTR_SOURCE, + .module = PERIPH_UART1_MODULE, + } +}; \ No newline at end of file