Psram driver cleanup: remove DMA and test functions, tabs to spaces, add copyright header
This commit is contained in:
Jeroen Domburg
parent
0a88301fce
commit
15012589a5
336
components/esp32/psram.c
Executable file → Normal file
336
components/esp32/psram.c
Executable file → Normal file
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@ -1,7 +1,20 @@
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// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "esp_types.h"
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#include "rom/ets_sys.h"
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#include "psram.h"
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//#include "spi.h"
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#include "soc/io_mux_reg.h"
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#include "soc/dport_reg.h"
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#include "rom/gpio.h"
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@ -42,7 +55,6 @@ typedef struct {
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static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode);
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static void psram_clear_spi_fifo(psram_spi_num_t spiNum)
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{
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int i;
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@ -51,14 +63,6 @@ static void psram_clear_spi_fifo(psram_spi_num_t spiNum)
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}
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}
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static void disp_fifo(psram_spi_num_t spiNum)
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{
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int i;
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for(i=0;i<16;i++){
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ets_printf(" FIFO[%d]: 0x%08x\n",i, READ_PERI_REG(SPI_W0_REG(spiNum)+i*4));
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}
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}
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//set basic SPI write mode
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static void psram_set_basic_write_mode(psram_spi_num_t spiNum)
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{
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@ -677,18 +681,6 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode) //psram init
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#if GPIO_MATRIX_FOR_40M
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psram_gpio_config(mode);
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// /* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping
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// * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd
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// *
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// * @return None
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// */
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// uint32_t ishspi = ( (6 & 0x3f) << 0) //clk
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// | ( (7 & 0x3f) << 6) //d0
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// | ( (8 & 0x3f) << 12) //d1
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// | ( (11 & 0x3f) << 18) //cs
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// | ( (9 & 0x3f) << 24); //d2
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// SelectSpiFunction(ishspi);
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// spi_dummy_len_fix(1, 2);
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#endif
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@ -775,303 +767,3 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode)
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CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM)
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}
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typedef enum {
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SPI_INT_SRC_TRANS_DONE = SPI_TRANS_DONE,
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SPI_INT_SRC_WR_STA_DONE = SPI_SLV_WR_STA_DONE,
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SPI_INT_SRC_RD_STA_DONE = SPI_SLV_RD_STA_DONE,
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SPI_INT_SRC_WR_BUF_DONE = SPI_SLV_WR_BUF_DONE,
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SPI_INT_SRC_RD_BUF_DONE = SPI_SLV_RD_BUF_DONE,
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SPI_INT_SRC_ONE_BUF_RECV_DONE = SPI_IN_SUC_EOF_INT_ENA,
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SPI_INT_SRC_ONE_BUF_SEND_DONE = SPI_OUT_EOF_INT_ENA,
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} spi_int_src_t;
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/**
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* @brief DMA queue description.
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*/
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typedef struct {
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uint32_t block_size: 12;
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uint32_t data_length: 12;
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uint32_t unused: 5;
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uint32_t sub_sof: 1;
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uint32_t eof: 1;
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uint32_t owner: 1;
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uint32_t buf_ptr;
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uint32_t next_link_ptr;
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} dma_queue_t;
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/**
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* @brief Initialize DMA and create a SPI DMA instance.
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*
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*/
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//int spi_dma_init(spi_dma_attr_t *obj, void *isr)
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int psram_dma_tx(int dma_channel, uint32_t addr, uint32_t* buf, size_t data_len)
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{
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int spi_num = 1;
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// Reset DMA
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SET_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
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CLEAR_PERI_REG_MASK(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_START);
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CLEAR_PERI_REG_MASK(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_START);
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CLEAR_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
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// Select DMA channel.
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SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_channel, ((spi_num - 1) * 2));
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);//////add
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// enable send intr
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SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_SEND_DONE);
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SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_RECV_DONE);
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// Clear all of interrupt source
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//spi_int_clear(obj->spi_num);
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CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_INT_SRC_TRANS_DONE
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| SPI_INT_SRC_WR_STA_DONE
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| SPI_INT_SRC_RD_STA_DONE
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| SPI_INT_SRC_WR_BUF_DONE
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| SPI_INT_SRC_RD_BUF_DONE);
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dma_queue_t* dma_link = (dma_queue_t*) malloc( sizeof(dma_queue_t));
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dma_link->block_size = data_len;
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dma_link->data_length = data_len;
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dma_link->buf_ptr = (uint32_t)buf;
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dma_link->eof = 1;
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dma_link->next_link_ptr = (uint32_t)NULL;
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dma_link->owner = 1;//0: cpu 1: dma
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dma_link->sub_sof = 0;
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dma_link->unused = 0;
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SET_PERI_REG_BITS(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_ADDR, ((uint32_t )dma_link),
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SPI_OUTLINK_ADDR_S);
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SET_PERI_REG_MASK(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_START);
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// 1. Waiting DMA controller fill TX FIFO
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while ((READ_PERI_REG(SPI_DMA_RSTATUS_REG(spi_num))&0x80000000));
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psram_dma_cmd_write_config(addr, data_len, 0);
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psram_cmd_start(spi_num, PSRAM_CMD_QPI);
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free(dma_link);
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return 0;
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}
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int psram_dma_rx(int dma_channel, uint32_t addr, uint32_t* buf, size_t data_len)
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{
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int spi_num = 1;
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// Reset DMA
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SET_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
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CLEAR_PERI_REG_MASK(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_START);
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CLEAR_PERI_REG_MASK(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_START);
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CLEAR_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST);
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// Select DMA channel.
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SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, DPORT_SPI3_DMA_CHAN_SEL_V, dma_channel, ((spi_num - 1) * 2));
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SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);//////add
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// enable send intr
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SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_SEND_DONE);
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SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_RECV_DONE);
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// Clear all of interrupt source
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//spi_int_clear(obj->spi_num);
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CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_INT_SRC_TRANS_DONE
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| SPI_INT_SRC_WR_STA_DONE
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| SPI_INT_SRC_RD_STA_DONE
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| SPI_INT_SRC_WR_BUF_DONE
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| SPI_INT_SRC_RD_BUF_DONE);
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dma_queue_t* rx_dma_link = (dma_queue_t*) malloc( sizeof(dma_queue_t));
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rx_dma_link->block_size = data_len;
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rx_dma_link->data_length = data_len;
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rx_dma_link->buf_ptr = (uint32_t)buf;
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rx_dma_link->eof = 1;
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rx_dma_link->next_link_ptr = (uint32_t)NULL;
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rx_dma_link->owner = 1;//0: cpu 1: dma
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rx_dma_link->sub_sof = 0;
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rx_dma_link->unused = 0;
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SET_PERI_REG_BITS(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_ADDR, ((uint32_t )rx_dma_link),
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SPI_INLINK_ADDR_S);
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SET_PERI_REG_MASK(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_START);
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psram_dma_qio_read_config( spi_num, addr, data_len);
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psram_cmd_start(spi_num, PSRAM_CMD_QPI);
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//add semaphore to wait trans done, instead of while loop.
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free(rx_dma_link);
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return 0;
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}
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//---------------------------
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//-- below is test code --
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//---------------------------
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#if 1
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void psram_write_once(uint32_t loop_num,uint32_t write_addr,uint32_t mode,uint32_t repeat)
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{
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// psram_enable(PSRAM_CACHE_F80M_S40M);
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// psram_enable_qio_mode(PSRAM_SPI_1);
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uint32_t data_w[8];
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int i;
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for(i=0;i<8;i++) {
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data_w[i]= ((i+1)<<24)|((i+1)<<16)|((i+1)<<8)|(i+1);
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}
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ets_printf("WRITE DATA IN QMODE\n");
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for(i = 0;i<loop_num;i++){
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psram_write_data(write_addr+32*i,data_w,32);
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}
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vTaskDelay(500);
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}
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void psram_rw_loop_test(uint32_t loop_num,uint32_t write_addr,uint32_t mode,uint32_t repeat)
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{
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// psram_enable(PSRAM_CACHE_F80M_S40M);
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// psram_enable_qio_mode(PSRAM_SPI_1);
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uint32_t data_w[8];
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int i;
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int test_num = 0;
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do{
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ets_printf("-----test num: %d------\n",test_num++);
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ets_printf("---write----0x%08x\n",(test_num%2 == 0? 0x55555555:0xaaaaaaaa));
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for(i=0;i<8;i++) {
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data_w[i] = (test_num%2 == 0? 0x55555555:0xaaaaaaaa);
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}
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for(i = 0;i<loop_num;i++){
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psram_write_data(write_addr+32*i,data_w,32);
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}
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ets_printf("----read----\n");
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int fail_flg = 0;
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uint32_t data_r[8]={0};
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for(i = 0;i<loop_num;i++){
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if((i%1000 == 0)){
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ets_printf("addr [%d]: 0x%08x\n",i,write_addr+32*i);
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}
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memset(data_r,0,sizeof(data_r));
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psram_clear_spi_fifo(PSRAM_SPI_1);
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int dummy_num = 0;
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psram_read_data_quad(PSRAM_SPI_1,data_r,write_addr+32*i,32);
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int k = 0;
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int ii = 0;
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for(k=0;k<8;k++){
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if(data_r[k] != (test_num%2 == 0? 0x55555555:0xaaaaaaaa)){
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ets_printf("ERROR!!! @%d [0x%08x]\n",k,write_addr+32*i);
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ets_printf("data_r[%d] : 0x%08x\n",k,data_r[k]);
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ets_printf("set val: 0x%08x\n",(test_num%2 == 0? 0x55555555:0xaaaaaaaa));
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uint32_t vtmp = 0x9999;
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psram_read_data(PSRAM_SPI_1,&vtmp,write_addr+32*i+k*4,4);
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ets_printf("spi1 read again11 addr[0x%08x]: 0x%08x\n",write_addr+32*i+k*4,vtmp);
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vtmp = 0x9999;
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psram_read_data(PSRAM_SPI_1,&vtmp,write_addr+32*i+k*4,4);
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ets_printf("spi1 read again22 addr[0x%08x]: 0x%08x\n",write_addr+32*i+k*4,vtmp);
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for(ii = 0;ii<8;ii++){
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//ets_printf("data[%d]: 0x%08x\n",ii,data_r[ii]);
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}
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fail_flg = 1;
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}
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}
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}
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if(fail_flg == 0){
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ets_printf("TEST PASS!!!\n");
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continue;
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}
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psram_clear_spi_fifo(PSRAM_SPI_1);
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break;
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}while(repeat == 0 ? 0 :1 );
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ets_printf("TEST FAILED...\n");
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}
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void psram_read_test(uint32_t loop_num,uint32_t write_addr,uint32_t mode,uint32_t repeat)
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{
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int i;
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int test_num = 0;
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do{
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ets_printf("-----test num: %d------\n",test_num++);
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int fail_flg = 0;
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uint32_t data_r[8]={0};
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for(i = 0;i<loop_num;i++){
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if((i%100 == 0)){
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ets_printf("addr [%d]: 0x%08x\n",i,write_addr+32*i);
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}
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memset(data_r,0,sizeof(data_r));
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psram_clear_spi_fifo(PSRAM_SPI_1);
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int dummy_num = 0;
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psram_read_data(PSRAM_SPI_1,data_r,write_addr+32*i,32);
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int k = 0;
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int ii = 0;
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for(k=0;k<8;k++){
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if(data_r[k] != (((k+1)<<24)|((k+1)<<16)|((k+1)<<8)|(k+1))){
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ets_printf("ERROR!!! @%d\n",k);
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ets_printf("data_r[%d] : 0x%08x\n",k,data_r[k]);
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ets_printf("set val: 0x%08x\n",(((k+1)<<24)|((k+1)<<16)|((k+1)<<8)|(k+1)));
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for(ii = 0;ii<16;ii++){
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ets_printf("data[%d]: 0x%08x\n",ii,data_r[ii]);
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}
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fail_flg = 1;
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//return;
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}
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}
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}
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if(fail_flg == 0){
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ets_printf("TEST PASS!!!\n");
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continue;
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}
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psram_clear_spi_fifo(PSRAM_SPI_1);
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break;
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}while(repeat == 0 ? 0 :1 );
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}
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void psram_rw_test(uint32_t loop_num,uint32_t write_addr,uint32_t mode,uint32_t repeat)
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{
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// psram_enable_qio_mode(PSRAM_SPI_1);
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while(repeat--)
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{
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uint32_t data_w[16];
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int i;
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for(i = 0; i < 16; i++) {
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data_w[i] = ((i + 1) << 24) | ((i + 1) << 16) | ((i + 1) << 8) | (i + 1);
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}
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ets_printf("WRITE DATA IN QMODE\n");
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for(i = 0; i < loop_num; i++) {
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psram_write_data(write_addr + 32 * i, data_w, 32);
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}
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// vTaskDelay(500);
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int fail_flg = 0;
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uint32_t data_r[16] = {0};
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memset(data_r, 0, sizeof(data_r));
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for(i = 0; i < loop_num; i++) {
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if((i % 10 == 0)) {
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ets_printf("addr i: %d\n", i);
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}
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memset(data_r, 0, sizeof(data_r));
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psram_clear_spi_fifo(PSRAM_SPI_1);
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int dummy_num = 0;
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psram_read_data_quad(PSRAM_SPI_1, data_r, write_addr + 32 * i, 32);
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int k = 0;
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int ii = 0;
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for(k = 0; k < 8; k++) {
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if(data_r[k] != (((k + 1) << 24) | ((k + 1) << 16) | ((k + 1) << 8) | (k + 1))) {
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ets_printf("ERROR!!! @%d\n", k);
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ets_printf("data_r[%d] : 0x%08x\n", k, data_r[k]);
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ets_printf("set val: 0x%08x\n", (((k + 1) << 24) | ((k + 1) << 16) | ((k + 1) << 8) | (k + 1)));
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for(ii = 0; ii < 16; ii++) {
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ets_printf("data[%d]: 0x%08x\n", ii, data_r[ii]);
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}
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fail_flg = 1;
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return;
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}
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}
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}
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if(fail_flg == 0) {
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ets_printf("TEST PASS!!!\n");
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}
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ets_printf("END OF TEST.\n");
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psram_clear_spi_fifo(PSRAM_SPI_1);
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}
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}
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#endif
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