From 15012589a5e046d7f95186bd465b88c3821c3f59 Mon Sep 17 00:00:00 2001 From: Jeroen Domburg Date: Mon, 20 Feb 2017 11:56:12 +0800 Subject: [PATCH] Psram driver cleanup: remove DMA and test functions, tabs to spaces, add copyright header --- components/esp32/psram.c | 978 ++++++++++++++------------------------- 1 file changed, 335 insertions(+), 643 deletions(-) mode change 100755 => 100644 components/esp32/psram.c diff --git a/components/esp32/psram.c b/components/esp32/psram.c old mode 100755 new mode 100644 index 7c891def8..7d5458380 --- a/components/esp32/psram.c +++ b/components/esp32/psram.c @@ -1,7 +1,20 @@ +// Copyright 2013-2016 Espressif Systems (Shanghai) PTE LTD +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + #include "esp_types.h" #include "rom/ets_sys.h" #include "psram.h" -//#include "spi.h" #include "soc/io_mux_reg.h" #include "soc/dport_reg.h" #include "rom/gpio.h" @@ -42,20 +55,11 @@ typedef struct { static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode); - static void psram_clear_spi_fifo(psram_spi_num_t spiNum) -{ - int i; - for(i=0;i<16;i++){ - WRITE_PERI_REG(SPI_W0_REG(spiNum)+i*4,0); - } -} - -static void disp_fifo(psram_spi_num_t spiNum) { int i; for(i=0;i<16;i++){ - ets_printf(" FIFO[%d]: 0x%08x\n",i, READ_PERI_REG(SPI_W0_REG(spiNum)+i*4)); + WRITE_PERI_REG(SPI_W0_REG(spiNum)+i*4,0); } } @@ -171,11 +175,11 @@ static void IRAM_ATTR psram_recv_start(psram_spi_num_t spiNum,uint32_t* pRxData, SET_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1),SPI_CS1_DIS_M); CLEAR_PERI_REG_MASK(SPI_PIN_REG(PSRAM_SPI_1),SPI_CS0_DIS_M); - int idx = 0; - // Read data out - do { - *pRxData++ = READ_PERI_REG(SPI_W0_REG(spiNum) + (idx << 2)); - } while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0))); + int idx = 0; + // Read data out + do { + *pRxData++ = READ_PERI_REG(SPI_W0_REG(spiNum) + (idx << 2)); + } while (++idx < ((rxByteLen / 4) + ((rxByteLen % 4) ? 1 : 0))); } //setup spi command/addr/data/dummy in user mode @@ -193,8 +197,8 @@ static int psram_cmd_config(psram_spi_num_t spiNum, psram_cmd_t* pInData) // Load command,bit15-0 is cmd value. SET_PERI_REG_BITS(SPI_USER2_REG(spiNum), SPI_USR_COMMAND_VALUE, pInData->cmd, SPI_USR_COMMAND_VALUE_S); } else { - CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_COMMAND); - SET_PERI_REG_BITS(SPI_USER2_REG(spiNum), SPI_USR_COMMAND_BITLEN,0, SPI_USR_COMMAND_BITLEN_S); + CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_COMMAND); + SET_PERI_REG_BITS(SPI_USER2_REG(spiNum), SPI_USR_COMMAND_BITLEN,0, SPI_USR_COMMAND_BITLEN_S); } // Set Address by user. if (pInData->addrBitLen != 0) { @@ -212,37 +216,37 @@ static int psram_cmd_config(psram_spi_num_t spiNum, psram_cmd_t* pInData) // Set data by user. uint32_t* pTxVal = pInData->txData; if (pInData->txDataBitLen != 0 ) { - // Enable MOSI - SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MOSI); - // Load send buffer + // Enable MOSI + SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MOSI); + // Load send buffer int len = ((pInData->txDataBitLen / 32) + ((pInData->txDataBitLen % 32) ? 1 : 0)); if(pTxVal != NULL) { do { WRITE_PERI_REG((SPI_W0_REG(spiNum) + (idx << 2)), *pTxVal++); } while(++idx < len); } - // Set data send buffer length.Max data length 64 bytes. - SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spiNum), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1), SPI_USR_MOSI_DBITLEN_S); + // Set data send buffer length.Max data length 64 bytes. + SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spiNum), SPI_USR_MOSI_DBITLEN, (pInData->txDataBitLen - 1), SPI_USR_MOSI_DBITLEN_S); } else { - CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MOSI); - SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spiNum), SPI_USR_MOSI_DBITLEN,0, SPI_USR_MOSI_DBITLEN_S); + CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MOSI); + SET_PERI_REG_BITS(SPI_MOSI_DLEN_REG(spiNum), SPI_USR_MOSI_DBITLEN,0, SPI_USR_MOSI_DBITLEN_S); } // Set rx data by user. if (pInData->rxDataBitLen != 0 ) { // Enable MOSI - SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MISO); - // Set data send buffer length.Max data length 64 bytes. - SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spiNum), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen -1 ), SPI_USR_MISO_DBITLEN_S); + SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MISO); + // Set data send buffer length.Max data length 64 bytes. + SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spiNum), SPI_USR_MISO_DBITLEN, (pInData->rxDataBitLen -1 ), SPI_USR_MISO_DBITLEN_S); } else { - CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MISO); - SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spiNum), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S); + CLEAR_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_USR_MISO); + SET_PERI_REG_BITS(SPI_MISO_DLEN_REG(spiNum), SPI_USR_MISO_DBITLEN, 0, SPI_USR_MISO_DBITLEN_S); } if(pInData->dummyBitLen != 0){ - SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_USR_DUMMY); // dummy en - SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1),SPI_USR_DUMMY_CYCLELEN_V,pInData->dummyBitLen-1,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY + SET_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_USR_DUMMY); // dummy en + SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1),SPI_USR_DUMMY_CYCLELEN_V,pInData->dummyBitLen-1,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY }else{ - CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_USR_DUMMY); // dummy en - SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1),SPI_USR_DUMMY_CYCLELEN_V,0,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY + CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_USR_DUMMY); // dummy en + SET_PERI_REG_BITS(SPI_USER1_REG(PSRAM_SPI_1),SPI_USR_DUMMY_CYCLELEN_V,0,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY } return 0; } @@ -250,94 +254,94 @@ static int psram_cmd_config(psram_spi_num_t spiNum, psram_cmd_t* pInData) //read psram data in fast read mode static void psram_read_data(psram_spi_num_t spiNum,uint32_t* dst,uint32_t src,uint32_t len) { - uint32_t addr = 0; - uint32_t dummy_bits = 0; - psram_cmd_t pDat; - addr = (PSRAM_FAST_READ <<24) | src; - switch(g_PsramMode){ - case PSRAM_CACHE_F80M_S80M: - dummy_bits = 4+extra_dummy; - pDat.cmdBitLen = 0; - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - dummy_bits = 4+extra_dummy; - pDat.cmdBitLen = 2; - break; - } - pDat.cmd = 0; - pDat.addr = &addr; - pDat.addrBitLen = 4*8; - pDat.txDataBitLen = 0; - pDat.txData = NULL; - pDat.rxDataBitLen = len*8 ; - pDat.rxData = dst; - pDat.dummyBitLen = dummy_bits; - psram_cmd_config(spiNum,&pDat); - psram_clear_spi_fifo(spiNum); - psram_recv_start(spiNum,pDat.rxData,pDat.rxDataBitLen/8, PSRAM_CMD_QPI); + uint32_t addr = 0; + uint32_t dummy_bits = 0; + psram_cmd_t pDat; + addr = (PSRAM_FAST_READ <<24) | src; + switch(g_PsramMode){ + case PSRAM_CACHE_F80M_S80M: + dummy_bits = 4+extra_dummy; + pDat.cmdBitLen = 0; + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + dummy_bits = 4+extra_dummy; + pDat.cmdBitLen = 2; + break; + } + pDat.cmd = 0; + pDat.addr = &addr; + pDat.addrBitLen = 4*8; + pDat.txDataBitLen = 0; + pDat.txData = NULL; + pDat.rxDataBitLen = len*8 ; + pDat.rxData = dst; + pDat.dummyBitLen = dummy_bits; + psram_cmd_config(spiNum,&pDat); + psram_clear_spi_fifo(spiNum); + psram_recv_start(spiNum,pDat.rxData,pDat.rxDataBitLen/8, PSRAM_CMD_QPI); } //read psram data in fast read quad mode static void psram_read_data_quad(psram_spi_num_t spiNum,uint32_t* dst,uint32_t src,uint32_t len) { - uint32_t addr = (PSRAM_FAST_READ_QUAD <<24) | src; - uint32_t dummy_bits = 0; - psram_cmd_t pDat; - switch(g_PsramMode){ - case PSRAM_CACHE_F80M_S80M: - dummy_bits = 6+extra_dummy; - pDat.cmdBitLen = 0; - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - dummy_bits = 6+extra_dummy; - pDat.cmdBitLen = 2; - break; - } - pDat.cmd = 0; - pDat.addr = &addr; - pDat.addrBitLen = 4*8; - pDat.txDataBitLen = 0; - pDat.txData = NULL; - pDat.rxDataBitLen = len*8 ; - pDat.rxData = dst; - pDat.dummyBitLen = dummy_bits; - psram_cmd_config(spiNum,&pDat); - psram_clear_spi_fifo(spiNum); - psram_recv_start(spiNum,pDat.rxData,pDat.rxDataBitLen/8, PSRAM_CMD_QPI); + uint32_t addr = (PSRAM_FAST_READ_QUAD <<24) | src; + uint32_t dummy_bits = 0; + psram_cmd_t pDat; + switch(g_PsramMode){ + case PSRAM_CACHE_F80M_S80M: + dummy_bits = 6+extra_dummy; + pDat.cmdBitLen = 0; + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + dummy_bits = 6+extra_dummy; + pDat.cmdBitLen = 2; + break; + } + pDat.cmd = 0; + pDat.addr = &addr; + pDat.addrBitLen = 4*8; + pDat.txDataBitLen = 0; + pDat.txData = NULL; + pDat.rxDataBitLen = len*8 ; + pDat.rxData = dst; + pDat.dummyBitLen = dummy_bits; + psram_cmd_config(spiNum,&pDat); + psram_clear_spi_fifo(spiNum); + psram_recv_start(spiNum,pDat.rxData,pDat.rxDataBitLen/8, PSRAM_CMD_QPI); } //write data to psram static void psram_write_data(uint32_t dst,uint32_t* src,uint32_t len) { - uint32_t addr = (PSRAM_QUAD_WRITE <<24) | dst; - psram_cmd_t pDat; - int dummy_bits = 0; - switch(g_PsramMode){ - case PSRAM_CACHE_F80M_S80M: - dummy_bits = 0 + 0; - pDat.cmdBitLen = 0; - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - dummy_bits = 0 + 0; - pDat.cmdBitLen = 2; - break; - } - pDat.cmd = 0; - pDat.addr = &addr; - pDat.addrBitLen = 32; - pDat.txData = src; - pDat.txDataBitLen = len*8; - pDat.rxData = NULL; - pDat.rxDataBitLen = 0; - pDat.dummyBitLen = dummy_bits; - psram_cmd_config(PSRAM_SPI_1, &pDat); - psram_cmd_start(PSRAM_SPI_1, PSRAM_CMD_QPI); + uint32_t addr = (PSRAM_QUAD_WRITE <<24) | dst; + psram_cmd_t pDat; + int dummy_bits = 0; + switch(g_PsramMode){ + case PSRAM_CACHE_F80M_S80M: + dummy_bits = 0 + 0; + pDat.cmdBitLen = 0; + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + dummy_bits = 0 + 0; + pDat.cmdBitLen = 2; + break; + } + pDat.cmd = 0; + pDat.addr = &addr; + pDat.addrBitLen = 32; + pDat.txData = src; + pDat.txDataBitLen = len*8; + pDat.rxData = NULL; + pDat.rxDataBitLen = 0; + pDat.dummyBitLen = dummy_bits; + psram_cmd_config(PSRAM_SPI_1, &pDat); + psram_cmd_start(PSRAM_SPI_1, PSRAM_CMD_QPI); } static void psram_dma_cmd_write_config(uint32_t dst, uint32_t len, uint32_t dummy_bits) @@ -397,35 +401,35 @@ static void psram_dma_qio_read_config(psram_spi_num_t spiNum, uint32_t src, uint //read psram id static void psram_read_id(uint32_t* dev_id) { - psram_spi_num_t spiNum = PSRAM_SPI_1; -// psram_set_basic_write_mode(spiNum); -// psram_set_basic_read_mode(spiNum); - uint32_t addr = (PSRAM_DEVICE_ID <<24) | 0; - uint32_t dummy_bits = 0; - psram_cmd_t pDat; - switch(g_PsramMode){ - case PSRAM_CACHE_F80M_S80M: - dummy_bits = 0+extra_dummy; - pDat.cmdBitLen = 0; - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - dummy_bits = 0+extra_dummy; - pDat.cmdBitLen = 2; //this two bits is used for delay one byte in qio mode - break; - } - pDat.cmd = 0; - pDat.addr = &addr; - pDat.addrBitLen = 4*8; - pDat.txDataBitLen = 0; - pDat.txData = NULL; - pDat.rxDataBitLen = 4*8 ; - pDat.rxData = dev_id; - pDat.dummyBitLen = dummy_bits; - psram_cmd_config(spiNum,&pDat); - psram_clear_spi_fifo(spiNum); - psram_recv_start(spiNum,pDat.rxData,pDat.rxDataBitLen/8, PSRAM_CMD_SPI); + psram_spi_num_t spiNum = PSRAM_SPI_1; +// psram_set_basic_write_mode(spiNum); +// psram_set_basic_read_mode(spiNum); + uint32_t addr = (PSRAM_DEVICE_ID <<24) | 0; + uint32_t dummy_bits = 0; + psram_cmd_t pDat; + switch(g_PsramMode){ + case PSRAM_CACHE_F80M_S80M: + dummy_bits = 0+extra_dummy; + pDat.cmdBitLen = 0; + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + dummy_bits = 0+extra_dummy; + pDat.cmdBitLen = 2; //this two bits is used for delay one byte in qio mode + break; + } + pDat.cmd = 0; + pDat.addr = &addr; + pDat.addrBitLen = 4*8; + pDat.txDataBitLen = 0; + pDat.txData = NULL; + pDat.rxDataBitLen = 4*8 ; + pDat.rxData = dev_id; + pDat.dummyBitLen = dummy_bits; + psram_cmd_config(spiNum,&pDat); + psram_clear_spi_fifo(spiNum); + psram_recv_start(spiNum,pDat.rxData,pDat.rxDataBitLen/8, PSRAM_CMD_SPI); } //switch psram burst length(32 bytes or 1024 bytes) @@ -433,101 +437,101 @@ static void psram_read_id(uint32_t* dev_id) //but they sent us a correction doc and told us it is 32 bytes for these samples static void psram_set_burst_length(psram_spi_num_t spiNum) { - psram_cmd_t pDat; - switch(g_PsramMode){ - case PSRAM_CACHE_F80M_S80M: - pDat.cmd = 0xC0; - pDat.cmdBitLen = 8; - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - pDat.cmd = 0x0030; - pDat.cmdBitLen = 10; - break; - } - pDat.addr = 0; - pDat.addrBitLen = 0; - pDat.txData = NULL; - pDat.txDataBitLen = 0; - pDat.rxData = NULL; - pDat.rxDataBitLen = 0; - pDat.dummyBitLen = 0; - psram_cmd_config(spiNum, &pDat); - psram_cmd_start(spiNum, PSRAM_CMD_QPI); + psram_cmd_t pDat; + switch(g_PsramMode){ + case PSRAM_CACHE_F80M_S80M: + pDat.cmd = 0xC0; + pDat.cmdBitLen = 8; + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + pDat.cmd = 0x0030; + pDat.cmdBitLen = 10; + break; + } + pDat.addr = 0; + pDat.addrBitLen = 0; + pDat.txData = NULL; + pDat.txDataBitLen = 0; + pDat.rxData = NULL; + pDat.rxDataBitLen = 0; + pDat.dummyBitLen = 0; + psram_cmd_config(spiNum, &pDat); + psram_cmd_start(spiNum, PSRAM_CMD_QPI); } //send reset command to psram(right now,we only send this command in QPI mode) //seems not working static void psram_reset_mode(psram_spi_num_t spiNum) { - psram_cmd_t pDat; - uint32_t cmd_rst = 0x99066; - pDat.txData = &cmd_rst; - pDat.txDataBitLen = 20; - pDat.addr = NULL; - pDat.addrBitLen = 0; - pDat.cmd = 0; - pDat.cmdBitLen = 0; - pDat.rxData = NULL; - pDat.rxDataBitLen = 0; - pDat.dummyBitLen = 0; - psram_cmd_config(spiNum, &pDat); - psram_cmd_start(spiNum, PSRAM_CMD_QPI); + psram_cmd_t pDat; + uint32_t cmd_rst = 0x99066; + pDat.txData = &cmd_rst; + pDat.txDataBitLen = 20; + pDat.addr = NULL; + pDat.addrBitLen = 0; + pDat.cmd = 0; + pDat.cmdBitLen = 0; + pDat.rxData = NULL; + pDat.rxDataBitLen = 0; + pDat.dummyBitLen = 0; + psram_cmd_config(spiNum, &pDat); + psram_cmd_start(spiNum, PSRAM_CMD_QPI); } //exit QPI mode(set back to SPI mode) static void psram_disable_qio_mode(psram_spi_num_t spiNum) { - psram_cmd_t pDat; - uint32_t cmd_exit_qpi; - switch(g_PsramMode){ - case PSRAM_CACHE_F80M_S80M: - cmd_exit_qpi = PSRAM_EXIT_QMODE; - pDat.txDataBitLen = 8; - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - cmd_exit_qpi = PSRAM_EXIT_QMODE<<8; - pDat.txDataBitLen = 16; - break; - } - pDat.txData = &cmd_exit_qpi; - pDat.cmd = 0; - pDat.cmdBitLen = 0; - pDat.addr = 0; - pDat.addrBitLen = 0; - pDat.rxData = NULL; - pDat.rxDataBitLen = 0; - pDat.dummyBitLen = 0; - psram_cmd_config(spiNum, &pDat); - psram_cmd_start(spiNum, PSRAM_CMD_QPI); + psram_cmd_t pDat; + uint32_t cmd_exit_qpi; + switch(g_PsramMode){ + case PSRAM_CACHE_F80M_S80M: + cmd_exit_qpi = PSRAM_EXIT_QMODE; + pDat.txDataBitLen = 8; + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + cmd_exit_qpi = PSRAM_EXIT_QMODE<<8; + pDat.txDataBitLen = 16; + break; + } + pDat.txData = &cmd_exit_qpi; + pDat.cmd = 0; + pDat.cmdBitLen = 0; + pDat.addr = 0; + pDat.addrBitLen = 0; + pDat.rxData = NULL; + pDat.rxDataBitLen = 0; + pDat.dummyBitLen = 0; + psram_cmd_config(spiNum, &pDat); + psram_cmd_start(spiNum, PSRAM_CMD_QPI); } //enter QPI mode static void IRAM_ATTR psram_enable_qio_mode(psram_spi_num_t spiNum) { - psram_cmd_t pDat; - switch(g_PsramMode){ - case PSRAM_CACHE_F80M_S80M: - pDat.cmd = PSRAM_ENTER_QMODE; - pDat.cmdBitLen = 8; - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - pDat.cmd = 0x400d; - pDat.cmdBitLen = 10; - break; - } - pDat.addr = 0; - pDat.addrBitLen = 0; - pDat.txData = NULL; - pDat.txDataBitLen = 0; - pDat.rxData = NULL; - pDat.rxDataBitLen = 0; - pDat.dummyBitLen = 0; - psram_cmd_config(spiNum, &pDat); - psram_cmd_start(spiNum, PSRAM_CMD_SPI); + psram_cmd_t pDat; + switch(g_PsramMode){ + case PSRAM_CACHE_F80M_S80M: + pDat.cmd = PSRAM_ENTER_QMODE; + pDat.cmdBitLen = 8; + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + pDat.cmd = 0x400d; + pDat.cmdBitLen = 10; + break; + } + pDat.addr = 0; + pDat.addrBitLen = 0; + pDat.txData = NULL; + pDat.txDataBitLen = 0; + pDat.rxData = NULL; + pDat.rxDataBitLen = 0; + pDat.dummyBitLen = 0; + psram_cmd_config(spiNum, &pDat); + psram_cmd_start(spiNum, PSRAM_CMD_SPI); } @@ -536,38 +540,38 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) gpio_matrix_out(6, SPICLK_OUT_IDX, 0, 0); gpio_matrix_out(11, SPICS0_OUT_IDX, 0, 0); - gpio_matrix_out(7, SPIQ_OUT_IDX, 0, 0); - gpio_matrix_in(7,SPIQ_IN_IDX, 0); - gpio_matrix_out(8, SPID_OUT_IDX, 0, 0); - gpio_matrix_in(8, SPID_IN_IDX, 0); - gpio_matrix_out(10, SPIWP_OUT_IDX, 0, 0); - gpio_matrix_in(10, SPIWP_IN_IDX, 0); - gpio_matrix_out(9, SPIHD_OUT_IDX, 0, 0); - gpio_matrix_in(9, SPIHD_IN_IDX, 0); + gpio_matrix_out(7, SPIQ_OUT_IDX, 0, 0); + gpio_matrix_in(7,SPIQ_IN_IDX, 0); + gpio_matrix_out(8, SPID_OUT_IDX, 0, 0); + gpio_matrix_in(8, SPID_IN_IDX, 0); + gpio_matrix_out(10, SPIWP_OUT_IDX, 0, 0); + gpio_matrix_in(10, SPIWP_IN_IDX, 0); + gpio_matrix_out(9, SPIHD_OUT_IDX, 0, 0); + gpio_matrix_in(9, SPIHD_IN_IDX, 0); - switch(mode){ - case PSRAM_CACHE_F80M_S80M: - case PSRAM_CACHE_F80M_S40M: - SET_PERI_REG_MASK(SPI_USER_REG(0),SPI_USR_DUMMY); // dummy en - SET_PERI_REG_BITS(SPI_USER1_REG(0),SPI_USR_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY - break; - case PSRAM_CACHE_F40M_S40M: - default: - SET_PERI_REG_MASK(SPI_USER_REG(0),SPI_USR_DUMMY); // dummy en - SET_PERI_REG_BITS(SPI_USER1_REG(0),SPI_USR_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY - break; - } - //drive ability - SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3 ,FUN_DRV_S); - SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA0_U,FUN_DRV, 3 ,FUN_DRV_S); - SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA1_U,FUN_DRV, 3 ,FUN_DRV_S); - SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA2_U,FUN_DRV, 3 ,FUN_DRV_S); - SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA3_U,FUN_DRV, 3 ,FUN_DRV_S); - SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3 ,FUN_DRV_S); - //select pin function gpio - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U,2); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U,2); - PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U,2); + switch(mode){ + case PSRAM_CACHE_F80M_S80M: + case PSRAM_CACHE_F80M_S40M: + SET_PERI_REG_MASK(SPI_USER_REG(0),SPI_USR_DUMMY); // dummy en + SET_PERI_REG_BITS(SPI_USER1_REG(0),SPI_USR_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY + break; + case PSRAM_CACHE_F40M_S40M: + default: + SET_PERI_REG_MASK(SPI_USER_REG(0),SPI_USR_DUMMY); // dummy en + SET_PERI_REG_BITS(SPI_USER1_REG(0),SPI_USR_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_USR_DUMMY_CYCLELEN_S); //DUMMY + break; + } + //drive ability + SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_CLK_U, FUN_DRV, 3 ,FUN_DRV_S); + SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA0_U,FUN_DRV, 3 ,FUN_DRV_S); + SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA1_U,FUN_DRV, 3 ,FUN_DRV_S); + SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA2_U,FUN_DRV, 3 ,FUN_DRV_S); + SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_DATA3_U,FUN_DRV, 3 ,FUN_DRV_S); + SET_PERI_REG_BITS( PERIPHS_IO_MUX_SD_CMD_U, FUN_DRV, 3 ,FUN_DRV_S); + //select pin function gpio + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA0_U,2); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA1_U,2); + PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA2_U,2); PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_DATA3_U,2); PIN_FUNC_SELECT(PERIPHS_IO_MUX_SD_CLK_U,2); @@ -578,7 +582,7 @@ static void IRAM_ATTR psram_gpio_config(psram_cache_mode_t mode) //spi param init for psram void IRAM_ATTR psram_spi_init(psram_spi_num_t spiNum,psram_cache_mode_t mode) { - uint8_t i, k; + uint8_t i, k; CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spiNum), SPI_TRANS_DONE << 5); SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_CS_SETUP); // SPI_CPOL & SPI_CPHA @@ -594,21 +598,21 @@ void IRAM_ATTR psram_spi_init(psram_spi_num_t spiNum,psram_cache_mode_t mode) // SPI mode type CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spiNum), SPI_SLAVE_MODE); switch(mode){ - case PSRAM_CACHE_F80M_S80M: - WRITE_PERI_REG(SPI_CLOCK_REG(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: - i = (2 / 40) ? (2 / 40) : 1; - k = 2 / i; - CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(spiNum), SPI_CLK_EQU_SYSCLK); - WRITE_PERI_REG(SPI_CLOCK_REG(spiNum), - (((i - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) | - (((k - 1) & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) | - ((((k + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) | - (((k - 1) & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div - break; + case PSRAM_CACHE_F80M_S80M: + WRITE_PERI_REG(SPI_CLOCK_REG(spiNum), SPI_CLK_EQU_SYSCLK); // 80Mhz speed + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: + i = (2 / 40) ? (2 / 40) : 1; + k = 2 / i; + CLEAR_PERI_REG_MASK(SPI_CLOCK_REG(spiNum), SPI_CLK_EQU_SYSCLK); + WRITE_PERI_REG(SPI_CLOCK_REG(spiNum), + (((i - 1) & SPI_CLKDIV_PRE) << SPI_CLKDIV_PRE_S) | + (((k - 1) & SPI_CLKCNT_N) << SPI_CLKCNT_N_S) | + ((((k + 1) / 2 - 1) & SPI_CLKCNT_H) << SPI_CLKCNT_H_S) | + (((k - 1) & SPI_CLKCNT_L) << SPI_CLKCNT_L_S)); //clear bit 31,set SPI clock div + break; } // Enable MOSI SET_PERI_REG_MASK(SPI_USER_REG(spiNum), SPI_CS_SETUP | SPI_CS_HOLD | SPI_USR_MOSI); @@ -623,72 +627,60 @@ esp_err_t IRAM_ATTR psram_enable(psram_cache_mode_t mode) //psram init { WRITE_PERI_REG(GPIO_ENABLE_W1TC_REG,BIT16|BIT17);//DISALBE OUPUT FOR IO16/17 - g_PsramMode = mode; + g_PsramMode = mode; - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT16);//DPORT_SPI_CLK_EN - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT16);//DPORT_SPI_RST - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT1);//DPORT_SPI_CLK_EN_1 - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT1);//DPORT_SPI_RST_1 - SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT6);//DPORT_SPI_CLK_EN_2 - CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT6);//DPORT_SPI_RST_2 + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT16);//DPORT_SPI_CLK_EN + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT16);//DPORT_SPI_RST + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT1);//DPORT_SPI_CLK_EN_1 + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT1);//DPORT_SPI_RST_1 + SET_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT6);//DPORT_SPI_CLK_EN_2 + CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,BIT6);//DPORT_SPI_RST_2 WRITE_PERI_REG( SPI_EXT3_REG(0), 0x1); CLEAR_PERI_REG_MASK( SPI_USER_REG(PSRAM_SPI_1), SPI_USR_PREP_HOLD_M); switch(mode){ - case PSRAM_CACHE_F80M_S80M: - psram_spi_init(PSRAM_SPI_1, mode); - extra_dummy = 2; - CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD); - gpio_matrix_out(16, SPICS1_OUT_IDX, 0, 0); - gpio_matrix_out(17, VSPICLK_OUT_IDX, 0, 0); - //use spi3 clock,but use spi1 data/cs wires - WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_3), 32<<24); - WRITE_PERI_REG(SPI_CLOCK_REG(PSRAM_SPI_3),SPI_CLK_EQU_SYSCLK_M);//SET 80M AND CLEAR OTHERS - SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_3),SPI_FLASH_READ_M); - uint32_t spi_status; - while(1){ - spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_3)); - if(spi_status != 0 && spi_status != 1){ - CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT16);//DPORT_SPI_CLK_EN - break; - } - } - break; - case PSRAM_CACHE_F80M_S40M: - case PSRAM_CACHE_F40M_S40M: - default: + case PSRAM_CACHE_F80M_S80M: + psram_spi_init(PSRAM_SPI_1, mode); + extra_dummy = 2; + CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD); + gpio_matrix_out(16, SPICS1_OUT_IDX, 0, 0); + gpio_matrix_out(17, VSPICLK_OUT_IDX, 0, 0); + //use spi3 clock,but use spi1 data/cs wires + WRITE_PERI_REG(SPI_ADDR_REG(PSRAM_SPI_3), 32<<24); + WRITE_PERI_REG(SPI_CLOCK_REG(PSRAM_SPI_3),SPI_CLK_EQU_SYSCLK_M);//SET 80M AND CLEAR OTHERS + SET_PERI_REG_MASK(SPI_CMD_REG(PSRAM_SPI_3),SPI_FLASH_READ_M); + uint32_t spi_status; + while(1){ + spi_status = READ_PERI_REG(SPI_EXT2_REG(PSRAM_SPI_3)); + if(spi_status != 0 && spi_status != 1){ + CLEAR_PERI_REG_MASK(DPORT_PERIP_CLK_EN_REG,BIT16);//DPORT_SPI_CLK_EN + break; + } + } + break; + case PSRAM_CACHE_F80M_S40M: + case PSRAM_CACHE_F40M_S40M: + default: #if GPIO_MATRIX_FOR_40M - extra_dummy = 1; + extra_dummy = 1; #else - extra_dummy = 0; + extra_dummy = 0; #endif - psram_spi_init(PSRAM_SPI_1, mode); - CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD); - gpio_matrix_out(16, SPICS1_OUT_IDX, 0, 0); - gpio_matrix_in(6,SIG_IN_FUNC224_IDX,0); - gpio_matrix_out(20,SIG_IN_FUNC224_IDX,0,0); - gpio_matrix_in(20,SIG_IN_FUNC225_IDX,0); - gpio_matrix_out(17,SIG_IN_FUNC225_IDX,0,0); - break; + psram_spi_init(PSRAM_SPI_1, mode); + CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1), SPI_CS_HOLD); + gpio_matrix_out(16, SPICS1_OUT_IDX, 0, 0); + gpio_matrix_in(6,SIG_IN_FUNC224_IDX,0); + gpio_matrix_out(20,SIG_IN_FUNC224_IDX,0,0); + gpio_matrix_in(20,SIG_IN_FUNC225_IDX,0); + gpio_matrix_out(17,SIG_IN_FUNC225_IDX,0,0); + break; } CLEAR_PERI_REG_MASK(SPI_USER_REG(PSRAM_SPI_1),SPI_CS_SETUP_M); #if GPIO_MATRIX_FOR_40M psram_gpio_config(mode); -// /* @param uint32_t ishspi: 0 for spi, 1 for hspi, flash pad decided by strapping -// * else, bit[5:0] spiclk, bit[11:6] spiq, bit[17:12] spid, bit[23:18] spics0, bit[29:24] spihd -// * -// * @return None -// */ -// uint32_t ishspi = ( (6 & 0x3f) << 0) //clk -// | ( (7 & 0x3f) << 6) //d0 -// | ( (8 & 0x3f) << 12) //d1 -// | ( (11 & 0x3f) << 18) //cs -// | ( (9 & 0x3f) << 24); //d2 -// SelectSpiFunction(ishspi); -// spi_dummy_len_fix(1, 2); #endif @@ -716,29 +708,29 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode) SET_PERI_REG_BITS(SPI_CLOCK_REG(0),SPI_CLKCNT_L,1,SPI_CLKCNT_L_S); switch(psram_cache_mode){ - case PSRAM_CACHE_F80M_S80M: - CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk,80+40; - CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4 - WRITE_PERI_REG(SPI_CLOCK_REG(0),SPI_CLK_EQU_SYSCLK_M);//SET 1DIV CLOCK AND RESET OTHER PARAMS - SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy - SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy - SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command - break; - case PSRAM_CACHE_F80M_S40M: - SET_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk - CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. - SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy - SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy - SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command - break; - case PSRAM_CACHE_F40M_S40M: - default: - CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk - CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div - SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy - SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy - SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command - break; + case PSRAM_CACHE_F80M_S80M: + CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk,80+40; + CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. FLASH DIV 2+SRAM DIV4 + WRITE_PERI_REG(SPI_CLOCK_REG(0),SPI_CLK_EQU_SYSCLK_M);//SET 1DIV CLOCK AND RESET OTHER PARAMS + SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy + SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy + SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command + break; + case PSRAM_CACHE_F80M_S40M: + SET_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk + CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div , ONLY IF SPI/SRAM@ DIFFERENT SPEED,JUST FOR SPI0. + SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy + SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy + SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command + break; + case PSRAM_CACHE_F40M_S40M: + default: + CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(31));//flash 1 div clk + CLEAR_PERI_REG_MASK(SPI_DATE_REG(0),BIT(30));//pre clk div + SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_USR_RD_SRAM_DUMMY_M);//enable cache read dummy + SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_DUMMY_CYCLELEN_V,3+extra_dummy,SPI_SRAM_DUMMY_CYCLELEN_S); //dummy, psram cache : 40m--+1dummy,80m--+2dummy + SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_RCMD_M);//enable user mode for cache read command + break; } SET_PERI_REG_MASK(SPI_CACHE_SCTRL_REG(0),SPI_CACHE_SRAM_USR_WCMD_M); // cache write command enable SET_PERI_REG_BITS(SPI_CACHE_SCTRL_REG(0),SPI_SRAM_ADDR_BITLEN_V,23,SPI_SRAM_ADDR_BITLEN_S);//write address for cache command. @@ -775,303 +767,3 @@ static void IRAM_ATTR psram_cache_init(psram_cache_mode_t psram_cache_mode) CLEAR_PERI_REG_MASK(SPI_PIN_REG(0), SPI_CS1_DIS_M); //ENABLE SPI0 CS1 TO PSRAM(CS0--FLASH; CS1--SRAM) } -typedef enum { - SPI_INT_SRC_TRANS_DONE = SPI_TRANS_DONE, - SPI_INT_SRC_WR_STA_DONE = SPI_SLV_WR_STA_DONE, - SPI_INT_SRC_RD_STA_DONE = SPI_SLV_RD_STA_DONE, - SPI_INT_SRC_WR_BUF_DONE = SPI_SLV_WR_BUF_DONE, - SPI_INT_SRC_RD_BUF_DONE = SPI_SLV_RD_BUF_DONE, - SPI_INT_SRC_ONE_BUF_RECV_DONE = SPI_IN_SUC_EOF_INT_ENA, - SPI_INT_SRC_ONE_BUF_SEND_DONE = SPI_OUT_EOF_INT_ENA, -} spi_int_src_t; - -/** - * @brief DMA queue description. - */ -typedef struct { - uint32_t block_size: 12; - uint32_t data_length: 12; - uint32_t unused: 5; - uint32_t sub_sof: 1; - uint32_t eof: 1; - uint32_t owner: 1; - uint32_t buf_ptr; - uint32_t next_link_ptr; -} dma_queue_t; - -/** - * @brief Initialize DMA and create a SPI DMA instance. - * - */ -//int spi_dma_init(spi_dma_attr_t *obj, void *isr) -int psram_dma_tx(int dma_channel, uint32_t addr, uint32_t* buf, size_t data_len) -{ - int spi_num = 1; - // Reset DMA - SET_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST); - CLEAR_PERI_REG_MASK(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_START); - CLEAR_PERI_REG_MASK(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_START); - CLEAR_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST); - - // Select DMA channel. - SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_channel, ((spi_num - 1) * 2)); - - SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MOSI);//////add - - // enable send intr - SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_SEND_DONE); - SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_RECV_DONE); - - // Clear all of interrupt source - //spi_int_clear(obj->spi_num); - CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_INT_SRC_TRANS_DONE - | SPI_INT_SRC_WR_STA_DONE - | SPI_INT_SRC_RD_STA_DONE - | SPI_INT_SRC_WR_BUF_DONE - | SPI_INT_SRC_RD_BUF_DONE); - - - dma_queue_t* dma_link = (dma_queue_t*) malloc( sizeof(dma_queue_t)); - dma_link->block_size = data_len; - dma_link->data_length = data_len; - dma_link->buf_ptr = (uint32_t)buf; - dma_link->eof = 1; - dma_link->next_link_ptr = (uint32_t)NULL; - dma_link->owner = 1;//0: cpu 1: dma - dma_link->sub_sof = 0; - dma_link->unused = 0; - - SET_PERI_REG_BITS(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_ADDR, ((uint32_t )dma_link), - SPI_OUTLINK_ADDR_S); - SET_PERI_REG_MASK(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_START); - - // 1. Waiting DMA controller fill TX FIFO - while ((READ_PERI_REG(SPI_DMA_RSTATUS_REG(spi_num))&0x80000000)); - psram_dma_cmd_write_config(addr, data_len, 0); - psram_cmd_start(spi_num, PSRAM_CMD_QPI); - free(dma_link); - return 0; -} - - - -int psram_dma_rx(int dma_channel, uint32_t addr, uint32_t* buf, size_t data_len) -{ - int spi_num = 1; - // Reset DMA - SET_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST); - CLEAR_PERI_REG_MASK(SPI_DMA_OUT_LINK_REG(spi_num), SPI_OUTLINK_START); - CLEAR_PERI_REG_MASK(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_START); - CLEAR_PERI_REG_MASK(SPI_DMA_CONF_REG(spi_num), SPI_OUT_RST | SPI_AHBM_RST | SPI_AHBM_FIFO_RST); - - // Select DMA channel. - SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, DPORT_SPI3_DMA_CHAN_SEL_V, dma_channel, ((spi_num - 1) * 2)); - - SET_PERI_REG_MASK(SPI_USER_REG(spi_num), SPI_USR_MISO);//////add - - // enable send intr - SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_SEND_DONE); - SET_PERI_REG_MASK(SPI_DMA_INT_ENA_REG(spi_num ), SPI_INT_SRC_ONE_BUF_RECV_DONE); - - // Clear all of interrupt source - //spi_int_clear(obj->spi_num); - CLEAR_PERI_REG_MASK(SPI_SLAVE_REG(spi_num), SPI_INT_SRC_TRANS_DONE - | SPI_INT_SRC_WR_STA_DONE - | SPI_INT_SRC_RD_STA_DONE - | SPI_INT_SRC_WR_BUF_DONE - | SPI_INT_SRC_RD_BUF_DONE); - - - dma_queue_t* rx_dma_link = (dma_queue_t*) malloc( sizeof(dma_queue_t)); - rx_dma_link->block_size = data_len; - rx_dma_link->data_length = data_len; - rx_dma_link->buf_ptr = (uint32_t)buf; - rx_dma_link->eof = 1; - rx_dma_link->next_link_ptr = (uint32_t)NULL; - rx_dma_link->owner = 1;//0: cpu 1: dma - rx_dma_link->sub_sof = 0; - rx_dma_link->unused = 0; - - SET_PERI_REG_BITS(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_ADDR, ((uint32_t )rx_dma_link), - SPI_INLINK_ADDR_S); - SET_PERI_REG_MASK(SPI_DMA_IN_LINK_REG(spi_num), SPI_INLINK_START); - - psram_dma_qio_read_config( spi_num, addr, data_len); - psram_cmd_start(spi_num, PSRAM_CMD_QPI); - - //add semaphore to wait trans done, instead of while loop. - free(rx_dma_link); - return 0; -} - -//--------------------------- -//-- below is test code -- -//--------------------------- -#if 1 -void psram_write_once(uint32_t loop_num,uint32_t write_addr,uint32_t mode,uint32_t repeat) -{ -// psram_enable(PSRAM_CACHE_F80M_S40M); -// psram_enable_qio_mode(PSRAM_SPI_1); - uint32_t data_w[8]; - int i; - for(i=0;i<8;i++) { - data_w[i]= ((i+1)<<24)|((i+1)<<16)|((i+1)<<8)|(i+1); - } - ets_printf("WRITE DATA IN QMODE\n"); - for(i = 0;i