uint32_tin_rst:1;/*Set this bit to reset in link operations.*/
uint32_tout_rst:1;/*Set this bit to reset out link operations.*/
uint32_tahbm_fifo_rst:1;/*Set this bit to reset dma ahb fifo.*/
uint32_tahbm_rst:1;/*Set this bit to reset dma ahb interface.*/
uint32_tin_loop_test:1;/*Set this bit to enable loop test for in links.*/
uint32_tout_loop_test:1;/*Set this bit to enable loop test for out links.*/
uint32_tout_auto_wrback:1;/*when in link's length is 0 go on to use the next in link automatically.*/
uint32_tout_no_restart_clr:1;/*don't use*/
uint32_tout_eof_mode:1;/*Set this bit to produce eof after DMA pops all data clear this bit to produce eof after DMA pushes all data*/
uint32_tuart0_ce:1;/*Set this bit to use UART to transmit or receive data.*/
uint32_tuart1_ce:1;/*Set this bit to use UART1 to transmit or receive data.*/
uint32_tuart2_ce:1;/*Set this bit to use UART2 to transmit or receive data.*/
uint32_toutdscr_burst_en:1;/*Set this bit to enable DMA in links to use burst mode.*/
uint32_tindscr_burst_en:1;/*Set this bit to enable DMA out links to use burst mode.*/
uint32_tout_data_burst_en:1;/*Set this bit to enable DMA burst MODE*/
uint32_tmem_trans_en:1;
uint32_tseper_en:1;/*Set this bit to use special char to separate the data frame.*/
uint32_thead_en:1;/*Set this bit to enable to use head packet before the data frame.*/
uint32_tcrc_rec_en:1;/*Set this bit to enable receiver''s ability of crc calculation when crc_en bit in head packet is 1 then there will be crc bytes after data_frame*/
uint32_tuart_idle_eof_en:1;/*Set this bit to enable to use idle time when the idle time after data frame is satisfied this means the end of a data frame.*/
uint32_tlen_eof_en:1;/*Set this bit to enable to use packet_len in packet head when the received data is equal to packet_len this means the end of a data frame.*/
uint32_tencode_crc_en:1;/*Set this bit to enable crc calculation for data frame when bit6 in the head packet is 1.*/
uint32_tclk_en:1;/*Set this bit to enable clock-gating for read or write registers.*/
uint32_tuart_rx_brk_eof_en:1;/*Set this bit to enable to use brk char as the end of a data frame.*/
uint32_trx_start:1;/*when a separator char has been send it will produce uhci_rx_start_int interrupt.*/
uint32_ttx_start:1;/*when DMA detects a separator char it will produce uhci_tx_start_int interrupt.*/
uint32_trx_hung:1;/*when DMA takes a lot of time to receive a data it will produce uhci_rx_hung_int interrupt.*/
uint32_ttx_hung:1;/*when DMA takes a lot of time to read a data from RAM it will produce uhci_tx_hung_int interrupt.*/
uint32_tin_done:1;/*when a in link descriptor has been completed it will produce uhci_in_done_int interrupt.*/
uint32_tin_suc_eof:1;/*when a data packet has been received it will produce uhci_in_suc_eof_int interrupt.*/
uint32_tin_err_eof:1;/*when there are some errors about eof in in link descriptor it will produce uhci_in_err_eof_int interrupt.*/
uint32_tout_done:1;/*when a out link descriptor is completed it will produce uhci_out_done_int interrupt.*/
uint32_tout_eof:1;/*when the current descriptor's eof bit is 1 it will produce uhci_out_eof_int interrupt.*/
uint32_tin_dscr_err:1;/*when there are some errors about the out link descriptor it will produce uhci_in_dscr_err_int interrupt.*/
uint32_tout_dscr_err:1;/*when there are some errors about the in link descriptor it will produce uhci_out_dscr_err_int interrupt.*/
uint32_tin_dscr_empty:1;/*when there are not enough in links for DMA it will produce uhci_in_dscr_err_int interrupt.*/
uint32_toutlink_eof_err:1;/*when there are some errors about eof in outlink descriptor it will produce uhci_outlink_eof_err_int interrupt.*/
uint32_tout_total_eof:1;/*When all data have been send it will produce uhci_out_total_eof_int interrupt.*/
uint32_tsend_s_q:1;/*When use single send registers to send a short packets it will produce this interrupt when dma has send the short packet.*/
uint32_tsend_a_q:1;/*When use always_send registers to send a series of short packets it will produce this interrupt when dma has send the short packet.*/
uint32_tcheck_sum_en:1;/*Set this bit to enable decoder to check check_sum in packet header.*/
uint32_tcheck_seq_en:1;/*Set this bit to enable decoder to check seq num in packet header.*/
uint32_tcrc_disable:1;/*Set this bit to disable crc calculation.*/
uint32_tsave_head:1;/*Set this bit to save packet header .*/
uint32_ttx_check_sum_re:1;/*Set this bit to enable hardware replace check_sum in packet header automatically.*/
uint32_ttx_ack_num_re:1;/*Set this bit to enable hardware replace ack num in packet header automatically.*/
uint32_tcheck_owner:1;/*Set this bit to check the owner bit in link descriptor.*/
uint32_twait_sw_start:1;/*Set this bit to enable software way to add packet header.*/
uint32_tsw_start:1;/*Set this bit to start inserting the packet header.*/
uint32_tdma_in_fifo_full_thrs:12;/*when data amount in link descriptor's fifo is more than this register value it will produce uhci_dma_in_fifo_full_wm_int interrupt.*/
uint32_ttest_mode:3;/*bit2 is ahb bus test enable ，bit1 is used to choose write(1) or read(0) mode. bit0 is used to choose test only once(1) or continue(0)*/
uint32_treserved3:1;
uint32_ttest_addr:2;/*The two bits represent ahb bus address bit[20:19]*/
uint32_ttxfifo_timeout:8;/*This register stores the timeout value.when DMA takes more time than this register value to receive a data it will produce uhci_tx_hung_int interrupt.*/
uint32_ttxfifo_timeout_shift:3;/*The tick count is cleared when its value >=(17'd8000>>reg_txfifo_timeout_shift)*/
uint32_ttxfifo_timeout_ena:1;/*The enable bit for tx fifo receive data timeout*/
uint32_trxfifo_timeout:8;/*This register stores the timeout value.when DMA takes more time than this register value to read a data from RAM it will produce uhci_rx_hung_int interrupt.*/
uint32_trxfifo_timeout_shift:3;/*The tick count is cleared when its value >=(17'd8000>>reg_rxfifo_timeout_shift)*/
uint32_trxfifo_timeout_ena:1;/*This is the enable bit for DMA send data timeout*/
