Crash_Override/OVMS3-idf
1
0
Fork 0
Code Issues Pull requests Projects Releases Wiki Activity
OVMS3-idf/components/esp32/ld/esp32.ld

75 lines
2.8 KiB
Text
Raw Normal View History

esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
/* ESP32 Linker Script Memory Layout
This file describes the memory layout (memory blocks) as virtual
memory addresses.
esp32.common.ld contains output sections to link compiler output
into these memory blocks.
***
This linker script is passed through the C preprocessor to include
configuration options.
Please use preprocessor features sparingly! Restrict
to simple macros with numeric values, and/or #if/#endif blocks.
*/
#include "sdkconfig.h"
Provide a default for CONFIG_BT_RESERVE_DRAM ...when BT is not built Merges https://github.com/espressif/esp-idf/pull/910
2017-08-15 13:36:06 +00:00
/* If BT is not built at all */
#ifndef CONFIG_BT_RESERVE_DRAM
#define CONFIG_BT_RESERVE_DRAM 0
#endif
ld: seperate/rename eagle.xxx.ld to esp32.xxx.ld
2016-08-19 10:28:32 +00:00
MEMORY
{
/* All these values assume the flash cache is on, and have the blocks this uses subtracted from the length
of the various regions. The 'data access port' dram/drom regions map to the same iram/irom regions but
are connected to the data port of the CPU and eg allow bytewise access. */
esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
/* IRAM for PRO cpu. Not sure if happy with this, this is MMU area... */
iram0_0_seg (RX) : org = 0x40080000, len = 0x20000
linker script: Add some comments about significance of 0x18 byte offset
2017-07-19 07:38:05 +00:00
/* Even though the segment name is iram, it is actually mapped to flash
*/
linker scripts: Limit DROM/IROM section lengths correctly
2017-07-19 06:33:48 +00:00
iram0_2_seg (RX) : org = 0x400D0018, len = 0x330000-0x18
esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
linker script: Add some comments about significance of 0x18 byte offset
2017-07-19 07:38:05 +00:00
/*
(0x18 offset above is a convenience for the app binary image generation. Flash cache has 64KB pages. The .bin file
which is flashed to the chip has a 0x18 byte file header. Setting this offset makes it simple to meet the flash
cache MMU's constraint that (paddr % 64KB == vaddr % 64KB).)
*/
esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
/* Shared data RAM, excluding memory reserved for ROM bss/data/stack.
Enabling Bluetooth & Trace Memory features in menuconfig will decrease
the amount of RAM available.
esp32: Change 192KB runtime static limit workaround to a 176KB link time workaround Turns out some app memory around 0x3ffdc000 is also used by APP CPU. This is a workaround until code to remove the 176KB limit is committed.
2017-12-22 07:36:12 +00:00
Note: Length of this section *should* be 0x50000, and this extra DRAM is available
in heap at runtime. However due to static ROM memory usage at this 176KB mark, the
additional static memory temporarily cannot be used.
esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
*/
dram0_0_seg (RW) : org = 0x3FFB0000 + CONFIG_BT_RESERVE_DRAM,
esp32: Change 192KB runtime static limit workaround to a 176KB link time workaround Turns out some app memory around 0x3ffdc000 is also used by APP CPU. This is a workaround until code to remove the 176KB limit is committed.
2017-12-22 07:36:12 +00:00
len = 0x2c200 - CONFIG_BT_RESERVE_DRAM
esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
/* Flash mapped constant data */
linker scripts: Limit DROM/IROM section lengths correctly
2017-07-19 06:33:48 +00:00
drom0_0_seg (R) : org = 0x3F400018, len = 0x400000-0x18
esp32: Bootloader wake deep sleep stub App can contain a stub program resident in RTC fast memory. Bootloader will load the stub on initial boot. If the device wakes from deep sleep, the stub is run immediately (before any other data is loaded, etc.) To implement a custom wake stub, implement a function in your program: ``` void RTC_IRAM_ATTR esp_wake_deep_sleep(void) { esp_default_wake_deep_sleep(); // other wake logic } ``` ... and it will replace the default implementation.
2016-09-12 07:23:15 +00:00
linker script: Add some comments about significance of 0x18 byte offset
2017-07-19 07:38:05 +00:00
/* (See iram0_2_seg for meaning of 0x18 offset in the above.) */
esp32: Bootloader wake deep sleep stub App can contain a stub program resident in RTC fast memory. Bootloader will load the stub on initial boot. If the device wakes from deep sleep, the stub is run immediately (before any other data is loaded, etc.) To implement a custom wake stub, implement a function in your program: ``` void RTC_IRAM_ATTR esp_wake_deep_sleep(void) { esp_default_wake_deep_sleep(); // other wake logic } ``` ... and it will replace the default implementation.
2016-09-12 07:23:15 +00:00
/* RTC fast memory (executable). Persists over deep sleep.
*/
rtc_iram_seg(RWX) : org = 0x400C0000, len = 0x2000
esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
esp32: Allow RTC slow memory to be reserved for ULP coprocessor
2016-09-21 01:24:02 +00:00
/* RTC slow memory (data accessible). Persists over deep sleep.
Start of RTC slow memory is reserved for ULP co-processor code + data, if enabled.
*/
rtc_slow_seg(RW) : org = 0x50000000 + CONFIG_ULP_COPROC_RESERVE_MEM,
Add Comments We reserve 4KB Slow RTC memory to save RF calibation result and BT NVS data. If not all these Slow RTC momory Blocks are used, we will open the other parts.
2016-09-29 08:29:13 +00:00
len = 0x1000 - CONFIG_ULP_COPROC_RESERVE_MEM
ld: seperate/rename eagle.xxx.ld to esp32.xxx.ld
2016-08-19 10:28:32 +00:00
}
esp32: Pass memory layout linker script through C preprocessor C preprocessor is a bit icky, but with ULP we will have 3 possible variables influencing the memory layout and 9 linker scripts is too many!
2016-09-21 01:04:16 +00:00
/* Heap ends at top of dram0_0_seg */
_heap_end = 0x40000000 - CONFIG_TRACEMEM_RESERVE_DRAM;
Reference in a new issue Copy permalink