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OVMS3-idf/components/spi_flash/CMakeLists.txt

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CMake
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components: use new component registration api
2019-04-28 07:38:23 +00:00
set(priv_requires bootloader_support soc)
ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation Otherwise IRAM usage is too high in this example.
2019-11-28 01:20:00 +00:00
build system: Initial cmake support, work in progress
2018-01-12 02:49:13 +00:00
if(BOOTLOADER_BUILD)
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-22 02:51:49 +00:00
if (CONFIG_IDF_TARGET_ESP32)
# ESP32 Bootloader needs SPIUnlock from this file, but doesn't
# need other parts of this component
fix dummy issue in spi mem and make some spiflash api called from idf
2019-11-05 05:10:03 +00:00
set(srcs "esp32/spi_flash_rom_patch.c")
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-22 02:51:49 +00:00
else()
# but on other platforms no source files are needed for bootloader
set(srcs)
endif()
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 05:11:36 +00:00
set(cache_srcs "")
build system: Initial cmake support, work in progress
2018-01-12 02:49:13 +00:00
else()
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 05:11:36 +00:00
set(cache_srcs
cmake: some formatting fixes Do not include bootloader in flash target when secure boot is enabled. Emit signing warning on all cases where signed apps are enabled (secure boot and signed images) Follow convention of capital letters for SECURE_BOOT_SIGNING_KEY variable, since it is relevant to other components, not just bootloader. Pass signing key and verification key via config, not requiring bootloader to know parent app dir. Misc. variables name corrections
2019-06-21 06:29:32 +00:00
"cache_utils.c"
"flash_mmap.c"
"flash_ops.c"
spi_flash: Use per-chip flash_ops files for legacy API Looks like when ESP32-S2 Beta support was merged, the separate files were dropped by accident.
2020-04-16 11:31:13 +00:00
"${IDF_TARGET}/flash_ops_${IDF_TARGET}.c"
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 05:11:36 +00:00
)
set(srcs
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-22 02:51:49 +00:00
"partition.c")
if (CONFIG_IDF_TARGET_ESP32)
list(APPEND srcs
fix dummy issue in spi mem and make some spiflash api called from idf
2019-11-05 05:10:03 +00:00
"esp32/spi_flash_rom_patch.c")
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-22 02:51:49 +00:00
endif()
esp_flash: fix the quad issue for some GD flash chips The GD flash with product ID 40H, is already used in Wrover-nosufix modules.
2019-09-09 16:56:46 +00:00
# New implementation after IDF v4.0
esp_flash: fix coredump for legacy spi flash API When legacy mode is used, the coredump still fails during linking because "esp_flash_init_default_chip", "esp_flash_app_init" and "esp_flash_default_chip " are not compiled and linked. Instead of using ``if`` macros in callers, these functions are protected by ``if`` macros in the header, and also not compiled in the sources. "esp_flash_default_chip" variable is compiled with safe default value.
2019-09-10 06:34:06 +00:00
list(APPEND srcs
cmake: some formatting fixes Do not include bootloader in flash target when secure boot is enabled. Emit signing warning on all cases where signed apps are enabled (secure boot and signed images) Follow convention of capital letters for SECURE_BOOT_SIGNING_KEY variable, since it is relevant to other components, not just bootloader. Pass signing key and verification key via config, not requiring bootloader to know parent app dir. Misc. variables name corrections
2019-06-21 06:29:32 +00:00
"spi_flash_chip_drivers.c"
"spi_flash_chip_generic.c"
"spi_flash_chip_issi.c"
esp_flash: support MXIC flash chips The default chip driver (chip_generic) use command 01H + 2 bytes to clear the QE bit. However this will accidently change the configuration register value of the MXIC chip. MXIC chip driver is added to fix that.
2020-03-19 14:49:25 +00:00
"spi_flash_chip_mxic.c"
ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation Otherwise IRAM usage is too high in this example.
2019-11-28 01:20:00 +00:00
"spi_flash_chip_gd.c"
"memspi_host_driver.c")
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-22 02:51:49 +00:00
ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation Otherwise IRAM usage is too high in this example.
2019-11-28 01:20:00 +00:00
list(APPEND cache_srcs
Merge branch 'master' into feature/esp32s2beta_merge
2019-10-22 02:51:49 +00:00
"esp_flash_api.c"
"esp_flash_spi_init.c"
"spi_flash_os_func_app.c"
"spi_flash_os_func_noos.c")
ble_mesh_wifi_coexist example: Disable Wi-Fi RX IRAM optimisation Otherwise IRAM usage is too high in this example.
2019-11-28 01:20:00 +00:00
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 05:11:36 +00:00
list(APPEND srcs ${cache_srcs})
components: use new component registration api
2019-04-28 07:38:23 +00:00
set(priv_requires bootloader_support app_update soc)
build system: Initial cmake support, work in progress
2018-01-12 02:49:13 +00:00
endif()
components: use new component registration api
2019-04-28 07:38:23 +00:00
idf_component_register(SRCS "${srcs}"
PRIV_REQUIRES "${priv_requires}"
INCLUDE_DIRS include
PRIV_INCLUDE_DIRS private_include
LDFRAGMENTS linker.lf)
tools: implement linker script generation
2018-04-18 02:57:45 +00:00
esp_flash: fix set qe bit and write command issues There used to be dummy phase before out phase in common command transactions. This corrupts the data. The code before never actually operate (clear) the QE bit, once it finds the QE bit is set. It's hard to check whether the QE set/disable functions work well. This commit: 1. Cancel the dummy phase 2. Set and clear the QE bit according to chip settings, allowing tests for QE bits. However for some chips (Winbond for example), it's not forced to clear the QE bit if not able to. 3. Also refactor to allow chip_generic and other chips to share the same code to read and write qe bit; let common command and read command share configure_host_io_mode. 4. Rename read mode to io mode since maybe we will write data with quad mode one day.
2019-09-05 05:11:36 +00:00
# Avoid cache miss by unexpected inlineing when built by -Os
set_source_files_properties(${cache_srcs} PROPERTIES COMPILE_FLAGS
"-fno-inline-functions -fno-inline-small-functions -fno-inline-functions-called-once")
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