DJ2LS
36b7ac91f8
smaller PEP8 cleanup
2021-03-12 14:14:36 +01:00
DJ2LS
d361750293
fall back to threading --> asyncio causes probs
2021-03-10 11:26:15 +01:00
DJ2LS
a826248090
test with wait for data channel
2021-03-10 10:30:49 +01:00
DJ2LS
465926cf4d
improvement of audio to stream
2021-03-09 21:35:52 +01:00
DJ2LS
2c120065f5
first async / non block transmission
...
really ugly at this point. we need a lot of code cleanup.
2021-03-09 20:56:17 +01:00
DJ2LS
71ceaeb6f7
smaller improvements
2021-03-09 16:45:27 +01:00
DJ2LS
42c10c5780
updated other signalling frams with callsign crc8
2021-03-09 14:01:54 +01:00
DJ2LS
69809a9145
close freedv session after sucessfully transmit
2021-03-09 11:13:23 +01:00
DJ2LS
cbdbd30c39
selective repeating
...
first try
2021-03-09 11:05:59 +01:00
DJ2LS
8115cfae97
CQ now with callsign detection
2021-03-09 10:00:20 +01:00
DJ2LS
c62ac5019e
code cleanup
2021-03-07 16:24:09 +01:00
DJ2LS
821be594f2
first attempt with ASYNCIO instead of THREADING
2021-03-04 14:28:01 +01:00
DJ2LS
d4f63844d6
changed PER to BER
2021-02-28 19:34:36 +01:00
DJ2LS
7cdc1a06b3
addded PER messurement
2021-02-28 19:13:47 +01:00
DJ2LS
37af525cc5
first attempt with ASYNCIO instead of THREADING
2021-02-28 16:46:18 +01:00
DJ2LS
9a263757b1
first working data channel
2021-02-28 15:24:14 +01:00
DJ2LS
c9c869e802
n_tx_preamble_modem_samples function
...
n_tx_preamble_modem_samples = self.c_lib.freedv_get_n_tx_preamble_modem_samples(freedv)
2021-02-25 08:40:48 +01:00
DJ2LS
697106b567
beacon placeholder and connect optimization
2021-02-24 17:29:08 +01:00
DJ2LS
812e00a403
first connect, cq and ping handler
2021-02-24 16:47:52 +01:00
DJ2LS
55d56b8e83
renamed arq module to data_handler
2021-02-24 14:22:28 +01:00
DJ2LS
adfb9d3625
switching to signalling mode as default
...
necessary for mode gear shifting, ping, cq ...
2021-02-24 14:16:29 +01:00
DJ2LS
327f07ed4d
modem optimization
2021-02-23 13:21:41 +01:00
DJ2LS
2c7ca05bee
maybe fix of "stuck in sync"
...
fixed a lot of buffer allocation problems
2021-02-23 11:31:19 +01:00
DJ2LS
681fe6d8ac
first hamlib integration
...
still only for development purposes.
2021-02-19 11:08:44 +01:00
DJ2LS
7f1a502a81
PTT_STATE
2021-02-19 09:58:12 +01:00
DJ2LS
4e3d2cc158
cleanup & optimized data/cmd socket
2021-02-16 14:36:01 +01:00
DJ2LS
1969349b50
code cleanup
2021-02-16 14:23:57 +01:00
DJ2LS
129e0c0645
improved single frame transmission
...
solved timing issues
2021-02-15 16:33:43 +01:00
DJ2LS
63628f56d3
improved logging
...
now with colors and timestamps...
2021-02-10 19:43:59 +01:00
DJ2LS
be7bc9744f
improved states
2021-02-10 15:05:03 +01:00
DJ2LS
91114d0db2
improved state and timing
2021-02-09 14:27:36 +01:00
DJ2LS
0a8ea24112
improved RPT
...
Now working, but still timing issues and stuck in sync
2021-02-09 12:35:24 +01:00
DJ2LS
6adf7db483
bleeding edge ARQ RPT
...
no working, but with tooo much debugging output
furthermore the frame ACK is not working correctly on the TX side
2021-02-08 21:25:22 +01:00
DJ2LS
eb7f98e2e1
RPT FRAME
...
first bleeding edge attempt
not completed yet
2021-02-08 19:00:12 +01:00
DJ2LS
06cb35276e
removed burst crc
...
the burst CRC is not needed, because we only receive frames with correct CRC. So its more important to create a correct ARQ algorithm. The 2byte CRC has been removed bei 2 x CRC8 for DX call sign and own callsign
2021-02-08 16:33:11 +01:00
DJ2LS
9cf0008da6
updated logging and stuck in sync detection
2021-02-06 15:11:42 +01:00
DJ2LS
6f770d1d69
improved data frame processing
2021-02-05 14:40:32 +01:00
DJ2LS
b9f2f1874f
improved logging and statistics
2021-02-04 17:51:01 +01:00
DJ2LS
51398382f7
code cleanup and bug fixes
2021-02-04 15:25:15 +01:00
DJ2LS
b52081866f
improved RX
2021-02-01 21:46:33 +01:00
DJ2LS
95674ebca7
Update modem.py
2021-01-30 17:48:25 +01:00
DJ2LS
e71902b7ae
removed frame rate conversion
2021-01-30 17:40:03 +01:00
DJ2LS
63e96ea156
removed frame rate conversion
2021-01-30 17:25:24 +01:00
DJ2LS
2bfa53354d
added timing tests
2021-01-21 21:00:21 +01:00
DJ2LS
0dbe03669d
added ARQ ACK TX function
2021-01-21 08:33:45 +01:00
DJ2LS
66cf834bed
transmit nonblocking
2021-01-20 23:42:45 +01:00
DJ2LS
678d32cdcc
complete ARQ redesign
2021-01-20 22:51:14 +01:00
DJ2LS
2be28cafb1
own function to send arqburst from TX_BUFFER
...
done without practical tests. just thinking..... uff
2021-01-16 20:43:10 +01:00
DJ2LS
fa49e90c9b
added preamble transmission
2021-01-16 14:29:49 +01:00
DJ2LS
a316126725
added preamble transmission
2021-01-16 14:28:47 +01:00